From c20ee0ed070953600b54b16c8b48725348abead5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 29 Aug 2017 14:15:50 -0600 Subject: dtoc: Add support for 32 or 64-bit addresses When using 32-bit addresses dtoc works correctly. For 64-bit addresses it does not since it ignores the #address-cells and #size-cells properties. Update the tool to use fdt64_t as the element type for reg properties when either the address or size is larger than one cell. Use the correct value so that C code can obtain the information from the device tree easily. Alos create a new type, fdt_val_t, which is defined to either fdt32_t or fdt64_t depending on the word size of the machine. This type corresponds to fdt_addr_t and fdt_size_t. Unfortunately we cannot just use those types since they are defined to phys_addr_t and phys_size_t which use 'unsigned long' in the 32-bit case, rather than 'unsigned int'. Add tests for the four combinations of address and size values (32/32, 64/64, 32/64, 64/32). Also update existing uses for rk3399 and rk3368 which now need to use the new fdt_val_t type. Signed-off-by: Simon Glass Suggested-by: Heiko Stuebner Reported-by: Kever Yang Reviewed-by: Philipp Tomsich Tested-by: Kever Yang --- drivers/clk/rockchip/clk_rk3368.c | 2 +- drivers/clk/rockchip/clk_rk3399.c | 4 ++-- drivers/core/regmap.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 2be1f572d72..0160d50c038 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -471,7 +471,7 @@ static int rk3368_clk_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3368_clk_plat *plat = dev_get_platdata(dev); - priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]); + priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) rkclk_init(priv->cru); diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 3edafea1400..72328067241 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -963,7 +963,7 @@ static int rk3399_clk_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_clk_plat *plat = dev_get_platdata(dev); - priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]); + priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif rkclk_init(priv->cru); #endif @@ -1145,7 +1145,7 @@ static int rk3399_pmuclk_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); - priv->pmucru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]); + priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif #ifndef CONFIG_SPL_BUILD diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index d4e16a27ef3..0f1d30820c6 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -40,7 +40,7 @@ static struct regmap *regmap_alloc_count(int count) } #if CONFIG_IS_ENABLED(OF_PLATDATA) -int regmap_init_mem_platdata(struct udevice *dev, u32 *reg, int count, +int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count, struct regmap **mapp) { struct regmap_range *range; -- cgit v1.3.1 From 0d15463c0537806f70ea2359e32e4deb8c4766c2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 29 Aug 2017 14:15:56 -0600 Subject: dtoc: Rename the phandle struct Rather than naming the phandle struct according to the number of cells it uses (e.g. struct phandle_2_cell) name it according to the number of arguments it has (e.g. struct phandle_1_arg). This is a more intuitive naming. Signed-off-by: Simon Glass Tested-by: Kever Yang --- doc/driver-model/of-plat.txt | 2 +- drivers/clk/clk-uclass.c | 2 +- include/clk.h | 4 ++-- include/dt-structs.h | 7 ++++++- tools/dtoc/dtb_platdata.py | 3 ++- tools/dtoc/test_dtoc.py | 2 +- 6 files changed, 13 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/doc/driver-model/of-plat.txt b/doc/driver-model/of-plat.txt index 3ed8c759d69..732bc34f067 100644 --- a/doc/driver-model/of-plat.txt +++ b/doc/driver-model/of-plat.txt @@ -111,7 +111,7 @@ struct dtd_rockchip_rk3288_dw_mshc { bool cap_sd_highspeed; fdt32_t card_detect_delay; fdt32_t clock_freq_min_max[2]; - struct phandle_2_cell clocks[4]; + struct phandle_1_arg clocks[4]; bool disable_wp; fdt32_t fifo_depth; fdt32_t interrupts[3]; diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index e68d9279b96..8b40326efa2 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -23,7 +23,7 @@ static inline struct clk_ops *clk_dev_ops(struct udevice *dev) #if CONFIG_IS_ENABLED(OF_CONTROL) # if CONFIG_IS_ENABLED(OF_PLATDATA) int clk_get_by_index_platdata(struct udevice *dev, int index, - struct phandle_2_cell *cells, struct clk *clk) + struct phandle_1_arg *cells, struct clk *clk) { int ret; diff --git a/include/clk.h b/include/clk.h index c5988f78a8f..e7ce3e85768 100644 --- a/include/clk.h +++ b/include/clk.h @@ -61,9 +61,9 @@ struct clk { }; #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK) -struct phandle_2_cell; +struct phandle_1_arg; int clk_get_by_index_platdata(struct udevice *dev, int index, - struct phandle_2_cell *cells, struct clk *clk); + struct phandle_1_arg *cells, struct clk *clk); /** * clock_get_by_index - Get/request a clock by integer index. diff --git a/include/dt-structs.h b/include/dt-structs.h index 0732c442ff8..2ed997115ae 100644 --- a/include/dt-structs.h +++ b/include/dt-structs.h @@ -9,7 +9,12 @@ /* These structures may only be used in SPL */ #if CONFIG_IS_ENABLED(OF_PLATDATA) -struct phandle_2_cell { +struct phandle_0_arg { + const void *node; + int id[0]; +}; + +struct phandle_1_arg { const void *node; int id; }; diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py index 001bc4ea668..0234f71b767 100644 --- a/tools/dtoc/dtb_platdata.py +++ b/tools/dtoc/dtb_platdata.py @@ -419,7 +419,8 @@ class DtbPlatdata(object): info = self.get_phandle_argc(prop, structs[name]) if info: # For phandles, include a reference to the target - self.out('\t%s%s[%d]' % (tab_to(2, 'struct phandle_2_cell'), + struct_name = 'struct phandle_%d_arg' % info.max_args + self.out('\t%s%s[%d]' % (tab_to(2, struct_name), conv_name_to_c(prop.name), len(prop.value) / 2)) else: diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py index 62460acb7c5..23c4439ed91 100644 --- a/tools/dtoc/test_dtoc.py +++ b/tools/dtoc/test_dtoc.py @@ -228,7 +228,7 @@ U_BOOT_DEVICE(pmic_at_9) = { self.assertEqual('''#include #include struct dtd_source { -\tstruct phandle_2_cell clocks[1]; +\tstruct phandle_1_arg clocks[1]; }; struct dtd_target { \tfdt32_t\t\tintval; -- cgit v1.3.1 From bc79617fdfeb4afabb94774885447dd64d7bea6c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 29 Aug 2017 14:15:58 -0600 Subject: dtoc: Put phandle args in an array We want to support more than one phandle argument. It makes sense to use an array for this rather than discrete struct members. Adjust the code to support this. Rename the member to 'arg' instead of 'id'. Signed-off-by: Simon Glass Tested-by: Kever Yang --- drivers/clk/clk-uclass.c | 2 +- include/dt-structs.h | 4 ++-- tools/dtoc/dtb_platdata.py | 2 +- tools/dtoc/test_dtoc.py | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 8b40326efa2..83ba13374c7 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -32,7 +32,7 @@ int clk_get_by_index_platdata(struct udevice *dev, int index, ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev); if (ret) return ret; - clk->id = cells[0].id; + clk->id = cells[0].arg[0]; return 0; } diff --git a/include/dt-structs.h b/include/dt-structs.h index 2ed997115ae..9ab4e2524d1 100644 --- a/include/dt-structs.h +++ b/include/dt-structs.h @@ -11,12 +11,12 @@ #if CONFIG_IS_ENABLED(OF_PLATDATA) struct phandle_0_arg { const void *node; - int id[0]; + int arg[0]; }; struct phandle_1_arg { const void *node; - int id; + int arg[1]; }; #include #endif diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py index c0a3ae692bc..1920a59f821 100644 --- a/tools/dtoc/dtb_platdata.py +++ b/tools/dtoc/dtb_platdata.py @@ -467,7 +467,7 @@ class DtbPlatdata(object): id_num = fdt_util.fdt32_to_cpu(id_cell) target_node = self._fdt.phandle_to_node[phandle] name = conv_name_to_c(target_node.name) - vals.append('{&%s%s, %d}' % (VAL_PREFIX, name, id_num)) + vals.append('{&%s%s, {%d}}' % (VAL_PREFIX, name, id_num)) for val in vals: self.buf('\n\t\t%s,' % val) else: diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py index aa617a649c8..fbae927cf8f 100644 --- a/tools/dtoc/test_dtoc.py +++ b/tools/dtoc/test_dtoc.py @@ -253,7 +253,7 @@ U_BOOT_DEVICE(phandle_target) = { static struct dtd_source dtv_phandle_source = { \t.clocks\t\t\t= { -\t\t{&dtv_phandle_target, 1},}, +\t\t{&dtv_phandle_target, {1}},}, }; U_BOOT_DEVICE(phandle_source) = { \t.name\t\t= "source", -- cgit v1.3.1