From 83f2843f20f171122a9d70ec04049e74042ec7e1 Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Tue, 3 Feb 2026 15:56:53 +0800 Subject: socfpga: agilex: fix NAND clock handling In v2025.10, the Agilex clock driver was updated to support clk_enable() and clk_disable() using clock-ID based bitmasks. However, only AGILEX_NAND_CLK was implemented, while the NAND DT node still referenced both nand and nand_x clocks. Since AGILEX_NAND_X_CLK is not defined in the clock driver or the clock-ID specification, clk_enable() failed during NAND probe. As a result, the Denali NAND controller never completed initialization. Fix this by mapping the NAND X clock to the existing l4_mp clock bitmask, aligning the DT expectations with the clock driver and restoring proper NAND controller initialization. Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- drivers/clk/altera/clk-agilex.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index fdbf834bb2f..f1e2fded7d4 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -657,6 +657,7 @@ static int bitmask_from_clk_id(struct clk *clk) plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK; break; case AGILEX_L4_MP_CLK: + case AGILEX_NAND_X_CLK: plat->pllgrp = CLKMGR_MAINPLL_EN; plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK; break; -- cgit v1.2.3 From 847e67582b1f0eee85e8f1aa7f5a7a3a41286288 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Tue, 16 Dec 2025 00:46:22 -0800 Subject: ddr: altera: arria10: Add DRAM size checking Add DRAM size checking compare between size from device tree and actual hardware. Trigger hang if DRAM size from device tree is greater than actual hardware. Display warning message if DRAM size mismatch between device tree and actual hardware. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee Best regards, --- drivers/ddr/altera/sdram_arria10.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers') diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index d3305a6c82d..c281f711fdf 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -667,6 +668,22 @@ static int of_sdram_firewall_setup(const void *blob) return 0; } +static void sdram_size_check(void) +{ + phys_size_t ram_check = 0; + + debug("DDR: Running SDRAM size sanity check\n"); + + ram_check = get_ram_size((long *)gd->bd->bi_dram[0].start, + gd->bd->bi_dram[0].size); + if (ram_check != gd->bd->bi_dram[0].size) { + puts("DDR: SDRAM size check failed!\n"); + hang(); + } + + debug("DDR: SDRAM size check passed!\n"); +} + int ddr_calibration_sequence(void) { schedule(); @@ -702,11 +719,26 @@ int ddr_calibration_sequence(void) /* setup the dram info within bd */ dram_init_banksize(); + if (gd->ram_size != gd->bd->bi_dram[0].size) { + printf("DDR: Warning: DRAM size from device tree (%ld MiB)\n", + gd->bd->bi_dram[0].size >> 20); + printf(" mismatch with hardware (%ld MiB).\n", + gd->ram_size >> 20); + } + + if (gd->bd->bi_dram[0].size > gd->ram_size) { + printf("DDR: Error: DRAM size from device tree is greater\n"); + printf(" than hardware size.\n"); + hang(); + } + if (of_sdram_firewall_setup(gd->fdt_blob)) puts("FW: Error Configuring Firewall\n"); if (sdram_is_ecc_enabled()) sdram_init_ecc_bits(gd->ram_size); + sdram_size_check(); + return 0; } -- cgit v1.2.3 From 22aac1c5b466da72095ccf3464660eae47579e2e Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Mon, 2 Feb 2026 23:59:24 -0800 Subject: clk: altera: agilex: Exclude AGILEX_L4_SYS_FREE_CLK from enable/disable operations AGILEX_L4_SYS_FREE_CLK is a free-running clock with no gate control in hardware, therefore attempting to enable or disable it is not applicable. Update the clock driver to explicitly exclude this clock ID from enable/disable operations by returning -EOPNOTSUPP in bitmask_from_clk_id() and treating this as a no-op in the socfpga_clk_enable() and socfpga_clk_disable() functions. This prevents unnecessary register access for clocks that cannot be gated and ensures clean handling when the clock is present in the device tree. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- drivers/clk/altera/clk-agilex.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index f1e2fded7d4..e5be43b6317 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -729,6 +729,8 @@ static int bitmask_from_clk_id(struct clk *clk) plat->pllgrp = CLKMGR_PERPLL_EN; plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK; break; + case AGILEX_L4_SYS_FREE_CLK: + return -EOPNOTSUPP; default: return -ENXIO; } @@ -743,6 +745,9 @@ static int socfpga_clk_enable(struct clk *clk) int ret; ret = bitmask_from_clk_id(clk); + if (ret == -EOPNOTSUPP) + return 0; + if (ret) return ret; @@ -758,6 +763,9 @@ static int socfpga_clk_disable(struct clk *clk) int ret; ret = bitmask_from_clk_id(clk); + if (ret == -EOPNOTSUPP) + return 0; + if (ret) return ret; -- cgit v1.2.3 From cb23bbf4d7403dbfe1e4b4ef80bca6ae585a181e Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Mon, 9 Feb 2026 10:07:09 +0800 Subject: drivers: ddr: altera: iossm_mailbox: widen MEM_TOTAL_CAPACITY mask The previous mask for MEM_TOTAL_CAPACITY_INTF was limited to 8 bits, which could truncate DDR size values on larger-memory systems. Update INTF_CAPACITY_GBITS_MASK to 32 bits to correctly represent the full capacity field according to the hardware specification. Signed-off-by: Naresh Kumar Ravulapalli Signed-off-by: Chen Huei Lok Reviewed-by: Tien Fong Chee Best regards, --- drivers/ddr/altera/iossm_mailbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c index 2a2f86a650e..3156cb9d4b6 100644 --- a/drivers/ddr/altera/iossm_mailbox.c +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -86,7 +86,7 @@ #define INTF_DDR_TYPE_MASK GENMASK(2, 0) /* offset info of MEM_TOTAL_CAPACITY_INTF */ -#define INTF_CAPACITY_GBITS_MASK GENMASK(7, 0) +#define INTF_CAPACITY_GBITS_MASK GENMASK(31, 0) /* offset info of ECC_ENABLE_INTF */ #define INTF_ECC_ENABLE_TYPE_MASK GENMASK(1, 0) -- cgit v1.2.3 From 62f7a94602094617ac384839ed695c2906893a88 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Fri, 13 Feb 2026 20:27:23 +0800 Subject: Replace TARGET namespace and cleanup properly TARGET namespace is for machines / boards / what-have-you that building U-Boot for. Simply replace from TARGET to ARCH make things more clear and proper for ALL SoCFPGA. Signed-off-by: Brian Sune Reviewed-by: Tien Fong Chee # Conflicts: # drivers/ddr/altera/Makefile --- drivers/clk/altera/Makefile | 12 ++++++------ drivers/ddr/altera/Kconfig | 6 +++--- drivers/ddr/altera/Makefile | 14 +++++++------- drivers/ddr/altera/sdram_soc64.c | 14 +++++++------- drivers/ddr/altera/sdram_soc64.h | 4 ++-- drivers/fpga/Kconfig | 2 +- drivers/fpga/Makefile | 4 ++-- drivers/fpga/altera.c | 8 ++++---- drivers/mmc/socfpga_dw_mmc.c | 8 ++++---- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/net/Kconfig | 2 +- drivers/power/domain/Kconfig | 2 +- drivers/reset/reset-socfpga.c | 2 +- drivers/sysreset/Kconfig | 4 ++-- 14 files changed, 42 insertions(+), 42 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index 858f828e537..693446b3d89 100644 --- a/drivers/clk/altera/Makefile +++ b/drivers/clk/altera/Makefile @@ -3,9 +3,9 @@ # Copyright (C) 2018-2021 Marek Vasut # -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += clk-agilex.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o -obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o -obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += clk-agilex5.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX) += clk-agilex.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX7M) += clk-agilex.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-arria10.o +obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-n5x.o +obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-mem-n5x.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += clk-agilex5.o diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 4660d20deff..615e0421abf 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,8 +1,8 @@ config SPL_ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver in SPL" depends on SPL - depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_SOC64 - select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64 - select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64 + depends on ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 || ARCH_SOCFPGA_SOC64 + select RAM if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_SOC64 + select SPL_RAM if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_SOC64 help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 7ed43965be5..8259ab04a7e 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -7,11 +7,11 @@ # Copyright (C) 2014-2025 Altera Corporation ifdef CONFIG_$(PHASE_)ALTERA_SDRAM -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o -obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o -obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o +obj-$(CONFIG_ARCH_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += sdram_arria10.o +obj-$(CONFIG_ARCH_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o +obj-$(CONFIG_ARCH_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o endif diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 2d0093c591c..8ee7049b164 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -32,7 +32,7 @@ #define SINGLE_RANK_CLAMSHELL 0xc3c3 #define DUAL_RANK_CLAMSHELL 0xa5a5 -#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg) { return readl(plat->iomhc + reg); @@ -106,7 +106,7 @@ int emif_reset(struct altera_sdram_plat *plat) } #endif -#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) +#if !(IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) int poll_hmc_clock_status(void) { return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + @@ -347,7 +347,7 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) } } -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) static void sdram_set_firewall_f2sdram(struct bd_info *bd) { u32 i, lower, upper; @@ -397,22 +397,22 @@ void sdram_set_firewall(struct bd_info *bd) { sdram_set_firewall_non_f2sdram(bd); -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) sdram_set_firewall_f2sdram(bd); #endif } static int altera_sdram_of_to_plat(struct udevice *dev) { -#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if !IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) struct altera_sdram_plat *plat = dev_get_plat(dev); fdt_addr_t addr; #endif /* These regs info are part of DDR handoff in bitstream */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) return 0; -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 6fe0653922c..e8090f91002 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -15,13 +15,13 @@ struct altera_sdram_priv { struct reset_ctl_bulk resets; }; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) struct altera_sdram_plat { fdt_addr_t mpfe_base_addr; bool dualport; bool dualemif; }; -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) enum memory_type { DDR_MEMORY = 0, HBM_MEMORY diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index e2593057fac..1658c73bca4 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -46,7 +46,7 @@ config FPGA_CYCLON2 config FPGA_INTEL_SDM_MAILBOX bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" - depends on TARGET_SOCFPGA_SOC64 + depends on ARCH_SOCFPGA_SOC64 select FPGA_ALTERA help Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index f22d3b3d86e..ccfed94717e 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -21,6 +21,6 @@ obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o +obj-$(CONFIG_ARCH_SOCFPGA_GEN5) += socfpga_gen5.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += socfpga_arria10.o endif diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 4a9aa74357e..822183c5785 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -12,8 +12,8 @@ /* * Altera FPGA support */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) #include #endif #include @@ -48,8 +48,8 @@ static const struct altera_fpga { #endif }; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) int fpga_is_partial_data(int devnum, size_t img_len) { /* diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 6219284df3e..c8da6ead0ea 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -58,8 +58,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); - if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)) { + if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) { /* Disable SDMMC clock. */ clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); @@ -95,8 +95,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); #endif - if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)) { + if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) { /* Enable SDMMC clock */ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 306175873fa..2999e6b1710 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -217,7 +217,7 @@ config NAND_DENALI bool select DEVRES select SYS_NAND_SELF_INIT - select SYS_NAND_ONFI_DETECTION if TARGET_SOCFPGA_SOC64 + select SYS_NAND_ONFI_DETECTION if ARCH_SOCFPGA_SOC64 imply CMD_NAND config NAND_DENALI_DT diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index fce8004e134..d3ef050d1a1 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -194,7 +194,7 @@ config DWC_ETH_XGMAC_SOCFPGA select SYSCON select DWC_ETH_XGMAC depends on ARCH_SOCFPGA - default y if TARGET_SOCFPGA_AGILEX5 + default y if ARCH_SOCFPGA_AGILEX5 help The Synopsys Designware Ethernet XGMAC IP block with specific configuration used in Intel SoC FPGA chip. diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 935f282d6c5..2f63a8e54e5 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -20,7 +20,7 @@ config APPLE_PMGR_POWER_DOMAIN config AGILEX5_PMGR_POWER_DOMAIN bool "Enable the Agilex5 PMGR power domain driver" - depends on SPL_POWER_DOMAIN && TARGET_SOCFPGA_SOC64 + depends on SPL_POWER_DOMAIN && ARCH_SOCFPGA_SOC64 help Enable support for power gating peripherals' SRAM specified in the handoff data values obtained from the bitstream to reduce diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index e57729f0ef9..36a205f9fca 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -115,7 +115,7 @@ static int socfpga_reset_remove(struct udevice *dev) if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); - if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_ARRIA10)) + if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_ARRIA10)) writel(0, data->modrst_base + 8); } diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 120e7510f15..16ef434a8d9 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -196,14 +196,14 @@ config SYSRESET_SBI config SYSRESET_SOCFPGA bool "Enable support for Intel SOCFPGA family" - depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10) + depends on ARCH_SOCFPGA && (ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10) help This enables the system reset driver support for Intel SOCFPGA SoCs (Cyclone 5, Arria 5 and Arria 10). config SYSRESET_SOCFPGA_SOC64 bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)" - depends on ARCH_SOCFPGA && TARGET_SOCFPGA_SOC64 + depends on ARCH_SOCFPGA && ARCH_SOCFPGA_SOC64 help This enables the system reset driver support for Intel SOCFPGA SoC64 SoCs. -- cgit v1.2.3