From 4ab0a58a9067bb6ceacccefe98cc7db8cbed79c6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:30:19 +0200 Subject: mtd: rpc: renesas: Add R-Car Gen4 DT compatible Add device tree compatible string "renesas,rcar-gen4-rpc-if" to the driver to match on upstream RPC DT node in R-Car Gen4 DTs. Signed-off-by: Marek Vasut --- drivers/mtd/renesas_rpc_hf.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c index 941f2040983..03545822b07 100644 --- a/drivers/mtd/renesas_rpc_hf.c +++ b/drivers/mtd/renesas_rpc_hf.c @@ -387,6 +387,7 @@ static int rpc_hf_probe(struct udevice *dev) static const struct udevice_id rpc_hf_ids[] = { { .compatible = "renesas,r7s72100-rpc-if" }, { .compatible = "renesas,rcar-gen3-rpc-if" }, + { .compatible = "renesas,rcar-gen4-rpc-if" }, {} }; -- cgit v1.2.3 From 1cc7c7e119a31c64cf64d887374c95b58ffe9993 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:31:44 +0200 Subject: mtd: spi: renesas: Write DREAR register once Instead of writing DREAR with 0 first and then overwriting DREAR again in case of 4 byte addressing mode, write DREAR in every case once with the correct content right away. No functional change. Signed-off-by: Marek Vasut --- drivers/spi/renesas_rpc_spi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index e6b602cf7b4..749c686a6c4 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -277,14 +277,15 @@ static int rpc_spi_mem_exec_op(struct spi_slave *spi, writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR); smenr |= RPC_DRENR_CDE; - writel(0, priv->regs + RPC_DREAR); if (op->addr.nbytes == 4) { writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1), priv->regs + RPC_DREAR); smenr |= RPC_DRENR_ADE(0xF); } else if (op->addr.nbytes == 3) { + writel(0, priv->regs + RPC_DREAR); smenr |= RPC_DRENR_ADE(0x7); } else { + writel(0, priv->regs + RPC_DREAR); smenr |= RPC_DRENR_ADE(0); } -- cgit v1.2.3 From 3fba388e611e27e663c7cb4c1d1483e8909bdbc0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:31:45 +0200 Subject: mtd: spi: renesas: Write DRDMCR register once Instead of writing DRDMCR with 0 first and then overwriting DRDMCR again in case any dummy bytes have to be sent out, write DRDMCR in every case with the amount of dummy bytes that have to be sent out. In case no dummy bytes have to be sent out, the value written into DRDMCR is zero, so no dummy bytes are sent out. No functional change. Signed-off-by: Marek Vasut --- drivers/spi/renesas_rpc_spi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index 749c686a6c4..a2ac5525b90 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -289,12 +289,10 @@ static int rpc_spi_mem_exec_op(struct spi_slave *spi, smenr |= RPC_DRENR_ADE(0); } - writel(0, priv->regs + RPC_DRDMCR); - if (op->dummy.nbytes) { - writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); + if (op->dummy.nbytes) smenr |= RPC_DRENR_DME; - } + writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); writel(0, priv->regs + RPC_DROPR); writel(smenr, priv->regs + RPC_DRENR); -- cgit v1.2.3 From c90795076b30c33a95bcaf6d89979543d31fdde1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:31:46 +0200 Subject: mtd: spi: renesas: Configure DRDRENR register Make sure DRDRENR register is configured before performing external address space read. This register might have been configured by a prior stage bootloader and leaving it unconfigured would interfere with U-Boot operation. Since U-Boot RPC SPI driver does not support DDR data transfer mode yet, set this register unconditionally to 0. Signed-off-by: Marek Vasut --- drivers/spi/renesas_rpc_spi.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index a2ac5525b90..50890981149 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -294,6 +294,7 @@ static int rpc_spi_mem_exec_op(struct spi_slave *spi, writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); writel(0, priv->regs + RPC_DROPR); + writel(0, priv->regs + RPC_DRDRENR); writel(smenr, priv->regs + RPC_DRENR); memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes); -- cgit v1.2.3 From d5162463243da66b27ac7ea96fcffb5da4c9a639 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:31:47 +0200 Subject: mtd: spi: renesas: Configure RPC PHY timing registers Make sure RPC PHY timing registers are configured before performing bus access. These registers might have been left unconfigured or may have been configured by a prior stage bootloader and leaving them unconfigured or misconfigured would interfere with U-Boot operation. Set PHYOFFSET1 DDRTMG field to 3 which enables DDR timing adjustment when SPIDRE or DRDRE = 0 and set PHYOFFSET2 OCTTMG field to 4 which makes the interface operate in Serial flash or HyperFlash mode. Signed-off-by: Marek Vasut --- drivers/spi/renesas_rpc_spi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers') diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index 50890981149..9aab71db1de 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -145,6 +145,12 @@ #define RPC_PHYCNT_WBUF BIT(2) #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0) +#define RPCIF_PHYOFFSET1 0x0080 /* R/W */ +#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28) + +#define RPCIF_PHYOFFSET2 0x0084 /* R/W */ +#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8) + #define RPC_PHYINT 0x0088 /* R/W */ #define RPC_PHYINT_RSTEN BIT(18) #define RPC_PHYINT_WPEN BIT(17) @@ -227,6 +233,12 @@ static int rpc_spi_claim_bus(struct udevice *dev, bool manual) struct udevice *bus = dev->parent; struct rpc_spi_priv *priv = dev_get_priv(bus); + setbits_le32(priv->regs + RPCIF_PHYOFFSET1, + RPCIF_PHYOFFSET1_DDRTMG(3)); + clrsetbits_le32(priv->regs + RPCIF_PHYOFFSET2, + RPCIF_PHYOFFSET2_OCTTMG(7), + RPCIF_PHYOFFSET2_OCTTMG(4)); + /* NOTE: The 0x260 are undocumented bits, but they must be set. */ writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260, priv->regs + RPC_PHYCNT); -- cgit v1.2.3 From 2e255d2e6e1a8b56f594de4e6f969c97ce1aff46 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:31:48 +0200 Subject: mtd: spi: renesas: Add R-Car Gen4 DT compatible Add device tree compatible string "renesas,rcar-gen4-rpc-if" to the driver to match on upstream RPC DT node in R-Car Gen4 DTs. Signed-off-by: Marek Vasut --- drivers/spi/renesas_rpc_spi.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index 9aab71db1de..f1e6f9f4e01 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -465,6 +465,7 @@ static const struct dm_spi_ops rpc_spi_ops = { static const struct udevice_id rpc_spi_ids[] = { { .compatible = "renesas,r7s72100-rpc-if" }, { .compatible = "renesas,rcar-gen3-rpc-if" }, + { .compatible = "renesas,rcar-gen4-rpc-if" }, { } }; -- cgit v1.2.3 From f7fead89141e72558dd24bb7ac47aabb77fc4662 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 16 Feb 2024 17:35:35 +0100 Subject: clk: sifive: append missing \n to messages If multiple messages are written, line-feeds improve the readability. Fixes: c40b6df87fc0 ("clk: Add SiFive FU540 PRCI clock driver") Signed-off-by: Heinrich Schuchardt Reviewed-by: Sean Anderson --- drivers/clk/analogbits/wrpll-cln28hpc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c index a3cb109d357..537c696b727 100644 --- a/drivers/clk/analogbits/wrpll-cln28hpc.c +++ b/drivers/clk/analogbits/wrpll-cln28hpc.c @@ -81,7 +81,7 @@ static int __wrpll_calc_filter_range(unsigned long post_divr_freq) { if (post_divr_freq < MIN_POST_DIVR_FREQ || post_divr_freq > MAX_POST_DIVR_FREQ) { - WARN(1, "%s: post-divider reference freq out of range: %lu", + WARN(1, "%s: post-divider reference freq out of range: %lu\n", __func__, post_divr_freq); return -ERANGE; } @@ -229,7 +229,7 @@ int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, int range; if (c->flags == 0) { - WARN(1, "%s called with uninitialized PLL config", __func__); + WARN(1, "%s called with uninitialized PLL config\n", __func__); return -EINVAL; } @@ -335,7 +335,7 @@ unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c, u64 n; if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) { - WARN(1, "external feedback mode not yet supported"); + WARN(1, "external feedback mode not yet supported\n"); return ULONG_MAX; } -- cgit v1.2.3 From 5896ac5766fdafb0ba087c16261e3dff792dbe3e Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 17 Feb 2024 00:18:04 +0100 Subject: clk: sifive: avoid declaring static variables in includes The existing code is unnecessarily convoluted: Arrays __prci_init_clocks_fu[5|7]40 are initialized with data. In separate includes fu[5|7]40-prci.h the size of the arrays is provided as constants. By moving the structures prci_clk_fu[5|7]40 to the respective code modules we can directly use ARRAY_SIZE() to access the size of the data used for initialization. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/sifive/fu540-prci.c | 7 ++++++- drivers/clk/sifive/fu540-prci.h | 22 ---------------------- drivers/clk/sifive/fu740-prci.c | 7 ++++++- drivers/clk/sifive/fu740-prci.h | 22 ---------------------- drivers/clk/sifive/sifive-prci.c | 3 +-- drivers/clk/sifive/sifive-prci.h | 4 ++++ 6 files changed, 17 insertions(+), 48 deletions(-) delete mode 100644 drivers/clk/sifive/fu540-prci.h delete mode 100644 drivers/clk/sifive/fu740-prci.h (limited to 'drivers') diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index ceb2c6fab0d..e55a26ab8fd 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -58,7 +58,7 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { }; /* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu540[] = { +static struct __prci_clock __prci_init_clocks_fu540[] = { [PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", @@ -83,3 +83,8 @@ struct __prci_clock __prci_init_clocks_fu540[] = { .ops = &sifive_fu540_prci_tlclksel_clk_ops, }, }; + +const struct prci_clk_desc prci_clk_fu540 = { + .clks = __prci_init_clocks_fu540, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), +}; diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h deleted file mode 100644 index 113301107da..00000000000 --- a/drivers/clk/sifive/fu540-prci.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * Zong Li - * Pragnesh Patel - */ - -#ifndef __SIFIVE_CLK_FU540_PRCI_H -#define __SIFIVE_CLK_FU540_PRCI_H - -#include "sifive-prci.h" - -#define NUM_CLOCK_FU540 4 - -extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540]; - -static const struct prci_clk_desc prci_clk_fu540 = { - .clks = __prci_init_clocks_fu540, - .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), -}; - -#endif /* __SIFIVE_CLK_FU540_PRCI_H */ diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 5edc864e4bd..4274b215d2f 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -102,7 +102,7 @@ static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = { }; /* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu740[] = { +static struct __prci_clock __prci_init_clocks_fu740[] = { [FU740_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", @@ -156,3 +156,8 @@ struct __prci_clock __prci_init_clocks_fu740[] = { .pwd = &__prci_pcieaux_data, } }; + +const struct prci_clk_desc prci_clk_fu740 = { + .clks = __prci_init_clocks_fu740, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), +}; diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h deleted file mode 100644 index b74f0789061..00000000000 --- a/drivers/clk/sifive/fu740-prci.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * Zong Li - * Pragnesh Patel - */ - -#ifndef __SIFIVE_CLK_FU740_PRCI_H -#define __SIFIVE_CLK_FU740_PRCI_H - -#include "sifive-prci.h" - -#define NUM_CLOCK_FU740 9 - -extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; - -static const struct prci_clk_desc prci_clk_fu740 = { - .clks = __prci_init_clocks_fu740, - .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), -}; - -#endif /* __SIFIVE_CLK_FU740_PRCI_H */ diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 5ea86062800..aa26d3a109b 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -33,8 +33,7 @@ #include #include -#include "fu540-prci.h" -#include "fu740-prci.h" +#include "sifive-prci.h" /* * Private functions diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 5ce33d61846..b391698081d 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -320,4 +320,8 @@ unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc, int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable); +/* Clock driver data */ +extern const struct prci_clk_desc prci_clk_fu540; +extern const struct prci_clk_desc prci_clk_fu740; + #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ -- cgit v1.2.3 From 7387be522efe2ead220fadc1e249d06aaf435719 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 26 Aug 2024 10:49:56 -0600 Subject: bootcount: Update to point to current documentation The current documentation for the bootcount API is on our website and not the old wiki, update the link in two places. Signed-off-by: Tom Rini --- drivers/bootcount/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 2105cea3d45..d375984bb33 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -6,7 +6,7 @@ menuconfig BOOTCOUNT_LIMIT bool "Enable support for checking boot count limit" help Enable checking for exceeding the boot count limit. - More information: http://www.denx.de/wiki/DULG/UBootBootCountLimit + More information: https://docs.u-boot.org/en/latest/api/bootcount.html if BOOTCOUNT_LIMIT -- cgit v1.2.3