From de6b405e615232817322416b89bcde637ade40d4 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Tue, 30 Sep 2025 17:43:46 +0100 Subject: video: exynos: node variable should not be unsigned THe variable 'node' is assigned a value of an int, tested for being less than or equal to zero then passed as an argument to a function that takes an int so 'node' should not be unsigned. Fix it. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/video/exynos/exynos_fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c index 0407a3f51b0..1cc1bd92e57 100644 --- a/drivers/video/exynos/exynos_fb.c +++ b/drivers/video/exynos/exynos_fb.c @@ -350,7 +350,7 @@ void exynos_fimd_window_off(struct exynos_fb_priv *priv, unsigned int win_id) void exynos_fimd_disable_sysmmu(void) { u32 *sysmmufimd; - unsigned int node; + int node; int node_list[2]; int count; int i; -- cgit v1.3.1 From 548e9a254c7d0bd9796decfea43d7759070c7312 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 1 Oct 2025 11:05:10 +0100 Subject: video: nexell: unsigned parameter cannot be negative The parameter 'alpha' is declared as an unsigned type so cannot be negative. The code to test it as being less than zero will always fail and so is redundant and should be removed. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Stefan Bosch Signed-off-by: Minkyu Kang --- drivers/video/nexell/soc/s5pxx18_soc_mlc.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers') diff --git a/drivers/video/nexell/soc/s5pxx18_soc_mlc.c b/drivers/video/nexell/soc/s5pxx18_soc_mlc.c index c8cf833f308..2c8348bf633 100644 --- a/drivers/video/nexell/soc/s5pxx18_soc_mlc.c +++ b/drivers/video/nexell/soc/s5pxx18_soc_mlc.c @@ -1641,8 +1641,6 @@ void nx_mlc_set_layer_alpha256(u32 module_index, u32 layer, u32 alpha) u32 register_data; register struct nx_mlc_register_set *pregister; - if (alpha < 0) - alpha = 0; if (alpha > 255) alpha = 255; -- cgit v1.3.1 From 7accb716c10c231e3785b47d02929919b3c5cd86 Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Thu, 5 Feb 2026 09:07:49 +0100 Subject: gpio: stm32-gpio: prevent the use of the secure protected pins The hardware denies any access from the U-Boot non-secure world to the secure-protected pins. Hence, prevent any driver to request such a pin. Signed-off-by: Fabien Dessenne Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/gpio/stm32_gpio.c | 25 +++++++++++++++++++++++++ drivers/gpio/stm32_gpio_priv.h | 5 +++++ 2 files changed, 30 insertions(+) (limited to 'drivers') diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c index b8eb55465d3..e354a4148ca 100644 --- a/drivers/gpio/stm32_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -32,6 +32,9 @@ #define OTYPE_BITS(gpio_pin) (gpio_pin) #define OTYPE_MSK 1 +#define SECCFG_BITS(gpio_pin) (gpio_pin) +#define SECCFG_MSK 1 + static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs, int idx, int mode) @@ -89,6 +92,27 @@ static bool stm32_gpio_is_mapped(struct udevice *dev, int offset) return !!(priv->gpio_range & BIT(offset)); } +static int stm32_gpio_request(struct udevice *dev, unsigned int offset, const char *label) +{ + struct stm32_gpio_priv *priv = dev_get_priv(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct stm32_gpio_regs *regs = priv->regs; + ulong drv_data = dev_get_driver_data(dev); + + if (!stm32_gpio_is_mapped(dev, offset)) + return -ENXIO; + + /* Deny request access if IO is secured */ + if ((drv_data & STM32_GPIO_FLAG_SEC_CTRL) && + ((readl(®s->seccfgr) >> SECCFG_BITS(offset)) & SECCFG_MSK)) { + dev_err(dev, "Failed to get secure IO %s %d @ %p\n", + uc_priv->bank_name, offset, regs); + return -EACCES; + } + + return 0; +} + static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset) { struct stm32_gpio_priv *priv = dev_get_priv(dev); @@ -238,6 +262,7 @@ static int stm32_gpio_get_flags(struct udevice *dev, unsigned int offset, } static const struct dm_gpio_ops gpio_stm32_ops = { + .request = stm32_gpio_request, .direction_input = stm32_gpio_direction_input, .direction_output = stm32_gpio_direction_output, .get_value = stm32_gpio_get_value, diff --git a/drivers/gpio/stm32_gpio_priv.h b/drivers/gpio/stm32_gpio_priv.h index 662a000fe73..d89e9b8ed60 100644 --- a/drivers/gpio/stm32_gpio_priv.h +++ b/drivers/gpio/stm32_gpio_priv.h @@ -51,6 +51,8 @@ enum stm32_gpio_af { STM32_GPIO_AF15 }; +#define STM32_GPIO_FLAG_SEC_CTRL BIT(0) + struct stm32_gpio_dsc { u8 port; u8 pin; @@ -74,6 +76,9 @@ struct stm32_gpio_regs { u32 bsrr; /* GPIO port bit set/reset */ u32 lckr; /* GPIO port configuration lock */ u32 afr[2]; /* GPIO alternate function */ + u32 brr; /* GPIO port bit reset */ + u32 rfu; /* Reserved */ + u32 seccfgr; /* GPIO secure configuration */ }; struct stm32_gpio_priv { -- cgit v1.3.1 From 04dcaadd4392d8b7498e6e80a977e0cd67074558 Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Thu, 5 Feb 2026 09:07:50 +0100 Subject: pinctrl: pinctrl_stm32: prevent the use of the secure protected pins The hardware denies any access from the U-Boot non-secure world to the secure-protected pins. Hence, prevent any driver to configure such a pin. Identify the secure pins with "NO ACCESS" through the 'pinmux status -a' command. Use a driver data structure to identify which hardware versions support this feature. Signed-off-by: Fabien Dessenne Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/pinctrl/pinctrl_stm32.c | 83 +++++++++++++++++++++++++++++++++++------ 1 file changed, 71 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index fbf0271f08a..1758f9a909c 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,7 @@ #define PUPD_MASK 3 #define OTYPE_MSK 1 #define AFR_MASK 0xF +#define SECCFG_MSK 1 struct stm32_pinctrl_priv { struct hwspinlock hws; @@ -39,7 +41,12 @@ struct stm32_gpio_bank { struct list_head list; }; +struct stm32_pinctrl_data { + bool secure_control; +}; + #ifndef CONFIG_XPL_BUILD +static int stm32_pinctrl_get_access(struct udevice *gpio_dev, unsigned int gpio_idx); static char pin_name[PINNAME_SIZE]; static const char * const pinmux_mode[GPIOF_COUNT] = { @@ -216,6 +223,12 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, if (!gpio_dev) return -ENODEV; + /* Check access protection */ + if (stm32_pinctrl_get_access(gpio_dev, gpio_idx)) { + snprintf(buf, size, "NO ACCESS"); + return 0; + } + mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label); dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n", selector, gpio_idx, mode); @@ -252,6 +265,20 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, #endif +static int stm32_pinctrl_get_access(struct udevice *gpio_dev, unsigned int gpio_idx) +{ + struct stm32_gpio_priv *priv = dev_get_priv(gpio_dev); + struct stm32_gpio_regs *regs = priv->regs; + ulong drv_data = dev_get_driver_data(gpio_dev); + + /* Deny request access if IO is secured */ + if ((drv_data & STM32_GPIO_FLAG_SEC_CTRL) && + ((readl(®s->seccfgr) >> gpio_idx) & SECCFG_MSK)) + return -EACCES; + + return 0; +} + static int stm32_pinctrl_probe(struct udevice *dev) { struct stm32_pinctrl_priv *priv = dev_get_priv(dev); @@ -279,6 +306,14 @@ static int stm32_gpio_config(ofnode node, int ret; u32 index; + /* Check access protection */ + ret = stm32_pinctrl_get_access(desc->dev, desc->offset); + if (ret) { + dev_err(desc->dev, "Failed to get secure IO %s %d @ %p\n", + uc_priv->bank_name, desc->offset, regs); + return ret; + } + if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || ctl->pupd > 2 || ctl->speed > 3) return -EINVAL; @@ -414,8 +449,25 @@ static int stm32_pinctrl_bind(struct udevice *dev) { ofnode node; const char *name; + struct driver *drv; + const struct stm32_pinctrl_data *drv_data; + ulong gpio_data = 0; int ret; + drv = lists_driver_lookup_name("gpio_stm32"); + if (!drv) { + debug("Cannot find driver 'gpio_stm32'\n"); + return -ENOENT; + } + + drv_data = (const struct stm32_pinctrl_data *)dev_get_driver_data(dev); + if (!drv_data) { + debug("Cannot find driver data\n"); + return -EINVAL; + } + if (drv_data->secure_control) + gpio_data = STM32_GPIO_FLAG_SEC_CTRL; + dev_for_each_subnode(node, dev) { dev_dbg(dev, "bind %s\n", ofnode_get_name(node)); @@ -431,8 +483,7 @@ static int stm32_pinctrl_bind(struct udevice *dev) return -EINVAL; /* Bind each gpio node */ - ret = device_bind_driver_to_node(dev, "gpio_stm32", - name, node, NULL); + ret = device_bind_with_driver_data(dev, drv, name, gpio_data, node, NULL); if (ret) return ret; @@ -495,17 +546,25 @@ static struct pinctrl_ops stm32_pinctrl_ops = { #endif }; +static const struct stm32_pinctrl_data stm32_pinctrl_no_sec = { + .secure_control = false, +}; + +static const struct stm32_pinctrl_data stm32_pinctrl_with_sec = { + .secure_control = true, +}; + static const struct udevice_id stm32_pinctrl_ids[] = { - { .compatible = "st,stm32f429-pinctrl" }, - { .compatible = "st,stm32f469-pinctrl" }, - { .compatible = "st,stm32f746-pinctrl" }, - { .compatible = "st,stm32f769-pinctrl" }, - { .compatible = "st,stm32h743-pinctrl" }, - { .compatible = "st,stm32mp157-pinctrl" }, - { .compatible = "st,stm32mp157-z-pinctrl" }, - { .compatible = "st,stm32mp135-pinctrl" }, - { .compatible = "st,stm32mp257-pinctrl" }, - { .compatible = "st,stm32mp257-z-pinctrl" }, + { .compatible = "st,stm32f429-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec }, + { .compatible = "st,stm32f469-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec }, + { .compatible = "st,stm32f746-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec }, + { .compatible = "st,stm32f769-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec }, + { .compatible = "st,stm32h743-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec }, + { .compatible = "st,stm32mp157-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec }, + { .compatible = "st,stm32mp157-z-pinctrl", .data = (ulong)&stm32_pinctrl_no_sec }, + { .compatible = "st,stm32mp135-pinctrl", .data = (ulong)&stm32_pinctrl_with_sec }, + { .compatible = "st,stm32mp257-pinctrl", .data = (ulong)&stm32_pinctrl_with_sec }, + { .compatible = "st,stm32mp257-z-pinctrl", .data = (ulong)&stm32_pinctrl_with_sec }, { } }; -- cgit v1.3.1 From a44b36a044f2307a46d6b6a15f96144b6e437695 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 3 Feb 2026 17:49:21 +0100 Subject: clk: stm32mp21: Add clock driver support Add clock driver support for STM32MP21 SoCs. Signed-off-by: Nicolas Le Bayon Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/clk/stm32/Kconfig | 9 + drivers/clk/stm32/Makefile | 1 + drivers/clk/stm32/clk-stm32mp21.c | 709 ++++++++++++++++++++++++++++++++++++++ include/stm32mp21_rcc.h | 651 ++++++++++++++++++++++++++++++++++ 4 files changed, 1370 insertions(+) create mode 100644 drivers/clk/stm32/clk-stm32mp21.c create mode 100644 include/stm32mp21_rcc.h (limited to 'drivers') diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig index ea856be1662..4e488136eac 100644 --- a/drivers/clk/stm32/Kconfig +++ b/drivers/clk/stm32/Kconfig @@ -37,6 +37,15 @@ config CLK_STM32MP13 Enable the STM32 clock (RCC) driver. Enable support for manipulating STM32MP13's on-SoC clocks. +config CLK_STM32MP21 + bool "Enable RCC clock driver for STM32MP21" + depends on ARCH_STM32MP && CLK + default y if STM32MP21X + select CLK_STM32_CORE + help + Enable the STM32 clock (RCC) driver. Enable support for + manipulating STM32MP21's on-SoC clocks. + config CLK_STM32MP25 bool "Enable RCC clock driver for STM32MP25" depends on ARCH_STM32MP && CLK diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile index 56adb8a4bbb..0b849c52a3b 100644 --- a/drivers/clk/stm32/Makefile +++ b/drivers/clk/stm32/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_CLK_STM32F) += clk-stm32f.o obj-$(CONFIG_CLK_STM32H7) += clk-stm32h7.o obj-$(CONFIG_CLK_STM32MP1) += clk-stm32mp1.o obj-$(CONFIG_CLK_STM32MP13) += clk-stm32mp13.o +obj-$(CONFIG_CLK_STM32MP21) += clk-stm32mp21.o obj-$(CONFIG_CLK_STM32MP25) += clk-stm32mp25.o diff --git a/drivers/clk/stm32/clk-stm32mp21.c b/drivers/clk/stm32/clk-stm32mp21.c new file mode 100644 index 00000000000..ad990b6ad93 --- /dev/null +++ b/drivers/clk/stm32/clk-stm32mp21.c @@ -0,0 +1,709 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2026, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk-stm32-core.h" +#include "stm32mp21_rcc.h" + +/* Clock security definition */ +#define SECF_NONE -1 + +#define RCC_REG_SIZE 32 +#define RCC_SECCFGR(x) (((x) / RCC_REG_SIZE) * 0x4 + RCC_SECCFGR0) +#define RCC_CIDCFGR(x) ((x) * 0x8 + RCC_R0CIDCFGR) +#define RCC_SEMCR(x) ((x) * 0x8 + RCC_R0SEMCR) +#define RCC_CID1 1 + +/* Register: RIFSC_CIDCFGR */ +#define RCC_CIDCFGR_CFEN BIT(0) +#define RCC_CIDCFGR_SEM_EN BIT(1) +#define RCC_CIDCFGR_SEMWLC1_EN BIT(17) +#define RCC_CIDCFGR_SCID_MASK GENMASK(6, 4) + +/* Register: RIFSC_SEMCR */ +#define RCC_SEMCR_SEMCID_MASK GENMASK(6, 4) + +#define STM32MP21_RIFRCC_DBG_ID 73 +#define STM32MP21_RIFRCC_MCO1_ID 108 +#define STM32MP21_RIFRCC_MCO2_ID 109 +#define STM32MP21_RIFRCC_OSPI1_ID 110 + +#define SEC_RIFSC_FLAG BIT(31) +#define SEC_RIFRCC(_id) (STM32MP21_RIFRCC_##_id##_ID) +#define SEC_RIFSC(_id) ((_id) | SEC_RIFSC_FLAG) + +/* must match scmi clock order found in DT */ +enum { + IDX_HSE, + IDX_HSI, + IDX_MSI, + IDX_LSE, + IDX_LSI, + IDX_HSE_DIV2, + IDX_ICN_HS_MCU, + IDX_ICN_LS_MCU, + IDX_ICN_SDMMC, + IDX_ICN_DDR, + IDX_ICN_DISPLAY, + IDX_ICN_HSL, + IDX_ICN_NIC, + IDX_FLEXGEN_07, + IDX_FLEXGEN_08, + IDX_FLEXGEN_09, + IDX_FLEXGEN_10, + IDX_FLEXGEN_11, + IDX_FLEXGEN_12, + IDX_FLEXGEN_13, + IDX_FLEXGEN_14, + IDX_FLEXGEN_16, + IDX_FLEXGEN_17, + IDX_FLEXGEN_18, + IDX_FLEXGEN_19, + IDX_FLEXGEN_20, + IDX_FLEXGEN_21, + IDX_FLEXGEN_22, + IDX_FLEXGEN_23, + IDX_FLEXGEN_24, + IDX_FLEXGEN_25, + IDX_FLEXGEN_26, + IDX_FLEXGEN_27, + IDX_FLEXGEN_28, + IDX_FLEXGEN_29, + IDX_FLEXGEN_30, + IDX_FLEXGEN_31, + IDX_FLEXGEN_33, + IDX_FLEXGEN_36, + IDX_FLEXGEN_37, + IDX_FLEXGEN_38, + IDX_FLEXGEN_39, + IDX_FLEXGEN_40, + IDX_FLEXGEN_41, + IDX_FLEXGEN_42, + IDX_FLEXGEN_43, + IDX_FLEXGEN_44, + IDX_FLEXGEN_45, + IDX_FLEXGEN_46, + IDX_FLEXGEN_47, + IDX_FLEXGEN_48, + IDX_FLEXGEN_50, + IDX_FLEXGEN_51, + IDX_FLEXGEN_52, + IDX_FLEXGEN_53, + IDX_FLEXGEN_54, + IDX_FLEXGEN_55, + IDX_FLEXGEN_56, + IDX_FLEXGEN_57, + IDX_FLEXGEN_58, + IDX_FLEXGEN_61, + IDX_FLEXGEN_62, + IDX_FLEXGEN_63, + IDX_ICN_APB1, + IDX_ICN_APB2, + IDX_ICN_APB3, + IDX_ICN_APB4, + IDX_ICN_APB5, + IDX_ICN_APBDBG, + IDX_TIMG1, + IDX_TIMG2, +}; + +static const struct clk_parent_data adc1_src[] = { + { .index = IDX_FLEXGEN_46 }, + { .index = IDX_ICN_LS_MCU }, +}; + +static const struct clk_parent_data adc2_src[] = { + { .index = IDX_FLEXGEN_47 }, + { .index = IDX_ICN_LS_MCU }, + { .index = IDX_FLEXGEN_46 }, +}; + +static const struct clk_parent_data usb2phy1_src[] = { + { .index = IDX_FLEXGEN_57 }, + { .index = IDX_HSE_DIV2 }, +}; + +static const struct clk_parent_data usb2phy2_src[] = { + { .index = IDX_FLEXGEN_58 }, + { .index = IDX_HSE_DIV2 }, +}; + +static const struct clk_parent_data dts_src[] = { + { .index = IDX_HSI }, + { .index = IDX_HSE }, + { .index = IDX_MSI }, +}; + +static const struct clk_parent_data mco1_src[] = { + { .index = IDX_FLEXGEN_61 }, + { .name = "ck_obs0" }, +}; + +static const struct clk_parent_data mco2_src[] = { + { .index = IDX_FLEXGEN_62 }, + { .name = "ck_obs1" }, +}; + +enum enum_mux_cfg { + MUX_MCO1, + MUX_MCO2, + MUX_ADC1, + MUX_ADC2, + MUX_USB2PHY1, + MUX_USB2PHY2, + MUX_DTS, + MUX_NB +}; + +#define MUX_CFG(id, src, _offset, _shift, _witdh)[id] = {\ + .num_parents = ARRAY_SIZE(src),\ + .parent_data = src,\ + .reg_off = (_offset),\ + .shift = (_shift),\ + .width = (_witdh),\ +} + +static const struct stm32_mux_cfg stm32mp21_muxes[MUX_NB] = { + MUX_CFG(MUX_ADC1, adc1_src, RCC_ADC1CFGR, 12, 1), + MUX_CFG(MUX_ADC2, adc2_src, RCC_ADC2CFGR, 12, 2), + MUX_CFG(MUX_DTS, dts_src, RCC_DTSCFGR, 12, 2), + MUX_CFG(MUX_MCO1, mco1_src, RCC_MCO1CFGR, 0, 1), + MUX_CFG(MUX_MCO2, mco2_src, RCC_MCO2CFGR, 0, 1), + MUX_CFG(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1), + MUX_CFG(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1), +}; + +enum enum_gate_cfg { + GATE_ADC1, + GATE_ADC2, + GATE_CRC, + GATE_CRYP1, + GATE_CRYP2, + GATE_CSI, + GATE_DBG, + GATE_DCMIPP, + GATE_DTS, + GATE_ETH1, + GATE_ETH1MAC, + GATE_ETH1RX, + GATE_ETH1STP, + GATE_ETH1TX, + GATE_ETH2, + GATE_ETH2MAC, + GATE_ETH2RX, + GATE_ETH2STP, + GATE_ETH2TX, + GATE_ETR, + GATE_FDCAN, + GATE_HASH1, + GATE_HASH2, + GATE_HDP, + GATE_I2C1, + GATE_I2C2, + GATE_I2C3, + GATE_I3C1, + GATE_I3C2, + GATE_I3C3, + GATE_IWDG1, + GATE_IWDG2, + GATE_IWDG3, + GATE_IWDG4, + GATE_LPTIM1, + GATE_LPTIM2, + GATE_LPTIM3, + GATE_LPTIM4, + GATE_LPTIM5, + GATE_LPUART1, + GATE_LTDC, + GATE_MCO1, + GATE_MCO2, + GATE_MDF1, + GATE_OSPI1, + GATE_PKA, + GATE_RNG1, + GATE_RNG2, + GATE_SAES, + GATE_SAI1, + GATE_SAI2, + GATE_SAI3, + GATE_SAI4, + GATE_SDMMC1, + GATE_SDMMC2, + GATE_SDMMC3, + GATE_SERC, + GATE_SPDIFRX, + GATE_SPI1, + GATE_SPI2, + GATE_SPI3, + GATE_SPI4, + GATE_SPI5, + GATE_SPI6, + GATE_STGEN, + GATE_STM, + GATE_TIM1, + GATE_TIM2, + GATE_TIM3, + GATE_TIM4, + GATE_TIM5, + GATE_TIM6, + GATE_TIM7, + GATE_TIM8, + GATE_TIM10, + GATE_TIM11, + GATE_TIM12, + GATE_TIM13, + GATE_TIM14, + GATE_TIM15, + GATE_TIM16, + GATE_TIM17, + GATE_TRACE, + GATE_UART4, + GATE_UART5, + GATE_UART7, + GATE_USART1, + GATE_USART2, + GATE_USART3, + GATE_USART6, + GATE_USBH, + GATE_USBOTG, + GATE_USB2PHY1, + GATE_USB2PHY2, + GATE_VREF, + GATE_WWDG1, + GATE_NB +}; + +#define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\ + .reg_off = (_offset),\ + .bit_idx = (_bit_idx),\ + .set_clr = (_offset_clr),\ +} + +static const struct stm32_gate_cfg stm32mp21_gates[GATE_NB] = { + GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0), + GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0), + GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0), + GATE_CFG(GATE_DBG, RCC_DBGCFGR, 8, 0), + GATE_CFG(GATE_TRACE, RCC_DBGCFGR, 9, 0), + GATE_CFG(GATE_STM, RCC_STMCFGR, 1, 0), + GATE_CFG(GATE_ETR, RCC_ETRCFGR, 1, 0), + GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0), + GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0), + GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0), + GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0), + GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0), + GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0), + GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0), + GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0), + GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0), + GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0), + GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0), + GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0), + GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0), + GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0), + GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0), + GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0), + GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0), + GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0), + GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0), + GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0), + GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0), + GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0), + GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0), + GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0), + GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0), + GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0), + GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0), + GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0), + GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0), + GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0), + GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0), + GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0), + GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0), + GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0), + GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0), + GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0), + GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0), + GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0), + GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0), + GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0), + GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0), + GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0), + GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0), + GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0), + GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0), + GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0), + GATE_CFG(GATE_ADC1, RCC_ADC1CFGR, 1, 0), + GATE_CFG(GATE_ADC2, RCC_ADC2CFGR, 1, 0), + GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0), + GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0), + GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0), + GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0), + GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0), + GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0), + GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0), + GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0), + GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0), + GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0), + GATE_CFG(GATE_USBH, RCC_USBHCFGR, 1, 0), + GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0), + GATE_CFG(GATE_USBOTG, RCC_OTGCFGR, 1, 0), + GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0), + GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0), + GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0), + GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0), + GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0), + GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0), + GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0), + GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0), + GATE_CFG(GATE_RNG1, RCC_RNG1CFGR, 1, 0), + GATE_CFG(GATE_RNG2, RCC_RNG2CFGR, 1, 0), + GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0), + GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0), + GATE_CFG(GATE_HASH1, RCC_HASH1CFGR, 1, 0), + GATE_CFG(GATE_HASH2, RCC_HASH2CFGR, 1, 0), + GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0), + GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0), + GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0), + GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0), + GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0), + GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0), + GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0), + GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0), + GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0), + GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0), + GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0), + GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0), + GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0), + GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0), +}; + +static int stm32_rcc_get_access(struct udevice *dev, u32 index) +{ + fdt_addr_t rcc_base = dev_read_addr(dev->parent); + u32 seccfgr, cidcfgr, semcr; + int bit, cid; + + bit = index % RCC_REG_SIZE; + + seccfgr = readl(rcc_base + RCC_SECCFGR(index)); + if (seccfgr & BIT(bit)) + return -EACCES; + + cidcfgr = readl(rcc_base + RCC_CIDCFGR(index)); + if (!(cidcfgr & RCC_CIDCFGR_CFEN)) + /* CID filtering is turned off: access granted */ + return 0; + + if (!(cidcfgr & RCC_CIDCFGR_SEM_EN)) { + /* Static CID mode */ + cid = FIELD_GET(RCC_CIDCFGR_SCID_MASK, cidcfgr); + if (cid != RCC_CID1) + return -EACCES; + return 0; + } + + /* Pass-list with semaphore mode */ + if (!(cidcfgr & RCC_CIDCFGR_SEMWLC1_EN)) + return -EACCES; + + semcr = readl(rcc_base + RCC_SEMCR(index)); + + cid = FIELD_GET(RCC_SEMCR_SEMCID_MASK, semcr); + if (cid != RCC_CID1) + return -EACCES; + + return 0; +} + +static int stm32mp21_check_security(struct udevice *dev, void __iomem *base, + const struct clock_config *cfg) +{ + int ret = 0; + + if (cfg->sec_id != SECF_NONE) { + u32 index = (u32)cfg->sec_id; + + if (index & SEC_RIFSC_FLAG) + ret = stm32_rifsc_grant_access_by_id(dev_ofnode(dev), + index & ~SEC_RIFSC_FLAG); + else + ret = stm32_rcc_get_access(dev, index); + } + + return ret; +} + +#define STM32_COMPOSITE_NODIV(_id, _name, _flags, _sec_id, _gate_id, _mux_id)\ + STM32_COMPOSITE(_id, _name, _flags, _sec_id, _gate_id, _mux_id, NO_STM32_DIV) + +static const struct clock_config stm32mp21_clock_cfg[] = { + /* ADC */ + STM32_GATE(CK_BUS_ADC1, "ck_icn_p_adc1", IDX_ICN_LS_MCU, 0, GATE_ADC1, + SEC_RIFSC(58)), + STM32_COMPOSITE_NODIV(CK_KER_ADC1, "ck_ker_adc12", 0, SEC_RIFSC(58), + GATE_ADC1, MUX_ADC1), + STM32_GATE(CK_BUS_ADC2, "ck_icn_p_adc2", IDX_ICN_LS_MCU, 0, GATE_ADC2, SEC_RIFSC(59)), + STM32_COMPOSITE_NODIV(CK_KER_ADC2, "ck_ker_adc2", 0, SEC_RIFSC(59), GATE_ADC2, MUX_ADC2), + + /* CSI-HOST */ + STM32_GATE(CK_BUS_CSI, "ck_icn_p_csi", IDX_ICN_APB4, 0, GATE_CSI, SEC_RIFSC(86)), + STM32_GATE(CK_KER_CSI, "ck_ker_csi", IDX_FLEXGEN_29, 0, GATE_CSI, SEC_RIFSC(86)), + STM32_GATE(CK_KER_CSITXESC, "ck_ker_csitxesc", IDX_FLEXGEN_30, 0, GATE_CSI, + SEC_RIFSC(86)), + + /* CSI-PHY */ + STM32_GATE(CK_KER_CSIPHY, "ck_ker_csiphy", IDX_FLEXGEN_31, 0, GATE_CSI, + SEC_RIFSC(86)), + + /* DCMIPP */ + STM32_GATE(CK_BUS_DCMIPP, "ck_icn_p_dcmipp", IDX_ICN_APB4, 0, GATE_DCMIPP, + SEC_RIFSC(87)), + + /* CRC */ + STM32_GATE(CK_BUS_CRC, "ck_icn_p_crc", IDX_ICN_LS_MCU, 0, GATE_CRC, SEC_RIFSC(109)), + + /* CRYP */ + STM32_GATE(CK_BUS_CRYP1, "ck_icn_p_cryp1", IDX_ICN_LS_MCU, 0, GATE_CRYP1, + SEC_RIFSC(98)), + STM32_GATE(CK_BUS_CRYP2, "ck_icn_p_cryp2", IDX_ICN_LS_MCU, 0, GATE_CRYP2, + SEC_RIFSC(99)), + + /* DBG & TRACE*/ + /* Trace and debug clocks are managed by SCMI */ + + /* Display subsystem */ + /* LTDC */ + STM32_GATE(CK_BUS_LTDC, "ck_icn_p_ltdc", IDX_ICN_APB4, 0, GATE_LTDC, SEC_RIFSC(80)), + STM32_GATE(CK_KER_LTDC, "ck_ker_ltdc", IDX_FLEXGEN_27, CLK_SET_RATE_PARENT, GATE_LTDC, + SEC_RIFSC(80)), + + /* DTS */ + STM32_COMPOSITE_NODIV(CK_KER_DTS, "ck_ker_dts", 0, SEC_RIFSC(107), GATE_DTS, MUX_DTS), + + /* ETHERNET */ + STM32_GATE(CK_BUS_ETH1, "ck_icn_p_eth1", IDX_ICN_LS_MCU, 0, GATE_ETH1, SEC_RIFSC(60)), + STM32_GATE(CK_ETH1_STP, "ck_ker_eth1stp", IDX_ICN_LS_MCU, 0, GATE_ETH1STP, + SEC_RIFSC(60)), + STM32_GATE(CK_KER_ETH1, "ck_ker_eth1", IDX_FLEXGEN_54, 0, GATE_ETH1, SEC_RIFSC(60)), + STM32_GATE(CK_KER_ETH1, "ck_ker_eth1ptp", IDX_FLEXGEN_56, 0, GATE_ETH1, SEC_RIFSC(60)), + STM32_GATE(CK_ETH1_MAC, "ck_ker_eth1mac", IDX_ICN_LS_MCU, 0, GATE_ETH1MAC, + SEC_RIFSC(60)), + STM32_GATE(CK_ETH1_TX, "ck_ker_eth1tx", IDX_ICN_LS_MCU, 0, GATE_ETH1TX, SEC_RIFSC(60)), + STM32_GATE(CK_ETH1_RX, "ck_ker_eth1rx", IDX_ICN_LS_MCU, 0, GATE_ETH1RX, SEC_RIFSC(60)), + + STM32_GATE(CK_BUS_ETH2, "ck_icn_p_eth2", IDX_ICN_LS_MCU, 0, GATE_ETH2, SEC_RIFSC(61)), + STM32_GATE(CK_ETH2_STP, "ck_ker_eth2stp", IDX_ICN_LS_MCU, 0, GATE_ETH2STP, + SEC_RIFSC(61)), + STM32_GATE(CK_KER_ETH2, "ck_ker_eth2", IDX_FLEXGEN_54, 0, GATE_ETH2, SEC_RIFSC(61)), + STM32_GATE(CK_KER_ETH2, "ck_ker_eth2ptp", IDX_FLEXGEN_56, 0, GATE_ETH2, SEC_RIFSC(61)), + STM32_GATE(CK_ETH2_MAC, "ck_ker_eth2mac", IDX_ICN_LS_MCU, 0, GATE_ETH2MAC, + SEC_RIFSC(61)), + STM32_GATE(CK_ETH2_TX, "ck_ker_eth2tx", IDX_ICN_LS_MCU, 0, GATE_ETH2TX, SEC_RIFSC(61)), + STM32_GATE(CK_ETH2_RX, "ck_ker_eth2rx", IDX_ICN_LS_MCU, 0, GATE_ETH2RX, SEC_RIFSC(61)), + + /* FDCAN */ + STM32_GATE(CK_BUS_FDCAN, "ck_icn_p_fdcan", IDX_ICN_APB2, 0, GATE_FDCAN, SEC_RIFSC(56)), + STM32_GATE(CK_KER_FDCAN, "ck_ker_fdcan", IDX_FLEXGEN_26, 0, GATE_FDCAN, SEC_RIFSC(56)), + + /* HASH */ + STM32_GATE(CK_BUS_HASH1, "ck_icn_p_hash1", IDX_ICN_LS_MCU, 0, GATE_HASH1, SEC_RIFSC(96)), + STM32_GATE(CK_BUS_HASH2, "ck_icn_p_hash2", IDX_ICN_LS_MCU, 0, GATE_HASH2, SEC_RIFSC(97)), + + /* HDP */ + STM32_GATE(CK_BUS_HDP, "ck_icn_p_hdp", IDX_ICN_APB3, 0, GATE_HDP, SEC_RIFSC(57)), + + /* I2C */ + STM32_GATE(CK_KER_I2C1, "ck_ker_i2c1", IDX_FLEXGEN_13, 0, GATE_I2C1, SEC_RIFSC(41)), + STM32_GATE(CK_KER_I2C2, "ck_ker_i2c2", IDX_FLEXGEN_13, 0, GATE_I2C2, SEC_RIFSC(42)), + STM32_GATE(CK_KER_I2C3, "ck_ker_i2c3", IDX_FLEXGEN_38, 0, GATE_I2C3, SEC_RIFSC(43)), + + /* I3C */ + STM32_GATE(CK_KER_I3C1, "ck_ker_i3c1", IDX_FLEXGEN_14, 0, GATE_I3C1, SEC_RIFSC(114)), + STM32_GATE(CK_KER_I3C2, "ck_ker_i3c2", IDX_FLEXGEN_14, 0, GATE_I3C2, SEC_RIFSC(115)), + STM32_GATE(CK_KER_I3C3, "ck_ker_i3c3", IDX_FLEXGEN_36, 0, GATE_I3C3, SEC_RIFSC(116)), + + /* IWDG */ + STM32_GATE(CK_BUS_IWDG1, "ck_icn_p_iwdg1", IDX_ICN_APB3, 0, GATE_IWDG1, SEC_RIFSC(100)), + STM32_GATE(CK_BUS_IWDG2, "ck_icn_p_iwdg2", IDX_ICN_APB3, 0, GATE_IWDG2, SEC_RIFSC(101)), + STM32_GATE(CK_BUS_IWDG3, "ck_icn_p_iwdg3", IDX_ICN_APB3, 0, GATE_IWDG3, SEC_RIFSC(102)), + STM32_GATE(CK_BUS_IWDG4, "ck_icn_p_iwdg4", IDX_ICN_APB3, 0, GATE_IWDG4, SEC_RIFSC(103)), + + /* LPTIM */ + STM32_GATE(CK_KER_LPTIM1, "ck_ker_lptim1", IDX_FLEXGEN_07, 0, GATE_LPTIM1, + SEC_RIFSC(17)), + STM32_GATE(CK_KER_LPTIM2, "ck_ker_lptim2", IDX_FLEXGEN_07, 0, GATE_LPTIM2, + SEC_RIFSC(18)), + STM32_GATE(CK_KER_LPTIM3, "ck_ker_lptim3", IDX_FLEXGEN_40, 0, GATE_LPTIM3, + SEC_RIFSC(19)), + STM32_GATE(CK_KER_LPTIM4, "ck_ker_lptim4", IDX_FLEXGEN_41, 0, GATE_LPTIM4, + SEC_RIFSC(20)), + STM32_GATE(CK_KER_LPTIM5, "ck_ker_lptim5", IDX_FLEXGEN_42, 0, GATE_LPTIM5, + SEC_RIFSC(21)), + + /* LPUART */ + STM32_GATE(CK_KER_LPUART1, "ck_ker_lpuart1", IDX_FLEXGEN_39, 0, GATE_LPUART1, + SEC_RIFSC(40)), + + /* MCO1 & MCO2 */ + STM32_COMPOSITE_NODIV(CK_MCO1, "ck_mco1", 0, SEC_RIFRCC(MCO1), GATE_MCO1, MUX_MCO1), + STM32_COMPOSITE_NODIV(CK_MCO2, "ck_mco2", 0, SEC_RIFRCC(MCO2), GATE_MCO2, MUX_MCO2), + + /* MDF */ + STM32_GATE(CK_KER_MDF1, "ck_ker_mdf1", IDX_FLEXGEN_21, 0, GATE_MDF1, SEC_RIFSC(54)), + + /* PKA */ + STM32_GATE(CK_BUS_PKA, "ck_icn_p_pka", IDX_ICN_LS_MCU, 0, GATE_PKA, SEC_RIFSC(94)), + + /* RNG */ + STM32_GATE(CK_BUS_RNG1, "ck_icn_p_rng1", IDX_ICN_LS_MCU, CLK_IGNORE_UNUSED, GATE_RNG1, + SEC_RIFSC(92)), + STM32_GATE(CK_BUS_RNG2, "ck_icn_p_rng2", IDX_ICN_LS_MCU, CLK_IGNORE_UNUSED, GATE_RNG2, + SEC_RIFSC(93)), + + /* SAES */ + STM32_GATE(CK_BUS_SAES, "ck_icn_p_saes", IDX_ICN_LS_MCU, 0, GATE_SAES, SEC_RIFSC(95)), + + /* SAI [1..4] */ + STM32_GATE(CK_BUS_SAI1, "ck_icn_p_sai1", IDX_ICN_APB2, 0, GATE_SAI1, SEC_RIFSC(49)), + STM32_GATE(CK_BUS_SAI2, "ck_icn_p_sai2", IDX_ICN_APB2, 0, GATE_SAI2, SEC_RIFSC(50)), + STM32_GATE(CK_BUS_SAI3, "ck_icn_p_sai3", IDX_ICN_APB2, 0, GATE_SAI3, SEC_RIFSC(51)), + STM32_GATE(CK_BUS_SAI4, "ck_icn_p_sai4", IDX_ICN_APB2, 0, GATE_SAI4, SEC_RIFSC(52)), + STM32_GATE(CK_KER_SAI1, "ck_ker_sai1", IDX_FLEXGEN_22, 0, GATE_SAI1, SEC_RIFSC(49)), + STM32_GATE(CK_KER_SAI2, "ck_ker_sai2", IDX_FLEXGEN_23, 0, GATE_SAI2, SEC_RIFSC(50)), + STM32_GATE(CK_KER_SAI3, "ck_ker_sai3", IDX_FLEXGEN_24, 0, GATE_SAI3, SEC_RIFSC(51)), + STM32_GATE(CK_KER_SAI4, "ck_ker_sai4", IDX_FLEXGEN_25, 0, GATE_SAI4, SEC_RIFSC(52)), + + /* SDMMC */ + STM32_GATE(CK_KER_SDMMC1, "ck_ker_sdmmc1", IDX_FLEXGEN_51, 0, GATE_SDMMC1, + SEC_RIFSC(76)), + STM32_GATE(CK_KER_SDMMC2, "ck_ker_sdmmc2", IDX_FLEXGEN_52, 0, GATE_SDMMC2, + SEC_RIFSC(77)), + STM32_GATE(CK_KER_SDMMC3, "ck_ker_sdmmc3", IDX_FLEXGEN_53, 0, GATE_SDMMC3, + SEC_RIFSC(78)), + + /* SERC */ + STM32_GATE(CK_BUS_SERC, "ck_icn_p_serc", IDX_ICN_APB3, 0, GATE_SERC, SEC_RIFSC(110)), + + /* SPDIF */ + STM32_GATE(CK_KER_SPDIFRX, "ck_ker_spdifrx", IDX_FLEXGEN_12, 0, GATE_SPDIFRX, + SEC_RIFSC(30)), + + /* SPI */ + STM32_GATE(CK_KER_SPI1, "ck_ker_spi1", IDX_FLEXGEN_16, 0, GATE_SPI1, SEC_RIFSC(22)), + STM32_GATE(CK_KER_SPI2, "ck_ker_spi2", IDX_FLEXGEN_10, 0, GATE_SPI2, SEC_RIFSC(23)), + STM32_GATE(CK_KER_SPI3, "ck_ker_spi3", IDX_FLEXGEN_11, 0, GATE_SPI3, SEC_RIFSC(24)), + STM32_GATE(CK_KER_SPI4, "ck_ker_spi4", IDX_FLEXGEN_17, 0, GATE_SPI4, SEC_RIFSC(25)), + STM32_GATE(CK_KER_SPI5, "ck_ker_spi5", IDX_FLEXGEN_17, 0, GATE_SPI5, SEC_RIFSC(26)), + STM32_GATE(CK_KER_SPI6, "ck_ker_spi6", IDX_FLEXGEN_37, 0, GATE_SPI6, SEC_RIFSC(27)), + + /* STGEN */ + STM32_GATE(CK_KER_STGEN, "ck_ker_stgen", IDX_FLEXGEN_33, CLK_IGNORE_UNUSED, GATE_STGEN, + SEC_RIFSC(73)), + + /* Timers */ + STM32_GATE(CK_KER_TIM2, "ck_ker_tim2", IDX_TIMG1, 0, GATE_TIM2, SEC_RIFSC(1)), + STM32_GATE(CK_KER_TIM3, "ck_ker_tim3", IDX_TIMG1, 0, GATE_TIM3, SEC_RIFSC(2)), + STM32_GATE(CK_KER_TIM4, "ck_ker_tim4", IDX_TIMG1, 0, GATE_TIM4, SEC_RIFSC(3)), + STM32_GATE(CK_KER_TIM5, "ck_ker_tim5", IDX_TIMG1, 0, GATE_TIM5, SEC_RIFSC(4)), + STM32_GATE(CK_KER_TIM6, "ck_ker_tim6", IDX_TIMG1, 0, GATE_TIM6, SEC_RIFSC(5)), + STM32_GATE(CK_KER_TIM7, "ck_ker_tim7", IDX_TIMG1, 0, GATE_TIM7, SEC_RIFSC(6)), + STM32_GATE(CK_KER_TIM10, "ck_ker_tim10", IDX_TIMG1, 0, GATE_TIM10, SEC_RIFSC(8)), + STM32_GATE(CK_KER_TIM11, "ck_ker_tim11", IDX_TIMG1, 0, GATE_TIM11, SEC_RIFSC(9)), + STM32_GATE(CK_KER_TIM12, "ck_ker_tim12", IDX_TIMG1, 0, GATE_TIM12, SEC_RIFSC(10)), + STM32_GATE(CK_KER_TIM13, "ck_ker_tim13", IDX_TIMG1, 0, GATE_TIM13, SEC_RIFSC(11)), + STM32_GATE(CK_KER_TIM14, "ck_ker_tim14", IDX_TIMG1, 0, GATE_TIM14, SEC_RIFSC(12)), + + STM32_GATE(CK_KER_TIM1, "ck_ker_tim1", IDX_TIMG2, 0, GATE_TIM1, SEC_RIFSC(0)), + STM32_GATE(CK_KER_TIM8, "ck_ker_tim8", IDX_TIMG2, 0, GATE_TIM8, SEC_RIFSC(7)), + STM32_GATE(CK_KER_TIM15, "ck_ker_tim15", IDX_TIMG2, 0, GATE_TIM15, SEC_RIFSC(13)), + STM32_GATE(CK_KER_TIM16, "ck_ker_tim16", IDX_TIMG2, 0, GATE_TIM16, SEC_RIFSC(14)), + STM32_GATE(CK_KER_TIM17, "ck_ker_tim17", IDX_TIMG2, 0, GATE_TIM17, SEC_RIFSC(15)), + + /* UART/USART */ + STM32_GATE(CK_KER_USART2, "ck_ker_usart2", IDX_FLEXGEN_08, 0, GATE_USART2, + SEC_RIFSC(32)), + STM32_GATE(CK_KER_UART4, "ck_ker_uart4", IDX_FLEXGEN_08, 0, GATE_UART4, + SEC_RIFSC(34)), + STM32_GATE(CK_KER_USART3, "ck_ker_usart3", IDX_FLEXGEN_09, 0, GATE_USART3, + SEC_RIFSC(33)), + STM32_GATE(CK_KER_UART5, "ck_ker_uart5", IDX_FLEXGEN_09, 0, GATE_UART5, + SEC_RIFSC(35)), + STM32_GATE(CK_KER_USART1, "ck_ker_usart1", IDX_FLEXGEN_18, 0, GATE_USART1, + SEC_RIFSC(31)), + STM32_GATE(CK_KER_USART6, "ck_ker_usart6", IDX_FLEXGEN_19, 0, GATE_USART6, + SEC_RIFSC(36)), + STM32_GATE(CK_KER_UART7, "ck_ker_uart7", IDX_FLEXGEN_20, 0, GATE_UART7, + SEC_RIFSC(37)), + + /* USB2PHY1 */ + STM32_COMPOSITE_NODIV(CK_KER_USB2PHY1, "ck_ker_usb2phy1", 0, SEC_RIFSC(63), + GATE_USB2PHY1, MUX_USB2PHY1), + + /* USB2H */ + STM32_GATE(CK_BUS_USBHOHCI, "ck_icn_m_usbhohci", IDX_ICN_HSL, 0, GATE_USBH, + SEC_RIFSC(63)), + STM32_GATE(CK_BUS_USBHEHCI, "ck_icn_m_usbhehci", IDX_ICN_HSL, 0, GATE_USBH, + SEC_RIFSC(63)), + + /* USBOTG */ + STM32_GATE(CK_BUS_OTG, "ck_icn_m_otg", IDX_ICN_HSL, 0, GATE_USBOTG, + SEC_RIFSC(66)), + + /* USB2PHY2 */ + STM32_COMPOSITE_NODIV(CK_KER_USB2PHY2EN, "ck_ker_usb2phy2_en", 0, SEC_RIFSC(66), + GATE_USB2PHY2, MUX_USB2PHY2), + + /* VREF */ + STM32_GATE(CK_BUS_VREF, "ck_icn_p_vref", IDX_ICN_APB3, 0, RCC_VREFCFGR, + SEC_RIFSC(106)), + + /* WWDG */ + STM32_GATE(CK_BUS_WWDG1, "ck_icn_p_wwdg1", IDX_ICN_APB3, 0, GATE_WWDG1, + SEC_RIFSC(104)), +}; + +static const struct stm32_clock_match_data stm32mp21_data = { + .tab_clocks = stm32mp21_clock_cfg, + .num_clocks = ARRAY_SIZE(stm32mp21_clock_cfg), + .clock_data = &(const struct clk_stm32_clock_data) { + .num_gates = ARRAY_SIZE(stm32mp21_gates), + .gates = stm32mp21_gates, + .muxes = stm32mp21_muxes, + }, + .check_security = stm32mp21_check_security, + +}; + +static int stm32mp21_clk_probe(struct udevice *dev) +{ + fdt_addr_t base = dev_read_addr(dev->parent); + struct udevice *scmi; + + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + /* force SCMI probe to register all SCMI clocks */ + uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(scmi_clock), &scmi); + + stm32_rcc_init(dev, &stm32mp21_data); + + return 0; +} + +U_BOOT_DRIVER(stm32mp21_clock) = { + .name = "stm32mp21_clk", + .id = UCLASS_CLK, + .ops = &stm32_clk_ops, + .priv_auto = sizeof(struct stm32mp_rcc_priv), + .probe = stm32mp21_clk_probe, +}; diff --git a/include/stm32mp21_rcc.h b/include/stm32mp21_rcc.h new file mode 100644 index 00000000000..73863412720 --- /dev/null +++ b/include/stm32mp21_rcc.h @@ -0,0 +1,651 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef STM32MP21_RCC_H +#define STM32MP21_RCC_H + +#define RCC_SECCFGR0 0x0 +#define RCC_SECCFGR1 0x4 +#define RCC_SECCFGR2 0x8 +#define RCC_SECCFGR3 0xC +#define RCC_PRIVCFGR0 0x10 +#define RCC_PRIVCFGR1 0x14 +#define RCC_PRIVCFGR2 0x18 +#define RCC_PRIVCFGR3 0x1C +#define RCC_RCFGLOCKR0 0x20 +#define RCC_RCFGLOCKR1 0x24 +#define RCC_RCFGLOCKR2 0x28 +#define RCC_RCFGLOCKR3 0x2C +#define RCC_R0CIDCFGR 0x30 +#define RCC_R0SEMCR 0x34 +#define RCC_R1CIDCFGR 0x38 +#define RCC_R1SEMCR 0x3C +#define RCC_R2CIDCFGR 0x40 +#define RCC_R2SEMCR 0x44 +#define RCC_R3CIDCFGR 0x48 +#define RCC_R3SEMCR 0x4C +#define RCC_R4CIDCFGR 0x50 +#define RCC_R4SEMCR 0x54 +#define RCC_R5CIDCFGR 0x58 +#define RCC_R5SEMCR 0x5C +#define RCC_R6CIDCFGR 0x60 +#define RCC_R6SEMCR 0x64 +#define RCC_R7CIDCFGR 0x68 +#define RCC_R7SEMCR 0x6C +#define RCC_R8CIDCFGR 0x70 +#define RCC_R8SEMCR 0x74 +#define RCC_R9CIDCFGR 0x78 +#define RCC_R9SEMCR 0x7C +#define RCC_R10CIDCFGR 0x80 +#define RCC_R10SEMCR 0x84 +#define RCC_R11CIDCFGR 0x88 +#define RCC_R11SEMCR 0x8C +#define RCC_R12CIDCFGR 0x90 +#define RCC_R12SEMCR 0x94 +#define RCC_R13CIDCFGR 0x98 +#define RCC_R13SEMCR 0x9C +#define RCC_R14CIDCFGR 0xA0 +#define RCC_R14SEMCR 0xA4 +#define RCC_R15CIDCFGR 0xA8 +#define RCC_R15SEMCR 0xAC +#define RCC_R16CIDCFGR 0xB0 +#define RCC_R16SEMCR 0xB4 +#define RCC_R17CIDCFGR 0xB8 +#define RCC_R17SEMCR 0xBC +#define RCC_R18CIDCFGR 0xC0 +#define RCC_R18SEMCR 0xC4 +#define RCC_R19CIDCFGR 0xC8 +#define RCC_R19SEMCR 0xCC +#define RCC_R20CIDCFGR 0xD0 +#define RCC_R20SEMCR 0xD4 +#define RCC_R21CIDCFGR 0xD8 +#define RCC_R21SEMCR 0xDC +#define RCC_R22CIDCFGR 0xE0 +#define RCC_R22SEMCR 0xE4 +#define RCC_R23CIDCFGR 0xE8 +#define RCC_R23SEMCR 0xEC +#define RCC_R24CIDCFGR 0xF0 +#define RCC_R24SEMCR 0xF4 +#define RCC_R25CIDCFGR 0xF8 +#define RCC_R25SEMCR 0xFC +#define RCC_R26CIDCFGR 0x100 +#define RCC_R26SEMCR 0x104 +#define RCC_R27CIDCFGR 0x108 +#define RCC_R27SEMCR 0x10C +#define RCC_R28CIDCFGR 0x110 +#define RCC_R28SEMCR 0x114 +#define RCC_R29CIDCFGR 0x118 +#define RCC_R29SEMCR 0x11C +#define RCC_R30CIDCFGR 0x120 +#define RCC_R30SEMCR 0x124 +#define RCC_R31CIDCFGR 0x128 +#define RCC_R31SEMCR 0x12C +#define RCC_R32CIDCFGR 0x130 +#define RCC_R32SEMCR 0x134 +#define RCC_R33CIDCFGR 0x138 +#define RCC_R33SEMCR 0x13C +#define RCC_R34CIDCFGR 0x140 +#define RCC_R34SEMCR 0x144 +#define RCC_R35CIDCFGR 0x148 +#define RCC_R35SEMCR 0x14C +#define RCC_R36CIDCFGR 0x150 +#define RCC_R36SEMCR 0x154 +#define RCC_R37CIDCFGR 0x158 +#define RCC_R37SEMCR 0x15C +#define RCC_R38CIDCFGR 0x160 +#define RCC_R38SEMCR 0x164 +#define RCC_R39CIDCFGR 0x168 +#define RCC_R39SEMCR 0x16C +#define RCC_R40CIDCFGR 0x170 +#define RCC_R40SEMCR 0x174 +#define RCC_R41CIDCFGR 0x178 +#define RCC_R41SEMCR 0x17C +#define RCC_R42CIDCFGR 0x180 +#define RCC_R42SEMCR 0x184 +#define RCC_R43CIDCFGR 0x188 +#define RCC_R43SEMCR 0x18C +#define RCC_R44CIDCFGR 0x190 +#define RCC_R44SEMCR 0x194 +#define RCC_R45CIDCFGR 0x198 +#define RCC_R45SEMCR 0x19C +#define RCC_R46CIDCFGR 0x1A0 +#define RCC_R46SEMCR 0x1A4 +#define RCC_R47CIDCFGR 0x1A8 +#define RCC_R47SEMCR 0x1AC +#define RCC_R48CIDCFGR 0x1B0 +#define RCC_R48SEMCR 0x1B4 +#define RCC_R49CIDCFGR 0x1B8 +#define RCC_R49SEMCR 0x1BC +#define RCC_R50CIDCFGR 0x1C0 +#define RCC_R50SEMCR 0x1C4 +#define RCC_R51CIDCFGR 0x1C8 +#define RCC_R51SEMCR 0x1CC +#define RCC_R52CIDCFGR 0x1D0 +#define RCC_R52SEMCR 0x1D4 +#define RCC_R53CIDCFGR 0x1D8 +#define RCC_R53SEMCR 0x1DC +#define RCC_R54CIDCFGR 0x1E0 +#define RCC_R54SEMCR 0x1E4 +#define RCC_R55CIDCFGR 0x1E8 +#define RCC_R55SEMCR 0x1EC +#define RCC_R56CIDCFGR 0x1F0 +#define RCC_R56SEMCR 0x1F4 +#define RCC_R57CIDCFGR 0x1F8 +#define RCC_R57SEMCR 0x1FC +#define RCC_R58CIDCFGR 0x200 +#define RCC_R58SEMCR 0x204 +#define RCC_R59CIDCFGR 0x208 +#define RCC_R59SEMCR 0x20C +#define RCC_R60CIDCFGR 0x210 +#define RCC_R60SEMCR 0x214 +#define RCC_R61CIDCFGR 0x218 +#define RCC_R61SEMCR 0x21C +#define RCC_R62CIDCFGR 0x220 +#define RCC_R62SEMCR 0x224 +#define RCC_R63CIDCFGR 0x228 +#define RCC_R63SEMCR 0x22C +#define RCC_R64CIDCFGR 0x230 +#define RCC_R64SEMCR 0x234 +#define RCC_R65CIDCFGR 0x238 +#define RCC_R65SEMCR 0x23C +#define RCC_R66CIDCFGR 0x240 +#define RCC_R66SEMCR 0x244 +#define RCC_R67CIDCFGR 0x248 +#define RCC_R67SEMCR 0x24C +#define RCC_R68CIDCFGR 0x250 +#define RCC_R68SEMCR 0x254 +#define RCC_R69CIDCFGR 0x258 +#define RCC_R69SEMCR 0x25C +#define RCC_R70CIDCFGR 0x260 +#define RCC_R70SEMCR 0x264 +#define RCC_R71CIDCFGR 0x268 +#define RCC_R71SEMCR 0x26C +#define RCC_R73CIDCFGR 0x278 +#define RCC_R73SEMCR 0x27C +#define RCC_R74CIDCFGR 0x280 +#define RCC_R74SEMCR 0x284 +#define RCC_R75CIDCFGR 0x288 +#define RCC_R75SEMCR 0x28C +#define RCC_R76CIDCFGR 0x290 +#define RCC_R76SEMCR 0x294 +#define RCC_R77CIDCFGR 0x298 +#define RCC_R77SEMCR 0x29C +#define RCC_R78CIDCFGR 0x2A0 +#define RCC_R78SEMCR 0x2A4 +#define RCC_R79CIDCFGR 0x2A8 +#define RCC_R79SEMCR 0x2AC +#define RCC_R83CIDCFGR 0x2C8 +#define RCC_R83SEMCR 0x2CC +#define RCC_R84CIDCFGR 0x2D0 +#define RCC_R84SEMCR 0x2D4 +#define RCC_R85CIDCFGR 0x2D8 +#define RCC_R85SEMCR 0x2DC +#define RCC_R86CIDCFGR 0x2E0 +#define RCC_R86SEMCR 0x2E4 +#define RCC_R87CIDCFGR 0x2E8 +#define RCC_R87SEMCR 0x2EC +#define RCC_R88CIDCFGR 0x2F0 +#define RCC_R88SEMCR 0x2F4 +#define RCC_R90CIDCFGR 0x300 +#define RCC_R90SEMCR 0x304 +#define RCC_R91CIDCFGR 0x308 +#define RCC_R91SEMCR 0x30C +#define RCC_R92CIDCFGR 0x310 +#define RCC_R92SEMCR 0x314 +#define RCC_R93CIDCFGR 0x318 +#define RCC_R93SEMCR 0x31C +#define RCC_R94CIDCFGR 0x320 +#define RCC_R94SEMCR 0x324 +#define RCC_R95CIDCFGR 0x328 +#define RCC_R95SEMCR 0x32C +#define RCC_R96CIDCFGR 0x330 +#define RCC_R96SEMCR 0x334 +#define RCC_R97CIDCFGR 0x338 +#define RCC_R97SEMCR 0x33C +#define RCC_R98CIDCFGR 0x340 +#define RCC_R98SEMCR 0x344 +#define RCC_R101CIDCFGR 0x358 +#define RCC_R101SEMCR 0x35C +#define RCC_R102CIDCFGR 0x360 +#define RCC_R102SEMCR 0x364 +#define RCC_R103CIDCFGR 0x368 +#define RCC_R103SEMCR 0x36C +#define RCC_R104CIDCFGR 0x370 +#define RCC_R104SEMCR 0x374 +#define RCC_R105CIDCFGR 0x378 +#define RCC_R105SEMCR 0x37C +#define RCC_R106CIDCFGR 0x380 +#define RCC_R106SEMCR 0x384 +#define RCC_R108CIDCFGR 0x390 +#define RCC_R108SEMCR 0x394 +#define RCC_R109CIDCFGR 0x398 +#define RCC_R109SEMCR 0x39C +#define RCC_R110CIDCFGR 0x3A0 +#define RCC_R110SEMCR 0x3A4 +#define RCC_R111CIDCFGR 0x3A8 +#define RCC_R111SEMCR 0x3AC +#define RCC_R112CIDCFGR 0x3B0 +#define RCC_R112SEMCR 0x3B4 +#define RCC_R113CIDCFGR 0x3B8 +#define RCC_R113SEMCR 0x3BC +#define RCC_GRSTCSETR 0x400 +#define RCC_C1RSTCSETR 0x404 +#define RCC_C2RSTCSETR 0x40C +#define RCC_HWRSTSCLRR 0x410 +#define RCC_C1HWRSTSCLRR 0x414 +#define RCC_C2HWRSTSCLRR 0x418 +#define RCC_C1BOOTRSTSSETR 0x41C +#define RCC_C1BOOTRSTSCLRR 0x420 +#define RCC_C2BOOTRSTSSETR 0x424 +#define RCC_C2BOOTRSTSCLRR 0x428 +#define RCC_C1SREQSETR 0x42C +#define RCC_C1SREQCLRR 0x430 +#define RCC_CPUBOOTCR 0x434 +#define RCC_STBYBOOTCR 0x438 +#define RCC_LEGBOOTCR 0x43C +#define RCC_BDCR 0x440 +#define RCC_RDCR 0x44C +#define RCC_C1MSRDCR 0x450 +#define RCC_PWRLPDLYCR 0x454 +#define RCC_C1CIESETR 0x458 +#define RCC_C1CIFCLRR 0x45C +#define RCC_C2CIESETR 0x460 +#define RCC_C2CIFCLRR 0x464 +#define RCC_IWDGC1FZSETR 0x468 +#define RCC_IWDGC1FZCLRR 0x46C +#define RCC_IWDGC1CFGSETR 0x470 +#define RCC_IWDGC1CFGCLRR 0x474 +#define RCC_IWDGC2FZSETR 0x478 +#define RCC_IWDGC2FZCLRR 0x47C +#define RCC_IWDGC2CFGSETR 0x480 +#define RCC_IWDGC2CFGCLRR 0x484 +#define RCC_MCO1CFGR 0x488 +#define RCC_MCO2CFGR 0x48C +#define RCC_OCENSETR 0x490 +#define RCC_OCENCLRR 0x494 +#define RCC_OCRDYR 0x498 +#define RCC_HSICFGR 0x49C +#define RCC_MSICFGR 0x4A0 +#define RCC_LSICR 0x4A4 +#define RCC_RTCDIVR 0x4A8 +#define RCC_APB1DIVR 0x4AC +#define RCC_APB2DIVR 0x4B0 +#define RCC_APB3DIVR 0x4B4 +#define RCC_APB4DIVR 0x4B8 +#define RCC_APB5DIVR 0x4BC +#define RCC_APBDBGDIVR 0x4C0 +#define RCC_TIMG1PRER 0x4C8 +#define RCC_TIMG2PRER 0x4CC +#define RCC_LSMCUDIVR 0x4D0 +#define RCC_DDRCPCFGR 0x4D4 +#define RCC_DDRCAPBCFGR 0x4D8 +#define RCC_DDRPHYCAPBCFGR 0x4DC +#define RCC_DDRPHYCCFGR 0x4E0 +#define RCC_DDRCFGR 0x4E4 +#define RCC_DDRITFCFGR 0x4E8 +#define RCC_SYSRAMCFGR 0x4F0 +#define RCC_SRAM1CFGR 0x4F8 +#define RCC_RETRAMCFGR 0x500 +#define RCC_BKPSRAMCFGR 0x504 +#define RCC_OSPI1CFGR 0x514 +#define RCC_FMCCFGR 0x51C +#define RCC_DBGCFGR 0x520 +#define RCC_STMCFGR 0x524 +#define RCC_ETRCFGR 0x528 +#define RCC_GPIOACFGR 0x52C +#define RCC_GPIOBCFGR 0x530 +#define RCC_GPIOCCFGR 0x534 +#define RCC_GPIODCFGR 0x538 +#define RCC_GPIOECFGR 0x53C +#define RCC_GPIOFCFGR 0x540 +#define RCC_GPIOGCFGR 0x544 +#define RCC_GPIOHCFGR 0x548 +#define RCC_GPIOICFGR 0x54C +#define RCC_GPIOZCFGR 0x558 +#define RCC_HPDMA1CFGR 0x55C +#define RCC_HPDMA2CFGR 0x560 +#define RCC_HPDMA3CFGR 0x564 +#define RCC_IPCC1CFGR 0x570 +#define RCC_RTCCFGR 0x578 +#define RCC_SYSCPU1CFGR 0x580 +#define RCC_BSECCFGR 0x584 +#define RCC_PLL2CFGR1 0x590 +#define RCC_PLL2CFGR2 0x594 +#define RCC_PLL2CFGR3 0x598 +#define RCC_PLL2CFGR4 0x59C +#define RCC_PLL2CFGR5 0x5A0 +#define RCC_PLL2CFGR6 0x5A8 +#define RCC_PLL2CFGR7 0x5AC +#define RCC_HSIFMONCR 0x5E0 +#define RCC_HSIFVALR 0x5E4 +#define RCC_MSIFMONCR 0x5E8 +#define RCC_MSIFVALR 0x5EC +#define RCC_TIM1CFGR 0x700 +#define RCC_TIM2CFGR 0x704 +#define RCC_TIM3CFGR 0x708 +#define RCC_TIM4CFGR 0x70C +#define RCC_TIM5CFGR 0x710 +#define RCC_TIM6CFGR 0x714 +#define RCC_TIM7CFGR 0x718 +#define RCC_TIM8CFGR 0x71C +#define RCC_TIM10CFGR 0x720 +#define RCC_TIM11CFGR 0x724 +#define RCC_TIM12CFGR 0x728 +#define RCC_TIM13CFGR 0x72C +#define RCC_TIM14CFGR 0x730 +#define RCC_TIM15CFGR 0x734 +#define RCC_TIM16CFGR 0x738 +#define RCC_TIM17CFGR 0x73C +#define RCC_LPTIM1CFGR 0x744 +#define RCC_LPTIM2CFGR 0x748 +#define RCC_LPTIM3CFGR 0x74C +#define RCC_LPTIM4CFGR 0x750 +#define RCC_LPTIM5CFGR 0x754 +#define RCC_SPI1CFGR 0x758 +#define RCC_SPI2CFGR 0x75C +#define RCC_SPI3CFGR 0x760 +#define RCC_SPI4CFGR 0x764 +#define RCC_SPI5CFGR 0x768 +#define RCC_SPI6CFGR 0x76C +#define RCC_SPDIFRXCFGR 0x778 +#define RCC_USART1CFGR 0x77C +#define RCC_USART2CFGR 0x780 +#define RCC_USART3CFGR 0x784 +#define RCC_UART4CFGR 0x788 +#define RCC_UART5CFGR 0x78C +#define RCC_USART6CFGR 0x790 +#define RCC_UART7CFGR 0x794 +#define RCC_LPUART1CFGR 0x7A0 +#define RCC_I2C1CFGR 0x7A4 +#define RCC_I2C2CFGR 0x7A8 +#define RCC_I2C3CFGR 0x7AC +#define RCC_SAI1CFGR 0x7C4 +#define RCC_SAI2CFGR 0x7C8 +#define RCC_SAI3CFGR 0x7CC +#define RCC_SAI4CFGR 0x7D0 +#define RCC_MDF1CFGR 0x7D8 +#define RCC_FDCANCFGR 0x7E0 +#define RCC_HDPCFGR 0x7E4 +#define RCC_ADC1CFGR 0x7E8 +#define RCC_ADC2CFGR 0x7EC +#define RCC_ETH1CFGR 0x7F0 +#define RCC_ETH2CFGR 0x7F4 +#define RCC_USBHCFGR 0x7FC +#define RCC_USB2PHY1CFGR 0x800 +#define RCC_OTGCFGR 0x808 +#define RCC_USB2PHY2CFGR 0x80C +#define RCC_STGENCFGR 0x824 +#define RCC_SDMMC1CFGR 0x830 +#define RCC_SDMMC2CFGR 0x834 +#define RCC_SDMMC3CFGR 0x838 +#define RCC_LTDCCFGR 0x840 +#define RCC_CSICFGR 0x858 +#define RCC_DCMIPPCFGR 0x85C +#define RCC_DCMIPSSICFGR 0x860 +#define RCC_RNG1CFGR 0x870 +#define RCC_RNG2CFGR 0x874 +#define RCC_PKACFGR 0x878 +#define RCC_SAESCFGR 0x87C +#define RCC_HASH1CFGR 0x880 +#define RCC_HASH2CFGR 0x884 +#define RCC_CRYP1CFGR 0x888 +#define RCC_CRYP2CFGR 0x88C +#define RCC_IWDG1CFGR 0x894 +#define RCC_IWDG2CFGR 0x898 +#define RCC_IWDG3CFGR 0x89C +#define RCC_IWDG4CFGR 0x8A0 +#define RCC_WWDG1CFGR 0x8A4 +#define RCC_VREFCFGR 0x8AC +#define RCC_DTSCFGR 0x8B0 +#define RCC_CRCCFGR 0x8B4 +#define RCC_SERCCFGR 0x8B8 +#define RCC_DDRPERFMCFGR 0x8C0 +#define RCC_I3C1CFGR 0x8C8 +#define RCC_I3C2CFGR 0x8CC +#define RCC_I3C3CFGR 0x8D0 +#define RCC_MUXSELCFGR 0x1000 +#define RCC_XBAR0CFGR 0x1018 +#define RCC_XBAR1CFGR 0x101C +#define RCC_XBAR2CFGR 0x1020 +#define RCC_XBAR3CFGR 0x1024 +#define RCC_XBAR4CFGR 0x1028 +#define RCC_XBAR5CFGR 0x102C +#define RCC_XBAR6CFGR 0x1030 +#define RCC_XBAR7CFGR 0x1034 +#define RCC_XBAR8CFGR 0x1038 +#define RCC_XBAR9CFGR 0x103C +#define RCC_XBAR10CFGR 0x1040 +#define RCC_XBAR11CFGR 0x1044 +#define RCC_XBAR12CFGR 0x1048 +#define RCC_XBAR13CFGR 0x104C +#define RCC_XBAR14CFGR 0x1050 +#define RCC_XBAR15CFGR 0x1054 +#define RCC_XBAR16CFGR 0x1058 +#define RCC_XBAR17CFGR 0x105C +#define RCC_XBAR18CFGR 0x1060 +#define RCC_XBAR19CFGR 0x1064 +#define RCC_XBAR20CFGR 0x1068 +#define RCC_XBAR21CFGR 0x106C +#define RCC_XBAR22CFGR 0x1070 +#define RCC_XBAR23CFGR 0x1074 +#define RCC_XBAR24CFGR 0x1078 +#define RCC_XBAR25CFGR 0x107C +#define RCC_XBAR26CFGR 0x1080 +#define RCC_XBAR27CFGR 0x1084 +#define RCC_XBAR28CFGR 0x1088 +#define RCC_XBAR29CFGR 0x108C +#define RCC_XBAR30CFGR 0x1090 +#define RCC_XBAR31CFGR 0x1094 +#define RCC_XBAR32CFGR 0x1098 +#define RCC_XBAR33CFGR 0x109C +#define RCC_XBAR34CFGR 0x10A0 +#define RCC_XBAR35CFGR 0x10A4 +#define RCC_XBAR36CFGR 0x10A8 +#define RCC_XBAR37CFGR 0x10AC +#define RCC_XBAR38CFGR 0x10B0 +#define RCC_XBAR39CFGR 0x10B4 +#define RCC_XBAR40CFGR 0x10B8 +#define RCC_XBAR41CFGR 0x10BC +#define RCC_XBAR42CFGR 0x10C0 +#define RCC_XBAR43CFGR 0x10C4 +#define RCC_XBAR44CFGR 0x10C8 +#define RCC_XBAR45CFGR 0x10CC +#define RCC_XBAR46CFGR 0x10D0 +#define RCC_XBAR47CFGR 0x10D4 +#define RCC_XBAR48CFGR 0x10D8 +#define RCC_XBAR49CFGR 0x10DC +#define RCC_XBAR50CFGR 0x10E0 +#define RCC_XBAR51CFGR 0x10E4 +#define RCC_XBAR52CFGR 0x10E8 +#define RCC_XBAR53CFGR 0x10EC +#define RCC_XBAR54CFGR 0x10F0 +#define RCC_XBAR55CFGR 0x10F4 +#define RCC_XBAR56CFGR 0x10F8 +#define RCC_XBAR57CFGR 0x10FC +#define RCC_XBAR58CFGR 0x1100 +#define RCC_XBAR59CFGR 0x1104 +#define RCC_XBAR60CFGR 0x1108 +#define RCC_XBAR61CFGR 0x110C +#define RCC_XBAR62CFGR 0x1110 +#define RCC_XBAR63CFGR 0x1114 +#define RCC_PREDIV0CFGR 0x1118 +#define RCC_PREDIV1CFGR 0x111C +#define RCC_PREDIV2CFGR 0x1120 +#define RCC_PREDIV3CFGR 0x1124 +#define RCC_PREDIV4CFGR 0x1128 +#define RCC_PREDIV5CFGR 0x112C +#define RCC_PREDIV6CFGR 0x1130 +#define RCC_PREDIV7CFGR 0x1134 +#define RCC_PREDIV8CFGR 0x1138 +#define RCC_PREDIV9CFGR 0x113C +#define RCC_PREDIV10CFGR 0x1140 +#define RCC_PREDIV11CFGR 0x1144 +#define RCC_PREDIV12CFGR 0x1148 +#define RCC_PREDIV13CFGR 0x114C +#define RCC_PREDIV14CFGR 0x1150 +#define RCC_PREDIV15CFGR 0x1154 +#define RCC_PREDIV16CFGR 0x1158 +#define RCC_PREDIV17CFGR 0x115C +#define RCC_PREDIV18CFGR 0x1160 +#define RCC_PREDIV19CFGR 0x1164 +#define RCC_PREDIV20CFGR 0x1168 +#define RCC_PREDIV21CFGR 0x116C +#define RCC_PREDIV22CFGR 0x1170 +#define RCC_PREDIV23CFGR 0x1174 +#define RCC_PREDIV24CFGR 0x1178 +#define RCC_PREDIV25CFGR 0x117C +#define RCC_PREDIV26CFGR 0x1180 +#define RCC_PREDIV27CFGR 0x1184 +#define RCC_PREDIV28CFGR 0x1188 +#define RCC_PREDIV29CFGR 0x118C +#define RCC_PREDIV30CFGR 0x1190 +#define RCC_PREDIV31CFGR 0x1194 +#define RCC_PREDIV32CFGR 0x1198 +#define RCC_PREDIV33CFGR 0x119C +#define RCC_PREDIV34CFGR 0x11A0 +#define RCC_PREDIV35CFGR 0x11A4 +#define RCC_PREDIV36CFGR 0x11A8 +#define RCC_PREDIV37CFGR 0x11AC +#define RCC_PREDIV38CFGR 0x11B0 +#define RCC_PREDIV39CFGR 0x11B4 +#define RCC_PREDIV40CFGR 0x11B8 +#define RCC_PREDIV41CFGR 0x11BC +#define RCC_PREDIV42CFGR 0x11C0 +#define RCC_PREDIV43CFGR 0x11C4 +#define RCC_PREDIV44CFGR 0x11C8 +#define RCC_PREDIV45CFGR 0x11CC +#define RCC_PREDIV46CFGR 0x11D0 +#define RCC_PREDIV47CFGR 0x11D4 +#define RCC_PREDIV48CFGR 0x11D8 +#define RCC_PREDIV49CFGR 0x11DC +#define RCC_PREDIV50CFGR 0x11E0 +#define RCC_PREDIV51CFGR 0x11E4 +#define RCC_PREDIV52CFGR 0x11E8 +#define RCC_PREDIV53CFGR 0x11EC +#define RCC_PREDIV54CFGR 0x11F0 +#define RCC_PREDIV55CFGR 0x11F4 +#define RCC_PREDIV56CFGR 0x11F8 +#define RCC_PREDIV57CFGR 0x11FC +#define RCC_PREDIV58CFGR 0x1200 +#define RCC_PREDIV59CFGR 0x1204 +#define RCC_PREDIV60CFGR 0x1208 +#define RCC_PREDIV61CFGR 0x120C +#define RCC_PREDIV62CFGR 0x1210 +#define RCC_PREDIV63CFGR 0x1214 +#define RCC_PREDIVSR1 0x1218 +#define RCC_PREDIVSR2 0x121C +#define RCC_FINDIV0CFGR 0x1224 +#define RCC_FINDIV1CFGR 0x1228 +#define RCC_FINDIV2CFGR 0x122C +#define RCC_FINDIV3CFGR 0x1230 +#define RCC_FINDIV4CFGR 0x1234 +#define RCC_FINDIV5CFGR 0x1238 +#define RCC_FINDIV6CFGR 0x123C +#define RCC_FINDIV7CFGR 0x1240 +#define RCC_FINDIV8CFGR 0x1244 +#define RCC_FINDIV9CFGR 0x1248 +#define RCC_FINDIV10CFGR 0x124C +#define RCC_FINDIV11CFGR 0x1250 +#define RCC_FINDIV12CFGR 0x1254 +#define RCC_FINDIV13CFGR 0x1258 +#define RCC_FINDIV14CFGR 0x125C +#define RCC_FINDIV15CFGR 0x1260 +#define RCC_FINDIV16CFGR 0x1264 +#define RCC_FINDIV17CFGR 0x1268 +#define RCC_FINDIV18CFGR 0x126C +#define RCC_FINDIV19CFGR 0x1270 +#define RCC_FINDIV20CFGR 0x1274 +#define RCC_FINDIV21CFGR 0x1278 +#define RCC_FINDIV22CFGR 0x127C +#define RCC_FINDIV23CFGR 0x1280 +#define RCC_FINDIV24CFGR 0x1284 +#define RCC_FINDIV25CFGR 0x1288 +#define RCC_FINDIV26CFGR 0x128C +#define RCC_FINDIV27CFGR 0x1290 +#define RCC_FINDIV28CFGR 0x1294 +#define RCC_FINDIV29CFGR 0x1298 +#define RCC_FINDIV30CFGR 0x129C +#define RCC_FINDIV31CFGR 0x12A0 +#define RCC_FINDIV32CFGR 0x12A4 +#define RCC_FINDIV33CFGR 0x12A8 +#define RCC_FINDIV34CFGR 0x12AC +#define RCC_FINDIV35CFGR 0x12B0 +#define RCC_FINDIV36CFGR 0x12B4 +#define RCC_FINDIV37CFGR 0x12B8 +#define RCC_FINDIV38CFGR 0x12BC +#define RCC_FINDIV39CFGR 0x12C0 +#define RCC_FINDIV40CFGR 0x12C4 +#define RCC_FINDIV41CFGR 0x12C8 +#define RCC_FINDIV42CFGR 0x12CC +#define RCC_FINDIV43CFGR 0x12D0 +#define RCC_FINDIV44CFGR 0x12D4 +#define RCC_FINDIV45CFGR 0x12D8 +#define RCC_FINDIV46CFGR 0x12DC +#define RCC_FINDIV47CFGR 0x12E0 +#define RCC_FINDIV48CFGR 0x12E4 +#define RCC_FINDIV49CFGR 0x12E8 +#define RCC_FINDIV50CFGR 0x12EC +#define RCC_FINDIV51CFGR 0x12F0 +#define RCC_FINDIV52CFGR 0x12F4 +#define RCC_FINDIV53CFGR 0x12F8 +#define RCC_FINDIV54CFGR 0x12FC +#define RCC_FINDIV55CFGR 0x1300 +#define RCC_FINDIV56CFGR 0x1304 +#define RCC_FINDIV57CFGR 0x1308 +#define RCC_FINDIV58CFGR 0x130C +#define RCC_FINDIV59CFGR 0x1310 +#define RCC_FINDIV60CFGR 0x1314 +#define RCC_FINDIV61CFGR 0x1318 +#define RCC_FINDIV62CFGR 0x131C +#define RCC_FINDIV63CFGR 0x1320 +#define RCC_FINDIVSR1 0x1324 +#define RCC_FINDIVSR2 0x1328 +#define RCC_FCALCOBS0CFGR 0x1340 +#define RCC_FCALCOBS1CFGR 0x1344 +#define RCC_FCALCREFCFGR 0x1348 +#define RCC_FCALCCR1 0x134C +#define RCC_FCALCCR2 0x1354 +#define RCC_FCALCSR 0x1358 +#define RCC_PLL4CFGR1 0x1360 +#define RCC_PLL4CFGR2 0x1364 +#define RCC_PLL4CFGR3 0x1368 +#define RCC_PLL4CFGR4 0x136C +#define RCC_PLL4CFGR5 0x1370 +#define RCC_PLL4CFGR6 0x1378 +#define RCC_PLL4CFGR7 0x137C +#define RCC_PLL5CFGR1 0x1388 +#define RCC_PLL5CFGR2 0x138C +#define RCC_PLL5CFGR3 0x1390 +#define RCC_PLL5CFGR4 0x1394 +#define RCC_PLL5CFGR5 0x1398 +#define RCC_PLL5CFGR6 0x13A0 +#define RCC_PLL5CFGR7 0x13A4 +#define RCC_PLL6CFGR1 0x13B0 +#define RCC_PLL6CFGR2 0x13B4 +#define RCC_PLL6CFGR3 0x13B8 +#define RCC_PLL6CFGR4 0x13BC +#define RCC_PLL6CFGR5 0x13C0 +#define RCC_PLL6CFGR6 0x13C8 +#define RCC_PLL6CFGR7 0x13CC +#define RCC_PLL7CFGR1 0x13D8 +#define RCC_PLL7CFGR2 0x13DC +#define RCC_PLL7CFGR3 0x13E0 +#define RCC_PLL7CFGR4 0x13E4 +#define RCC_PLL7CFGR5 0x13E8 +#define RCC_PLL7CFGR6 0x13F0 +#define RCC_PLL7CFGR7 0x13F4 +#define RCC_PLL8CFGR1 0x1400 +#define RCC_PLL8CFGR2 0x1404 +#define RCC_PLL8CFGR3 0x1408 +#define RCC_PLL8CFGR4 0x140C +#define RCC_PLL8CFGR5 0x1410 +#define RCC_PLL8CFGR6 0x1418 +#define RCC_PLL8CFGR7 0x141C +#define RCC_VERR 0xFFF4 +#define RCC_IDR 0xFFF8 +#define RCC_SIDR 0xFFFC + +#endif /* STM32MP21_RCC_H */ -- cgit v1.3.1 From 56356278331ee3934484ce8ee83aea892e3c0710 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 3 Feb 2026 17:49:22 +0100 Subject: reset: stm32mp21: add stm32mp21 reset driver Implement STM32MP21 reset drivers using stm32-core-reset API. Signed-off-by: Gabriel Fernandez Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/reset/stm32/Kconfig | 7 ++ drivers/reset/stm32/Makefile | 1 + drivers/reset/stm32/stm32-reset-mp21.c | 136 +++++++++++++++++++++++++++++++++ 3 files changed, 144 insertions(+) create mode 100644 drivers/reset/stm32/stm32-reset-mp21.c (limited to 'drivers') diff --git a/drivers/reset/stm32/Kconfig b/drivers/reset/stm32/Kconfig index fdd88a6bfae..1bafba516af 100644 --- a/drivers/reset/stm32/Kconfig +++ b/drivers/reset/stm32/Kconfig @@ -14,6 +14,13 @@ config RESET_STM32MP1 Support for reset controllers on STMicroelectronics STM32MP1 family SoCs. This reset driver is compatible with STM32MP13 and STM32MP15 SoCs. +config RESET_STM32MP21 + bool "Enable the STM32MP21 reset" + default y if STM32MP21X + help + Support for reset controllers on STMicroelectronics STM32MP21 family SoCs. + This reset driver is compatible with STM32MP21 SoCs. + config RESET_STM32MP25 bool "Enable the STM32MP25 reset" depends on STM32MP23X || STM32MP25X diff --git a/drivers/reset/stm32/Makefile b/drivers/reset/stm32/Makefile index c31ae524ba1..ac4d3c6fc8f 100644 --- a/drivers/reset/stm32/Makefile +++ b/drivers/reset/stm32/Makefile @@ -6,4 +6,5 @@ obj-y += stm32-reset-core.o obj-$(CONFIG_RESET_STM32) += stm32-reset.o obj-$(CONFIG_RESET_STM32MP1) += stm32-reset-mp1.o +obj-$(CONFIG_RESET_STM32MP21) += stm32-reset-mp21.o obj-$(CONFIG_RESET_STM32MP25) += stm32-reset-mp25.o diff --git a/drivers/reset/stm32/stm32-reset-mp21.c b/drivers/reset/stm32/stm32-reset-mp21.c new file mode 100644 index 00000000000..7d169d7582f --- /dev/null +++ b/drivers/reset/stm32/stm32-reset-mp21.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2026, STMicroelectronics - All Rights Reserved + * Author(s): Gabriel Fernandez, for STMicroelectronics. + */ + +#include +#include +#include +#include + +/* Reset clear offset for STM32MP RCC */ +#define RCC_CLR_OFFSET 0x4 + +/* Timeout for deassert */ +#define STM32_DEASSERT_TIMEOUT_US 10000 + +#define RESET(id, _offset, _bit_idx, _set_clr) \ + [id] = &(struct stm32_reset_cfg){ \ + .offset = (_offset), \ + .bit_idx = (_bit_idx), \ + .set_clr = (_set_clr), \ + } + +static const struct stm32_reset_cfg *stm32mp21_reset[] = { + RESET(TIM1_R, RCC_TIM1CFGR, 0, 0), + RESET(TIM2_R, RCC_TIM2CFGR, 0, 0), + RESET(TIM3_R, RCC_TIM3CFGR, 0, 0), + RESET(TIM4_R, RCC_TIM4CFGR, 0, 0), + RESET(TIM5_R, RCC_TIM5CFGR, 0, 0), + RESET(TIM6_R, RCC_TIM6CFGR, 0, 0), + RESET(TIM7_R, RCC_TIM7CFGR, 0, 0), + RESET(TIM8_R, RCC_TIM8CFGR, 0, 0), + RESET(TIM10_R, RCC_TIM10CFGR, 0, 0), + RESET(TIM11_R, RCC_TIM11CFGR, 0, 0), + RESET(TIM12_R, RCC_TIM12CFGR, 0, 0), + RESET(TIM13_R, RCC_TIM13CFGR, 0, 0), + RESET(TIM14_R, RCC_TIM14CFGR, 0, 0), + RESET(TIM15_R, RCC_TIM15CFGR, 0, 0), + RESET(TIM16_R, RCC_TIM16CFGR, 0, 0), + RESET(TIM17_R, RCC_TIM17CFGR, 0, 0), + RESET(LPTIM1_R, RCC_LPTIM1CFGR, 0, 0), + RESET(LPTIM2_R, RCC_LPTIM2CFGR, 0, 0), + RESET(LPTIM3_R, RCC_LPTIM3CFGR, 0, 0), + RESET(LPTIM4_R, RCC_LPTIM4CFGR, 0, 0), + RESET(LPTIM5_R, RCC_LPTIM5CFGR, 0, 0), + RESET(SPI1_R, RCC_SPI1CFGR, 0, 0), + RESET(SPI2_R, RCC_SPI2CFGR, 0, 0), + RESET(SPI3_R, RCC_SPI3CFGR, 0, 0), + RESET(SPI4_R, RCC_SPI4CFGR, 0, 0), + RESET(SPI5_R, RCC_SPI5CFGR, 0, 0), + RESET(SPI6_R, RCC_SPI6CFGR, 0, 0), + RESET(SPDIFRX_R, RCC_SPDIFRXCFGR, 0, 0), + RESET(USART1_R, RCC_USART1CFGR, 0, 0), + RESET(USART2_R, RCC_USART2CFGR, 0, 0), + RESET(USART3_R, RCC_USART3CFGR, 0, 0), + RESET(UART4_R, RCC_UART4CFGR, 0, 0), + RESET(UART5_R, RCC_UART5CFGR, 0, 0), + RESET(USART6_R, RCC_USART6CFGR, 0, 0), + RESET(UART7_R, RCC_UART7CFGR, 0, 0), + RESET(LPUART1_R, RCC_LPUART1CFGR, 0, 0), + RESET(I2C1_R, RCC_I2C1CFGR, 0, 0), + RESET(I2C2_R, RCC_I2C2CFGR, 0, 0), + RESET(I2C3_R, RCC_I2C3CFGR, 0, 0), + RESET(SAI1_R, RCC_SAI1CFGR, 0, 0), + RESET(SAI2_R, RCC_SAI2CFGR, 0, 0), + RESET(SAI3_R, RCC_SAI3CFGR, 0, 0), + RESET(SAI4_R, RCC_SAI4CFGR, 0, 0), + RESET(MDF1_R, RCC_MDF1CFGR, 0, 0), + RESET(FDCAN_R, RCC_FDCANCFGR, 0, 0), + RESET(HDP_R, RCC_HDPCFGR, 0, 0), + RESET(ADC1_R, RCC_ADC1CFGR, 0, 0), + RESET(ADC2_R, RCC_ADC2CFGR, 0, 0), + RESET(ETH1_R, RCC_ETH1CFGR, 0, 0), + RESET(ETH2_R, RCC_ETH2CFGR, 0, 0), + RESET(USBH_R, RCC_USBHCFGR, 0, 0), + RESET(USB2PHY1_R, RCC_USB2PHY1CFGR, 0, 0), + RESET(USB2PHY2_R, RCC_USB2PHY2CFGR, 0, 0), + RESET(SDMMC1_R, RCC_SDMMC1CFGR, 0, 0), + RESET(SDMMC1DLL_R, RCC_SDMMC1CFGR, 16, 0), + RESET(SDMMC2_R, RCC_SDMMC2CFGR, 0, 0), + RESET(SDMMC2DLL_R, RCC_SDMMC2CFGR, 16, 0), + RESET(SDMMC3_R, RCC_SDMMC3CFGR, 0, 0), + RESET(SDMMC3DLL_R, RCC_SDMMC3CFGR, 16, 0), + RESET(LTDC_R, RCC_LTDCCFGR, 0, 0), + RESET(CSI_R, RCC_CSICFGR, 0, 0), + RESET(DCMIPP_R, RCC_DCMIPPCFGR, 0, 0), + RESET(DCMIPSSI_R, RCC_DCMIPSSICFGR, 0, 0), + RESET(WWDG1_R, RCC_WWDG1CFGR, 0, 0), + RESET(VREF_R, RCC_VREFCFGR, 0, 0), + RESET(DTS_R, RCC_DTSCFGR, 0, 0), + RESET(CRC_R, RCC_CRCCFGR, 0, 0), + RESET(SERC_R, RCC_SERCCFGR, 0, 0), + RESET(I3C1_R, RCC_I3C1CFGR, 0, 0), + RESET(I3C2_R, RCC_I3C2CFGR, 0, 0), + RESET(IWDG2_KER_R, RCC_IWDGC1CFGSETR, 18, 1), + RESET(IWDG4_KER_R, RCC_IWDGC2CFGSETR, 18, 1), + RESET(RNG1_R, RCC_RNG1CFGR, 0, 0), + RESET(RNG2_R, RCC_RNG2CFGR, 0, 0), + RESET(PKA_R, RCC_PKACFGR, 0, 0), + RESET(SAES_R, RCC_SAESCFGR, 0, 0), + RESET(HASH1_R, RCC_HASH1CFGR, 0, 0), + RESET(HASH2_R, RCC_HASH2CFGR, 0, 0), + RESET(CRYP1_R, RCC_CRYP1CFGR, 0, 0), + RESET(CRYP2_R, RCC_CRYP2CFGR, 0, 0), + RESET(OTG_R, RCC_OTGCFGR, 0, 0), +}; + +static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_ctl *reset_ctl) +{ + unsigned long id = reset_ctl->id; + + if (id < ARRAY_SIZE(stm32mp21_reset)) + return stm32mp21_reset[id]; + + return NULL; +} + +static const struct stm32_reset_data stm32mp21_reset_data = { + .get_reset_line = stm32_get_reset_line, + .clear_offset = RCC_CLR_OFFSET, + .reset_us = STM32_DEASSERT_TIMEOUT_US, +}; + +static int stm32_reset_probe(struct udevice *dev) +{ + return stm32_reset_core_probe(dev, &stm32mp21_reset_data); +} + +U_BOOT_DRIVER(stm32mp21_rcc_reset) = { + .name = "stm32mp21_reset", + .id = UCLASS_RESET, + .probe = stm32_reset_probe, + .priv_auto = sizeof(struct stm32_reset_priv), + .ops = &stm32_reset_ops, +}; -- cgit v1.3.1 From ae1e081f83fb4b4d79e32f1bdcea3e47519ce05c Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Mon, 23 Feb 2026 19:55:23 +0530 Subject: phy: samsung: add enum for variants based on SoCs The variant enum is used to uniquely identify which SoC the PHY block belongs to. It is initially set in the match table, along with the compatible string, it gets copied to driver data struct during probe. SoC specific functions must only be called if the respective variant enum is set. Add switch-case blocks wherever required. Reviewed-by: Mattijs Korpershoek Signed-off-by: Kaustabh Chakraborty Signed-off-by: Minkyu Kang --- drivers/phy/phy-exynos-usbdrd.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/phy/phy-exynos-usbdrd.c b/drivers/phy/phy-exynos-usbdrd.c index db5815ed184..4ab8da2a08f 100644 --- a/drivers/phy/phy-exynos-usbdrd.c +++ b/drivers/phy/phy-exynos-usbdrd.c @@ -66,6 +66,10 @@ #define KHZ 1000 #define MHZ (KHZ * KHZ) +enum exynos_usbdrd_phy_variant { + EXYNOS850_USBDRD_PHY, +}; + /** * struct exynos_usbdrd_phy - driver data for Exynos USB PHY * @reg_phy: USB PHY controller register memory base @@ -73,6 +77,7 @@ * @core_clk: core clock for phy (ref clock) * @reg_pmu: regmap for PMU block * @extrefclk: frequency select settings when using 'separate reference clocks' + * @variant: ID to uniquely distinguish USB PHY variant */ struct exynos_usbdrd_phy { void __iomem *reg_phy; @@ -80,6 +85,7 @@ struct exynos_usbdrd_phy { struct clk *core_clk; struct regmap *reg_pmu; u32 extrefclk; + enum exynos_usbdrd_phy_variant variant; }; static void exynos_usbdrd_phy_isol(struct regmap *reg_pmu, bool isolate) @@ -254,7 +260,13 @@ static int exynos_usbdrd_phy_init(struct phy *phy) if (ret) return ret; - exynos850_usbdrd_utmi_init(phy); + switch (phy_drd->variant) { + case EXYNOS850_USBDRD_PHY: + exynos850_usbdrd_utmi_init(phy); + break; + default: + dev_err(phy->dev, "Failed to recognize phy variant\n"); + } clk_disable_unprepare(phy_drd->clk); @@ -270,7 +282,13 @@ static int exynos_usbdrd_phy_exit(struct phy *phy) if (ret) return ret; - exynos850_usbdrd_utmi_exit(phy); + switch (phy_drd->variant) { + case EXYNOS850_USBDRD_PHY: + exynos850_usbdrd_utmi_exit(phy); + break; + default: + dev_err(phy->dev, "Failed to recognize phy variant\n"); + } clk_disable_unprepare(phy_drd->clk); @@ -359,6 +377,8 @@ static int exynos_usbdrd_phy_probe(struct udevice *dev) return err; } + phy_drd->variant = dev_get_driver_data(dev); + return 0; } @@ -372,6 +392,7 @@ static const struct phy_ops exynos_usbdrd_phy_ops = { static const struct udevice_id exynos_usbdrd_phy_of_match[] = { { .compatible = "samsung,exynos850-usbdrd-phy", + .data = EXYNOS850_USBDRD_PHY, }, { } }; -- cgit v1.3.1 From e4001865ff387b928ea3d422d673dcc7389f8665 Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Mon, 23 Feb 2026 19:55:24 +0530 Subject: phy: samsung: add support for exynos7870 USB PHY The USB PHY used by the Exynos7870 SoC has a single USB 2.0 interface. Add its dedicated variant enum, compatible, and init/exit functions. The PHY enable bit of Exynos7870's PHY is different in contrast to that of Exynos850 and most Exynos PHYs. To allow this change, a simple if condition is added in exynos_usbdrd_phy_isol() which changes the bitmask. Since the variant enum is required, the function argument is changed to accept the driver data itself. Reviewed-by: Mattijs Korpershoek Signed-off-by: Kaustabh Chakraborty Signed-off-by: Minkyu Kang --- drivers/phy/phy-exynos-usbdrd.c | 246 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 238 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/phy/phy-exynos-usbdrd.c b/drivers/phy/phy-exynos-usbdrd.c index 4ab8da2a08f..c5eed29a2c8 100644 --- a/drivers/phy/phy-exynos-usbdrd.c +++ b/drivers/phy/phy-exynos-usbdrd.c @@ -21,6 +21,7 @@ /* Offset of PMU register controlling USB PHY output isolation */ #define EXYNOS_USBDRD_PHY_CONTROL 0x0704 #define EXYNOS_PHY_ENABLE BIT(0) +#define EXYNOS7870_PHY_ENABLE BIT(1) /* Exynos USB PHY registers */ #define EXYNOS5_FSEL_9MHZ6 0x0 @@ -32,6 +33,88 @@ #define EXYNOS5_FSEL_26MHZ 0x6 #define EXYNOS5_FSEL_50MHZ 0x7 +/* Exynos5: USB DRD PHY registers */ +#define EXYNOS5_DRD_LINKSYSTEM 0x04 +#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27) +#define LINKSYSTEM_FORCE_VBUSVALID BIT(8) +#define LINKSYSTEM_FORCE_BVALID BIT(7) +#define LINKSYSTEM_FLADJ GENMASK(6, 1) + +#define EXYNOS5_DRD_PHYUTMI 0x08 +#define PHYUTMI_UTMI_SUSPEND_COM_N BIT(12) +#define PHYUTMI_UTMI_L1_SUSPEND_COM_N BIT(11) +#define PHYUTMI_VBUSVLDEXTSEL BIT(10) +#define PHYUTMI_VBUSVLDEXT BIT(9) +#define PHYUTMI_TXBITSTUFFENH BIT(8) +#define PHYUTMI_TXBITSTUFFEN BIT(7) +#define PHYUTMI_OTGDISABLE BIT(6) +#define PHYUTMI_IDPULLUP BIT(5) +#define PHYUTMI_DRVVBUS BIT(4) +#define PHYUTMI_DPPULLDOWN BIT(3) +#define PHYUTMI_DMPULLDOWN BIT(2) +#define PHYUTMI_FORCESUSPEND BIT(1) +#define PHYUTMI_FORCESLEEP BIT(0) + +#define EXYNOS5_DRD_PHYCLKRST 0x10 +#define PHYCLKRST_EN_UTMISUSPEND BIT(31) +#define PHYCLKRST_SSC_REFCLKSEL GENMASK(30, 23) +#define PHYCLKRST_SSC_RANGE GENMASK(22, 21) +#define PHYCLKRST_SSC_EN BIT(20) +#define PHYCLKRST_REF_SSP_EN BIT(19) +#define PHYCLKRST_REF_CLKDIV2 BIT(18) +#define PHYCLKRST_MPLL_MULTIPLIER GENMASK(17, 11) +#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF 0x19 +#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF 0x32 +#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF 0x68 +#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF 0x7d +#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF 0x02 +#define PHYCLKRST_FSEL_PIPE GENMASK(10, 8) +#define PHYCLKRST_FSEL_UTMI GENMASK(7, 5) +#define PHYCLKRST_FSEL_PAD_100MHZ 0x27 +#define PHYCLKRST_FSEL_PAD_24MHZ 0x2a +#define PHYCLKRST_FSEL_PAD_20MHZ 0x31 +#define PHYCLKRST_FSEL_PAD_19_2MHZ 0x38 +#define PHYCLKRST_RETENABLEN BIT(4) +#define PHYCLKRST_REFCLKSEL GENMASK(3, 2) +#define PHYCLKRST_REFCLKSEL_PAD_REFCLK 0x2 +#define PHYCLKRST_REFCLKSEL_EXT_REFCLK 0x3 +#define PHYCLKRST_PORTRESET BIT(1) +#define PHYCLKRST_COMMONONN BIT(0) + +#define EXYNOS5_DRD_PHYPARAM0 0x1c +#define PHYPARAM0_REF_USE_PAD BIT(31) +#define PHYPARAM0_REF_LOSLEVEL GENMASK(30, 26) +#define PHYPARAM0_REF_LOSLEVEL_VAL 0x9 +#define PHYPARAM0_TXVREFTUNE GENMASK(25, 22) +#define PHYPARAM0_TXRISETUNE GENMASK(21, 20) +#define PHYPARAM0_TXRESTUNE GENMASK(19, 18) +#define PHYPARAM0_TXPREEMPPULSETUNE BIT(17) +#define PHYPARAM0_TXPREEMPAMPTUNE GENMASK(16, 15) +#define PHYPARAM0_TXHSXVTUNE GENMASK(14, 13) +#define PHYPARAM0_TXFSLSTUNE GENMASK(12, 9) +#define PHYPARAM0_SQRXTUNE GENMASK(8, 6) +#define PHYPARAM0_OTGTUNE GENMASK(5, 3) +#define PHYPARAM0_COMPDISTUNE GENMASK(2, 0) + +#define EXYNOS5_DRD_LINKPORT 0x44 +#define LINKPORT_HOST_U3_PORT_DISABLE BIT(8) +#define LINKPORT_HOST_U2_PORT_DISABLE BIT(7) +#define LINKPORT_HOST_PORT_OVCR_U3 BIT(5) +#define LINKPORT_HOST_PORT_OVCR_U2 BIT(4) +#define LINKPORT_HOST_PORT_OVCR_U3_SEL BIT(3) +#define LINKPORT_HOST_PORT_OVCR_U2_SEL BIT(2) + +/* Exynos7870: USB DRD PHY registers */ +#define EXYNOS7870_DRD_HSPHYCTRL 0x54 +#define HSPHYCTRL_PHYSWRSTALL BIT(31) +#define HSPHYCTRL_SIDDQ BIT(6) +#define HSPHYCTRL_PHYSWRST BIT(0) + +#define EXYNOS7870_DRD_HSPHYPLLTUNE 0x70 +#define HSPHYPLLTUNE_PLL_B_TUNE BIT(6) +#define HSPHYPLLTUNE_PLL_I_TUNE GENMASK(5, 4) +#define HSPHYPLLTUNE_PLL_P_TUNE GENMASK(3, 0) + /* Exynos850: USB DRD PHY registers */ #define EXYNOS850_DRD_LINKCTRL 0x04 #define LINKCTRL_FORCE_QACT BIT(8) @@ -67,6 +150,7 @@ #define MHZ (KHZ * KHZ) enum exynos_usbdrd_phy_variant { + EXYNOS7870_USBDRD_PHY, EXYNOS850_USBDRD_PHY, }; @@ -88,16 +172,20 @@ struct exynos_usbdrd_phy { enum exynos_usbdrd_phy_variant variant; }; -static void exynos_usbdrd_phy_isol(struct regmap *reg_pmu, bool isolate) +static void exynos_usbdrd_phy_isol(struct exynos_usbdrd_phy *phy_drd, + bool isolate) { - unsigned int val; + unsigned int mask = EXYNOS_PHY_ENABLE, val; - if (!reg_pmu) + if (!phy_drd->reg_pmu) return; - val = isolate ? 0 : EXYNOS_PHY_ENABLE; - regmap_update_bits(reg_pmu, EXYNOS_USBDRD_PHY_CONTROL, - EXYNOS_PHY_ENABLE, val); + if (phy_drd->variant == EXYNOS7870_USBDRD_PHY) + mask = EXYNOS7870_PHY_ENABLE; + + val = isolate ? 0 : mask; + regmap_update_bits(phy_drd->reg_pmu, EXYNOS_USBDRD_PHY_CONTROL, + mask, val); } /* @@ -138,6 +226,111 @@ static unsigned int exynos_rate_to_clk(unsigned long rate, u32 *reg) return 0; } +static void exynos7870_usbdrd_utmi_init(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + void __iomem *regs_base = phy_drd->reg_phy; + u32 reg; + + reg = readl(regs_base + EXYNOS5_DRD_PHYCLKRST); + /* Use PADREFCLK as ref clock */ + reg &= ~PHYCLKRST_REFCLKSEL; + reg |= FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_PAD_REFCLK); + /* Select ref clock rate */ + reg &= ~PHYCLKRST_FSEL_UTMI; + reg &= ~PHYCLKRST_FSEL_PIPE; + reg |= FIELD_PREP(PHYCLKRST_FSEL_UTMI, phy_drd->extrefclk); + /* Enable suspend and reset the port */ + reg |= PHYCLKRST_EN_UTMISUSPEND; + reg |= PHYCLKRST_COMMONONN; + reg |= PHYCLKRST_PORTRESET; + writel(reg, regs_base + EXYNOS5_DRD_PHYCLKRST); + udelay(10); + + /* Clear the port reset bit */ + reg &= ~PHYCLKRST_PORTRESET; + writel(reg, regs_base + EXYNOS5_DRD_PHYCLKRST); + + /* Change PHY PLL tune value */ + reg = readl(regs_base + EXYNOS7870_DRD_HSPHYPLLTUNE); + if (phy_drd->extrefclk == EXYNOS5_FSEL_24MHZ) + reg |= HSPHYPLLTUNE_PLL_B_TUNE; + else + reg &= ~HSPHYPLLTUNE_PLL_B_TUNE; + reg &= ~HSPHYPLLTUNE_PLL_P_TUNE; + reg |= FIELD_PREP(HSPHYPLLTUNE_PLL_P_TUNE, 14); + writel(reg, regs_base + EXYNOS7870_DRD_HSPHYPLLTUNE); + + /* High-Speed PHY control */ + reg = readl(regs_base + EXYNOS7870_DRD_HSPHYCTRL); + reg &= ~HSPHYCTRL_SIDDQ; + reg &= ~HSPHYCTRL_PHYSWRST; + reg &= ~HSPHYCTRL_PHYSWRSTALL; + writel(reg, regs_base + EXYNOS7870_DRD_HSPHYCTRL); + udelay(500); + + reg = readl(regs_base + EXYNOS5_DRD_LINKSYSTEM); + /* + * Setting the Frame length Adj value[6:1] to default 0x20 + * See xHCI 1.0 spec, 5.2.4 + */ + reg |= LINKSYSTEM_XHCI_VERSION_CONTROL; + reg &= ~LINKSYSTEM_FLADJ; + reg |= FIELD_PREP(LINKSYSTEM_FLADJ, 0x20); + /* Set VBUSVALID signal as the VBUS pad is not used */ + reg |= LINKSYSTEM_FORCE_BVALID; + reg |= LINKSYSTEM_FORCE_VBUSVALID; + writel(reg, regs_base + EXYNOS5_DRD_LINKSYSTEM); + + reg = readl(regs_base + EXYNOS5_DRD_PHYUTMI); + /* Release force_sleep & force_suspend */ + reg &= ~PHYUTMI_FORCESLEEP; + reg &= ~PHYUTMI_FORCESUSPEND; + /* DP/DM pull down control */ + reg &= ~PHYUTMI_DMPULLDOWN; + reg &= ~PHYUTMI_DPPULLDOWN; + reg &= ~PHYUTMI_DRVVBUS; + /* Set DP-pull up as the VBUS pad is not used */ + reg |= PHYUTMI_VBUSVLDEXTSEL; + reg |= PHYUTMI_VBUSVLDEXT; + /* Disable OTG block and VBUS valid comparator */ + reg |= PHYUTMI_OTGDISABLE; + writel(reg, regs_base + EXYNOS5_DRD_PHYUTMI); + + /* Configure OVC IO usage */ + reg = readl(regs_base + EXYNOS5_DRD_LINKPORT); + reg |= LINKPORT_HOST_PORT_OVCR_U3_SEL | LINKPORT_HOST_PORT_OVCR_U2_SEL; + writel(reg, regs_base + EXYNOS5_DRD_LINKPORT); + + /* High-Speed PHY swrst */ + reg = readl(regs_base + EXYNOS7870_DRD_HSPHYCTRL); + reg |= HSPHYCTRL_PHYSWRST; + writel(reg, regs_base + EXYNOS7870_DRD_HSPHYCTRL); + udelay(20); + + /* Clear the PHY swrst bit */ + reg = readl(regs_base + EXYNOS7870_DRD_HSPHYCTRL); + reg &= ~HSPHYCTRL_PHYSWRST; + writel(reg, regs_base + EXYNOS7870_DRD_HSPHYCTRL); + + reg = readl(regs_base + EXYNOS5_DRD_PHYPARAM0); + reg &= ~(PHYPARAM0_TXVREFTUNE | PHYPARAM0_TXRISETUNE | + PHYPARAM0_TXRESTUNE | PHYPARAM0_TXPREEMPPULSETUNE | + PHYPARAM0_TXPREEMPAMPTUNE | PHYPARAM0_TXHSXVTUNE | + PHYPARAM0_TXFSLSTUNE | PHYPARAM0_SQRXTUNE | + PHYPARAM0_OTGTUNE | PHYPARAM0_COMPDISTUNE); + reg |= FIELD_PREP_CONST(PHYPARAM0_TXVREFTUNE, 14) | + FIELD_PREP_CONST(PHYPARAM0_TXRISETUNE, 1) | + FIELD_PREP_CONST(PHYPARAM0_TXRESTUNE, 3) | + FIELD_PREP_CONST(PHYPARAM0_TXPREEMPAMPTUNE, 0) | + FIELD_PREP_CONST(PHYPARAM0_TXHSXVTUNE, 0) | + FIELD_PREP_CONST(PHYPARAM0_TXFSLSTUNE, 3) | + FIELD_PREP_CONST(PHYPARAM0_SQRXTUNE, 6) | + FIELD_PREP_CONST(PHYPARAM0_OTGTUNE, 2) | + FIELD_PREP_CONST(PHYPARAM0_COMPDISTUNE, 3); + writel(reg, regs_base + EXYNOS5_DRD_PHYPARAM0); +} + static void exynos850_usbdrd_utmi_init(struct phy *phy) { struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); @@ -225,6 +418,33 @@ static void exynos850_usbdrd_utmi_init(struct phy *phy) writel(reg, regs_base + EXYNOS850_DRD_HSP); } +static void exynos7870_usbdrd_utmi_exit(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + void __iomem *regs_base = phy_drd->reg_phy; + u32 reg; + + /* + * Disable the VBUS signal and the ID pull-up resistor. + * Enable force-suspend and force-sleep modes. + */ + reg = readl(regs_base + EXYNOS5_DRD_PHYUTMI); + reg &= ~(PHYUTMI_DRVVBUS | PHYUTMI_VBUSVLDEXT | PHYUTMI_VBUSVLDEXTSEL); + reg &= ~PHYUTMI_IDPULLUP; + reg |= PHYUTMI_FORCESUSPEND | PHYUTMI_FORCESLEEP; + writel(reg, regs_base + EXYNOS5_DRD_PHYUTMI); + + /* Power down PHY analog blocks */ + reg = readl(regs_base + EXYNOS7870_DRD_HSPHYCTRL); + reg |= HSPHYCTRL_SIDDQ; + writel(reg, regs_base + EXYNOS7870_DRD_HSPHYCTRL); + + /* Clear VBUSVALID signal as the VBUS pad is not used */ + reg = readl(regs_base + EXYNOS5_DRD_LINKSYSTEM); + reg &= ~(LINKSYSTEM_FORCE_BVALID | LINKSYSTEM_FORCE_VBUSVALID); + writel(reg, regs_base + EXYNOS5_DRD_LINKSYSTEM); +} + static void exynos850_usbdrd_utmi_exit(struct phy *phy) { struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); @@ -261,6 +481,9 @@ static int exynos_usbdrd_phy_init(struct phy *phy) return ret; switch (phy_drd->variant) { + case EXYNOS7870_USBDRD_PHY: + exynos7870_usbdrd_utmi_init(phy); + break; case EXYNOS850_USBDRD_PHY: exynos850_usbdrd_utmi_init(phy); break; @@ -283,6 +506,9 @@ static int exynos_usbdrd_phy_exit(struct phy *phy) return ret; switch (phy_drd->variant) { + case EXYNOS7870_USBDRD_PHY: + exynos7870_usbdrd_utmi_exit(phy); + break; case EXYNOS850_USBDRD_PHY: exynos850_usbdrd_utmi_exit(phy); break; @@ -307,7 +533,7 @@ static int exynos_usbdrd_phy_power_on(struct phy *phy) return ret; /* Power-on PHY */ - exynos_usbdrd_phy_isol(phy_drd->reg_pmu, false); + exynos_usbdrd_phy_isol(phy_drd, false); return 0; } @@ -319,7 +545,7 @@ static int exynos_usbdrd_phy_power_off(struct phy *phy) dev_dbg(phy->dev, "Request to power_off usbdrd_phy phy\n"); /* Power-off the PHY */ - exynos_usbdrd_phy_isol(phy_drd->reg_pmu, true); + exynos_usbdrd_phy_isol(phy_drd, true); clk_disable_unprepare(phy_drd->core_clk); @@ -390,6 +616,10 @@ static const struct phy_ops exynos_usbdrd_phy_ops = { }; static const struct udevice_id exynos_usbdrd_phy_of_match[] = { + { + .compatible = "samsung,exynos7870-usbdrd-phy", + .data = EXYNOS7870_USBDRD_PHY, + }, { .compatible = "samsung,exynos850-usbdrd-phy", .data = EXYNOS850_USBDRD_PHY, -- cgit v1.3.1 From 3ee1408eeb7352d770bbf063df85fa23cd6b79a4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 10 Feb 2026 16:12:14 +0800 Subject: firmware: scmi: Validate device tree node before setup channel SCMI base protocol device does not have a device tree, it should use and need to use the agent base channel. For scmi_base.[x], there is no real device tree node for it. ofnode_null() is assigned as the device tree node for scmi base protocol device: commit 7eb4eb541c14 ("firmware: scmi: install base protocol to SCMI agent") However with recent update in commit 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c"), SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1 and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF. So add a check in x_get_channel() to validate the protocol devices' ofnode. Reported-by: Ye Li Closes: https://lore.kernel.org/u-boot/939a9696-27fa-45a1-b428-feffe21ac6d5@oss.nxp.com/ Signed-off-by: Peng Fan --- drivers/firmware/scmi/mailbox_agent.c | 2 +- drivers/firmware/scmi/optee_agent.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c index 16a82f55ab7..cda94565de5 100644 --- a/drivers/firmware/scmi/mailbox_agent.c +++ b/drivers/firmware/scmi/mailbox_agent.c @@ -101,7 +101,7 @@ static int scmi_mbox_get_channel(struct udevice *dev, struct scmi_mbox_channel *chan; int ret; - if (!dev_read_prop(protocol, "shmem", NULL)) { + if (!dev_has_ofnode(protocol) || !dev_read_prop(protocol, "shmem", NULL)) { /* Uses agent base channel */ *channel = container_of(base_chan, struct scmi_channel, ref); diff --git a/drivers/firmware/scmi/optee_agent.c b/drivers/firmware/scmi/optee_agent.c index 631625d715b..7170bd1e682 100644 --- a/drivers/firmware/scmi/optee_agent.c +++ b/drivers/firmware/scmi/optee_agent.c @@ -331,7 +331,8 @@ static int scmi_optee_get_channel(struct udevice *dev, u32 channel_id; int ret; - if (dev_read_u32(protocol, "linaro,optee-channel-id", &channel_id)) { + if (!dev_has_ofnode(protocol) || + dev_read_u32(protocol, "linaro,optee-channel-id", &channel_id)) { /* Uses agent base channel */ *channel = container_of(base_chan, struct scmi_channel, ref); -- cgit v1.3.1 From 6ee82240de63b085325b4f4ce4874240724f9dbe Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 10 Feb 2026 16:12:15 +0800 Subject: power: domain: Validate device tree node in dev_power_domain_ctrl Similar to pinctrl_select_state(), add dev_has_ofnode() check before doing the real work. Device(scmi_base.0) does not have a real device node, ofnode_null() is assigned as the device tree node for scmi base protocol device: 'commit 7eb4eb541c14 ("firmware: scmi: install base protocol to SCMI agent")' However with recent update in 'commit 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c")', SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1 and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF. So need to validate device tree node. Reported-by: Ye Li Closes: https://lore.kernel.org/u-boot/939a9696-27fa-45a1-b428-feffe21ac6d5@oss.nxp.com/ Signed-off-by: Peng Fan --- drivers/power/domain/power-domain-uclass.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index d9fa8ad4bd2..cea68945cbd 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -180,6 +180,9 @@ static int dev_power_domain_ctrl(struct udevice *dev, bool on) struct power_domain pd; int i, count, ret = 0; + if (!dev_has_ofnode(dev)) + return 0; + count = dev_count_phandle_with_args(dev, "power-domains", "#power-domain-cells", 0); for (i = 0; i < count; i++) { -- cgit v1.3.1 From efc9be77d851b98b38afcfb4e46d17703057efad Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 10 Feb 2026 16:12:16 +0800 Subject: iommu: Validate device tree node in dev_iommu_enable Similar to pinctrl_select_state(), add dev_has_ofnode() check before doing the real work. Device(scmi_base.0) does not have a real device node, ofnode_null() is assigned as the device tree node for scmi base protocol device: 'commit 7eb4eb541c14 ("firmware: scmi: install base protocol to SCMI agent")' However with recent update in 'commit 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c")', SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1 and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF. So need to validate device tree node. Reported-by: Ye Li Closes: https://lore.kernel.org/u-boot/939a9696-27fa-45a1-b428-feffe21ac6d5@oss.nxp.com/ Signed-off-by: Peng Fan --- drivers/iommu/iommu-uclass.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/iommu/iommu-uclass.c b/drivers/iommu/iommu-uclass.c index bb31cd519d2..31b40e5713a 100644 --- a/drivers/iommu/iommu-uclass.c +++ b/drivers/iommu/iommu-uclass.c @@ -79,6 +79,9 @@ int dev_iommu_enable(struct udevice *dev) const struct iommu_ops *ops; int i, count, ret = 0; + if (!dev_has_ofnode(dev)) + return 0; + count = dev_count_phandle_with_args(dev, "iommus", "#iommu-cells", 0); for (i = 0; i < count; i++) { -- cgit v1.3.1 From 080b4f099558212703a772d3ca74c0521cf5a7e8 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Wed, 26 Nov 2025 16:06:41 +0100 Subject: ufs: Disable UTP command timeout in slow mode When the UFS controller is operating in slow (PWM) mode, the driver is disabled the timeout for UTP send commands. In high-speed mode, the timeout remains enabled to detect stalled or failed transfers. This change ensures reliable operation in slow mode, where command completion may take longer and timeouts are not required. Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/e6deb9086afab9d2bdd53db8ecbc7db93af5204d.1764169598.git.michal.simek@amd.com Signed-off-by: Neil Armstrong --- drivers/ufs/ufs-uclass.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c index 3c8e4299259..7a80a9d5664 100644 --- a/drivers/ufs/ufs-uclass.c +++ b/drivers/ufs/ufs-uclass.c @@ -917,11 +917,13 @@ static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) enabled_intr_status = intr_status & hba->intr_mask; ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); - if (get_timer(start) > QUERY_REQ_TIMEOUT) { - dev_err(hba->dev, - "Timedout waiting for UTP response\n"); - - return -ETIMEDOUT; + if (hba->max_pwr_info.info.pwr_rx != SLOWAUTO_MODE && + hba->max_pwr_info.info.pwr_tx != SLOWAUTO_MODE) { + if (get_timer(start) > QUERY_REQ_TIMEOUT) { + dev_err(hba->dev, + "Timedout waiting for UTP response\n"); + return -ETIMEDOUT; + } } if (enabled_intr_status & UFSHCD_ERROR_MASK) { -- cgit v1.3.1 From 25f142543196e5b5f0f9c916f15671dcd26eb2f7 Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Sat, 11 Oct 2025 21:10:04 +0200 Subject: phy: Add MediaTek UFS PHY Driver This UFS M-PHY driver can be used on recent MediaTek SoCs as the primary PHY for the UFS controller. Signed-off-by: Igor Belwon Link: https://patch.msgid.link/20251011-mtk-ufs-uboot-v1-1-a05f991ee150@mentallysanemainliners.org Signed-off-by: Neil Armstrong --- drivers/phy/Kconfig | 10 +++ drivers/phy/Makefile | 1 + drivers/phy/phy-mtk-ufs.c | 190 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 201 insertions(+) create mode 100644 drivers/phy/phy-mtk-ufs.c (limited to 'drivers') diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 87729b479bd..09810b62b51 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -282,6 +282,16 @@ config PHY_MTK_TPHY multi-ports is first version, otherwise is second veriosn, so you can easily distinguish them by banks layout. +config PHY_MTK_UFS + tristate "MediaTek UFS M-PHY driver" + depends on ARCH_MEDIATEK + depends on PHY + help + Support for UFS M-PHY on MediaTek chipsets. + Enable this to provide vendor-specific probing, + initialization, power on and power off flow of + specified M-PHYs. + config PHY_NPCM_USB bool "Nuvoton NPCM USB PHY support" depends on PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 5a6df0ecfeb..83102349669 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_EXYNOS_USBDRD) += phy-exynos-usbdrd.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o +obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o obj-$(CONFIG_$(PHASE_)PHY_IMX8MQ_USB) += phy-imx8mq-usb.o obj-$(CONFIG_PHY_IMX8M_PCIE) += phy-imx8m-pcie.o diff --git a/drivers/phy/phy-mtk-ufs.c b/drivers/phy/phy-mtk-ufs.c new file mode 100644 index 00000000000..1eda3df858d --- /dev/null +++ b/drivers/phy/phy-mtk-ufs.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Stanley Chu + * + * Copyright (c) 2025, Igor Belwon + */ + +#include "dm/ofnode.h" +#include "dm/read.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* mphy register and offsets */ +#define MP_GLB_DIG_8C 0x008C +#define FRC_PLL_ISO_EN BIT(8) +#define PLL_ISO_EN BIT(9) +#define FRC_FRC_PWR_ON BIT(10) +#define PLL_PWR_ON BIT(11) + +#define MP_LN_DIG_RX_9C 0xA09C +#define FSM_DIFZ_FRC BIT(18) + +#define MP_LN_DIG_RX_AC 0xA0AC +#define FRC_RX_SQ_EN BIT(0) +#define RX_SQ_EN BIT(1) + +#define MP_LN_RX_44 0xB044 +#define FRC_CDR_PWR_ON BIT(17) +#define CDR_PWR_ON BIT(18) +#define FRC_CDR_ISO_EN BIT(19) +#define CDR_ISO_EN BIT(20) + +#define UFSPHY_CLKS_CNT 2 + +struct mtk_ufs_phy { + struct udevice *dev; + void __iomem *mmio; + + struct clk *unipro_clk; + struct clk *mp_clk; +}; + +static void ufs_mtk_phy_set_active(struct mtk_ufs_phy *phy) +{ + /* release DA_MP_PLL_PWR_ON */ + setbits_le32(phy->mmio + MP_GLB_DIG_8C, PLL_PWR_ON); + clrbits_le32(phy->mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); + + /* release DA_MP_PLL_ISO_EN */ + clrbits_le32(phy->mmio + MP_GLB_DIG_8C, PLL_ISO_EN); + clrbits_le32(phy->mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); + + /* release DA_MP_CDR_PWR_ON */ + setbits_le32(phy->mmio + MP_LN_RX_44, CDR_PWR_ON); + clrbits_le32(phy->mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); + + /* release DA_MP_CDR_ISO_EN */ + clrbits_le32(phy->mmio + MP_LN_RX_44, CDR_ISO_EN); + clrbits_le32(phy->mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); + + /* release DA_MP_RX0_SQ_EN */ + setbits_le32(phy->mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); + clrbits_le32(phy->mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); + + /* delay 1us to wait DIFZ stable */ + udelay(1); + + /* release DIFZ */ + clrbits_le32(phy->mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); +} + +static int mtk_phy_power_on(struct phy *phy) +{ + struct mtk_ufs_phy *ufs_phy = dev_get_priv(phy->dev); + int ret; + + ret = clk_enable(ufs_phy->mp_clk); + if (ret < 0) { + dev_err(phy->dev, "failed to enable mp_clk\n"); + return ret; + } + + ret = clk_enable(ufs_phy->unipro_clk); + if (ret < 0) { + dev_err(phy->dev, "failed to enable unipro_clk %d\n", ret); + clk_disable(ufs_phy->unipro_clk); + return ret; + } + + ufs_mtk_phy_set_active(ufs_phy); + + return 0; +} + +static int mtk_phy_power_off(struct phy *phy) +{ + struct mtk_ufs_phy *ufs_phy = dev_get_priv(phy->dev); + + /* Set PHY to Deep Hibernate mode */ + setbits_le32(ufs_phy->mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); + + /* force DA_MP_RX0_SQ_EN */ + setbits_le32(ufs_phy->mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); + clrbits_le32(ufs_phy->mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); + + /* force DA_MP_CDR_ISO_EN */ + setbits_le32(ufs_phy->mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); + setbits_le32(ufs_phy->mmio + MP_LN_RX_44, CDR_ISO_EN); + + /* force DA_MP_CDR_PWR_ON */ + setbits_le32(ufs_phy->mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); + clrbits_le32(ufs_phy->mmio + MP_LN_RX_44, CDR_PWR_ON); + + /* force DA_MP_PLL_ISO_EN */ + setbits_le32(ufs_phy->mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); + setbits_le32(ufs_phy->mmio + MP_GLB_DIG_8C, PLL_ISO_EN); + + /* force DA_MP_PLL_PWR_ON */ + setbits_le32(ufs_phy->mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); + clrbits_le32(ufs_phy->mmio + MP_GLB_DIG_8C, PLL_PWR_ON); + + return 0; +} + +static const struct phy_ops mtk_ufs_phy_ops = { + .power_on = mtk_phy_power_on, + .power_off = mtk_phy_power_off, +}; + +static int mtk_ufs_phy_probe(struct udevice *dev) +{ + struct mtk_ufs_phy *phy = dev_get_priv(dev); + fdt_addr_t addr; + int ret; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -ENOMEM; + + phy->dev = dev; + phy->mmio = map_sysmem(addr, 0); + + phy->mp_clk = devm_clk_get(dev, "mp"); + if (IS_ERR(phy->mp_clk)) { + ret = PTR_ERR(phy->mp_clk); + dev_err(dev, "Failed to get mp clock (ret=%d)\n", ret); + return ret; + } + + phy->unipro_clk = devm_clk_get(dev, "unipro"); + if (IS_ERR(phy->unipro_clk)) { + ret = PTR_ERR(phy->unipro_clk); + dev_err(dev, "Failed to get unipro clock (ret=%d)\n", ret); + return ret; + } + + return 0; +} + +static const struct udevice_id mtk_ufs_phy_id_table[] = { + {.compatible = "mediatek,mt8183-ufsphy"}, + {}, +}; + +U_BOOT_DRIVER(mtk_ufs_phy) = { + .name = "mtk-ufs_phy", + .id = UCLASS_PHY, + .of_match = mtk_ufs_phy_id_table, + .ops = &mtk_ufs_phy_ops, + .probe = mtk_ufs_phy_probe, + .priv_auto = sizeof(struct mtk_ufs_phy), +}; -- cgit v1.3.1 From 47905f28468e3524cb5f775f52928cdcc568815a Mon Sep 17 00:00:00 2001 From: Julien Stephan Date: Tue, 3 Feb 2026 10:21:26 +0100 Subject: drivers: ufs: remove unused ufs_post_bind() declaration Commit 067c1b033282 ("ufs: Call ufs_scsi_bind() from uclass .post_bind") inlined ufs_scsi_bind() into ufs_post_bind() as trivial device_bind_driver() call. ufs_scsi_bind() is no longer referenced anywhere in the codebase, so drop its declaration from include/ufs.h. Drivers used to include to include prototype of ufs_scsi_bind() function, so we can now safely remove such includes. Fixes: 067c1b033282 ("ufs: Call ufs_scsi_bind() from uclass .post_bind") Signed-off-by: Julien Stephan Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260203-cleanup-ufs-header-v1-1-4c10424485f0@baylibre.com Signed-off-by: Neil Armstrong --- drivers/ufs/cdns-platform.c | 1 - drivers/ufs/ufs-amd-versal2.c | 1 - drivers/ufs/ufs-pci.c | 1 - drivers/ufs/ufs-qcom.c | 1 - drivers/ufs/ufs-renesas-rcar-gen5.c | 1 - drivers/ufs/ufs-renesas.c | 1 - drivers/ufs/ufs-rockchip.c | 1 - drivers/ufs/ufshcd-dwc.c | 1 - include/ufs.h | 9 --------- 9 files changed, 17 deletions(-) (limited to 'drivers') diff --git a/drivers/ufs/cdns-platform.c b/drivers/ufs/cdns-platform.c index 87d9c5bad79..40883a187b0 100644 --- a/drivers/ufs/cdns-platform.c +++ b/drivers/ufs/cdns-platform.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c index dd62c9819ba..6c949b2ca76 100644 --- a/drivers/ufs/ufs-amd-versal2.c +++ b/drivers/ufs/ufs-amd-versal2.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include diff --git a/drivers/ufs/ufs-pci.c b/drivers/ufs/ufs-pci.c index 5b9c72a695d..e1e010d027c 100644 --- a/drivers/ufs/ufs-pci.c +++ b/drivers/ufs/ufs-pci.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include "ufs.h" diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c index ee43958d5d8..dc40ee62daf 100644 --- a/drivers/ufs/ufs-qcom.c +++ b/drivers/ufs/ufs-qcom.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include diff --git a/drivers/ufs/ufs-renesas-rcar-gen5.c b/drivers/ufs/ufs-renesas-rcar-gen5.c index cc53e91449c..a21ae3f390e 100644 --- a/drivers/ufs/ufs-renesas-rcar-gen5.c +++ b/drivers/ufs/ufs-renesas-rcar-gen5.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include diff --git a/drivers/ufs/ufs-renesas.c b/drivers/ufs/ufs-renesas.c index 5652309911e..a206e3c6d58 100644 --- a/drivers/ufs/ufs-renesas.c +++ b/drivers/ufs/ufs-renesas.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include diff --git a/drivers/ufs/ufs-rockchip.c b/drivers/ufs/ufs-rockchip.c index 0384244387d..643a6ffb9bc 100644 --- a/drivers/ufs/ufs-rockchip.c +++ b/drivers/ufs/ufs-rockchip.c @@ -13,7 +13,6 @@ #include #include #include -#include #include "ufs.h" #include "unipro.h" diff --git a/drivers/ufs/ufshcd-dwc.c b/drivers/ufs/ufshcd-dwc.c index 3f62e59a060..98422d742a0 100644 --- a/drivers/ufs/ufshcd-dwc.c +++ b/drivers/ufs/ufshcd-dwc.c @@ -7,7 +7,6 @@ */ #include #include -#include #include #include #include diff --git a/include/ufs.h b/include/ufs.h index 702b8359dbd..f6e27d90e43 100644 --- a/include/ufs.h +++ b/include/ufs.h @@ -20,13 +20,4 @@ int ufs_probe(void); */ int ufs_probe_dev(int index); -/* - * ufs_scsi_bind() - Create a new scsi device as a child of the UFS device and - * bind it to the ufs_scsi driver - * @ufs_dev: UFS device - * @scsi_devp: Pointer to scsi device - * - * Return: 0 if Ok, -ve on error - */ -int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp); #endif -- cgit v1.3.1 From 39e1ccc777563d8c769531f1dfce24d38d023086 Mon Sep 17 00:00:00 2001 From: Romain Gantois Date: Tue, 17 Feb 2026 10:27:52 +0100 Subject: dm: core: Don't allow ofnode_to_fdt() to return NULL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ofnode_to_fdt() function may return a NULL pointer in multiple cases. Or, this function's return value is often passed directly to functions such as fdt_getprop() which end up dereferencing it, thus causing a NULL pointer exception. Don't allow ofnode_to_fdt() to return NULL, to avoid a NULL pointer dereference. Reviewed-by: Raphaël Gallais-Pou Signed-off-by: Romain Gantois Reviewed-by: Simon Glass --- drivers/core/ofnode.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index cf1cf8abfbe..3a36b6fdd03 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -164,15 +164,20 @@ void *ofnode_lookup_fdt(ofnode node) void *ofnode_to_fdt(ofnode node) { + void *fdt; + #ifdef OF_CHECKS if (of_live_active()) - return NULL; + panic("%s called with live tree in use!\n", __func__); #endif if (CONFIG_IS_ENABLED(OFNODE_MULTI_TREE) && ofnode_valid(node)) - return ofnode_lookup_fdt(node); + fdt = ofnode_lookup_fdt(node); + else + fdt = (void *)gd->fdt_blob; + + assert(fdt); - /* Use the control FDT by default */ - return (void *)gd->fdt_blob; + return fdt; } /** -- cgit v1.3.1 From e15b78bcf72bae42c7d198dfac5317c1058b8c26 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Mon, 16 Feb 2026 12:28:39 -0500 Subject: drivers: cpu: fix syntax error in Kconfig documentation Replace then -> they so that the sentence makes sense. Signed-off-by: Hugo Villeneuve Reviewed-by: Quentin Schulz --- drivers/cpu/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig index 4cc3679c009..6a96be94de4 100644 --- a/drivers/cpu/Kconfig +++ b/drivers/cpu/Kconfig @@ -3,7 +3,7 @@ config CPU help This allows drivers to be provided for CPUs and their type to be specified in the board's device tree. For boards which support - multiple CPUs, then normally have to be set up in U-Boot so that + multiple CPUs, they normally have to be set up in U-Boot so that they can work correctly in the OS. This provides a framework for finding out information about available CPUs and making changes. -- cgit v1.3.1 From 15e2bacc308d1ea2f50c53f8116fd15ba6c4af6e Mon Sep 17 00:00:00 2001 From: Philip Molloy Date: Thu, 26 Feb 2026 11:11:50 +0000 Subject: treewide: Remove Timesys from ADI ADSP maintenance After years of developing the ADI ADSP platform, Timesys was purchased by another company and is no longer contracted to maintain the platform. Signed-off-by: Philip Molloy Reviewed-by: Greg Malysa --- arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h | 4 +--- arch/arm/include/asm/arch-adi/sc5xx/soc.h | 4 +--- arch/arm/include/asm/arch-adi/sc5xx/spl.h | 4 +--- arch/arm/mach-sc5xx/Kconfig | 5 +---- arch/arm/mach-sc5xx/Makefile | 5 +---- arch/arm/mach-sc5xx/config.mk | 5 +---- arch/arm/mach-sc5xx/init/Makefile | 5 +---- arch/arm/mach-sc5xx/init/clkinit.c | 4 +--- arch/arm/mach-sc5xx/init/clkinit.h | 4 +--- arch/arm/mach-sc5xx/init/dmcinit.c | 4 +--- arch/arm/mach-sc5xx/init/dmcinit.h | 4 +--- arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h | 4 +--- arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h | 4 +--- arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h | 4 +--- arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h | 4 +--- arch/arm/mach-sc5xx/rcu.c | 3 +-- arch/arm/mach-sc5xx/sc57x.c | 4 +--- arch/arm/mach-sc5xx/sc58x.c | 4 +--- arch/arm/mach-sc5xx/sc59x.c | 4 +--- arch/arm/mach-sc5xx/sc59x_64.c | 4 +--- arch/arm/mach-sc5xx/soc.c | 4 +--- arch/arm/mach-sc5xx/spl.c | 4 +--- drivers/clk/adi/Kconfig | 5 +---- drivers/clk/adi/Makefile | 5 +---- drivers/clk/adi/clk-adi-pll.c | 2 +- drivers/clk/adi/clk-adi-sc57x.c | 2 +- drivers/clk/adi/clk-adi-sc58x.c | 2 +- drivers/clk/adi/clk-adi-sc594.c | 2 +- drivers/clk/adi/clk-adi-sc598.c | 2 +- drivers/clk/adi/clk-shared.c | 2 +- drivers/clk/adi/clk.h | 2 +- drivers/dma/adi_dma.c | 5 +---- drivers/gpio/adp5588_gpio.c | 4 +--- drivers/gpio/gpio-adi-adsp.c | 3 +-- drivers/i2c/adi_i2c.c | 4 +--- drivers/mmc/adi_sdhci.c | 4 +--- drivers/net/dwc_eth_qos_adi.c | 3 +-- drivers/pinctrl/pinctrl-adi-adsp.c | 3 +-- drivers/remoteproc/adi_sc5xx_rproc.c | 4 +--- drivers/serial/serial_adi_uart4.c | 4 +--- drivers/spi/adi_spi3.c | 6 +----- drivers/timer/adi_sc5xx_timer.c | 3 +-- drivers/usb/musb-new/sc5xx.c | 2 +- drivers/watchdog/adi_wdt.c | 4 +--- include/dt-bindings/clock/adi-sc5xx-clock.h | 4 +--- include/dt-bindings/pinctrl/adi-adsp.h | 4 +--- 46 files changed, 46 insertions(+), 126 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h b/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h index 683e3d412ce..c80de67d7ae 100644 --- a/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h +++ b/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #ifndef ARCH_ADI_SC5XX_SC5XX_H #define ARCH_ADI_SC5XX_SC5XX_H diff --git a/arch/arm/include/asm/arch-adi/sc5xx/soc.h b/arch/arm/include/asm/arch-adi/sc5xx/soc.h index 430dbe2dae4..065d272acab 100644 --- a/arch/arm/include/asm/arch-adi/sc5xx/soc.h +++ b/arch/arm/include/asm/arch-adi/sc5xx/soc.h @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #ifndef BOARD_ADI_COMMON_SOC_H diff --git a/arch/arm/include/asm/arch-adi/sc5xx/spl.h b/arch/arm/include/asm/arch-adi/sc5xx/spl.h index c215e6b892a..077667daa10 100644 --- a/arch/arm/include/asm/arch-adi/sc5xx/spl.h +++ b/arch/arm/include/asm/arch-adi/sc5xx/spl.h @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #ifndef ARCH_ADI_SC5XX_SPL_H #define ARCH_ADI_SC5XX_SPL_H diff --git a/arch/arm/mach-sc5xx/Kconfig b/arch/arm/mach-sc5xx/Kconfig index ec1d5539dc9..1486656b36b 100644 --- a/arch/arm/mach-sc5xx/Kconfig +++ b/arch/arm/mach-sc5xx/Kconfig @@ -2,10 +2,7 @@ # # (C) Copyright 2022 - Analog Devices, Inc. # -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison -# Contact: Greg Malysa +# Written by Timesys Corporation # # All 32-bit platforms require SYS_ARM_CACHE_WRITETHROUGH diff --git a/arch/arm/mach-sc5xx/Makefile b/arch/arm/mach-sc5xx/Makefile index 47b28200a03..4aaf94f6b9f 100644 --- a/arch/arm/mach-sc5xx/Makefile +++ b/arch/arm/mach-sc5xx/Makefile @@ -2,10 +2,7 @@ # # (C) Copyright 2022 - Analog Devices, Inc. # -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison -# Contact: Greg Malysa +# Written by Timesys Corporation # obj-y += soc.o init/ diff --git a/arch/arm/mach-sc5xx/config.mk b/arch/arm/mach-sc5xx/config.mk index b4eb1c42810..85889f54e89 100644 --- a/arch/arm/mach-sc5xx/config.mk +++ b/arch/arm/mach-sc5xx/config.mk @@ -2,10 +2,7 @@ # # (C) Copyright 2022 - Analog Devices, Inc. # -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison -# Contact: Greg Malysa +# Written by Timesys Corporation # ifdef CONFIG_XPL_BUILD diff --git a/arch/arm/mach-sc5xx/init/Makefile b/arch/arm/mach-sc5xx/init/Makefile index 9d4920fe076..6f99bdaeb72 100644 --- a/arch/arm/mach-sc5xx/init/Makefile +++ b/arch/arm/mach-sc5xx/init/Makefile @@ -2,10 +2,7 @@ # # (C) Copyright 2022 - Analog Devices, Inc. # -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison -# Contact: Greg Malysa +# Written by Timesys Corporation # obj-y += dmcinit.o clkinit.o diff --git a/arch/arm/mach-sc5xx/init/clkinit.c b/arch/arm/mach-sc5xx/init/clkinit.c index ae53cd61efd..3dcba33bd1b 100644 --- a/arch/arm/mach-sc5xx/init/clkinit.c +++ b/arch/arm/mach-sc5xx/init/clkinit.c @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #include diff --git a/arch/arm/mach-sc5xx/init/clkinit.h b/arch/arm/mach-sc5xx/init/clkinit.h index b05f4325bfc..035a766d266 100644 --- a/arch/arm/mach-sc5xx/init/clkinit.h +++ b/arch/arm/mach-sc5xx/init/clkinit.h @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #ifndef CLKINIT_H_ diff --git a/arch/arm/mach-sc5xx/init/dmcinit.c b/arch/arm/mach-sc5xx/init/dmcinit.c index 30b77aee459..2bf2cc53a9f 100644 --- a/arch/arm/mach-sc5xx/init/dmcinit.c +++ b/arch/arm/mach-sc5xx/init/dmcinit.c @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #include diff --git a/arch/arm/mach-sc5xx/init/dmcinit.h b/arch/arm/mach-sc5xx/init/dmcinit.h index 46ff729282d..6ddabdbf325 100644 --- a/arch/arm/mach-sc5xx/init/dmcinit.h +++ b/arch/arm/mach-sc5xx/init/dmcinit.h @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #ifndef DMCINIT_H_ diff --git a/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h b/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h index a5838370555..0cb1184c236 100644 --- a/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h +++ b/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #ifndef IS43TR16512BL_H diff --git a/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h b/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h index 882777521b8..7c1381e5a18 100644 --- a/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h +++ b/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #ifndef MT41K128M16JT_H diff --git a/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h b/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h index 5735b87871c..21e3f44ccb5 100644 --- a/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h +++ b/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #ifndef MT41K512M16HA_H diff --git a/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h b/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h index 5ada7f2985b..b0d012818cf 100644 --- a/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h +++ b/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #ifndef MT47H128M16RT_H diff --git a/arch/arm/mach-sc5xx/rcu.c b/arch/arm/mach-sc5xx/rcu.c index 49357501a93..c9911be91d6 100644 --- a/arch/arm/mach-sc5xx/rcu.c +++ b/arch/arm/mach-sc5xx/rcu.c @@ -2,9 +2,8 @@ /* * (C) Copyright 2024 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Ian Roberts */ #include diff --git a/arch/arm/mach-sc5xx/sc57x.c b/arch/arm/mach-sc5xx/sc57x.c index b0587686d73..02b04cd1b2f 100644 --- a/arch/arm/mach-sc5xx/sc57x.c +++ b/arch/arm/mach-sc5xx/sc57x.c @@ -2,10 +2,8 @@ /* * (C) Copyright 2024 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #include diff --git a/arch/arm/mach-sc5xx/sc58x.c b/arch/arm/mach-sc5xx/sc58x.c index 0f892774309..c981cafd986 100644 --- a/arch/arm/mach-sc5xx/sc58x.c +++ b/arch/arm/mach-sc5xx/sc58x.c @@ -2,10 +2,8 @@ /* * (C) Copyright 2024 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #include diff --git a/arch/arm/mach-sc5xx/sc59x.c b/arch/arm/mach-sc5xx/sc59x.c index 174c6f5c445..675f8c7d69a 100644 --- a/arch/arm/mach-sc5xx/sc59x.c +++ b/arch/arm/mach-sc5xx/sc59x.c @@ -2,10 +2,8 @@ /* * (C) Copyright 2024 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #include diff --git a/arch/arm/mach-sc5xx/sc59x_64.c b/arch/arm/mach-sc5xx/sc59x_64.c index 001747f223d..a8402075d0a 100644 --- a/arch/arm/mach-sc5xx/sc59x_64.c +++ b/arch/arm/mach-sc5xx/sc59x_64.c @@ -2,10 +2,8 @@ /* * (C) Copyright 2024 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #include diff --git a/arch/arm/mach-sc5xx/soc.c b/arch/arm/mach-sc5xx/soc.c index 8f13127a660..cf8ff0dc3af 100644 --- a/arch/arm/mach-sc5xx/soc.c +++ b/arch/arm/mach-sc5xx/soc.c @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #include diff --git a/arch/arm/mach-sc5xx/spl.c b/arch/arm/mach-sc5xx/spl.c index 68e0310f5af..c529829420d 100644 --- a/arch/arm/mach-sc5xx/spl.c +++ b/arch/arm/mach-sc5xx/spl.c @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #include diff --git a/drivers/clk/adi/Kconfig b/drivers/clk/adi/Kconfig index 5745bedf88c..94cf744305f 100644 --- a/drivers/clk/adi/Kconfig +++ b/drivers/clk/adi/Kconfig @@ -2,10 +2,7 @@ # # (C) Copyright 2022 - Analog Devices, Inc. # -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison -# Contact: Greg Malysa +# Written by Timesys Corporation # config COMMON_CLK_ADI_SHARED diff --git a/drivers/clk/adi/Makefile b/drivers/clk/adi/Makefile index f3f1fd92e5f..b7664fe1da0 100644 --- a/drivers/clk/adi/Makefile +++ b/drivers/clk/adi/Makefile @@ -2,10 +2,7 @@ # # (C) Copyright 2022 - Analog Devices, Inc. # -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison -# Contact: Greg Malysa +# Written by Timesys Corporation # obj-$(CONFIG_COMMON_CLK_ADI_SHARED) += clk-shared.o clk-adi-pll.o diff --git a/drivers/clk/adi/clk-adi-pll.c b/drivers/clk/adi/clk-adi-pll.c index 372baa9c11b..34818cb1af0 100644 --- a/drivers/clk/adi/clk-adi-pll.c +++ b/drivers/clk/adi/clk-adi-pll.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Author: Greg Malysa * diff --git a/drivers/clk/adi/clk-adi-sc57x.c b/drivers/clk/adi/clk-adi-sc57x.c index b17563f0444..3eeb3109bd6 100644 --- a/drivers/clk/adi/clk-adi-sc57x.c +++ b/drivers/clk/adi/clk-adi-sc57x.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Author: Greg Malysa * diff --git a/drivers/clk/adi/clk-adi-sc58x.c b/drivers/clk/adi/clk-adi-sc58x.c index 05a0feddec7..776e4748c42 100644 --- a/drivers/clk/adi/clk-adi-sc58x.c +++ b/drivers/clk/adi/clk-adi-sc58x.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Author: Greg Malysa * diff --git a/drivers/clk/adi/clk-adi-sc594.c b/drivers/clk/adi/clk-adi-sc594.c index c80bbf9728d..6749c6d0382 100644 --- a/drivers/clk/adi/clk-adi-sc594.c +++ b/drivers/clk/adi/clk-adi-sc594.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Author: Greg Malysa * diff --git a/drivers/clk/adi/clk-adi-sc598.c b/drivers/clk/adi/clk-adi-sc598.c index d4a16ac9603..05176f2fa85 100644 --- a/drivers/clk/adi/clk-adi-sc598.c +++ b/drivers/clk/adi/clk-adi-sc598.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Author: Greg Malysa * diff --git a/drivers/clk/adi/clk-shared.c b/drivers/clk/adi/clk-shared.c index dcadcafa9d2..afd5f46c845 100644 --- a/drivers/clk/adi/clk-shared.c +++ b/drivers/clk/adi/clk-shared.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Author: Greg Malysa */ diff --git a/drivers/clk/adi/clk.h b/drivers/clk/adi/clk.h index f230205c311..acd4e384746 100644 --- a/drivers/clk/adi/clk.h +++ b/drivers/clk/adi/clk.h @@ -2,7 +2,7 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Author: Greg Malysa * diff --git a/drivers/dma/adi_dma.c b/drivers/dma/adi_dma.c index 28afe488db0..9244ba22068 100644 --- a/drivers/dma/adi_dma.c +++ b/drivers/dma/adi_dma.c @@ -4,11 +4,8 @@ * * (C) Copyright 2024 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - * Contact: Ian Roberts * */ #include diff --git a/drivers/gpio/adp5588_gpio.c b/drivers/gpio/adp5588_gpio.c index 36304e48893..a5b2ccfea17 100644 --- a/drivers/gpio/adp5588_gpio.c +++ b/drivers/gpio/adp5588_gpio.c @@ -5,10 +5,8 @@ * * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa * * Based on Michael Hennerich's Linux driver: * Michael Hennerich diff --git a/drivers/gpio/gpio-adi-adsp.c b/drivers/gpio/gpio-adi-adsp.c index 0ce00572e08..af54354fa76 100644 --- a/drivers/gpio/gpio-adi-adsp.c +++ b/drivers/gpio/gpio-adi-adsp.c @@ -2,10 +2,9 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Author: Greg Malysa - * Additional Contact: Nathan Barrett-Morrison */ #include diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c index 4cddcfa6b7f..c80a1517b5f 100644 --- a/drivers/i2c/adi_i2c.c +++ b/drivers/i2c/adi_i2c.c @@ -2,12 +2,10 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Converted to driver model by Nathan Barrett-Morrison * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa */ #include diff --git a/drivers/mmc/adi_sdhci.c b/drivers/mmc/adi_sdhci.c index f58897b5218..2bcd16ec3ba 100644 --- a/drivers/mmc/adi_sdhci.c +++ b/drivers/mmc/adi_sdhci.c @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa * * Based on Rockchip's sdhci.c file */ diff --git a/drivers/net/dwc_eth_qos_adi.c b/drivers/net/dwc_eth_qos_adi.c index fee50a88156..b578225eaad 100644 --- a/drivers/net/dwc_eth_qos_adi.c +++ b/drivers/net/dwc_eth_qos_adi.c @@ -2,10 +2,9 @@ /** * (C) Copyright 2024 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Author: Greg Malysa - * Additional Contact: Nathan Barrett-Morrison */ #include diff --git a/drivers/pinctrl/pinctrl-adi-adsp.c b/drivers/pinctrl/pinctrl-adi-adsp.c index debf434212d..e39f88c8b26 100644 --- a/drivers/pinctrl/pinctrl-adi-adsp.c +++ b/drivers/pinctrl/pinctrl-adi-adsp.c @@ -2,10 +2,9 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Author: Greg Malysa - * Additional Contact: Nathan Barrett-Morrison * * dm pinctrl implementation for ADI ADSP SoCs * diff --git a/drivers/remoteproc/adi_sc5xx_rproc.c b/drivers/remoteproc/adi_sc5xx_rproc.c index 86acd1b98c7..b96603263a5 100644 --- a/drivers/remoteproc/adi_sc5xx_rproc.c +++ b/drivers/remoteproc/adi_sc5xx_rproc.c @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa * * Analog Devices SC5xx remoteproc driver for loading code onto SHARC cores */ diff --git a/drivers/serial/serial_adi_uart4.c b/drivers/serial/serial_adi_uart4.c index 45f8315d0a0..24b2071d705 100644 --- a/drivers/serial/serial_adi_uart4.c +++ b/drivers/serial/serial_adi_uart4.c @@ -2,12 +2,10 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Converted to driver model by Nathan Barrett-Morrison * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa * */ diff --git a/drivers/spi/adi_spi3.c b/drivers/spi/adi_spi3.c index 2125d25561a..bc66dfbfdd6 100644 --- a/drivers/spi/adi_spi3.c +++ b/drivers/spi/adi_spi3.c @@ -2,14 +2,10 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Converted to driver model by Nathan Barrett-Morrison * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - * Contact: Ian Roberts - * Contact: Piotr Wojtaszczyk * */ diff --git a/drivers/timer/adi_sc5xx_timer.c b/drivers/timer/adi_sc5xx_timer.c index 11c098434a8..d9aef3da11e 100644 --- a/drivers/timer/adi_sc5xx_timer.c +++ b/drivers/timer/adi_sc5xx_timer.c @@ -2,12 +2,11 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Converted to driver model by Nathan Barrett-Morrison * * Author: Greg Malysa - * Additional Contact: Nathan Barrett-Morrison * * dm timer implementation for ADI ADSP-SC5xx SoCs * diff --git a/drivers/usb/musb-new/sc5xx.c b/drivers/usb/musb-new/sc5xx.c index 16201480b43..991846818a2 100644 --- a/drivers/usb/musb-new/sc5xx.c +++ b/drivers/usb/musb-new/sc5xx.c @@ -4,7 +4,7 @@ * * ADI SC5XX MUSB "glue layer" * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Loosely ported from Linux driver: * Author: Nathan Barrett-Morrison diff --git a/drivers/watchdog/adi_wdt.c b/drivers/watchdog/adi_wdt.c index 6f5b3d5d042..7d7cf98b55e 100644 --- a/drivers/watchdog/adi_wdt.c +++ b/drivers/watchdog/adi_wdt.c @@ -2,12 +2,10 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * * Converted to driver model by Nathan Barrett-Morrison * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa * * adi_wtd.c - driver for ADI on-chip watchdog * diff --git a/include/dt-bindings/clock/adi-sc5xx-clock.h b/include/dt-bindings/clock/adi-sc5xx-clock.h index 4a5373d1141..94ab225d3b7 100644 --- a/include/dt-bindings/clock/adi-sc5xx-clock.h +++ b/include/dt-bindings/clock/adi-sc5xx-clock.h @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa * */ diff --git a/include/dt-bindings/pinctrl/adi-adsp.h b/include/dt-bindings/pinctrl/adi-adsp.h index 7dc8a1ef5c4..afe68e836e7 100644 --- a/include/dt-bindings/pinctrl/adi-adsp.h +++ b/include/dt-bindings/pinctrl/adi-adsp.h @@ -2,10 +2,8 @@ /* * (C) Copyright 2022 - Analog Devices, Inc. * - * Written and/or maintained by Timesys Corporation + * Written by Timesys Corporation * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa * */ -- cgit v1.3.1 From 0b429f7c6b9de24eb4b8d8ddab74b0020994c405 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Thu, 5 Feb 2026 00:35:40 +0100 Subject: video: stm32: dsi: add .of_to_plat callback Drivers should extract device-tree data before probing via the .of_to_plat hook. Implement it for stm32_dsi driver. By doing so, it also solve a variable shadowing in stm32_dsi_probe() where &clk was used as peripheral clock and ref clock. For readability some struct have been renamed such as: * struct stm32_dsi_priv *dsi -> struct stm32_dsi_priv *priv * struct clk clk -> struct clk pclk Signed-off-by: Raphael Gallais-Pou Reviewed-by: Patrick Delaunay --- drivers/video/stm32/stm32_dsi.c | 164 ++++++++++++++++++++++------------------ 1 file changed, 89 insertions(+), 75 deletions(-) (limited to 'drivers') diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c index 438ed41e8d5..65a91f5cff7 100644 --- a/drivers/video/stm32/stm32_dsi.c +++ b/drivers/video/stm32/stm32_dsi.c @@ -84,42 +84,48 @@ enum dsi_color { /* Timeout for regulator on/off, pll lock/unlock & fifo empty */ #define TIMEOUT_US 200000 -struct stm32_dsi_priv { +struct stm32_dsi_plat { struct mipi_dsi_device device; void __iomem *base; struct udevice *panel; + struct udevice *vdd_reg; + struct udevice *dsi_host; + struct reset_ctl rst; + struct clk pclk; + struct clk refclk; +}; + +struct stm32_dsi_priv { u32 pllref_clk; u32 hw_version; int lane_min_kbps; int lane_max_kbps; - struct udevice *vdd_reg; - struct udevice *dsi_host; }; -static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val) +static inline void dsi_write(void __iomem *base, u32 reg, u32 val) { - writel(val, dsi->base + reg); + writel(val, base + reg); } -static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg) +static inline u32 dsi_read(void __iomem *base, u32 reg) { - return readl(dsi->base + reg); + return readl(base + reg); } -static inline void dsi_set(struct stm32_dsi_priv *dsi, u32 reg, u32 mask) +static inline void dsi_set(void __iomem *base, u32 reg, u32 mask) { - dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); + dsi_write(base, reg, dsi_read(base, reg) | mask); } -static inline void dsi_clear(struct stm32_dsi_priv *dsi, u32 reg, u32 mask) +static inline void dsi_clear(void __iomem *base, u32 reg, u32 mask) { - dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask); + dsi_write(base, reg, dsi_read(base, reg) & ~mask); } -static inline void dsi_update_bits(struct stm32_dsi_priv *dsi, u32 reg, +static inline void dsi_update_bits(void __iomem *base, u32 reg, u32 mask, u32 val) { - dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); + dsi_write(base, reg, (dsi_read(base, reg) & ~mask) | val); } static enum dsi_color dsi_color_from_mipi(u32 fmt) @@ -210,14 +216,14 @@ static int dsi_phy_init(void *priv_data) { struct mipi_dsi_device *device = priv_data; struct udevice *dev = device->dev; - struct stm32_dsi_priv *dsi = dev_get_priv(dev); + struct stm32_dsi_plat *dsi = dev_get_plat(dev); u32 val; int ret; dev_dbg(dev, "Initialize DSI physical layer\n"); /* Enable the regulator */ - dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN); + dsi_set(dsi->base, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN); ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS, TIMEOUT_US); if (ret) { @@ -226,7 +232,7 @@ static int dsi_phy_init(void *priv_data) } /* Enable the DSI PLL & wait for its lock */ - dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN); + dsi_set(dsi->base, DSI_WRPCR, WRPCR_PLLEN); ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS, TIMEOUT_US); if (ret) { @@ -241,7 +247,7 @@ static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags) { struct mipi_dsi_device *device = priv_data; struct udevice *dev = device->dev; - struct stm32_dsi_priv *dsi = dev_get_priv(dev); + struct stm32_dsi_plat *dsi = dev_get_plat(dev); dev_dbg(dev, "Set mode %p enable %ld\n", dsi, mode_flags & MIPI_DSI_MODE_VIDEO); @@ -256,9 +262,9 @@ static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags) */ if (mode_flags & MIPI_DSI_MODE_VIDEO) - dsi_set(dsi, DSI_WCR, WCR_DSIEN); + dsi_set(dsi->base, DSI_WCR, WCR_DSIEN); else - dsi_clear(dsi, DSI_WCR, WCR_DSIEN); + dsi_clear(dsi->base, DSI_WCR, WCR_DSIEN); } static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings, @@ -266,32 +272,33 @@ static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings, { struct mipi_dsi_device *device = priv_data; struct udevice *dev = device->dev; - struct stm32_dsi_priv *dsi = dev_get_priv(dev); + struct stm32_dsi_plat *plat = dev_get_plat(dev); + struct stm32_dsi_priv *priv = dev_get_priv(dev); int idf, ndiv, odf, pll_in_khz, pll_out_khz; int ret, bpp; u32 val; /* Update lane capabilities according to hw version */ - dsi->lane_min_kbps = LANE_MIN_KBPS; - dsi->lane_max_kbps = LANE_MAX_KBPS; - if (dsi->hw_version == HWVER_131) { - dsi->lane_min_kbps *= 2; - dsi->lane_max_kbps *= 2; + priv->lane_min_kbps = LANE_MIN_KBPS; + priv->lane_max_kbps = LANE_MAX_KBPS; + if (priv->hw_version == HWVER_131) { + priv->lane_min_kbps *= 2; + priv->lane_max_kbps *= 2; } - pll_in_khz = dsi->pllref_clk / 1000; + pll_in_khz = priv->pllref_clk / 1000; /* Compute requested pll out */ bpp = mipi_dsi_pixel_format_to_bpp(format); pll_out_khz = (timings->pixelclock.typ / 1000) * bpp / lanes; /* Add 20% to pll out to be higher than pixel bw (burst mode only) */ pll_out_khz = (pll_out_khz * 12) / 10; - if (pll_out_khz > dsi->lane_max_kbps) { - pll_out_khz = dsi->lane_max_kbps; + if (pll_out_khz > priv->lane_max_kbps) { + pll_out_khz = priv->lane_max_kbps; dev_warn(dev, "Warning max phy mbps is used\n"); } - if (pll_out_khz < dsi->lane_min_kbps) { - pll_out_khz = dsi->lane_min_kbps; + if (pll_out_khz < priv->lane_min_kbps) { + pll_out_khz = priv->lane_min_kbps; dev_warn(dev, "Warning min phy mbps is used\n"); } @@ -299,7 +306,7 @@ static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings, idf = 0; ndiv = 0; odf = 0; - ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz, + ret = dsi_pll_get_params(priv, pll_in_khz, pll_out_khz, &idf, &ndiv, &odf); if (ret) { dev_err(dev, "Warning dsi_pll_get_params(): bad params\n"); @@ -310,18 +317,18 @@ static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings, pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf); /* Set the PLL division factors */ - dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF, + dsi_update_bits(plat->base, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF, (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16)); /* Compute uix4 & set the bit period in high-speed mode */ val = 4000000 / pll_out_khz; - dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val); + dsi_update_bits(plat->base, DSI_WPCR0, WPCR0_UIX4, val); /* Select video mode by resetting DSIM bit */ - dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM); + dsi_clear(plat->base, DSI_WCFGR, WCFGR_DSIM); /* Select the color coding */ - dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX, + dsi_update_bits(plat->base, DSI_WCFGR, WCFGR_COLMUX, dsi_color_from_mipi(format) << 1); *lane_mbps = pll_out_khz / 1000; @@ -340,27 +347,27 @@ static const struct mipi_dsi_phy_ops dsi_stm_phy_ops = { static int stm32_dsi_attach(struct udevice *dev) { - struct stm32_dsi_priv *priv = dev_get_priv(dev); - struct mipi_dsi_device *device = &priv->device; + struct stm32_dsi_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = &plat->device; struct mipi_dsi_panel_plat *mplat; struct display_timing timings; int ret; - ret = uclass_first_device_err(UCLASS_PANEL, &priv->panel); + ret = uclass_first_device_err(UCLASS_PANEL, &plat->panel); if (ret) { dev_err(dev, "panel device error %d\n", ret); return ret; } - mplat = dev_get_plat(priv->panel); - mplat->device = &priv->device; + mplat = dev_get_plat(plat->panel); + mplat->device = &plat->device; device->lanes = mplat->lanes; device->format = mplat->format; device->mode_flags = mplat->mode_flags; - ret = panel_get_display_timing(priv->panel, &timings); + ret = panel_get_display_timing(plat->panel, &timings); if (ret) { - ret = ofnode_decode_display_timing(dev_ofnode(priv->panel), + ret = ofnode_decode_display_timing(dev_ofnode(plat->panel), 0, &timings); if (ret) { dev_err(dev, "decode display timing error %d\n", ret); @@ -368,13 +375,13 @@ static int stm32_dsi_attach(struct udevice *dev) } } - ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host); + ret = uclass_get_device(UCLASS_DSI_HOST, 0, &plat->dsi_host); if (ret) { dev_err(dev, "No video dsi host detected %d\n", ret); return ret; } - ret = dsi_host_init(priv->dsi_host, device, &timings, 2, + ret = dsi_host_init(plat->dsi_host, device, &timings, 2, &dsi_stm_phy_ops); if (ret) { dev_err(dev, "failed to initialize mipi dsi host\n"); @@ -386,17 +393,17 @@ static int stm32_dsi_attach(struct udevice *dev) static int stm32_dsi_set_backlight(struct udevice *dev, int percent) { - struct stm32_dsi_priv *priv = dev_get_priv(dev); + struct stm32_dsi_plat *plat = dev_get_plat(dev); int ret; - ret = panel_enable_backlight(priv->panel); + ret = panel_enable_backlight(plat->panel); if (ret) { dev_err(dev, "panel %s enable backlight error %d\n", - priv->panel->name, ret); + plat->panel->name, ret); return ret; } - ret = dsi_host_enable(priv->dsi_host); + ret = dsi_host_enable(plat->dsi_host); if (ret) { dev_err(dev, "failed to enable mipi dsi host\n"); return ret; @@ -417,66 +424,71 @@ static int stm32_dsi_bind(struct udevice *dev) return dm_scan_fdt_dev(dev); } -static int stm32_dsi_probe(struct udevice *dev) +static int stm32_dsi_of_to_plat(struct udevice *dev) { - struct stm32_dsi_priv *priv = dev_get_priv(dev); - struct mipi_dsi_device *device = &priv->device; - struct reset_ctl rst; - struct clk clk; + struct stm32_dsi_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = &plat->device; int ret; device->dev = dev; - priv->base = dev_read_addr_ptr(dev); - if (!priv->base) { + plat->base = dev_read_addr_ptr(dev); + if (!plat->base) { dev_err(dev, "dsi dt register address error\n"); return -EINVAL; } ret = device_get_supply_regulator(dev, "phy-dsi-supply", - &priv->vdd_reg); + &plat->vdd_reg); if (ret && ret != -ENOENT) { dev_err(dev, "Warning: cannot get phy dsi supply\n"); return -ENODEV; } if (ret != -ENOENT) { - ret = regulator_set_enable(priv->vdd_reg, true); + ret = regulator_set_enable(plat->vdd_reg, true); if (ret) return ret; } - ret = clk_get_by_name(device->dev, "pclk", &clk); + ret = clk_get_by_name(device->dev, "pclk", &plat->pclk); if (ret) { dev_err(dev, "peripheral clock get error %d\n", ret); - goto err_reg; - } - - ret = clk_enable(&clk); - if (ret) { - dev_err(dev, "peripheral clock enable error %d\n", ret); - goto err_reg; + return ret; } - ret = clk_get_by_name(dev, "ref", &clk); + ret = clk_get_by_name(dev, "ref", &plat->refclk); if (ret) { dev_err(dev, "pll reference clock get error %d\n", ret); - goto err_clk; + return ret; } - priv->pllref_clk = (unsigned int)clk_get_rate(&clk); + ret = reset_get_by_index(device->dev, 0, &plat->rst); + if (ret) + dev_err(dev, "missing dsi hardware reset\n"); + + return ret; +} - ret = reset_get_by_index(device->dev, 0, &rst); +static int stm32_dsi_probe(struct udevice *dev) +{ + struct stm32_dsi_plat *plat = dev_get_plat(dev); + struct stm32_dsi_priv *priv = dev_get_priv(dev); + int ret; + + ret = clk_enable(&plat->pclk); if (ret) { - dev_err(dev, "missing dsi hardware reset\n"); - goto err_clk; + dev_err(dev, "peripheral clock enable error %d\n", ret); + goto err_reg; } + priv->pllref_clk = (unsigned int)clk_get_rate(&plat->refclk); + /* Reset */ - reset_deassert(&rst); + reset_deassert(&plat->rst); /* check hardware version */ - priv->hw_version = dsi_read(priv, DSI_VERSION) & VERSION; + priv->hw_version = dsi_read(plat->base, DSI_VERSION) & VERSION; if (priv->hw_version != HWVER_130 && priv->hw_version != HWVER_131) { dev_err(dev, "DSI version 0x%x not supported\n", priv->hw_version); @@ -489,9 +501,9 @@ static int stm32_dsi_probe(struct udevice *dev) return 0; err_clk: - clk_disable(&clk); + clk_disable(&plat->pclk); err_reg: - regulator_set_enable(priv->vdd_reg, false); + regulator_set_enable(plat->vdd_reg, false); return ret; } @@ -512,6 +524,8 @@ U_BOOT_DRIVER(stm32_dsi) = { .of_match = stm32_dsi_ids, .bind = stm32_dsi_bind, .probe = stm32_dsi_probe, + .of_to_plat = stm32_dsi_of_to_plat, .ops = &stm32_dsi_ops, + .plat_auto = sizeof(struct stm32_dsi_plat), .priv_auto = sizeof(struct stm32_dsi_priv), }; -- cgit v1.3.1 From 068d05ad5f82a58316e895fd1497cf10898b3beb Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Fri, 27 Feb 2026 17:28:30 +0530 Subject: pci: pcie_cdns_ti: enable PCIe root-complex mode for J784S4 SoC The PCIe Controllers on the J784S4 SoC support Root-Complex mode of operation. Hence, enable it. Signed-off-by: Siddharth Vadapalli Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream") --- drivers/pci/pcie_cdns_ti.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers') diff --git a/drivers/pci/pcie_cdns_ti.c b/drivers/pci/pcie_cdns_ti.c index 38804f1c09c..63d249c2506 100644 --- a/drivers/pci/pcie_cdns_ti.c +++ b/drivers/pci/pcie_cdns_ti.c @@ -860,6 +860,12 @@ static const struct pcie_cdns_ti_data j722s_pcie_rc_data = { .max_lanes = 1, }; +static const struct pcie_cdns_ti_data j784s4_pcie_rc_data = { + .mode = PCIE_MODE_RC, + .quirk_detect_quiet_flag = true, + .max_lanes = 4, +}; + static const struct udevice_id pcie_cdns_ti_ids[] = { { .compatible = "ti,j7200-pcie-host", @@ -873,6 +879,10 @@ static const struct udevice_id pcie_cdns_ti_ids[] = { .compatible = "ti,j722s-pcie-host", .data = (ulong)&j722s_pcie_rc_data, }, + { + .compatible = "ti,j784s4-pcie-host", + .data = (ulong)&j784s4_pcie_rc_data, + }, {}, }; -- cgit v1.3.1