From adc983b4d676e4ca958067f86bec1bb02cb17950 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 10:13:48 +0000 Subject: dm: pcie_fsl: Convert IS_ENABLED() run-time checking to #ifdef This can avoid build error: The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only defined on the platforms that select the CONFIG_FOO, while it's not defined on platforms that do not select the CONFIG_FOO. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 69 ++++++++++++++++++++++++++------------------------ 1 file changed, 36 insertions(+), 33 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 4d61a46cefb..1879d8104c2 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -299,8 +299,9 @@ static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx, out_be32(&pi->piwbear, 0); #endif - if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434)) - flag = 0; +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + flag = 0; +#endif flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; if (pf) @@ -401,47 +402,47 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) fsl_pcie_init_atmu(pcie); - if (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) { - val_32 = 0; - fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32); - val_32 &= ~0x03; - fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32); - udelay(1); - } +#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM + val_32 = 0; + fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32); + val_32 &= ~0x03; + fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32); + udelay(1); +#endif - if (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) { - u16 ltssm; - int i; +#ifdef CONFIG_FSL_PCIE_RESET + u16 ltssm; + int i; - if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + /* assert PCIe reset */ + setbits_be32(®s->pdb_stat, 0x08000000); + (void)in_be32(®s->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } else { + fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); + if (ltssm == 1) { /* assert PCIe reset */ setbits_be32(®s->pdb_stat, 0x08000000); (void)in_be32(®s->pdb_stat); - udelay(1000); + udelay(100); /* clear PCIe reset */ clrbits_be32(®s->pdb_stat, 0x08000000); asm("sync;isync"); - for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + for (i = 0; i < 100 && + !fsl_pcie_link_up(pcie); i++) udelay(1000); - } else { - fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); - if (ltssm == 1) { - /* assert PCIe reset */ - setbits_be32(®s->pdb_stat, 0x08000000); - (void)in_be32(®s->pdb_stat); - udelay(100); - /* clear PCIe reset */ - clrbits_be32(®s->pdb_stat, 0x08000000); - asm("sync;isync"); - for (i = 0; i < 100 && - !fsl_pcie_link_up(pcie); i++) - udelay(1000); - } } } +#endif - if (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) && - !fsl_pcie_link_up(pcie)) { +#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 + if (!fsl_pcie_link_up(pcie)) { serdes_corenet_t *srds_regs; srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; @@ -460,13 +461,15 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) udelay(1000); } } +#endif /* * The Read-Only Write Enable bit defaults to 1 instead of 0. * Set to 0 to protect the read-only registers. */ - if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815)) - clrbits_be32(®s->dbi_ro_wr_en, 0x01); +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + clrbits_be32(®s->dbi_ro_wr_en, 0x01); +#endif /* * Enable All Error Interrupts except -- cgit v1.3.1 From d18d06ac35229345a0af80977a408cfbe1d1015b Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 10:13:51 +0000 Subject: dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 17 +++++++++++++---- drivers/pci/pcie_fsl.h | 3 +++ 2 files changed, 16 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 1879d8104c2..1be50634674 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -503,14 +503,23 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) { ccsr_fsl_pci_t *regs = pcie->regs; + u32 classcode_reg; u32 val; - setbits_be32(®s->dbi_ro_wr_en, 0x01); - fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val); + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + classcode_reg = PCI_CLASS_REVISION; + setbits_be32(®s->dbi_ro_wr_en, 0x01); + } else { + classcode_reg = CSR_CLASSCODE; + } + + fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val); val &= 0xff; val |= PCI_CLASS_BRIDGE_PCI << 16; - fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val); - clrbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val); + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) + clrbits_be32(®s->dbi_ro_wr_en, 0x01); return 0; } diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 5eefc31fa9a..032775ca05d 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -9,6 +9,9 @@ #ifndef _PCIE_FSL_H_ #define _PCIE_FSL_H_ +/* GPEX CSR */ +#define CSR_CLASSCODE 0x474 + #ifdef CONFIG_SYS_FSL_PCI_VER_3_X #define FSL_PCIE_CAP_ID 0x70 #else -- cgit v1.3.1 From fbcb2ff5c6477c7d2ddc9f54967a5cfc21aefbed Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 10:13:54 +0000 Subject: dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 14 ++++++++++++-- drivers/pci/pcie_fsl.h | 7 +++++++ 2 files changed, 19 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 1be50634674..d3d2c191e5d 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -582,6 +582,7 @@ static int fsl_pcie_probe(struct udevice *dev) static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) { struct fsl_pcie *pcie = dev_get_priv(dev); + struct fsl_pcie_data *info; int ret; pcie->regs = dev_remap_addr(dev); @@ -596,7 +597,10 @@ static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) return ret; } - pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000; + info = (struct fsl_pcie_data *)dev_get_driver_data(dev); + pcie->info = info; + pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) - + info->block_offset) / info->stride; return 0; } @@ -606,8 +610,14 @@ static const struct dm_pci_ops fsl_pcie_ops = { .write_config = fsl_pcie_write_config, }; +static struct fsl_pcie_data t2080_data = { + .block_offset = 0x240000, + .block_offset_mask = 0x3fffff, + .stride = 0x10000, +}; + static const struct udevice_id fsl_pcie_ids[] = { - { .compatible = "fsl,pcie-t2080" }, + { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, { } }; diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 032775ca05d..dc8368d5592 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -43,6 +43,12 @@ #define LTSSM_L0_REV3 0x11 #define LTSSM_L0 0x16 +struct fsl_pcie_data { + u32 block_offset; /* Offset from CCSR of 1st controller */ + u32 block_offset_mask; /* Mask out the CCSR base */ + u32 stride; /* Offset stride between controllers */ +}; + struct fsl_pcie { int idx; struct udevice *bus; @@ -52,6 +58,7 @@ struct fsl_pcie { bool mode; /* RC&EP mode flag */ bool enabled; /* Enable status */ struct list_head list; + struct fsl_pcie_data *info; }; extern struct list_head fsl_pcie_list; -- cgit v1.3.1 From 9acc038b3990a3f74292f9c77c535e569e41dd74 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:06 +0000 Subject: dm: pcie_fsl: Add T4240 PCIe support Add compatible string for T4240 PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index d3d2c191e5d..f15deb04954 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -618,6 +618,7 @@ static struct fsl_pcie_data t2080_data = { static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, + { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data }, { } }; -- cgit v1.3.1 From a8c79f6189c608cf000218db5d08876425b5f71c Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:24 +0000 Subject: dm: pcie_fsl: Add T102x PCIe support Add compatible string for T102x PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index f15deb04954..fd7aae59f7d 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -617,6 +617,7 @@ static struct fsl_pcie_data t2080_data = { }; static const struct udevice_id fsl_pcie_ids[] = { + { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data }, { } -- cgit v1.3.1 From 4392ddbbbba50df69687a4ea0e043d25c944835f Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:44 +0000 Subject: dm: pcie_fsl: Add T104x PCIe support Add compatible string for T104x PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index fd7aae59f7d..a085c0cab92 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -618,6 +618,7 @@ static struct fsl_pcie_data t2080_data = { static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, + { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data }, { } -- cgit v1.3.1 From ba827365f7e1ad7546e6ec3098221ebd1bcfaf27 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:01 +0000 Subject: dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs Add compatible string for PCIe of P1020, P1021, P1024, P1025 and P2020 SoCs. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index a085c0cab92..31cb5d25ad8 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -610,6 +610,12 @@ static const struct dm_pci_ops fsl_pcie_ops = { .write_config = fsl_pcie_write_config, }; +static struct fsl_pcie_data p1_p2_data = { + .block_offset = 0xa000, + .block_offset_mask = 0xffff, + .stride = 0x1000, +}; + static struct fsl_pcie_data t2080_data = { .block_offset = 0x240000, .block_offset_mask = 0x3fffff, @@ -617,6 +623,7 @@ static struct fsl_pcie_data t2080_data = { }; static const struct udevice_id fsl_pcie_ids[] = { + { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, -- cgit v1.3.1 From 1a92802e3207ef362e77115654336bfbe76fd5da Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:25 +0000 Subject: dm: pcie_fsl: Add P2041 PCIe support Add compatible string for P2041 PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 31cb5d25ad8..687947ed858 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -616,6 +616,12 @@ static struct fsl_pcie_data p1_p2_data = { .stride = 0x1000, }; +static struct fsl_pcie_data p2041_data = { + .block_offset = 0x200000, + .block_offset_mask = 0x3fffff, + .stride = 0x1000, +}; + static struct fsl_pcie_data t2080_data = { .block_offset = 0x240000, .block_offset_mask = 0x3fffff, @@ -624,6 +630,7 @@ static struct fsl_pcie_data t2080_data = { static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, + { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, -- cgit v1.3.1 From 096d5f80151f2160f6defe7b1497b9590cbcecfa Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:39 +0000 Subject: dm: pcie_fsl: Add P3041 PCIe support Add compatible string for P3041 PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 687947ed858..9b60492fc55 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -631,6 +631,7 @@ static struct fsl_pcie_data t2080_data = { static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, -- cgit v1.3.1 From 7b7e4e1b7e10c1b102f12f920fec81997464e568 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:52 +0000 Subject: dm: pcie_fsl: Add P4080 PCIe support Add compatible string for P4080 PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 9b60492fc55..30fff1ede7b 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -632,6 +632,7 @@ static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, -- cgit v1.3.1 From 52744596284042f0865f70ce9d12064b6d898452 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:05:02 +0000 Subject: dm: pcie_fsl: Add P5040 PCIe support Add compatible string for P5040 PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 30fff1ede7b..199cec3e9b6 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -633,6 +633,7 @@ static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, -- cgit v1.3.1 From 92e025c6e15be4eb0f045da423eba0f58d61305f Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:05:19 +0000 Subject: dm: pcie_fsl: Add MPC8548 PCIe support Add compatible string for MPC8548 PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 199cec3e9b6..ab25aeee731 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -629,6 +629,7 @@ static struct fsl_pcie_data t2080_data = { }; static const struct udevice_id fsl_pcie_ids[] = { + { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, -- cgit v1.3.1