From 969dd4c7dbdf722bdaa323d7b9e5e6a33bcd3c80 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 21 Feb 2018 13:59:21 +0100 Subject: clk: zynqmp: Add new compatible string for clock driver New and old clk drivers are sharing IDs and descriptions. Signed-off-by: Michal Simek --- drivers/clk/clk_zynqmp.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 4ef8662af56..d0d6c898bc5 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -702,6 +702,7 @@ static struct clk_ops zynqmp_clk_ops = { }; static const struct udevice_id zynqmp_clk_ids[] = { + { .compatible = "xlnx,zynqmp-clk" }, { .compatible = "xlnx,zynqmp-clkc" }, { } }; -- cgit v1.3.1 From b32e11a7158063c6cd773087a2b3b5736da0a273 Mon Sep 17 00:00:00 2001 From: Nitin Jain Date: Fri, 16 Feb 2018 17:29:54 +0530 Subject: fpga: zynqmp: Add support to get the PCAP status for fpga info command This patch adds support for ZynqMP platform to print FPGA PCAP status for "fpga status" command. Signed-off-by: Nitin Jain Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqmppl.c | 14 ++++++++++++++ include/zynqmppl.h | 1 + 2 files changed, 15 insertions(+) (limited to 'drivers') diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 57a4e6c88e7..80388ae7f2c 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -224,6 +224,20 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, return ret; } +static int zynqmp_pcap_info(xilinx_desc *desc) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0, + 0, ret_payload); + if (!ret) + printf("PCAP status\t0x%x\n", ret_payload[1]); + + return ret; +} + struct xilinx_fpga_op zynqmp_op = { .load = zynqmp_load, + .info = zynqmp_pcap_info, }; diff --git a/include/zynqmppl.h b/include/zynqmppl.h index 4c8c2f88f04..8b3ce8ef770 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -12,6 +12,7 @@ #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018 #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016 +#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS 0xC2000017 #define ZYNQMP_FPGA_OP_INIT (1 << 0) #define ZYNQMP_FPGA_OP_LOAD (1 << 1) #define ZYNQMP_FPGA_OP_DONE (1 << 2) -- cgit v1.3.1 From 19ed4b697b9732e0a5097bd233fba7e24dfe9146 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 1 Mar 2018 17:44:47 +0530 Subject: fpga: zynqmp: Update zynqmp_load() as per latest xilfpga Latest xilfpga expects to set BIT5 of flags for nonsecure bitsream and also expects length in bytes instead of words This patch does the same. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek Reviewed-by: Joe Hershberger --- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 2 ++ drivers/fpga/zynqmppl.c | 6 +----- 2 files changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index ad3dc9aba50..3daf0e81d80 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -14,6 +14,8 @@ #define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D #define KEY_PTR_LEN 32 +#define ZYNQMP_FPGA_BIT_NS 5 + enum { IDCODE, VERSION, diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 80388ae7f2c..aae0efc7348 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -209,13 +209,9 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, debug("%s called!\n", __func__); flush_dcache_range(bin_buf, bin_buf + bsize); - if (bsize % 4) - bsize = bsize / 4 + 1; - else - bsize = bsize / 4; - buf_lo = (u32)bin_buf; buf_hi = upper_32_bits(bin_buf); + bstype |= BIT(ZYNQMP_FPGA_BIT_NS); ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize, bstype, ret_payload); if (ret) -- cgit v1.3.1 From 31bcb3444cbd5002ca9d8f6a3a2644092748cdba Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 15 Mar 2018 00:17:24 +0530 Subject: fpga: zynqmp: Fix the nonsecure bitstream loading issue Xilfpga library expects the size of bitstream in a pointer but currenly we are passing the size as a value. This patch fixes this issue. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Nava kishore Manne Signed-off-by: Michal Simek --- drivers/fpga/zynqmppl.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index aae0efc7348..43e8b2520e3 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -11,6 +11,7 @@ #include #include #include +#include #define DUMMY_WORD 0xffffffff @@ -195,6 +196,7 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype) { + ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1); u32 swap; ulong bin_buf; int ret; @@ -205,15 +207,17 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, return FPGA_FAIL; bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap); + bsizeptr = (u32 *)&bsize; debug("%s called!\n", __func__); flush_dcache_range(bin_buf, bin_buf + bsize); + flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t)); buf_lo = (u32)bin_buf; buf_hi = upper_32_bits(bin_buf); bstype |= BIT(ZYNQMP_FPGA_BIT_NS); - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize, - bstype, ret_payload); + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, + (u32)(uintptr_t)bsizeptr, bstype, ret_payload); if (ret) debug("PL FPGA LOAD fail\n"); -- cgit v1.3.1 From 71723aaec5e6dbfbc401d65461fe1cae98912e79 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 6 Mar 2018 17:37:09 +0530 Subject: fpga: zynq: Add delay after PCFG_PROG_B change There is delay needed after PCFG_PROGB change if AES key source is efuse. This fixes the issue of encrypted bitstream loading with AES efuse as key source. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers') diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 2ff716c2522..db9bd12992f 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -17,6 +17,7 @@ #include #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 +#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 @@ -205,9 +206,24 @@ static int zynq_dma_xfer_init(bitstream_type bstype) /* Setting PCFG_PROG_B signal to high */ control = readl(&devcfg_base->ctrl); writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); + + /* + * Delay is required if AES efuse is selected as + * key source. + */ + if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK) + mdelay(5); + /* Setting PCFG_PROG_B signal to low */ writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); + /* + * Delay is required if AES efuse is selected as + * key source. + */ + if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK) + mdelay(5); + /* Polling the PCAP_INIT status for Reset */ ts = get_timer(0); while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { -- cgit v1.3.1 From 6fbbe2d8f671920948a0b1882c6884cfdd0cbe67 Mon Sep 17 00:00:00 2001 From: Vipul Kumar Date: Sat, 10 Mar 2018 17:52:23 +0530 Subject: nand: arasan_nfc: Fixed NAND write issue In commit 2453c695185f ("arm64: zynqmp: nand: Fixed NAND erase issue for size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed to 0xFFFF and the same macro is used in nand write and so that getting nand write error. This patch reverted this macro to the 0xFFFF0000 and used ARASAN_NAND_MEM_ADDR1_COL_MASK in the nand erase function which is equal to 0xFFFF. Signed-off-by: Vipul Kumar Signed-off-by: Michal Simek --- drivers/mtd/nand/arasan_nfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c index 9c82c7db33f..3be66efb73f 100644 --- a/drivers/mtd/nand/arasan_nfc.c +++ b/drivers/mtd/nand/arasan_nfc.c @@ -86,7 +86,7 @@ struct arasan_nand_command_format { #define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28 -#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF +#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000 #define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF @@ -796,7 +796,7 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd, writel(reg_val, &arasan_nand_base->cmd_reg); page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & - ARASAN_NAND_MEM_ADDR1_PAGE_MASK; + ARASAN_NAND_MEM_ADDR1_COL_MASK; column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK; writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT), &arasan_nand_base->memadr_reg1); -- cgit v1.3.1 From 047f3bf8282f87a8cad2fc5b1fef569895cbd2dd Mon Sep 17 00:00:00 2001 From: Vipul Kumar Date: Tue, 23 Jan 2018 14:52:35 +0530 Subject: axi: ethernet: Added support for 64 bit addressing for axi-ethernet This patch uses writeq() function to enable greater than 32 bit addressing of axi-ethernet for the ZynqMP devices. Signed-off-by: Vipul Kumar Signed-off-by: Michal Simek Acked-by: Joe Hershberger --- drivers/net/xilinx_axi_emac.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 70a2e95a8ec..80ed06ac66c 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -78,9 +78,10 @@ static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); struct axidma_reg { u32 control; /* DMACR */ u32 status; /* DMASR */ - u32 current; /* CURDESC */ - u32 reserved; - u32 tail; /* TAILDESC */ + u32 current; /* CURDESC low 32 bit */ + u32 current_hi; /* CURDESC high 32 bit */ + u32 tail; /* TAILDESC low 32 bit */ + u32 tail_hi; /* TAILDESC high 32 bit */ }; /* Private driver structures */ @@ -168,6 +169,22 @@ static inline int mdio_wait(struct axi_regs *regs) return 0; } +/** + * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write. + * @bd: pointer to BD descriptor structure + * @desc: Address offset of DMA descriptors + * + * This function writes the value into the corresponding Axi DMA register. + */ +static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc) +{ +#if defined(CONFIG_PHYS_64BIT) + writeq(bd, desc); +#else + writel((u32)bd, desc); +#endif +} + static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum, u16 *val) { @@ -465,7 +482,7 @@ static int axiemac_start(struct udevice *dev) writel(temp, &priv->dmarx->control); /* Start DMA RX channel. Now it's ready to receive data.*/ - writel((u32)&rx_bd, &priv->dmarx->current); + axienet_dma_write(&rx_bd, &priv->dmarx->current); /* Setup the BD. */ memset(&rx_bd, 0, sizeof(rx_bd)); @@ -485,7 +502,7 @@ static int axiemac_start(struct udevice *dev) writel(temp, &priv->dmarx->control); /* Rx BD is ready - start */ - writel((u32)&rx_bd, &priv->dmarx->tail); + axienet_dma_write(&rx_bd, &priv->dmarx->tail); /* Enable TX */ writel(XAE_TC_TX_MASK, ®s->tc); @@ -527,7 +544,7 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len) if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) { u32 temp; - writel((u32)&tx_bd, &priv->dmatx->current); + axienet_dma_write(&tx_bd, &priv->dmatx->current); /* Start the hardware */ temp = readl(&priv->dmatx->control); temp |= XAXIDMA_CR_RUNSTOP_MASK; @@ -535,7 +552,7 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len) } /* Start transfer */ - writel((u32)&tx_bd, &priv->dmatx->tail); + axienet_dma_write(&tx_bd, &priv->dmatx->tail); /* Wait for transmission to complete */ debug("axiemac: Waiting for tx to be done\n"); @@ -626,7 +643,7 @@ static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length) flush_cache((u32)&rxframe, sizeof(rxframe)); /* Rx BD is ready - start again */ - writel((u32)&rx_bd, &priv->dmarx->tail); + axienet_dma_write(&rx_bd, &priv->dmarx->tail); debug("axiemac: RX completed, framelength = %d\n", length); -- cgit v1.3.1 From c643c491b952d40d46224e788847b9f59ddcec04 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 12 Jan 2018 12:44:54 +0530 Subject: net: phy: xilinx_phy: Read phytype using property xlnx,phy-type This patch reads phytype from property "xlnx,phy-type" instead od simply looking for "phy-type". This is to be inline with Linux and also fixes the issue of detecting it wrongly in u-boot. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek Acked-by: Joe Hershberger --- drivers/net/phy/xilinx_phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c index 3f80f0495e8..7142a99ce58 100644 --- a/drivers/net/phy/xilinx_phy.c +++ b/drivers/net/phy/xilinx_phy.c @@ -105,7 +105,7 @@ static int xilinxphy_of_init(struct phy_device *phydev) debug("%s\n", __func__); phytype = fdtdec_get_int(gd->fdt_blob, dev_of_offset(phydev->dev), - "phy-type", -1); + "xlnx,phy-type", -1); if (phytype == XAE_PHY_TYPE_1000BASE_X) phydev->flags |= XAE_PHY_TYPE_1000BASE_X; -- cgit v1.3.1