From 98fbd71d7a4492e23377b8753cfd77add26c63ec Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Sat, 17 Oct 2015 08:31:55 -0500 Subject: spi: cadence_qspi: Ensure spi_calibration is run when sclk change Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Marek Vasut Cc: Stefan Roese Cc: Vikas Manocha Cc: Jagannadh Teki Cc: Pavel Machek Acked-by: Marek Vasut Reviewed-by: Jagan Teki --- drivers/spi/cadence_qspi.c | 22 +++++++++++++--------- drivers/spi/cadence_qspi.h | 1 + 2 files changed, 14 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46a1ae..c5a427698e6 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -37,9 +37,8 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) } /* Calibration sequence to determine the read data capture delay register */ -static int spi_calibration(struct udevice *bus) +static int spi_calibration(struct udevice *bus, uint hz) { - struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); void *base = priv->regbase; u8 opcode_rdid = 0x9F; @@ -64,7 +63,7 @@ static int spi_calibration(struct udevice *bus) } /* use back the intended clock and find low range */ - cadence_spi_write_speed(bus, plat->max_hz); + cadence_spi_write_speed(bus, hz); for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { /* Disable QSPI */ cadence_qspi_apb_controller_disable(base); @@ -111,7 +110,7 @@ static int spi_calibration(struct udevice *bus) (range_hi + range_lo) / 2, range_lo, range_hi); /* just to ensure we do once only when speed or chip select change */ - priv->qspi_calibrated_hz = plat->max_hz; + priv->qspi_calibrated_hz = hz; priv->qspi_calibrated_cs = spi_chip_select(bus); return 0; @@ -126,14 +125,19 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) /* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase); - cadence_spi_write_speed(bus, hz); - - /* Calibration required for different SCLK speed or chip select */ - if (priv->qspi_calibrated_hz != plat->max_hz || + /* + * Calibration required for different current SCLK speed, requested + * SCLK speed or chip select + */ + if (priv->previous_hz != hz || + priv->qspi_calibrated_hz != hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) { - err = spi_calibration(bus); + err = spi_calibration(bus, hz); if (err) return err; + + /* prevent calibration run when same as previous request */ + priv->previous_hz = hz; } /* Enable QSPI */ diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 98e57aa5bcc..2912e36a53f 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -38,6 +38,7 @@ struct cadence_spi_priv { int qspi_is_init; unsigned int qspi_calibrated_hz; unsigned int qspi_calibrated_cs; + unsigned int previous_hz; }; /* Functions call declaration */ -- cgit v1.2.3 From 040f4ba742700529d950a92da5ddbe99d9ae335e Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Sat, 17 Oct 2015 08:32:14 -0500 Subject: spi: cadence_qspi: Fix fdt read of spi-max-frequency Fix the fdt read for spi-max-frequency as it's contained in the child node. Current state of code is always returning default value. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Marek Vasut Cc: Stefan Roese Cc: Vikas Manocha Cc: Jagannadh Teki Cc: Pavel Machek Acked-by: Marek Vasut Acked-by: Pavel Machek --- drivers/spi/cadence_qspi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index c5a427698e6..57561787610 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -295,10 +295,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->regbase = (void *)data[0]; plat->ahbbase = (void *)data[2]; - /* Use 500KHz as a suitable default */ - plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", - 500000); - /* All other paramters are embedded in the child node */ subnode = fdt_first_subnode(blob, node); if (subnode < 0) { @@ -306,6 +302,10 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) return -ENODEV; } + /* Use 500 KHz as a suitable default */ + plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency", + 500000); + /* Read other parameters from DT */ plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256); plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16); -- cgit v1.2.3 From 4e609b6cb1e6e8cb14c55fd50c73c5affcba26b5 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Sat, 17 Oct 2015 08:32:38 -0500 Subject: spi: cadence_qspi: Ensure check for max frequency in place Ensure the intended SCLK frequency not exceeding the maximum frequency. If that happen, SCLK will set to maximum frequency. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Marek Vasut Cc: Stefan Roese Cc: Vikas Manocha Cc: Jagannadh Teki Cc: Pavel Machek Acked-by: Pavel Machek --- drivers/spi/cadence_qspi.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 57561787610..4f7fd525322 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -122,6 +122,9 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) struct cadence_spi_priv *priv = dev_get_priv(bus); int err; + if (hz > plat->max_hz) + hz = plat->max_hz; + /* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase); -- cgit v1.2.3