From 5c7ea64bb74a850a2b2303f853a8270695ad8602 Mon Sep 17 00:00:00 2001 From: Dan Wilson Date: Fri, 19 Oct 2007 11:33:48 -0500 Subject: tsec driver should clear RHALT on startup This was causing problems for some people. Signed-off-by: Alain Gravel Signed-off-by: Dan Wilson Signed-off-by: Andy Fleming --- drivers/tsec.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index 4ff3339c7de..7ba8f0cace9 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -803,6 +803,7 @@ static void startup_tsec(struct eth_device *dev) /* Tell the DMA it is clear to go */ regs->dmactrl |= DMACTRL_INIT_SETTINGS; regs->tstat = TSTAT_CLEAR_THALT; + regs->rstat = RSTAT_CLEAR_RHALT; regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); } -- cgit v1.3.1 From ff285ca07eda1ea4a8909848cc1cc604ec8fec9c Mon Sep 17 00:00:00 2001 From: Vlad Lungu Date: Thu, 4 Oct 2007 20:47:10 +0300 Subject: Fix NE2000 driver: Fixed typo in ne2000.h, thinko re n2k_inb() usage, don't try to do anything in eth_stop() if eth_init() was not called. Simplified RX path in order to avoid timeouts on really really fast NE2000 cards (read: qemu with internal tftp), NetLoop() is clever enough to cope with 1 packet per eth_rx(). Signed-off-by: Vlad Lungu --- drivers/ne2000.c | 36 +++++++++++++----------------------- drivers/ne2000.h | 2 +- 2 files changed, 14 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/ne2000.c b/drivers/ne2000.c index b7ed8761659..0bfe74e5472 100644 --- a/drivers/ne2000.c +++ b/drivers/ne2000.c @@ -755,7 +755,7 @@ static void pcnet_reset_8390(void) #endif n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); - n2k_outb(n2k_inb(nic_base + PCNET_RESET), PCNET_RESET); + n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET); for (i = 0; i < 100; i++) { if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0) @@ -833,6 +833,7 @@ static int plen[NB]; static int nrx = 0; static int pkey = -1; +static int initialized=0; void uboot_push_packet_len(int len) { PRINTK("pushed len = %d, nrx = %d\n", len, nrx); @@ -846,7 +847,12 @@ void uboot_push_packet_len(int len) { } plen[nrx] = len; dp83902a_recv(&pbuf[nrx*2000], len); +/*Just pass it to the upper layer*/ + NetReceive(&pbuf[nrx*2000], plen[nrx]); +/*eth_rx() was gutted, so this is not needed anymore*/ +#if 0 nrx++; +#endif } void uboot_push_tx_done(int key, int val) { @@ -903,37 +909,21 @@ int eth_init(bd_t *bd) { if (dp83902a_init() == false) return -1; dp83902a_start(dev_addr); + initialized=1; return 0; } void eth_halt() { PRINTK("### eth_halt\n"); - - dp83902a_stop(); + if(initialized) + dp83902a_stop(); + initialized=0; } int eth_rx() { - int j, tmo; - - PRINTK("### eth_rx\n"); - - tmo = get_timer (0) + TOUT * CFG_HZ; - while(1) { - dp83902a_poll(); - if (nrx > 0) { - for(j=0; j= tmo) { - printf("timeout during rx\n"); - return 0; - } - } - return 0; +dp83902a_poll(); +return 1; } int eth_send(volatile void *packet, int length) { diff --git a/drivers/ne2000.h b/drivers/ne2000.h index 2955533d7a7..c13d9f0bbb7 100644 --- a/drivers/ne2000.h +++ b/drivers/ne2000.h @@ -42,7 +42,7 @@ are GPL, so this is, of course, GPL. this file might be covered by the GNU General Public License. Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. - at http://sources.redhat.com/ecos/ecos-license/ */ + at http://sources.redhat.com/ecos/ecos-license/ ------------------------------------------- ####ECOSGPLCOPYRIGHTEND#### ####BSDCOPYRIGHTBEGIN#### -- cgit v1.3.1 From 05bf4919c1ce49cdedadacd564d0786a8ed796a1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 21 Oct 2007 01:01:17 +0200 Subject: Minor coding style cleanup; update CHANGELOG Signed-off-by: Wolfgang Denk --- CHANGELOG | 248 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ Makefile | 18 ++-- drivers/ne2000.c | 10 +-- 3 files changed, 259 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/CHANGELOG b/CHANGELOG index b038749c9b3..05400013897 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,206 @@ +commit ff285ca07eda1ea4a8909848cc1cc604ec8fec9c +Author: Vlad Lungu +Date: Thu Oct 4 20:47:10 2007 +0300 + + Fix NE2000 driver: + + Fixed typo in ne2000.h, thinko re n2k_inb() usage, don't try + to do anything in eth_stop() if eth_init() was not called. + Simplified RX path in order to avoid timeouts on really really + fast NE2000 cards (read: qemu with internal tftp), NetLoop() is + clever enough to cope with 1 packet per eth_rx(). + + Signed-off-by: Vlad Lungu + +commit 5441f61a3d8b7034f19fc1361183e936198e6dbb +Author: Detlev Zundel +Date: Fri Oct 19 16:47:26 2007 +0200 + + Fix two typos. + + Signed-off-by: Detlev Zundel + +commit 281df457c1aa50d2752165d0c5c3282d4027b974 +Author: Tony Li +Date: Thu Oct 18 17:47:19 2007 +0800 + + mpc83xx: Add configure entry for MPC83xx ATM support + + Add MPC8360EMDS_ATM_config and MPC832XEMDS_ATM_config into + Makfile and MAKEALL + + Signed-off-by: Tony Li + Signed-off-by: Kim Phillips + +commit d2646554f529a9577515eceb0ec5eceee18244ba +Author: Tony Li +Date: Thu Oct 18 17:44:38 2007 +0800 + + mpc83xx: pq-mds-pib.c typo error + + Correct to val8 from val. + + Signed-off-by: Tony Li + Signed-off-by: Kim Phillips + +commit 3e11ae80fec1ee12194940955431186abf6009c2 +Author: Stefan Roese +Date: Wed Oct 17 15:40:19 2007 +0200 + + ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap command + + Signed-off-by: Stefan Roese + +commit 7ee6ba1a056e4061ab4cfde30127e332e7957afd +Author: runet@innovsys.com +Date: Tue Oct 16 14:50:40 2007 -0500 + + Make MPC8266ADS board compile again. + + Signed-off-by: Runet Torgersen + +commit 2491167c245d8ebe6f2dbd8c4287aaa0d14fe93a +Author: Jon Loeliger +Date: Mon Aug 27 12:41:03 2007 -0500 + + 86xx: Allow for fewer DDR slots per memory controller. + + As a direct correlation exists between DDR DIMM slots + and SPD EEPROM addresses used to configure them, use + the individually defined SPD_EEPROM_ADDRESS* values to + determine if a DDR DIMM slot should have its SPD + configuration read or not. + + Effectively, this now allows for 1 or 2 DIMM slots + per memory controller. + + Signed-off-by: Jon Loeliger + +commit 4d4a945e189a2f384c66432316da2788a0ac1607 +Author: Rodolfo Giometti +Date: Mon Oct 15 11:59:17 2007 +0200 + + PXA USB OHCI: "usb stop" implementation. + + Some USB keys need to be switched off before loading the kernel + otherwise they can remain in an undefined status which prevents them + to be correctly recognized by the kernel. + + Signed-off-by: Rodolfo Giometti + +commit e2e93442e558cf1500e92861f99713b2f045ea22 +Author: Stefan Roese +Date: Mon Oct 15 11:39:00 2007 +0200 + + ppc4xx: Fix bug in I2C bootstrap values for Sequoia/Rainier + + The I2C bootstrap values that can be setup via the "bootstrap" command, + were setup incorrect regarding the generation of the internal sync PCI + clock. The values for PLB clock == 133MHz were slighly incorrect and the + values for PLB clock == 166MHz were totally incorrect. This could + lead to a hangup upon booting while PCI configuration scan. + + This patch fixes this issue and configures valid PCI divisor values + for the sync PCI clock, with respect to the provided external async + PCI frequency. + + Here the values of the formula in the chapter 14.2 "PCI clocking" + from the 440EPx users manual: + + AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz + + 33MHz async PCI frequency: + PLB = 133: + => 32 <= 44.3 <= 65 (div = 3) + + PLB = 166: + => 32 <= 55.3 <= 65 (div = 3) + + 66MHz async PCI frequency: + PLB = 133: + => 65 <= 66.5 <= 132 (div = 2) + + PLB = 166: + => 65 <= 83 <= 132 (div = 2) + + Signed-off-by: Stefan Roese + +commit 5a5958b7de70ae99f0e7cbd5c97ec1346e051587 +Author: Stefan Roese +Date: Mon Oct 15 11:29:33 2007 +0200 + + ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite + + The BCSR status bit for the 66MHz PCI operation was correctly + addressed (MSB/LSB problem). Now the correct currently setup + PCI frequency is displayed upon bootup. + + This patch also fixes this problem on Rainier & Yellowstone, since these + boards use the same souce code as Sequoia & Yosemite do. + + Signed-off-by: Stefan Roese + +commit da3aad55cbde80ab6e301aafa82a2c411aa53eff +Author: Martin Krause +Date: Wed Sep 26 17:55:56 2007 +0200 + + TQM860M: adjust for doubled flash sector size. + + Adjust flash map to support the new S29GLxxN (N-Type) Flashes with + doubled sector size. + + Signed-off-by: Martin Krause + +commit 9d29250e2e62f4bf20c7a20b4173d84c48f11f5d +Author: Jens Gehrlein +Date: Wed Sep 26 17:55:54 2007 +0200 + + TQM8xx: Fix CAN timing. + + Signed-off-by: Martin Krause + +commit d43e489baf02afae49077791fb22332d240d8656 +Author: Martin Krause +Date: Thu Sep 27 14:54:36 2007 +0200 + + TQM866M: fix SDRAM refresh + + At 133 MHz the current SDRAM refresh rate is too fast + (measured 4 * 1.17 us). + CFG_MAMR_PTA changes from 39 to 97. This result + in a refresh rate of 4 * 7.8 us at the default clock + 50 MHz. At 133 MHz the value will be then 4 * 2.9 us. + This is a compromise until a new method is found to + adjust the refresh rate. + + Signed-off-by: Martin Krause + +commit 9ef57bbee1c67cc01da2026c242c4692db32be36 +Author: Martin Krause +Date: Wed Sep 26 17:55:55 2007 +0200 + + TQM866M: adjust for doubled flash sector size. + + Adjust flash map to support the new S29GLxxN (N-Type) Flashes with + doubled sector size. + + Signed-off-by: Martin Krause + +commit f8bf90461d9bad2e6fed31fcebaf235f60dd6763 +Author: Michal Simek +Date: Sun Oct 14 16:12:29 2007 +0200 + + [FIX] XUPV2P change command handling + and remove code violation + +commit 636400198228d96983c06657b17f760f5989958e +Author: Wolfgang Denk +Date: Sun Oct 14 00:13:19 2007 +0200 + + Prepare for 1.3.0-rc3 release + + Signed-off-by: Wolfgang Denk + commit 68f14f77ca5fe5f9cc025c8cae101671f628309f Author: Jean-Christophe PLAGNIOL-VILLARD Date: Sat Sep 29 13:41:37 2007 +0200 @@ -109,6 +312,26 @@ Date: Mon Oct 1 09:51:50 2007 +0200 Signed-off-by: Grzegorz Bernacki +commit 785c13477b77dcd2e6c5128fffcdb4e1943f4818 +Author: Timo Ketola +Date: Mon Sep 24 14:50:32 2007 +0300 + + Bugfix: Use only one PTD for one endpoint + + Original isp116x-hcd code prepared multiple PTDs for longer than 16 + byte transfers for one endpoint. That is unnecessary because the + ISP116x is able to split long data from one PTD into multiple + transactions based on the buffer size of the endpoint. It also caused + serious problems if the endpoint NAKed some of the transactions. In + that case ISP116x wouldn't notice that the other PTDs were for the same + endpoint and would try the other PTDs possibly out of order. That would + break the whole transfer. + + This patch makes isp116x_submit_job to use one PTD for one transfer. + + Signed-off-by: Timo Ketola + Signed-off-by: Markus Klotzbuecher + commit 86ec86c04326c3913178a7679aa910de071da75d Author: Jean-Christophe PLAGNIOL-VILLARD Date: Thu Sep 27 23:27:47 2007 +0200 @@ -331,6 +554,12 @@ Date: Mon Sep 10 17:13:49 2007 +0900 Signed-off-by: Kyungmin Park +commit b49c90df6e7cfcfb8b862b8bbf8448dff5eed9a5 +Author: Michal Simek +Date: Sun Sep 16 20:51:57 2007 +0200 + + [FIX] remove files form repository + commit 67c31036acaaaa992fc346cc89db0909a7e733c4 Author: Wolfgang Denk Date: Sun Sep 16 17:10:04 2007 +0200 @@ -478,6 +707,25 @@ Date: Sat Sep 15 11:55:42 2007 +0200 [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/31805 +commit 991b089d1ce5ad945725e3657a8f106dfa02a38e +Author: Michal Simek +Date: Sat Sep 15 00:03:35 2007 +0200 + + Synchronize with U-BOOT mainline + +commit d7fee32b7e61fe11c64e371cde79faa4768e8350 +Author: Sam Sparks +Date: Fri Sep 14 11:14:42 2007 -0600 + + Update MPC8349ITX*_config to place config.tmp in right place. + + MPC834ITX*_config does not store config.tmp at the correct locatation, + causing MPC8349ITXGP to have the wrong TEXT_BASE. + + Signed-off-by: Sam Sparks + Signed-off-by: Grant Likely + Signed-off-by: Kim Phillips + commit 6e7b7b6ea1b6d04dbe96242eb6a0c1c664c98e8c Author: Bartlomiej Sieka Date: Thu Sep 13 18:21:48 2007 +0200 diff --git a/Makefile b/Makefile index ce7b07f9d18..5643aa91213 100644 --- a/Makefile +++ b/Makefile @@ -393,7 +393,7 @@ BC3450_config: unconfig cpci5200_config: unconfig @$(MKCONFIG) -a cpci5200 ppc mpc5xxx cpci5200 esd -hmi1001_config: unconfig +hmi1001_config: unconfig @$(MKCONFIG) hmi1001 ppc mpc5xxx hmi1001 Lite5200_config \ @@ -435,7 +435,7 @@ icecube_5100_config: unconfig } @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube -jupiter_config: unconfig +jupiter_config: unconfig @$(MKCONFIG) jupiter ppc mpc5xxx jupiter v38b_config: unconfig @@ -640,9 +640,9 @@ TQM5200_STK100_config: unconfig { echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \ } @$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200 -uc101_config: unconfig +uc101_config: unconfig @$(MKCONFIG) uc101 ppc mpc5xxx uc101 -motionpro_config: unconfig +motionpro_config: unconfig @$(MKCONFIG) motionpro ppc mpc5xxx motionpro @@ -930,7 +930,7 @@ RPXlite_DW_NVRAM_config \ RPXlite_DW_NVRAM_64_config \ RPXlite_DW_NVRAM_LCD_config \ RPXlite_DW_NVRAM_64_LCD_config \ -RPXlite_DW_config: unconfig +RPXlite_DW_config: unconfig @mkdir -p $(obj)include @ >$(obj)include/config.h @[ -z "$(findstring _64,$@)" ] || \ @@ -1793,7 +1793,7 @@ MPC832XEMDS_ATM_config: unconfig echo -n "...ATM..." ; \ echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \ - fi ; + fi ; @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale MPC8349EMDS_config: unconfig @@ -2001,13 +2001,13 @@ AmigaOneG3SE_config: unconfig BAB7xx_config: unconfig @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx bab7xx eltec -CPCI750_config: unconfig +CPCI750_config: unconfig @$(MKCONFIG) CPCI750 ppc 74xx_7xx cpci750 esd -DB64360_config: unconfig +DB64360_config: unconfig @$(MKCONFIG) DB64360 ppc 74xx_7xx db64360 Marvell -DB64460_config: unconfig +DB64460_config: unconfig @$(MKCONFIG) DB64460 ppc 74xx_7xx db64460 Marvell ELPPC_config: unconfig diff --git a/drivers/ne2000.c b/drivers/ne2000.c index 0bfe74e5472..695a1dc6c90 100644 --- a/drivers/ne2000.c +++ b/drivers/ne2000.c @@ -745,14 +745,12 @@ static void pcnet_reset_8390(void) PRINTK("nic base is %lx\n", nic_base); -#if 1 n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD); PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); -#endif n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET); @@ -847,12 +845,9 @@ void uboot_push_packet_len(int len) { } plen[nrx] = len; dp83902a_recv(&pbuf[nrx*2000], len); -/*Just pass it to the upper layer*/ + + /*Just pass it to the upper layer*/ NetReceive(&pbuf[nrx*2000], plen[nrx]); -/*eth_rx() was gutted, so this is not needed anymore*/ -#if 0 - nrx++; -#endif } void uboot_push_tx_done(int key, int val) { @@ -949,5 +944,4 @@ int eth_send(volatile void *packet, int length) { } return 0; } - #endif -- cgit v1.3.1 From 7a9348728ebda63cdbaacffd83099aa71d9d4c54 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 23 Oct 2007 10:22:16 +0100 Subject: Move PL01* serial drivers to drivers/serial and adjust Makefiles. --- drivers/Makefile | 2 +- drivers/serial/Makefile | 2 +- drivers/serial/serial_pl010.c | 171 ++++++++++++++++++++++++++++++++++++++++++ drivers/serial/serial_pl011.c | 161 +++++++++++++++++++++++++++++++++++++++ drivers/serial/serial_pl011.h | 137 +++++++++++++++++++++++++++++++++ drivers/serial_pl010.c | 171 ------------------------------------------ drivers/serial_pl011.c | 161 --------------------------------------- drivers/serial_pl011.h | 137 --------------------------------- 8 files changed, 471 insertions(+), 471 deletions(-) create mode 100644 drivers/serial/serial_pl010.c create mode 100644 drivers/serial/serial_pl011.c create mode 100644 drivers/serial/serial_pl011.h delete mode 100644 drivers/serial_pl010.c delete mode 100644 drivers/serial_pl011.c delete mode 100644 drivers/serial_pl011.h (limited to 'drivers') diff --git a/drivers/Makefile b/drivers/Makefile index 6bf05ccad19..1889698bca8 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -42,7 +42,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \ s3c4510b_eth.o s3c4510b_uart.o \ sed13806.o sed156x.o \ serial.o serial_max3100.o \ - serial_pl010.o serial_pl011.o serial_xuartlite.o \ + serial_xuartlite.o \ sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ status_led.o sym53c8xx.o systemace.o ahci.o \ ti_pci1410a.o tigon3.o tsec.o \ diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 93c68dd2e08..40f3d672ec9 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libserial.a -COBJS := mcfuart.o +COBJS := mcfuart.o serial_pl010.o serial_pl011.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/serial/serial_pl010.c b/drivers/serial/serial_pl010.c new file mode 100644 index 00000000000..417b6aeda64 --- /dev/null +++ b/drivers/serial/serial_pl010.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ +/* Should be fairly simple to make it work with the PL010 as well */ + +#include + +#ifdef CFG_PL010_SERIAL + +#include "serial_pl011.h" + +#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) +#define IO_READ(addr) (*(volatile unsigned int *)(addr)) + +/* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */ +#define CONSOLE_PORT CONFIG_CONS_INDEX +#define baudRate CONFIG_BAUDRATE +static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; +#define NUM_PORTS (sizeof(port)/sizeof(port[0])) + + +static void pl010_putc (int portnum, char c); +static int pl010_getc (int portnum); +static int pl010_tstc (int portnum); + + +int serial_init (void) +{ + unsigned int divisor; + + /* + ** First, disable everything. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0); + + /* + ** Set baud rate + ** + */ + switch (baudRate) { + case 9600: + divisor = UART_PL010_BAUD_9600; + break; + + case 19200: + divisor = UART_PL010_BAUD_9600; + break; + + case 38400: + divisor = UART_PL010_BAUD_38400; + break; + + case 57600: + divisor = UART_PL010_BAUD_57600; + break; + + case 115200: + divisor = UART_PL010_BAUD_115200; + break; + + default: + divisor = UART_PL010_BAUD_38400; + } + + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM, + ((divisor & 0xf00) >> 8)); + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff)); + + /* + ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH, + (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN)); + + /* + ** Finally, enable the UART + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN)); + + return (0); +} + +void serial_putc (const char c) +{ + if (c == '\n') + pl010_putc (CONSOLE_PORT, '\r'); + + pl010_putc (CONSOLE_PORT, c); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + return pl010_getc (CONSOLE_PORT); +} + +int serial_tstc (void) +{ + return pl010_tstc (CONSOLE_PORT); +} + +void serial_setbrg (void) +{ +} + +static void pl010_putc (int portnum, char c) +{ + /* Wait until there is space in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); + + /* Send the character */ + IO_WRITE (port[portnum] + UART_PL01x_DR, c); +} + +static int pl010_getc (int portnum) +{ + unsigned int data; + + /* Wait until there is data in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); + + data = IO_READ (port[portnum] + UART_PL01x_DR); + + /* Check for an error flag */ + if (data & 0xFFFFFF00) { + /* Clear the error */ + IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); + return -1; + } + + return (int) data; +} + +static int pl010_tstc (int portnum) +{ + return !(IO_READ (port[portnum] + UART_PL01x_FR) & + UART_PL01x_FR_RXFE); +} + +#endif diff --git a/drivers/serial/serial_pl011.c b/drivers/serial/serial_pl011.c new file mode 100644 index 00000000000..4d35fe5e9ed --- /dev/null +++ b/drivers/serial/serial_pl011.c @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ +/* Should be fairly simple to make it work with the PL010 as well */ + +#include + +#ifdef CFG_PL011_SERIAL + +#include "serial_pl011.h" + +#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) +#define IO_READ(addr) (*(volatile unsigned int *)(addr)) + +/* + * IntegratorCP has two UARTs, use the first one, at 38400-8-N-1 + * Versatile PB has four UARTs. + */ + +#define CONSOLE_PORT CONFIG_CONS_INDEX +#define baudRate CONFIG_BAUDRATE +static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; +#define NUM_PORTS (sizeof(port)/sizeof(port[0])) + +static void pl011_putc (int portnum, char c); +static int pl011_getc (int portnum); +static int pl011_tstc (int portnum); + + +int serial_init (void) +{ + unsigned int temp; + unsigned int divider; + unsigned int remainder; + unsigned int fraction; + + /* + ** First, disable everything. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0); + + /* + ** Set baud rate + ** + ** IBRD = UART_CLK / (16 * BAUD_RATE) + ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) + */ + temp = 16 * baudRate; + divider = CONFIG_PL011_CLOCK / temp; + remainder = CONFIG_PL011_CLOCK % temp; + temp = (8 * remainder) / baudRate; + fraction = (temp >> 1) + (temp & 1); + + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider); + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); + + /* + ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, + (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); + + /* + ** Finally, enable the UART + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, + (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | + UART_PL011_CR_RXE)); + + return 0; +} + +void serial_putc (const char c) +{ + if (c == '\n') + pl011_putc (CONSOLE_PORT, '\r'); + + pl011_putc (CONSOLE_PORT, c); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + return pl011_getc (CONSOLE_PORT); +} + +int serial_tstc (void) +{ + return pl011_tstc (CONSOLE_PORT); +} + +void serial_setbrg (void) +{ +} + +static void pl011_putc (int portnum, char c) +{ + /* Wait until there is space in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); + + /* Send the character */ + IO_WRITE (port[portnum] + UART_PL01x_DR, c); +} + +static int pl011_getc (int portnum) +{ + unsigned int data; + + /* Wait until there is data in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); + + data = IO_READ (port[portnum] + UART_PL01x_DR); + + /* Check for an error flag */ + if (data & 0xFFFFFF00) { + /* Clear the error */ + IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); + return -1; + } + + return (int) data; +} + +static int pl011_tstc (int portnum) +{ + return !(IO_READ (port[portnum] + UART_PL01x_FR) & + UART_PL01x_FR_RXFE); +} + +#endif diff --git a/drivers/serial/serial_pl011.h b/drivers/serial/serial_pl011.h new file mode 100644 index 00000000000..5f20fdd108a --- /dev/null +++ b/drivers/serial/serial_pl011.h @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2003, 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * ARM PrimeCell UART's (PL010 & PL011) + * ------------------------------------ + * + * Definitions common to both PL010 & PL011 + * + */ +#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */ +#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */ +#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */ +#define UART_PL01x_FR 0x18 /* Flag register (Read only). */ + +#define UART_PL01x_RSR_OE 0x08 +#define UART_PL01x_RSR_BE 0x04 +#define UART_PL01x_RSR_PE 0x02 +#define UART_PL01x_RSR_FE 0x01 + +#define UART_PL01x_FR_TXFE 0x80 +#define UART_PL01x_FR_RXFF 0x40 +#define UART_PL01x_FR_TXFF 0x20 +#define UART_PL01x_FR_RXFE 0x10 +#define UART_PL01x_FR_BUSY 0x08 +#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) + +/* + * PL010 definitions + * + */ +#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */ +#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */ +#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */ +#define UART_PL010_CR 0x14 /* Control register. */ +#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */ +#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */ +#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */ + +#define UART_PL010_CR_LPE (1 << 7) +#define UART_PL010_CR_RTIE (1 << 6) +#define UART_PL010_CR_TIE (1 << 5) +#define UART_PL010_CR_RIE (1 << 4) +#define UART_PL010_CR_MSIE (1 << 3) +#define UART_PL010_CR_IIRLP (1 << 2) +#define UART_PL010_CR_SIREN (1 << 1) +#define UART_PL010_CR_UARTEN (1 << 0) + +#define UART_PL010_LCRH_WLEN_8 (3 << 5) +#define UART_PL010_LCRH_WLEN_7 (2 << 5) +#define UART_PL010_LCRH_WLEN_6 (1 << 5) +#define UART_PL010_LCRH_WLEN_5 (0 << 5) +#define UART_PL010_LCRH_FEN (1 << 4) +#define UART_PL010_LCRH_STP2 (1 << 3) +#define UART_PL010_LCRH_EPS (1 << 2) +#define UART_PL010_LCRH_PEN (1 << 1) +#define UART_PL010_LCRH_BRK (1 << 0) + + +#define UART_PL010_BAUD_460800 1 +#define UART_PL010_BAUD_230400 3 +#define UART_PL010_BAUD_115200 7 +#define UART_PL010_BAUD_57600 15 +#define UART_PL010_BAUD_38400 23 +#define UART_PL010_BAUD_19200 47 +#define UART_PL010_BAUD_14400 63 +#define UART_PL010_BAUD_9600 95 +#define UART_PL010_BAUD_4800 191 +#define UART_PL010_BAUD_2400 383 +#define UART_PL010_BAUD_1200 767 +/* + * PL011 definitions + * + */ +#define UART_PL011_IBRD 0x24 +#define UART_PL011_FBRD 0x28 +#define UART_PL011_LCRH 0x2C +#define UART_PL011_CR 0x30 +#define UART_PL011_IMSC 0x38 +#define UART_PL011_PERIPH_ID0 0xFE0 + +#define UART_PL011_LCRH_SPS (1 << 7) +#define UART_PL011_LCRH_WLEN_8 (3 << 5) +#define UART_PL011_LCRH_WLEN_7 (2 << 5) +#define UART_PL011_LCRH_WLEN_6 (1 << 5) +#define UART_PL011_LCRH_WLEN_5 (0 << 5) +#define UART_PL011_LCRH_FEN (1 << 4) +#define UART_PL011_LCRH_STP2 (1 << 3) +#define UART_PL011_LCRH_EPS (1 << 2) +#define UART_PL011_LCRH_PEN (1 << 1) +#define UART_PL011_LCRH_BRK (1 << 0) + +#define UART_PL011_CR_CTSEN (1 << 15) +#define UART_PL011_CR_RTSEN (1 << 14) +#define UART_PL011_CR_OUT2 (1 << 13) +#define UART_PL011_CR_OUT1 (1 << 12) +#define UART_PL011_CR_RTS (1 << 11) +#define UART_PL011_CR_DTR (1 << 10) +#define UART_PL011_CR_RXE (1 << 9) +#define UART_PL011_CR_TXE (1 << 8) +#define UART_PL011_CR_LPE (1 << 7) +#define UART_PL011_CR_IIRLP (1 << 2) +#define UART_PL011_CR_SIREN (1 << 1) +#define UART_PL011_CR_UARTEN (1 << 0) + +#define UART_PL011_IMSC_OEIM (1 << 10) +#define UART_PL011_IMSC_BEIM (1 << 9) +#define UART_PL011_IMSC_PEIM (1 << 8) +#define UART_PL011_IMSC_FEIM (1 << 7) +#define UART_PL011_IMSC_RTIM (1 << 6) +#define UART_PL011_IMSC_TXIM (1 << 5) +#define UART_PL011_IMSC_RXIM (1 << 4) +#define UART_PL011_IMSC_DSRMIM (1 << 3) +#define UART_PL011_IMSC_DCDMIM (1 << 2) +#define UART_PL011_IMSC_CTSMIM (1 << 1) +#define UART_PL011_IMSC_RIMIM (1 << 0) diff --git a/drivers/serial_pl010.c b/drivers/serial_pl010.c deleted file mode 100644 index 417b6aeda64..00000000000 --- a/drivers/serial_pl010.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ -/* Should be fairly simple to make it work with the PL010 as well */ - -#include - -#ifdef CFG_PL010_SERIAL - -#include "serial_pl011.h" - -#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) -#define IO_READ(addr) (*(volatile unsigned int *)(addr)) - -/* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */ -#define CONSOLE_PORT CONFIG_CONS_INDEX -#define baudRate CONFIG_BAUDRATE -static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; -#define NUM_PORTS (sizeof(port)/sizeof(port[0])) - - -static void pl010_putc (int portnum, char c); -static int pl010_getc (int portnum); -static int pl010_tstc (int portnum); - - -int serial_init (void) -{ - unsigned int divisor; - - /* - ** First, disable everything. - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0); - - /* - ** Set baud rate - ** - */ - switch (baudRate) { - case 9600: - divisor = UART_PL010_BAUD_9600; - break; - - case 19200: - divisor = UART_PL010_BAUD_9600; - break; - - case 38400: - divisor = UART_PL010_BAUD_38400; - break; - - case 57600: - divisor = UART_PL010_BAUD_57600; - break; - - case 115200: - divisor = UART_PL010_BAUD_115200; - break; - - default: - divisor = UART_PL010_BAUD_38400; - } - - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM, - ((divisor & 0xf00) >> 8)); - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff)); - - /* - ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH, - (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN)); - - /* - ** Finally, enable the UART - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN)); - - return (0); -} - -void serial_putc (const char c) -{ - if (c == '\n') - pl010_putc (CONSOLE_PORT, '\r'); - - pl010_putc (CONSOLE_PORT, c); -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc (void) -{ - return pl010_getc (CONSOLE_PORT); -} - -int serial_tstc (void) -{ - return pl010_tstc (CONSOLE_PORT); -} - -void serial_setbrg (void) -{ -} - -static void pl010_putc (int portnum, char c) -{ - /* Wait until there is space in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); - - /* Send the character */ - IO_WRITE (port[portnum] + UART_PL01x_DR, c); -} - -static int pl010_getc (int portnum) -{ - unsigned int data; - - /* Wait until there is data in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); - - data = IO_READ (port[portnum] + UART_PL01x_DR); - - /* Check for an error flag */ - if (data & 0xFFFFFF00) { - /* Clear the error */ - IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); - return -1; - } - - return (int) data; -} - -static int pl010_tstc (int portnum) -{ - return !(IO_READ (port[portnum] + UART_PL01x_FR) & - UART_PL01x_FR_RXFE); -} - -#endif diff --git a/drivers/serial_pl011.c b/drivers/serial_pl011.c deleted file mode 100644 index 4d35fe5e9ed..00000000000 --- a/drivers/serial_pl011.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ -/* Should be fairly simple to make it work with the PL010 as well */ - -#include - -#ifdef CFG_PL011_SERIAL - -#include "serial_pl011.h" - -#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) -#define IO_READ(addr) (*(volatile unsigned int *)(addr)) - -/* - * IntegratorCP has two UARTs, use the first one, at 38400-8-N-1 - * Versatile PB has four UARTs. - */ - -#define CONSOLE_PORT CONFIG_CONS_INDEX -#define baudRate CONFIG_BAUDRATE -static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; -#define NUM_PORTS (sizeof(port)/sizeof(port[0])) - -static void pl011_putc (int portnum, char c); -static int pl011_getc (int portnum); -static int pl011_tstc (int portnum); - - -int serial_init (void) -{ - unsigned int temp; - unsigned int divider; - unsigned int remainder; - unsigned int fraction; - - /* - ** First, disable everything. - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0); - - /* - ** Set baud rate - ** - ** IBRD = UART_CLK / (16 * BAUD_RATE) - ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) - */ - temp = 16 * baudRate; - divider = CONFIG_PL011_CLOCK / temp; - remainder = CONFIG_PL011_CLOCK % temp; - temp = (8 * remainder) / baudRate; - fraction = (temp >> 1) + (temp & 1); - - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider); - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); - - /* - ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, - (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); - - /* - ** Finally, enable the UART - */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, - (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | - UART_PL011_CR_RXE)); - - return 0; -} - -void serial_putc (const char c) -{ - if (c == '\n') - pl011_putc (CONSOLE_PORT, '\r'); - - pl011_putc (CONSOLE_PORT, c); -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc (void) -{ - return pl011_getc (CONSOLE_PORT); -} - -int serial_tstc (void) -{ - return pl011_tstc (CONSOLE_PORT); -} - -void serial_setbrg (void) -{ -} - -static void pl011_putc (int portnum, char c) -{ - /* Wait until there is space in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); - - /* Send the character */ - IO_WRITE (port[portnum] + UART_PL01x_DR, c); -} - -static int pl011_getc (int portnum) -{ - unsigned int data; - - /* Wait until there is data in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); - - data = IO_READ (port[portnum] + UART_PL01x_DR); - - /* Check for an error flag */ - if (data & 0xFFFFFF00) { - /* Clear the error */ - IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); - return -1; - } - - return (int) data; -} - -static int pl011_tstc (int portnum) -{ - return !(IO_READ (port[portnum] + UART_PL01x_FR) & - UART_PL01x_FR_RXFE); -} - -#endif diff --git a/drivers/serial_pl011.h b/drivers/serial_pl011.h deleted file mode 100644 index 5f20fdd108a..00000000000 --- a/drivers/serial_pl011.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2003, 2004 - * ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * ARM PrimeCell UART's (PL010 & PL011) - * ------------------------------------ - * - * Definitions common to both PL010 & PL011 - * - */ -#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */ -#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */ -#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */ -#define UART_PL01x_FR 0x18 /* Flag register (Read only). */ - -#define UART_PL01x_RSR_OE 0x08 -#define UART_PL01x_RSR_BE 0x04 -#define UART_PL01x_RSR_PE 0x02 -#define UART_PL01x_RSR_FE 0x01 - -#define UART_PL01x_FR_TXFE 0x80 -#define UART_PL01x_FR_RXFF 0x40 -#define UART_PL01x_FR_TXFF 0x20 -#define UART_PL01x_FR_RXFE 0x10 -#define UART_PL01x_FR_BUSY 0x08 -#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) - -/* - * PL010 definitions - * - */ -#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */ -#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */ -#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */ -#define UART_PL010_CR 0x14 /* Control register. */ -#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */ -#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */ -#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */ - -#define UART_PL010_CR_LPE (1 << 7) -#define UART_PL010_CR_RTIE (1 << 6) -#define UART_PL010_CR_TIE (1 << 5) -#define UART_PL010_CR_RIE (1 << 4) -#define UART_PL010_CR_MSIE (1 << 3) -#define UART_PL010_CR_IIRLP (1 << 2) -#define UART_PL010_CR_SIREN (1 << 1) -#define UART_PL010_CR_UARTEN (1 << 0) - -#define UART_PL010_LCRH_WLEN_8 (3 << 5) -#define UART_PL010_LCRH_WLEN_7 (2 << 5) -#define UART_PL010_LCRH_WLEN_6 (1 << 5) -#define UART_PL010_LCRH_WLEN_5 (0 << 5) -#define UART_PL010_LCRH_FEN (1 << 4) -#define UART_PL010_LCRH_STP2 (1 << 3) -#define UART_PL010_LCRH_EPS (1 << 2) -#define UART_PL010_LCRH_PEN (1 << 1) -#define UART_PL010_LCRH_BRK (1 << 0) - - -#define UART_PL010_BAUD_460800 1 -#define UART_PL010_BAUD_230400 3 -#define UART_PL010_BAUD_115200 7 -#define UART_PL010_BAUD_57600 15 -#define UART_PL010_BAUD_38400 23 -#define UART_PL010_BAUD_19200 47 -#define UART_PL010_BAUD_14400 63 -#define UART_PL010_BAUD_9600 95 -#define UART_PL010_BAUD_4800 191 -#define UART_PL010_BAUD_2400 383 -#define UART_PL010_BAUD_1200 767 -/* - * PL011 definitions - * - */ -#define UART_PL011_IBRD 0x24 -#define UART_PL011_FBRD 0x28 -#define UART_PL011_LCRH 0x2C -#define UART_PL011_CR 0x30 -#define UART_PL011_IMSC 0x38 -#define UART_PL011_PERIPH_ID0 0xFE0 - -#define UART_PL011_LCRH_SPS (1 << 7) -#define UART_PL011_LCRH_WLEN_8 (3 << 5) -#define UART_PL011_LCRH_WLEN_7 (2 << 5) -#define UART_PL011_LCRH_WLEN_6 (1 << 5) -#define UART_PL011_LCRH_WLEN_5 (0 << 5) -#define UART_PL011_LCRH_FEN (1 << 4) -#define UART_PL011_LCRH_STP2 (1 << 3) -#define UART_PL011_LCRH_EPS (1 << 2) -#define UART_PL011_LCRH_PEN (1 << 1) -#define UART_PL011_LCRH_BRK (1 << 0) - -#define UART_PL011_CR_CTSEN (1 << 15) -#define UART_PL011_CR_RTSEN (1 << 14) -#define UART_PL011_CR_OUT2 (1 << 13) -#define UART_PL011_CR_OUT1 (1 << 12) -#define UART_PL011_CR_RTS (1 << 11) -#define UART_PL011_CR_DTR (1 << 10) -#define UART_PL011_CR_RXE (1 << 9) -#define UART_PL011_CR_TXE (1 << 8) -#define UART_PL011_CR_LPE (1 << 7) -#define UART_PL011_CR_IIRLP (1 << 2) -#define UART_PL011_CR_SIREN (1 << 1) -#define UART_PL011_CR_UARTEN (1 << 0) - -#define UART_PL011_IMSC_OEIM (1 << 10) -#define UART_PL011_IMSC_BEIM (1 << 9) -#define UART_PL011_IMSC_PEIM (1 << 8) -#define UART_PL011_IMSC_FEIM (1 << 7) -#define UART_PL011_IMSC_RTIM (1 << 6) -#define UART_PL011_IMSC_TXIM (1 << 5) -#define UART_PL011_IMSC_RXIM (1 << 4) -#define UART_PL011_IMSC_DSRMIM (1 << 3) -#define UART_PL011_IMSC_DCDMIM (1 << 2) -#define UART_PL011_IMSC_CTSMIM (1 << 1) -#define UART_PL011_IMSC_RIMIM (1 << 0) -- cgit v1.3.1 From 58b74b05c621e2835ecf4e2d3243042cf4186777 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 19 Oct 2007 00:09:05 +0200 Subject: Fix missing drivers makefile entries ds1722.c mw_eeprom.c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- drivers/Makefile | 3 ++- drivers/ds1722.c | 4 ++-- drivers/mw_eeprom.c | 4 ++-- 3 files changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/Makefile b/drivers/Makefile index 6bf05ccad19..aba64f573a5 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -54,7 +54,8 @@ COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \ ks8695eth.o \ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ rpx_pcmcia.o \ - fsl_i2c.o fsl_pci_init.o ati_radeon_fb.o + fsl_i2c.o fsl_pci_init.o ati_radeon_fb.o \ + ds1722.o mw_eeprom.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/ds1722.c b/drivers/ds1722.c index 227d8169a5b..c19ee01393f 100644 --- a/drivers/ds1722.c +++ b/drivers/ds1722.c @@ -1,10 +1,10 @@ #include -#include - #ifdef CONFIG_DS1722 +#include + static void ds1722_select(int dev) { ssi_set_interface(4096, 0, 0, 0); diff --git a/drivers/mw_eeprom.c b/drivers/mw_eeprom.c index 2a1f4898429..2b3348810d2 100644 --- a/drivers/mw_eeprom.c +++ b/drivers/mw_eeprom.c @@ -1,11 +1,11 @@ /* Three-wire (MicroWire) serial eeprom driver (for 93C46 and compatibles) */ #include -#include - #ifdef CONFIG_MW_EEPROM +#include + /* * Serial EEPROM opcodes, including start bit */ -- cgit v1.3.1 From 41b4d282d38fa7231c315c5f6cfff5bdd24e0191 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 23 Oct 2007 16:50:03 +0200 Subject: Coding style: keep lists sorted; update CHANGELOG Signed-off-by: Wolfgang Denk --- CHANGELOG | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/Makefile | 30 +++++++++++++--------------- 2 files changed, 75 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/CHANGELOG b/CHANGELOG index 05400013897..549c4f919cb 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,64 @@ +commit 58b74b05c621e2835ecf4e2d3243042cf4186777 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Fri Oct 19 00:09:05 2007 +0200 + + Fix missing drivers makefile entries ds1722.c mw_eeprom.c + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 96455bfebc9887837095c9051d216f53c61b5f10 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Fri Oct 19 00:07:39 2007 +0200 + + Fix warning differ in signedness in board/innokom/innokom.c + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 2a4741d9a14ec475f50e9856d2c0a67e8b4271bd +Author: Marcel Ziswiler +Date: Fri Oct 19 00:25:33 2007 +0200 + + fix pxa255_idp board + + The pxa255_idp being an old unmaintained board showed several issues: + 1. CONFIG_INIT_CRITICAL was still defined. + 2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined. + 3. Symbol flash_addr was undeclared. + 4. The boards lowlevel_init function was still called memsetup. + 5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000. + 6. Using -march=armv5 instead of -march=armv5te resulted in lots of + 'target CPU does not support interworking' warnings on recent compilers. + 7. The PXA's serial driver redefined FFUART, BTUART and STUART used as + indexes rather than the register definitions from the pxa-regs header + file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to + avoid any ambiguities. + 8. There were several redefinition warnings concerning ICMR, OSMR3, + OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file. + 9. The board configuration file was rather outdated. + 10. The part header file defined the vendor, product and revision arrays + as unsigned chars instead of just chars in the block_dev_desc_t + structure. + + Signed-off-by: Marcel Ziswiler + +commit 298cd4cafe81ff8a6c87be8fbc440a20720d3ed6 +Author: Rune Torgersen +Date: Wed Oct 17 11:56:31 2007 -0500 + + Make MPC8266ADS command selection more robust + + Fix MPC8266 command line definition so it won't break when new commands + are added to u-boot. + Signed-off-by Rune Torgersen + +commit 05bf4919c1ce49cdedadacd564d0786a8ed796a1 +Author: Wolfgang Denk +Date: Sun Oct 21 01:01:17 2007 +0200 + + Minor coding style cleanup; update CHANGELOG + + Signed-off-by: Wolfgang Denk + commit ff285ca07eda1ea4a8909848cc1cc604ec8fec9c Author: Vlad Lungu Date: Thu Oct 4 20:47:10 2007 +0300 diff --git a/drivers/Makefile b/drivers/Makefile index aba64f573a5..00978d82853 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -27,35 +27,33 @@ include $(TOPDIR)/config.mk LIB = $(obj)libdrivers.a -COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \ +COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o \ + ati_radeon_fb.o atmel_usart.o \ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ - e1000.o eepro100.o enc28j60.o \ - i8042.o inca-ip_sw.o isp116x-hcd.o keyboard.o \ - lan91c96.o macb.o \ + ds1722.o e1000.o eepro100.o enc28j60.o \ + fsl_i2c.o fsl_pci_init.o \ + i8042.o inca-ip_sw.o isp116x-hcd.o \ + keyboard.o ks8695eth.o \ + lan91c96.o macb.o mpc8xx_pcmcia.o mw_eeprom.o \ natsemi.o ne2000.o netarm_eth.o netconsole.o \ ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \ - omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \ - pcnet.o plb2800_eth.o \ - ps2ser.o ps2mult.o pc_keyb.o \ - rtl8019.o rtl8139.o rtl8169.o \ + omap24xx_i2c.o pc_keyb.o \ + pci.o pci_auto.o pci_indirect.o \ + pcnet.o plb2800_eth.o ps2ser.o ps2mult.o pxa_pcmcia.o \ + rpx_pcmcia.o rtl8019.o rtl8139.o rtl8169.o \ s3c4510b_eth.o s3c4510b_uart.o \ sed13806.o sed156x.o \ serial.o serial_max3100.o \ serial_pl010.o serial_pl011.o serial_xuartlite.o \ sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ status_led.o sym53c8xx.o systemace.o ahci.o \ - ti_pci1410a.o tigon3.o tsec.o \ + ti_pci1410a.o tigon3.o tqm8xx_pcmcia.o tsec.o \ tsi108_eth.o tsi108_i2c.o tsi108_pci.o \ usb_ohci.o \ usbdcore.o usbdcore_ep0.o usbdcore_mpc8xx.o usbdcore_omap1510.o \ usbtty.o \ - videomodes.o w83c553f.o \ - ks8695eth.o \ - pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ - rpx_pcmcia.o \ - fsl_i2c.o fsl_pci_init.o ati_radeon_fb.o \ - ds1722.o mw_eeprom.o + videomodes.o w83c553f.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -- cgit v1.3.1 From cb8250fe4b3c4ed549b270e8a20bc22060e7e1d2 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 19 Oct 2007 17:51:40 -0500 Subject: fsl_pci_init enable COMMAND_MEMORY if inbound window Patch 16e23c3f removed PCSRBAR allocation. But passing zero windows to pciauto_setup_device has the side effect of not getting COMMAND_MEMORY set. Signed-off-by: Ed Swarthout --- drivers/fsl_pci_init.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 3a13eea1f2b..1e778844a5a 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -54,6 +54,7 @@ fsl_pci_init(struct pci_controller *hose) u8 temp8; int r; int bridge; + int inbound = 0; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; pci_dev_t dev = PCI_BDF(busno,0,0); @@ -74,6 +75,7 @@ fsl_pci_init(struct pci_controller *hose) PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | (__ilog2(hose->regions[r].size) - 1); pi++; + inbound = hose->regions[r].size > 0; } else { /* Outbound */ po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff; @@ -138,6 +140,12 @@ fsl_pci_init(struct pci_controller *hose) pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + if (inbound) { + pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); + pci_hose_write_config_word(hose, dev, PCI_COMMAND, + temp16 | PCI_COMMAND_MEMORY); + } + #ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); -- cgit v1.3.1