From c959374e841de4c9d2317ff3f110f03574e7db79 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 1 Aug 2022 12:11:13 +0200 Subject: gpio: turris_omnia_mcu: Fix usage of CMD_EXT_CONTROL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CMD_GENERAL_CONTROL takes two 8-bit arguments but CMD_EXT_CONTROL takes two 16-bit arguments. Fix this issue and change CMD_EXT_CONTROL arguments to 16-bit. Fixes: 5e4d24ccc115 ("gpio: Add Turris Omnia MCU driver") Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/gpio/turris_omnia_mcu.c | 56 +++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/turris_omnia_mcu.c b/drivers/gpio/turris_omnia_mcu.c index 3e5d74e62cd..986ccde6bc7 100644 --- a/drivers/gpio/turris_omnia_mcu.c +++ b/drivers/gpio/turris_omnia_mcu.c @@ -137,48 +137,44 @@ static int turris_omnia_mcu_get_value(struct udevice *dev, uint offset) static int turris_omnia_mcu_set_value(struct udevice *dev, uint offset, int value) { struct turris_omnia_mcu_info *info = dev_get_plat(dev); - u8 val[2]; - int ret; - u8 reg; + u8 val16[2]; + u8 val32[4]; switch (offset) { /* bank 0 */ - case ilog2(STS_USB30_PWRON): - reg = CMD_GENERAL_CONTROL; - val[1] = CTL_USB30_PWRON; - break; - case ilog2(STS_USB31_PWRON): - reg = CMD_GENERAL_CONTROL; - val[1] = CTL_USB31_PWRON; - break; - case ilog2(STS_ENABLE_4V5): - reg = CMD_GENERAL_CONTROL; - val[1] = CTL_ENABLE_4V5; - break; - case ilog2(STS_BUTTON_MODE): - reg = CMD_GENERAL_CONTROL; - val[1] = CTL_BUTTON_MODE; - break; + case 0 ... 15: + switch (offset) { + case ilog2(STS_USB30_PWRON): + val16[1] = CTL_USB30_PWRON; + break; + case ilog2(STS_USB31_PWRON): + val16[1] = CTL_USB31_PWRON; + break; + case ilog2(STS_ENABLE_4V5): + val16[1] = CTL_ENABLE_4V5; + break; + case ilog2(STS_BUTTON_MODE): + val16[1] = CTL_BUTTON_MODE; + break; + default: + return -EINVAL; + } + val16[0] = value ? val16[1] : 0; + return dm_i2c_write(dev, CMD_GENERAL_CONTROL, val16, sizeof(val16)); /* bank 2 - supported only when FEAT_EXT_CMDS is set */ case (16 + 32 + 0) ... (16 + 32 + 15): if (!(info->features & FEAT_EXT_CMDS)) return -EINVAL; - reg = CMD_EXT_CONTROL; - val[1] = BIT(offset - 16 - 32); - break; + val32[3] = BIT(offset - 16 - 32) >> 8; + val32[2] = BIT(offset - 16 - 32) & 0xff; + val32[1] = value ? val32[3] : 0; + val32[0] = value ? val32[2] : 0; + return dm_i2c_write(dev, CMD_EXT_CONTROL, val32, sizeof(val32)); default: return -EINVAL; } - - val[0] = value ? val[1] : 0; - - ret = dm_i2c_write(dev, reg, val, 2); - if (ret) - return ret; - - return 0; } static int turris_omnia_mcu_direction_input(struct udevice *dev, uint offset) -- cgit v1.3.1 From 65b3b24eba7558fa4085a0695b3ad3e7dbf7a3fb Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 4 Aug 2022 11:43:57 +1200 Subject: gpio: Remove mvgpio driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The last user of this driver was removed in commit dee08b1999e2 ("arm: Remove gplugd board"). Remove the unused driver. Signed-off-by: Chris Packham Acked-by: Pali Rohár --- drivers/gpio/Makefile | 1 - drivers/gpio/mvgpio.c | 97 --------------------------------------------------- drivers/gpio/mvgpio.h | 53 ---------------------------- 3 files changed, 151 deletions(-) delete mode 100644 drivers/gpio/mvgpio.c delete mode 100644 drivers/gpio/mvgpio.h (limited to 'drivers') diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 219f37e0e43..39762fa06ce 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -24,7 +24,6 @@ obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o obj-$(CONFIG_KONA_GPIO) += kona_gpio.o -obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c deleted file mode 100644 index 12e7197daf7..00000000000 --- a/drivers/gpio/mvgpio.c +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 - * eInfochips Ltd. - * Written-by: Ajay Bhargav - * - * (C) Copyright 2010 - * Marvell Semiconductor - */ - -#include -#include -#include -#include -#include "mvgpio.h" -#include - -#ifndef MV_MAX_GPIO -#define MV_MAX_GPIO 128 -#endif - -int gpio_request(unsigned gpio, const char *label) -{ - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO requested %d\n", __func__, gpio); - return -1; - } - return 0; -} - -int gpio_free(unsigned gpio) -{ - return 0; -} - -int gpio_direction_input(unsigned gpio) -{ - struct gpio_reg *gpio_reg_bank; - - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gpio); - return -1; - } - - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); - writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gcdr); - return 0; -} - -int gpio_direction_output(unsigned gpio, int value) -{ - struct gpio_reg *gpio_reg_bank; - - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gpio); - return -1; - } - - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); - writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gsdr); - gpio_set_value(gpio, value); - return 0; -} - -int gpio_get_value(unsigned gpio) -{ - struct gpio_reg *gpio_reg_bank; - u32 gpio_val; - - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gpio); - return -1; - } - - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); - gpio_val = readl(&gpio_reg_bank->gplr); - - return GPIO_VAL(gpio, gpio_val); -} - -int gpio_set_value(unsigned gpio, int value) -{ - struct gpio_reg *gpio_reg_bank; - - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gpio); - return -1; - } - - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); - if (value) - writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gpsr); - else - writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gpcr); - - return 0; -} diff --git a/drivers/gpio/mvgpio.h b/drivers/gpio/mvgpio.h deleted file mode 100644 index d68c48e6373..00000000000 --- a/drivers/gpio/mvgpio.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * eInfochips Ltd. - * Written-by: Ajay Bhargav - * - * (C) Copyright 2010 - * Marvell Semiconductor - */ - -#ifndef __MVGPIO_H__ -#define __MVGPIO_H__ - -#include - -/* - * GPIO Register map for Marvell SOCs - */ -struct gpio_reg { - u32 gplr; /* Pin Level Register - 0x0000 */ - u32 pad0[2]; - u32 gpdr; /* Pin Direction Register - 0x000C */ - u32 pad1[2]; - u32 gpsr; /* Pin Output Set Register - 0x0018 */ - u32 pad2[2]; - u32 gpcr; /* Pin Output Clear Register - 0x0024 */ - u32 pad3[2]; - u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */ - u32 pad4[2]; - u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */ - u32 pad5[2]; - u32 gedr; /* Edge Detect Status Register - 0x0048 */ - u32 pad6[2]; - u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */ - u32 pad7[2]; - u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */ - u32 pad8[2]; - u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable - Register - 0x006C */ - u32 pad9[2]; - u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable - Register - 0x0078 */ - u32 pad10[2]; - u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable - Register - 0x0084 */ - u32 pad11[2]; - u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable - Register - 0x0090 */ - u32 pad12[2]; - u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */ -}; - -#endif /* __MVGPIO_H__ */ -- cgit v1.3.1 From 7a1c07117372c746258f79e035dc188fe52c1b48 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Thu, 4 Aug 2022 12:41:54 +0200 Subject: arm64: a37xx: pinctrl: Fix definitions for MPP pins 20-22 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All 3 MPP pins (20, 21 and 22) can be configured individually and also can be configured to GPIO functions. Fix definitions for these MPP pins in existing pin groups. After this change GPIO function can be enabled just for one of these 3 pins. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index bb7a76baed1..a5407a16ee3 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -200,9 +200,11 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), - PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), - PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), - PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), + PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"), + PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12), + "ptp", "mii"), + PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13), + "ptp", "mii"), PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), "mii", "mii_err"), }; -- cgit v1.3.1 From 361cf5c7e1ec01c8660fa549edac86ecb435913a Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Thu, 4 Aug 2022 12:41:55 +0200 Subject: arm64: a37xx: pinctrl: Remove unused macro PIN_GRP() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Macro PIN_GRP() is not used, remove it. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index a5407a16ee3..32b49f167c6 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -99,16 +99,6 @@ struct armada_37xx_pinctrl { unsigned int nfuncs; }; -#define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \ - { \ - .name = _name, \ - .start_pin = _start, \ - .npins = _nr, \ - .reg_mask = _mask, \ - .val = {0, _mask}, \ - .funcs = {_func1, _func2} \ - } - #define PIN_GRP_GPIO_0(_name, _start, _nr) \ { \ .name = _name, \ -- cgit v1.3.1 From 019090647cab4eb0e9a3ab99e64adde3b65e631e Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Thu, 4 Aug 2022 12:41:56 +0200 Subject: arm64: a37xx: pinctrl: Improve description for pinmux command MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In more cases group name consist of function name followed by function number. So if function name is just prefix of group name, show group name. So in 'pinmux status -a' command output would be visible also extended function number, which is useful for debugging. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 32b49f167c6..25fbe39abd1 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -406,7 +406,17 @@ static int armada_37xx_pmx_get_pin_muxing(struct udevice *dev, unsigned int sele for (f = 0; f < NB_FUNCS && grp->funcs[f]; f++) { if (grp->val[f] == val) { - strlcpy(buf, grp->funcs[f], size); + /* + * In more cases group name consist of + * function name followed by function + * number. So if function name is just + * prefix of group name, show group name. + */ + if (strncmp(grp->name, grp->funcs[f], + strlen(grp->funcs[f])) == 0) + strlcpy(buf, grp->name, size); + else + strlcpy(buf, grp->funcs[f], size); return 0; } } -- cgit v1.3.1 From ca3756c86b0ae997699abac7c5371550dd4842a0 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 5 Aug 2022 16:03:41 +0200 Subject: pci: pci_mvebu: Add support for reset-gpios MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Release PERST# signal via GPIO when "reset-gpios" is defined in device tree. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Reviewed-by: Stefan Roese --- drivers/pci/Kconfig | 1 + drivers/pci/pci_mvebu.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) (limited to 'drivers') diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 436acca898e..22f4995453e 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -301,6 +301,7 @@ config PCI_MVEBU depends on (ARCH_KIRKWOOD || ARCH_MVEBU) select MISC select DM_RESET + select DM_GPIO help Say Y here if you want to enable PCIe controller support on Kirkwood and Armada 370/XP/375/38x SoCs. diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index d80f87e0cfc..5bd340a421b 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -60,6 +61,7 @@ struct mvebu_pcie { struct resource mem; void __iomem *iobase; struct resource io; + struct gpio_desc reset_gpio; u32 intregs; u32 port; u32 lane; @@ -416,6 +418,14 @@ static int mvebu_pcie_probe(struct udevice *dev) struct udevice *ctlr = pci_get_controller(dev); struct pci_controller *hose = dev_get_uclass_priv(ctlr); u32 reg; + int ret; + + /* Request for optional PERST# GPIO */ + ret = gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio, GPIOD_IS_OUT); + if (ret && ret != -ENOENT) { + printf("%s: unable to request reset-gpios: %d\n", pcie->name, ret); + return ret; + } /* * Change Class Code of PCI Bridge device to PCI Bridge (0x600400) @@ -537,6 +547,10 @@ static int mvebu_pcie_probe(struct udevice *dev) pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] = PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16); + /* Release PERST# via GPIO when it was defined */ + if (dm_gpio_is_valid(&pcie->reset_gpio)) + dm_gpio_set_value(&pcie->reset_gpio, 0); + mvebu_pcie_wait_for_link(pcie); return 0; -- cgit v1.3.1 From ca514d0267f92d8aac2eb5f92ff7d150078df423 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Thu, 4 Aug 2022 13:03:44 +0200 Subject: misc: atsha204a: Don't check for error when waking up the device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The device ignores any levels or transitions on the SCL pin when the device is idle, asleep or during waking up. Linux kernel driver for atsha204a (atmel-sha204a.ko) also ignores return value from i2c wakeup send command, see: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/crypto/atmel-i2c.c?h=v5.19#n174 And also userspace Turris libatsha204 library ignores return value from wakeup send command, see: https://gitlab.nic.cz/turris/libatsha204/-/blob/v29.2/src/libatsha204/layer_ni2c.c#L75-76 U-Boot driver should do same thing. Fixes waking up ATSHA204 on Turris 1.x boards. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Tested-by: Paweł Anikiel Reviewed-by: Marek Behún --- drivers/misc/atsha204a-i2c.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c index e7c6be593dc..d3c515828ff 100644 --- a/drivers/misc/atsha204a-i2c.c +++ b/drivers/misc/atsha204a-i2c.c @@ -103,12 +103,13 @@ int atsha204a_wakeup(struct udevice *dev) for (try = 1; try <= 10; ++try) { debug("Try %i... ", try); + /* + * The device ignores any levels or transitions on the SCL pin + * when the device is idle, asleep or during waking up. + * Don't check for error when waking up the device. + */ memset(req, 0, 4); - res = atsha204a_send(dev, req, 4); - if (res) { - debug("failed on I2C send, trying again\n"); - continue; - } + atsha204a_send(dev, req, 4); udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US); -- cgit v1.3.1