From 7c8e0e052853a181e379735f25cfe85dfb575e1c Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 25 May 2017 17:03:23 -0700 Subject: driver: ddr: fsl: Fix compiling error for DDR2 Fix compiling error of "no member named 'taamin_ps'" for DDR2. Signed-off-by: York Sun --- drivers/ddr/fsl/interactive.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index 202ad138f99..653bbabc956 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -154,7 +154,9 @@ static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo, static const struct options_string options[] = { COMMON_TIMING(tckmin_x_ps), COMMON_TIMING(tckmax_ps), +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) COMMON_TIMING(taamin_ps), +#endif COMMON_TIMING(trcd_ps), COMMON_TIMING(trp_ps), COMMON_TIMING(tras_ps), @@ -422,7 +424,9 @@ static void print_lowest_common_dimm_parameters( const common_timing_params_t *plcd_dimm_params) { static const struct options_string options[] = { +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) COMMON_TIMING(taamin_ps), +#endif COMMON_TIMING(trcd_ps), COMMON_TIMING(trp_ps), COMMON_TIMING(tras_ps), -- cgit v1.2.3 From ef621da7f87a4e6907276595dbb9b6eba8784ddf Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jun 2017 09:22:40 -0700 Subject: net: phy: marvell: Fix init function for m88e1145 Commit a058052c changed the generic phy_reset() to clear all bits in BMCR. This inevitably clears the ANEG bit. m88e1145 requires any change to ANEG bit to be followed by a software reset. This seems to be different from other PHYs. Implement read-modify-write procedure for this PHY init. Signed-off-by: York Sun Acked-by: Joe Hershberger --- drivers/net/phy/marvell.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 8041922a02d..b7f300e40f2 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -482,7 +482,10 @@ static int m88e1145_config(struct phy_device *phydev) genphy_config_aneg(phydev); - phy_reset(phydev); + /* soft reset */ + reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + reg |= BMCR_RESET; + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); return 0; } -- cgit v1.2.3