From 716527299a496afcbf495d38bd9e5edfd71ce120 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Oct 2022 13:05:39 +0200 Subject: Revert "pinctrl: zynqmp: Add support for output-enable and bias-high-impedance" This reverts commit 123462e5e534d6e17b1b7d2006734bbe54b03e0a. On systems with older PMUFW using these pinctrl properties can cause system hang because there is missing feature autodetection. When it is implemented support for these two properties should go back. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c2900319ea80484f21692997f296269aee701c1f.1665659138.git.michal.simek@amd.com --- drivers/pinctrl/pinctrl-zynqmp.c | 9 --------- 1 file changed, 9 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 52d428f566f..7c5a02db1b9 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -467,10 +467,6 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, pin); break; case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - param = PM_PINCTRL_CONFIG_TRI_STATE; - arg = PM_PINCTRL_TRI_STATE_ENABLE; - ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); - break; case PIN_CONFIG_LOW_POWER_MODE: /* * This cases are mentioned in dts but configurable @@ -479,11 +475,6 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, */ ret = 0; break; - case PIN_CONFIG_OUTPUT_ENABLE: - param = PM_PINCTRL_CONFIG_TRI_STATE; - arg = PM_PINCTRL_TRI_STATE_DISABLE; - ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); - break; default: dev_warn(dev, "unsupported configuration parameter '%u'\n", param); -- cgit v1.2.3 From ba74bcf3e07b10ffebf42e72a656b420215b5a2e Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Mon, 17 Oct 2022 15:18:18 +0530 Subject: xilinx: common: Remove zynq_board_read_rom_ethaddr() Removing the zynq_board_read_rom_ethaddr() function as xlnx,eeprom is not used anymore. As all board dts to use nvmem alias instead of xlnx,eeprom. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20221017094818.17996-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 16 ---------------- 1 file changed, 16 deletions(-) (limited to 'drivers') diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 3f4357ec80b..507b19b7597 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -662,21 +662,6 @@ static void zynq_gem_halt(struct udevice *dev) ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); } -__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) -{ - return -ENOSYS; -} - -static int zynq_gem_read_rom_mac(struct udevice *dev) -{ - struct eth_pdata *pdata = dev_get_plat(dev); - - if (!pdata) - return -ENOSYS; - - return zynq_board_read_rom_ethaddr(pdata->enetaddr); -} - static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { @@ -884,7 +869,6 @@ static const struct eth_ops zynq_gem_ops = { .free_pkt = zynq_gem_free_pkt, .stop = zynq_gem_halt, .write_hwaddr = zynq_gem_setup_mac, - .read_rom_hwaddr = zynq_gem_read_rom_mac, }; static int zynq_gem_of_to_plat(struct udevice *dev) -- cgit v1.2.3 From 1e766a04c723e003c001c0f1a4f301aef026a75e Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Wed, 12 Oct 2022 08:36:54 +0300 Subject: timer-uclass: add timer_get_ops() macro Align timer uclass with the other subsystems and provide a timer_get_ops() convenience macro. Using this instead of the generic device_get_ops() also prevents -Wdiscarded-qualifiers warnings when used with non-const variables. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/20221012053656.1492457-1-ovpanait@gmail.com Signed-off-by: Michal Simek --- drivers/timer/timer-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index cbc36476987..bdc77b38223 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; int notrace timer_get_count(struct udevice *dev, u64 *count) { - const struct timer_ops *ops = device_get_ops(dev); + struct timer_ops *ops = timer_get_ops(dev); if (!ops->get_count) return -ENOSYS; -- cgit v1.2.3 From 8272d4cb897ca15eef2f39afe488f6731312e5c2 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Wed, 12 Oct 2022 08:36:55 +0300 Subject: timer-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOC Relocate timer_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled. The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done logic works for drivers that use DM_FLAG_PRE_RELOC. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/20221012053656.1492457-2-ovpanait@gmail.com Signed-off-by: Michal Simek --- drivers/timer/timer-uclass.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers') diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index bdc77b38223..bb719792135 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -18,6 +18,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +51,19 @@ unsigned long notrace timer_get_rate(struct udevice *dev) static int timer_pre_probe(struct udevice *dev) { + if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) && + (gd->flags & GD_FLG_RELOC)) { + struct timer_ops *ops = timer_get_ops(dev); + static int reloc_done; + + if (!reloc_done) { + if (ops->get_count) + MANUAL_RELOC(ops->get_count); + + reloc_done++; + } + } + if (CONFIG_IS_ENABLED(OF_REAL)) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct clk timer_clk; -- cgit v1.2.3 From b34bc22bd9921547246c117fb95eb58bedaceff5 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Wed, 12 Oct 2022 08:36:56 +0300 Subject: timer: xilinx-timer: use timer_conv_64() to fix timer wrap around Current xilinx_timer_get_count() implementation does not take into account the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter register value. The roll-overs cause problems in the upper timer layers, as generic timer code expects an incrementing 64-bit value from get_count() to work correctly. Add the missing 64-bit up-conversion to fix random hangs/delays in __udelay(). Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver") Signed-off-by: Ovidiu Panait Reviewed-by: Michal Simek Link: https://lore.kernel.org/r/20221012053656.1492457-3-ovpanait@gmail.com Signed-off-by: Michal Simek --- drivers/timer/xilinx-timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c index 75b4473b639..172fd9f9296 100644 --- a/drivers/timer/xilinx-timer.c +++ b/drivers/timer/xilinx-timer.c @@ -40,7 +40,7 @@ static u64 xilinx_timer_get_count(struct udevice *dev) regmap_read(priv->regs, TIMER_COUNTER_OFFSET, &value); - return value; + return timer_conv_64(value); } static int xilinx_timer_probe(struct udevice *dev) -- cgit v1.2.3 From 2e9946aba8e770a626ea5b9a23c95981569d6e61 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 31 Oct 2022 17:08:44 -0700 Subject: net: phy: Fix ethernet-phy-id in the code Use dot instead of comma. The fix doesn't affect anything but it is good to be aligned with used pattern. The first is used only for string size calculation and the second change is in the comment. Fixes: db681d4929ca ("net: phy: Add new read ethernet phy id function") Signed-off-by: Michal Simek --- drivers/core/ofnode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 14bbfe72327..4d56b1a7675 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -1197,12 +1197,12 @@ int ofnode_read_eth_phy_id(ofnode node, u16 *vendor, u16 *device) while (list < end) { len = strlen(list); - if (len >= strlen("ethernet-phy-idVVVV,DDDD")) { + if (len >= strlen("ethernet-phy-idVVVV.DDDD")) { char *s = strstr(list, "ethernet-phy-id"); /* * check if the string is something like - * ethernet-phy-idVVVV,DDDD + * ethernet-phy-idVVVV.DDDD */ if (s && s[19] == '.') { s += strlen("ethernet-phy-id"); -- cgit v1.2.3 From 64fc7fc887a5341bff46ac030d0b5c68eb781b5a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Nov 2022 16:36:35 +0100 Subject: soc: xilinx: versal-net: Add soc_xilinx_versal_net driver Add soc_xilinx_versal_net driver to identify the family & revision of versal-net SoC. Add Kconfig option CONFIG_SOC_XILINX_VERSAL_NET to enable/disable this driver. To enable this driver by default, add this config to xilinx_versal_net_virt_defconfig file. This driver will be probed using platdata U_BOOT_DEVICE structure which is specified in mach-versal-net/cpu.c. Signed-off-by: Michal Simek Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/613d6bcffd9070f62cf348079ed16c120f8fc56f.1668612993.git.michal.simek@amd.com --- drivers/soc/Kconfig | 8 ++++ drivers/soc/Makefile | 1 + drivers/soc/soc_xilinx_versal_net.c | 78 +++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 drivers/soc/soc_xilinx_versal_net.c (limited to 'drivers') diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 292dc41b6fa..acf555baaec 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -32,6 +32,14 @@ config SOC_XILINX_VERSAL This allows other drivers to verify the SoC familiy & revision using matching SoC attributes. +config SOC_XILINX_VERSAL_NET + bool "Enable SoC Device ID driver for Xilinx Versal NET" + depends on SOC_DEVICE && ARCH_VERSAL_NET + help + Enable this option to select SoC device id driver for Xilinx Versal NET. + This allows other drivers to verify the SoC familiy & revision using + matching SoC attributes. + source "drivers/soc/ti/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 031fa7612f4..84385650d46 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o obj-$(CONFIG_SANDBOX) += soc_sandbox.o obj-$(CONFIG_SOC_XILINX_ZYNQMP) += soc_xilinx_zynqmp.o obj-$(CONFIG_SOC_XILINX_VERSAL) += soc_xilinx_versal.o +obj-$(CONFIG_SOC_XILINX_VERSAL_NET) += soc_xilinx_versal_net.o diff --git a/drivers/soc/soc_xilinx_versal_net.c b/drivers/soc/soc_xilinx_versal_net.c new file mode 100644 index 00000000000..146d068bb4a --- /dev/null +++ b/drivers/soc/soc_xilinx_versal_net.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET SOC driver + * + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* + * v1 -> 0x10 - ES1 + * v2 -> 0x20 - Production + */ +static const char versal_family[] = "Versal NET"; + +struct soc_xilinx_versal_net_priv { + const char *family; + char revision; +}; + +static int soc_xilinx_versal_net_get_family(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_versal_net_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "%s", priv->family); +} + +static int soc_xilinx_versal_net_get_revision(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_versal_net_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "v%d", priv->revision); +} + +static const struct soc_ops soc_xilinx_versal_net_ops = { + .get_family = soc_xilinx_versal_net_get_family, + .get_revision = soc_xilinx_versal_net_get_revision, +}; + +static int soc_xilinx_versal_net_probe(struct udevice *dev) +{ + struct soc_xilinx_versal_net_priv *priv = dev_get_priv(dev); + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + priv->family = versal_family; + + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { + ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, + ret_payload); + if (ret) + return ret; + } else { + ret_payload[2] = readl(PMC_TAP_VERSION); + if (!ret_payload[2]) + return -EINVAL; + } + + priv->revision = FIELD_GET(PS_VERSION_MASK, ret_payload[2]); + + return 0; +} + +U_BOOT_DRIVER(soc_xilinx_versal_net) = { + .name = "soc_xilinx_versal_net", + .id = UCLASS_SOC, + .ops = &soc_xilinx_versal_net_ops, + .probe = soc_xilinx_versal_net_probe, + .priv_auto = sizeof(struct soc_xilinx_versal_net_priv), + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v1.2.3 From 450d8eb54fe3016d7e265f9acca96575d2bf1f6e Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 16 Nov 2022 16:40:30 +0100 Subject: qspi: versal-net: Add condition for tapdelay register Add CONFIG_ARCH_VERSAL_NET to select tapdelay register for versal-net. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/2500dd688214e2ec2d54ed3fabbfee0b1ca861a6.1668613229.git.michal.simek@amd.com --- drivers/spi/zynqmp_gqspi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 49facc46d3c..48eff777dfb 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -104,7 +104,8 @@ #define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 #define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8 -#define IOU_TAPDLY_BYPASS_OFST !IS_ENABLED(CONFIG_ARCH_VERSAL) ? \ +#define IOU_TAPDLY_BYPASS_OFST !(IS_ENABLED(CONFIG_ARCH_VERSAL) || \ + IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) ? \ 0xFF180390 : 0xF103003C #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020 #define GQSPI_FREQ_37_5MHZ 37500000 -- cgit v1.2.3 From ce8adf1a415b3027cc74c4e41e32cffad3e5ea40 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 16 Nov 2022 07:11:54 -0700 Subject: spi: cadence-qspi: Fix compilation error in mini u-boot flash reset When cadence_qspi_versal_flash_reset() function is called in mini u-boot where there is no firmware support, it is missing defines for macro's BOOT_MODE_POR_0 & BOOT_MODE_POR_1. Remove them and replace with already define macro's which have same values as these. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20221116141155.14788-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/spi/cadence_ospi_versal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index a9547a82003..e0d5e6b9e69 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -182,11 +182,11 @@ int cadence_qspi_versal_flash_reset(struct udevice *dev) /* set direction as output */ writel((readl(BOOT_MODE_DIR) | BIT(FLASH_RESET_GPIO)), - BOOT_MODE_POR_0); + BOOT_MODE_DIR); /* Data output enable */ writel((readl(BOOT_MODE_OUT) | BIT(FLASH_RESET_GPIO)), - BOOT_MODE_POR_1); + BOOT_MODE_OUT); /* IOU SLCR write enable */ writel(0, WPROT_PMC_MIO); -- cgit v1.2.3