From 942b5fc03218d1c94468fc658e7dec65dabcc830 Mon Sep 17 00:00:00 2001 From: Benedikt Grassl Date: Tue, 14 Apr 2020 07:32:12 +0200 Subject: mmc: zynq: parse dt when probing Currently, the entry "bus-width = <8>" in the ZynqMP's sdhci nodes is not evaluated. This results in the bus width staying at its default value (4 bit in HS200 mode). Fix this by calling mmc_of_parse. This function also checks for the "no-1-8-v" and "max-frequency" entries. Remove the handling of those nodes from this driver. Signed-off-by: Benedikt Grassl Reviewed-by: Jaehoon Chung Signed-off-by: Michal Simek --- drivers/mmc/sdhci.c | 3 +-- drivers/mmc/zynq_sdhci.c | 15 ++++++--------- 2 files changed, 7 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 520c9f9feba..372dc0a8201 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -839,8 +839,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, cfg->host_caps &= ~MMC_MODE_HS_52MHz; } - if (!(cfg->voltages & MMC_VDD_165_195) || - (host->quirks & SDHCI_QUIRK_NO_1_8_V)) + if (!(cfg->voltages & MMC_VDD_165_195)) caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index da3ff53da10..18925d01fa0 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -22,14 +22,12 @@ DECLARE_GLOBAL_DATA_PTR; struct arasan_sdhci_plat { struct mmc_config cfg; struct mmc mmc; - unsigned int f_max; }; struct arasan_sdhci_priv { struct sdhci_host *host; u8 deviceid; u8 bank; - u8 no_1p8; }; #if defined(CONFIG_ARCH_ZYNQMP) @@ -238,8 +236,11 @@ static int arasan_sdhci_probe(struct udevice *dev) host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE; #endif - if (priv->no_1p8) - host->quirks |= SDHCI_QUIRK_NO_1_8_V; + plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ; + + ret = mmc_of_parse(dev, &plat->cfg); + if (ret) + return ret; host->max_clk = clock; @@ -247,7 +248,7 @@ static int arasan_sdhci_probe(struct udevice *dev) host->mmc->dev = dev; host->mmc->priv = host; - ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max, + ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max, CONFIG_ZYNQ_SDHCI_MIN_FREQ); if (ret) return ret; @@ -258,7 +259,6 @@ static int arasan_sdhci_probe(struct udevice *dev) static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) { - struct arasan_sdhci_plat *plat = dev_get_platdata(dev); struct arasan_sdhci_priv *priv = dev_get_priv(dev); priv->host = calloc(1, sizeof(struct sdhci_host)); @@ -277,10 +277,7 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1); priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1); - priv->no_1p8 = dev_read_bool(dev, "no-1-8-v"); - plat->f_max = dev_read_u32_default(dev, "max-frequency", - CONFIG_ZYNQ_SDHCI_MAX_FREQ); return 0; } -- cgit v1.3.1 From 7eab624baf96a6d967416ffeb51e3fef289c47ae Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 8 Apr 2020 21:34:54 -0600 Subject: clk: versal: Fix watchdog clock issue Enable mux based clocks to populate LPD_LSBUS clock to xilinx_wwdt driver. Skip reading clock rate for the mux based clocks with parent clock id is zero. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma --- drivers/clk/clk_versal.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index d3673a5c8b8..075a08380d8 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -503,6 +503,9 @@ static u64 versal_clock_calc(u32 clk_id) NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF) return versal_clock_ref(clk_id); + if (!parent_id) + return 0; + clk_rate = versal_clock_calc(parent_id); if (versal_clock_div(clk_id)) { @@ -526,7 +529,7 @@ static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate) NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT && ((clk_id >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK) == NODE_CLASS_CLOCK) { - if (!versal_clock_gate(clk_id)) + if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id)) return -EINVAL; *clk_rate = versal_clock_calc(clk_id); return 0; -- cgit v1.3.1 From 27d706937a5c72f0414a540ca20fd36b4b72bda7 Mon Sep 17 00:00:00 2001 From: Patrick van Gelder Date: Fri, 24 Apr 2020 01:28:56 -0600 Subject: ARM: zynq: Fix invalid check on NAND_CMD_NONE. The end_cmd field in the variables cmd_phase_addr and data_phase_addr contains the value 0xFF when the end_cmd equals NAND_CMD_NONE. This should be 0x00. This is caused by comparing NAND_CMD_NONE (int) with end_cmd (u8). end_cmd will be promoted by the int value -1 and therefore is not equal to 0xFF. Solved by casting NAND_CMD_NONE to u8 which will avoid int promotion. Signed-off-by: Patrick van Gelder Reviewed-by: T Karthik Reddy Signed-off-by: Michal Simek --- drivers/mtd/nand/raw/zynq_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index 0aea83dac0e..39412974183 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -845,7 +845,7 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE) end_cmd_valid = 1; - if (curr_cmd->end_cmd == NAND_CMD_NONE) + if (curr_cmd->end_cmd == (u8)NAND_CMD_NONE) end_cmd = 0x0; else end_cmd = curr_cmd->end_cmd; -- cgit v1.3.1