From c43acfdc24a13882200b3bdc81c0ecd1329a1212 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 20 Dec 2018 11:33:42 +0800 Subject: rockchip: ram: update license for sdram driver Rockchip may use this sdram copy of source code for both open source and internal project, update the license to use both GPL2.0+ and BSD-3 Clause. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich --- drivers/ram/rockchip/sdram_rk3128.c | 2 +- drivers/ram/rockchip/sdram_rk3188.c | 2 +- drivers/ram/rockchip/sdram_rk322x.c | 2 +- drivers/ram/rockchip/sdram_rk3288.c | 2 +- drivers/ram/rockchip/sdram_rk3328.c | 2 +- drivers/ram/rockchip/sdram_rk3399.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c index 49689002114..df7b9887033 100644 --- a/drivers/ram/rockchip/sdram_rk3128.c +++ b/drivers/ram/rockchip/sdram_rk3128.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index 3774abfa98a..fdd500aa472 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index e079ef7a70c..53835a9cd08 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index bb3cf48788c..d1e52d84e7a 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 89d95b4f897..e8b234d8665 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 49ebd8809f0..94dd01156a7 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2016-2017 Rockchip Inc. * -- cgit v1.3.1 From ddc824f89aa81d2e6749a9c6967eeb70a2fcdbb1 Mon Sep 17 00:00:00 2001 From: Christoph Muellner Date: Wed, 2 Jan 2019 15:09:16 +0100 Subject: power: regulator: Allow PWM regulator to be omitted from SPL. This patch allows to enable the PWM regulator driver independent for U-Boot and SPL. Signed-off-by: Christoph Muellner Reviewed-by: Philipp Tomsich --- drivers/power/regulator/Kconfig | 7 +++++++ drivers/power/regulator/Makefile | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 09b311de8bb..3ed0dd2264a 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -61,6 +61,13 @@ config REGULATOR_PWM This driver is controlled by a device tree node which includes voltage limits. +config SPL_REGULATOR_PWM + bool "Enable Driver for PWM regulators in SPL" + depends on REGULATOR_PWM + help + This config enables implementation of driver-model regulator uclass + features for PWM regulators in SPL. + config DM_REGULATOR_MAX77686 bool "Enable Driver Model for REGULATOR MAX77686" depends on DM_REGULATOR && DM_PMIC_MAX77686 diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 8017045d542..f617ce723a9 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o -obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o +obj-$(CONFIG_$(SPL_)REGULATOR_PWM) += pwm_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o -- cgit v1.3.1 From 5ff776889212c080e3d1a33634ac904405ed6845 Mon Sep 17 00:00:00 2001 From: Christoph Muellner Date: Wed, 2 Jan 2019 15:09:18 +0100 Subject: dm: pinctrl: Add pinctrl_decode_pin_config_dm(). pinctrl_decode_pin_config_dm() is basically a feature-equivalent implementation of pinctrl_decode_pin_config(), which operates on struct udevice devices and uses the dev_read_*() API. Signed-off-by: Christoph Muellner Reviewed-by: Philipp Tomsich --- drivers/pinctrl/pinctrl-uclass.c | 22 ++++++++++++++++++++++ include/dm/pinctrl.h | 12 ++++++++++++ 2 files changed, 34 insertions(+) (limited to 'drivers') diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index 29c910c55f3..c8b38d78f6b 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -27,6 +27,28 @@ int pinctrl_decode_pin_config(const void *blob, int node) return flags; } +/* + * TODO: this function is temporary for v2019.01. + * It should be renamed to pinctrl_decode_pin_config(), + * the original pinctrl_decode_pin_config() function should + * be removed and all callers of the original function should + * be migrated to use the new one. + */ +int pinctrl_decode_pin_config_dm(struct udevice *dev) +{ + int pinconfig = 0; + + if (dev->uclass->uc_drv->id != UCLASS_PINCONFIG) + return -EINVAL; + + if (dev_read_bool(dev, "bias-pull-up")) + pinconfig |= 1 << PIN_CONFIG_BIAS_PULL_UP; + else if (dev_read_bool(dev, "bias-pull-down")) + pinconfig |= 1 << PIN_CONFIG_BIAS_PULL_DOWN; + + return pinconfig; +} + #if CONFIG_IS_ENABLED(PINCTRL_FULL) /** * pinctrl_config_one() - apply pinctrl settings for a single node diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h index 63a7d55b888..ff2b82e7c25 100644 --- a/include/dm/pinctrl.h +++ b/include/dm/pinctrl.h @@ -354,6 +354,18 @@ int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph); */ int pinctrl_decode_pin_config(const void *blob, int node); +/** + * pinctrl_decode_pin_config_dm() - decode pin configuration flags + * + * This decodes some of the PIN_CONFIG values into flags, with each value + * being (1 << pin_cfg). This does not support things with values like the + * slew rate. + * + * @pinconfig: Pinconfig udevice + * @return decoded flag value, or -ve on error + */ +int pinctrl_decode_pin_config_dm(struct udevice *dev); + /** * pinctrl_get_gpio_mux() - get the mux value for a particular GPIO * -- cgit v1.3.1 From 600888110d32a6c2c343e1cc3fa3ef040f4031d7 Mon Sep 17 00:00:00 2001 From: Christoph Muellner Date: Wed, 2 Jan 2019 15:09:19 +0100 Subject: rockchip: rk3399: Add improved pinctrl driver. The current pinctrl driver for the RK3399 has a range of qulity issues. E.g. it only implements the .set_state_simple() callback, it does not parse the available pinctrl information from the DTS (instead uses hardcoded values), is not flexible enough to cover devices without 'interrupt' field in the DTS (e.g. PWM), is not written generic enough to make code reusable among other rockchip SoCs... This patch addresses these issues by reimplementing the whole driver from scratch using the .set_state() callback. The new implementation covers all featurese of the old code (i.e. it supports pinmuxing and pullup/pulldown configuration). This patch has been tested on a RK3399-Q7 SoM (Puma). Signed-off-by: Christoph Muellner Reviewed-by: Philipp Tomsich --- drivers/pinctrl/rockchip/pinctrl_rk3399.c | 227 ++++++++++++++++++++++++++++++ 1 file changed, 227 insertions(+) (limited to 'drivers') diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index bc92dd7c062..a1d5e8d0d52 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) 2018 Theobroma Systems Design und Consulting GmbH */ #include @@ -14,11 +15,235 @@ #include #include +static const u32 RK_GRF_P_PULLUP = 1; +static const u32 RK_GRF_P_PULLDOWN = 2; + struct rk3399_pinctrl_priv { struct rk3399_grf_regs *grf; struct rk3399_pmugrf_regs *pmugrf; + struct rockchip_pin_bank *banks; +}; + +/* Location of pinctrl/pinconf registers. */ +enum rk_grf_location { + RK_GRF, + RK_PMUGRF, +}; + +/** + * @nr_pins: number of pins in this bank + * @grf_location: location of pinctrl/pinconf registers + * @bank_num: number of the bank, to account for holes + * @iomux: array describing the 4 iomux sources of the bank + */ +struct rockchip_pin_bank { + u8 nr_pins; + enum rk_grf_location grf_location; + size_t iomux_offset; + size_t pupd_offset; +}; + +#define PIN_BANK(pins, grf, iomux, pupd) \ + { \ + .nr_pins = pins, \ + .grf_location = grf, \ + .iomux_offset = iomux, \ + .pupd_offset = pupd, \ + } + +static struct rockchip_pin_bank rk3399_pin_banks[] = { + PIN_BANK(16, RK_PMUGRF, + offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux), + offsetof(struct rk3399_pmugrf_regs, gpio0_p)), + PIN_BANK(32, RK_PMUGRF, + offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux), + offsetof(struct rk3399_pmugrf_regs, gpio1_p)), + PIN_BANK(32, RK_GRF, + offsetof(struct rk3399_grf_regs, gpio2a_iomux), + offsetof(struct rk3399_grf_regs, gpio2_p)), + PIN_BANK(32, RK_GRF, + offsetof(struct rk3399_grf_regs, gpio3a_iomux), + offsetof(struct rk3399_grf_regs, gpio3_p)), + PIN_BANK(32, RK_GRF, + offsetof(struct rk3399_grf_regs, gpio4a_iomux), + offsetof(struct rk3399_grf_regs, gpio4_p)), }; +static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t *addr, + u32 *shift, u32 *mask) +{ + /* + * In general we four subsequent 32-bit configuration registers + * per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P). + * The configuration for each pin has two bits. + * + * @base...contains the address to the first register. + * @index...defines the pin within the bank (0..31). + * @addr...will be the address of the actual register to use + * @shift...will be the bit position in the configuration register + * @mask...will be the (unshifted) mask + */ + + const u32 pins_per_register = 8; + const u32 config_bits_per_pin = 2; + + /* Get the address of the configuration register. */ + *addr = base + (index / pins_per_register) * sizeof(u32); + + /* Get the bit offset within the configuration register. */ + *shift = (index & (pins_per_register - 1)) * config_bits_per_pin; + + /* Get the (unshifted) mask for the configuration pins. */ + *mask = ((1 << config_bits_per_pin) - 1); + + pr_debug("%s: addr=0x%lx, mask=0x%x, shift=0x%x\n", + __func__, *addr, *mask, *shift); +} + +static void rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr, + struct rockchip_pin_bank *bank, + u32 index, u32 muxval) +{ + uintptr_t iomux_base, addr; + u32 shift, mask; + + iomux_base = grf_addr + bank->iomux_offset; + rk_pinctrl_get_info(iomux_base, index, &addr, &shift, &mask); + + /* Set pinmux register */ + rk_clrsetreg(addr, mask << shift, muxval << shift); +} + +static void rk3399_pinctrl_set_pin_pupd(uintptr_t grf_addr, + struct rockchip_pin_bank *bank, + u32 index, int pinconfig) +{ + uintptr_t pupd_base, addr; + u32 shift, mask, pupdval; + + /* Fast path in case there's nothing to do. */ + if (!pinconfig) + return; + + if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_UP)) + pupdval = RK_GRF_P_PULLUP; + else if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) + pupdval = RK_GRF_P_PULLDOWN; + else + /* Flag not supported. */ + pr_warn("%s: Unsupported pinconfig flag: 0x%x\n", __func__, + pinconfig); + return; + + pupd_base = grf_addr + (uintptr_t)bank->pupd_offset; + rk_pinctrl_get_info(pupd_base, index, &addr, &shift, &mask); + + /* Set pull-up/pull-down regisrer */ + rk_clrsetreg(addr, mask << shift, pupdval << shift); +} + +static int rk3399_pinctrl_set_pin(struct udevice *dev, u32 banknum, u32 index, + u32 muxval, int pinconfig) +{ + struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); + struct rockchip_pin_bank *bank = &priv->banks[banknum]; + uintptr_t grf_addr; + + pr_debug("%s: 0x%x 0x%x 0x%x 0x%x\n", __func__, banknum, index, muxval, + pinconfig); + + if (bank->grf_location == RK_GRF) + grf_addr = (uintptr_t)priv->grf; + else if (bank->grf_location == RK_PMUGRF) + grf_addr = (uintptr_t)priv->pmugrf; + else + return -EINVAL; + + rk3399_pinctrl_set_pin_iomux(grf_addr, bank, index, muxval); + + rk3399_pinctrl_set_pin_pupd(grf_addr, bank, index, pinconfig); + return 0; +} + +static int rk3399_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + /* + * The order of the fields in this struct must match the order of + * the fields in the "rockchip,pins" property. + */ + struct rk_pin { + u32 banknum; + u32 index; + u32 muxval; + u32 phandle; + } __packed; + + u32 *fields = NULL; + const int fields_per_pin = 4; + int num_fields, num_pins; + int ret; + int size; + int i; + struct rk_pin *pin; + + pr_debug("%s: %s\n", __func__, config->name); + + size = dev_read_size(config, "rockchip,pins"); + if (size < 0) + return -EINVAL; + + num_fields = size / sizeof(u32); + num_pins = num_fields / fields_per_pin; + + if (num_fields * sizeof(u32) != size || + num_pins * fields_per_pin != num_fields) { + pr_warn("Invalid number of rockchip,pins fields.\n"); + return -EINVAL; + } + + fields = calloc(num_fields, sizeof(u32)); + if (!fields) + return -ENOMEM; + + ret = dev_read_u32_array(config, "rockchip,pins", fields, num_fields); + if (ret) { + pr_warn("%s: Failed to read rockchip,pins fields.\n", + config->name); + goto end; + } + + pin = (struct rk_pin *)fields; + for (i = 0; i < num_pins; i++, pin++) { + struct udevice *dev_pinconfig; + int pinconfig; + + ret = uclass_get_device_by_phandle_id(UCLASS_PINCONFIG, + pin->phandle, + &dev_pinconfig); + if (ret) { + pr_debug("Could not get pinconfig device\n"); + goto end; + } + + pinconfig = pinctrl_decode_pin_config_dm(dev_pinconfig); + if (pinconfig < 0) { + pr_warn("Could not parse pinconfig\n"); + goto end; + } + + ret = rk3399_pinctrl_set_pin(dev, pin->banknum, pin->index, + pin->muxval, pinconfig); + if (ret) { + pr_warn("Could not set pinctrl settings\n"); + goto end; + } + } + +end: + free(fields); + return ret; +} + static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf, struct rk3399_pmugrf_regs *pmugrf, int pwm_id) { @@ -468,6 +693,7 @@ static int rk3399_pinctrl_set_state_simple(struct udevice *dev, } static struct pinctrl_ops rk3399_pinctrl_ops = { + .set_state = rk3399_pinctrl_set_state, .set_state_simple = rk3399_pinctrl_set_state_simple, .request = rk3399_pinctrl_request, .get_periph_id = rk3399_pinctrl_get_periph_id, @@ -481,6 +707,7 @@ static int rk3399_pinctrl_probe(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf); + priv->banks = rk3399_pin_banks; return ret; } -- cgit v1.3.1 From 8188c83cfa2919a2a8e1d4d1d0daebdad6a1bc99 Mon Sep 17 00:00:00 2001 From: Christoph Muellner Date: Wed, 2 Jan 2019 15:09:20 +0100 Subject: rockchip: rk3399: Add Kconfig option for full pinctrl driver This patch adds a Kconfig option to enable the full pinctrl driver for the RK3399. This flag needs to be enabed in order to get the features of the full pinctrl driver compiled in (i.e. a .set_state() callback). Signed-off-by: Christoph Muellner Reviewed-by: Philipp Tomsich --- drivers/pinctrl/Kconfig | 10 ++++++++++ drivers/pinctrl/rockchip/pinctrl_rk3399.c | 9 +++++++++ 2 files changed, 19 insertions(+) (limited to 'drivers') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 1dbe2b104b2..30a6aa6ee8e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -238,6 +238,16 @@ config PINCTRL_ROCKCHIP_RK3399 the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_ROCKCHIP_RK3399_FULL + bool "Rockchip rk3399 pin control driver (full)" + depends on PINCTRL_FULL && PINCTRL_ROCKCHIP_RK3399 + help + Support full pin multiplexing control on Rockchip rk3399 SoCs. + + This enables the full pinctrl driver for the RK3399. + Contrary to the non-full pinctrl driver, this will evaluate + the board DTB to get the pinctrl settings. + config PINCTRL_ROCKCHIP_RV1108 bool "Rockchip rv1108 pin control driver" depends on DM diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index a1d5e8d0d52..c4746b0122d 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -15,8 +15,10 @@ #include #include +#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) static const u32 RK_GRF_P_PULLUP = 1; static const u32 RK_GRF_P_PULLDOWN = 2; +#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */ struct rk3399_pinctrl_priv { struct rk3399_grf_regs *grf; @@ -24,6 +26,7 @@ struct rk3399_pinctrl_priv { struct rockchip_pin_bank *banks; }; +#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) /* Location of pinctrl/pinconf registers. */ enum rk_grf_location { RK_GRF, @@ -244,6 +247,8 @@ end: return ret; } +#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */ + static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf, struct rk3399_pmugrf_regs *pmugrf, int pwm_id) { @@ -693,7 +698,9 @@ static int rk3399_pinctrl_set_state_simple(struct udevice *dev, } static struct pinctrl_ops rk3399_pinctrl_ops = { +#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) .set_state = rk3399_pinctrl_set_state, +#endif .set_state_simple = rk3399_pinctrl_set_state_simple, .request = rk3399_pinctrl_request, .get_periph_id = rk3399_pinctrl_get_periph_id, @@ -707,7 +714,9 @@ static int rk3399_pinctrl_probe(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf); +#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) priv->banks = rk3399_pin_banks; +#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */ return ret; } -- cgit v1.3.1