From 774ec60b74a7b8d356a2ec6249936b097631a726 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 11 Dec 2018 11:34:45 +0000 Subject: Enable FEC driver to retrieve PHY address from device tree Currently if we have more than one phy on the MDIO bus, we do not have a good mechanism for determining which should be used at runtime. Enable the FEC driver to determine the address for the PHY from the device tree. Signed-off-by: Martyn Welch Reviewed-by: Lukasz Majewski --- drivers/net/fec_mxc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers') diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 32fb34b7932..1a59026a62f 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1264,11 +1264,32 @@ static const struct eth_ops fecmxc_ops = { .read_rom_hwaddr = fecmxc_read_rom_hwaddr, }; +static int device_get_phy_addr(struct udevice *dev) +{ + struct ofnode_phandle_args phandle_args; + int reg; + + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phandle_args)) { + debug("Failed to find phy-handle"); + return -ENODEV; + } + + reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); + + return reg; +} + static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) { struct phy_device *phydev; + int addr; int mask = 0xffffffff; + addr = device_get_phy_addr(dev); + if (addr >= 0) + mask = 1 << addr; + #ifdef CONFIG_FEC_MXC_PHYADDR mask = 1 << CONFIG_FEC_MXC_PHYADDR; #endif -- cgit v1.2.3 From 04b249656ebf311080a8efbbc0022acb38beca13 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 21 Dec 2018 06:21:15 +0000 Subject: imx8: scu: use dedicated MU for SPL SPL runs in EL3 mode, except MU0_A, others are not powered on, and could not be used. However normal U-Boot use MU1_A, so we could not reuse the one in dts. And we could not replace the one in dts with MU0_A, because MU0_A is reserved in secure world. Signed-off-by: Peng Fan --- drivers/misc/imx8/scu.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c index 15101b3e5f2..1b9c49c99c9 100644 --- a/drivers/misc/imx8/scu.c +++ b/drivers/misc/imx8/scu.c @@ -191,7 +191,11 @@ static int imx8_scu_probe(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; +#ifdef CONFIG_SPL_BUILD + plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL; +#else plat->base = (struct mu_type *)addr; +#endif /* U-Boot not enable interrupts, so need to enable RX interrupts */ mu_hal_init(plat->base); -- cgit v1.2.3 From 16103682348c59536a3117e3d7014b8ab327db86 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 21 Dec 2018 06:21:21 +0000 Subject: gpio: introduce CONFIG_SPL_DM_PCA953X Introduce CONFIG_SPL_DM_PCA953X for SPL usage. Signed-off-by: Peng Fan --- drivers/gpio/Kconfig | 23 +++++++++++++++++++++++ drivers/gpio/Makefile | 2 +- 2 files changed, 24 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 14a14be9177..b103180cf37 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -303,6 +303,29 @@ config DM_PCA953X Now, max 24 bits chips and PCA953X compatible chips are supported +config SPL_DM_PCA953X + bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports in SPL" + depends on DM_GPIO + help + Say yes here to provide access to several register-oriented + SMBus I/O expanders, made mostly by NXP or TI. Compatible + models include: + + 4 bits: pca9536, pca9537 + + 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554, + pca9556, pca9557, pca9574, tca6408, xra1202 + + 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575, + tca6416 + + 24 bits: tca6424 + + 40 bits: pca9505, pca9698 + + Now, max 24 bits chips and PCA953X compatible chips are + supported + config MPC8XXX_GPIO bool "Freescale MPC8XXX GPIO driver" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 7c479efe2d6..3be325044f9 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_AXP_GPIO) += axp_gpio.o endif obj-$(CONFIG_DM_GPIO) += gpio-uclass.o -obj-$(CONFIG_DM_PCA953X) += pca953x_gpio.o +obj-$(CONFIG_$(SPL_)DM_PCA953X) += pca953x_gpio.o obj-$(CONFIG_DM_74X164) += 74x164_gpio.o obj-$(CONFIG_AT91_GPIO) += at91_gpio.o -- cgit v1.2.3 From 11a1c27eb454ece04ca4e61f0ea1ab4ebaafa5b5 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 4 Jan 2019 09:08:26 +0000 Subject: pinctrl: imx: Fix select input issue The pinctrl supports to set any bit in input register on iMX6 if the MSB of input value is 0xff. But the driver uses signed int for input value, so when executing the codes below, it won't meet. Because this is arithmetic right shift. if (input_val >> 24 == 0xff) Fix the issue by changing the input_val, config_val and mux_mode to u32. Signed-off-by: Ye Li Reviewed-by: Fugang Duan Reviewed-by: Peng Fan --- drivers/pinctrl/nxp/pinctrl-imx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index 04ea82aba5b..0c9d15cb0c9 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -22,7 +22,8 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) const struct fdt_property *prop; u32 *pin_data; int npins, size, pin_size; - int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val; + int mux_reg, conf_reg, input_reg; + u32 input_val, mux_mode, config_val; u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0; int i, j = 0; -- cgit v1.2.3 From 65a106e36fdd307a241bec9f0af1564889f10830 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 4 Jan 2019 09:26:00 +0000 Subject: spi: mxc_spi: Fix build warning on ARM64 platforms MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When building mxc_spi driver on ARM64 platforms, get below build warnings. Fix it in this patch. In file included from include/common.h:48:0, from drivers/spi/mxc_spi.c:9: drivers/spi/mxc_spi.c: In function ‘spi_xchg_single’: drivers/spi/mxc_spi.c:232:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] _func_, bitlen, (u32)dout, (u32)din); ^ include/log.h:135:26: note: in definition of macro ‘debug_cond’ printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’ debug("%s: bitlen %d dout 0x%x din 0x%x\n", ^~~~~ drivers/spi/mxc_spi.c:232:32: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] _func_, bitlen, (u32)dout, (u32)din); ^ include/log.h:135:26: note: in definition of macro ‘debug_cond’ printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’ debug("%s: bitlen %d dout 0x%x din 0x%x\n", ^~~~~ Signed-off-by: Ye Li Reviewed-by: Peng Fan --- drivers/spi/mxc_spi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index b2636909ce6..68467627199 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -224,8 +224,8 @@ int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen, u32 ts; int status; - debug("%s: bitlen %d dout 0x%x din 0x%x\n", - __func__, bitlen, (u32)dout, (u32)din); + debug("%s: bitlen %d dout 0x%lx din 0x%lx\n", + __func__, bitlen, (ulong)dout, (ulong)din); mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | -- cgit v1.2.3 From 96d0be07e7498e7174daa6f3b56fc807b9feb71d Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 30 Dec 2018 10:11:16 -0600 Subject: MTD: nand: mxs_nand_spl: Fix empty function pointer for BBT The initialization function calls a nand_chip.scan_bbt(mtd) but scan_bbt is never initialized resulting in an undefined function pointer. This will direct the function pointer to nand_default_bbt defined in the same file. Signed-off-by: Adam Ford Acked-by: Stefan Agner --- drivers/mtd/nand/raw/mxs_nand_spl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 2d7bbe83cce..c628f3adec0 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -185,6 +185,7 @@ static int mxs_nand_init(void) mtd = nand_to_mtd(&nand_chip); /* set mtd functions */ nand_chip.cmdfunc = mxs_nand_command; + nand_chip.scan_bbt = nand_default_bbt; nand_chip.numchips = 1; /* identify flash device */ -- cgit v1.2.3 From 791c88da31387d6bcc3f6aba08bbc4983c4ff4b5 Mon Sep 17 00:00:00 2001 From: Patrick Bruenn Date: Thu, 3 Jan 2019 07:54:32 +0100 Subject: mmc: fsl_esdhc: add compatible for fsl, imx53-esdhc Add compatible "fsl,imx53-esdhc" to keep mmc working on i.MX53 platforms with CONFIG_DM_MMC=y Signed-off-by: Patrick Bruenn --- drivers/mmc/fsl_esdhc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 84637313e0a..2fa61c4259b 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1584,6 +1584,7 @@ static struct esdhc_soc_data usdhc_imx7d_data = { }; static const struct udevice_id fsl_esdhc_ids[] = { + { .compatible = "fsl,imx53-esdhc", }, { .compatible = "fsl,imx6ul-usdhc", }, { .compatible = "fsl,imx6sx-usdhc", }, { .compatible = "fsl,imx6sl-usdhc", }, -- cgit v1.2.3