From 7d4541cdfbf9697c39e720690f13b9c02d3c7555 Mon Sep 17 00:00:00 2001 From: Haolin Li Date: Sun, 18 Jul 2021 10:13:39 +0800 Subject: mtd: nand: Fix typo in MXC Kconfig symbol description Trivial typo fix. Signed-off-by: Haolin Li Reviewed-by: Michal Simek --- drivers/mtd/nand/raw/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 790ee344038..d4da639dd13 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -369,7 +369,7 @@ config NAND_MXC imply CMD_NAND help This enables the NAND driver for the NAND flash controller on the - i.MX27 / i.MX31 / i.MX5 rocessors. + i.MX27 / i.MX31 / i.MX5 processors. config NAND_MXS bool "MXS NAND support" -- cgit v1.2.3 From 9b7c3495500c31b4acf416c9f866947feab3e230 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 17 Aug 2021 17:09:20 +0800 Subject: mmc: fsl_esdhc_imx: Fix clock disable issue The SD clock disable is wrapped by MMC_SUPPORTS_TUNING. So it only works when UHS is enabled. However, in SD initialization the power cycle does not depends on UHS. But the power cycle needs disable the SD clock before power down. So this causes a problem when UHS is not enabled. Some cards can't become ready (ACMD14 timeout) due to the clock is enabled during power cycle. Signed-off-by: Ye Li Reviewed-by: Haibo Chen Reviewed-by: Jaehoon Chung --- drivers/mmc/fsl_esdhc_imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 5dfd484ef9a..7c8d82afead 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -971,7 +971,6 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) if (priv->clock != clock) set_sysctl(priv, mmc, clock); -#ifdef MMC_SUPPORTS_TUNING if (mmc->clk_disable) { #ifdef CONFIG_FSL_USDHC esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); @@ -987,6 +986,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #endif } +#ifdef MMC_SUPPORTS_TUNING /* * For HS400/HS400ES mode, make sure set the strobe dll in the * target clock rate. So call esdhc_set_strobe_dll() after the -- cgit v1.2.3 From f68c897e2deacbf7870f3ba618d8d46efb44c149 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 17 Aug 2021 17:24:47 +0800 Subject: mtd: nand: mxs_nand_spl: Add nand_spl_adjust_offset Since the mxs_nand_spl has implemented adjust read offset in nand_spl_load_image, so we don't need to check the bad block in nand_spl_adjust_offset. Directly return the offset to continue read by nand_spl_load_image. Signed-off-by: Ye Li --- drivers/mtd/nand/raw/mxs_nand_spl.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 6b70d68fe7b..9e0b8afb522 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -296,3 +296,9 @@ int nand_default_bbt(struct mtd_info *mtd) void nand_deselect(void) { } + +u32 nand_spl_adjust_offset(u32 sector, u32 offs) +{ + /* Handle the offset adjust in nand_spl_load_image,*/ + return offs; +} -- cgit v1.2.3 From e1918ce299a10797df0f0f8e3df992fd6ed89aa6 Mon Sep 17 00:00:00 2001 From: Heiko Thiery Date: Thu, 23 Sep 2021 11:14:32 +0200 Subject: rtc: rv8803: add epson,rx8803 and epson,rx8900 compatible The RX8803 and RX8900 register layouts are compatible with the one of the RV8803. So add these to the compatibles. The same compatible strings are used and approved in linux kernel. Signed-off-by: Heiko Thiery Reviewed-by: Michael Walle --- drivers/rtc/rv8803.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/rtc/rv8803.c b/drivers/rtc/rv8803.c index acd50c65648..5bae39d6e09 100644 --- a/drivers/rtc/rv8803.c +++ b/drivers/rtc/rv8803.c @@ -157,6 +157,8 @@ static const struct rtc_ops rv8803_rtc_ops = { static const struct udevice_id rv8803_rtc_ids[] = { { .compatible = "microcrystal,rv8803", }, + { .compatible = "epson,rx8803" }, + { .compatible = "epson,rx8900" }, { } }; -- cgit v1.2.3 From 33e9a6956058663c6b92ed39b0464d1693cc963a Mon Sep 17 00:00:00 2001 From: Michael Scott Date: Sat, 25 Sep 2021 19:49:28 +0300 Subject: misc: ocotp: Allow disabling ocotp driver in SPL This allows removal of the OCOTP driver when SPL is enabled. Disabling OCOTP reduces SPL size efficiently. Signed-off-by: Michael Scott Co-developed-by: Oleksandr Suvorov Signed-off-by: Oleksandr Suvorov Reviewed-by: Peng Fan --- drivers/misc/Kconfig | 9 +++++++++ drivers/misc/Makefile | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 099ff293489..3bae0720058 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -233,6 +233,15 @@ config MXC_OCOTP Programmable memory pages that are stored on the some Freescale i.MX processors. +config SPL_MXC_OCOTP + bool "Enable MXC OCOTP driver in SPL" + depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) + default y + help + If you say Y here, you will get support for the One Time + Programmable memory pages, that are stored on some + Freescale i.MX processors, in SPL. + config NUVOTON_NCT6102D bool "Enable Nuvoton NCT6102D Super I/O driver" help diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index c16a77c34c4..f9826d2462d 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -50,7 +50,7 @@ obj-$(CONFIG_IMX8ULP) += imx8ulp/ obj-$(CONFIG_LED_STATUS) += status_led.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o -obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o +obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o obj-$(CONFIG_P2SB) += p2sb-uclass.o -- cgit v1.2.3 From c1412cbb17b2f6cd6c2301d7102346bec3a260d6 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Wed, 8 Sep 2021 21:56:42 +0300 Subject: mmc: fsl_esdhc_imx: initialize data for imx7ulp Import data for eSDHC driver for SoC iMX7ULP from the Linux kernel. Set supported by u-boot flags only. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Ricardo Salveti Co-developed-by: Oleksandr Suvorov Signed-off-by: Oleksandr Suvorov Reviewed-by: Fabio Estevam Reviewed-by: Jaehoon Chung Reviewed-by: Igor Opaniuk --- drivers/mmc/fsl_esdhc_imx.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 7c8d82afead..2ee53c71061 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1707,6 +1707,11 @@ static struct esdhc_soc_data usdhc_imx7d_data = { | ESDHC_FLAG_HS400, }; +static struct esdhc_soc_data usdhc_imx7ulp_data = { + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, +}; + static struct esdhc_soc_data usdhc_imx8qm_data = { .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 | @@ -1721,7 +1726,7 @@ static const struct udevice_id fsl_esdhc_ids[] = { { .compatible = "fsl,imx6sl-usdhc", }, { .compatible = "fsl,imx6q-usdhc", }, { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,}, - { .compatible = "fsl,imx7ulp-usdhc", }, + { .compatible = "fsl,imx7ulp-usdhc", .data = (ulong)&usdhc_imx7ulp_data,}, { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, -- cgit v1.2.3 From fa0223a75946ad3aec2596dac34d88f2dcca7baa Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Wed, 8 Sep 2021 21:56:43 +0300 Subject: mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP Import HS400 support for iMX7ULP B0 from the Linux kernel: 2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP") According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET before any setting of STROBE_DLL_CTRL register. USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL) for slave sel value. If this register bits value is 0, it needs 256 ref_clk cycles to update slave sel value. IC suggest to set bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave sel value. This will short the lock time of slave. i.MX7ULP B0 will need more time to lock the REF and SLV, so change to add 5us delay. Signed-off-by: Oleksandr Suvorov Reviewed-by: Fabio Estevam Reviewed-by: Jaehoon Chung Reviewed-by: Igor Opaniuk --- drivers/mmc/fsl_esdhc_imx.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 2ee53c71061..4c06361beef 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -727,17 +727,20 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET); + /* clear the reset bit on strobe dll before any setting */ + esdhc_write32(®s->strobe_dllctrl, 0); /* * enable strobe dll ctrl and adjust the delay target * for the uSDHC loopback read clock */ val = ESDHC_STROBE_DLL_CTRL_ENABLE | + ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | (priv->strobe_dll_delay_target << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); esdhc_write32(®s->strobe_dllctrl, val); - /* wait 1us to make sure strobe dll status register stable */ - mdelay(1); + /* wait 5us to make sure strobe dll status register stable */ + mdelay(5); val = esdhc_read32(®s->strobe_dllstat); if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK)) pr_warn("HS400 strobe DLL status REF not lock!\n"); @@ -1709,7 +1712,8 @@ static struct esdhc_soc_data usdhc_imx7d_data = { static struct esdhc_soc_data usdhc_imx7ulp_data = { .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING - | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 + | ESDHC_FLAG_HS400, }; static struct esdhc_soc_data usdhc_imx8qm_data = { -- cgit v1.2.3