From b4610c7177c5ea978837693be7b18779414e6212 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 9 Jun 2026 16:36:25 +0800 Subject: serial: lpuart: Use livetree API for fdt access Use livetree API, otherwise driver will fail to read properties from the device tree when OF_LIVE is enabled. Signed-off-by: Peng Fan --- drivers/serial/serial_lpuart.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 3f5fadfc80a..955f1c96407 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -519,8 +519,7 @@ static int lpuart_serial_probe(struct udevice *dev) static int lpuart_serial_of_to_plat(struct udevice *dev) { struct lpuart_serial_plat *plat = dev_get_plat(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); + ofnode node = dev_ofnode(dev); fdt_addr_t addr; addr = dev_read_addr(dev); @@ -530,18 +529,18 @@ static int lpuart_serial_of_to_plat(struct udevice *dev) plat->reg = (void *)addr; plat->flags = dev_get_driver_data(dev); - if (fdtdec_get_bool(blob, node, "little-endian")) + if (ofnode_read_bool(node, "little-endian")) plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG; - if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart")) + if (ofnode_device_is_compatible(node, "fsl,ls1021a-lpuart")) plat->devtype = DEV_LS1021A; - else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imx7ulp-lpuart")) plat->devtype = DEV_MX7ULP; - else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,vf610-lpuart")) plat->devtype = DEV_VF610; - else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imx8qm-lpuart")) plat->devtype = DEV_IMX8; - else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imxrt-lpuart")) plat->devtype = DEV_IMXRT; return 0; -- cgit v1.3.1 From 8db4311b4b2b918005cf2d2e67e58d31f44507cc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 9 Jun 2026 16:36:26 +0800 Subject: gpio: imx_rgpio2p: Use dev_read_addr_index Use dev_read_addr_index which supports livetree API, otherwise driver will fail to get addr when OF_LIVE is enabled. Signed-off-by: Peng Fan --- drivers/gpio/imx_rgpio2p.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c index 7cf178f8a48..ba3c5fcf25b 100644 --- a/drivers/gpio/imx_rgpio2p.c +++ b/drivers/gpio/imx_rgpio2p.c @@ -194,11 +194,11 @@ static int imx_rgpio2p_bind(struct udevice *dev) dual_base = true; if (dual_base) { - addr = devfdt_get_addr_index(dev, 1); + addr = dev_read_addr_index(dev, 1); if (addr == FDT_ADDR_T_NONE) return -EINVAL; } else { - addr = devfdt_get_addr_index(dev, 0); + addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) return -EINVAL; -- cgit v1.3.1 From 170291f04267269c1cbe88628d03b29feec4d6c0 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 9 Jun 2026 16:36:27 +0800 Subject: misc: ele: Use dev_read_addr Use dev_read_addr which supports livetree API, otherwise driver will fail to get addr when OF_LIVE is enabled. Signed-off-by: Peng Fan --- drivers/misc/imx_ele/ele_mu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index cdb85b999db..65a4779c041 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -209,7 +209,7 @@ static int imx8ulp_mu_probe(struct udevice *dev) debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); - addr = devfdt_get_addr(dev); + addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; -- cgit v1.3.1 From 450d9eaf5e64663674f21efec82f2c1dc6cac6d5 Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:34 +0300 Subject: clk: imx6q: cosmetic: keep pll definitions together Make it easier to reason about by keeping similar clocks grouped together. While at it, fix comment spacing. Signed-off-by: Brian Ruley --- drivers/clk/imx/clk-imx6q.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index f57ac79f8ca..cd06d211e8d 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -126,18 +126,19 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_PLL3_USB_OTG, imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3)); + clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", + base + 0xa0, 0x7f)); + clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", + "osc", base + 0xe0, 0x3)); + clk_dm(IMX6QDL_CLK_PLL3_60M, imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); clk_dm(IMX6QDL_CLK_PLL3_80M, imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); clk_dm(IMX6QDL_CLK_PLL3_120M, imx_clk_fixed_factor(dev, "pll3_120m", "pll3_usb_otg", 1, 4)); - clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", - base + 0xa0, 0x7f)); clk_dm(IMX6QDL_CLK_PLL5_VIDEO, imx_clk_gate(dev, "pll5_video", "pll5", base + 0xa0, 13)); - clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", - "osc", base + 0xe0, 0x3)); clk_dm(IMX6QDL_CLK_PLL6_ENET, imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); @@ -279,9 +280,9 @@ static int imx6q_clk_probe(struct udevice *dev) ldb_di_sels, ARRAY_SIZE(ldb_di_sels))); } else { /* - * Need to set these as read-only due to a hardware bug. - * Keeping default mux values. Fixed on the i.MX6 QuadPlus - */ + * Need to set these as read-only due to a hardware bug. + * Keeping default mux values. Fixed on the i.MX6 QuadPlus + */ clk_dm(IMX6QDL_CLK_LDB_DI0_SEL, imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), -- cgit v1.3.1 From d6331d465d8ae6091a737d5df15ec3c76ee85c5f Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:35 +0300 Subject: clk: imx6q: guard video clocks behind config Do not touch the video clocks unless explicitly required by the configuration. This avoids the issue of the binary size increase on SPL builds that do not enable video. For those that do, they should increase the size limit to fit the new code and data. Signed-off-by: Brian Ruley --- drivers/clk/imx/clk-imx6q.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index cd06d211e8d..67c0261091d 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -72,6 +72,8 @@ static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; + +#if CONFIG_IS_ENABLED(VIDEO) static const char *const ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", @@ -112,6 +114,7 @@ static const char *ipu2_di1_sels_2[] = { }; static unsigned int share_count_mipi_core_cfg; +#endif /* CONFIG_IS_ENABLED(VIDEO) */ static int imx6q_clk_probe(struct udevice *dev) { @@ -264,6 +267,7 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22)); +#if CONFIG_IS_ENABLED(VIDEO) clk_dm(IMX6QDL_CLK_IPU1_SEL, imx_clk_mux(dev, "ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels))); @@ -414,6 +418,7 @@ static int imx6q_clk_probe(struct udevice *dev) ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT)); } +#endif /* CONFIG_IS_ENABLED(VIDEO) */ clk_dm(IMX6QDL_CLK_ECSPI1, imx_clk_gate2(dev, "ecspi1", "ecspi_root", base + 0x6c, 0)); @@ -454,6 +459,8 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1)); + +#if CONFIG_IS_ENABLED(VIDEO) clk_dm(IMX6QDL_CLK_MIPI_CORE_CFG, imx_clk_gate2_shared(dev, "mipi_core_cfg", "video_27m", base + 0x74, 16, @@ -481,6 +488,7 @@ static int imx6q_clk_probe(struct udevice *dev) SET_CLK_PARENT(IMX6QDL_CLK_IPU1_SEL, IMX6QDL_CLK_PLL3_PFD1_540M); } +#endif /* CONFIG_IS_ENABLED(VIDEO) */ return 0; } -- cgit v1.3.1 From 73394a3cdcea4e6670d7f34b79bbb54586a5b840 Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:36 +0300 Subject: clk: imx6q: add missing pll bypasses After reset, all PLLs are bypassed by default so unbypass them so that dependent clocks can function correctly. Signed-off-by: Brian Ruley --- drivers/clk/imx/clk-imx6q.c | 90 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 80 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 67c0261091d..9ee3109bf1d 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -46,6 +46,33 @@ static struct clk_ops imx6q_clk_ops = { .disable = ccf_clk_disable, }; +static const char *const pll_bypass_src_sels[] = { + "osc", + "lvds1_in", + "lvds2_in", + "dummy", +}; + +static const char *const pll2_bypass_sels[] = { + "pll2", + "pll2_bypass_src", +}; + +static const char *const pll3_bypass_sels[] = { + "pll3", + "pll3_bypass_src", +}; + +static const char *const pll5_bypass_sels[] = { + "pll5", + "pll5_bypass_src", +}; + +static const char *const pll6_bypass_sels[] = { + "pll6", + "pll6_bypass_src", +}; + static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", @@ -123,27 +150,70 @@ static int imx6q_clk_probe(struct udevice *dev) /* Anatop clocks */ base = (void *)ANATOP_BASE_ADDR; - clk_dm(IMX6QDL_CLK_PLL2, - imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc", - base + 0x30, 0x1)); - clk_dm(IMX6QDL_CLK_PLL3_USB_OTG, - imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", - base + 0x10, 0x3)); + clk_dm(IMX6QDL_PLL2_BYPASS_SRC, + imx_clk_mux(dev, "pll2_bypass_src", base + 0x30, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL3_BYPASS_SRC, + imx_clk_mux(dev, "pll3_bypass_src", base + 0x10, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL5_BYPASS_SRC, + imx_clk_mux(dev, "pll5_bypass_src", base + 0xa0, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL6_BYPASS_SRC, + imx_clk_mux(dev, "pll6_bypass_src", base + 0xe0, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + + clk_dm(IMX6QDL_CLK_PLL2, imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2", + "osc", base + 0x30, 0x1)); + clk_dm(IMX6QDL_CLK_PLL3, imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3", + "osc", base + 0x10, 0x3)); clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f)); clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3)); + clk_dm(IMX6QDL_PLL2_BYPASS, + imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1, + pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL3_BYPASS, + imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1, + pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL5_BYPASS, + imx_clk_mux_flags(dev, "pll5_bypass", base + 0xa0, 16, 1, + pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL6_BYPASS, + imx_clk_mux_flags(dev, "pll6_bypass", base + 0xe0, 16, 1, + pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), + CLK_SET_RATE_PARENT)); + + SET_CLK_PARENT(IMX6QDL_PLL2_BYPASS, IMX6QDL_CLK_PLL2); + SET_CLK_PARENT(IMX6QDL_PLL3_BYPASS, IMX6QDL_CLK_PLL3); + SET_CLK_PARENT(IMX6QDL_PLL5_BYPASS, IMX6QDL_CLK_PLL5); + SET_CLK_PARENT(IMX6QDL_PLL6_BYPASS, IMX6QDL_CLK_PLL6); + + clk_dm(IMX6QDL_CLK_PLL2_BUS, + imx_clk_gate(dev, "pll2_bus", "pll2_bypass", base + 0x30, 13)); + clk_dm(IMX6QDL_CLK_PLL3_USB_OTG, + imx_clk_gate(dev, "pll3_usb_otg", "pll3_bypass", base + 0x10, + 13)); + clk_dm(IMX6QDL_CLK_PLL5_VIDEO, + imx_clk_gate(dev, "pll5_video", "pll5_bypass", base + 0xa0, 13)); + clk_dm(IMX6QDL_CLK_PLL6_ENET, + imx_clk_gate(dev, "pll6_enet", "pll6_bypass", base + 0xe0, 13)); + clk_dm(IMX6QDL_CLK_PLL3_60M, imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); clk_dm(IMX6QDL_CLK_PLL3_80M, imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); clk_dm(IMX6QDL_CLK_PLL3_120M, imx_clk_fixed_factor(dev, "pll3_120m", "pll3_usb_otg", 1, 4)); - clk_dm(IMX6QDL_CLK_PLL5_VIDEO, - imx_clk_gate(dev, "pll5_video", "pll5", base + 0xa0, 13)); - clk_dm(IMX6QDL_CLK_PLL6_ENET, - imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); -- cgit v1.3.1 From db4aa4571882a8d42c3b2b8da9cf6099a8db8852 Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:38 +0300 Subject: clk: imx6q: configure ldb clock selectors A hardware bug prevents LDB clock selectors from being configured later on non-plus i.MX6QD variants, so let's set the desired configuration in the probe before we register them. We also have to make the necessary clock functions available in XPL builds. Signed-off-by: Brian Ruley --- drivers/clk/imx/clk-imx6q.c | 119 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 9ee3109bf1d..393b4215fe8 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "clk.h" @@ -141,6 +142,121 @@ static const char *ipu2_di1_sels_2[] = { }; static unsigned int share_count_mipi_core_cfg; + +static void of_assigned_ldb_sels(struct udevice *dev, int *ldb_di0_sel, + int *ldb_di1_sel) +{ + struct ofnode_phandle_args clk_args, parent_args; + ofnode node = dev_ofnode(dev); + int count, err; + + count = dev_count_phandle_with_args(dev, "assigned-clocks", + "#clock-cells", 0); + if (count <= 0) { + if (count == 0) + debug("%s: no assigned_clocks found\n", dev->name); + else + pr_err("%s: failed to get phandle count (%d)\n", + dev->name, count); + return; + } + + for (int i = 0; i < count; i++) { + err = dev_read_phandle_with_args(dev, "assigned-clocks", + "#clock-cells", 0, i, + &clk_args); + if (err == -ENOENT) + /* Skip empty handles */ + continue; + else if (err < 0) + return; + + if (!ofnode_equal(clk_args.node, node) || + clk_args.args[0] >= IMX6QDL_CLK_END) { + pr_err("%s: clock %d not in ccm\n", dev->name, i); + return; + } + + err = dev_read_phandle_with_args(dev, "assigned-clock-parents", + "#clock-cells", 0, i, + &parent_args); + if (err < 0) + return; + + if (!ofnode_equal(parent_args.node, node) || + parent_args.args[0] >= IMX6QDL_CLK_END) { + pr_err("%s: parent clock %d not in ccm\n", dev->name, + i); + return; + } + + if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI0_SEL) + *ldb_di0_sel = parent_args.args[0]; + else if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI1_SEL) + *ldb_di1_sel = parent_args.args[0]; + } +} + +static void imx6q_init_ldb_clks(struct udevice *dev) +{ + int ldb_di_sel[] = { IMX6QDL_CLK_END, IMX6QDL_CLK_END }; + enum ldb_di_clock ldb_di_clk[] = { MXC_MMDC_CH1_CLK, MXC_MMDC_CH1_CLK }; + + of_assigned_ldb_sels(dev, &ldb_di_sel[0], &ldb_di_sel[1]); + for (int i = 0; i < 2; i++) { + switch (ldb_di_sel[i]) { + case IMX6QDL_CLK_PLL5_VIDEO_DIV: + ldb_di_clk[i] = MXC_PLL5_CLK; + break; + case IMX6QDL_CLK_PLL2_PFD0_352M: + ldb_di_clk[i] = MXC_PLL2_PFD0_CLK; + break; + case IMX6QDL_CLK_PLL2_PFD2_396M: { + struct clk *clk, *parent; + + int err = clk_get_by_id(IMX6QDL_CLK_PERIPH_PRE, &clk); + + if (err) { + pr_err("%s: failed to get periph_pre clock " + "(%d)\n", + dev->name, err); + return; + } + + err = clk_get_by_id(IMX6QDL_CLK_PLL2_PFD2_396M, + &parent); + if (err) { + pr_err("%s: failed to get pll2_pfd2_396m clock" + " (%d)\n", + dev->name, err); + return; + } + + if (parent == clk) { + pr_err("%s: ldb_di%d_sel: couldn't disable " + "pll2_pfd2_396m clock\n", + dev->name, i); + return; + } + + ldb_di_clk[i] = MXC_PLL2_PFD2_CLK; + break; + } + case IMX6QDL_CLK_MMDC_CH1_AXI: + case IMX6QDL_CLK_END: + /* use the default clock */ + break; + case IMX6QDL_CLK_PLL3_USB_OTG: + ldb_di_clk[i] = MXC_PLL3_SW_CLK; + break; + default: + pr_err("%s: invalid LDB clock parent\n", dev->name); + return; + } + } + + select_ldb_di_clock_source(ldb_di_clk[0], ldb_di_clk[1]); +} #endif /* CONFIG_IS_ENABLED(VIDEO) */ static int imx6q_clk_probe(struct udevice *dev) @@ -356,7 +472,10 @@ static int imx6q_clk_probe(struct udevice *dev) /* * Need to set these as read-only due to a hardware bug. * Keeping default mux values. Fixed on the i.MX6 QuadPlus + * Need to set the clocks now and make them read-only due to a + * hardware bug. Fixed on the i.MX6 QuadPlus */ + imx6q_init_ldb_clks(dev); clk_dm(IMX6QDL_CLK_LDB_DI0_SEL, imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), -- cgit v1.3.1 From d8673fd3b5998ceb2ba3552a9d579c14566ffec7 Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:39 +0300 Subject: video: imx: ipuv3: enable ipu clk before writing registers in CCF Obviously, the clock has to be enabled if writing to it's registers. This was missed because the board I tested on had enabled the clocks in early init. Also, remove the completely useless "ipu_clk_enabled" struct member and use the accurate usecount / enabled_count instead. Signed-off-by: Brian Ruley --- drivers/video/imx/ipu.h | 1 - drivers/video/imx/ipu_common.c | 13 +++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/video/imx/ipu.h b/drivers/video/imx/ipu.h index ae40e20bc28..aecb6adffce 100644 --- a/drivers/video/imx/ipu.h +++ b/drivers/video/imx/ipu.h @@ -136,7 +136,6 @@ struct ipu_ctx { struct clk *ipu_clk; struct clk *ldb_clk; - unsigned char ipu_clk_enabled; struct clk *di_clk[2]; struct clk *pixel_clk[2]; diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index 8630374a055..d3b52605731 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -299,9 +299,9 @@ struct ipu_ctx *ipu_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) clk_set_parent(ctx->pixel_clk[0], ctx->ipu_clk); clk_set_parent(ctx->pixel_clk[1], ctx->ipu_clk); +#endif clk_enable(ctx->ipu_clk); -#endif for (int i = 0; i <= 1; i++) { ret = ipu_di_clk_init(ctx, i); @@ -384,10 +384,8 @@ int32_t ipu_init_channel(struct ipu_ctx *ctx, ipu_channel_t channel, debug("init channel = %d\n", IPU_CHAN_ID(channel)); - if (ctx->ipu_clk_enabled == 0) { - ctx->ipu_clk_enabled = 1; + if (!ipu_clk_enabled(ctx)) clk_enable(ipu_clk); - } if (*channel_init_mask & (1L << IPU_CHAN_ID(channel))) { printf("Warning: channel already initialized %d\n", @@ -543,7 +541,6 @@ void ipu_uninit_channel(struct ipu_ctx *ctx, ipu_channel_t channel) if (ipu_conf == 0) { clk_disable(ctx->ipu_clk); - ctx->ipu_clk_enabled = 0; } } @@ -1045,5 +1042,9 @@ ipu_color_space_t format_to_colorspace(u32 fmt) bool ipu_clk_enabled(struct ipu_ctx *ctx) { - return ctx->ipu_clk_enabled; +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + return clk_get_usecount(ctx->ipu_clk); +#else + return ctx->ipu_clk->enable_count; +#endif } -- cgit v1.3.1 From 3c9cb48b4757f631e30a6cba634d62be815ac066 Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:40 +0300 Subject: clk: clk-divider: add clk_register_divider_table() The existing clk_register_divider() only supports linear or power-of-two divider mappings. Some hardware (e.g. i.MX6 PLL5 post_div and video_div) uses non-linear register-value-to-divisor mappings that require a lookup table. Add clk_register_divider_table() which accepts a clk_div_table, and reimplement clk_register_divider() as a wrapper passing table=NULL. Signed-off-by: Brian Ruley --- drivers/clk/clk-divider.c | 16 +++++++++++++--- include/linux/clk-provider.h | 5 +++++ 2 files changed, 18 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index e692b9c2167..d30786a9e6c 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -228,20 +228,30 @@ static struct clk *_register_divider(struct udevice *dev, const char *name, return clk; } -struct clk *clk_register_divider(struct udevice *dev, const char *name, +struct clk *clk_register_divider_table(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, - u8 clk_divider_flags) + u8 clk_divider_flags, const struct clk_div_table *table) { struct clk *clk; clk = _register_divider(dev, name, parent_name, flags, reg, shift, - width, clk_divider_flags, NULL); + width, clk_divider_flags, table); if (IS_ERR(clk)) return ERR_CAST(clk); return clk; } +struct clk *clk_register_divider(struct udevice *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags) +{ + return clk_register_divider_table(dev, name, parent_name, flags, reg, + shift, width, clk_divider_flags, + NULL); +} + U_BOOT_DRIVER(ccf_clk_divider) = { .name = UBOOT_DM_CLK_CCF_DIVIDER, .id = UCLASS_CLK, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2d754fa4287..366f2d968a3 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -246,6 +246,11 @@ struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk *clk_register_divider_table(struct udevice *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table); + struct clk *clk_register_divider(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, -- cgit v1.3.1 From 40c9ef1e77aa991c79a7408547aa3a0a8a3a858b Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:41 +0300 Subject: clk: imx6q: use clk_divider_table instead of fixed factor for pll5 divs Now that non-linear clk divider tables are supported, replace the fixed factor implementation with the proper divider, which allows more fine control over clock rates. Signed-off-by: Brian Ruley --- drivers/clk/imx/clk-imx6q.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 393b4215fe8..846b8011f5c 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -101,6 +101,21 @@ static const char *const ecspi_sels[] = { "osc", }; +static const struct clk_div_table post_div_table[] = { + { .val = 2, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 0, .div = 4, }, + { /* sentinel */ } +}; + +static const struct clk_div_table video_div_table[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 1, }, + { .val = 3, .div = 4, }, + { /* sentinel */ } +}; + #if CONFIG_IS_ENABLED(VIDEO) static const char *const ipu_sels[] = { "mmdc_ch0_axi", @@ -341,10 +356,14 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_PLL2_198M, imx_clk_fixed_factor(dev, "pll2_198m", "pll2_pfd2_396m", 1, 2)); clk_dm(IMX6QDL_CLK_PLL5_POST_DIV, - imx_clk_fixed_factor(dev, "pll5_post_div", "pll5_video", 1, 1)); + clk_register_divider_table(dev, "pll5_post_div", "pll5_video", + CLK_SET_RATE_PARENT, base + 0xa0, 19, + 2, 0, post_div_table)); clk_dm(IMX6QDL_CLK_PLL5_VIDEO_DIV, - imx_clk_fixed_factor(dev, "pll5_video_div", "pll5_post_div", 1, - 1)); + clk_register_divider_table(dev, "pll5_video_div", + "pll5_post_div", CLK_SET_RATE_PARENT, + base + 0x170, 30, 2, 0, + video_div_table)); clk_dm(IMX6QDL_CLK_VIDEO_27M, imx_clk_fixed_factor(dev, "video_27m", "pll3_pfd1_540m", 1, 20)); -- cgit v1.3.1 From 00bba5a3587f1b18e8ed8aa67c5dcfca7917dc89 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 26 Jun 2026 19:11:52 +0800 Subject: misc: ele_api: Add V2X Get State API Add V2X Get State API to return V2X states for debug purpose Signed-off-by: Ye Li --- arch/arm/include/asm/mach-imx/ele_api.h | 8 ++++++++ drivers/misc/imx_ele/ele_api.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) (limited to 'drivers') diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 04e7f20a2a6..8d779d6ae1b 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -30,6 +30,7 @@ #define ELE_START_RNG (0xA3) #define ELE_CMD_DERIVE_KEY (0xA9) #define ELE_GENERATE_DEK_BLOB (0xAF) +#define ELE_V2X_GET_STATE_REQ (0xB2) #define ELE_ENABLE_PATCH_REQ (0xC3) #define ELE_RELEASE_RDC_REQ (0xC4) #define ELE_GET_FW_STATUS_REQ (0xC5) @@ -141,6 +142,12 @@ struct ele_get_info_data { u32 reserved[8]; }; +struct v2x_get_state { + u8 v2x_state; + u8 v2x_power_state; + u32 v2x_err_code; +}; + int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response); int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response); int ele_release_container(u32 *response); @@ -166,4 +173,5 @@ int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response); int ele_set_gmid(u32 *response); int ele_volt_change_start_req(void); int ele_volt_change_finish_req(void); +int ele_v2x_get_state(struct v2x_get_state *state, u32 *response); #endif diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 8ee0a7733ca..355fd86ed8c 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -795,6 +795,38 @@ int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_outp return ret; } +int ele_v2x_get_state(struct v2x_get_state *state, u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg = {}; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 1; + msg.command = ELE_V2X_GET_STATE_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + state->v2x_state = msg.data[1] & 0xFF; + state->v2x_power_state = (msg.data[1] & 0xFF00) >> 8; + state->v2x_err_code = msg.data[2]; + + return ret; +} + int ele_volt_change_start_req(void) { struct udevice *dev = gd->arch.ele_dev; -- cgit v1.3.1