From d5be43de93ff905c465e509d45a3164ef48d26e7 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 11 Jun 2007 19:02:10 -0500 Subject: drivers/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). This is a compatibility step that allows both the older form and the new form to co-exist for a while until the older can be removed entirely. All transformations are of the form: Before: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) After: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) Signed-off-by: Jon Loeliger --- drivers/bcm570x.c | 4 ++-- drivers/cfb_console.c | 4 ++-- drivers/cs8900.c | 2 +- drivers/dc2114x.c | 4 ++-- drivers/e1000.c | 4 ++-- drivers/eepro100.c | 8 ++++---- drivers/inca-ip_sw.c | 4 ++-- drivers/lan91c96.c | 2 +- drivers/macb.c | 8 +++++--- drivers/mpc8xx_pcmcia.c | 8 ++++---- drivers/nand/nand.c | 2 +- drivers/nand/nand_base.c | 2 +- drivers/nand/nand_bbt.c | 2 +- drivers/nand/nand_ecc.c | 2 +- drivers/nand/nand_ids.c | 2 +- drivers/nand/nand_util.c | 2 +- drivers/nand_legacy/nand_legacy.c | 2 +- drivers/natsemi.c | 4 ++-- drivers/netarm_eth.c | 2 +- drivers/ns8382x.c | 4 ++-- drivers/pcnet.c | 4 ++-- drivers/plb2800_eth.c | 4 ++-- drivers/pxa_pcmcia.c | 2 +- drivers/rpx_pcmcia.c | 6 +++--- drivers/rtl8019.c | 2 +- drivers/rtl8139.c | 2 +- drivers/rtl8169.c | 2 +- drivers/sk98lin/uboot_drv.c | 2 +- drivers/sym53c8xx.c | 2 +- drivers/ti_pci1410a.c | 2 +- drivers/tigon3.c | 2 +- drivers/tqm8xx_pcmcia.c | 6 +++--- drivers/tsec.c | 4 ++-- drivers/tsi108_eth.c | 2 +- drivers/tsi108_i2c.c | 2 +- 35 files changed, 59 insertions(+), 57 deletions(-) (limited to 'drivers') diff --git a/drivers/bcm570x.c b/drivers/bcm570x.c index 5f632a64692..5a3ec22df02 100644 --- a/drivers/bcm570x.c +++ b/drivers/bcm570x.c @@ -6,8 +6,8 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && (!defined(CONFIG_NET_MULTI)) && \ - defined(CONFIG_BCM570x) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ + && (!defined(CONFIG_NET_MULTI)) && defined(CONFIG_BCM570x) #ifdef CONFIG_BMW #include diff --git a/drivers/cfb_console.c b/drivers/cfb_console.c index 9727aebbcb2..d9568b5c794 100644 --- a/drivers/cfb_console.c +++ b/drivers/cfb_console.c @@ -180,7 +180,7 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #endif -#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) #include #include #endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ @@ -709,7 +709,7 @@ void video_puts (const char *s) /*****************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) #define FILL_8BIT_332RGB(r,g,b) { \ *fb = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6); \ diff --git a/drivers/cs8900.c b/drivers/cs8900.c index 082434ca289..b92519a68fa 100644 --- a/drivers/cs8900.c +++ b/drivers/cs8900.c @@ -43,7 +43,7 @@ #ifdef CONFIG_DRIVER_CS8900 -#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) #undef DEBUG diff --git a/drivers/dc2114x.c b/drivers/dc2114x.c index c43cd5ec2fe..844cc8df5d7 100644 --- a/drivers/dc2114x.c +++ b/drivers/dc2114x.c @@ -20,8 +20,8 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ - && defined(CONFIG_TULIP) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ + && defined(CONFIG_NET_MULTI) && defined(CONFIG_TULIP) #include #include diff --git a/drivers/e1000.c b/drivers/e1000.c index 927acbb2673..1ba766019df 100644 --- a/drivers/e1000.c +++ b/drivers/e1000.c @@ -44,8 +44,8 @@ tested on both gig copper and gig fiber boards #include "e1000.h" -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ - defined(CONFIG_E1000) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ + && defined(CONFIG_NET_MULTI) && defined(CONFIG_E1000) #define TOUT_LOOP 100000 diff --git a/drivers/eepro100.c b/drivers/eepro100.c index 04c17f69f6e..e37f69cacb9 100644 --- a/drivers/eepro100.c +++ b/drivers/eepro100.c @@ -30,8 +30,8 @@ #undef DEBUG -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ - defined(CONFIG_EEPRO100) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ + && defined(CONFIG_NET_MULTI) && defined(CONFIG_EEPRO100) /* Ethernet chip registers. */ @@ -272,7 +272,7 @@ static inline void OUTL (struct eth_device *dev, int command, u_long addr) *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command); } -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) static inline int INL (struct eth_device *dev, u_long addr) { return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase)); @@ -462,7 +462,7 @@ int eepro100_initialize (bd_t * bis) eth_register (dev); -#if defined (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) /* register mii command access routines */ miiphy_register(dev->name, eepro100_miiphy_read, eepro100_miiphy_write); diff --git a/drivers/inca-ip_sw.c b/drivers/inca-ip_sw.c index ab22b4d5385..0dff3a9ef01 100644 --- a/drivers/inca-ip_sw.c +++ b/drivers/inca-ip_sw.c @@ -26,8 +26,8 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ - && defined(CONFIG_INCA_IP_SWITCH) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ + && defined(CONFIG_NET_MULTI) && defined(CONFIG_INCA_IP_SWITCH) #include #include diff --git a/drivers/lan91c96.c b/drivers/lan91c96.c index a50c5f0abec..07c374f05c7 100644 --- a/drivers/lan91c96.c +++ b/drivers/lan91c96.c @@ -65,7 +65,7 @@ #ifdef CONFIG_DRIVER_LAN91C96 -#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) /*------------------------------------------------------------------------ * diff --git a/drivers/macb.c b/drivers/macb.c index 186ab19d35e..251a0292d5c 100644 --- a/drivers/macb.c +++ b/drivers/macb.c @@ -17,7 +17,9 @@ */ #include -#if defined(CONFIG_MACB) && (CONFIG_COMMANDS & (CFG_CMD_NET | CFG_CMD_MII)) +#if defined(CONFIG_MACB) \ + && ((CONFIG_COMMANDS & (CFG_CMD_NET | CFG_CMD_MII)) \ + || (defined(CONFIG_CMD_NET) || defined(CONFIG_CMD_MII))) /* * The u-boot networking stack is a little weird. It seems like the @@ -163,7 +165,7 @@ static u16 macb_mdio_read(struct macb_device *macb, u8 reg) return MACB_BFEXT(DATA, frame); } -#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) static int macb_send(struct eth_device *netdev, volatile void *packet, int length) @@ -494,7 +496,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) #endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */ -#if (CONFIG_COMMANDS & CFG_CMD_MII) +#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value) { diff --git a/drivers/mpc8xx_pcmcia.c b/drivers/mpc8xx_pcmcia.c index 399a719e565..2358900fd42 100644 --- a/drivers/mpc8xx_pcmcia.c +++ b/drivers/mpc8xx_pcmcia.c @@ -6,11 +6,11 @@ #undef CONFIG_PCMCIA -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -23,7 +23,7 @@ extern int check_ide_device (int slot); extern int pcmcia_hardware_enable (int slot); extern int pcmcia_voltage_set(int slot, int vcc, int vpp); -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) extern int pcmcia_hardware_disable(int slot); #endif @@ -189,7 +189,7 @@ int pcmcia_on (void) return rc; } -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) int pcmcia_off (void) { int i; diff --git a/drivers/nand/nand.c b/drivers/nand/nand.c index 9fef71d6293..104a4167fba 100644 --- a/drivers/nand/nand.c +++ b/drivers/nand/nand.c @@ -23,7 +23,7 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) +#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) #include diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c index c6fee18222b..2e53076af27 100644 --- a/drivers/nand/nand_base.c +++ b/drivers/nand/nand_base.c @@ -72,7 +72,7 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) +#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) #include #include diff --git a/drivers/nand/nand_bbt.c b/drivers/nand/nand_bbt.c index aaa9400e54d..13ea97e39a5 100644 --- a/drivers/nand/nand_bbt.c +++ b/drivers/nand/nand_bbt.c @@ -54,7 +54,7 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) +#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) #include #include diff --git a/drivers/nand/nand_ecc.c b/drivers/nand/nand_ecc.c index 90274e6d6dd..8b39e2a9746 100644 --- a/drivers/nand/nand_ecc.c +++ b/drivers/nand/nand_ecc.c @@ -37,7 +37,7 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) +#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) #include diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c index 8b58736bc10..5b944a58dc5 100644 --- a/drivers/nand/nand_ids.c +++ b/drivers/nand/nand_ids.c @@ -13,7 +13,7 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) +#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) #include diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c index 10bf03659ed..135e3c43ae8 100644 --- a/drivers/nand/nand_util.c +++ b/drivers/nand/nand_util.c @@ -32,7 +32,7 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) +#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) #include #include diff --git a/drivers/nand_legacy/nand_legacy.c b/drivers/nand_legacy/nand_legacy.c index 458046d41c3..18b4e459399 100644 --- a/drivers/nand_legacy/nand_legacy.c +++ b/drivers/nand_legacy/nand_legacy.c @@ -22,7 +22,7 @@ # define SHOW_BOOT_PROGRESS(arg) #endif -#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && defined(CFG_NAND_LEGACY) #include #include diff --git a/drivers/natsemi.c b/drivers/natsemi.c index b009db63ebe..6e0e73f6c5a 100644 --- a/drivers/natsemi.c +++ b/drivers/natsemi.c @@ -56,8 +56,8 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ - defined(CONFIG_NATSEMI) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ + && defined(CONFIG_NET_MULTI) && defined(CONFIG_NATSEMI) /* defines */ #define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/ diff --git a/drivers/netarm_eth.c b/drivers/netarm_eth.c index 89b3a8394ed..913e89b7912 100644 --- a/drivers/netarm_eth.c +++ b/drivers/netarm_eth.c @@ -30,7 +30,7 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) static int na_mii_poll_busy (void); diff --git a/drivers/ns8382x.c b/drivers/ns8382x.c index 976f86aaff5..69002cd5249 100644 --- a/drivers/ns8382x.c +++ b/drivers/ns8382x.c @@ -56,8 +56,8 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ - defined(CONFIG_NS8382X) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ + && defined(CONFIG_NET_MULTI) && defined(CONFIG_NS8382X) /* defines */ #define DSIZE 0x00000FFF diff --git a/drivers/pcnet.c b/drivers/pcnet.c index da9ac7f99af..24fc64223aa 100644 --- a/drivers/pcnet.c +++ b/drivers/pcnet.c @@ -45,8 +45,8 @@ #define PCNET_DEBUG2(fmt,args...) #endif -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ - && defined(CONFIG_PCNET) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ + && defined(CONFIG_NET_MULTI) && defined(CONFIG_PCNET) #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) #error "Macro for PCnet chip version is not defined!" diff --git a/drivers/plb2800_eth.c b/drivers/plb2800_eth.c index 4c683d7a5c4..770f31b655c 100644 --- a/drivers/plb2800_eth.c +++ b/drivers/plb2800_eth.c @@ -25,8 +25,8 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ - && defined(CONFIG_PLB2800_ETHER) +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ + && defined(CONFIG_NET_MULTI) && defined(CONFIG_PLB2800_ETHER) #include #include diff --git a/drivers/pxa_pcmcia.c b/drivers/pxa_pcmcia.c index d9d38bbfcd8..ecadd452d9c 100644 --- a/drivers/pxa_pcmcia.c +++ b/drivers/pxa_pcmcia.c @@ -85,7 +85,7 @@ int pcmcia_on (void) return rc; } -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) int pcmcia_off (void) { return 0; diff --git a/drivers/rpx_pcmcia.c b/drivers/rpx_pcmcia.c index 2a0a9e05a27..530525d05d0 100644 --- a/drivers/rpx_pcmcia.c +++ b/drivers/rpx_pcmcia.c @@ -9,11 +9,11 @@ #undef CONFIG_PCMCIA -#if CONFIG_COMMANDS & CFG_CMD_PCMCIA +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -62,7 +62,7 @@ int pcmcia_hardware_enable (int slot) return 0; /* No hardware to enable */ } -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) static int pcmcia_hardware_disable(int slot) { return 0; /* No hardware to disable */ diff --git a/drivers/rtl8019.c b/drivers/rtl8019.c index 62b9245517b..31462b30127 100644 --- a/drivers/rtl8019.c +++ b/drivers/rtl8019.c @@ -34,7 +34,7 @@ #ifdef CONFIG_DRIVER_RTL8019 -#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) /* packet page register access functions */ diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index afe1a4fdaf6..31ed855d7e2 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -77,7 +77,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_RTL8139) #define TICKS_PER_SEC CFG_HZ diff --git a/drivers/rtl8169.c b/drivers/rtl8169.c index 3393ba890ae..1810850f5bd 100644 --- a/drivers/rtl8169.c +++ b/drivers/rtl8169.c @@ -55,7 +55,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_RTL8169) #undef DEBUG_RTL8169 diff --git a/drivers/sk98lin/uboot_drv.c b/drivers/sk98lin/uboot_drv.c index 263dac81069..ff06ab38f96 100644 --- a/drivers/sk98lin/uboot_drv.c +++ b/drivers/sk98lin/uboot_drv.c @@ -25,7 +25,7 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_SK98) #include "h/skdrv1st.h" diff --git a/drivers/sym53c8xx.c b/drivers/sym53c8xx.c index ae10f80ecfb..f2c94ddaa5e 100644 --- a/drivers/sym53c8xx.c +++ b/drivers/sym53c8xx.c @@ -51,7 +51,7 @@ #define PRINTF(fmt,args...) #endif -#if (CONFIG_COMMANDS & CFG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX) +#if ((CONFIG_COMMANDS & CFG_CMD_SCSI) || defined(CONFIG_CMD_SCSI)) && defined(CONFIG_SCSI_SYM53C8XX) #undef SCSI_SINGLE_STEP /* diff --git a/drivers/ti_pci1410a.c b/drivers/ti_pci1410a.c index d5297b57213..d5808e5751e 100644 --- a/drivers/ti_pci1410a.c +++ b/drivers/ti_pci1410a.c @@ -64,7 +64,7 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && defined(CONFIG_IDE_TI_CARDBUS) +#if ((CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA)) && defined(CONFIG_IDE_TI_CARDBUS) int pcmcia_on(int ide_base_bus); diff --git a/drivers/tigon3.c b/drivers/tigon3.c index ec2cd2ac36f..a6a4989bd39 100644 --- a/drivers/tigon3.c +++ b/drivers/tigon3.c @@ -12,7 +12,7 @@ /******************************************************************************/ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_NET_MULTI) && \ +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && !defined(CONFIG_NET_MULTI) && \ defined(CONFIG_TIGON3) #ifdef CONFIG_BMW #include diff --git a/drivers/tqm8xx_pcmcia.c b/drivers/tqm8xx_pcmcia.c index a0f53cd6841..1dcefaa82b4 100644 --- a/drivers/tqm8xx_pcmcia.c +++ b/drivers/tqm8xx_pcmcia.c @@ -10,11 +10,11 @@ #undef CONFIG_PCMCIA -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -241,7 +241,7 @@ int pcmcia_hardware_enable(int slot) } -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { u_long reg; diff --git a/drivers/tsec.c b/drivers/tsec.c index 1298478704f..e717cd74884 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -176,7 +176,7 @@ int tsec_initialize(bd_t * bis, int index, char *devname) priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \ +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) \ && !defined(BITBANGMII) miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); #endif @@ -1443,7 +1443,7 @@ static void relocate_cmds(void) relocated = 1; } -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \ +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) \ && !defined(BITBANGMII) struct tsec_private *get_priv_for_phy(unsigned char phyaddr) diff --git a/drivers/tsi108_eth.c b/drivers/tsi108_eth.c index 47341bee7f1..a25728eac33 100644 --- a/drivers/tsi108_eth.c +++ b/drivers/tsi108_eth.c @@ -27,7 +27,7 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ +#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_NET_MULTI) \ && defined(CONFIG_TSI108_ETH) #if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2) diff --git a/drivers/tsi108_i2c.c b/drivers/tsi108_i2c.c index eb52cb66c96..2c90eed0d6f 100644 --- a/drivers/tsi108_i2c.c +++ b/drivers/tsi108_i2c.c @@ -28,7 +28,7 @@ #ifdef CONFIG_TSI108_I2C #include -#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) || defined(CONFIG_CMD_I2C) #define I2C_DELAY 100000 #undef DEBUG_I2C -- cgit v1.3.1 From 52b8704d0245e589f86d462e9ec25aeb7ecbbbdd Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 4 Jul 2007 00:43:53 +0200 Subject: Fix a few file permission problems. Signed-off-by: Wolfgang Denk --- board/siemens/SMN42/flash.c | 0 board/xilinx/ml401/xparameters.h | 0 cpu/microblaze/cache.c | 0 cpu/microblaze/interrupts.c | 0 cpu/microblaze/irq.S | 0 cpu/ppc4xx/traps.c | 0 drivers/enc28j60.c | 0 include/asm-microblaze/asm.h | 0 include/configs/SMN42.h | 0 include/configs/lpc2292sodimm.h | 0 10 files changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 board/siemens/SMN42/flash.c mode change 100755 => 100644 board/xilinx/ml401/xparameters.h mode change 100755 => 100644 cpu/microblaze/cache.c mode change 100755 => 100644 cpu/microblaze/interrupts.c mode change 100755 => 100644 cpu/microblaze/irq.S mode change 100755 => 100644 cpu/ppc4xx/traps.c mode change 100755 => 100644 drivers/enc28j60.c mode change 100755 => 100644 include/asm-microblaze/asm.h mode change 100755 => 100644 include/configs/SMN42.h mode change 100755 => 100644 include/configs/lpc2292sodimm.h (limited to 'drivers') diff --git a/board/siemens/SMN42/flash.c b/board/siemens/SMN42/flash.c old mode 100755 new mode 100644 diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h old mode 100755 new mode 100644 diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c old mode 100755 new mode 100644 diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c old mode 100755 new mode 100644 diff --git a/cpu/microblaze/irq.S b/cpu/microblaze/irq.S old mode 100755 new mode 100644 diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c old mode 100755 new mode 100644 diff --git a/drivers/enc28j60.c b/drivers/enc28j60.c old mode 100755 new mode 100644 diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h old mode 100755 new mode 100644 diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h old mode 100755 new mode 100644 diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h old mode 100755 new mode 100644 -- cgit v1.3.1 From 07d38a17e964aec4c7827f0ee9a583bc8cc1ad6b Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 17:30:01 -0500 Subject: drivers/[a-m]*: Remove obsolete references to CONFIG_COMMANDS Signed-off-by: Jon Loeliger --- drivers/bcm570x.c | 2 +- drivers/cfb_console.c | 8 ++++---- drivers/cs8900.c | 2 +- drivers/dc2114x.c | 2 +- drivers/e1000.c | 2 +- drivers/eepro100.c | 8 ++++---- drivers/inca-ip_sw.c | 2 +- drivers/lan91c96.c | 2 +- drivers/macb.c | 11 +++++------ drivers/mpc8xx_pcmcia.c | 8 ++++---- 10 files changed, 23 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/bcm570x.c b/drivers/bcm570x.c index 5a3ec22df02..b00bcd772fc 100644 --- a/drivers/bcm570x.c +++ b/drivers/bcm570x.c @@ -6,7 +6,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ +#if defined(CONFIG_CMD_NET) \ && (!defined(CONFIG_NET_MULTI)) && defined(CONFIG_BCM570x) #ifdef CONFIG_BMW diff --git a/drivers/cfb_console.c b/drivers/cfb_console.c index d9568b5c794..617361e405f 100644 --- a/drivers/cfb_console.c +++ b/drivers/cfb_console.c @@ -180,10 +180,10 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #endif -#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) #include #include -#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ +#endif /*****************************************************************************/ /* Cursor definition: */ @@ -709,7 +709,7 @@ void video_puts (const char *s) /*****************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) #define FILL_8BIT_332RGB(r,g,b) { \ *fb = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6); \ @@ -1004,7 +1004,7 @@ int video_display_bitmap (ulong bmp_image, int x, int y) return (0); } -#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ +#endif /*****************************************************************************/ diff --git a/drivers/cs8900.c b/drivers/cs8900.c index b92519a68fa..80c4ba21a68 100644 --- a/drivers/cs8900.c +++ b/drivers/cs8900.c @@ -43,7 +43,7 @@ #ifdef CONFIG_DRIVER_CS8900 -#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) #undef DEBUG diff --git a/drivers/dc2114x.c b/drivers/dc2114x.c index 844cc8df5d7..721bbfc2ff0 100644 --- a/drivers/dc2114x.c +++ b/drivers/dc2114x.c @@ -20,7 +20,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ +#if defined(CONFIG_CMD_NET) \ && defined(CONFIG_NET_MULTI) && defined(CONFIG_TULIP) #include diff --git a/drivers/e1000.c b/drivers/e1000.c index 1ba766019df..f0741da82b2 100644 --- a/drivers/e1000.c +++ b/drivers/e1000.c @@ -44,7 +44,7 @@ tested on both gig copper and gig fiber boards #include "e1000.h" -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ +#if defined(CONFIG_CMD_NET) \ && defined(CONFIG_NET_MULTI) && defined(CONFIG_E1000) #define TOUT_LOOP 100000 diff --git a/drivers/eepro100.c b/drivers/eepro100.c index e37f69cacb9..738146e6618 100644 --- a/drivers/eepro100.c +++ b/drivers/eepro100.c @@ -30,7 +30,7 @@ #undef DEBUG -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ +#if defined(CONFIG_CMD_NET) \ && defined(CONFIG_NET_MULTI) && defined(CONFIG_EEPRO100) /* Ethernet chip registers. @@ -272,7 +272,7 @@ static inline void OUTL (struct eth_device *dev, int command, u_long addr) *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command); } -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) static inline int INL (struct eth_device *dev, u_long addr) { return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase)); @@ -386,7 +386,7 @@ static int eepro100_miiphy_write (char *devname, unsigned char addr, return 0; } -#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */ +#endif /* Wait for the chip get the command. */ @@ -462,7 +462,7 @@ int eepro100_initialize (bd_t * bis) eth_register (dev); -#if defined (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined (CONFIG_MII) || defined(CONFIG_CMD_MII) /* register mii command access routines */ miiphy_register(dev->name, eepro100_miiphy_read, eepro100_miiphy_write); diff --git a/drivers/inca-ip_sw.c b/drivers/inca-ip_sw.c index 0dff3a9ef01..e4aaed6afbc 100644 --- a/drivers/inca-ip_sw.c +++ b/drivers/inca-ip_sw.c @@ -26,7 +26,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ +#if defined(CONFIG_CMD_NET) \ && defined(CONFIG_NET_MULTI) && defined(CONFIG_INCA_IP_SWITCH) #include diff --git a/drivers/lan91c96.c b/drivers/lan91c96.c index 07c374f05c7..ecdcbd9b32b 100644 --- a/drivers/lan91c96.c +++ b/drivers/lan91c96.c @@ -65,7 +65,7 @@ #ifdef CONFIG_DRIVER_LAN91C96 -#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) /*------------------------------------------------------------------------ * diff --git a/drivers/macb.c b/drivers/macb.c index 251a0292d5c..ffb5f74cc52 100644 --- a/drivers/macb.c +++ b/drivers/macb.c @@ -18,8 +18,7 @@ #include #if defined(CONFIG_MACB) \ - && ((CONFIG_COMMANDS & (CFG_CMD_NET | CFG_CMD_MII)) \ - || (defined(CONFIG_CMD_NET) || defined(CONFIG_CMD_MII))) + && (defined(CONFIG_CMD_NET) || defined(CONFIG_CMD_MII))) /* * The u-boot networking stack is a little weird. It seems like the @@ -165,7 +164,7 @@ static u16 macb_mdio_read(struct macb_device *macb, u8 reg) return MACB_BFEXT(DATA, frame); } -#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) static int macb_send(struct eth_device *netdev, volatile void *packet, int length) @@ -494,9 +493,9 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) return 0; } -#endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */ +#endif -#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_CMD_MII) int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value) { @@ -572,6 +571,6 @@ int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) return 0; } -#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */ +#endif #endif /* CONFIG_MACB */ diff --git a/drivers/mpc8xx_pcmcia.c b/drivers/mpc8xx_pcmcia.c index 2358900fd42..04c44a44bf3 100644 --- a/drivers/mpc8xx_pcmcia.c +++ b/drivers/mpc8xx_pcmcia.c @@ -6,11 +6,11 @@ #undef CONFIG_PCMCIA -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) +#if defined(CONFIG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD) +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -23,7 +23,7 @@ extern int check_ide_device (int slot); extern int pcmcia_hardware_enable (int slot); extern int pcmcia_voltage_set(int slot, int vcc, int vpp); -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) +#if defined(CONFIG_CMD_PCMCIA) extern int pcmcia_hardware_disable(int slot); #endif @@ -189,7 +189,7 @@ int pcmcia_on (void) return rc; } -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) +#if defined(CONFIG_CMD_PCMCIA) int pcmcia_off (void) { int i; -- cgit v1.3.1 From cb51c0bf88f95a1bca68324b0126f8eed8b43273 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 17:39:42 -0500 Subject: drivers/[n-z]*: Remove obsolete references to CONFIG_COMMANDS Signed-off-by: Jon Loeliger --- drivers/nand/nand.c | 2 +- drivers/nand/nand_base.c | 2 +- drivers/nand/nand_bbt.c | 2 +- drivers/nand/nand_ecc.c | 4 ++-- drivers/nand/nand_ids.c | 2 +- drivers/nand/nand_util.c | 4 ++-- drivers/nand_legacy/nand_legacy.c | 4 ++-- drivers/natsemi.c | 2 +- drivers/netarm_eth.c | 2 +- drivers/ns8382x.c | 2 +- drivers/pcnet.c | 2 +- drivers/plb2800_eth.c | 2 +- drivers/pxa_pcmcia.c | 2 +- drivers/rpx_pcmcia.c | 8 ++++---- drivers/rtl8019.c | 2 +- drivers/rtl8139.c | 2 +- drivers/rtl8169.c | 2 +- drivers/sk98lin/uboot_drv.c | 2 +- drivers/sym53c8xx.c | 4 ++-- drivers/ti_pci1410a.c | 2 +- drivers/tigon3.c | 2 +- drivers/tqm8xx_pcmcia.c | 6 +++--- drivers/tsec.c | 7 +++---- drivers/tsi108_eth.c | 2 +- drivers/tsi108_i2c.c | 4 ++-- 25 files changed, 37 insertions(+), 38 deletions(-) (limited to 'drivers') diff --git a/drivers/nand/nand.c b/drivers/nand/nand.c index 104a4167fba..27b5792bcc9 100644 --- a/drivers/nand/nand.c +++ b/drivers/nand/nand.c @@ -23,7 +23,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) #include diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c index 2e53076af27..151f535c58b 100644 --- a/drivers/nand/nand_base.c +++ b/drivers/nand/nand_base.c @@ -72,7 +72,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) #include #include diff --git a/drivers/nand/nand_bbt.c b/drivers/nand/nand_bbt.c index 13ea97e39a5..19a9bc2a5b6 100644 --- a/drivers/nand/nand_bbt.c +++ b/drivers/nand/nand_bbt.c @@ -54,7 +54,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) #include #include diff --git a/drivers/nand/nand_ecc.c b/drivers/nand/nand_ecc.c index 8b39e2a9746..4c532b0794e 100644 --- a/drivers/nand/nand_ecc.c +++ b/drivers/nand/nand_ecc.c @@ -37,7 +37,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) #include @@ -197,4 +197,4 @@ int nand_correct_data(struct mtd_info *mtd, u_char *dat, return -1; } -#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ +#endif diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c index 5b944a58dc5..075cae66b06 100644 --- a/drivers/nand/nand_ids.c +++ b/drivers/nand/nand_ids.c @@ -13,7 +13,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) #include diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c index 135e3c43ae8..88c1df6c20b 100644 --- a/drivers/nand/nand_util.c +++ b/drivers/nand/nand_util.c @@ -32,7 +32,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && !defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) #include #include @@ -859,4 +859,4 @@ int nand_unlock(nand_info_t *meminfo, ulong start, ulong length) return ret; } -#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) */ +#endif diff --git a/drivers/nand_legacy/nand_legacy.c b/drivers/nand_legacy/nand_legacy.c index 18b4e459399..fcb6d2b5334 100644 --- a/drivers/nand_legacy/nand_legacy.c +++ b/drivers/nand_legacy/nand_legacy.c @@ -22,7 +22,7 @@ # define SHOW_BOOT_PROGRESS(arg) #endif -#if ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) && defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) #include #include @@ -1616,4 +1616,4 @@ int read_jffs2_nand(size_t start, size_t len, } #endif /* CONFIG_JFFS2_NAND */ -#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) */ +#endif diff --git a/drivers/natsemi.c b/drivers/natsemi.c index 6e0e73f6c5a..075d6c52c45 100644 --- a/drivers/natsemi.c +++ b/drivers/natsemi.c @@ -56,7 +56,7 @@ #include #include -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ +#if defined(CONFIG_CMD_NET) \ && defined(CONFIG_NET_MULTI) && defined(CONFIG_NATSEMI) /* defines */ diff --git a/drivers/netarm_eth.c b/drivers/netarm_eth.c index 913e89b7912..a99ee5da2e3 100644 --- a/drivers/netarm_eth.c +++ b/drivers/netarm_eth.c @@ -30,7 +30,7 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) static int na_mii_poll_busy (void); diff --git a/drivers/ns8382x.c b/drivers/ns8382x.c index 69002cd5249..f8b143a01a6 100644 --- a/drivers/ns8382x.c +++ b/drivers/ns8382x.c @@ -56,7 +56,7 @@ #include #include -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ +#if defined(CONFIG_CMD_NET) \ && defined(CONFIG_NET_MULTI) && defined(CONFIG_NS8382X) /* defines */ diff --git a/drivers/pcnet.c b/drivers/pcnet.c index 24fc64223aa..2af0e8f244f 100644 --- a/drivers/pcnet.c +++ b/drivers/pcnet.c @@ -45,7 +45,7 @@ #define PCNET_DEBUG2(fmt,args...) #endif -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ +#if defined(CONFIG_CMD_NET) \ && defined(CONFIG_NET_MULTI) && defined(CONFIG_PCNET) #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) diff --git a/drivers/plb2800_eth.c b/drivers/plb2800_eth.c index 770f31b655c..0ae5d808a6f 100644 --- a/drivers/plb2800_eth.c +++ b/drivers/plb2800_eth.c @@ -25,7 +25,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) \ +#if defined(CONFIG_CMD_NET) \ && defined(CONFIG_NET_MULTI) && defined(CONFIG_PLB2800_ETHER) #include diff --git a/drivers/pxa_pcmcia.c b/drivers/pxa_pcmcia.c index ecadd452d9c..6020e46283a 100644 --- a/drivers/pxa_pcmcia.c +++ b/drivers/pxa_pcmcia.c @@ -85,7 +85,7 @@ int pcmcia_on (void) return rc; } -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) +#if defined(CONFIG_CMD_PCMCIA) int pcmcia_off (void) { return 0; diff --git a/drivers/rpx_pcmcia.c b/drivers/rpx_pcmcia.c index 530525d05d0..c7c425b93cf 100644 --- a/drivers/rpx_pcmcia.c +++ b/drivers/rpx_pcmcia.c @@ -9,11 +9,11 @@ #undef CONFIG_PCMCIA -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) +#if defined(CONFIG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD) +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -62,12 +62,12 @@ int pcmcia_hardware_enable (int slot) return 0; /* No hardware to enable */ } -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) +#if defined(CONFIG_CMD_PCMCIA) static int pcmcia_hardware_disable(int slot) { return 0; /* No hardware to disable */ } -#endif /* CONFIG_COMMANDS & CFG_CMD_PCMCIA */ +#endif #endif /* CONFIG_PCMCIA && (CONFIG_RPXCLASSIC || CONFIG_RPXLITE) */ diff --git a/drivers/rtl8019.c b/drivers/rtl8019.c index 31462b30127..409a69f0214 100644 --- a/drivers/rtl8019.c +++ b/drivers/rtl8019.c @@ -34,7 +34,7 @@ #ifdef CONFIG_DRIVER_RTL8019 -#if (CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) /* packet page register access functions */ diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index 31ed855d7e2..4954cd0f7df 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -77,7 +77,7 @@ #include #include -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_NET_MULTI) && \ +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_RTL8139) #define TICKS_PER_SEC CFG_HZ diff --git a/drivers/rtl8169.c b/drivers/rtl8169.c index 1810850f5bd..63ea2cca9b1 100644 --- a/drivers/rtl8169.c +++ b/drivers/rtl8169.c @@ -55,7 +55,7 @@ #include #include -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_NET_MULTI) && \ +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_RTL8169) #undef DEBUG_RTL8169 diff --git a/drivers/sk98lin/uboot_drv.c b/drivers/sk98lin/uboot_drv.c index ff06ab38f96..d02cd1be242 100644 --- a/drivers/sk98lin/uboot_drv.c +++ b/drivers/sk98lin/uboot_drv.c @@ -25,7 +25,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_NET_MULTI) && \ +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_SK98) #include "h/skdrv1st.h" diff --git a/drivers/sym53c8xx.c b/drivers/sym53c8xx.c index f2c94ddaa5e..29eeccd9a8f 100644 --- a/drivers/sym53c8xx.c +++ b/drivers/sym53c8xx.c @@ -51,7 +51,7 @@ #define PRINTF(fmt,args...) #endif -#if ((CONFIG_COMMANDS & CFG_CMD_SCSI) || defined(CONFIG_CMD_SCSI)) && defined(CONFIG_SCSI_SYM53C8XX) +#if defined(CONFIG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX) #undef SCSI_SINGLE_STEP /* @@ -787,7 +787,7 @@ void scsi_chip_init(void) scsi_write_byte(DMODE,0x00); #endif } -#endif /* (CONFIG_COMMANDS & CFG_CMD_SCSI) */ +#endif #endif /* CONFIG_SCSI_SYM53C8XX */ diff --git a/drivers/ti_pci1410a.c b/drivers/ti_pci1410a.c index d5808e5751e..208ca50a743 100644 --- a/drivers/ti_pci1410a.c +++ b/drivers/ti_pci1410a.c @@ -64,7 +64,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA)) && defined(CONFIG_IDE_TI_CARDBUS) +#if defined(CONFIG_CMD_PCMCIA) && defined(CONFIG_IDE_TI_CARDBUS) int pcmcia_on(int ide_base_bus); diff --git a/drivers/tigon3.c b/drivers/tigon3.c index a6a4989bd39..7506a67003b 100644 --- a/drivers/tigon3.c +++ b/drivers/tigon3.c @@ -12,7 +12,7 @@ /******************************************************************************/ #include #include -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && !defined(CONFIG_NET_MULTI) && \ +#if defined(CONFIG_CMD_NET) && !defined(CONFIG_NET_MULTI) && \ defined(CONFIG_TIGON3) #ifdef CONFIG_BMW #include diff --git a/drivers/tqm8xx_pcmcia.c b/drivers/tqm8xx_pcmcia.c index 1dcefaa82b4..ce4b006a7fa 100644 --- a/drivers/tqm8xx_pcmcia.c +++ b/drivers/tqm8xx_pcmcia.c @@ -10,11 +10,11 @@ #undef CONFIG_PCMCIA -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) +#if defined(CONFIG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD) +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -241,7 +241,7 @@ int pcmcia_hardware_enable(int slot) } -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) +#if defined(CONFIG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { u_long reg; diff --git a/drivers/tsec.c b/drivers/tsec.c index e717cd74884..55334d69e1b 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -176,7 +176,7 @@ int tsec_initialize(bd_t * bis, int index, char *devname) priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) \ +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ && !defined(BITBANGMII) miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); #endif @@ -1443,7 +1443,7 @@ static void relocate_cmds(void) relocated = 1; } -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII) \ +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ && !defined(BITBANGMII) struct tsec_private *get_priv_for_phy(unsigned char phyaddr) @@ -1502,7 +1502,6 @@ static int tsec_miiphy_write(char *devname, unsigned char addr, return 0; } -#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) - && !defined(BITBANGMII) */ +#endif #endif /* CONFIG_TSEC_ENET */ diff --git a/drivers/tsi108_eth.c b/drivers/tsi108_eth.c index a25728eac33..524e9daa4cb 100644 --- a/drivers/tsi108_eth.c +++ b/drivers/tsi108_eth.c @@ -27,7 +27,7 @@ #include -#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(CONFIG_NET_MULTI) \ +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) \ && defined(CONFIG_TSI108_ETH) #if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2) diff --git a/drivers/tsi108_i2c.c b/drivers/tsi108_i2c.c index 2c90eed0d6f..3a3b75c39bf 100644 --- a/drivers/tsi108_i2c.c +++ b/drivers/tsi108_i2c.c @@ -28,7 +28,7 @@ #ifdef CONFIG_TSI108_I2C #include -#if (CONFIG_COMMANDS & CFG_CMD_I2C) || defined(CONFIG_CMD_I2C) +#if defined(CONFIG_CMD_I2C) #define I2C_DELAY 100000 #undef DEBUG_I2C @@ -279,5 +279,5 @@ int i2c_probe (uchar chip) return i2c_read (chip, 0, 1, (char *)&tmp, 1); } -#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */ +#endif #endif /* CONFIG_TSI108_I2C */ -- cgit v1.3.1 From ddb5d86f0215bcb6c293510c50eb050e92883b7a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Jul 2007 11:13:21 -0500 Subject: drivers/: Remove lingering references to CFG_CMD_* symbols. Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. Those always evaluated TRUE, and thus were always compiled even when IDE really wasn't defined/wanted. Signed-off-by: Jon Loeliger --- drivers/bcm570x.c | 2 +- drivers/cfb_console.c | 6 +++--- drivers/dc2114x.c | 2 +- drivers/mpc8xx_pcmcia.c | 2 +- drivers/rtl8139.c | 2 +- drivers/tigon3.c | 2 +- drivers/tqm8xx_pcmcia.c | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/bcm570x.c b/drivers/bcm570x.c index b00bcd772fc..703cda48653 100644 --- a/drivers/bcm570x.c +++ b/drivers/bcm570x.c @@ -1688,4 +1688,4 @@ QQ_GetTail( return pQueue->Array[Idx]; } -#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_BCM570x */ +#endif diff --git a/drivers/cfb_console.c b/drivers/cfb_console.c index 617361e405f..bcf877194e0 100644 --- a/drivers/cfb_console.c +++ b/drivers/cfb_console.c @@ -63,7 +63,7 @@ loop in VIDEO_TSTC_FCT (i8042) CFG_CONSOLE_BLINK_COUNT - value for delay loop - blink rate CONFIG_CONSOLE_TIME - display time/date in upper right corner, - needs CFG_CMD_DATE and CONFIG_CONSOLE_CURSOR + needs CONFIG_CMD_DATE and CONFIG_CONSOLE_CURSOR CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo CONFIG_CONSOLE_EXTRA_INFO - display additional board information strings @@ -175,9 +175,9 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #include #include #include -#ifdef CFG_CMD_DATE -#include +#if defined(CONFIG_CMD_DATE) +#include #endif #if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) diff --git a/drivers/dc2114x.c b/drivers/dc2114x.c index 721bbfc2ff0..d5275dceb0f 100644 --- a/drivers/dc2114x.c +++ b/drivers/dc2114x.c @@ -768,4 +768,4 @@ static void update_srom(struct eth_device *dev, bd_t *bis) } #endif /* UPDATE_SROM */ -#endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_TULIP */ +#endif diff --git a/drivers/mpc8xx_pcmcia.c b/drivers/mpc8xx_pcmcia.c index 04c44a44bf3..8a34cd30547 100644 --- a/drivers/mpc8xx_pcmcia.c +++ b/drivers/mpc8xx_pcmcia.c @@ -221,7 +221,7 @@ int pcmcia_off (void) pcmcia_hardware_disable(_slot_); return 0; } -#endif /* CFG_CMD_PCMCIA */ +#endif static u_int m8xx_get_graycode(u_int size) diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index 4954cd0f7df..9045523a312 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -535,4 +535,4 @@ static void rtl_disable(struct eth_device *dev) udelay (100); /* wait 100us */ } } -#endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_RTL8139 */ +#endif diff --git a/drivers/tigon3.c b/drivers/tigon3.c index 7506a67003b..860a8894fc7 100644 --- a/drivers/tigon3.c +++ b/drivers/tigon3.c @@ -6197,4 +6197,4 @@ LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, } return LM_STATUS_SUCCESS; } -#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_TIGON3 */ +#endif diff --git a/drivers/tqm8xx_pcmcia.c b/drivers/tqm8xx_pcmcia.c index ce4b006a7fa..132c7a5169b 100644 --- a/drivers/tqm8xx_pcmcia.c +++ b/drivers/tqm8xx_pcmcia.c @@ -263,7 +263,7 @@ int pcmcia_hardware_disable(int slot) return (0); } -#endif /* CFG_CMD_PCMCIA */ +#endif int pcmcia_voltage_set(int slot, int vcc, int vpp) { -- cgit v1.3.1 From 3865b1fb7843a08ad49a6319a36415752276ff48 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 11 Jul 2007 12:13:53 +0200 Subject: Fix some compile problems introduced by the latest CFG_CMD_xxx cleanup Signed-off-by: Stefan Roese --- common/cmd_flash.c | 2 +- common/cmd_nvedit.c | 5 ++--- drivers/macb.c | 2 +- net/nfs.c | 3 +-- net/sntp.c | 3 +-- 5 files changed, 6 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/common/cmd_flash.c b/common/cmd_flash.c index db38f94d034..11c8857313b 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -33,7 +33,7 @@ #if defined(CONFIG_CMD_FLASH) -#if (defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) #include /* parition handling routines */ diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index e313f2c4b67..de5a5148f69 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -538,7 +538,7 @@ int getenv_r (char *name, char *buf, unsigned len) return (-1); } -#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \ +#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \ || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \ || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -550,7 +550,6 @@ int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (saveenv() ? 1 : 0); } - #endif @@ -594,7 +593,7 @@ U_BOOT_CMD( " - delete environment variable 'name'\n" ); -#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \ +#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \ || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \ || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) U_BOOT_CMD( diff --git a/drivers/macb.c b/drivers/macb.c index ffb5f74cc52..bf7853aadd7 100644 --- a/drivers/macb.c +++ b/drivers/macb.c @@ -18,7 +18,7 @@ #include #if defined(CONFIG_MACB) \ - && (defined(CONFIG_CMD_NET) || defined(CONFIG_CMD_MII))) + && (defined(CONFIG_CMD_NET) || defined(CONFIG_CMD_MII)) /* * The u-boot networking stack is a little weird. It seems like the diff --git a/net/nfs.c b/net/nfs.c index 30a897d0633..df2caac48c8 100644 --- a/net/nfs.c +++ b/net/nfs.c @@ -31,8 +31,7 @@ /*#define NFS_DEBUG*/ -#if (defined(CONFIG_CMD_NET) \ - && defined(CONFIG_CMD_NFS) +#if defined(CONFIG_CMD_NET) && defined(CONFIG_CMD_NFS) #define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */ #define NFS_TIMEOUT 60 diff --git a/net/sntp.c b/net/sntp.c index 0a7f4782cbb..95e75422c10 100644 --- a/net/sntp.c +++ b/net/sntp.c @@ -12,8 +12,7 @@ #include "sntp.h" -#if (defined(CONFIG_CMD_NET) \ - && defined(CONFIG_CMD_SNTP) +#if defined(CONFIG_CMD_NET) && defined(CONFIG_CMD_SNTP) #define SNTP_TIMEOUT 10 -- cgit v1.3.1 From 40e81addab7bb74d20ddf681ce9babc880a828ee Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Wed, 11 Jul 2007 14:51:35 -0500 Subject: Start pci hose scan from hose->current_busno. Ensure hose->current_busno is not less than first_busno. This fixes broken board code which leaves current_busno=0 when first_busno is greater than 0 for the cases with multiple controllers. Signed-off-by: Ed Swarthout --- drivers/pci.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci.c b/drivers/pci.c index 050582f7826..41589192c1c 100644 --- a/drivers/pci.c +++ b/drivers/pci.c @@ -490,10 +490,16 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) int pci_hose_scan(struct pci_controller *hose) { + /* Start scan at current_busno. + * PCIe will start scan at first_busno+1. + */ + /* For legacy support, ensure current>=first */ + if (hose->first_busno > hose->current_busno) + hose->current_busno = hose->first_busno; #ifdef CONFIG_PCI_PNP pciauto_config_init(hose); #endif - return pci_hose_scan_bus(hose, hose->first_busno); + return pci_hose_scan_bus(hose, hose->current_busno); } void pci_init(void) -- cgit v1.3.1 From ba5feb12581bb2912ce301e4866b71f846e9fc07 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Wed, 11 Jul 2007 14:51:48 -0500 Subject: Minor improvements to drivers/pci_auto.c - Make pciauto_{pre,post}scan_setup_bridge non-static - Added physical address display in debug messages. Signed-off-by: Ed Swarthout --- drivers/pci_auto.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index f170c2db89e..9fa18e54276 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -65,7 +65,7 @@ int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned res->bus_lower = addr + size; - DEBUGF("address=0x%lx", addr); + DEBUGF("address=0x%lx bus_lower=%x", addr, res->bus_lower); *bar = addr; return 0; @@ -154,7 +154,7 @@ void pciauto_setup_device(struct pci_controller *hose, pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); } -static void pciauto_prescan_setup_bridge(struct pci_controller *hose, +void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus) { struct pci_region *pci_mem = hose->pci_mem; @@ -211,7 +211,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); } -static void pciauto_postscan_setup_bridge(struct pci_controller *hose, +void pciauto_postscan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus) { struct pci_region *pci_mem = hose->pci_mem; @@ -282,25 +282,36 @@ void pciauto_config_init(struct pci_controller *hose) if (hose->pci_mem) { pciauto_region_init(hose->pci_mem); - DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n", + DEBUGF("PCI Autoconfig: Bus Memory region: [%lx-%lx],\n" + "\t\tPhysical Memory [%x-%x]\n", hose->pci_mem->bus_start, - hose->pci_mem->bus_start + hose->pci_mem->size - 1); + hose->pci_mem->bus_start + hose->pci_mem->size - 1, + hose->pci_mem->phys_start, + hose->pci_mem->phys_start + hose->pci_mem->size - 1); } if (hose->pci_prefetch) { pciauto_region_init(hose->pci_prefetch); - DEBUGF("PCI Autoconfig: Prefetchable Memory region: [%lx-%lx]\n", + DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [%lx-%lx],\n" + "\t\tPhysical Memory [%x-%x]\n", hose->pci_prefetch->bus_start, - hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1); + hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1, + hose->pci_prefetch->phys_start, + hose->pci_prefetch->phys_start + + hose->pci_prefetch->size - 1); } if (hose->pci_io) { pciauto_region_init(hose->pci_io); - DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n", + DEBUGF("PCI Autoconfig: Bus I/O region: [%lx-%lx],\n" + "\t\tPhysical Memory: [%x-%x]\n", hose->pci_io->bus_start, - hose->pci_io->bus_start + hose->pci_io->size - 1); + hose->pci_io->bus_start + hose->pci_io->size - 1, + hose->pci_io->phys_start, + hose->pci_io->phys_start + hose->pci_io->size - 1); + } } -- cgit v1.3.1 From 571f49fa717004ca4268b4e24057efc7bf9f987b Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Wed, 11 Jul 2007 14:52:01 -0500 Subject: Support PCIe extended config registers FSL PCIe block has extended cfg registers in the 100 and 400 range. For example, to read the LTSSM register: pci display .0 404 1 Signed-off-by: Ed Swarthout --- drivers/pci_indirect.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c index d7be0810f57..a8220fb4117 100644 --- a/drivers/pci_indirect.c +++ b/drivers/pci_indirect.c @@ -45,7 +45,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ return 0; \ } -#elif defined(CONFIG_E500) +#elif defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ static int \ indirect_##rw##_config_##size(struct pci_controller *hose, \ @@ -55,7 +55,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \ b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ b = b - hose->first_busno; \ dev = PCI_BDF(b, d, f); \ - *(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000; \ + *(hose->cfg_addr) = dev | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; \ sync(); \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ return 0; \ -- cgit v1.3.1 From e8b85f3ba4cd8930e0a2fea2100c815d64201765 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Wed, 11 Jul 2007 14:52:08 -0500 Subject: pciauto setup bridge The P2P bridge bus numbers programmed into the device are relative to hose->first_busno. Signed-off-by: Ed Swarthout --- drivers/pci_auto.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 9fa18e54276..f16f8d3c84a 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -165,8 +165,10 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); /* Configure bus number registers */ - pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev)); - pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus); + pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, + PCI_BUS(dev) - hose->first_busno); + pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, + sub_bus - hose->first_busno); pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); if (pci_mem) { @@ -219,7 +221,8 @@ void pciauto_postscan_setup_bridge(struct pci_controller *hose, struct pci_region *pci_io = hose->pci_io; /* Configure bus number registers */ - pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus); + pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, + sub_bus - hose->first_busno); if (pci_mem) { /* Round memory allocator to 1MB boundary */ -- cgit v1.3.1 From 5dc210dec5bace98a50b6ba905347890091a9bb0 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Wed, 11 Jul 2007 14:52:16 -0500 Subject: Add simple agent/end-point configuration in PCI AutoConfig for PCI_CLASS_PROCESSOR_POWERPC. Signed-off-by: Ed Swarthout --- drivers/pci_auto.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index f16f8d3c84a..a3c609ba49c 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -331,6 +331,12 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); switch(class) { + case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ + DEBUGF("PCI AutoConfig: Found PowerPC device\n"); + pciauto_setup_device(hose, dev, 6, hose->pci_mem, + hose->pci_prefetch, hose->pci_io); + break; + case PCI_CLASS_BRIDGE_PCI: hose->current_busno++; pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io); -- cgit v1.3.1 From 7507d56ccaf7aae1c474342a9a5540165cd7e9d9 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 8 May 2007 17:23:02 -0500 Subject: Fix Marvell 88e1145 PHY init code Fix a bug in the Marvell 88e1145 PHY init code in the TSEC driver where the reset was being done after the errata code instead of before. Signed-off-by: Haiying Wang Signed-off-by: Andy Fleming --- drivers/tsec.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index 1298478704f..c19d87fc6a4 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -1037,14 +1037,16 @@ static struct phy_info phy_info_M88E1145 = { "Marvell 88E1145", 4, (struct phy_cmd[]){ /* config */ + /* Reset the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + /* Errata E0, E1 */ {29, 0x001b, NULL}, {30, 0x418f, NULL}, {29, 0x0016, NULL}, {30, 0xa2da, NULL}, - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + /* Configure the PHY */ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, -- cgit v1.3.1 From 2a3cee43c3b71fa5b8d91db19f05067865290f3e Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 9 May 2007 00:54:20 -0500 Subject: tsec: Fix PHY code to match first driver Jarrold Wen noticed that the generic PHY code always matches under the current implementation. Change it so the first match wins, and *only* unknown PHYs trigger the generic driver Signed-off-by: Andy Fleming --- drivers/tsec.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index c19d87fc6a4..467df8430ba 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -1353,8 +1353,10 @@ struct phy_info *get_phy_info(struct eth_device *dev) /* loop through all the known PHY types, and find one that */ /* matches the ID we read from the PHY. */ for (i = 0; phy_info[i]; i++) { - if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) + if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { theInfo = phy_info[i]; + break; + } } if (theInfo == NULL) { -- cgit v1.3.1 From 5a56af3b522ba47fb33a3fee84d23bf1e5429654 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Fri, 8 Jun 2007 16:41:18 -0500 Subject: Remove erroneous errata code from Marvel 88E1111S driver The Marvel 88E1111S driver for the TSEC was copied from the 88E1101 driver, and included a fix for an erratum which does not exist on that part. Now it is removed Signed-off-by: Andy Fleming --- drivers/tsec.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index 467df8430ba..b6c086f4a1f 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -993,11 +993,6 @@ struct phy_info phy_info_M88E1111S = { (struct phy_cmd[]){ /* config */ /* Reset and configure the PHY */ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {0x1d, 0x1f, NULL}, - {0x1e, 0x200c, NULL}, - {0x1d, 0x5, NULL}, - {0x1e, 0x0, NULL}, - {0x1e, 0x100, NULL}, {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, -- cgit v1.3.1 From c7e717ebc2b044d7a71062552c9dc0f54ea9b779 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Fri, 3 Aug 2007 04:05:25 -0500 Subject: Add Marvell 1149 PHY support to the TSEC --- drivers/tsec.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index f7bb9c12374..1399d076891 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -898,6 +898,39 @@ static void tsec_halt(struct eth_device *dev) phy_run_commands(priv, priv->phyinfo->shutdown); } +struct phy_info phy_info_M88E1149S = { + 0x1410ca, + "Marvell 88E1149S", + 4, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, +}; + /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ struct phy_info phy_info_BCM5461S = { 0x02060c1, /* 5461 ID */ @@ -1318,6 +1351,7 @@ struct phy_info *phy_info[] = { &phy_info_M88E1011S, &phy_info_M88E1111S, &phy_info_M88E1145, + &phy_info_M88E1149S, &phy_info_dm9161, &phy_info_lxt971, &phy_info_VSC8244, -- cgit v1.3.1 From 63cec5814fab5d2b1c86982327433807a5ac0249 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Thu, 2 Aug 2007 14:09:49 -0500 Subject: Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout Signed-off-by: Zhang Wei Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 165 +++++++++++++++++++++++++-------- board/mpc8641hpcn/u-boot.lds | 1 - cpu/mpc86xx/Makefile | 3 +- cpu/mpc86xx/pci.c | 146 ----------------------------- cpu/mpc86xx/pcie_indirect.c | 199 ---------------------------------------- drivers/Makefile | 2 +- drivers/ahci.c | 3 +- drivers/fsl_pci_init.c | 180 ++++++++++++++++++++++++++++++++++++ include/asm-ppc/immap_fsl_pci.h | 150 ++++++++++++++++++++++++++++++ include/configs/MPC8641HPCN.h | 44 +++++---- include/pci.h | 6 ++ 11 files changed, 493 insertions(+), 406 deletions(-) delete mode 100644 cpu/mpc86xx/pci.c delete mode 100644 cpu/mpc86xx/pcie_indirect.c create mode 100644 drivers/fsl_pci_init.c create mode 100644 include/asm-ppc/immap_fsl_pci.h (limited to 'drivers') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 5e02cc5a5e6..d2182aba5f0 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -11,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -55,37 +56,6 @@ int checkboard(void) { puts("Board: MPC8641HPCN\n"); -#ifdef CONFIG_PCI - - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_pex_t *pex1 = &immap->im_pex1; - - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; -#ifdef DEBUG - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); -#endif - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 - || io_sel == 6 || io_sel == 7 || io_sel == 0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det); - if (pex1->pme_msg_det) { - pex1->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pex1->pme_msg_det); - } - debug("\n"); - } else { - puts("PCI-EXPRESS 1: Disabled\n"); - } - -#else - puts("PCI-EXPRESS1: Disabled\n"); -#endif - return 0; } @@ -220,21 +190,138 @@ static struct pci_config_table pci_fsl86xxads_config_table[] = { #endif -static struct pci_controller hose = { +static struct pci_controller pci1_hose = { #ifndef CONFIG_PCI_PNP - config_table:pci_mpc86xxcts_config_table, + config_table:pci_mpc86xxcts_config_table #endif }; - #endif /* CONFIG_PCI */ +#ifdef CONFIG_PCI2 +static struct pci_controller pci2_hose; +#endif /* CONFIG_PCI2 */ + +int first_free_busno = 0; + + void pci_init_board(void) { -#ifdef CONFIG_PCI - extern void pci_mpc86xx_init(struct pci_controller *hose); + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; +#ifdef DEBUG + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); +#endif + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + debug("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + /* + * Activate ULI1575 legacy chip by performing a fake + * memory access. Needed to make ULI RTC work. + */ + in_be32((unsigned *) CFG_PCI1_MEM_BASE + + CFG_PCI1_MEM_SIZE - 0x1000000); + + } else { + puts("PCI-EXPRESS 1: Disabled\n"); + } +} +#else + puts("PCI-EXPRESS1: Disabled\n"); +#endif /* CONFIG_PCI1 */ + +#ifdef CONFIG_PCI2 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci2_hose; + + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); +} +#else + puts("PCI-EXPRESS 2: Disabled\n"); +#endif /* CONFIG_PCI2 */ - pci_mpc86xx_init(&hose); -#endif /* CONFIG_PCI */ } #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index 34b50e4be20..e4792ef1998 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -57,7 +57,6 @@ SECTIONS cpu/mpc86xx/cpu_init.o (.text) cpu/mpc86xx/cpu.o (.text) cpu/mpc86xx/speed.o (.text) - cpu/mpc86xx/pci.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index fffcfd24029..6d9300e22e7 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -1,4 +1,5 @@ # +# Copyright 2007 Freescale Semiconductor, Inc. # (C) Copyright 2002,2003 Motorola Inc. # Xianghua Xiao,X.Xiao@motorola.com # @@ -30,7 +31,7 @@ LIB = $(obj)lib$(CPU).a START = start.o #resetvec.o SOBJS = cache.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o pcie_indirect.o spd_sdram.o + spd_sdram.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c deleted file mode 100644 index b86548db4f9..00000000000 --- a/cpu/mpc86xx/pci.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor,Inc. - * 2005, 2006. All rights reserved. - * - * Ed Swarthout (ed.swarthout@freescale.com) - * Jason Jin (Jason.jin@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PCIE Configuration space access support for PCIE Bridge - */ -#include -#include - -#if defined(CONFIG_PCI) -void -pci_mpc86xx_init(struct pci_controller *hose) -{ - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_pex_t *pcie1 = &immap->im_pex1; - u16 temp16; - u32 temp32; - - volatile ccsr_gur_t *gur = &immap->im_gur; - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pcie1_host = (host1_agent == 2) || (host1_agent == 3); - uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || - io_sel == 7 || io_sel == 0xf) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - printf("PCI-EXPRESS 1: Configured as %s \n", - pcie1_agent ? "Agent" : "Host"); - if (pcie1_agent) - return; /*Don't scan bus when configured as agent */ - printf(" Scanning PCIE bus"); - debug("0x%08x=0x%08x ", - &pcie1->pme_msg_det, - pcie1->pme_msg_det); - if (pcie1->pme_msg_det) { - pcie1->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pcie1->pme_msg_det); - } - debug("\n"); - } else { - printf("PCI-EXPRESS 1 disabled!\n"); - return; - } - - /* - * Set first_bus=0 only skipped B0:D0:F0 which is - * a reserved device in M1575, but make it easy for - * most of the scan process. - */ - hose->first_busno = 0x00; - hose->last_busno = 0xfe; - - pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004)); - - pci_hose_read_config_word(hose, - PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16); - temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_hose_write_config_word(hose, - PCI_BDF(0, 0, 0), PCI_COMMAND, temp16); - - pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, - PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80); - - pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, - &temp32); - temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16); - pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, - temp32); - - pcie1->powar1 = 0; - pcie1->powar2 = 0; - pcie1->piwar1 = 0; - pcie1->piwar1 = 0; - - pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcie1->powar1 = 0x8004401c; /* 512M MEM space */ - pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcie1->potear1 = 0x00000000; - - pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; - pcie1->powar2 = 0x80088017; /* 16M IO space */ - pcie1->potar2 = 0x00000000; - pcie1->potear2 = 0x00000000; - - pcie1->pitar1 = 0x00000000; - pcie1->piwbar1 = 0x00000000; - /* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */ - pcie1->piwar1 = 0xa0f5501e; - - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno); - debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno); - - printf("....PCIE1 scan & enumeration done\n"); -} -#endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/pcie_indirect.c b/cpu/mpc86xx/pcie_indirect.c deleted file mode 100644 index b00ad76ab89..00000000000 --- a/cpu/mpc86xx/pcie_indirect.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Support for indirect PCI bridges. - * - * Copyright (c) Freescale Semiconductor, Inc. - * 2006. All rights reserved. - * - * Jason Jin - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * partly derived from - * arch/powerpc/platforms/86xx/mpc86xx_pcie.c - */ - -#include - -#ifdef CONFIG_PCI - -#include -#include -#include - -#define PCI_CFG_OUT out_be32 -#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff) - -static int -indirect_read_config_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - int len, - u32 *val) -{ - int bus = PCI_BUS(dev); - - volatile unsigned char *cfg_data; - u32 temp; - - PEX_FIX; - if (bus == 0xff) { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000001); - } else { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000000); - } - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ - cfg_data = hose->cfg_data; - PEX_FIX; - temp = in_le32((u32 *) cfg_data); - switch (len) { - case 1: - *val = (temp >> (((offset & 3)) * 8)) & 0xff; - break; - case 2: - *val = (temp >> (((offset & 3)) * 8)) & 0xffff; - break; - default: - *val = temp; - break; - } - - return 0; -} - -static int -indirect_write_config_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - int len, - u32 val) -{ - int bus = PCI_BUS(dev); - volatile unsigned char *cfg_data; - u32 temp; - - PEX_FIX; - if (bus == 0xff) { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000001); - } else { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000000); - } - - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ - cfg_data = hose->cfg_data; - switch (len) { - case 1: - PEX_FIX; - temp = in_le32((u32 *) cfg_data); - temp = (temp & ~(0xff << ((offset & 3) * 8))) | - (val << ((offset & 3) * 8)); - PEX_FIX; - out_le32((u32 *) cfg_data, temp); - break; - case 2: - PEX_FIX; - temp = in_le32((u32 *) cfg_data); - temp = (temp & ~(0xffff << ((offset & 3) * 8))); - temp |= (val << ((offset & 3) * 8)); - PEX_FIX; - out_le32((u32 *) cfg_data, temp); - break; - default: - PEX_FIX; - out_le32((u32 *) cfg_data, val); - break; - } - PEX_FIX; - return 0; -} - -static int -indirect_read_config_byte_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u8 *val) -{ - u32 val32; - indirect_read_config_pcie(hose, dev, offset, 1, &val32); - *val = (u8) val32; - return 0; -} - -static int -indirect_read_config_word_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u16 *val) -{ - u32 val32; - indirect_read_config_pcie(hose, dev, offset, 2, &val32); - *val = (u16) val32; - return 0; -} - -static int -indirect_read_config_dword_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u32 *val) -{ - return indirect_read_config_pcie(hose, dev, offset, 4, val); -} - -static int -indirect_write_config_byte_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u8 val) -{ - return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val); -} - -static int -indirect_write_config_word_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - unsigned short val) -{ - return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val); -} - -static int -indirect_write_config_dword_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u32 val) -{ - return indirect_write_config_pcie(hose, dev, offset, 4, val); -} - -void -pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) -{ - pci_set_ops(hose, - indirect_read_config_byte_pcie, - indirect_read_config_word_pcie, - indirect_read_config_dword_pcie, - indirect_write_config_byte_pcie, - indirect_write_config_word_pcie, - indirect_write_config_dword_pcie); - - hose->cfg_addr = (unsigned int *)cfg_addr; - hose->cfg_data = (unsigned char *)cfg_data; -} - -#endif /* CONFIG_PCI */ diff --git a/drivers/Makefile b/drivers/Makefile index 48fd4eaade0..fa2e86fd20f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -52,7 +52,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \ ks8695eth.o \ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ rpx_pcmcia.o \ - fsl_i2c.o + fsl_i2c.o fsl_pci_init.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/ahci.c b/drivers/ahci.c index 8ceff00925f..ccd4d71e8ae 100644 --- a/drivers/ahci.c +++ b/drivers/ahci.c @@ -253,7 +253,8 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) static int ahci_init_one(pci_dev_t pdev) { - u32 iobase, vendor; + u32 iobase; + u16 vendor; int rc; memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c new file mode 100644 index 00000000000..1d1f6df997a --- /dev/null +++ b/drivers/fsl_pci_init.c @@ -0,0 +1,180 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define DEBUG +#include + +#ifdef CONFIG_FSL_PCI_INIT + +/* + * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's + * + * Initialize controller and call the common driver/pci pci_hose_scan to + * scan for bridges and devices. + * + * Hose fields which need to be pre-initialized by board specific code: + * regions[] + * first_busno + * + * Fields updated: + * last_busno + */ + +#include +#include + +void pciauto_prescan_setup_bridge(struct pci_controller *hose, + pci_dev_t dev, int sub_bus); +void pciauto_postscan_setup_bridge(struct pci_controller *hose, + pci_dev_t dev, int sub_bus); + +void pciauto_config_init(struct pci_controller *hose); +void +fsl_pci_init(struct pci_controller *hose) +{ + u16 temp16; + u32 temp32; + int busno = hose->first_busno; + int enabled; + u16 ltssm; + u8 temp8; + int r; + int bridge; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; + pci_dev_t dev = PCI_BDF(busno,0,0); + + /* Initialize ATMU registers based on hose regions and flags */ + volatile pot_t *po=&pci->pot[1]; /* skip 0 */ + volatile pit_t *pi=&pci->pit[0]; /* ranges from: 3 to 1 */ + +#ifdef DEBUG + int neg_link_w; +#endif + + for (r=0; rregion_count; r++) { + if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */ + pi->pitar = (hose->regions[r].bus_start >> 12) & 0x000fffff; + pi->piwbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; + pi->piwbear = 0; + pi->piwar = PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | + (__ilog2(hose->regions[r].size) - 1); + pi++; + } else { /* Outbound */ + po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; + po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff; + po->potear = 0; + if (hose->regions[r].flags & PCI_REGION_IO) + po->powar = POWAR_EN | POWAR_IO_READ | POWAR_IO_WRITE | + (__ilog2(hose->regions[r].size) - 1); + else + po->powar = POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE | + (__ilog2(hose->regions[r].size) - 1); + po++; + } + } + + pci_register_hose(hose); + pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ + hose->current_busno = hose->first_busno; + + pci->pedr = 0xffffffff; /* Clear any errors */ + pci->peer = 0xffffffff; /* Enable Error Interupts */ + pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32); + temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ + pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); + + pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8); + bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */ + + if ( bridge ) { + + pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); + enabled = ltssm >= PCI_LTSSM_L0; + + if (!enabled) { + debug("....PCIE link error. Skipping scan." + "LTSSM=0x%02x\n", temp16); + hose->last_busno = hose->first_busno; + return; + } + + pci->pme_msg_det = 0xffffffff; + pci->pme_msg_int_en = 0xffffffff; +#ifdef DEBUG + pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); + neg_link_w = (temp16 & 0x3f0 ) >> 4; + debug("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", + ltssm, neg_link_w); +#endif + hose->current_busno++; /* Start scan with secondary */ + pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); + + } else { +#if 0 +/* done in pci_hose_config_device() */ + pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); + temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, temp16); + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); +#endif + } + + /* Call setup to allocate PCSRBAR window */ + pciauto_setup_device(hose, dev, 1, hose->pci_mem, + hose->pci_prefetch, hose->pci_io); + + printf (" Scanning PCI bus %02x\n", hose->current_busno); + hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); + + if ( bridge ) { /* update limit regs and subordinate busno */ + pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); + } + + /* Clear all error indications */ + + if (pci->pme_msg_det && pci->pme_msg_det != 0xffffffff) { + debug("pci_fsl_init: pme_msg_det@%x=%x. Clearing\n", + &pci->pme_msg_det, pci->pme_msg_det); + pci->pme_msg_det = 0xffffffff; + } + + if (pci->pedr) { + debug("pci_fsl_init: pedr@%x=%x. Clearing\n", + &pci->pedr, pci->pedr); + pci->pedr = 0xffffffff; + } + + pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); + if (temp16) { + debug("pci_fsl_init: PCI_DSR@%x=%x. Clearing\n", + PCI_DSR, temp16); + pci_hose_write_config_word(hose, dev, + PCI_DSR, 0xffff); + } + + pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); + if (temp16) { + debug("pci_fsl_init: PCI_SEC_STATUS@%x=%x. Clearing\n", + PCI_SEC_STATUS, temp16); + pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); + } +} + +#endif /* CONFIG_FSL_PCI */ diff --git a/include/asm-ppc/immap_fsl_pci.h b/include/asm-ppc/immap_fsl_pci.h new file mode 100644 index 00000000000..bd732b66889 --- /dev/null +++ b/include/asm-ppc/immap_fsl_pci.h @@ -0,0 +1,150 @@ +/* (C) Copyright 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __IMMAP_85xx_fsl_pci__ +#define __IMMAP_85xx_fsl_pci__ + +/* + * Common PCI/PCIE Register structure for mpc85xx and mpc86xx + */ + +/* + * PCI Translation Registers + */ +typedef struct pci_outbound_window { + u32 potar; /* 0x00 - Address */ + u32 potear; /* 0x04 - Address Extended */ + u32 powbar; /* 0x08 - Window Base Address */ + u32 res1; + u32 powar; /* 0x10 - Window Attributes */ +#define POWAR_EN 0x80000000 +#define POWAR_IO_READ 0x00080000 +#define POWAR_MEM_READ 0x00040000 +#define POWAR_IO_WRITE 0x00008000 +#define POWAR_MEM_WRITE 0x00004000 + u32 res2[3]; +} pot_t; + +typedef struct pci_inbound_window { + u32 pitar; /* 0x00 - Address */ + u32 res1; + u32 piwbar; /* 0x08 - Window Base Address */ + u32 piwbear; /* 0x0c - Window Base Address Extended */ + u32 piwar; /* 0x10 - Window Attributes */ +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_LOCAL 0x00f00000 +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 + u32 res2[3]; +} pit_t; + +/* PCI/PCI Express Registers */ +typedef struct ccsr_pci { + u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */ + u32 cfg_data; /* 0x004 - PCI Configuration Data Register */ + u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */ + u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */ + u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */ + u32 config; /* 0x014 - PCIE CONFIG Register */ + char res2[8]; + u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */ + u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ + u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ + u32 pm_command; /* 0x02c - PCIE PM Command register */ + char res4[3016]; /* (- #xbf8 #x30)3016 */ + u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ + u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ + + pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */ + u32 res5[64]; + pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */ +#define PIT3 0 +#define PIT2 1 +#define PIT1 2 + +#if 0 + u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */ + u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */ + char res5[8]; + u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */ + char res6[12]; + u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */ + u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */ + u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */ + char res7[4]; + u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */ + char res8[12]; + u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */ + u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */ + u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */ + char res9[4]; + u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */ + char res10[12]; + u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */ + u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */ + u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */ + char res11[4]; + u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */ + char res12[12]; + u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */ + u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */ + u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */ + char res13[4]; + u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */ + char res14[268]; + u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */ + char res15[4]; + u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */ + u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */ + u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */ + char res16[12]; + u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */ + char res17[4]; + u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */ + u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */ + u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */ + char res18[12]; + u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */ + char res19[4]; + u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */ + char res20[4]; + u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */ + char res21[12]; +#endif + u32 pedr; /* 0xe00 - PCI Error Detect Register */ + u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */ + u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */ + u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */ + u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */ +/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */ + u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */ + u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */ + u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */ + u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */ +/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */ + char res22[4]; + u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */ + u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */ + u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */ + u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ + char res23[456]; /* (- #x1000 #xe38) 456 */ +} ccsr_fsl_pci_t; + +#endif /*__IMMAP_fsl_pci__*/ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 808c19f7673..5a511e53244 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -46,8 +46,10 @@ #define CFG_RESET_ADDRESS 0xfff00100 -/*#undef CONFIG_PCI*/ -#define CONFIG_PCI +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ +#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -76,6 +78,9 @@ #define L2_ENABLE (L2CR_L2E) #ifndef CONFIG_SYS_CLK_FREQ +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif @@ -93,6 +98,9 @@ #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) + /* * DDR Setup */ @@ -296,9 +304,9 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ /* PCI view of System Memory */ #define CFG_PCI_MEMORY_BUS 0x00000000 @@ -311,10 +319,10 @@ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe3000000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) @@ -396,20 +404,20 @@ * 0xa000_0000 512M PCI-Express 2 Memory * Changed it for operating from 0xd0000000 */ -#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ +#define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT1U CFG_DBAT1U /* * BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ -#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ +#define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) -#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_DBAT2U (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT2U CFG_DBAT2U /* @@ -428,10 +436,10 @@ * 0xe300_0000 16M PCI-Express 2 I/0 * Note that this is at 0xe0000000 */ -#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ +#define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_DBAT4U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT4U CFG_DBAT4U /* diff --git a/include/pci.h b/include/pci.h index 7c9a0e34410..8e5dacc0df6 100644 --- a/include/pci.h +++ b/include/pci.h @@ -302,6 +302,12 @@ #define PCI_MAX_PCI_DEVICES 32 #define PCI_MAX_PCI_FUNCTIONS 8 +#define PCI_DCR 0x54 /* PCIe Device Control Register */ +#define PCI_DSR 0x56 /* PCIe Device Status Register */ +#define PCI_LSR 0x5e /* PCIe Link Status Register */ +#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ +#define PCI_LTSSM_L0 0x16 /* L0 state */ + /* Include the ID list */ #include -- cgit v1.3.1 From 5728be389e65fd47f34b33c2596271eb4db751ae Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 6 Aug 2007 01:01:49 +0200 Subject: Coding style cleanup. Update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 931 ++++++++++++++++++++++++++++++++++++++++++--- cpu/ppc4xx/44x_spd_ddr.c | 2 +- drivers/tsec.c | 62 +-- include/configs/ADNPESC1.h | 6 +- include/configs/APC405.h | 2 +- include/configs/Adder.h | 8 +- include/configs/BAB7xx.h | 6 +- include/configs/BC3450.h | 2 +- include/configs/CANBT.h | 2 +- include/configs/CPCI750.h | 24 +- include/configs/CU824.h | 2 +- 11 files changed, 931 insertions(+), 116 deletions(-) (limited to 'drivers') diff --git a/CHANGELOG b/CHANGELOG index 207f1bc653e..58ef66ecdc4 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,830 @@ +commit 8092fef4c29b395958bb649647da7e3775731517 +Author: Martin Krause +Date: Tue Dec 12 14:26:01 2006 +0100 + + Add functions to list of exported functions + + Additionally export the following fuctions (to make trab_config build again): + - simple_strtol() + - strcmp() + + Also bump the ABI version to reflect this change + + Signed-off-by: Martin Krause + +commit 63cec5814fab5d2b1c86982327433807a5ac0249 +Author: Ed Swarthout +Date: Thu Aug 2 14:09:49 2007 -0500 + + Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. + + All of the PCI/PCI-Express driver and initialization code that + was in the MPC8641HPCN port has now been moved into the common + drivers/fsl_pci_init.c. In a subsequent patch, this will be + utilized by the 85xx ports as well. + + Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. + + Also enable the second PCI-Express controller on 8641 + by getting its BATS and CFG_ setup right. + + Fixed a u16 vendor compiler warning in AHCI driver too. + + Signed-off-by: Ed Swarthout + Signed-off-by: Zhang Wei + Signed-off-by: Jon Loeliger + +commit c7e717ebc2b044d7a71062552c9dc0f54ea9b779 +Author: Andy Fleming +Date: Fri Aug 3 04:05:25 2007 -0500 + + Add Marvell 1149 PHY support to the TSEC + +commit 63e22764d2f8653f68888c667eb65b3996b52680 +Author: Wolfgang Denk +Date: Thu Aug 2 10:11:18 2007 +0200 + + Minor cleanup of _nand build rules. + +commit cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197 +Author: Wolfgang Denk +Date: Thu Aug 2 00:48:45 2007 +0200 + + Fix build errors and warnings / code cleanup. + + Signed-off-by: Wolfgang Denk + +commit 5a56af3b522ba47fb33a3fee84d23bf1e5429654 +Author: Andy Fleming +Date: Fri Jun 8 16:41:18 2007 -0500 + + Remove erroneous errata code from Marvel 88E1111S driver + + The Marvel 88E1111S driver for the TSEC was copied from the + 88E1101 driver, and included a fix for an erratum which does not + exist on that part. Now it is removed + + Signed-off-by: Andy Fleming + +commit 982efcf23fd03647e01e2fbe28a7a36239156cc0 +Author: Andy Fleming +Date: Tue Jun 5 16:38:44 2007 -0500 + + From: eran liberty + + adds the reset register to 85xx immap + + Signed-off-by: Eran Liberty + Signed-off-by: Andy Fleming + +commit d3ec0d943a045bdb99e159e7bbc77430e09f11d7 +Author: Andy Fleming +Date: Thu May 10 17:50:01 2007 -0500 + + Polished the 85xx ADS config files + + Made the boot commands use device trees by default. + Also moved the ramdisk to 1000000 (I think the previous address + was getting overridden during boot). + + Signed-off-by: Andy Fleming + +commit bfb37b32d1b0b03f18077dba49cc66a6e76fa038 +Author: Ed Swarthout +Date: Wed May 9 11:03:32 2007 -0500 + + 8544ds: Fix Makefile after moving pixis to board/freescale. + + The OBJTREE != SRCTREE build scenario was broken. + This fixes it. + + Signed-off-by: Ed Swarthout + Signed-off-by: Jon Loeliger + +commit 2a3cee43c3b71fa5b8d91db19f05067865290f3e +Author: Andy Fleming +Date: Wed May 9 00:54:20 2007 -0500 + + tsec: Fix PHY code to match first driver + + Jarrold Wen noticed that the generic PHY code always matches + under the current implementation. Change it so the first match + wins, and *only* unknown PHYs trigger the generic driver + + Signed-off-by: Andy Fleming + +commit ccc091aac61a38cd998d575d92f7232e256d6312 +Author: Andy Fleming +Date: Tue May 8 17:27:43 2007 -0500 + + Add support for CPM device tree configuration to 8560 ADS + + * Adds code to modify CPM frequencies + * Cleans up the config file to #define TSEC and (for now) #undef FCC + * Adds the MII command for all 8560 ADS configurations + * Updates config file to provide convenience commands for booting + with a device tree + + Signed-off-by: Vitaly Bordug + Signed-off-by: Andy Fleming + +commit 7507d56ccaf7aae1c474342a9a5540165cd7e9d9 +Author: Andy Fleming +Date: Tue May 8 17:23:02 2007 -0500 + + Fix Marvell 88e1145 PHY init code + + Fix a bug in the Marvell 88e1145 PHY init code in the TSEC driver + where the reset was being done after the errata code instead of + before. + + Signed-off-by: Haiying Wang + Signed-off-by: Andy Fleming + +commit 5dc210dec5bace98a50b6ba905347890091a9bb0 +Author: Ed Swarthout +Date: Wed Jul 11 14:52:16 2007 -0500 + + Add simple agent/end-point configuration in PCI AutoConfig for PCI_CLASS_PROCESSOR_POWERPC. + + Signed-off-by: Ed Swarthout + +commit e8b85f3ba4cd8930e0a2fea2100c815d64201765 +Author: Ed Swarthout +Date: Wed Jul 11 14:52:08 2007 -0500 + + pciauto setup bridge + + The P2P bridge bus numbers programmed into the device are relative to + hose->first_busno. + + Signed-off-by: Ed Swarthout + +commit 571f49fa717004ca4268b4e24057efc7bf9f987b +Author: Ed Swarthout +Date: Wed Jul 11 14:52:01 2007 -0500 + + Support PCIe extended config registers + + FSL PCIe block has extended cfg registers in the 100 and 400 range. + For example, to read the LTSSM register: pci display .0 404 1 + + Signed-off-by: Ed Swarthout + +commit ba5feb12581bb2912ce301e4866b71f846e9fc07 +Author: Ed Swarthout +Date: Wed Jul 11 14:51:48 2007 -0500 + + Minor improvements to drivers/pci_auto.c + + - Make pciauto_{pre,post}scan_setup_bridge non-static + - Added physical address display in debug messages. + + Signed-off-by: Ed Swarthout + +commit 40e81addab7bb74d20ddf681ce9babc880a828ee +Author: Ed Swarthout +Date: Wed Jul 11 14:51:35 2007 -0500 + + Start pci hose scan from hose->current_busno. + + Ensure hose->current_busno is not less than first_busno. This fixes + broken board code which leaves current_busno=0 when first_busno is + greater than 0 for the cases with multiple controllers. + + Signed-off-by: Ed Swarthout + +commit 3865b1fb7843a08ad49a6319a36415752276ff48 +Author: Stefan Roese +Date: Wed Jul 11 12:13:53 2007 +0200 + + Fix some compile problems introduced by the latest CFG_CMD_xxx cleanup + + Signed-off-by: Stefan Roese + +commit e9514751cfa5cce61ea699fa0d3eb37898a5eeb5 +Author: Stefan Roese +Date: Sun Jul 8 13:44:27 2007 +0200 + + Fix malloc problem introduced with the relocation fixup for the PPC platform + + The relocation fixup didn't handle the malloc pointer initialization + correctly. This patch fixes this problem. Tested successfully on 4xx. + The relocation fixup patches for 4xx will follow soon. + + Signed-off-by: Stefan Roese + +commit b3aff0cb9ecf236d7e8c93761dd1dadf6837a582 +Author: Jon Loeliger +Date: Tue Jul 10 11:19:50 2007 -0500 + + disk/ doc/ lib_*/ and tools/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit ddb5d86f0215bcb6c293510c50eb050e92883b7a +Author: Jon Loeliger +Date: Tue Jul 10 11:13:21 2007 -0500 + + drivers/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit f40a7f3e3888b42a43674b099e5470022c8c544c +Author: Jon Loeliger +Date: Tue Jul 10 11:07:56 2007 -0500 + + fs/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit 610f2e9c28a9c101e09fa1b78143cf5f00ed1593 +Author: Jon Loeliger +Date: Tue Jul 10 11:05:02 2007 -0500 + + net/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit 902531788376046da212afd1661cffb62f3daa1c +Author: Jon Loeliger +Date: Tue Jul 10 11:02:44 2007 -0500 + + common/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit d39b57415838c73fb0a37eca84de3c68ba990586 +Author: Jon Loeliger +Date: Tue Jul 10 10:48:22 2007 -0500 + + board/[j-z]*: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit 77a318545d57aefa844752465b94c7e09a3f26d0 +Author: Jon Loeliger +Date: Tue Jul 10 10:39:10 2007 -0500 + + board/[A-Za-i]*: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit 068b60a0eb7e73b243ca55399f2a7df76e2c3f3d +Author: Jon Loeliger +Date: Tue Jul 10 10:27:39 2007 -0500 + + cpu/ rtc/ include/: Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 079a136c3588814784561d6e4856970ee82d6e2a +Author: Jon Loeliger +Date: Tue Jul 10 10:12:10 2007 -0500 + + include/configs/[p-z]* + misc: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 7f5c01577400c74cc5bac74f41dd0d3c79df623c +Author: Jon Loeliger +Date: Tue Jul 10 09:38:02 2007 -0500 + + include/configs/[g-o]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 80ff4f99b84b64edca3fd10da365ec1493be1c95 +Author: Jon Loeliger +Date: Tue Jul 10 09:29:01 2007 -0500 + + include/configs/[a-e]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit a1aa0bb502e25fd598b5e0ccdfb2c174921d714a +Author: Jon Loeliger +Date: Tue Jul 10 09:22:23 2007 -0500 + + include/configs/[P-Z]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 659e2f6736232a08acca8785c206e2b4d9cd07d7 +Author: Jon Loeliger +Date: Tue Jul 10 09:10:49 2007 -0500 + + include/configs/[J-O]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 11799434c5ff15a612577bb1ad1f4ea1a0595e4b +Author: Jon Loeliger +Date: Tue Jul 10 09:02:57 2007 -0500 + + include/configs/[A-I]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 1fe80d79c5c4e52d3410a7ab4b8515da095cdab3 +Author: Jon Loeliger +Date: Mon Jul 9 22:08:34 2007 -0500 + + Finally retire cmd_confdefs.h and CONFIG_BOOTP_MASK! + + All of the choices for CONFIG_BOOTP_ are now documented in + the README file. You must now individually select exactly + the set that you want using a series of + #define CONFIG_BOOTP_ + statements in the board port config files now. + + Signed-off-by: Jon Loeliger + +commit d3b8c1a743dcd31625c99e6a44590f207eb00028 +Author: Jon Loeliger +Date: Mon Jul 9 21:57:31 2007 -0500 + + include/configs/[m-z]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 2fd90ce575b02d189cbf443c85309bcd001aa393 +Author: Jon Loeliger +Date: Mon Jul 9 21:48:26 2007 -0500 + + include/configs/[a-m]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 37d4bb70586659dedef1658ce1bed071be098aec +Author: Jon Loeliger +Date: Mon Jul 9 21:38:02 2007 -0500 + + include/configs/[T-Z]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 18225e8dd1950bd6dbf35011e436db7f474c187d +Author: Jon Loeliger +Date: Mon Jul 9 21:31:24 2007 -0500 + + include/configs/[P-S]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 7be044e4ea644b0ef1c486dadc1a4c2665b4374d +Author: Jon Loeliger +Date: Mon Jul 9 21:24:19 2007 -0500 + + include/configs/[H-N]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 5d2ebe1b3ef0055c661bb1a0d252bf252380069f +Author: Jon Loeliger +Date: Mon Jul 9 21:16:53 2007 -0500 + + include/configs/[A-G]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit f55f7f8d83f36021ab1f0e3d738f5d8c8083a7e3 +Author: Jon Loeliger +Date: Mon Jul 9 19:12:30 2007 -0500 + + Retire CONFIG_COMMANDS finally. + Strip old CFG_CMD_* symbols out. + + Signed-off-by: Jon Loeliger + +commit b5501f7d720fed99ab0b42c83f5dea52868ce007 +Author: Jon Loeliger +Date: Mon Jul 9 19:10:03 2007 -0500 + + Update README.* to reference new CONFIG_CMD_* names now. + + Signed-off-by: Jon Loeliger + +commit 4431283c7e6d54ae180d466e51bf2d97471a0ad9 +Author: Jon Loeliger +Date: Mon Jul 9 19:06:00 2007 -0500 + + cpu/m*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 3a1ed1e1f922c419bb71f7df4949d783ade369fa +Author: Jon Loeliger +Date: Mon Jul 9 18:57:22 2007 -0500 + + cpu/[7a-ln-z]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit ab3abcbabd840928fb1eb5122118ca466b5e5013 +Author: Jon Loeliger +Date: Mon Jul 9 18:45:16 2007 -0500 + + board/[q-z]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 3fe00109a5f12de55b6e25b1f98dfc24bc9090c9 +Author: Jon Loeliger +Date: Mon Jul 9 18:38:39 2007 -0500 + + board/[m-p]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit c508a4cefd8a953fc64957650506a035e6e3d9d1 +Author: Jon Loeliger +Date: Mon Jul 9 18:31:28 2007 -0500 + + board/[f-l]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit b9307262f8a9f3b5c9e15a6067eadc17407146f6 +Author: Jon Loeliger +Date: Mon Jul 9 18:24:55 2007 -0500 + + board/[d-e]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit fcec2eb93e126400009729328e797f12bc94f1fd +Author: Jon Loeliger +Date: Mon Jul 9 18:19:09 2007 -0500 + + board/[A-Za-c]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit a593814f2be0c9cdc3133cd550b167b8a988328f +Author: Jon Loeliger +Date: Mon Jul 9 18:10:50 2007 -0500 + + rtc/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 67350568f9d46e66c21829f3513b3db0caeb948b +Author: Jon Loeliger +Date: Mon Jul 9 18:05:38 2007 -0500 + + lib_{arm,avr32,blackfin,generic,i386}/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 7def6b34f910f08d7ef0a14646da067719237ca2 +Author: Jon Loeliger +Date: Mon Jul 9 18:02:11 2007 -0500 + + lib_{m68k,microblaze,mips,ppc}/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit dd60d1223b99a88a7216f3e041fe40634ad4c2bb +Author: Jon Loeliger +Date: Mon Jul 9 17:56:50 2007 -0500 + + fs/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit c91898bbc505aff3e12a807af88e76da18efb7ee +Author: Jon Loeliger +Date: Mon Jul 9 17:46:09 2007 -0500 + + tools/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 643d1ab23960950b52e0a2803c2d3ea4c558fa01 +Author: Jon Loeliger +Date: Mon Jul 9 17:45:14 2007 -0500 + + net/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit cb51c0bf88f95a1bca68324b0126f8eed8b43273 +Author: Jon Loeliger +Date: Mon Jul 9 17:39:42 2007 -0500 + + drivers/[n-z]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 07d38a17e964aec4c7827f0ee9a583bc8cc1ad6b +Author: Jon Loeliger +Date: Mon Jul 9 17:30:01 2007 -0500 + + drivers/[a-m]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit cde5c64d17cf4834aa7b5c373f288bc7dad27b29 +Author: Jon Loeliger +Date: Mon Jul 9 17:22:37 2007 -0500 + + disk/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 639221c76c88215bd55af83ad174fc30d1940f8f +Author: Jon Loeliger +Date: Mon Jul 9 17:15:49 2007 -0500 + + include/: Remove obsolete references to CONFIG_COMMANDS + Mostly removed from comments here. + + Signed-off-by: Jon Loeliger + +commit 4ef218f6fdf8d747f4589da5252b004e7d2c2876 +Author: Wolfgang Denk +Date: Tue Jul 10 00:01:28 2007 +0200 + + Coding style cleanup; update CHANGELOG. + + Signed-off-by: Wolfgang Denk + +commit c3517f919d0f61650cf3027fd4faf0f631142f6c +Author: Jon Loeliger +Date: Sun Jul 8 18:10:08 2007 -0500 + + common/* non-cmd*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit fd9bcaa35be64fe41a4223fdb6ecdbad52470b39 +Author: Jon Loeliger +Date: Sun Jul 8 18:05:39 2007 -0500 + + common/cmd_[p-x]*: Remove obsolete references to CONFIG_COMMANDS. + + Signed-off-by: Jon Loeliger + +commit c76fe47425afc7d5d670ff0539823c85d65d9c42 +Author: Jon Loeliger +Date: Sun Jul 8 18:02:23 2007 -0500 + + common/cmd_[i-n]*: Remove obsolete references to CONFIG_COMMANDS. + + Signed-off-by: Jon Loeliger + +commit baa26db4113679b80970ff447d91cc10217742a6 +Author: Jon Loeliger +Date: Sun Jul 8 17:51:39 2007 -0500 + + common/cmd_[af]*: Remove obsolete references to CONFIG_COMMANDS. + + Signed-off-by: Jon Loeliger + +commit af075ee96e52dda7b6bca6c937588aeaaec5f2cd +Author: Jon Loeliger +Date: Sun Jul 8 17:02:01 2007 -0500 + + Clear up confusion over the CMD_POST and POST_DIAG mess. + + For some reason, CONFIG_POST permeated as CONFIG_CMD_POST_DIAG + when it really means just CONFIG_CMD_DIAG. There is no CMD_POST. + Clear this mess up some. + + Signed-off-by: Jon Loeliger + +commit b3631487105a57ab7cbadfc26efbaf9676275018 +Author: Jon Loeliger +Date: Sun Jul 8 15:45:08 2007 -0500 + + Remove references to the old cmd_confdefs.h include file. + + Signed-off-by: Jon Loeliger + +commit a22d4da95e20049b4daa1c2a022f61e8a72f2fb6 +Author: Jon Loeliger +Date: Sun Jul 8 15:42:59 2007 -0500 + + include/configs: Catch some CONFIG_CMD_* conversion stragglers. + + Use new CONFIG_CMD_* in lwmon5.h board config file. + Fix CONFIG_CMD_* typo braindamage in omap1510inn.h + + Signed-off-by: Jon Loeliger + +commit a5562901661bd428f7e5feb333f796372cb81019 +Author: Jon Loeliger +Date: Sun Jul 8 15:31:57 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various [TUVWZYZ]* named board config files. + + Signed-off-by: Jon Loeliger + +commit fe7f782d5b8c64a0195c68c31a0a11d4f641355e +Author: Jon Loeliger +Date: Sun Jul 8 15:02:44 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various S* named board config files. + + Signed-off-by: Jon Loeliger + +commit e9a0f8f15c11f337967aa0600ad6e8af33037f50 +Author: Jon Loeliger +Date: Sun Jul 8 15:12:40 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various R* named board config files. + + Signed-off-by: Jon Loeliger + +commit 12aa9fd23d724bd6ab88e1baa0db35133a27303f +Author: Jon Loeliger +Date: Sun Jul 8 14:55:07 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various Q* named board config files. + + Signed-off-by: Jon Loeliger + +commit acf0269779422f3e147d2ddfb499c9f6ff10ad5e +Author: Jon Loeliger +Date: Sun Jul 8 14:49:44 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various P* named board config files. + + Signed-off-by: Jon Loeliger + +commit e18a1061a8630cb67995fdf99afd3fb50d1b187d +Author: Jon Loeliger +Date: Sun Jul 8 14:21:43 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various [NO]* named board config files. + + Signed-off-by: Jon Loeliger + +commit 8353e139bfad9059c54f5b2421f1a3090e15a2e2 +Author: Jon Loeliger +Date: Sun Jul 8 14:14:17 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various M* named board config files. + + Signed-off-by: Jon Loeliger + +commit 348f258f24253433e4a2302a0bbceb6740a67246 +Author: Jon Loeliger +Date: Sun Jul 8 13:46:18 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various [IJKL]* named board config files. + + Signed-off-by: Jon Loeliger + +commit 6c4f4da9bfc9f9403f54fce678ed0364b7c86a6a +Author: Jon Loeliger +Date: Sun Jul 8 10:09:35 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various H* named board config files. + + Signed-off-by: Jon Loeliger + +commit 60a0876b5106b34220e459c208bbf648073306c0 +Author: Jon Loeliger +Date: Sat Jul 7 21:04:26 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various F* and G* named board config files. + + Signed-off-by: Jon Loeliger + +commit dcaa71562826a2466e894c868d132509dcda8444 +Author: Jon Loeliger +Date: Sat Jul 7 20:56:05 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various E* named board config files. + + Signed-off-by: Jon Loeliger + +commit 3c3227f3c737502311b25b72084573901cbbf17d +Author: Jon Loeliger +Date: Sat Jul 7 20:40:43 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various D* named board config files. + + Signed-off-by: Jon Loeliger + +commit 49cf7e8ee7ef943fdfe866ce28410b0bfbf6a26c +Author: Jon Loeliger +Date: Thu Jul 5 19:52:35 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various C* named board config files. + + Signed-off-by: Jon Loeliger + +commit de8b2a6e33298dcdb10bdda48db25e53c3089eba +Author: Jon Loeliger +Date: Thu Jul 5 19:32:07 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various B* named board config files. + + Signed-off-by: Jon Loeliger + +commit 498ff9a228485bd4b9f23d066bada268f9add1dd +Author: Jon Loeliger +Date: Thu Jul 5 19:13:52 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various A* named board config files. + + Since ADS860.h includes "board/fads/fads.h" with ramifications + on the CONFIG_COMMAND treatment, it too has to be adjusted to + exclude already configured commands in this same commit. + + Signed-off-by: Jon Loeliger + +commit 6b0a174a1e6f55e1f5a1fbb223cdad7645a4646e +Author: Stefan Roese +Date: Fri Jul 6 09:45:47 2007 +0200 + + Fix problem with get/setdcr commands introduced by cfg patches + + Signed-off-by: Stefan Roese + +commit f1152f8c28db4a22087c21c618a3f7baa48e9a4f +Author: Wolfgang Denk +Date: Fri Jul 6 02:50:19 2007 +0200 + + Code cleanup and default config update for STC GP3 SSA board. + + Signed-off-by: Wolfgang Denk + +commit e4dbe1b215f5c6c462e76909d240bd96472b84de +Author: Wolfgang Denk +Date: Thu Jul 5 17:56:27 2007 +0200 + + Fixing some typos etc. introduced mainly by cfg patches. + + Signed-off-by: Wolfgang Denk + +commit b6b4684546809f89c8bac72863ca49b5fd8ac0cd +Author: Wolfgang Denk +Date: Thu Jul 5 11:12:16 2007 +0200 + + Minor coding style cleanup. Update CHANGELOG. + commit dca3b3d6d6396b67e5e84af53452164923c73443 Author: Jon Loeliger Date: Wed Jul 4 22:33:46 2007 -0500 @@ -198,6 +1025,14 @@ Date: Wed Jul 4 22:30:06 2007 -0500 Signed-off-by: Jon Loeliger +commit b44896215a09c60fa40cae906f7ed207bbc2c492 +Author: Sergei Poselenov +Date: Thu Jul 5 08:17:37 2007 +0200 + + Merged POST framework with the current TOT. + + Signed-off-by: Sergei Poselenov + commit b24629fa377214d63bb40d1360e354b6d3e4af56 Author: Jon Loeliger Date: Wed Jun 13 13:23:15 2007 -0500 @@ -232,6 +1067,28 @@ Date: Wed Jun 13 13:21:37 2007 -0500 Signed-off-by: Jon Loeliger +commit f780b83316d9af1f61d71cc88b1917b387b9b995 +Author: Niklaus Giger +Date: Wed Jun 27 18:11:38 2007 +0200 + + resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX + + Signed-off-by: Niklaus Giger + +commit 04e6c38b766eaa2f3287561563c9e215e0c3a0d4 +Author: Stefan Roese +Date: Wed Jul 4 10:06:30 2007 +0200 + + ppc4xx: Update lwmon5 board + + - Add optional ECC generation routine to preserve existing + RAM values. This is needed for the Linux log-buffer support + - Add optional DDR2 setup with CL=4 + - GPIO50 not used anymore + - Lime register setup added + + Signed-off-by: Stefan Roese + commit 6810a34677dbc446334f5e451f1682426dd33b49 Author: Grant Likely Date: Tue Jul 3 00:17:28 2007 -0600 @@ -440,14 +1297,6 @@ Date: Tue Jul 3 00:32:53 2007 -0600 Signed-off-by: Grant Likely -commit f1152f8c28db4a22087c21c618a3f7baa48e9a4f -Author: Wolfgang Denk -Date: Fri Jul 6 02:50:19 2007 +0200 - - Code cleanup and default config update for STC GP3 SSA board. - - Signed-off-by: Wolfgang Denk - commit 52b8704d0245e589f86d462e9ec25aeb7ecbbbdd Author: Wolfgang Denk Date: Wed Jul 4 00:43:53 2007 +0200 @@ -456,14 +1305,6 @@ Date: Wed Jul 4 00:43:53 2007 +0200 Signed-off-by: Wolfgang Denk -commit b44896215a09c60fa40cae906f7ed207bbc2c492 -Author: Sergei Poselenov -Date: Thu Jul 5 08:17:37 2007 +0200 - - Merged POST framework with the current TOT. - - Signed-off-by: Sergei Poselenov - commit 78e0cf2de7be7f1eaeeb622eb61fd50e4d5e205c Author: Wolfgang Denk Date: Wed Jul 4 00:38:38 2007 +0200 @@ -478,14 +1319,6 @@ Date: Mon Jun 11 19:03:44 2007 -0500 Signed-off-by: Jon Loeliger -commit f780b83316d9af1f61d71cc88b1917b387b9b995 -Author: Niklaus Giger -Date: Wed Jun 27 18:11:38 2007 +0200 - - resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX - - Signed-off-by: Niklaus Giger - commit 602ad3b33d9ceef83dbab46be68646d645d637ee Author: Jon Loeliger Date: Mon Jun 11 19:03:39 2007 -0500 @@ -494,20 +1327,6 @@ Date: Mon Jun 11 19:03:39 2007 -0500 Signed-off-by: Jon Loeliger -commit 04e6c38b766eaa2f3287561563c9e215e0c3a0d4 -Author: Stefan Roese -Date: Wed Jul 4 10:06:30 2007 +0200 - - ppc4xx: Update lwmon5 board - - - Add optional ECC generation routine to preserve existing - RAM values. This is needed for the Linux log-buffer support - - Add optional DDR2 setup with CL=4 - - GPIO50 not used anymore - - Lime register setup added - - Signed-off-by: Stefan Roese - commit 72a074cec68e5bad60d63206c050974e08afd804 Author: Jon Loeliger Date: Mon Jun 11 19:03:34 2007 -0500 @@ -1875,7 +2694,7 @@ Date: Sat May 5 08:12:30 2007 +0200 5xxx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2017,7 +2836,7 @@ Date: Sat May 5 08:12:30 2007 +0200 5xxx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2148,7 +2967,7 @@ Date: Mon Apr 30 13:59:50 2007 -0500 Fix memory initialization on MPC8349E-mITX Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. - This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary + This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into @@ -2305,7 +3124,7 @@ Date: Mon Feb 12 13:34:55 2007 -0600 85xx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2614,7 +3433,7 @@ Date: Fri Apr 20 14:12:26 2007 -0500 mpc86xx; Write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2667,7 +3486,7 @@ Date: Thu Apr 19 23:14:39 2007 -0400 What was suppose to be a stack variable was declared as a pointer, overwriting random memory. - Also moved the libfdt.a requirement into the main Makefile. That is + Also moved the libfdt.a requirement into the main Makefile. That is The U-Boot Way. commit d21686263574e95cb3e9e9b0496f968b1b897fdb @@ -3262,7 +4081,7 @@ Date: Sat Mar 31 12:22:10 2007 -0400 Add a flattened device tree (fdt) command (1 of 2) The fdt command uses David Gibson's libfdt library to manipulate as well - as print the flattened device tree. This patch is the new command, + as print the flattened device tree. This patch is the new command, the second part is the modifications to the existing code. commit 3af0d587d93e0be5f96e1b30fa41e662f8b0803e @@ -3963,7 +4782,7 @@ Date: Tue Feb 13 10:41:42 2007 -0600 mpc83xx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, this patch + and some have both. To support all of these device trees, this patch updates ftp_cpu_setup() to write the MAC address to mac-address if it exists. This function already updates local-mac-address. @@ -4186,7 +5005,7 @@ Date: Wed Dec 6 21:23:55 2006 -0500 mpc83xx: Put the version (and magic) after the HRCW. - Put the version (and magic) after the HRCW. This puts it in a fixed + Put the version (and magic) after the HRCW. This puts it in a fixed location in flash, not at the start of flash but as close as we can get. Signed-off-by: Jerry Van Baren @@ -4480,7 +5299,7 @@ Date: Tue Feb 20 09:05:31 2007 +0100 [PATCH 7_9] Replace ace_readw_ace_writeb functions with macros - Register read/write does not need to be wrapped in a full function. The + Register read/write does not need to be wrapped in a full function. The patch replaces them with macros. Signed-off-by: Grant Likely @@ -4783,7 +5602,7 @@ commit fdef388758506765d4d6a7155c8f1584c63ff581 Author: roy zang Date: Mon Jan 22 13:19:21 2007 +0800 - use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP + use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP The patch by Heiko Schocher on Jan, 19, 2007 fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support mpc7448hpc2 board. @@ -5471,7 +6290,7 @@ Date: Mon Nov 27 17:04:06 2006 +0100 [PATCH] Allow CONFIG_OF_FLAT_TREE to boot a non-arch/powerpc kernel This patch allows an arch/ppc kernel to be booted by just passing 1 or 2 - arguments to bootm. It removes the getenv("disable_of") test that used + arguments to bootm. It removes the getenv("disable_of") test that used to be used for this purpose. Signed-off-by: Grant Likely @@ -6047,7 +6866,7 @@ Date: Thu Nov 2 19:08:55 2006 +0800 Gigabit Ethernet ports,E0 and E1. It uses a single Management interface to manage the two physical connection devices (PHYs). Each Ethernet port has its own statistics monitor that tracks and reports key interface - statistics. Each port supports a 256-entry hash table for address + statistics. Each port supports a 256-entry hash table for address filtering. In addition, each port is bridged to the Switch Fabric through a 2-Kbyte transmit FIFO and a 4-Kbyte Receive FIFO. @@ -6093,7 +6912,7 @@ commit 87c4db09699c6b89176b31004afcb83eb1585d47 Author: roy zang Date: Thu Nov 2 18:59:15 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. mpc7448hpc2 board support high level code:tsi108 init + mpc7448hpc2. Signed-off-by: Alexandre Bounine @@ -6103,7 +6922,7 @@ commit 27801b8ab11c61b577e45742a515bb3b23b80241 Author: roy zang Date: Thu Nov 2 18:57:21 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. Make ,config.mk and link file for the mpc7448hpc2 board. Signed-off-by: Alexandre Bounine @@ -6113,7 +6932,7 @@ commit c6411c0c3bbc79f9ba8aef58296a42d8f9d8a0a6 Author: roy zang Date: Thu Nov 2 18:55:04 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The mpc7448hpc2 board support header file. Signed-off-by: Alexandre Bounine @@ -6123,7 +6942,7 @@ commit 625bb5ddb50b243f931262ca8c46956409471917 Author: roy zang Date: Thu Nov 2 18:52:21 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The mpc7448hpc2 board support low level assemble language init code. Signed-off-by: Alexandre Bounine @@ -6348,7 +7167,7 @@ Date: Tue Oct 24 23:47:37 2006 -0500 If a Multi-Image file contains a third image we try to use it as a device tree. The device tree image is assumed to be uncompressed in the - image file. We automatically allocate space for the device tree in memory + image file. We automatically allocate space for the device tree in memory and provide an 8k pad to allow more than a reasonable amount of growth. Additionally, a device tree that was contained in flash will now automatically diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 8c18d0f4e21..4a31d323039 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -1017,7 +1017,7 @@ static int short_mem_test(void) */ for (i = 0; i < NUMMEMTESTS; i++) { for (j = 0; j < NUMMEMWORDS; j++) { -//printf("bank enabled base:%x\n", &membase[j]); + /*printf("bank enabled base:%x\n", &membase[j]);*/ membase[j] = test[i][j]; ppcDcbf((unsigned long)&(membase[j])); } diff --git a/drivers/tsec.c b/drivers/tsec.c index 1399d076891..60bef9af394 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -899,36 +899,36 @@ static void tsec_halt(struct eth_device *dev) } struct phy_info phy_info_M88E1149S = { - 0x1410ca, - "Marvell 88E1149S", - 4, - (struct phy_cmd[]){ /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {0x1d, 0x1f, NULL}, - {0x1e, 0x200c, NULL}, - {0x1d, 0x5, NULL}, - {0x1e, 0x0, NULL}, - {0x1e, 0x100, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, - &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + 0x1410ca, + "Marvell 88E1149S", + 4, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ @@ -1351,7 +1351,7 @@ struct phy_info *phy_info[] = { &phy_info_M88E1011S, &phy_info_M88E1111S, &phy_info_M88E1145, - &phy_info_M88E1149S, + &phy_info_M88E1149S, &phy_info_dm9161, &phy_info_lxt971, &phy_info_VSC8244, diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h index d4ee14c837f..77938b140da 100644 --- a/include/configs/ADNPESC1.h +++ b/include/configs/ADNPESC1.h @@ -563,8 +563,6 @@ #define CONFIG_POST CFG_POST_RTC #define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) - - /* * BOOTP options */ @@ -585,7 +583,7 @@ #undef CONFIG_CMD_DOC #undef CONFIG_CMD_DTT #undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_ELF #undef CONFIG_CMD_FAT #undef CONFIG_CMD_FDC #undef CONFIG_CMD_FDOS @@ -610,7 +608,6 @@ #undef CONFIG_CMD_DATE #endif - /*------------------------------------------------------------------------ * KGDB *----------------------------------------------------------------------*/ @@ -657,7 +654,6 @@ #undef CFG_LOAD_ADDR /* force error break */ #endif - /* MEM test area */ #if (CFG_SDRAM_SIZE != 0) diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 6dcfbc15d4c..f6495e4841a 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -92,7 +92,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EEPROM #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/Adder.h b/include/configs/Adder.h index 5e076dcc41c..4304ecca7de 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -67,10 +67,10 @@ */ #include -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index d8d09838eb4..c11e9c911d3 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -84,10 +84,10 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_SCSI +#define CONFIG_CMD_SCSI #define CONFIG_CMD_IDE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_FDC +#define CONFIG_CMD_DATE +#define CONFIG_CMD_FDC #define CONFIG_CMD_ELF diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 844bdc5d883..5c2bfc991f5 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -192,7 +192,7 @@ #ifdef CONFIG_BC3450_USB #define CONFIG_CMD_USB #endif - + #ifdef CONFIG_PCI #define CONFIG_CMD_PCI #endif diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index 0e082b318bb..ae32f6b14ac 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -72,7 +72,7 @@ #include #define CONFIG_CMD_IRQ -#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EEPROM #undef CONFIG_CMD_NET diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 8d04104e58a..48e29a20876 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -148,18 +148,18 @@ */ #include -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_PCI +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 #define CONFIG_DOS_PARTITION diff --git a/include/configs/CU824.h b/include/configs/CU824.h index f7fdd2d6ee8..68e816a7443 100644 --- a/include/configs/CU824.h +++ b/include/configs/CU824.h @@ -73,7 +73,7 @@ */ #include -#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_BEDBUG #define CONFIG_CMD_DHCP #define CONFIG_CMD_PCI #define CONFIG_CMD_NFS -- cgit v1.3.1 From 5072188acabde3178fac7f5a597150e6e74fd40c Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 6 Jul 2007 08:33:33 +0800 Subject: This is a framebuffer driver for ATI video card, can work for PCI9200, X300, X700, X800 ATI video cards. Signed-off-by: Zhang Wei Signed-off-by: Jason Jin --- drivers/Makefile | 2 +- drivers/ati_ids.h | 212 +++++ drivers/ati_radeon_fb.c | 486 ++++++++++++ drivers/ati_radeon_fb.h | 293 +++++++ include/radeon.h | 1986 +++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 2978 insertions(+), 1 deletion(-) create mode 100644 drivers/ati_ids.h create mode 100644 drivers/ati_radeon_fb.c create mode 100644 drivers/ati_radeon_fb.h create mode 100644 include/radeon.h (limited to 'drivers') diff --git a/drivers/Makefile b/drivers/Makefile index fa2e86fd20f..881153ac9dd 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -52,7 +52,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \ ks8695eth.o \ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ rpx_pcmcia.o \ - fsl_i2c.o fsl_pci_init.o + fsl_i2c.o fsl_pci_init.o ati_radeon_fb.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/ati_ids.h b/drivers/ati_ids.h new file mode 100644 index 00000000000..35fe505735f --- /dev/null +++ b/drivers/ati_ids.h @@ -0,0 +1,212 @@ +/* + * ATI PCI IDs from XFree86, kept here to make sync'ing with + * XFree much simpler. Currently, this list is only used by + * radeonfb + */ + +#define PCI_CHIP_RV380_3150 0x3150 +#define PCI_CHIP_RV380_3151 0x3151 +#define PCI_CHIP_RV380_3152 0x3152 +#define PCI_CHIP_RV380_3153 0x3153 +#define PCI_CHIP_RV380_3154 0x3154 +#define PCI_CHIP_RV380_3156 0x3156 +#define PCI_CHIP_RV380_3E50 0x3E50 +#define PCI_CHIP_RV380_3E51 0x3E51 +#define PCI_CHIP_RV380_3E52 0x3E52 +#define PCI_CHIP_RV380_3E53 0x3E53 +#define PCI_CHIP_RV380_3E54 0x3E54 +#define PCI_CHIP_RV380_3E56 0x3E56 +#define PCI_CHIP_RS100_4136 0x4136 +#define PCI_CHIP_RS200_4137 0x4137 +#define PCI_CHIP_R300_AD 0x4144 +#define PCI_CHIP_R300_AE 0x4145 +#define PCI_CHIP_R300_AF 0x4146 +#define PCI_CHIP_R300_AG 0x4147 +#define PCI_CHIP_R350_AH 0x4148 +#define PCI_CHIP_R350_AI 0x4149 +#define PCI_CHIP_R350_AJ 0x414A +#define PCI_CHIP_R350_AK 0x414B +#define PCI_CHIP_RV350_AP 0x4150 +#define PCI_CHIP_RV350_AQ 0x4151 +#define PCI_CHIP_RV360_AR 0x4152 +#define PCI_CHIP_RV350_AS 0x4153 +#define PCI_CHIP_RV350_AT 0x4154 +#define PCI_CHIP_RV350_AV 0x4156 +#define PCI_CHIP_MACH32 0x4158 +#define PCI_CHIP_RS250_4237 0x4237 +#define PCI_CHIP_R200_BB 0x4242 +#define PCI_CHIP_R200_BC 0x4243 +#define PCI_CHIP_RS100_4336 0x4336 +#define PCI_CHIP_RS200_4337 0x4337 +#define PCI_CHIP_MACH64CT 0x4354 +#define PCI_CHIP_MACH64CX 0x4358 +#define PCI_CHIP_RS250_4437 0x4437 +#define PCI_CHIP_MACH64ET 0x4554 +#define PCI_CHIP_MACH64GB 0x4742 +#define PCI_CHIP_MACH64GD 0x4744 +#define PCI_CHIP_MACH64GI 0x4749 +#define PCI_CHIP_MACH64GL 0x474C +#define PCI_CHIP_MACH64GM 0x474D +#define PCI_CHIP_MACH64GN 0x474E +#define PCI_CHIP_MACH64GO 0x474F +#define PCI_CHIP_MACH64GP 0x4750 +#define PCI_CHIP_MACH64GQ 0x4751 +#define PCI_CHIP_MACH64GR 0x4752 +#define PCI_CHIP_MACH64GS 0x4753 +#define PCI_CHIP_MACH64GT 0x4754 +#define PCI_CHIP_MACH64GU 0x4755 +#define PCI_CHIP_MACH64GV 0x4756 +#define PCI_CHIP_MACH64GW 0x4757 +#define PCI_CHIP_MACH64GX 0x4758 +#define PCI_CHIP_MACH64GY 0x4759 +#define PCI_CHIP_MACH64GZ 0x475A +#define PCI_CHIP_RV250_Id 0x4964 +#define PCI_CHIP_RV250_Ie 0x4965 +#define PCI_CHIP_RV250_If 0x4966 +#define PCI_CHIP_RV250_Ig 0x4967 +#define PCI_CHIP_R420_JH 0x4A48 +#define PCI_CHIP_R420_JI 0x4A49 +#define PCI_CHIP_R420_JJ 0x4A4A +#define PCI_CHIP_R420_JK 0x4A4B +#define PCI_CHIP_R420_JL 0x4A4C +#define PCI_CHIP_R420_JM 0x4A4D +#define PCI_CHIP_R420_JN 0x4A4E +#define PCI_CHIP_R420_JP 0x4A50 +#define PCI_CHIP_MACH64LB 0x4C42 +#define PCI_CHIP_MACH64LD 0x4C44 +#define PCI_CHIP_RAGE128LE 0x4C45 +#define PCI_CHIP_RAGE128LF 0x4C46 +#define PCI_CHIP_MACH64LG 0x4C47 +#define PCI_CHIP_MACH64LI 0x4C49 +#define PCI_CHIP_MACH64LM 0x4C4D +#define PCI_CHIP_MACH64LN 0x4C4E +#define PCI_CHIP_MACH64LP 0x4C50 +#define PCI_CHIP_MACH64LQ 0x4C51 +#define PCI_CHIP_MACH64LR 0x4C52 +#define PCI_CHIP_MACH64LS 0x4C53 +#define PCI_CHIP_MACH64LT 0x4C54 +#define PCI_CHIP_RADEON_LW 0x4C57 +#define PCI_CHIP_RADEON_LX 0x4C58 +#define PCI_CHIP_RADEON_LY 0x4C59 +#define PCI_CHIP_RADEON_LZ 0x4C5A +#define PCI_CHIP_RV250_Ld 0x4C64 +#define PCI_CHIP_RV250_Le 0x4C65 +#define PCI_CHIP_RV250_Lf 0x4C66 +#define PCI_CHIP_RV250_Lg 0x4C67 +#define PCI_CHIP_RV250_Ln 0x4C6E +#define PCI_CHIP_RAGE128MF 0x4D46 +#define PCI_CHIP_RAGE128ML 0x4D4C +#define PCI_CHIP_R300_ND 0x4E44 +#define PCI_CHIP_R300_NE 0x4E45 +#define PCI_CHIP_R300_NF 0x4E46 +#define PCI_CHIP_R300_NG 0x4E47 +#define PCI_CHIP_R350_NH 0x4E48 +#define PCI_CHIP_R350_NI 0x4E49 +#define PCI_CHIP_R360_NJ 0x4E4A +#define PCI_CHIP_R350_NK 0x4E4B +#define PCI_CHIP_RV350_NP 0x4E50 +#define PCI_CHIP_RV350_NQ 0x4E51 +#define PCI_CHIP_RV350_NR 0x4E52 +#define PCI_CHIP_RV350_NS 0x4E53 +#define PCI_CHIP_RV350_NT 0x4E54 +#define PCI_CHIP_RV350_NV 0x4E56 +#define PCI_CHIP_RAGE128PA 0x5041 +#define PCI_CHIP_RAGE128PB 0x5042 +#define PCI_CHIP_RAGE128PC 0x5043 +#define PCI_CHIP_RAGE128PD 0x5044 +#define PCI_CHIP_RAGE128PE 0x5045 +#define PCI_CHIP_RAGE128PF 0x5046 +#define PCI_CHIP_RAGE128PG 0x5047 +#define PCI_CHIP_RAGE128PH 0x5048 +#define PCI_CHIP_RAGE128PI 0x5049 +#define PCI_CHIP_RAGE128PJ 0x504A +#define PCI_CHIP_RAGE128PK 0x504B +#define PCI_CHIP_RAGE128PL 0x504C +#define PCI_CHIP_RAGE128PM 0x504D +#define PCI_CHIP_RAGE128PN 0x504E +#define PCI_CHIP_RAGE128PO 0x504F +#define PCI_CHIP_RAGE128PP 0x5050 +#define PCI_CHIP_RAGE128PQ 0x5051 +#define PCI_CHIP_RAGE128PR 0x5052 +#define PCI_CHIP_RAGE128PS 0x5053 +#define PCI_CHIP_RAGE128PT 0x5054 +#define PCI_CHIP_RAGE128PU 0x5055 +#define PCI_CHIP_RAGE128PV 0x5056 +#define PCI_CHIP_RAGE128PW 0x5057 +#define PCI_CHIP_RAGE128PX 0x5058 +#define PCI_CHIP_RADEON_QD 0x5144 +#define PCI_CHIP_RADEON_QE 0x5145 +#define PCI_CHIP_RADEON_QF 0x5146 +#define PCI_CHIP_RADEON_QG 0x5147 +#define PCI_CHIP_R200_QH 0x5148 +#define PCI_CHIP_R200_QI 0x5149 +#define PCI_CHIP_R200_QJ 0x514A +#define PCI_CHIP_R200_QK 0x514B +#define PCI_CHIP_R200_QL 0x514C +#define PCI_CHIP_R200_QM 0x514D +#define PCI_CHIP_R200_QN 0x514E +#define PCI_CHIP_R200_QO 0x514F +#define PCI_CHIP_RV200_QW 0x5157 +#define PCI_CHIP_RV200_QX 0x5158 +#define PCI_CHIP_RV100_QY 0x5159 +#define PCI_CHIP_RV100_QZ 0x515A +#define PCI_CHIP_RN50 0x515E +#define PCI_CHIP_RAGE128RE 0x5245 +#define PCI_CHIP_RAGE128RF 0x5246 +#define PCI_CHIP_RAGE128RG 0x5247 +#define PCI_CHIP_RAGE128RK 0x524B +#define PCI_CHIP_RAGE128RL 0x524C +#define PCI_CHIP_RAGE128SE 0x5345 +#define PCI_CHIP_RAGE128SF 0x5346 +#define PCI_CHIP_RAGE128SG 0x5347 +#define PCI_CHIP_RAGE128SH 0x5348 +#define PCI_CHIP_RAGE128SK 0x534B +#define PCI_CHIP_RAGE128SL 0x534C +#define PCI_CHIP_RAGE128SM 0x534D +#define PCI_CHIP_RAGE128SN 0x534E +#define PCI_CHIP_RAGE128TF 0x5446 +#define PCI_CHIP_RAGE128TL 0x544C +#define PCI_CHIP_RAGE128TR 0x5452 +#define PCI_CHIP_RAGE128TS 0x5453 +#define PCI_CHIP_RAGE128TT 0x5454 +#define PCI_CHIP_RAGE128TU 0x5455 +#define PCI_CHIP_RV370_5460 0x5460 +#define PCI_CHIP_RV370_5461 0x5461 +#define PCI_CHIP_RV370_5462 0x5462 +#define PCI_CHIP_RV370_5463 0x5463 +#define PCI_CHIP_RV370_5464 0x5464 +#define PCI_CHIP_RV370_5465 0x5465 +#define PCI_CHIP_RV370_5466 0x5466 +#define PCI_CHIP_RV370_5467 0x5467 +#define PCI_CHIP_R423_UH 0x5548 +#define PCI_CHIP_R423_UI 0x5549 +#define PCI_CHIP_R423_UJ 0x554A +#define PCI_CHIP_R423_UK 0x554B +#define PCI_CHIP_R423_UQ 0x5551 +#define PCI_CHIP_R423_UR 0x5552 +#define PCI_CHIP_R423_UT 0x5554 +#define PCI_CHIP_MACH64VT 0x5654 +#define PCI_CHIP_MACH64VU 0x5655 +#define PCI_CHIP_MACH64VV 0x5656 +#define PCI_CHIP_RS300_5834 0x5834 +#define PCI_CHIP_RS300_5835 0x5835 +#define PCI_CHIP_RS300_5836 0x5836 +#define PCI_CHIP_RS300_5837 0x5837 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV370_5B61 0x5B61 +#define PCI_CHIP_RV370_5B62 0x5B62 +#define PCI_CHIP_RV370_5B63 0x5B63 +#define PCI_CHIP_RV370_5B64 0x5B64 +#define PCI_CHIP_RV370_5B65 0x5B65 +#define PCI_CHIP_RV370_5B66 0x5B66 +#define PCI_CHIP_RV370_5B67 0x5B67 +#define PCI_CHIP_RV280_5960 0x5960 +#define PCI_CHIP_RV280_5961 0x5961 +#define PCI_CHIP_RV280_5962 0x5962 +#define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5C61 0x5C61 +#define PCI_CHIP_RV280_5C63 0x5C63 +#define PCI_CHIP_R423_5D57 0x5D57 +#define PCI_CHIP_RS350_7834 0x7834 +#define PCI_CHIP_RS350_7835 0x7835 + diff --git a/drivers/ati_radeon_fb.c b/drivers/ati_radeon_fb.c new file mode 100644 index 00000000000..e15140ab38d --- /dev/null +++ b/drivers/ati_radeon_fb.c @@ -0,0 +1,486 @@ +/* + * ATI Radeon Video card Framebuffer driver. + * + * Copyright 2007 Freescale Semiconductor, Inc. + * Zhang Wei + * Jason Jin + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Some codes of this file is partly ported from Linux kernel + * ATI video framebuffer driver. + * + * Now the driver is tested on below ATI chips: + * 9200 + * X300 + * X700 + * + */ + +#include + +#ifdef CONFIG_ATI_RADEON_FB + +#include +#include +#include +#include +#include +#include +#include + +#include +#include "ati_ids.h" +#include "ati_radeon_fb.h" + +#undef DEBUG + +#ifdef DEBUG +#define DPRINT(x...) printf(x) +#else +#define DPRINT(x...) do{}while(0) +#endif + +#ifndef min_t +#define min_t(type,x,y) \ + ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) +#endif + +#define MAX_MAPPED_VRAM (2048*2048*4) +#define MIN_MAPPED_VRAM (1024*768*1) + +/*#define PCI_VENDOR_ID_ATI*/ +#define PCI_CHIP_RV280_5960 0x5960 +#define PCI_CHIP_RV280_5961 0x5961 +#define PCI_CHIP_RV280_5962 0x5962 +#define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV380_5657 0x5657 +#define PCI_CHIP_R420_554d 0x554d + +static struct pci_device_id ati_radeon_pci_ids[] = { + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d}, + {0, 0} +}; + +static u16 ati_radeon_id_family_table[][2] = { + {PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380}, + {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380}, + {PCI_CHIP_R420_554d, CHIP_FAMILY_R420}, + {0, 0} +}; + +u16 get_radeon_id_family(u16 device) +{ + int i; + for (i=0; ati_radeon_id_family_table[0][i]; i+=2) + if (ati_radeon_id_family_table[0][i] == device) + return ati_radeon_id_family_table[0][i + 1]; + return 0; +} + +struct radeonfb_info *rinfo; + +static void radeon_identify_vram(struct radeonfb_info *rinfo) +{ + u32 tmp; + + /* framebuffer size */ + if ((rinfo->family == CHIP_FAMILY_RS100) || + (rinfo->family == CHIP_FAMILY_RS200) || + (rinfo->family == CHIP_FAMILY_RS300)) { + u32 tom = INREG(NB_TOM); + tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); + + radeon_fifo_wait(6); + OUTREG(MC_FB_LOCATION, tom); + OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); + OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); + OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); + + /* This is supposed to fix the crtc2 noise problem. */ + OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); + + if ((rinfo->family == CHIP_FAMILY_RS100) || + (rinfo->family == CHIP_FAMILY_RS200)) { + /* This is to workaround the asic bug for RMX, some versions + of BIOS dosen't have this register initialized correctly. + */ + OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, + ~CRTC_H_CUTOFF_ACTIVE_EN); + } + } else { + tmp = INREG(CONFIG_MEMSIZE); + } + + /* mem size is bits [28:0], mask off the rest */ + rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; + + /* + * Hack to get around some busted production M6's + * reporting no ram + */ + if (rinfo->video_ram == 0) { + switch (rinfo->pdev.device) { + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: + rinfo->video_ram = 8192 * 1024; + break; + default: + break; + } + } + + /* + * Now try to identify VRAM type + */ + if ((rinfo->family >= CHIP_FAMILY_R300) || + (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) + rinfo->vram_ddr = 1; + else + rinfo->vram_ddr = 0; + + tmp = INREG(MEM_CNTL); + if (IS_R300_VARIANT(rinfo)) { + tmp &= R300_MEM_NUM_CHANNELS_MASK; + switch (tmp) { + case 0: rinfo->vram_width = 64; break; + case 1: rinfo->vram_width = 128; break; + case 2: rinfo->vram_width = 256; break; + default: rinfo->vram_width = 128; break; + } + } else if ((rinfo->family == CHIP_FAMILY_RV100) || + (rinfo->family == CHIP_FAMILY_RS100) || + (rinfo->family == CHIP_FAMILY_RS200)){ + if (tmp & RV100_MEM_HALF_MODE) + rinfo->vram_width = 32; + else + rinfo->vram_width = 64; + } else { + if (tmp & MEM_NUM_CHANNELS_MASK) + rinfo->vram_width = 128; + else + rinfo->vram_width = 64; + } + + /* This may not be correct, as some cards can have half of channel disabled + * ToDo: identify these cases + */ + + DPRINT("radeonfb: Found %ldk of %s %d bits wide videoram\n", + rinfo->video_ram / 1024, + rinfo->vram_ddr ? "DDR" : "SDRAM", + rinfo->vram_width); + +} + +static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) +{ + int i; + + radeon_fifo_wait(20); + +#if 0 + /* Workaround from XFree */ + if (rinfo->is_mobility) { + /* A temporal workaround for the occational blanking on certain laptop + * panels. This appears to related to the PLL divider registers + * (fail to lock?). It occurs even when all dividers are the same + * with their old settings. In this case we really don't need to + * fiddle with PLL registers. By doing this we can avoid the blanking + * problem with some panels. + */ + if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && + (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & + (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { + /* We still have to force a switch to selected PPLL div thanks to + * an XFree86 driver bug which will switch it away in some cases + * even when using UseFDev */ + OUTREGP(CLOCK_CNTL_INDEX, + mode->clk_cntl_index & PPLL_DIV_SEL_MASK, + ~PPLL_DIV_SEL_MASK); + radeon_pll_errata_after_index(rinfo); + radeon_pll_errata_after_data(rinfo); + return; + } + } +#endif + if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return; + + /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ + OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); + + /* Reset PPLL & enable atomic update */ + OUTPLLP(PPLL_CNTL, + PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, + ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); + + /* Switch to selected PPLL divider */ + OUTREGP(CLOCK_CNTL_INDEX, + mode->clk_cntl_index & PPLL_DIV_SEL_MASK, + ~PPLL_DIV_SEL_MASK); + + /* Set PPLL ref. div */ + if (rinfo->family == CHIP_FAMILY_R300 || + rinfo->family == CHIP_FAMILY_RS300 || + rinfo->family == CHIP_FAMILY_R350 || + rinfo->family == CHIP_FAMILY_RV350) { + if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { + /* When restoring console mode, use saved PPLL_REF_DIV + * setting. + */ + OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); + } else { + /* R300 uses ref_div_acc field as real ref divider */ + OUTPLLP(PPLL_REF_DIV, + (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), + ~R300_PPLL_REF_DIV_ACC_MASK); + } + } else + OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); + + /* Set PPLL divider 3 & post divider*/ + OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); + OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); + + /* Write update */ + while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) + ; + OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); + + /* Wait read update complete */ + /* FIXME: Certain revisions of R300 can't recover here. Not sure of + the cause yet, but this workaround will mask the problem for now. + Other chips usually will pass at the very first test, so the + workaround shouldn't have any effect on them. */ + for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) + ; + + OUTPLL(HTOTAL_CNTL, 0); + + /* Clear reset & atomic update */ + OUTPLLP(PPLL_CNTL, 0, + ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); + + /* We may want some locking ... oh well */ + udelay(5000); + + /* Switch back VCLK source to PPLL */ + OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); +} + +typedef struct { + u16 reg; + u32 val; +} reg_val; + + +/* these common regs are cleared before mode setting so they do not + * interfere with anything + */ +static reg_val common_regs[] = { + { OVR_CLR, 0 }, + { OVR_WID_LEFT_RIGHT, 0 }, + { OVR_WID_TOP_BOTTOM, 0 }, + { OV0_SCALE_CNTL, 0 }, + { SUBPIC_CNTL, 0 }, + { VIPH_CONTROL, 0 }, + { I2C_CNTL_1, 0 }, + { GEN_INT_CNTL, 0 }, + { CAP0_TRIG_CNTL, 0 }, + { CAP1_TRIG_CNTL, 0 }, +}; + + +void radeon_setmode(void) +{ + int i; + struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); + + mode->crtc_gen_cntl = 0x03000200; + mode->crtc_ext_cntl = 0x00008048; + mode->dac_cntl = 0xff002100; + mode->crtc_h_total_disp = 0x4f0063; + mode->crtc_h_sync_strt_wid = 0x8c02a2; + mode->crtc_v_total_disp = 0x01df020c; + mode->crtc_v_sync_strt_wid = 0x8201ea; + mode->crtc_pitch = 0x00500050; + + OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); + OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, + ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); + OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); + OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); + OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); + OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); + OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); + OUTREG(CRTC_OFFSET, 0); + OUTREG(CRTC_OFFSET_CNTL, 0); + OUTREG(CRTC_PITCH, mode->crtc_pitch); + + mode->clk_cntl_index = 0x300; + mode->ppll_ref_div = 0xc; + mode->ppll_div_3 = 0x00030059; + + radeon_write_pll_regs(rinfo, mode); +} + +int radeon_probe(struct radeonfb_info *rinfo) +{ + pci_dev_t pdev; + u16 did; + + pdev = pci_find_devices(ati_radeon_pci_ids, 0); + + if (pdev != -1) { + pci_read_config_word(pdev, PCI_DEVICE_ID, &did); + printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n", + PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff, + (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); + + strcpy(rinfo->name, "ATI Radeon"); + rinfo->pdev.vendor = PCI_VENDOR_ID_ATI; + rinfo->pdev.device = did; + rinfo->family = get_radeon_id_family(rinfo->pdev.device); + pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, + &rinfo->fb_base_phys); + pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2, + &rinfo->mmio_base_phys); + rinfo->fb_base_phys &= 0xfffff000; + rinfo->mmio_base_phys &= ~0x04; + + rinfo->mmio_base = (void *)rinfo->mmio_base_phys; + DPRINT("rinfo->mmio_base = 0x%x\n",rinfo->mmio_base); + rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; + DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base); + /* PostBIOS with x86 emulater */ + BootVideoCardBIOS(pdev, NULL, 0); + + /* + * Check for errata + * (These will be added in the future for the chipfamily + * R300, RV200, RS200, RV100, RS100.) + */ + + /* Get VRAM size and type */ + radeon_identify_vram(rinfo); + + rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, + rinfo->video_ram); + rinfo->fb_base = (void *)rinfo->fb_base_phys; + + DPRINT("Radeon: framebuffer base phy address 0x%08x," \ + "MMIO base phy address 0x%08x," \ + "framebuffer local base 0x%08x.\n ", + rinfo->fb_base_phys, rinfo->mmio_base_phys, + rinfo->fb_local_base); + + return 0; + } + return -1; +} + +/* + * The Graphic Device + */ +GraphicDevice ctfb; + +#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ +#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ +#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ +#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ + +void *video_hw_init(void) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + int i; + u32 *vm; + + rinfo = malloc(sizeof(struct radeonfb_info)); + + if(radeon_probe(rinfo)) { + printf("No radeon video card found!\n"); + return NULL; + } + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", 640, + 480, 16, (1000 / 1000), + (2000 / 1000)); + printf ("%s\n", pGD->modeIdent); + + pGD->winSizeX = 640; + pGD->winSizeY = 480; + pGD->plnSizeX = 640; + pGD->plnSizeY = 480; + + pGD->gdfBytesPP = 1; + pGD->gdfIndex = GDF__8BIT_INDEX; + + pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS; + pGD->pciBase = rinfo->fb_base_phys; + pGD->frameAdrs = rinfo->fb_base_phys; + pGD->memSize = 64 * 1024 * 1024; + + /* Cursor Start Address */ + pGD->dprBase = + (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + rinfo->fb_base_phys; + if ((pGD->dprBase & 0x0fff) != 0) { + /* allign it */ + pGD->dprBase &= 0xfffff000; + pGD->dprBase += 0x00001000; + } + DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, + PATTERN_ADR); + pGD->vprBase = rinfo->fb_base_phys; /* Dummy */ + pGD->cprBase = rinfo->fb_base_phys; /* Dummy */ + /* set up Hardware */ + + /* Clear video memory */ + i = pGD->memSize / 4; + vm = (unsigned int *) pGD->pciBase; + while (i--) + *vm++ = 0; + /*SetDrawingEngine (bits_per_pixel);*/ + + radeon_setmode(); + + return ((void *) pGD); +} + +void video_set_lut (unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + OUTREG(PALETTE_INDEX, index); + OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b); +} +#endif diff --git a/drivers/ati_radeon_fb.h b/drivers/ati_radeon_fb.h new file mode 100644 index 00000000000..1c3ba64cfb0 --- /dev/null +++ b/drivers/ati_radeon_fb.h @@ -0,0 +1,293 @@ +#ifndef __ATI_RADEON_FB_H +#define __ATI_RADEON_FB_H + +/*************************************************************** + * Most of the definitions here are adapted right from XFree86 * + ***************************************************************/ + + +/* + * Chip families. Must fit in the low 16 bits of a long word + */ +enum radeon_family { + CHIP_FAMILY_UNKNOW, + CHIP_FAMILY_LEGACY, + CHIP_FAMILY_RADEON, + CHIP_FAMILY_RV100, + CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ + CHIP_FAMILY_RV200, + CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), + RS250 (IGP 7000) */ + CHIP_FAMILY_R200, + CHIP_FAMILY_RV250, + CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ + CHIP_FAMILY_RV280, + CHIP_FAMILY_R300, + CHIP_FAMILY_R350, + CHIP_FAMILY_RV350, + CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ + CHIP_FAMILY_R420, /* R420/R423/M18 */ + CHIP_FAMILY_LAST, +}; + +#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \ + ((rinfo)->family == CHIP_FAMILY_RV200) || \ + ((rinfo)->family == CHIP_FAMILY_RS100) || \ + ((rinfo)->family == CHIP_FAMILY_RS200) || \ + ((rinfo)->family == CHIP_FAMILY_RV250) || \ + ((rinfo)->family == CHIP_FAMILY_RV280) || \ + ((rinfo)->family == CHIP_FAMILY_RS300)) + + +#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ + ((rinfo)->family == CHIP_FAMILY_RV350) || \ + ((rinfo)->family == CHIP_FAMILY_R350) || \ + ((rinfo)->family == CHIP_FAMILY_RV380) || \ + ((rinfo)->family == CHIP_FAMILY_R420)) + + +struct radeonfb_info { + char name[20]; + + struct pci_device_id pdev; + u16 family; + + u32 fb_base_phys; + u32 mmio_base_phys; + + void *mmio_base; + void *fb_base; + + u32 video_ram; + u32 mapped_vram; + int vram_width; + int vram_ddr; + + u32 fb_local_base; +}; + +#define INREG8(addr) readb((rinfo->mmio_base)+addr) +#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) +#define INREG16(addr) readw((rinfo->mmio_base)+addr) +#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) +#define INREG(addr) readl((rinfo->mmio_base)+addr) +#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) + +static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, + u32 val, u32 mask) +{ + unsigned int tmp; + + tmp = INREG(addr); + tmp &= (mask); + tmp |= (val); + OUTREG(addr, tmp); +} + +#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) + + +/* + * 2D Engine helper routines + */ +static inline void radeon_engine_flush (struct radeonfb_info *rinfo) +{ + int i; + + /* initiate flush */ + OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, + ~RB2D_DC_FLUSH_ALL); + + for (i=0; i < 2000000; i++) { + if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) + return; + udelay(1); + } + printf("radeonfb: Flush Timeout !\n"); +} + + +static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) +{ + int i; + + for (i=0; i<2000000; i++) { + if ((INREG(RBBM_STATUS) & 0x7f) >= entries) + return; + udelay(1); + } + printf("radeonfb: FIFO Timeout !\n"); +} + + +static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) +{ + int i; + + /* ensure FIFO is empty before waiting for idle */ + _radeon_fifo_wait (rinfo, 64); + + for (i=0; i<2000000; i++) { + if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { + radeon_engine_flush (rinfo); + return; + } + udelay(1); + } + printf("radeonfb: Idle Timeout !\n"); +} + + +#define radeon_engine_idle() _radeon_engine_idle(rinfo) +#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) +#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) + +/* + * This structure contains the various registers manipulated by this + * driver for setting or restoring a mode. It's mostly copied from + * XFree's RADEONSaveRec structure. A few chip settings might still be + * tweaked without beeing reflected or saved in these registers though + */ +struct radeon_regs { + /* Common registers */ + u32 ovr_clr; + u32 ovr_wid_left_right; + u32 ovr_wid_top_bottom; + u32 ov0_scale_cntl; + u32 mpp_tb_config; + u32 mpp_gp_config; + u32 subpic_cntl; + u32 viph_control; + u32 i2c_cntl_1; + u32 gen_int_cntl; + u32 cap0_trig_cntl; + u32 cap1_trig_cntl; + u32 bus_cntl; + u32 surface_cntl; + u32 bios_5_scratch; + + /* Other registers to save for VT switches or driver load/unload */ + u32 dp_datatype; + u32 rbbm_soft_reset; + u32 clock_cntl_index; + u32 amcgpio_en_reg; + u32 amcgpio_mask; + + /* Surface/tiling registers */ + u32 surf_lower_bound[8]; + u32 surf_upper_bound[8]; + u32 surf_info[8]; + + /* CRTC registers */ + u32 crtc_gen_cntl; + u32 crtc_ext_cntl; + u32 dac_cntl; + u32 crtc_h_total_disp; + u32 crtc_h_sync_strt_wid; + u32 crtc_v_total_disp; + u32 crtc_v_sync_strt_wid; + u32 crtc_offset; + u32 crtc_offset_cntl; + u32 crtc_pitch; + u32 disp_merge_cntl; + u32 grph_buffer_cntl; + u32 crtc_more_cntl; + + /* CRTC2 registers */ + u32 crtc2_gen_cntl; + u32 dac2_cntl; + u32 disp_output_cntl; + u32 disp_hw_debug; + u32 disp2_merge_cntl; + u32 grph2_buffer_cntl; + u32 crtc2_h_total_disp; + u32 crtc2_h_sync_strt_wid; + u32 crtc2_v_total_disp; + u32 crtc2_v_sync_strt_wid; + u32 crtc2_offset; + u32 crtc2_offset_cntl; + u32 crtc2_pitch; + + /* Flat panel regs */ + u32 fp_crtc_h_total_disp; + u32 fp_crtc_v_total_disp; + u32 fp_gen_cntl; + u32 fp2_gen_cntl; + u32 fp_h_sync_strt_wid; + u32 fp2_h_sync_strt_wid; + u32 fp_horz_stretch; + u32 fp_panel_cntl; + u32 fp_v_sync_strt_wid; + u32 fp2_v_sync_strt_wid; + u32 fp_vert_stretch; + u32 lvds_gen_cntl; + u32 lvds_pll_cntl; + u32 tmds_crc; + u32 tmds_transmitter_cntl; + + /* Computed values for PLL */ + u32 dot_clock_freq; + int feedback_div; + int post_div; + + /* PLL registers */ + u32 ppll_div_3; + u32 ppll_ref_div; + u32 vclk_ecp_cntl; + u32 clk_cntl_index; + + /* Computed values for PLL2 */ + u32 dot_clock_freq_2; + int feedback_div_2; + int post_div_2; + + /* PLL2 registers */ + u32 p2pll_ref_div; + u32 p2pll_div_0; + u32 htotal_cntl2; + + /* Palette */ + int palette_valid; +}; + +static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) +{ + u32 data; + + OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); + //radeon_pll_errata_after_index(rinfo); + data = INREG(CLOCK_CNTL_DATA); + //radeon_pll_errata_after_data(rinfo); + return data; +} + +static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, + u32 val) +{ + + OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); + //radeon_pll_errata_after_index(rinfo); + OUTREG(CLOCK_CNTL_DATA, val); + //radeon_pll_errata_after_data(rinfo); +} + + +static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, + u32 val, u32 mask) +{ + unsigned int tmp; + + tmp = __INPLL(rinfo, index); + tmp &= (mask); + tmp |= (val); + __OUTPLL(rinfo, index, tmp); +} + + +#define INPLL(addr) __INPLL(rinfo, addr) +#define OUTPLL(index, val) __OUTPLL(rinfo, index, val) +#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) + + + +#endif diff --git a/include/radeon.h b/include/radeon.h new file mode 100644 index 00000000000..f4e24a7134b --- /dev/null +++ b/include/radeon.h @@ -0,0 +1,1986 @@ +#ifndef _RADEON_H +#define _RADEON_H + + +#define RADEON_REGSIZE 0x4000 + + +#define MM_INDEX 0x0000 +#define MM_DATA 0x0004 +#define BUS_CNTL 0x0030 +#define HI_STAT 0x004C +#define BUS_CNTL1 0x0034 +#define I2C_CNTL_1 0x0094 +#define CONFIG_CNTL 0x00E0 +#define CONFIG_MEMSIZE 0x00F8 +#define CONFIG_APER_0_BASE 0x0100 +#define CONFIG_APER_1_BASE 0x0104 +#define CONFIG_APER_SIZE 0x0108 +#define CONFIG_REG_1_BASE 0x010C +#define CONFIG_REG_APER_SIZE 0x0110 +#define PAD_AGPINPUT_DELAY 0x0164 +#define PAD_CTLR_STRENGTH 0x0168 +#define PAD_CTLR_UPDATE 0x016C +#define PAD_CTLR_MISC 0x0aa0 +#define AGP_CNTL 0x0174 +#define BM_STATUS 0x0160 +#define CAP0_TRIG_CNTL 0x0950 +#define CAP1_TRIG_CNTL 0x09c0 +#define VIPH_CONTROL 0x0C40 +#define VENDOR_ID 0x0F00 +#define DEVICE_ID 0x0F02 +#define COMMAND 0x0F04 +#define STATUS 0x0F06 +#define REVISION_ID 0x0F08 +#define REGPROG_INF 0x0F09 +#define SUB_CLASS 0x0F0A +#define BASE_CODE 0x0F0B +#define CACHE_LINE 0x0F0C +#define LATENCY 0x0F0D +#define HEADER 0x0F0E +#define BIST 0x0F0F +#define REG_MEM_BASE 0x0F10 +#define REG_IO_BASE 0x0F14 +#define REG_REG_BASE 0x0F18 +#define ADAPTER_ID 0x0F2C +#define BIOS_ROM 0x0F30 +#define CAPABILITIES_PTR 0x0F34 +#define INTERRUPT_LINE 0x0F3C +#define INTERRUPT_PIN 0x0F3D +#define MIN_GRANT 0x0F3E +#define MAX_LATENCY 0x0F3F +#define ADAPTER_ID_W 0x0F4C +#define PMI_CAP_ID 0x0F50 +#define PMI_NXT_CAP_PTR 0x0F51 +#define PMI_PMC_REG 0x0F52 +#define PM_STATUS 0x0F54 +#define PMI_DATA 0x0F57 +#define AGP_CAP_ID 0x0F58 +#define AGP_STATUS 0x0F5C +#define AGP_COMMAND 0x0F60 +#define AIC_CTRL 0x01D0 +#define AIC_STAT 0x01D4 +#define AIC_PT_BASE 0x01D8 +#define AIC_LO_ADDR 0x01DC +#define AIC_HI_ADDR 0x01E0 +#define AIC_TLB_ADDR 0x01E4 +#define AIC_TLB_DATA 0x01E8 +#define DAC_CNTL 0x0058 +#define DAC_CNTL2 0x007c +#define CRTC_GEN_CNTL 0x0050 +#define MEM_CNTL 0x0140 +#define MC_CNTL 0x0140 +#define EXT_MEM_CNTL 0x0144 +#define MC_TIMING_CNTL 0x0144 +#define MC_AGP_LOCATION 0x014C +#define MEM_IO_CNTL_A0 0x0178 +#define MEM_REFRESH_CNTL 0x0178 +#define MEM_INIT_LATENCY_TIMER 0x0154 +#define MC_INIT_GFX_LAT_TIMER 0x0154 +#define MEM_SDRAM_MODE_REG 0x0158 +#define AGP_BASE 0x0170 +#define MEM_IO_CNTL_A1 0x017C +#define MC_READ_CNTL_AB 0x017C +#define MEM_IO_CNTL_B0 0x0180 +#define MC_INIT_MISC_LAT_TIMER 0x0180 +#define MEM_IO_CNTL_B1 0x0184 +#define MC_IOPAD_CNTL 0x0184 +#define MC_DEBUG 0x0188 +#define MC_STATUS 0x0150 +#define MEM_IO_OE_CNTL 0x018C +#define MC_CHIP_IO_OE_CNTL_AB 0x018C +#define MC_FB_LOCATION 0x0148 +//#define MC_FB_LOCATION 0x0188 +#define HOST_PATH_CNTL 0x0130 +#define MEM_VGA_WP_SEL 0x0038 +#define MEM_VGA_RP_SEL 0x003C +#define HDP_DEBUG 0x0138 +#define SW_SEMAPHORE 0x013C +#define CRTC2_GEN_CNTL 0x03f8 +#define CRTC2_DISPLAY_BASE_ADDR 0x033c +#define SURFACE_CNTL 0x0B00 +#define SURFACE0_LOWER_BOUND 0x0B04 +#define SURFACE1_LOWER_BOUND 0x0B14 +#define SURFACE2_LOWER_BOUND 0x0B24 +#define SURFACE3_LOWER_BOUND 0x0B34 +#define SURFACE4_LOWER_BOUND 0x0B44 +#define SURFACE5_LOWER_BOUND 0x0B54 +#define SURFACE6_LOWER_BOUND 0x0B64 +#define SURFACE7_LOWER_BOUND 0x0B74 +#define SURFACE0_UPPER_BOUND 0x0B08 +#define SURFACE1_UPPER_BOUND 0x0B18 +#define SURFACE2_UPPER_BOUND 0x0B28 +#define SURFACE3_UPPER_BOUND 0x0B38 +#define SURFACE4_UPPER_BOUND 0x0B48 +#define SURFACE5_UPPER_BOUND 0x0B58 +#define SURFACE6_UPPER_BOUND 0x0B68 +#define SURFACE7_UPPER_BOUND 0x0B78 +#define SURFACE0_INFO 0x0B0C +#define SURFACE1_INFO 0x0B1C +#define SURFACE2_INFO 0x0B2C +#define SURFACE3_INFO 0x0B3C +#define SURFACE4_INFO 0x0B4C +#define SURFACE5_INFO 0x0B5C +#define SURFACE6_INFO 0x0B6C +#define SURFACE7_INFO 0x0B7C +#define SURFACE_ACCESS_FLAGS 0x0BF8 +#define SURFACE_ACCESS_CLR 0x0BFC +#define GEN_INT_CNTL 0x0040 +#define GEN_INT_STATUS 0x0044 +#define CRTC_EXT_CNTL 0x0054 +#define RB3D_CNTL 0x1C3C +#define WAIT_UNTIL 0x1720 +#define ISYNC_CNTL 0x1724 +#define RBBM_GUICNTL 0x172C +#define RBBM_STATUS 0x0E40 +#define RBBM_STATUS_alt_1 0x1740 +#define RBBM_CNTL 0x00EC +#define RBBM_CNTL_alt_1 0x0E44 +#define RBBM_SOFT_RESET 0x00F0 +#define RBBM_SOFT_RESET_alt_1 0x0E48 +#define NQWAIT_UNTIL 0x0E50 +#define RBBM_DEBUG 0x0E6C +#define RBBM_CMDFIFO_ADDR 0x0E70 +#define RBBM_CMDFIFO_DATAL 0x0E74 +#define RBBM_CMDFIFO_DATAH 0x0E78 +#define RBBM_CMDFIFO_STAT 0x0E7C +#define CRTC_STATUS 0x005C +#define GPIO_VGA_DDC 0x0060 +#define GPIO_DVI_DDC 0x0064 +#define GPIO_MONID 0x0068 +#define GPIO_CRT2_DDC 0x006c +#define PALETTE_INDEX 0x00B0 +#define PALETTE_DATA 0x00B4 +#define PALETTE_30_DATA 0x00B8 +#define CRTC_H_TOTAL_DISP 0x0200 +#define CRTC_H_SYNC_STRT_WID 0x0204 +#define CRTC_V_TOTAL_DISP 0x0208 +#define CRTC_V_SYNC_STRT_WID 0x020C +#define CRTC_VLINE_CRNT_VLINE 0x0210 +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC_DEBUG 0x021C +#define CRTC_OFFSET_RIGHT 0x0220 +#define CRTC_OFFSET 0x0224 +#define CRTC_OFFSET_CNTL 0x0228 +#define CRTC_PITCH 0x022C +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define DISPLAY_BASE_ADDR 0x023C +#define SNAPSHOT_VH_COUNTS 0x0240 +#define SNAPSHOT_F_COUNT 0x0244 +#define N_VIF_COUNT 0x0248 +#define SNAPSHOT_VIF_COUNT 0x024C +#define FP_CRTC_H_TOTAL_DISP 0x0250 +#define FP_CRTC_V_TOTAL_DISP 0x0254 +#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 +#define CRT_CRTC_V_SYNC_STRT_WID 0x025C +#define CUR_OFFSET 0x0260 +#define CUR_HORZ_VERT_POSN 0x0264 +#define CUR_HORZ_VERT_OFF 0x0268 +#define CUR_CLR0 0x026C +#define CUR_CLR1 0x0270 +#define FP_HORZ_VERT_ACTIVE 0x0278 +#define CRTC_MORE_CNTL 0x027C +#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +#define DAC_EXT_CNTL 0x0280 +#define FP_GEN_CNTL 0x0284 +#define FP_HORZ_STRETCH 0x028C +#define FP_VERT_STRETCH 0x0290 +#define FP_H_SYNC_STRT_WID 0x02C4 +#define FP_V_SYNC_STRT_WID 0x02C8 +#define AUX_WINDOW_HORZ_CNTL 0x02D8 +#define AUX_WINDOW_VERT_CNTL 0x02DC +//#define DDA_CONFIG 0x02e0 +//#define DDA_ON_OFF 0x02e4 +#define DVI_I2C_CNTL_1 0x02e4 +#define GRPH_BUFFER_CNTL 0x02F0 +#define GRPH2_BUFFER_CNTL 0x03F0 +#define VGA_BUFFER_CNTL 0x02F4 +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_PIPELINE_CNTL 0x0408 +#define OV0_REG_LOAD_CNTL 0x0410 +#define OV0_SCALE_CNTL 0x0420 +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +#define OV0_P23_V_ACCUM_INIT 0x042C +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +#define OV0_BASE_ADDR 0x043C +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +#define OV0_VID_BUF3_BASE_ADRS 0x044C +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTRL 0x0470 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_SUBMIT_HISTORY 0x0478 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +#define OV0_FOUR_TAP_COEF_0 0x04B0 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +#define OV0_FOUR_TAP_COEF_3 0x04BC +#define OV0_FOUR_TAP_COEF_4 0x04C0 +#define OV0_FLAG_CNTRL 0x04DC +#define OV0_SLICE_CNTL 0x04E0 +#define OV0_VID_KEY_CLR_LOW 0x04E4 +#define OV0_VID_KEY_CLR_HIGH 0x04E8 +#define OV0_GRPH_KEY_CLR_LOW 0x04EC +#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +#define OV0_TEST 0x04F8 +#define SUBPIC_CNTL 0x0540 +#define SUBPIC_DEFCOLCON 0x0544 +#define SUBPIC_Y_X_START 0x054C +#define SUBPIC_Y_X_END 0x0550 +#define SUBPIC_V_INC 0x0554 +#define SUBPIC_H_INC 0x0558 +#define SUBPIC_BUF0_OFFSET 0x055C +#define SUBPIC_BUF1_OFFSET 0x0560 +#define SUBPIC_LC0_OFFSET 0x0564 +#define SUBPIC_LC1_OFFSET 0x0568 +#define SUBPIC_PITCH 0x056C +#define SUBPIC_BTN_HLI_COLCON 0x0570 +#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +#define SUBPIC_PALETTE_INDEX 0x057C +#define SUBPIC_PALETTE_DATA 0x0580 +#define SUBPIC_H_ACCUM_INIT 0x0584 +#define SUBPIC_V_ACCUM_INIT 0x0588 +#define DISP_MISC_CNTL 0x0D00 +#define DAC_MACRO_CNTL 0x0D04 +#define DISP_PWR_MAN 0x0D08 +#define DISP_TEST_DEBUG_CNTL 0x0D10 +#define DISP_HW_DEBUG 0x0D14 +#define DAC_CRC_SIG1 0x0D18 +#define DAC_CRC_SIG2 0x0D1C +#define OV0_LIN_TRANS_A 0x0D20 +#define OV0_LIN_TRANS_B 0x0D24 +#define OV0_LIN_TRANS_C 0x0D28 +#define OV0_LIN_TRANS_D 0x0D2C +#define OV0_LIN_TRANS_E 0x0D30 +#define OV0_LIN_TRANS_F 0x0D34 +#define OV0_GAMMA_0_F 0x0D40 +#define OV0_GAMMA_10_1F 0x0D44 +#define OV0_GAMMA_20_3F 0x0D48 +#define OV0_GAMMA_40_7F 0x0D4C +#define OV0_GAMMA_380_3BF 0x0D50 +#define OV0_GAMMA_3C0_3FF 0x0D54 +#define DISP_MERGE_CNTL 0x0D60 +#define DISP_OUTPUT_CNTL 0x0D64 +#define DISP_LIN_TRANS_GRPH_A 0x0D80 +#define DISP_LIN_TRANS_GRPH_B 0x0D84 +#define DISP_LIN_TRANS_GRPH_C 0x0D88 +#define DISP_LIN_TRANS_GRPH_D 0x0D8C +#define DISP_LIN_TRANS_GRPH_E 0x0D90 +#define DISP_LIN_TRANS_GRPH_F 0x0D94 +#define DISP_LIN_TRANS_VID_A 0x0D98 +#define DISP_LIN_TRANS_VID_B 0x0D9C +#define DISP_LIN_TRANS_VID_C 0x0DA0 +#define DISP_LIN_TRANS_VID_D 0x0DA4 +#define DISP_LIN_TRANS_VID_E 0x0DA8 +#define DISP_LIN_TRANS_VID_F 0x0DAC +#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 +#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 +#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 +#define RMX_HORZ_PHASE 0x0DBC +#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 +#define DAC_BROAD_PULSE 0x0DC4 +#define DAC_SKEW_CLKS 0x0DC8 +#define DAC_INCR 0x0DCC +#define DAC_NEG_SYNC_LEVEL 0x0DD0 +#define DAC_POS_SYNC_LEVEL 0x0DD4 +#define DAC_BLANK_LEVEL 0x0DD8 +#define CLOCK_CNTL_INDEX 0x0008 +#define CLOCK_CNTL_DATA 0x000C +#define CP_RB_CNTL 0x0704 +#define CP_RB_BASE 0x0700 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define SCRATCH_REG0 0x15E0 +#define GUI_SCRATCH_REG0 0x15E0 +#define SCRATCH_REG1 0x15E4 +#define GUI_SCRATCH_REG1 0x15E4 +#define SCRATCH_REG2 0x15E8 +#define GUI_SCRATCH_REG2 0x15E8 +#define SCRATCH_REG3 0x15EC +#define GUI_SCRATCH_REG3 0x15EC +#define SCRATCH_REG4 0x15F0 +#define GUI_SCRATCH_REG4 0x15F0 +#define SCRATCH_REG5 0x15F4 +#define GUI_SCRATCH_REG5 0x15F4 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DP_BRUSH_FRGD_CLR 0x147C +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DST_LINE_START 0x1600 +#define DST_LINE_END 0x1604 +#define SRC_OFFSET 0x15AC +#define SRC_PITCH 0x15B0 +#define SRC_TILE 0x1704 +#define SRC_PITCH_OFFSET 0x1428 +#define SRC_X 0x1414 +#define SRC_Y 0x1418 +#define SRC_X_Y 0x1590 +#define SRC_Y_X 0x1434 +#define DST_Y_X 0x1438 +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_HEIGHT_WIDTH 0x143c +#define DST_OFFSET 0x1404 +#define SRC_CLUT_ADDRESS 0x1780 +#define SRC_CLUT_DATA 0x1784 +#define SRC_CLUT_DATA_RD 0x1788 +#define HOST_DATA0 0x17C0 +#define HOST_DATA1 0x17C4 +#define HOST_DATA2 0x17C8 +#define HOST_DATA3 0x17CC +#define HOST_DATA4 0x17D0 +#define HOST_DATA5 0x17D4 +#define HOST_DATA6 0x17D8 +#define HOST_DATA7 0x17DC +#define HOST_DATA_LAST 0x17E0 +#define DP_SRC_ENDIAN 0x15D4 +#define DP_SRC_FRGD_CLR 0x15D8 +#define DP_SRC_BKGD_CLR 0x15DC +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_BOTTOM 0x164C +#define SRC_SC_RIGHT 0x1654 +#define SRC_SC_BOTTOM 0x165C +#define DP_CNTL 0x16C0 +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 +#define DP_DATATYPE 0x16C4 +#define DP_MIX 0x16C8 +#define DP_WRITE_MSK 0x16CC +#define DP_XOP 0x17F8 +#define CLR_CMP_CLR_SRC 0x15C4 +#define CLR_CMP_CLR_DST 0x15C8 +#define CLR_CMP_CNTL 0x15C0 +#define CLR_CMP_MSK 0x15CC +#define DSTCACHE_MODE 0x1710 +#define DSTCACHE_CTLSTAT 0x1714 +#define DEFAULT_PITCH_OFFSET 0x16E0 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 +#define DEFAULT_SC_TOP_LEFT 0x16EC +#define SRC_PITCH_OFFSET 0x1428 +#define DST_PITCH_OFFSET 0x142C +#define DP_GUI_MASTER_CNTL 0x146C +#define SC_TOP_LEFT 0x16EC +#define SC_BOTTOM_RIGHT 0x16F0 +#define SRC_SC_BOTTOM_RIGHT 0x16F4 +#define RB2D_DSTCACHE_MODE 0x3428 +#define RB2D_DSTCACHE_CTLSTAT 0x342C +#define LVDS_GEN_CNTL 0x02d0 +#define LVDS_PLL_CNTL 0x02d4 +#define FP2_GEN_CNTL 0x0288 +#define TMDS_CNTL 0x0294 +#define TMDS_CRC 0x02a0 +#define TMDS_TRANSMITTER_CNTL 0x02a4 +#define MPP_TB_CONFIG 0x01c0 +#define PAMAC0_DLY_CNTL 0x0a94 +#define PAMAC1_DLY_CNTL 0x0a98 +#define PAMAC2_DLY_CNTL 0x0a9c +#define FW_CNTL 0x0118 +#define FCP_CNTL 0x0910 +#define VGA_DDA_ON_OFF 0x02ec +#define TV_MASTER_CNTL 0x0800 + +//#define BASE_CODE 0x0f0b +#define BIOS_0_SCRATCH 0x0010 +#define BIOS_1_SCRATCH 0x0014 +#define BIOS_2_SCRATCH 0x0018 +#define BIOS_3_SCRATCH 0x001c +#define BIOS_4_SCRATCH 0x0020 +#define BIOS_5_SCRATCH 0x0024 +#define BIOS_6_SCRATCH 0x0028 +#define BIOS_7_SCRATCH 0x002c + +#define HDP_SOFT_RESET (1 << 26) + +#define TV_DAC_CNTL 0x088c +#define GPIOPAD_MASK 0x0198 +#define GPIOPAD_A 0x019c +#define GPIOPAD_EN 0x01a0 +#define GPIOPAD_Y 0x01a4 +#define ZV_LCDPAD_MASK 0x01a8 +#define ZV_LCDPAD_A 0x01ac +#define ZV_LCDPAD_EN 0x01b0 +#define ZV_LCDPAD_Y 0x01b4 + +/* PLL Registers */ +#define CLK_PIN_CNTL 0x0001 +#define PPLL_CNTL 0x0002 +#define PPLL_REF_DIV 0x0003 +#define PPLL_DIV_0 0x0004 +#define PPLL_DIV_1 0x0005 +#define PPLL_DIV_2 0x0006 +#define PPLL_DIV_3 0x0007 +#define VCLK_ECP_CNTL 0x0008 +#define HTOTAL_CNTL 0x0009 +#define M_SPLL_REF_FB_DIV 0x000a +#define AGP_PLL_CNTL 0x000b +#define SPLL_CNTL 0x000c +#define SCLK_CNTL 0x000d +#define MPLL_CNTL 0x000e +#define MDLL_CKO 0x000f +#define MDLL_RDCKA 0x0010 +#define MCLK_CNTL 0x0012 +#define AGP_PLL_CNTL 0x000b +#define PLL_TEST_CNTL 0x0013 +#define CLK_PWRMGT_CNTL 0x0014 +#define PLL_PWRMGT_CNTL 0x0015 +#define MCLK_MISC 0x001f +#define P2PLL_CNTL 0x002a +#define P2PLL_REF_DIV 0x002b +#define PIXCLKS_CNTL 0x002d +#define SCLK_MORE_CNTL 0x0035 + +/* MCLK_CNTL bit constants */ +#define FORCEON_MCLKA (1 << 16) +#define FORCEON_MCLKB (1 << 17) +#define FORCEON_YCLKA (1 << 18) +#define FORCEON_YCLKB (1 << 19) +#define FORCEON_MC (1 << 20) +#define FORCEON_AIC (1 << 21) + +/* SCLK_CNTL bit constants */ +#define DYN_STOP_LAT_MASK 0x00007ff8 +#define CP_MAX_DYN_STOP_LAT 0x0008 +#define SCLK_FORCEON_MASK 0xffff8000 + +/* SCLK_MORE_CNTL bit constants */ +#define SCLK_MORE_FORCEON 0x0700 + +/* BUS_CNTL bit constants */ +#define BUS_DBL_RESYNC 0x00000001 +#define BUS_MSTR_RESET 0x00000002 +#define BUS_FLUSH_BUF 0x00000004 +#define BUS_STOP_REQ_DIS 0x00000008 +#define BUS_ROTATION_DIS 0x00000010 +#define BUS_MASTER_DIS 0x00000040 +#define BUS_ROM_WRT_EN 0x00000080 +#define BUS_DIS_ROM 0x00001000 +#define BUS_PCI_READ_RETRY_EN 0x00002000 +#define BUS_AGP_AD_STEPPING_EN 0x00004000 +#define BUS_PCI_WRT_RETRY_EN 0x00008000 +#define BUS_MSTR_RD_MULT 0x00100000 +#define BUS_MSTR_RD_LINE 0x00200000 +#define BUS_SUSPEND 0x00400000 +#define LAT_16X 0x00800000 +#define BUS_RD_DISCARD_EN 0x01000000 +#define BUS_RD_ABORT_EN 0x02000000 +#define BUS_MSTR_WS 0x04000000 +#define BUS_PARKING_DIS 0x08000000 +#define BUS_MSTR_DISCONNECT_EN 0x10000000 +#define BUS_WRT_BURST 0x20000000 +#define BUS_READ_BURST 0x40000000 +#define BUS_RDY_READ_DLY 0x80000000 + +/* PIXCLKS_CNTL */ +#define PIX2CLK_SRC_SEL_MASK 0x03 +#define PIX2CLK_SRC_SEL_CPUCLK 0x00 +#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 +#define PIX2CLK_SRC_SEL_BYTECLK 0x02 +#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +#define PIX2CLK_ALWAYS_ONb (1<<6) +#define PIX2CLK_DAC_ALWAYS_ONb (1<<7) +#define PIXCLK_TV_SRC_SEL (1 << 8) +#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) + + +/* CLOCK_CNTL_INDEX bit constants */ +#define PLL_WR_EN 0x00000080 + +/* CONFIG_CNTL bit constants */ +#define CFG_VGA_RAM_EN 0x00000100 +#define CFG_ATI_REV_ID_MASK (0xf << 16) +#define CFG_ATI_REV_A11 (0 << 16) +#define CFG_ATI_REV_A12 (1 << 16) +#define CFG_ATI_REV_A13 (2 << 16) + +/* CRTC_EXT_CNTL bit constants */ +#define VGA_ATI_LINEAR 0x00000008 +#define VGA_128KAP_PAGING 0x00000010 +#define XCRT_CNT_EN (1 << 6) +#define CRTC_HSYNC_DIS (1 << 8) +#define CRTC_VSYNC_DIS (1 << 9) +#define CRTC_DISPLAY_DIS (1 << 10) +#define CRTC_CRT_ON (1 << 15) + + +/* DSTCACHE_CTLSTAT bit constants */ +#define RB2D_DC_FLUSH (3 << 0) +#define RB2D_DC_FLUSH_ALL 0xf +#define RB2D_DC_BUSY (1 << 31) + + +/* CRTC_GEN_CNTL bit constants */ +#define CRTC_DBL_SCAN_EN 0x00000001 +#define CRTC_CUR_EN 0x00010000 +#define CRTC_INTERLACE_EN (1 << 1) +#define CRTC_BYPASS_LUT_EN (1 << 14) +#define CRTC_EXT_DISP_EN (1 << 24) +#define CRTC_EN (1 << 25) +#define CRTC_DISP_REQ_EN_B (1 << 26) + +/* CRTC_STATUS bit constants */ +#define CRTC_VBLANK 0x00000001 + +/* CRTC2_GEN_CNTL bit constants */ +#define CRT2_ON (1 << 7) +#define CRTC2_DISPLAY_DIS (1 << 23) +#define CRTC2_EN (1 << 25) +#define CRTC2_DISP_REQ_EN_B (1 << 26) + +/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ +#define CUR_LOCK 0x80000000 + +/* GPIO bit constants */ +#define GPIO_A_0 (1 << 0) +#define GPIO_A_1 (1 << 1) +#define GPIO_Y_0 (1 << 8) +#define GPIO_Y_1 (1 << 9) +#define GPIO_EN_0 (1 << 16) +#define GPIO_EN_1 (1 << 17) +#define GPIO_MASK_0 (1 << 24) +#define GPIO_MASK_1 (1 << 25) +#define VGA_DDC_DATA_OUTPUT GPIO_A_0 +#define VGA_DDC_CLK_OUTPUT GPIO_A_1 +#define VGA_DDC_DATA_INPUT GPIO_Y_0 +#define VGA_DDC_CLK_INPUT GPIO_Y_1 +#define VGA_DDC_DATA_OUT_EN GPIO_EN_0 +#define VGA_DDC_CLK_OUT_EN GPIO_EN_1 + + +/* FP bit constants */ +#define FP_CRTC_H_TOTAL_MASK 0x000003ff +#define FP_CRTC_H_DISP_MASK 0x01ff0000 +#define FP_CRTC_V_TOTAL_MASK 0x00000fff +#define FP_CRTC_V_DISP_MASK 0x0fff0000 +#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +#define FP_H_SYNC_WID_MASK 0x003f0000 +#define FP_V_SYNC_STRT_MASK 0x00000fff +#define FP_V_SYNC_WID_MASK 0x001f0000 +#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +#define FP_CRTC_H_DISP_SHIFT 0x00000010 +#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +#define FP_CRTC_V_DISP_SHIFT 0x00000010 +#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +#define FP_H_SYNC_WID_SHIFT 0x00000010 +#define FP_V_SYNC_STRT_SHIFT 0x00000000 +#define FP_V_SYNC_WID_SHIFT 0x00000010 + +/* FP_GEN_CNTL bit constants */ +#define FP_FPON (1 << 0) +#define FP_TMDS_EN (1 << 2) +#define FP_PANEL_FORMAT (1 << 3) +#define FP_EN_TMDS (1 << 7) +#define FP_DETECT_SENSE (1 << 8) +#define R200_FP_SOURCE_SEL_MASK (3 << 10) +#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) +#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) +#define R200_FP_SOURCE_SEL_RMX (2 << 10) +#define R200_FP_SOURCE_SEL_TRANS (3 << 10) +#define FP_SEL_CRTC1 (0 << 13) +#define FP_SEL_CRTC2 (1 << 13) +#define FP_USE_VGA_HSYNC (1 << 14) +#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +#define FP_CRTC_USE_SHADOW_VEND (1 << 18) +#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +#define FP_DFP_SYNC_SEL (1 << 21) +#define FP_CRTC_LOCK_8DOT (1 << 22) +#define FP_CRT_SYNC_SEL (1 << 23) +#define FP_USE_SHADOW_EN (1 << 24) +#define FP_CRT_SYNC_ALT (1 << 26) + +/* FP2_GEN_CNTL bit constants */ +#define FP2_BLANK_EN (1 << 1) +#define FP2_ON (1 << 2) +#define FP2_PANEL_FORMAT (1 << 3) +#define FP2_SOURCE_SEL_MASK (3 << 10) +#define FP2_SOURCE_SEL_CRTC2 (1 << 10) +#define FP2_SRC_SEL_MASK (3 << 13) +#define FP2_SRC_SEL_CRTC2 (1 << 13) +#define FP2_FP_POL (1 << 16) +#define FP2_LP_POL (1 << 17) +#define FP2_SCK_POL (1 << 18) +#define FP2_LCD_CNTL_MASK (7 << 19) +#define FP2_PAD_FLOP_EN (1 << 22) +#define FP2_CRC_EN (1 << 23) +#define FP2_CRC_READ_EN (1 << 24) +#define FP2_DV0_EN (1 << 25) +#define FP2_DV0_RATE_SEL_SDR (1 << 26) + + +/* LVDS_GEN_CNTL bit constants */ +#define LVDS_ON (1 << 0) +#define LVDS_DISPLAY_DIS (1 << 1) +#define LVDS_PANEL_TYPE (1 << 2) +#define LVDS_PANEL_FORMAT (1 << 3) +#define LVDS_EN (1 << 7) +#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 +#define LVDS_BL_MOD_LEVEL_SHIFT 8 +#define LVDS_BL_MOD_EN (1 << 16) +#define LVDS_DIGON (1 << 18) +#define LVDS_BLON (1 << 19) +#define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_STATE_MASK \ + (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) + +/* LVDS_PLL_CNTL bit constatns */ +#define HSYNC_DELAY_SHIFT 0x1c +#define HSYNC_DELAY_MASK (0xf << 0x1c) + +/* TMDS_TRANSMITTER_CNTL bit constants */ +#define TMDS_PLL_EN (1 << 0) +#define TMDS_PLLRST (1 << 1) +#define TMDS_RAN_PAT_RST (1 << 7) +#define TMDS_ICHCSEL (1 << 28) + +/* FP_HORZ_STRETCH bit constants */ +#define HORZ_STRETCH_RATIO_MASK 0xffff +#define HORZ_STRETCH_RATIO_MAX 4096 +#define HORZ_PANEL_SIZE (0x1ff << 16) +#define HORZ_PANEL_SHIFT 16 +#define HORZ_STRETCH_PIXREP (0 << 25) +#define HORZ_STRETCH_BLEND (1 << 26) +#define HORZ_STRETCH_ENABLE (1 << 25) +#define HORZ_AUTO_RATIO (1 << 27) +#define HORZ_FP_LOOP_STRETCH (0x7 << 28) +#define HORZ_AUTO_RATIO_INC (1 << 31) + + +/* FP_VERT_STRETCH bit constants */ +#define VERT_STRETCH_RATIO_MASK 0xfff +#define VERT_STRETCH_RATIO_MAX 4096 +#define VERT_PANEL_SIZE (0xfff << 12) +#define VERT_PANEL_SHIFT 12 +#define VERT_STRETCH_LINREP (0 << 26) +#define VERT_STRETCH_BLEND (1 << 26) +#define VERT_STRETCH_ENABLE (1 << 25) +#define VERT_AUTO_RATIO_EN (1 << 27) +#define VERT_FP_LOOP_STRETCH (0x7 << 28) +#define VERT_STRETCH_RESERVED 0xf1000000 + +/* DAC_CNTL bit constants */ +#define DAC_8BIT_EN 0x00000100 +#define DAC_4BPP_PIX_ORDER 0x00000200 +#define DAC_CRC_EN 0x00080000 +#define DAC_MASK_ALL (0xff << 24) +#define DAC_PDWN (1 << 15) +#define DAC_EXPAND_MODE (1 << 14) +#define DAC_VGA_ADR_EN (1 << 13) +#define DAC_RANGE_CNTL (3 << 0) +#define DAC_RANGE_CNTL_MASK 0x03 +#define DAC_BLANKING (1 << 2) +#define DAC_CMP_EN (1 << 3) +#define DAC_CMP_OUTPUT (1 << 7) + +/* DAC_CNTL2 bit constants */ +#define DAC2_EXPAND_MODE (1 << 14) +#define DAC2_CMP_EN (1 << 7) +#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) + +/* DAC_EXT_CNTL bit constants */ +#define DAC_FORCE_BLANK_OFF_EN (1 << 4) +#define DAC_FORCE_DATA_EN (1 << 5) +#define DAC_FORCE_DATA_SEL_MASK (3 << 6) +#define DAC_FORCE_DATA_MASK 0x0003ff00 +#define DAC_FORCE_DATA_SHIFT 8 + +/* GEN_RESET_CNTL bit constants */ +#define SOFT_RESET_GUI 0x00000001 +#define SOFT_RESET_VCLK 0x00000100 +#define SOFT_RESET_PCLK 0x00000200 +#define SOFT_RESET_ECP 0x00000400 +#define SOFT_RESET_DISPENG_XCLK 0x00000800 + +/* MEM_CNTL bit constants */ +#define MEM_CTLR_STATUS_IDLE 0x00000000 +#define MEM_CTLR_STATUS_BUSY 0x00100000 +#define MEM_SEQNCR_STATUS_IDLE 0x00000000 +#define MEM_SEQNCR_STATUS_BUSY 0x00200000 +#define MEM_ARBITER_STATUS_IDLE 0x00000000 +#define MEM_ARBITER_STATUS_BUSY 0x00400000 +#define MEM_REQ_UNLOCK 0x00000000 +#define MEM_REQ_LOCK 0x00800000 +#define MEM_NUM_CHANNELS_MASK 0x00000001 +#define MEM_USE_B_CH_ONLY 0x00000002 +#define RV100_MEM_HALF_MODE 0x00000008 +#define R300_MEM_NUM_CHANNELS_MASK 0x00000003 +#define R300_MEM_USE_CD_CH_ONLY 0x00000004 + + +/* RBBM_SOFT_RESET bit constants */ +#define SOFT_RESET_CP (1 << 0) +#define SOFT_RESET_HI (1 << 1) +#define SOFT_RESET_SE (1 << 2) +#define SOFT_RESET_RE (1 << 3) +#define SOFT_RESET_PP (1 << 4) +#define SOFT_RESET_E2 (1 << 5) +#define SOFT_RESET_RB (1 << 6) +#define SOFT_RESET_HDP (1 << 7) + +/* SURFACE_CNTL bit consants */ +#define SURF_TRANSLATION_DIS (1 << 8) +#define NONSURF_AP0_SWP_16BPP (1 << 20) +#define NONSURF_AP0_SWP_32BPP (1 << 21) +#define NONSURF_AP1_SWP_16BPP (1 << 22) +#define NONSURF_AP1_SWP_32BPP (1 << 23) + +/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ +#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) + +/* MM_INDEX bit constants */ +#define MM_APER 0x80000000 + +/* CLR_CMP_CNTL bit constants */ +#define COMPARE_SRC_FALSE 0x00000000 +#define COMPARE_SRC_TRUE 0x00000001 +#define COMPARE_SRC_NOT_EQUAL 0x00000004 +#define COMPARE_SRC_EQUAL 0x00000005 +#define COMPARE_SRC_EQUAL_FLIP 0x00000007 +#define COMPARE_DST_FALSE 0x00000000 +#define COMPARE_DST_TRUE 0x00000100 +#define COMPARE_DST_NOT_EQUAL 0x00000400 +#define COMPARE_DST_EQUAL 0x00000500 +#define COMPARE_DESTINATION 0x00000000 +#define COMPARE_SOURCE 0x01000000 +#define COMPARE_SRC_AND_DST 0x02000000 + + +/* DP_CNTL bit constants */ +#define DST_X_RIGHT_TO_LEFT 0x00000000 +#define DST_X_LEFT_TO_RIGHT 0x00000001 +#define DST_Y_BOTTOM_TO_TOP 0x00000000 +#define DST_Y_TOP_TO_BOTTOM 0x00000002 +#define DST_X_MAJOR 0x00000000 +#define DST_Y_MAJOR 0x00000004 +#define DST_X_TILE 0x00000008 +#define DST_Y_TILE 0x00000010 +#define DST_LAST_PEL 0x00000020 +#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +#define DST_BRES_SIGN 0x00000100 +#define DST_HOST_BIG_ENDIAN_EN 0x00000200 +#define DST_POLYLINE_NONLAST 0x00008000 +#define DST_RASTER_STALL 0x00010000 +#define DST_POLY_EDGE 0x00040000 + + +/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ +#define DST_X_MAJOR_S 0x00000000 +#define DST_Y_MAJOR_S 0x00000001 +#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 +#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 +#define DST_X_RIGHT_TO_LEFT_S 0x00000000 +#define DST_X_LEFT_TO_RIGHT_S 0x80000000 + + +/* DP_DATATYPE bit constants */ +#define DST_8BPP 0x00000002 +#define DST_15BPP 0x00000003 +#define DST_16BPP 0x00000004 +#define DST_24BPP 0x00000005 +#define DST_32BPP 0x00000006 +#define DST_8BPP_RGB332 0x00000007 +#define DST_8BPP_Y8 0x00000008 +#define DST_8BPP_RGB8 0x00000009 +#define DST_16BPP_VYUY422 0x0000000b +#define DST_16BPP_YVYU422 0x0000000c +#define DST_32BPP_AYUV444 0x0000000e +#define DST_16BPP_ARGB4444 0x0000000f +#define BRUSH_SOLIDCOLOR 0x00000d00 +#define SRC_MONO 0x00000000 +#define SRC_MONO_LBKGD 0x00010000 +#define SRC_DSTCOLOR 0x00030000 +#define BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define BYTE_ORDER_LSB_TO_MSB 0x40000000 +#define DP_CONVERSION_TEMP 0x80000000 +#define HOST_BIG_ENDIAN_EN (1 << 29) + + +/* DP_GUI_MASTER_CNTL bit constants */ +#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 +#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 +#define GMC_SRC_CLIP_DEFAULT 0x00000000 +#define GMC_SRC_CLIP_LEAVE 0x00000004 +#define GMC_DST_CLIP_DEFAULT 0x00000000 +#define GMC_DST_CLIP_LEAVE 0x00000008 +#define GMC_BRUSH_8x8MONO 0x00000000 +#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 +#define GMC_BRUSH_8x1MONO 0x00000020 +#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 +#define GMC_BRUSH_1x8MONO 0x00000040 +#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 +#define GMC_BRUSH_32x1MONO 0x00000060 +#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 +#define GMC_BRUSH_32x32MONO 0x00000080 +#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 +#define GMC_BRUSH_8x8COLOR 0x000000a0 +#define GMC_BRUSH_8x1COLOR 0x000000b0 +#define GMC_BRUSH_1x8COLOR 0x000000c0 +#define GMC_BRUSH_SOLID_COLOR 0x000000d0 +#define GMC_DST_8BPP 0x00000200 +#define GMC_DST_15BPP 0x00000300 +#define GMC_DST_16BPP 0x00000400 +#define GMC_DST_24BPP 0x00000500 +#define GMC_DST_32BPP 0x00000600 +#define GMC_DST_8BPP_RGB332 0x00000700 +#define GMC_DST_8BPP_Y8 0x00000800 +#define GMC_DST_8BPP_RGB8 0x00000900 +#define GMC_DST_16BPP_VYUY422 0x00000b00 +#define GMC_DST_16BPP_YVYU422 0x00000c00 +#define GMC_DST_32BPP_AYUV444 0x00000e00 +#define GMC_DST_16BPP_ARGB4444 0x00000f00 +#define GMC_SRC_MONO 0x00000000 +#define GMC_SRC_MONO_LBKGD 0x00001000 +#define GMC_SRC_DSTCOLOR 0x00003000 +#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 +#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 +#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +#define GMC_DP_SRC_RECT 0x02000000 +#define GMC_DP_SRC_HOST 0x03000000 +#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 +#define GMC_3D_FCN_EN_CLR 0x00000000 +#define GMC_3D_FCN_EN_SET 0x08000000 +#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 +#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +#define GMC_AUX_CLIP_LEAVE 0x00000000 +#define GMC_AUX_CLIP_CLEAR 0x20000000 +#define GMC_WRITE_MASK_LEAVE 0x00000000 +#define GMC_WRITE_MASK_SET 0x40000000 +#define GMC_CLR_CMP_CNTL_DIS (1 << 28) +#define GMC_SRC_DATATYPE_COLOR (3 << 12) +#define ROP3_S 0x00cc0000 +#define ROP3_SRCCOPY 0x00cc0000 +#define ROP3_P 0x00f00000 +#define ROP3_PATCOPY 0x00f00000 +#define DP_SRC_SOURCE_MASK (7 << 24) +#define GMC_BRUSH_NONE (15 << 4) +#define DP_SRC_SOURCE_MEMORY (2 << 24) +#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 + +/* DP_MIX bit constants */ +#define DP_SRC_RECT 0x00000200 +#define DP_SRC_HOST 0x00000300 +#define DP_SRC_HOST_BYTEALIGN 0x00000400 + +/* MPLL_CNTL bit constants */ +#define MPLL_RESET 0x00000001 + +/* MDLL_CKO bit constants */ +#define MCKOA_SLEEP 0x00000001 +#define MCKOA_RESET 0x00000002 +#define MCKOA_REF_SKEW_MASK 0x00000700 +#define MCKOA_FB_SKEW_MASK 0x00007000 + +/* MDLL_RDCKA bit constants */ +#define MRDCKA0_SLEEP 0x00000001 +#define MRDCKA0_RESET 0x00000002 +#define MRDCKA1_SLEEP 0x00010000 +#define MRDCKA1_RESET 0x00020000 + +/* VCLK_ECP_CNTL constants */ +#define VCLK_SRC_SEL_MASK 0x03 +#define VCLK_SRC_SEL_CPUCLK 0x00 +#define VCLK_SRC_SEL_PSCANCLK 0x01 +#define VCLK_SRC_SEL_BYTECLK 0x02 +#define VCLK_SRC_SEL_PPLLCLK 0x03 +#define PIXCLK_ALWAYS_ONb 0x00000040 +#define PIXCLK_DAC_ALWAYS_ONb 0x00000080 + +/* BUS_CNTL1 constants */ +#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 +#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 +#define BUS_CNTL1_AGPCLK_VALID 0x80000000 + +/* PLL_PWRMGT_CNTL constants */ +#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 +#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 +#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 +#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 +#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 +#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 +#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 + +/* TV_DAC_CNTL constants */ +#define TV_DAC_CNTL_BGSLEEP 0x00000040 +#define TV_DAC_CNTL_DETECT 0x00000010 +#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 +#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 +#define TV_DAC_CNTL_BGADJ__SHIFT 16 +#define TV_DAC_CNTL_DACADJ__SHIFT 20 +#define TV_DAC_CNTL_RDACPD 0x01000000 +#define TV_DAC_CNTL_GDACPD 0x02000000 +#define TV_DAC_CNTL_BDACPD 0x04000000 + +/* DISP_MISC_CNTL constants */ +#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) +#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) +#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) +#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) +#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) +#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) +#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) +#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) +#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) + +/* DISP_PWR_MAN constants */ +#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) +#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) +#define DISP_PWR_MAN_DISP_D3_RST (1 << 16) +#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) +#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) +#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) +#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) +#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) +#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) +#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) +#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) +#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) +#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) + +/* masks */ + +#define CONFIG_MEMSIZE_MASK 0x1f000000 +#define MEM_CFG_TYPE 0x40000000 +#define DST_OFFSET_MASK 0x003fffff +#define DST_PITCH_MASK 0x3fc00000 +#define DEFAULT_TILE_MASK 0xc0000000 +#define PPLL_DIV_SEL_MASK 0x00000300 +#define PPLL_RESET 0x00000001 +#define PPLL_SLEEP 0x00000002 +#define PPLL_ATOMIC_UPDATE_EN 0x00010000 +#define PPLL_REF_DIV_MASK 0x000003ff +#define PPLL_FB3_DIV_MASK 0x000007ff +#define PPLL_POST3_DIV_MASK 0x00070000 +#define PPLL_ATOMIC_UPDATE_R 0x00008000 +#define PPLL_ATOMIC_UPDATE_W 0x00008000 +#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 +#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) +#define R300_PPLL_REF_DIV_ACC_SHIFT 18 + +#define GUI_ACTIVE 0x80000000 + + +#define MC_IND_INDEX 0x01F8 +#define MC_IND_DATA 0x01FC + +/* PAD_CTLR_STRENGTH */ +#define PAD_MANUAL_OVERRIDE 0x80000000 + +// pllCLK_PIN_CNTL +#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L +#define CLK_PIN_CNTL__OSC_EN 0x00000001L +#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L +#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L +#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L +#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L +#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L +#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L +#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L +#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L +#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L +#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L +#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L +#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L +#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L +#define CLK_PIN_CNTL__CG_SPARE 0x00004000L +#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L +#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L +#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L +#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L +#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L +#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L +#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L +#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L + +// pllCLK_PWRMGT_CNTL +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 +#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 +#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c +#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f +#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 +#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 +#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 +#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 +#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 +#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 +#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f + +// pllP2PLL_CNTL +#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L +#define P2PLL_CNTL__P2PLL_RESET 0x00000001L +#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L +#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L +#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L +#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L +#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L +#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L +#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L +#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L +#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L +#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L +#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L +#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L +#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L +#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L +#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L +#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L +#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L + +// pllPIXCLKS_CNTL +#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 +#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f + + +// pllPIXCLKS_CNTL +#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L +#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L +#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) +#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) +#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) +#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) +#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) +#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) +#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) +#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) + + +// pllP2PLL_DIV_0 +#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L +#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L + +// pllSCLK_CNTL +#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L +#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L +#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L +#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L +#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L +#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L +#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L +#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L +#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L +#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L +#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L +#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L +#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L +#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 +#define SCLK_CNTL__FORCE_DISP2 0x00008000L +#define SCLK_CNTL__FORCE_CP 0x00010000L +#define SCLK_CNTL__FORCE_HDP 0x00020000L +#define SCLK_CNTL__FORCE_DISP1 0x00040000L +#define SCLK_CNTL__FORCE_TOP 0x00080000L +#define SCLK_CNTL__FORCE_E2 0x00100000L +#define SCLK_CNTL__FORCE_SE 0x00200000L +#define SCLK_CNTL__FORCE_IDCT 0x00400000L +#define SCLK_CNTL__FORCE_VIP 0x00800000L +#define SCLK_CNTL__FORCE_RE 0x01000000L +#define SCLK_CNTL__FORCE_PB 0x02000000L +#define SCLK_CNTL__FORCE_TAM 0x04000000L +#define SCLK_CNTL__FORCE_TDM 0x08000000L +#define SCLK_CNTL__FORCE_RB 0x10000000L +#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L +#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L +#define SCLK_CNTL__FORCE_OV0 0x80000000L +#define SCLK_CNTL__R300_FORCE_VAP (1<<21) +#define SCLK_CNTL__R300_FORCE_SR (1<<25) +#define SCLK_CNTL__R300_FORCE_PX (1<<26) +#define SCLK_CNTL__R300_FORCE_TX (1<<27) +#define SCLK_CNTL__R300_FORCE_US (1<<28) +#define SCLK_CNTL__R300_FORCE_SU (1<<30) +#define SCLK_CNTL__FORCEON_MASK 0xffff8000L + +// pllSCLK_CNTL2 +#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) +#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) +#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) +#define SCLK_CNTL2__R300_FORCE_TCL (1<<13) +#define SCLK_CNTL2__R300_FORCE_CBA (1<<14) +#define SCLK_CNTL2__R300_FORCE_GA (1<<15) + +// SCLK_MORE_CNTL +#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L +#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L +#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L +#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L +#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L +#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L +#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L +#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L +#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L +#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L +#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L +#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L +#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L +#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L +#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L +#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L +#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L +#define SCLK_MORE_CNTL__FORCEON 0x00000700L + +// MCLK_CNTL +#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L +#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L +#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L +#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L +#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L +#define MCLK_CNTL__FORCE_MCLKA 0x00010000L +#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L +#define MCLK_CNTL__FORCE_MCLKB 0x00020000L +#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L +#define MCLK_CNTL__FORCE_YCLKA 0x00040000L +#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L +#define MCLK_CNTL__FORCE_YCLKB 0x00080000L +#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L +#define MCLK_CNTL__FORCE_MC 0x00100000L +#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L +#define MCLK_CNTL__FORCE_AIC 0x00200000L +#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L +#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L +#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L +#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L +#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) +#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) + +// MCLK_MISC +#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L +#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L +#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L +#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L +#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L +#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L +#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L +#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L +#define MCLK_MISC__DLL_READY_LAT 0x00000100L +#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L +#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L +#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L +#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L +#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L +#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L +#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L +#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L +#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L +#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L +#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L +#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L +#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L +#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L +#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L +#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L +#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L +#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L +#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L + +// VCLK_ECP_CNTL +#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L +#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L +#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L +#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L +#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L +#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L +#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L +#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L +#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) + +// PLL_PWRMGT_CNTL +#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L +#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L +#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L +#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L +#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L +#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L +#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L +#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L +#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L +#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L +#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L +#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L +#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L +#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L +#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L +#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L +#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L +#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L +#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L +#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L +#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L +#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L +#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L +#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L +#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L +#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L +#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L +#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L +#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L +#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L +#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L +#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L + +// CLK_PWRMGT_CNTL +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L +#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L +#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L +#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L +#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L +#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L +#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L +#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L +#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L +#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L +#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L +#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L +#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L +#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L +#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L +#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L +#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L +#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L + +// BUS_CNTL1 +#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L +#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L +#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L +#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L +#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L +#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L +#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L +#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L +#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L +#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L +#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L +#define BUS_CNTL1__AGPCLK_VALID 0x80000000L + +// BUS_CNTL1 +#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 +#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 +#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 +#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b +#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a +#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c +#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f + +// CRTC_OFFSET_CNTL +#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL +#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L + +// CRTC_GEN_CNTL +#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L +#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L +#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L +#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L +#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L +#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L +#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L +#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L +#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L +#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L +#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L +#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L +#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L +#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L +#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L +#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L +#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L +#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L +#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L + +// CRTC2_GEN_CNTL +#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L +#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L +#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L +#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L +#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L +#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L +#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L +#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L +#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L +#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L +#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L +#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L +#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L +#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L +#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L +#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L +#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L +#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L +#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L + +// AGP_CNTL +#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL +#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L +#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L +#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L +#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L +#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L +#define AGP_CNTL__EN_2X_STBB 0x00000400L +#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L +#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L +#define AGP_CNTL__SBA_DIS_MASK 0x00001000L +#define AGP_CNTL__SBA_DIS 0x00001000L +#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L +#define AGP_CNTL__AGP_REV_ID 0x00002000L +#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L +#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L +#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L +#define AGP_CNTL__FORCE_INT_VREF 0x00010000L +#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L +#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L +#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L +#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L +#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L +#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L +#define AGP_CNTL__EN_RBFCALM 0x00800000L +#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L +#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L +#define AGP_CNTL__DIS_RBF_MASK 0x02000000L +#define AGP_CNTL__DIS_RBF 0x02000000L +#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L +#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L +#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L +#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L + +// AGP_CNTL +#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 +#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 +#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 +#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a +#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b +#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c +#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d +#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f +#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 +#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 +#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 +#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 +#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 +#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 +#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 +#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a +#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b +#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e + +// DISP_MISC_CNTL +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L +#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L +#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L +#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L +#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L +#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L +#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L +#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L +#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L +#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L +#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L +#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L +#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L +#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L +#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L + +// DISP_PWR_MAN +#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L +#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L +#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L +#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L +#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L +#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L +#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L +#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L +#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L +#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L +#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L +#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L +#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L +#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L +#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L +#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L +#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L +#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L +#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L +#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L +#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L +#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L +#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L +#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L +#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L +#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L +#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L + +// MC_IND_INDEX +#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL +#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L +#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L + +// MC_IND_DATA +#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL + +// MC_CHP_IO_CNTL_A1 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a +#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c +#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e +#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 +#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f + +// MC_CHP_IO_CNTL_B1 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a +#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c +#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e +#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 +#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f + +// MC_CHP_IO_CNTL_A1 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L +#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L + +// MC_CHP_IO_CNTL_B1 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L +#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L + +// MEM_SDRAM_MODE_REG +#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL +#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L +#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L + +// MEM_SDRAM_MODE_REG +#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 +#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 +#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f + +// MEM_REFRESH_CNTL +#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL +#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L +#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L +#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L +#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L +#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L +#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L +#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L +#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L +#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L +#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L +#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L +#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L +#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L +#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L +#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L +#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L +#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L +#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L +#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L +#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L + +// MC_STATUS +#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L +#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L +#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L +#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L +#define MC_STATUS__MC_IDLE_MASK 0x00000004L +#define MC_STATUS__MC_IDLE 0x00000004L +#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L +#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L +#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L +#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L +#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L +#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L +#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L +#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L +#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L +#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L + +// MDLL_CKO +#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L +#define MDLL_CKO__MCKOA_SLEEP 0x00000001L +#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L +#define MDLL_CKO__MCKOA_RESET 0x00000002L +#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL +#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L +#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L +#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L +#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L +#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L +#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L +#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L +#define MDLL_CKO__MCKOB_SLEEP 0x00010000L +#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L +#define MDLL_CKO__MCKOB_RESET 0x00020000L +#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L +#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L +#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L +#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L +#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L +#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L +#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L + +// MDLL_RDCKA +#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L +#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L +#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L +#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L +#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL +#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L +#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L +#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L +#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L +#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L +#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L +#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L +#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L +#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L +#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L +#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L +#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L +#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L +#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L +#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L +#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L +#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L +#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L +#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L +#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L +#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L + +// MDLL_RDCKB +#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L +#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L +#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L +#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L +#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL +#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L +#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L +#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L +#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L +#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L +#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L +#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L +#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L +#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L +#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L +#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L +#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L +#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L +#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L +#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L +#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L +#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L +#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L +#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L +#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L +#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L + +#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L +#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L +#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L +#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L +#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L +#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L +#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L +#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L + +#define pllCLK_PIN_CNTL 0x0001 +#define pllPPLL_CNTL 0x0002 +#define pllPPLL_REF_DIV 0x0003 +#define pllPPLL_DIV_0 0x0004 +#define pllPPLL_DIV_1 0x0005 +#define pllPPLL_DIV_2 0x0006 +#define pllPPLL_DIV_3 0x0007 +#define pllVCLK_ECP_CNTL 0x0008 +#define pllHTOTAL_CNTL 0x0009 +#define pllM_SPLL_REF_FB_DIV 0x000A +#define pllAGP_PLL_CNTL 0x000B +#define pllSPLL_CNTL 0x000C +#define pllSCLK_CNTL 0x000D +#define pllMPLL_CNTL 0x000E +#define pllMDLL_CKO 0x000F +#define pllMDLL_RDCKA 0x0010 +#define pllMDLL_RDCKB 0x0011 +#define pllMCLK_CNTL 0x0012 +#define pllPLL_TEST_CNTL 0x0013 +#define pllCLK_PWRMGT_CNTL 0x0014 +#define pllPLL_PWRMGT_CNTL 0x0015 +#define pllCG_TEST_MACRO_RW_WRITE 0x0016 +#define pllCG_TEST_MACRO_RW_READ 0x0017 +#define pllCG_TEST_MACRO_RW_DATA 0x0018 +#define pllCG_TEST_MACRO_RW_CNTL 0x0019 +#define pllDISP_TEST_MACRO_RW_WRITE 0x001A +#define pllDISP_TEST_MACRO_RW_READ 0x001B +#define pllDISP_TEST_MACRO_RW_DATA 0x001C +#define pllDISP_TEST_MACRO_RW_CNTL 0x001D +#define pllSCLK_CNTL2 0x001E +#define pllMCLK_MISC 0x001F +#define pllTV_PLL_FINE_CNTL 0x0020 +#define pllTV_PLL_CNTL 0x0021 +#define pllTV_PLL_CNTL1 0x0022 +#define pllTV_DTO_INCREMENTS 0x0023 +#define pllSPLL_AUX_CNTL 0x0024 +#define pllMPLL_AUX_CNTL 0x0025 +#define pllP2PLL_CNTL 0x002A +#define pllP2PLL_REF_DIV 0x002B +#define pllP2PLL_DIV_0 0x002C +#define pllPIXCLKS_CNTL 0x002D +#define pllHTOTAL2_CNTL 0x002E +#define pllSSPLL_CNTL 0x0030 +#define pllSSPLL_REF_DIV 0x0031 +#define pllSSPLL_DIV_0 0x0032 +#define pllSS_INT_CNTL 0x0033 +#define pllSS_TST_CNTL 0x0034 +#define pllSCLK_MORE_CNTL 0x0035 + +#define ixMC_PERF_CNTL 0x0000 +#define ixMC_PERF_SEL 0x0001 +#define ixMC_PERF_REGION_0 0x0002 +#define ixMC_PERF_REGION_1 0x0003 +#define ixMC_PERF_COUNT_0 0x0004 +#define ixMC_PERF_COUNT_1 0x0005 +#define ixMC_PERF_COUNT_2 0x0006 +#define ixMC_PERF_COUNT_3 0x0007 +#define ixMC_PERF_COUNT_MEMCH_A 0x0008 +#define ixMC_PERF_COUNT_MEMCH_B 0x0009 +#define ixMC_IMP_CNTL 0x000A +#define ixMC_CHP_IO_CNTL_A0 0x000B +#define ixMC_CHP_IO_CNTL_A1 0x000C +#define ixMC_CHP_IO_CNTL_B0 0x000D +#define ixMC_CHP_IO_CNTL_B1 0x000E +#define ixMC_IMP_CNTL_0 0x000F +#define ixTC_MISMATCH_1 0x0010 +#define ixTC_MISMATCH_2 0x0011 +#define ixMC_BIST_CTRL 0x0012 +#define ixREG_COLLAR_WRITE 0x0013 +#define ixREG_COLLAR_READ 0x0014 +#define ixR300_MC_IMP_CNTL 0x0018 +#define ixR300_MC_CHP_IO_CNTL_A0 0x0019 +#define ixR300_MC_CHP_IO_CNTL_A1 0x001a +#define ixR300_MC_CHP_IO_CNTL_B0 0x001b +#define ixR300_MC_CHP_IO_CNTL_B1 0x001c +#define ixR300_MC_CHP_IO_CNTL_C0 0x001d +#define ixR300_MC_CHP_IO_CNTL_C1 0x001e +#define ixR300_MC_CHP_IO_CNTL_D0 0x001f +#define ixR300_MC_CHP_IO_CNTL_D1 0x0020 +#define ixR300_MC_IMP_CNTL_0 0x0021 +#define ixR300_MC_ELPIDA_CNTL 0x0022 +#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 +#define ixR300_MC_READ_CNTL_CD 0x0024 +#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 +#define ixR300_MC_DEBUG_CNTL 0x0026 +#define ixR300_MC_BIST_CNTL_0 0x0028 +#define ixR300_MC_BIST_CNTL_1 0x0029 +#define ixR300_MC_BIST_CNTL_2 0x002a +#define ixR300_MC_BIST_CNTL_3 0x002b +#define ixR300_MC_BIST_CNTL_4 0x002c +#define ixR300_MC_BIST_CNTL_5 0x002d +#define ixR300_MC_IMP_STATUS 0x002e +#define ixR300_MC_DLL_CNTL 0x002f +#define NB_TOM 0x15C + + +#endif /* _RADEON_H */ + -- cgit v1.3.1 From ece92f85053b8df613edcf05b26a416cbc3d629c Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 6 Jul 2007 08:34:56 +0800 Subject: This is a BIOS emulator, porting from SciTech for u-boot, mainly for ATI video card BIOS. and can be used for x86 code emulation by some modifications. Signed-off-by: Jason Jin --- drivers/bios_emulator/Makefile | 30 + drivers/bios_emulator/atibios.c | 340 ++ drivers/bios_emulator/besys.c | 722 +++ drivers/bios_emulator/bios.c | 321 ++ drivers/bios_emulator/biosemu.c | 370 ++ drivers/bios_emulator/biosemui.h | 169 + drivers/bios_emulator/include/biosemu.h | 392 ++ drivers/bios_emulator/include/x86emu.h | 191 + drivers/bios_emulator/include/x86emu/debug.h | 209 + drivers/bios_emulator/include/x86emu/decode.h | 88 + drivers/bios_emulator/include/x86emu/ops.h | 45 + drivers/bios_emulator/include/x86emu/prim_asm.h | 970 ++++ drivers/bios_emulator/include/x86emu/prim_ops.h | 142 + drivers/bios_emulator/include/x86emu/regs.h | 340 ++ drivers/bios_emulator/include/x86emu/x86emui.h | 101 + drivers/bios_emulator/x86emu/debug.c | 461 ++ drivers/bios_emulator/x86emu/decode.c | 1148 +++++ drivers/bios_emulator/x86emu/ops.c | 5431 +++++++++++++++++++++++ drivers/bios_emulator/x86emu/ops2.c | 1770 ++++++++ drivers/bios_emulator/x86emu/prim_ops.c | 2446 ++++++++++ drivers/bios_emulator/x86emu/sys.c | 322 ++ 21 files changed, 16008 insertions(+) create mode 100644 drivers/bios_emulator/Makefile create mode 100644 drivers/bios_emulator/atibios.c create mode 100644 drivers/bios_emulator/besys.c create mode 100644 drivers/bios_emulator/bios.c create mode 100644 drivers/bios_emulator/biosemu.c create mode 100644 drivers/bios_emulator/biosemui.h create mode 100644 drivers/bios_emulator/include/biosemu.h create mode 100644 drivers/bios_emulator/include/x86emu.h create mode 100644 drivers/bios_emulator/include/x86emu/debug.h create mode 100644 drivers/bios_emulator/include/x86emu/decode.h create mode 100644 drivers/bios_emulator/include/x86emu/ops.h create mode 100644 drivers/bios_emulator/include/x86emu/prim_asm.h create mode 100644 drivers/bios_emulator/include/x86emu/prim_ops.h create mode 100644 drivers/bios_emulator/include/x86emu/regs.h create mode 100644 drivers/bios_emulator/include/x86emu/x86emui.h create mode 100644 drivers/bios_emulator/x86emu/debug.c create mode 100644 drivers/bios_emulator/x86emu/decode.c create mode 100644 drivers/bios_emulator/x86emu/ops.c create mode 100644 drivers/bios_emulator/x86emu/ops2.c create mode 100644 drivers/bios_emulator/x86emu/prim_ops.c create mode 100644 drivers/bios_emulator/x86emu/sys.c (limited to 'drivers') diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile new file mode 100644 index 00000000000..ba7d43673f7 --- /dev/null +++ b/drivers/bios_emulator/Makefile @@ -0,0 +1,30 @@ +include $(TOPDIR)/config.mk + +LIB := libatibiosemu.a + +X86DIR = ./x86emu + +OBJS = atibios.o biosemu.o besys.o bios.o \ + $(X86DIR)/decode.o \ + $(X86DIR)/ops2.o \ + $(X86DIR)/ops.o \ + $(X86DIR)/prim_ops.o \ + $(X86DIR)/sys.o \ + $(X86DIR)/debug.o + +CFLAGS += -I. -I./include -I$(X86DIR) -I$(TOPDIR)/include \ + -D__PPC__ -D__BIG_ENDIAN__ + +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c new file mode 100644 index 00000000000..084339c1b29 --- /dev/null +++ b/drivers/bios_emulator/atibios.c @@ -0,0 +1,340 @@ +/**************************************************************************** +* +* Video BOOT Graphics Card POST Module +* +* ======================================================================== +* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. +* Jason Jin +* +* Copyright (C) 1991-2004 SciTech Software, Inc. All rights reserved. +* +* This file may be distributed and/or modified under the terms of the +* GNU General Public License version 2.0 as published by the Free +* Software Foundation and appearing in the file LICENSE.GPL included +* in the packaging of this file. +* +* Licensees holding a valid Commercial License for this product from +* SciTech Software, Inc. may use this file in accordance with the +* Commercial License Agreement provided with the Software. +* +* This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING +* THE WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR +* PURPOSE. +* +* See http://www.scitechsoft.com/license/ for information about +* the licensing options available and how to purchase a Commercial +* License Agreement. +* +* Contact license@scitechsoft.com if any conditions of this licensing +* are not clear to you, or you have questions about licensing options. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux Kernel +* Developer: Kendall Bennett +* +* Description: Module to implement booting PCI/AGP controllers on the +* bus. We use the x86 real mode emulator to run the BIOS on +* graphics controllers to bring the cards up. +* +* Note that at present this module does *not* support +* multiple controllers. +* +* The orignal name of this file is warmboot.c. +* Jason ported this file to u-boot to run the ATI video card +* BIOS in u-boot. +****************************************************************************/ +#include + +#ifdef CONFIG_BIOSEMU + +#include "biosemui.h" +#include + +/* Length of the BIOS image */ +#define MAX_BIOSLEN (128 * 1024L) + +/* Define some useful types and macros */ +#define true 1 +#define false 0 + +/* Place to save PCI BAR's that we change and later restore */ +static u32 saveROMBaseAddress; +static u32 saveBaseAddress10; +static u32 saveBaseAddress14; +static u32 saveBaseAddress18; +static u32 saveBaseAddress20; + +/**************************************************************************** +PARAMETERS: +pcidev - PCI device info for the video card on the bus to boot +VGAInfo - BIOS emulator VGA info structure + +REMARKS: +This function executes the BIOS POST code on the controller. We assume that +at this stage the controller has its I/O and memory space enabled and +that all other controllers are in a disabled state. +****************************************************************************/ +static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) +{ + RMREGS regs; + RMSREGS sregs; + + /* Determine the value to store in AX for BIOS POST. Per the PCI specs, + AH must contain the bus and AL must contain the devfn, encoded as + (dev << 3) | fn + */ + memset(®s, 0, sizeof(regs)); + memset(&sregs, 0, sizeof(sregs)); + regs.x.ax = ((int)PCI_BUS(pcidev) << 8) | + ((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev); + + /*Setup the X86 emulator for the VGA BIOS*/ + BE_setVGA(VGAInfo); + + /*Execute the BIOS POST code*/ + BE_callRealMode(0xC000, 0x0003, ®s, &sregs); + + /*Cleanup and exit*/ + BE_getVGA(VGAInfo); +} + +/**************************************************************************** +PARAMETERS: +pcidev - PCI device info for the video card on the bus +bar - Place to return the base address register offset to use + +RETURNS: +The address to use to map the secondary BIOS (AGP devices) + +REMARKS: +Searches all the PCI base address registers for the device looking for a +memory mapping that is large enough to hold our ROM BIOS. We usually end up +finding the framebuffer mapping (usually BAR 0x10), and we use this mapping +to map the BIOS for the device into. We use a mapping that is already +assigned to the device to ensure the memory range will be passed through +by any PCI->PCI or AGP->PCI bridge that may be present. + +NOTE: Usually this function is only used for AGP devices, but it may be + used for PCI devices that have already been POST'ed and the BIOS + ROM base address has been zero'ed out. + +NOTE: This function leaves the original memory aperture disabled by leaving + it programmed to all 1's. It must be restored to the correct value + later. +****************************************************************************/ +static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar) +{ + u32 base, size; + + for (*bar = 0x10; *bar <= 0x14; (*bar) += 4) { + pci_read_config_dword(pcidev, *bar, &base); + if (!(base & 0x1)) { + pci_write_config_dword(pcidev, *bar, 0xFFFFFFFF); + pci_read_config_dword(pcidev, *bar, &size); + size = ~(size & ~0xFF) + 1; + if (size >= MAX_BIOSLEN) + return base & ~0xFF; + } + } + return 0; +} + +/**************************************************************************** +REMARKS: +Some non-x86 Linux kernels map PCI relocateable I/O to values that +are above 64K, which will not work with the BIOS image that requires +the offset for the I/O ports to be a maximum of 16-bits. Ideally +someone should fix the kernel to map the I/O ports for VGA compatible +devices to a different location (or just all I/O ports since it is +unlikely you can have enough devices in the machine to use up all +64K of the I/O space - a total of more than 256 cards would be +necessary). + +Anyway to fix this we change all I/O mapped base registers and +chop off the top bits. +****************************************************************************/ +static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base) +{ + if ((*base & 0x1) && (*base > 0xFFFE)) { + *base &= 0xFFFF; + pci_write_config_dword(pcidev, reg, *base); + + } +} + +/**************************************************************************** +PARAMETERS: +pcidev - PCI device info for the video card on the bus + +RETURNS: +Pointers to the mapped BIOS image + +REMARKS: +Maps a pointer to the BIOS image on the graphics card on the PCI bus. +****************************************************************************/ +void *PCI_mapBIOSImage(pci_dev_t pcidev) +{ + u32 BIOSImagePhys; + int BIOSImageBAR; + u8 *BIOSImage; + + /*Save PCI BAR registers that might get changed*/ + pci_read_config_dword(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress); + pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10); + pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14); + pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18); + pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20); + + /*Fix up I/O base registers to less than 64K */ + if(saveBaseAddress14 != 0) + PCI_fixupIObase(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14); + else + PCI_fixupIObase(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20); + + /* Some cards have problems that stop us from being able to read the + BIOS image from the ROM BAR. To fix this we have to do some chipset + specific programming for different cards to solve this problem. + */ + + if ((BIOSImagePhys = PCI_findBIOSAddr(pcidev, &BIOSImageBAR)) == 0) { + printf("Find bios addr error\n"); + return NULL; + } + + BIOSImage = (u8 *) BIOSImagePhys; + + /*Change the PCI BAR registers to map it onto the bus.*/ + pci_write_config_dword(pcidev, BIOSImageBAR, 0); + pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImagePhys | 0x1); + + udelay(1); + + /*Check that the BIOS image is valid. If not fail, or return the + compiled in BIOS image if that option was enabled + */ + if (BIOSImage[0] != 0x55 || BIOSImage[1] != 0xAA || BIOSImage[2] == 0) { + return NULL; + } + + return BIOSImage; +} + +/**************************************************************************** +PARAMETERS: +pcidev - PCI device info for the video card on the bus + +REMARKS: +Unmaps the BIOS image for the device and restores framebuffer mappings +****************************************************************************/ +void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage) +{ + pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress); + pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10); + pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14); + pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18); + pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20); +} + +/**************************************************************************** +PARAMETERS: +pcidev - PCI device info for the video card on the bus to boot +VGAInfo - BIOS emulator VGA info structure + +RETURNS: +True if successfully initialised, false if not. + +REMARKS: +Loads and POST's the display controllers BIOS, directly from the BIOS +image we can extract over the PCI bus. +****************************************************************************/ +static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) +{ + u32 BIOSImageLen; + uchar *mappedBIOS; + uchar *copyOfBIOS; + + /*Allocate memory to store copy of BIOS from display controller*/ + if ((mappedBIOS = PCI_mapBIOSImage(pcidev)) == NULL) { + printf("videoboot: Video ROM failed to map!\n"); + return false; + } + + BIOSImageLen = mappedBIOS[2] * 512; + + if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) { + printf("videoboot: Out of memory!\n"); + return false; + } + memcpy(copyOfBIOS, mappedBIOS, BIOSImageLen); + + PCI_unmapBIOSImage(pcidev, mappedBIOS); + + /*Save information in VGAInfo structure*/ + VGAInfo->function = PCI_FUNC(pcidev); + VGAInfo->device = PCI_DEV(pcidev); + VGAInfo->bus = PCI_BUS(pcidev); + VGAInfo->pcidev = pcidev; + VGAInfo->BIOSImage = copyOfBIOS; + VGAInfo->BIOSImageLen = BIOSImageLen; + + /*Now execute the BIOS POST for the device*/ + if (copyOfBIOS[0] != 0x55 || copyOfBIOS[1] != 0xAA) { + printf("videoboot: Video ROM image is invalid!\n"); + return false; + } + + PCI_doBIOSPOST(pcidev, VGAInfo); + + /*Reset the size of the BIOS image to the final size*/ + VGAInfo->BIOSImageLen = copyOfBIOS[2] * 512; + return true; +} + +/**************************************************************************** +PARAMETERS: +pcidev - PCI device info for the video card on the bus to boot +pVGAInfo - Place to return VGA info structure is requested +cleanUp - True to clean up on exit, false to leave emulator active + +REMARKS: +Boots the PCI/AGP video card on the bus using the Video ROM BIOS image +and the X86 BIOS emulator module. +****************************************************************************/ +int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp) +{ + BE_VGAInfo *VGAInfo; + + printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n", + PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev)); + + /*Initialise the x86 BIOS emulator*/ + if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) { + printf("videoboot: Out of memory!\n"); + return false; + } + memset(VGAInfo, 0, sizeof(*VGAInfo)); + BE_init(0, 65536, VGAInfo, 0); + + /*Post all the display controller BIOS'es*/ + PCI_postController(pcidev, VGAInfo); + + /*Cleanup and exit the emulator if requested. If the BIOS emulator + is needed after booting the card, we will not call BE_exit and + leave it enabled for further use (ie: VESA driver etc). + */ + if (cleanUp) { + BE_exit(); + if (VGAInfo->BIOSImage) + free(VGAInfo->BIOSImage); + free(VGAInfo); + VGAInfo = NULL; + } + /*Return VGA info pointer if the caller requested it*/ + if (pVGAInfo) + *pVGAInfo = VGAInfo; + return true; +} + +#endif diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c new file mode 100644 index 00000000000..894012fa898 --- /dev/null +++ b/drivers/bios_emulator/besys.c @@ -0,0 +1,722 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* ======================================================================== +* +* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. +* Jason Jin +* +* Copyright (C) 1991-2004 SciTech Software, Inc. All rights reserved. +* +* This file may be distributed and/or modified under the terms of the +* GNU General Public License version 2.0 as published by the Free +* Software Foundation and appearing in the file LICENSE.GPL included +* in the packaging of this file. +* +* Licensees holding a valid Commercial License for this product from +* SciTech Software, Inc. may use this file in accordance with the +* Commercial License Agreement provided with the Software. +* +* This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING +* THE WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR +* PURPOSE. +* +* See http://www.scitechsoft.com/license/ for information about +* the licensing options available and how to purchase a Commercial +* License Agreement. +* +* Contact license@scitechsoft.com if any conditions of this licensing +* are not clear to you, or you have questions about licensing options. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes BIOS emulator I/O and memory access +* functions. +* +* Jason ported this file to u-boot to run the ATI video card +* BIOS in u-boot. Removed some emulate functions such as the +* timer port access. Made all the VGA port except reading 0x3c3 +* be emulated. Seems like reading 0x3c3 should return the high +* 16 bit of the io port. +* +****************************************************************************/ + +#include "biosemui.h" + +/*------------------------- Global Variables ------------------------------*/ + +#ifndef __i386__ +static char *BE_biosDate = "08/14/99"; +static u8 BE_model = 0xFC; +static u8 BE_submodel = 0x00; +#endif + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to convert + +RETURNS: +Actual memory address to read or write the data + +REMARKS: +This function converts an emulator memory address in a 32-bit range to +a real memory address that we wish to access. It handles splitting up the +memory address space appropriately to access the emulator BIOS image, video +memory and system BIOS etc. +****************************************************************************/ +static u8 *BE_memaddr(u32 addr) +{ + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { + return (u8*)(_BE_env.biosmem_base + addr - 0xC0000); + } else if (addr > _BE_env.biosmem_limit && addr < 0xD0000) { + DB(printf("BE_memaddr: address %#lx may be invalid!\n", addr);) + return M.mem_base; + } else if (addr >= 0xA0000 && addr <= 0xBFFFF) { + return (u8*)(_BE_env.busmem_base + addr - 0xA0000); + } +#ifdef __i386__ + else if (addr >= 0xD0000 && addr <= 0xFFFFF) { + /* We map the real System BIOS directly on real PC's */ + DB(printf("BE_memaddr: System BIOS address %#lx\n", addr);) + return _BE_env.busmem_base + addr - 0xA0000; + } +#else + else if (addr >= 0xFFFF5 && addr < 0xFFFFE) { + /* Return a faked BIOS date string for non-x86 machines */ + DB(printf("BE_memaddr - Returning BIOS date\n");) + return BE_biosDate + addr - 0xFFFF5; + } else if (addr == 0xFFFFE) { + /* Return system model identifier for non-x86 machines */ + DB(printf("BE_memaddr - Returning model\n");) + return &BE_model; + } else if (addr == 0xFFFFF) { + /* Return system submodel identifier for non-x86 machines */ + DB(printf("BE_memaddr - Returning submodel\n");) + return &BE_submodel; + } +#endif + else if (addr > M.mem_size - 1) { + HALT_SYS(); + return M.mem_base; + } + + return M.mem_base + addr; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Byte value read from emulator memory. + +REMARKS: +Reads a byte value from the emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +u8 X86API BE_rdb(u32 addr) +{ + if (_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF) + return 0; + else { + u8 val = readb_le(BE_memaddr(addr)); + return val; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Word value read from emulator memory. + +REMARKS: +Reads a word value from the emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +u16 X86API BE_rdw(u32 addr) +{ + if (_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF) + return 0; + else { + u8 *base = BE_memaddr(addr); + u16 val = readw_le(base); + return val; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Long value read from emulator memory. + +REMARKS: +Reads a 32-bit value from the emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +u32 X86API BE_rdl(u32 addr) +{ + if (_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF) + return 0; + else { + u8 *base = BE_memaddr(addr); + u32 val = readl_le(base); + return val; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a byte value to emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +void X86API BE_wrb(u32 addr, u8 val) +{ + if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) { + writeb_le(BE_memaddr(addr), val); + } +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a word value to emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +void X86API BE_wrw(u32 addr, u16 val) +{ + if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) { + u8 *base = BE_memaddr(addr); + writew_le(base, val); + + } +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a 32-bit value to emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +void X86API BE_wrl(u32 addr, u32 val) +{ + if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) { + u8 *base = BE_memaddr(addr); + writel_le(base, val); + } +} + +#if defined(DEBUG) || !defined(__i386__) + +/* For Non-Intel machines we may need to emulate some I/O port accesses that + * the BIOS may try to access, such as the PCI config registers. + */ + +#define IS_TIMER_PORT(port) (0x40 <= port && port <= 0x43) +#define IS_CMOS_PORT(port) (0x70 <= port && port <= 0x71) +/*#define IS_VGA_PORT(port) (_BE_env.emulateVGA && 0x3C0 <= port && port <= 0x3DA)*/ +#define IS_VGA_PORT(port) (0x3C0 <= port && port <= 0x3DA) +#define IS_PCI_PORT(port) (0xCF8 <= port && port <= 0xCFF) +#define IS_SPKR_PORT(port) (port == 0x61) + +/**************************************************************************** +PARAMETERS: +port - Port to read from +type - Type of access to perform + +REMARKS: +Performs an emulated read from the Standard VGA I/O ports. If the target +hardware does not support mapping the VGA I/O and memory (such as some +PowerPC systems), we emulate the VGA so that the BIOS will still be able to +set NonVGA display modes such as on ATI hardware. +****************************************************************************/ +static u8 VGA_inpb( + const int port) +{ + u8 val = 0xff; + + switch (port) { + case 0x3C0: + /* 3C0 has funky characteristics because it can act as either + a data register or index register depending on the state + of an internal flip flop in the hardware. Hence we have + to emulate that functionality in here. */ + if (_BE_env.flipFlop3C0 == 0) { + /* Access 3C0 as index register*/ + val = _BE_env.emu3C0; + } + else { + /* Access 3C0 as data register*/ + if (_BE_env.emu3C0 < ATT_C) + val = _BE_env.emu3C1[_BE_env.emu3C0]; + } + _BE_env.flipFlop3C0 ^= 1; + break; + case 0x3C1: + if (_BE_env.emu3C0 < ATT_C) + return _BE_env.emu3C1[_BE_env.emu3C0]; + break; + case 0x3CC: + return _BE_env.emu3C2; + case 0x3C4: + return _BE_env.emu3C4; + case 0x3C5: + if (_BE_env.emu3C4 < ATT_C) + return _BE_env.emu3C5[_BE_env.emu3C4]; + break; + case 0x3C6: + return _BE_env.emu3C6; + case 0x3C7: + return _BE_env.emu3C7; + case 0x3C8: + return _BE_env.emu3C8; + case 0x3C9: + if (_BE_env.emu3C7 < PAL_C) + return _BE_env.emu3C9[_BE_env.emu3C7++]; + break; + case 0x3CE: + return _BE_env.emu3CE; + case 0x3CF: + if (_BE_env.emu3CE < GRA_C) + return _BE_env.emu3CF[_BE_env.emu3CE]; + break; + case 0x3D4: + if (_BE_env.emu3C2 & 0x1) + return _BE_env.emu3D4; + break; + case 0x3D5: + if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C)) + return _BE_env.emu3D5[_BE_env.emu3D4]; + break; + case 0x3DA: + _BE_env.flipFlop3C0 = 0; + val = _BE_env.emu3DA; + _BE_env.emu3DA ^= 0x9; + break; + } + return val; +} + +/**************************************************************************** +PARAMETERS: +port - Port to write to +type - Type of access to perform + +REMARKS: +Performs an emulated write to one of the 8253 timer registers. For now +we only emulate timer 0 which is the only timer that the BIOS code appears +to use. +****************************************************************************/ +static void VGA_outpb( + int port, + u8 val) +{ + switch (port) { + case 0x3C0: + /* 3C0 has funky characteristics because it can act as either + a data register or index register depending on the state + of an internal flip flop in the hardware. Hence we have + to emulate that functionality in here.*/ + if (_BE_env.flipFlop3C0 == 0) { + /* Access 3C0 as index register*/ + _BE_env.emu3C0 = val; + } + else { + /* Access 3C0 as data register*/ + if (_BE_env.emu3C0 < ATT_C) + _BE_env.emu3C1[_BE_env.emu3C0] = val; + } + _BE_env.flipFlop3C0 ^= 1; + break; + case 0x3C2: + _BE_env.emu3C2 = val; + break; + case 0x3C4: + _BE_env.emu3C4 = val; + break; + case 0x3C5: + if (_BE_env.emu3C4 < ATT_C) + _BE_env.emu3C5[_BE_env.emu3C4] = val; + break; + case 0x3C6: + _BE_env.emu3C6 = val; + break; + case 0x3C7: + _BE_env.emu3C7 = (int)val * 3; + break; + case 0x3C8: + _BE_env.emu3C8 = (int)val * 3; + break; + case 0x3C9: + if (_BE_env.emu3C8 < PAL_C) + _BE_env.emu3C9[_BE_env.emu3C8++] = val; + break; + case 0x3CE: + _BE_env.emu3CE = val; + break; + case 0x3CF: + if (_BE_env.emu3CE < GRA_C) + _BE_env.emu3CF[_BE_env.emu3CE] = val; + break; + case 0x3D4: + if (_BE_env.emu3C2 & 0x1) + _BE_env.emu3D4 = val; + break; + case 0x3D5: + if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C)) + _BE_env.emu3D5[_BE_env.emu3D4] = val; + break; + } +} + +/**************************************************************************** +PARAMETERS: +regOffset - Offset into register space for non-DWORD accesses +value - Value to write to register for PCI_WRITE_* operations +func - Function to perform (PCIAccessRegFlags) + +RETURNS: +Value read from configuration register for PCI_READ_* operations + +REMARKS: +Accesses a PCI configuration space register by decoding the value currently +stored in the _BE_env.configAddress variable and passing it through to the +portable PCI_accessReg function. +****************************************************************************/ +static u32 BE_accessReg(int regOffset, u32 value, int func) +{ +#ifdef __KERNEL__ + int function, device, bus; + u8 val8; + u16 val16; + u32 val32; + + + /* Decode the configuration register values for the register we wish to + * access + */ + regOffset += (_BE_env.configAddress & 0xFF); + function = (_BE_env.configAddress >> 8) & 0x7; + device = (_BE_env.configAddress >> 11) & 0x1F; + bus = (_BE_env.configAddress >> 16) & 0xFF; + + /* Ignore accesses to all devices other than the one we're POSTing */ + if ((function == _BE_env.vgaInfo.function) && + (device == _BE_env.vgaInfo.device) && + (bus == _BE_env.vgaInfo.bus)) { + switch (func) { + case REG_READ_BYTE: + pci_read_config_byte(_BE_env.vgaInfo.pcidev, regOffset, + &val8); + return val8; + case REG_READ_WORD: + pci_read_config_word(_BE_env.vgaInfo.pcidev, regOffset, + &val16); + return val16; + case REG_READ_DWORD: + pci_read_config_dword(_BE_env.vgaInfo.pcidev, regOffset, + &val32); + return val32; + case REG_WRITE_BYTE: + pci_write_config_byte(_BE_env.vgaInfo.pcidev, regOffset, + value); + + return 0; + case REG_WRITE_WORD: + pci_write_config_word(_BE_env.vgaInfo.pcidev, regOffset, + value); + + return 0; + case REG_WRITE_DWORD: + pci_write_config_dword(_BE_env.vgaInfo.pcidev, + regOffset, value); + + return 0; + } + } + return 0; +#else + PCIDeviceInfo pciInfo; + + pciInfo.mech1 = 1; + pciInfo.slot.i = 0; + pciInfo.slot.p.Function = (_BE_env.configAddress >> 8) & 0x7; + pciInfo.slot.p.Device = (_BE_env.configAddress >> 11) & 0x1F; + pciInfo.slot.p.Bus = (_BE_env.configAddress >> 16) & 0xFF; + pciInfo.slot.p.Enable = 1; + + /* Ignore accesses to all devices other than the one we're POSTing */ + if ((pciInfo.slot.p.Function == + _BE_env.vgaInfo.pciInfo->slot.p.Function) + && (pciInfo.slot.p.Device == _BE_env.vgaInfo.pciInfo->slot.p.Device) + && (pciInfo.slot.p.Bus == _BE_env.vgaInfo.pciInfo->slot.p.Bus)) + return PCI_accessReg((_BE_env.configAddress & 0xFF) + regOffset, + value, func, &pciInfo); + return 0; +#endif +} + +/**************************************************************************** +PARAMETERS: +port - Port to read from +type - Type of access to perform + +REMARKS: +Performs an emulated read from one of the PCI configuration space registers. +We emulate this using our PCI_accessReg function which will access the PCI +configuration space registers in a portable fashion. +****************************************************************************/ +static u32 PCI_inp(int port, int type) +{ + switch (type) { + case REG_READ_BYTE: + if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port + && port <= 0xCFF) + return BE_accessReg(port - 0xCFC, 0, REG_READ_BYTE); + break; + case REG_READ_WORD: + if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port + && port <= 0xCFF) + return BE_accessReg(port - 0xCFC, 0, REG_READ_WORD); + break; + case REG_READ_DWORD: + if (port == 0xCF8) + return _BE_env.configAddress; + else if ((_BE_env.configAddress & 0x80000000) && port == 0xCFC) + return BE_accessReg(0, 0, REG_READ_DWORD); + break; + } + return 0; +} + +/**************************************************************************** +PARAMETERS: +port - Port to write to +type - Type of access to perform + +REMARKS: +Performs an emulated write to one of the PCI control registers. +****************************************************************************/ +static void PCI_outp(int port, u32 val, int type) +{ + switch (type) { + case REG_WRITE_BYTE: + if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port + && port <= 0xCFF) + BE_accessReg(port - 0xCFC, val, REG_WRITE_BYTE); + break; + case REG_WRITE_WORD: + if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port + && port <= 0xCFF) + BE_accessReg(port - 0xCFC, val, REG_WRITE_WORD); + break; + case REG_WRITE_DWORD: + if (port == 0xCF8) + { + _BE_env.configAddress = val & 0x80FFFFFC; + } + else if ((_BE_env.configAddress & 0x80000000) && port == 0xCFC) + BE_accessReg(0, val, REG_WRITE_DWORD); + break; + } +} + +#endif + +/**************************************************************************** +PARAMETERS: +port - Port to write to + +RETURNS: +Value read from the I/O port + +REMARKS: +Performs an emulated 8-bit read from an I/O port. We handle special cases +that we need to emulate in here, and fall through to reflecting the write +through to the real hardware if we don't need to special case it. +****************************************************************************/ +u8 X86API BE_inb(X86EMU_pioAddr port) +{ + u8 val = 0; + +#if defined(DEBUG) || !defined(__i386__) + if (IS_VGA_PORT(port)){ + /*seems reading port 0x3c3 return the high 16 bit of io port*/ + if(port == 0x3c3) + val = LOG_inpb(port); + else + val = VGA_inpb(port); + } + else if (IS_TIMER_PORT(port)) + DB(printf("Can not interept TIMER port now!\n");) + else if (IS_SPKR_PORT(port)) + DB(printf("Can not interept SPEAKER port now!\n");) + else if (IS_CMOS_PORT(port)) + DB(printf("Can not interept CMOS port now!\n");) + else if (IS_PCI_PORT(port)) + val = PCI_inp(port, REG_READ_BYTE); + else if (port < 0x100) { + DB(printf("WARN: INVALID inb.%04X -> %02X\n", (u16) port, val);) + val = LOG_inpb(port); + } else +#endif + val = LOG_inpb(port); + return val; +} + +/**************************************************************************** +PARAMETERS: +port - Port to write to + +RETURNS: +Value read from the I/O port + +REMARKS: +Performs an emulated 16-bit read from an I/O port. We handle special cases +that we need to emulate in here, and fall through to reflecting the write +through to the real hardware if we don't need to special case it. +****************************************************************************/ +u16 X86API BE_inw(X86EMU_pioAddr port) +{ + u16 val = 0; + +#if defined(DEBUG) || !defined(__i386__) + if (IS_PCI_PORT(port)) + val = PCI_inp(port, REG_READ_WORD); + else if (port < 0x100) { + DB(printf("WARN: Maybe INVALID inw.%04X -> %04X\n", (u16) port, val);) + val = LOG_inpw(port); + } else +#endif + val = LOG_inpw(port); + return val; +} + +/**************************************************************************** +PARAMETERS: +port - Port to write to + +RETURNS: +Value read from the I/O port + +REMARKS: +Performs an emulated 32-bit read from an I/O port. We handle special cases +that we need to emulate in here, and fall through to reflecting the write +through to the real hardware if we don't need to special case it. +****************************************************************************/ +u32 X86API BE_inl(X86EMU_pioAddr port) +{ + u32 val = 0; + +#if defined(DEBUG) || !defined(__i386__) + if (IS_PCI_PORT(port)) + val = PCI_inp(port, REG_READ_DWORD); + else if (port < 0x100) { + val = LOG_inpd(port); + } else +#endif + val = LOG_inpd(port); + return val; +} + +/**************************************************************************** +PARAMETERS: +port - Port to write to +val - Value to write to port + +REMARKS: +Performs an emulated 8-bit write to an I/O port. We handle special cases +that we need to emulate in here, and fall through to reflecting the write +through to the real hardware if we don't need to special case it. +****************************************************************************/ +void X86API BE_outb(X86EMU_pioAddr port, u8 val) +{ +#if defined(DEBUG) || !defined(__i386__) + if (IS_VGA_PORT(port)) + VGA_outpb(port, val); + else if (IS_TIMER_PORT(port)) + DB(printf("Can not interept TIMER port now!\n");) + else if (IS_SPKR_PORT(port)) + DB(printf("Can not interept SPEAKER port now!\n");) + else if (IS_CMOS_PORT(port)) + DB(printf("Can not interept CMOS port now!\n");) + else if (IS_PCI_PORT(port)) + PCI_outp(port, val, REG_WRITE_BYTE); + else if (port < 0x100) { + DB(printf("WARN:Maybe INVALID outb.%04X <- %02X\n", (u16) port, val);) + LOG_outpb(port, val); + } else +#endif + LOG_outpb(port, val); +} + +/**************************************************************************** +PARAMETERS: +port - Port to write to +val - Value to write to port + +REMARKS: +Performs an emulated 16-bit write to an I/O port. We handle special cases +that we need to emulate in here, and fall through to reflecting the write +through to the real hardware if we don't need to special case it. +****************************************************************************/ +void X86API BE_outw(X86EMU_pioAddr port, u16 val) +{ +#if defined(DEBUG) || !defined(__i386__) + if (IS_VGA_PORT(port)) { + VGA_outpb(port, val); + VGA_outpb(port + 1, val >> 8); + } else if (IS_PCI_PORT(port)) + PCI_outp(port, val, REG_WRITE_WORD); + else if (port < 0x100) { + DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16) port, + val);) + LOG_outpw(port, val); + } else +#endif + LOG_outpw(port, val); +} + +/**************************************************************************** +PARAMETERS: +port - Port to write to +val - Value to write to port + +REMARKS: +Performs an emulated 32-bit write to an I/O port. We handle special cases +that we need to emulate in here, and fall through to reflecting the write +through to the real hardware if we don't need to special case it. +****************************************************************************/ +void X86API BE_outl(X86EMU_pioAddr port, u32 val) +{ +#if defined(DEBUG) || !defined(__i386__) + if (IS_PCI_PORT(port)) + PCI_outp(port, val, REG_WRITE_DWORD); + else if (port < 0x100) { + DB(printf("WARN: INVALID outl.%04X <- %08X\n", (u16) port,val);) + LOG_outpd(port, val); + } else +#endif + LOG_outpd(port, val); +} diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c new file mode 100644 index 00000000000..ed5437eec94 --- /dev/null +++ b/drivers/bios_emulator/bios.c @@ -0,0 +1,321 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. +* Jason Jin +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Module implementing the BIOS specific functions. +* +* Jason ported this file to u-boot to run the ATI video card +* video BIOS. +* +****************************************************************************/ + +#include "biosemui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number being serviced + +REMARKS: +Handler for undefined interrupts. +****************************************************************************/ +static void X86API undefined_intr(int intno) +{ + if (BE_rdw(intno * 4 + 2) == BIOS_SEG) { + DB(printf("biosEmu: undefined interrupt %xh called!\n", intno);) + } else + X86EMU_prepareForInt(intno); +} + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number being serviced + +REMARKS: +This function handles the default system BIOS Int 10h (the default is stored +in the Int 42h vector by the system BIOS at bootup). We only need to handle +a small number of special functions used by the BIOS during POST time. +****************************************************************************/ +static void X86API int42(int intno) +{ + if (M.x86.R_AH == 0x12 && M.x86.R_BL == 0x32) { + if (M.x86.R_AL == 0) { + /* Enable CPU accesses to video memory */ + PM_outpb(0x3c2, PM_inpb(0x3cc) | (u8) 0x02); + return; + } else if (M.x86.R_AL == 1) { + /* Disable CPU accesses to video memory */ + PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8) ~ 0x02); + return; + } +#ifdef DEBUG + else { + printf("int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n", + M.x86.R_AL); + } +#endif + } +#ifdef DEBUG + else { + printf("int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n", + M.x86.R_AH, M.x86.R_AL, M.x86.R_BL); + } +#endif +} + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number being serviced + +REMARKS: +This function handles the default system BIOS Int 10h. If the POST code +has not yet re-vectored the Int 10h BIOS interrupt vector, we handle this +by simply calling the int42 interrupt handler above. Very early in the +BIOS POST process, the vector gets replaced and we simply let the real +mode interrupt handler process the interrupt. +****************************************************************************/ +static void X86API int10(int intno) +{ + if (BE_rdw(intno * 4 + 2) == BIOS_SEG) + int42(intno); + else + X86EMU_prepareForInt(intno); +} + +/* Result codes returned by the PCI BIOS */ + +#define SUCCESSFUL 0x00 +#define FUNC_NOT_SUPPORT 0x81 +#define BAD_VENDOR_ID 0x83 +#define DEVICE_NOT_FOUND 0x86 +#define BAD_REGISTER_NUMBER 0x87 +#define SET_FAILED 0x88 +#define BUFFER_TOO_SMALL 0x89 + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number being serviced + +REMARKS: +This function handles the default Int 1Ah interrupt handler for the real +mode code, which provides support for the PCI BIOS functions. Since we only +want to allow the real mode BIOS code *only* see the PCI config space for +its own device, we only return information for the specific PCI config +space that we have passed in to the init function. This solves problems +when using the BIOS to warm boot a secondary adapter when there is an +identical adapter before it on the bus (some BIOS'es get confused in this +case). +****************************************************************************/ +static void X86API int1A(int unused) +{ + u16 pciSlot; + +#ifdef __KERNEL__ + u8 interface, subclass, baseclass; + + /* Initialise the PCI slot number */ + pciSlot = ((int)_BE_env.vgaInfo.bus << 8) | + ((int)_BE_env.vgaInfo.device << 3) | (int)_BE_env.vgaInfo.function; +#else +/* Fail if no PCI device information has been registered */ + if (!_BE_env.vgaInfo.pciInfo) + return; + + pciSlot = (u16) (_BE_env.vgaInfo.pciInfo->slot.i >> 8); +#endif + switch (M.x86.R_AX) { + case 0xB101: /* PCI bios present? */ + M.x86.R_AL = 0x00; /* no config space/special cycle generation support */ + M.x86.R_EDX = 0x20494350; /* " ICP" */ + M.x86.R_BX = 0x0210; /* Version 2.10 */ + M.x86.R_CL = 0; /* Max bus number in system */ + CLEAR_FLAG(F_CF); + break; + case 0xB102: /* Find PCI device */ + M.x86.R_AH = DEVICE_NOT_FOUND; +#ifdef __KERNEL__ + if (M.x86.R_DX == _BE_env.vgaInfo.VendorID && + M.x86.R_CX == _BE_env.vgaInfo.DeviceID && M.x86.R_SI == 0) { +#else + if (M.x86.R_DX == _BE_env.vgaInfo.pciInfo->VendorID && + M.x86.R_CX == _BE_env.vgaInfo.pciInfo->DeviceID && + M.x86.R_SI == 0) { +#endif + M.x86.R_AH = SUCCESSFUL; + M.x86.R_BX = pciSlot; + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB103: /* Find PCI class code */ + M.x86.R_AH = DEVICE_NOT_FOUND; +#ifdef __KERNEL__ + pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG, + &interface); + pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE, + &subclass); + pci_read_config_byte(_BE_env.vgaInfo.pcidev, + PCI_CLASS_DEVICE + 1, &baseclass); + if (M.x86.R_CL == interface && M.x86.R_CH == subclass + && (u8) (M.x86.R_ECX >> 16) == baseclass) { +#else + if (M.x86.R_CL == _BE_env.vgaInfo.pciInfo->Interface && + M.x86.R_CH == _BE_env.vgaInfo.pciInfo->SubClass && + (u8) (M.x86.R_ECX >> 16) == + _BE_env.vgaInfo.pciInfo->BaseClass) { +#endif + M.x86.R_AH = SUCCESSFUL; + M.x86.R_BX = pciSlot; + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB108: /* Read configuration byte */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; +#ifdef __KERNEL__ + pci_read_config_byte(_BE_env.vgaInfo.pcidev, M.x86.R_DI, + &M.x86.R_CL); +#else + M.x86.R_CL = + (u8) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_BYTE, + _BE_env.vgaInfo.pciInfo); +#endif + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB109: /* Read configuration word */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; +#ifdef __KERNEL__ + pci_read_config_word(_BE_env.vgaInfo.pcidev, M.x86.R_DI, + &M.x86.R_CX); +#else + M.x86.R_CX = + (u16) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_WORD, + _BE_env.vgaInfo.pciInfo); +#endif + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10A: /* Read configuration dword */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; +#ifdef __KERNEL__ + pci_read_config_dword(_BE_env.vgaInfo.pcidev, + M.x86.R_DI, &M.x86.R_ECX); +#else + M.x86.R_ECX = + (u32) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_DWORD, + _BE_env.vgaInfo.pciInfo); +#endif + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10B: /* Write configuration byte */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; +#ifdef __KERNEL__ + pci_write_config_byte(_BE_env.vgaInfo.pcidev, + M.x86.R_DI, M.x86.R_CL); +#else + PCI_accessReg(M.x86.R_DI, M.x86.R_CL, PCI_WRITE_BYTE, + _BE_env.vgaInfo.pciInfo); +#endif + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10C: /* Write configuration word */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; +#ifdef __KERNEL__ + pci_write_config_word(_BE_env.vgaInfo.pcidev, + M.x86.R_DI, M.x86.R_CX); +#else + PCI_accessReg(M.x86.R_DI, M.x86.R_CX, PCI_WRITE_WORD, + _BE_env.vgaInfo.pciInfo); +#endif + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10D: /* Write configuration dword */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; +#ifdef __KERNEL__ + pci_write_config_dword(_BE_env.vgaInfo.pcidev, + M.x86.R_DI, M.x86.R_ECX); +#else + PCI_accessReg(M.x86.R_DI, M.x86.R_ECX, PCI_WRITE_DWORD, + _BE_env.vgaInfo.pciInfo); +#endif + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + default: + printf("biosEmu/bios.int1a: unknown function AX=%#04x\n", + M.x86.R_AX); + } +} + +/**************************************************************************** +REMARKS: +This function initialises the BIOS emulation functions for the specific +PCI display device. We insulate the real mode BIOS from any other devices +on the bus, so that it will work correctly thinking that it is the only +device present on the bus (ie: avoiding any adapters present in from of +the device we are trying to control). +****************************************************************************/ +#define BE_constLE_32(v) ((((((v)&0xff00)>>8)|(((v)&0xff)<<8))<<16)|(((((v)&0xff000000)>>8)|(((v)&0x00ff0000)<<8))>>16)) + +void _BE_bios_init(u32 * intrTab) +{ + int i; + X86EMU_intrFuncs bios_intr_tab[256]; + + for (i = 0; i < 256; ++i) { + intrTab[i] = BE_constLE_32(BIOS_SEG << 16); + bios_intr_tab[i] = undefined_intr; + } + bios_intr_tab[0x10] = int10; + bios_intr_tab[0x1A] = int1A; + bios_intr_tab[0x42] = int42; + bios_intr_tab[0x6D] = int10; + X86EMU_setupIntrFuncs(bios_intr_tab); +} diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c new file mode 100644 index 00000000000..aca594ce711 --- /dev/null +++ b/drivers/bios_emulator/biosemu.c @@ -0,0 +1,370 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. +* Jason Jin +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Module implementing the system specific functions. This +* module is always compiled and linked in the OS depedent +* libraries, and never in a binary portable driver. +* +* Jason ported this file to u-boot to run the ATI video card BIOS +* in u-boot. Made all the video memory be emulated during the +* BIOS runing process which may affect the VGA function but the +* frambuffer function can work after run the BIOS. +* +****************************************************************************/ + +#include "biosemui.h" +#include + +BE_sysEnv _BE_env = {{0}}; +static X86EMU_memFuncs _BE_mem __attribute__((section(".got2"))) = { + BE_rdb, + BE_rdw, + BE_rdl, + BE_wrb, + BE_wrw, + BE_wrl, + }; + +static X86EMU_pioFuncs _BE_pio __attribute__((section(".got2"))) = { + BE_inb, + BE_inw, + BE_inl, + BE_outb, + BE_outw, + BE_outl, + }; + +#define OFF(addr) (u16)(((addr) >> 0) & 0xffff) +#define SEG(addr) (u16)(((addr) >> 4) & 0xf000) + +/**************************************************************************** +PARAMETERS: +debugFlags - Flags to enable debugging options (debug builds only) +memSize - Amount of memory to allocate for real mode machine +info - Pointer to default VGA device information + +REMARKS: +This functions initialises the BElib, and uses the passed in +BIOS image as the BIOS that is used and emulated at 0xC0000. +****************************************************************************/ +int X86API BE_init(u32 debugFlags, int memSize, BE_VGAInfo * info, int shared) +{ +#if !defined(__DRIVER__) && !defined(__KERNEL__) + + PM_init(); +#endif + memset(&M, 0, sizeof(M)); + if (memSize < 20480){ + printf("Emulator requires at least 20Kb of memory!\n"); + return 0; + } + + M.mem_base = (unsigned long)malloc(memSize); + + if (M.mem_base == NULL){ + printf("Biosemu:Out of memory!"); + return 0; + } + M.mem_size = memSize; + + _BE_env.emulateVGA = 0; + _BE_env.busmem_base = (unsigned long)malloc(128 * 1024); + if (_BE_env.busmem_base == NULL){ + printf("Biosemu:Out of memory!"); + return 0; + } + M.x86.debug = debugFlags; + _BE_bios_init((u32*)info->LowMem); + X86EMU_setupMemFuncs(&_BE_mem); + X86EMU_setupPioFuncs(&_BE_pio); + BE_setVGA(info); + return 1; +} + +/**************************************************************************** +PARAMETERS: +info - Pointer to VGA device information to make current + +REMARKS: +This function sets the VGA BIOS functions in the emulator to point to the +specific VGA BIOS in use. This includes swapping the BIOS interrupt +vectors, BIOS image and BIOS data area to the new BIOS. This allows the +real mode BIOS to be swapped without resetting the entire emulator. +****************************************************************************/ +void X86API BE_setVGA(BE_VGAInfo * info) +{ + +#ifdef __KERNEL__ + _BE_env.vgaInfo.function = info->function; + _BE_env.vgaInfo.device = info->device; + _BE_env.vgaInfo.bus = info->bus; + _BE_env.vgaInfo.pcidev = info->pcidev; +#else + _BE_env.vgaInfo.pciInfo = info->pciInfo; +#endif + _BE_env.vgaInfo.BIOSImage = info->BIOSImage; + if (info->BIOSImage) { + _BE_env.biosmem_base = (ulong) info->BIOSImage; + _BE_env.biosmem_limit = 0xC0000 + info->BIOSImageLen - 1; + } else { + _BE_env.biosmem_base = _BE_env.busmem_base + 0x20000; + _BE_env.biosmem_limit = 0xC7FFF; + } + if (*((u32 *) info->LowMem) == 0) + _BE_bios_init((u32 *) info->LowMem); + memcpy((u8 *) M.mem_base, info->LowMem, sizeof(info->LowMem)); +} + +/**************************************************************************** +PARAMETERS: +info - Pointer to VGA device information to retrieve current + +REMARKS: +This function returns the VGA BIOS functions currently active in the +emulator, so they can be restored at a later date. +****************************************************************************/ +void X86API BE_getVGA(BE_VGAInfo * info) +{ +#ifdef __KERNEL__ + info->function = _BE_env.vgaInfo.function; + info->device = _BE_env.vgaInfo.device; + info->bus = _BE_env.vgaInfo.bus; + info->pcidev = _BE_env.vgaInfo.pcidev; +#else + info->pciInfo = _BE_env.vgaInfo.pciInfo; +#endif + info->BIOSImage = _BE_env.vgaInfo.BIOSImage; + memcpy(info->LowMem, (u8 *) M.mem_base, sizeof(info->LowMem)); +} + +/**************************************************************************** +PARAMETERS: +r_seg - Segment for pointer to convert +r_off - Offset for pointer to convert + +REMARKS: +This function maps a real mode pointer in the emulator memory to a protected +mode pointer that can be used to directly access the memory. + +NOTE: The memory is *always* in little endian format, son on non-x86 + systems you will need to do endian translations to access this + memory. +****************************************************************************/ +void *X86API BE_mapRealPointer(uint r_seg, uint r_off) +{ + u32 addr = ((u32) r_seg << 4) + r_off; + + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { + return (void *)(_BE_env.biosmem_base + addr - 0xC0000); + } else if (addr >= 0xA0000 && addr <= 0xFFFFF) { + return (void *)(_BE_env.busmem_base + addr - 0xA0000); + } + return (void *)(M.mem_base + addr); +} + +/**************************************************************************** +PARAMETERS: +len - Return the length of the VESA buffer +rseg - Place to store VESA buffer segment +roff - Place to store VESA buffer offset + +REMARKS: +This function returns the address of the VESA transfer buffer in real +_BE_piomode emulator memory. The VESA transfer buffer is always 1024 bytes long, +and located at 15Kb into the start of the real mode memory (16Kb is where +we put the real mode code we execute for issuing interrupts). + +NOTE: The memory is *always* in little endian format, son on non-x86 + systems you will need to do endian translations to access this + memory. +****************************************************************************/ +void *X86API BE_getVESABuf(uint * len, uint * rseg, uint * roff) +{ + *len = 1024; + *rseg = SEG(0x03C00); + *roff = OFF(0x03C00); + return (void *)(M.mem_base + ((u32) * rseg << 4) + *roff); +} + +/**************************************************************************** +REMARKS: +Cleans up and exits the emulator. +****************************************************************************/ +void X86API BE_exit(void) +{ + free(M.mem_base); + free(_BE_env.busmem_base); +} + +/**************************************************************************** +PARAMETERS: +seg - Segment of code to call +off - Offset of code to call +regs - Real mode registers to load +sregs - Real mode segment registers to load + +REMARKS: +This functions calls a real mode far function at the specified address, +and loads all the x86 registers from the passed in registers structure. +On exit the registers returned from the call are returned in the same +structures. +****************************************************************************/ +void X86API BE_callRealMode(uint seg, uint off, RMREGS * regs, RMSREGS * sregs) +{ + M.x86.R_EAX = regs->e.eax; + M.x86.R_EBX = regs->e.ebx; + M.x86.R_ECX = regs->e.ecx; + M.x86.R_EDX = regs->e.edx; + M.x86.R_ESI = regs->e.esi; + M.x86.R_EDI = regs->e.edi; + M.x86.R_DS = sregs->ds; + M.x86.R_ES = sregs->es; + M.x86.R_FS = sregs->fs; + M.x86.R_GS = sregs->gs; + + ((u8 *) M.mem_base)[0x4000] = 0x9A; + ((u8 *) M.mem_base)[0x4001] = (u8) off; + ((u8 *) M.mem_base)[0x4002] = (u8) (off >> 8); + ((u8 *) M.mem_base)[0x4003] = (u8) seg; + ((u8 *) M.mem_base)[0x4004] = (u8) (seg >> 8); + ((u8 *) M.mem_base)[0x4005] = 0xF1; /* Illegal op-code */ + M.x86.R_CS = SEG(0x04000); + M.x86.R_IP = OFF(0x04000); + + M.x86.R_SS = SEG(M.mem_size - 2); + M.x86.R_SP = OFF(M.mem_size - 2) + 2; + + X86EMU_exec(); + + regs->e.cflag = M.x86.R_EFLG & F_CF; + regs->e.eax = M.x86.R_EAX; + regs->e.ebx = M.x86.R_EBX; + regs->e.ecx = M.x86.R_ECX; + regs->e.edx = M.x86.R_EDX; + regs->e.esi = M.x86.R_ESI; + regs->e.edi = M.x86.R_EDI; + sregs->ds = M.x86.R_DS; + sregs->es = M.x86.R_ES; + sregs->fs = M.x86.R_FS; + sregs->gs = M.x86.R_GS; +} + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number to execute +in - Real mode registers to load +out - Place to store resulting real mode registers + +REMARKS: +This functions calls a real mode interrupt function at the specified address, +and loads all the x86 registers from the passed in registers structure. +On exit the registers returned from the call are returned in out stucture. +****************************************************************************/ +int X86API BE_int86(int intno, RMREGS * in, RMREGS * out) +{ + M.x86.R_EAX = in->e.eax; + M.x86.R_EBX = in->e.ebx; + M.x86.R_ECX = in->e.ecx; + M.x86.R_EDX = in->e.edx; + M.x86.R_ESI = in->e.esi; + M.x86.R_EDI = in->e.edi; + ((u8 *) M.mem_base)[0x4000] = 0xCD; + ((u8 *) M.mem_base)[0x4001] = (u8) intno; + ((u8 *) M.mem_base)[0x4002] = 0xF1; + M.x86.R_CS = SEG(0x04000); + M.x86.R_IP = OFF(0x04000); + + M.x86.R_SS = SEG(M.mem_size - 1); + M.x86.R_SP = OFF(M.mem_size - 1) - 1; + + X86EMU_exec(); + out->e.cflag = M.x86.R_EFLG & F_CF; + out->e.eax = M.x86.R_EAX; + out->e.ebx = M.x86.R_EBX; + out->e.ecx = M.x86.R_ECX; + out->e.edx = M.x86.R_EDX; + out->e.esi = M.x86.R_ESI; + out->e.edi = M.x86.R_EDI; + return out->x.ax; +} + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number to execute +in - Real mode registers to load +out - Place to store resulting real mode registers +sregs - Real mode segment registers to load + +REMARKS: +This functions calls a real mode interrupt function at the specified address, +and loads all the x86 registers from the passed in registers structure. +On exit the registers returned from the call are returned in out stucture. +****************************************************************************/ +int X86API BE_int86x(int intno, RMREGS * in, RMREGS * out, RMSREGS * sregs) +{ + M.x86.R_EAX = in->e.eax; + M.x86.R_EBX = in->e.ebx; + M.x86.R_ECX = in->e.ecx; + M.x86.R_EDX = in->e.edx; + M.x86.R_ESI = in->e.esi; + M.x86.R_EDI = in->e.edi; + M.x86.R_DS = sregs->ds; + M.x86.R_ES = sregs->es; + M.x86.R_FS = sregs->fs; + M.x86.R_GS = sregs->gs; + ((u8 *) M.mem_base)[0x4000] = 0xCD; + ((u8 *) M.mem_base)[0x4001] = (u8) intno; + ((u8 *) M.mem_base)[0x4002] = 0xF1; + M.x86.R_CS = SEG(0x04000); + M.x86.R_IP = OFF(0x04000); + + M.x86.R_SS = SEG(M.mem_size - 1); + M.x86.R_SP = OFF(M.mem_size - 1) - 1; + + X86EMU_exec(); + out->e.cflag = M.x86.R_EFLG & F_CF; + out->e.eax = M.x86.R_EAX; + out->e.ebx = M.x86.R_EBX; + out->e.ecx = M.x86.R_ECX; + out->e.edx = M.x86.R_EDX; + out->e.esi = M.x86.R_ESI; + out->e.edi = M.x86.R_EDI; + sregs->ds = M.x86.R_DS; + sregs->es = M.x86.R_ES; + sregs->fs = M.x86.R_FS; + sregs->gs = M.x86.R_GS; + return out->x.ax; +} diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h new file mode 100644 index 00000000000..3265ac15cb6 --- /dev/null +++ b/drivers/bios_emulator/biosemui.h @@ -0,0 +1,169 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. +* Jason Jin +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Internal header file for the BIOS emulator library. +* +* Jason ported this file to u-boot, Added some architecture +* related Macro. +* +****************************************************************************/ + +#ifndef __BIOSEMUI_H +#define __BIOSEMUI_H + +#include "biosemu.h" +#include +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) do{}while(0); +#endif + +#define BIOS_SEG 0xfff0 +extern X86EMU_sysEnv _X86EMU_env; +#define M _X86EMU_env + +/* Macros to read and write values to x86 emulator memory. Memory is always + * considered to be little endian, so we use macros to do endian swapping + * where necessary. + */ + +#ifdef __BIG_ENDIAN__ +#define readb_le(base) *((u8*)(base)) +#define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8)) +#define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \ + ((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base) + 3) << 24)) +#define writeb_le(base, v) *((u8*)(base)) = (v) +#define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ + writeb_le(base + 1, (v >> 8) & 0xff) +#define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ + writeb_le(base + 1, (v >> 8) & 0xff), \ + writeb_le(base + 2, (v >> 16) & 0xff), \ + writeb_le(base + 3, (v >> 24) & 0xff) +#else +#define readb_le(base) *((u8*)(base)) +#define readw_le(base) *((u16*)(base)) +#define readl_le(base) *((u32*)(base)) +#define writeb_le(base, v) *((u8*)(base)) = (v) +#define writew_le(base, v) *((u16*)(base)) = (v) +#define writel_le(base, v) *((u32*)(base)) = (v) +#endif + +/**************************************************************************** +REMARKS: +Function codes passed to the emulated I/O port functions to determine the +type of operation to perform. +****************************************************************************/ +typedef enum { + REG_READ_BYTE = 0, + REG_READ_WORD = 1, + REG_READ_DWORD = 2, + REG_WRITE_BYTE = 3, + REG_WRITE_WORD = 4, + REG_WRITE_DWORD = 5 +} RegisterFlags; + +/**************************************************************************** +REMARKS: +Function codes passed to the emulated I/O port functions to determine the +type of operation to perform. +****************************************************************************/ +typedef enum { + PORT_BYTE = 1, + PORT_WORD = 2, + PORT_DWORD = 3, +} PortInfoFlags; + +/**************************************************************************** +REMARKS: +Data structure used to describe the details for the BIOS emulator system +environment as used by the X86 emulator library. + +HEADER: +biosemu.h + +MEMBERS: +type - Type of port access (1 = byte, 2 = word, 3 = dword) +defVal - Default power on value +finalVal - Final value +****************************************************************************/ +typedef struct { + u8 type; + u32 defVal; + u32 finalVal; +} BE_portInfo; + +#define PM_inpb(port) inb(port+VIDEO_IO_OFFSET) +#define PM_inpw(port) inw(port+VIDEO_IO_OFFSET) +#define PM_inpd(port) inl(port+VIDEO_IO_OFFSET) +#define PM_outpb(port,val) outb(val,port+VIDEO_IO_OFFSET) +#define PM_outpw(port,val) outw(val,port+VIDEO_IO_OFFSET) +#define PM_outpd(port,val) outl(val,port+VIDEO_IO_OFFSET) + +#define LOG_inpb(port) PM_inpb(port) +#define LOG_inpw(port) PM_inpw(port) +#define LOG_inpd(port) PM_inpd(port) +#define LOG_outpb(port,val) PM_outpb(port,val) +#define LOG_outpw(port,val) PM_outpw(port,val) +#define LOG_outpd(port,val) PM_outpd(port,val) + +/*-------------------------- Function Prototypes --------------------------*/ + +/* bios.c */ + +void _BE_bios_init(u32 * intrTab); +void _BE_setup_funcs(void); + +/* besys.c */ +#define DEBUG_IO() (M.x86.debug & DEBUG_IO_TRACE_F) + +u8 X86API BE_rdb(u32 addr); +u16 X86API BE_rdw(u32 addr); +u32 X86API BE_rdl(u32 addr); +void X86API BE_wrb(u32 addr, u8 val); +void X86API BE_wrw(u32 addr, u16 val); +void X86API BE_wrl(u32 addr, u32 val); + +u8 X86API BE_inb(X86EMU_pioAddr port); +u16 X86API BE_inw(X86EMU_pioAddr port); +u32 X86API BE_inl(X86EMU_pioAddr port); +void X86API BE_outb(X86EMU_pioAddr port, u8 val); +void X86API BE_outw(X86EMU_pioAddr port, u16 val); +void X86API BE_outl(X86EMU_pioAddr port, u32 val); +#endif +/* __BIOSEMUI_H */ diff --git a/drivers/bios_emulator/include/biosemu.h b/drivers/bios_emulator/include/biosemu.h new file mode 100644 index 00000000000..13cb3170c18 --- /dev/null +++ b/drivers/bios_emulator/include/biosemu.h @@ -0,0 +1,392 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for the real mode x86 BIOS emulator, which is +* used to warmboot any number of VGA compatible PCI/AGP +* controllers under any OS, on any processor family that +* supports PCI. We also allow the user application to call +* real mode BIOS functions and Int 10h functions (including +* the VESA BIOS). +* +****************************************************************************/ + +#ifndef __BIOSEMU_H +#define __BIOSEMU_H + +#ifdef __KERNEL__ +#include "x86emu.h" +#else +#include "x86emu.h" +#include "pmapi.h" +#include "pcilib.h" +#endif + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +#ifndef __KERNEL__ +/**************************************************************************** +REMARKS: +Data structure used to describe the details specific to a particular VGA +controller. This information is used to allow the VGA controller to be +swapped on the fly within the BIOS emulator. + +HEADER: +biosemu.h + +MEMBERS: +pciInfo - PCI device information block for the controller +BIOSImage - Pointer to a read/write copy of the BIOS image +BIOSImageLen - Length of the BIOS image +LowMem - Copy of key low memory areas +****************************************************************************/ +typedef struct { + PCIDeviceInfo *pciInfo; + void *BIOSImage; + ulong BIOSImageLen; + uchar LowMem[1536]; +} BE_VGAInfo; +#else +/**************************************************************************** +REMARKS: +Data structure used to describe the details for the BIOS emulator system +environment as used by the X86 emulator library. + +HEADER: +biosemu.h + +MEMBERS: +vgaInfo - VGA BIOS information structure +biosmem_base - Base of the BIOS image +biosmem_limit - Limit of the BIOS image +busmem_base - Base of the VGA bus memory +****************************************************************************/ +typedef struct { + int function; + int device; + int bus; + u32 VendorID; + u32 DeviceID; + pci_dev_t pcidev; + void *BIOSImage; + u32 BIOSImageLen; + u8 LowMem[1536]; +} BE_VGAInfo; + +#endif /* __KERNEL__ */ + +#define CRT_C 24 /* 24 CRT Controller Registers */ +#define ATT_C 21 /* 21 Attribute Controller Registers */ +#define GRA_C 9 /* 9 Graphics Controller Registers */ +#define SEQ_C 5 /* 5 Sequencer Registers */ +#define PAL_C 768 /* 768 Palette Registers */ + +/**************************************************************************** +REMARKS: +Data structure used to describe the details for the BIOS emulator system +environment as used by the X86 emulator library. + +HEADER: +biosemu.h + +MEMBERS: +vgaInfo - VGA BIOS information structure +biosmem_base - Base of the BIOS image +biosmem_limit - Limit of the BIOS image +busmem_base - Base of the VGA bus memory +timer - Timer used to emulate PC timer ports +timer0 - Latched value for timer 0 +timer0Latched - True if timer 0 value was just latched +timer2 - Current value for timer 2 +emulateVGA - True to emulate VGA I/O and memory accesses +****************************************************************************/ + +typedef struct { + BE_VGAInfo vgaInfo; + ulong biosmem_base; + ulong biosmem_limit; + ulong busmem_base; + + u32 timer0; + int timer0Latched; + u32 timer1; + int timer1Latched; + u32 timer2; + int timer2Latched; + + int emulateVGA; + u8 emu61; + u8 emu70; + int flipFlop3C0; + u32 configAddress; + u8 emu3C0; + u8 emu3C1[ATT_C]; + u8 emu3C2; + u8 emu3C4; + u8 emu3C5[SEQ_C]; + u8 emu3C6; + uint emu3C7; + uint emu3C8; + u8 emu3C9[PAL_C]; + u8 emu3CE; + u8 emu3CF[GRA_C]; + u8 emu3D4; + u8 emu3D5[CRT_C]; + u8 emu3DA; + +} BE_sysEnv; + +#ifdef __KERNEL__ + +/* Define some types when compiling for the Linux kernel that normally + * come from the SciTech PM library. + */ + +/**************************************************************************** +REMARKS: +Structure describing the 32-bit extended x86 CPU registers + +HEADER: +pmapi.h + +MEMBERS: +eax - Value of the EAX register +ebx - Value of the EBX register +ecx - Value of the ECX register +edx - Value of the EDX register +esi - Value of the ESI register +edi - Value of the EDI register +cflag - Value of the carry flag +****************************************************************************/ +typedef struct { + u32 eax; + u32 ebx; + u32 ecx; + u32 edx; + u32 esi; + u32 edi; + u32 cflag; +} RMDWORDREGS; + +/**************************************************************************** +REMARKS: +Structure describing the 16-bit x86 CPU registers + +HEADER: +pmapi.h + +MEMBERS: +ax - Value of the AX register +bx - Value of the BX register +cx - Value of the CX register +dx - Value of the DX register +si - Value of the SI register +di - Value of the DI register +cflag - Value of the carry flag +****************************************************************************/ +#ifdef __BIG_ENDIAN__ +typedef struct { + u16 ax_hi, ax; + u16 bx_hi, bx; + u16 cx_hi, cx; + u16 dx_hi, dx; + u16 si_hi, si; + u16 di_hi, di; + u16 cflag_hi, cflag; +} RMWORDREGS; +#else +typedef struct { + u16 ax, ax_hi; + u16 bx, bx_hi; + u16 cx, cx_hi; + u16 dx, dx_hi; + u16 si, si_hi; + u16 di, di_hi; + u16 cflag, cflag_hi; +} RMWORDREGS; +#endif + +/**************************************************************************** +REMARKS: +Structure describing the 8-bit x86 CPU registers + +HEADER: +pmapi.h + +MEMBERS: +al - Value of the AL register +ah - Value of the AH register +bl - Value of the BL register +bh - Value of the BH register +cl - Value of the CL register +ch - Value of the CH register +dl - Value of the DL register +dh - Value of the DH register +****************************************************************************/ +#ifdef __BIG_ENDIAN__ +typedef struct { + u16 ax_hi; + u8 ah, al; + u16 bx_hi; + u8 bh, bl; + u16 cx_hi; + u8 ch, cl; + u16 dx_hi; + u8 dh, dl; +} RMBYTEREGS; +#else +typedef struct { + u8 al; + u8 ah; + u16 ax_hi; + u8 bl; + u8 bh; + u16 bx_hi; + u8 cl; + u8 ch; + u16 cx_hi; + u8 dl; + u8 dh; + u16 dx_hi; +} RMBYTEREGS; +#endif + +/**************************************************************************** +REMARKS: +Structure describing all the x86 CPU registers + +HEADER: +pmapi.h + +MEMBERS: +e - Member to access registers as 32-bit values +x - Member to access registers as 16-bit values +h - Member to access registers as 8-bit values +****************************************************************************/ +typedef union { + RMDWORDREGS e; + RMWORDREGS x; + RMBYTEREGS h; +} RMREGS; + +/**************************************************************************** +REMARKS: +Structure describing all the x86 segment registers + +HEADER: +pmapi.h + +MEMBERS: +es - ES segment register +cs - CS segment register +ss - SS segment register +ds - DS segment register +fs - FS segment register +gs - GS segment register +****************************************************************************/ +typedef struct { + u16 es; + u16 cs; + u16 ss; + u16 ds; + u16 fs; + u16 gs; +} RMSREGS; + +#endif /* __KERNEL__ */ + +#ifndef __KERNEL__ + +/**************************************************************************** +REMARKS: +Structure defining all the BIOS Emulator API functions as exported from +the Binary Portable DLL. +{secret} +****************************************************************************/ +typedef struct { + ulong dwSize; + ibool(PMAPIP BE_init) (u32 debugFlags, int memSize, BE_VGAInfo * info); + void (PMAPIP BE_setVGA) (BE_VGAInfo * info); + void (PMAPIP BE_getVGA) (BE_VGAInfo * info); + void *(PMAPIP BE_mapRealPointer) (uint r_seg, uint r_off); + void *(PMAPIP BE_getVESABuf) (uint * len, uint * rseg, uint * roff); + void (PMAPIP BE_callRealMode) (uint seg, uint off, RMREGS * regs, + RMSREGS * sregs); + int (PMAPIP BE_int86) (int intno, RMREGS * in, RMREGS * out); + int (PMAPIP BE_int86x) (int intno, RMREGS * in, RMREGS * out, + RMSREGS * sregs); + void *reserved1; + void (PMAPIP BE_exit) (void); +} BE_exports; + +/**************************************************************************** +REMARKS: +Function pointer type for the Binary Portable DLL initialisation entry point. +{secret} +****************************************************************************/ +typedef BE_exports *(PMAPIP BE_initLibrary_t) (PM_imports * PMImp); +#endif + +#pragma pack() + +/*---------------------------- Global variables ---------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* {secret} Global BIOS emulator system environment */ + extern BE_sysEnv _BE_env; + +/*-------------------------- Function Prototypes --------------------------*/ + +/* BIOS emulator library entry points */ + int X86API BE_init(u32 debugFlags, int memSize, BE_VGAInfo * info, + int shared); + void X86API BE_setVGA(BE_VGAInfo * info); + void X86API BE_getVGA(BE_VGAInfo * info); + void X86API BE_setDebugFlags(u32 debugFlags); + void *X86API BE_mapRealPointer(uint r_seg, uint r_off); + void *X86API BE_getVESABuf(uint * len, uint * rseg, uint * roff); + void X86API BE_callRealMode(uint seg, uint off, RMREGS * regs, + RMSREGS * sregs); + int X86API BE_int86(int intno, RMREGS * in, RMREGS * out); + int X86API BE_int86x(int intno, RMREGS * in, RMREGS * out, + RMSREGS * sregs); + void X86API BE_exit(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif +#endif /* __BIOSEMU_H */ diff --git a/drivers/bios_emulator/include/x86emu.h b/drivers/bios_emulator/include/x86emu.h new file mode 100644 index 00000000000..6004beb05de --- /dev/null +++ b/drivers/bios_emulator/include/x86emu.h @@ -0,0 +1,191 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for public specific functions. +* Any application linking against us should only +* include this header +* +****************************************************************************/ + +#ifndef __X86EMU_X86EMU_H +#define __X86EMU_X86EMU_H + +#include +#include +#include +#include +#define X86API +#define X86APIP * +typedef u16 X86EMU_pioAddr; + +#include "x86emu/regs.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/**************************************************************************** +REMARKS: +Data structure containing ponters to programmed I/O functions used by the +emulator. This is used so that the user program can hook all programmed +I/O for the emulator to handled as necessary by the user program. By +default the emulator contains simple functions that do not do access the +hardware in any way. To allow the emualtor access the hardware, you will +need to override the programmed I/O functions using the X86EMU_setupPioFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +inb - Function to read a byte from an I/O port +inw - Function to read a word from an I/O port +inl - Function to read a dword from an I/O port +outb - Function to write a byte to an I/O port +outw - Function to write a word to an I/O port +outl - Function to write a dword to an I/O port +****************************************************************************/ +typedef struct { + u8(X86APIP inb) (X86EMU_pioAddr addr); + u16(X86APIP inw) (X86EMU_pioAddr addr); + u32(X86APIP inl) (X86EMU_pioAddr addr); + void (X86APIP outb) (X86EMU_pioAddr addr, u8 val); + void (X86APIP outw) (X86EMU_pioAddr addr, u16 val); + void (X86APIP outl) (X86EMU_pioAddr addr, u32 val); +} X86EMU_pioFuncs; + +/**************************************************************************** +REMARKS: +Data structure containing ponters to memory access functions used by the +emulator. This is used so that the user program can hook all memory +access functions as necessary for the emulator. By default the emulator +contains simple functions that only access the internal memory of the +emulator. If you need specialised functions to handle access to different +types of memory (ie: hardware framebuffer accesses and BIOS memory access +etc), you will need to override this using the X86EMU_setupMemFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +rdb - Function to read a byte from an address +rdw - Function to read a word from an address +rdl - Function to read a dword from an address +wrb - Function to write a byte to an address +wrw - Function to write a word to an address +wrl - Function to write a dword to an address +****************************************************************************/ +typedef struct { + u8(X86APIP rdb) (u32 addr); + u16(X86APIP rdw) (u32 addr); + u32(X86APIP rdl) (u32 addr); + void (X86APIP wrb) (u32 addr, u8 val); + void (X86APIP wrw) (u32 addr, u16 val); + void (X86APIP wrl) (u32 addr, u32 val); +} X86EMU_memFuncs; + +/**************************************************************************** + Here are the default memory read and write + function in case they are needed as fallbacks. +***************************************************************************/ +extern u8 X86API rdb(u32 addr); +extern u16 X86API rdw(u32 addr); +extern u32 X86API rdl(u32 addr); +extern void X86API wrb(u32 addr, u8 val); +extern void X86API wrw(u32 addr, u16 val); +extern void X86API wrl(u32 addr, u32 val); + +#pragma pack() + +/*--------------------- type definitions -----------------------------------*/ + +typedef void (X86APIP X86EMU_intrFuncs) (int num); +extern X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + + void X86EMU_setupMemFuncs(X86EMU_memFuncs * funcs); + void X86EMU_setupPioFuncs(X86EMU_pioFuncs * funcs); + void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); + void X86EMU_prepareForInt(int num); + +/* decode.c */ + + void X86EMU_exec(void); + void X86EMU_halt_sys(void); + +#ifdef DEBUG +#define HALT_SYS() \ + printf("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ + X86EMU_halt_sys() +#else +#define HALT_SYS() X86EMU_halt_sys() +#endif + +/* Debug options */ + +#define DEBUG_DECODE_F 0x0001 /* print decoded instruction */ +#define DEBUG_TRACE_F 0x0002 /* dump regs before/after execution */ +#define DEBUG_STEP_F 0x0004 +#define DEBUG_DISASSEMBLE_F 0x0008 +#define DEBUG_BREAK_F 0x0010 +#define DEBUG_SVC_F 0x0020 +#define DEBUG_SAVE_CS_IP 0x0040 +#define DEBUG_FS_F 0x0080 +#define DEBUG_PROC_F 0x0100 +#define DEBUG_SYSINT_F 0x0200 /* bios system interrupts. */ +#define DEBUG_TRACECALL_F 0x0400 +#define DEBUG_INSTRUMENT_F 0x0800 +#define DEBUG_MEM_TRACE_F 0x1000 +#define DEBUG_IO_TRACE_F 0x2000 +#define DEBUG_TRACECALL_REGS_F 0x4000 +#define DEBUG_DECODE_NOPRINT_F 0x8000 +#define DEBUG_EXIT 0x10000 +#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) + + void X86EMU_trace_regs(void); + void X86EMU_trace_xregs(void); + void X86EMU_dump_memory(u16 seg, u16 off, u32 amt); + int X86EMU_trace_on(void); + int X86EMU_trace_off(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif +#endif /* __X86EMU_X86EMU_H */ diff --git a/drivers/bios_emulator/include/x86emu/debug.h b/drivers/bios_emulator/include/x86emu/debug.h new file mode 100644 index 00000000000..35e1e9a92fb --- /dev/null +++ b/drivers/bios_emulator/include/x86emu/debug.h @@ -0,0 +1,209 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for debug definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_DEBUG_H +#define __X86EMU_DEBUG_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* checks to be enabled for "runtime" */ + +#define CHECK_IP_FETCH_F 0x1 +#define CHECK_SP_ACCESS_F 0x2 +#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ +#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset */ + +#ifdef DEBUG +# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) +# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) +# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) +# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) +#else +# define CHECK_IP_FETCH() +# define CHECK_SP_ACCESS() +# define CHECK_MEM_ACCESS() +# define CHECK_DATA_ACCESS() +#endif + +#ifdef DEBUG +# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) +# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) +# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) +# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) +# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) +# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) +# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) +# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_CS_IP) + +# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) +# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) +# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) +# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) +# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) +# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) +# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) +# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) +# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) +#else +# define DEBUG_INSTRUMENT() 0 +# define DEBUG_DECODE() 0 +# define DEBUG_TRACE() 0 +# define DEBUG_STEP() 0 +# define DEBUG_DISASSEMBLE() 0 +# define DEBUG_BREAK() 0 +# define DEBUG_SVC() 0 +# define DEBUG_SAVE_IP_CS() 0 +# define DEBUG_FS() 0 +# define DEBUG_PROC() 0 +# define DEBUG_SYSINT() 0 +# define DEBUG_TRACECALL() 0 +# define DEBUG_TRACECALLREGS() 0 +# define DEBUG_SYS() 0 +# define DEBUG_MEM_TRACE() 0 +# define DEBUG_IO_TRACE() 0 +# define DEBUG_DECODE_NOPRINT() 0 +#endif + +#ifdef DEBUG + +# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ + x86emu_decode_printf(x) +# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ + x86emu_decode_printf2(x,y) + +/* + * The following allow us to look at the bytes of an instruction. The + * first INCR_INSTRN_LEN, is called everytime bytes are consumed in + * the decoding process. The SAVE_IP_CS is called initially when the + * major opcode of the instruction is accessed. + */ +#define INC_DECODED_INST_LEN(x) \ + if (DEBUG_DECODE()) \ + x86emu_inc_decoded_inst_len(x) + +#define SAVE_IP_CS(x,y) \ + if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ + | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ + M.x86.saved_cs = x; \ + M.x86.saved_ip = y; \ + } +#else +# define INC_DECODED_INST_LEN(x) +# define DECODE_PRINTF(x) +# define DECODE_PRINTF2(x,y) +# define SAVE_IP_CS(x,y) +#endif + +#ifdef DEBUG +#define TRACE_REGS() \ + if (DEBUG_DISASSEMBLE()) { \ + x86emu_just_disassemble(); \ + goto EndOfTheInstructionProcedure; \ + } \ + if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() +#else +# define TRACE_REGS() +#endif + +#ifdef DEBUG +# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() +#else +# define SINGLE_STEP() +#endif + +#define TRACE_AND_STEP() \ + TRACE_REGS(); \ + SINGLE_STEP() + +#ifdef DEBUG +# define START_OF_INSTR() +# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); +# define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); +#else +# define START_OF_INSTR() +# define END_OF_INSTR() +# define END_OF_INSTR_NO_TRACE() +#endif + +#ifdef DEBUG +# define CALL_TRACE(u,v,w,x,s) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); +# define RETURN_TRACE(n,u,v) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: %s\n",u,v,n); +#else +# define CALL_TRACE(u,v,w,x,s) +# define RETURN_TRACE(n,u,v) +#endif + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + + extern void x86emu_inc_decoded_inst_len(int x); + extern void x86emu_decode_printf(char *x); + extern void x86emu_decode_printf2(char *x, int y); + extern void x86emu_just_disassemble(void); + extern void x86emu_single_step(void); + extern void x86emu_end_instr(void); + extern void x86emu_dump_regs(void); + extern void x86emu_dump_xregs(void); + extern void x86emu_print_int_vect(u16 iv); + extern void x86emu_instrument_instruction(void); + extern void x86emu_check_ip_access(void); + extern void x86emu_check_sp_access(void); + extern void x86emu_check_mem_access(u32 p); + extern void x86emu_check_data_access(uint s, uint o); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif +#endif /* __X86EMU_DEBUG_H */ diff --git a/drivers/bios_emulator/include/x86emu/decode.h b/drivers/bios_emulator/include/x86emu/decode.h new file mode 100644 index 00000000000..77769f0094c --- /dev/null +++ b/drivers/bios_emulator/include/x86emu/decode.h @@ -0,0 +1,88 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for instruction decoding logic. +* +****************************************************************************/ + +#ifndef __X86EMU_DECODE_H +#define __X86EMU_DECODE_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Instruction Decoding Stuff */ + +#define FETCH_DECODE_MODRM(mod,rh,rl) fetch_decode_modrm(&mod,&rh,&rl) +#define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r) +#define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r) +#define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r) +#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void x86emu_intr_raise (u8 type); +void fetch_decode_modrm (int *mod,int *regh,int *regl); +u8 fetch_byte_imm (void); +u16 fetch_word_imm (void); +u32 fetch_long_imm (void); +u8 fetch_data_byte (uint offset); +u8 fetch_data_byte_abs (uint segment, uint offset); +u16 fetch_data_word (uint offset); +u16 fetch_data_word_abs (uint segment, uint offset); +u32 fetch_data_long (uint offset); +u32 fetch_data_long_abs (uint segment, uint offset); +void store_data_byte (uint offset, u8 val); +void store_data_byte_abs (uint segment, uint offset, u8 val); +void store_data_word (uint offset, u16 val); +void store_data_word_abs (uint segment, uint offset, u16 val); +void store_data_long (uint offset, u32 val); +void store_data_long_abs (uint segment, uint offset, u32 val); +u8* decode_rm_byte_register(int reg); +u16* decode_rm_word_register(int reg); +u32* decode_rm_long_register(int reg); +u16* decode_rm_seg_register(int reg); +unsigned decode_rm00_address(int rm); +unsigned decode_rm01_address(int rm); +unsigned decode_rm10_address(int rm); +unsigned decode_rmXX_address(int mod, int rm); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DECODE_H */ diff --git a/drivers/bios_emulator/include/x86emu/ops.h b/drivers/bios_emulator/include/x86emu/ops.h new file mode 100644 index 00000000000..a4f2316ba0d --- /dev/null +++ b/drivers/bios_emulator/include/x86emu/ops.h @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for operand decoding functions. +* +****************************************************************************/ + +#ifndef __X86EMU_OPS_H +#define __X86EMU_OPS_H + +extern void (*x86emu_optab[0x100])(u8 op1); +extern void (*x86emu_optab2[0x100])(u8 op2); + +#endif /* __X86EMU_OPS_H */ diff --git a/drivers/bios_emulator/include/x86emu/prim_asm.h b/drivers/bios_emulator/include/x86emu/prim_asm.h new file mode 100644 index 00000000000..4cb4cab5d55 --- /dev/null +++ b/drivers/bios_emulator/include/x86emu/prim_asm.h @@ -0,0 +1,970 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: Watcom C++ 10.6 or later +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Inline assembler versions of the primitive operand +* functions for faster performance. At the moment this is +* x86 inline assembler, but these functions could be replaced +* with native inline assembler for each supported processor +* platform. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_ASM_H +#define __X86EMU_PRIM_ASM_H + +#ifdef __WATCOMC__ + +#ifndef VALIDATE +#define __HAVE_INLINE_ASSEMBLER__ +#endif + +u32 get_flags_asm(void); +#pragma aux get_flags_asm = \ + "pushf" \ + "pop eax" \ + value [eax] \ + modify exact [eax]; + +u16 aaa_word_asm(u32 * flags, u16 d); +#pragma aux aaa_word_asm = \ + "push [edi]" \ + "popf" \ + "aaa" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aas_word_asm(u32 * flags, u16 d); +#pragma aux aas_word_asm = \ + "push [edi]" \ + "popf" \ + "aas" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aad_word_asm(u32 * flags, u16 d); +#pragma aux aad_word_asm = \ + "push [edi]" \ + "popf" \ + "aad" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aam_word_asm(u32 * flags, u8 d); +#pragma aux aam_word_asm = \ + "push [edi]" \ + "popf" \ + "aam" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [ax] \ + modify exact [ax]; + +u8 adc_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux adc_byte_asm = \ + "push [edi]" \ + "popf" \ + "adc al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 adc_word_asm(u32 * flags, u16 d, u16 s); +#pragma aux adc_word_asm = \ + "push [edi]" \ + "popf" \ + "adc ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 adc_long_asm(u32 * flags, u32 d, u32 s); +#pragma aux adc_long_asm = \ + "push [edi]" \ + "popf" \ + "adc eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 add_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux add_byte_asm = \ + "push [edi]" \ + "popf" \ + "add al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 add_word_asm(u32 * flags, u16 d, u16 s); +#pragma aux add_word_asm = \ + "push [edi]" \ + "popf" \ + "add ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 add_long_asm(u32 * flags, u32 d, u32 s); +#pragma aux add_long_asm = \ + "push [edi]" \ + "popf" \ + "add eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 and_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux and_byte_asm = \ + "push [edi]" \ + "popf" \ + "and al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 and_word_asm(u32 * flags, u16 d, u16 s); +#pragma aux and_word_asm = \ + "push [edi]" \ + "popf" \ + "and ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 and_long_asm(u32 * flags, u32 d, u32 s); +#pragma aux and_long_asm = \ + "push [edi]" \ + "popf" \ + "and eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 cmp_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux cmp_byte_asm = \ + "push [edi]" \ + "popf" \ + "cmp al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 cmp_word_asm(u32 * flags, u16 d, u16 s); +#pragma aux cmp_word_asm = \ + "push [edi]" \ + "popf" \ + "cmp ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 cmp_long_asm(u32 * flags, u32 d, u32 s); +#pragma aux cmp_long_asm = \ + "push [edi]" \ + "popf" \ + "cmp eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 daa_byte_asm(u32 * flags, u8 d); +#pragma aux daa_byte_asm = \ + "push [edi]" \ + "popf" \ + "daa" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u8 das_byte_asm(u32 * flags, u8 d); +#pragma aux das_byte_asm = \ + "push [edi]" \ + "popf" \ + "das" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u8 dec_byte_asm(u32 * flags, u8 d); +#pragma aux dec_byte_asm = \ + "push [edi]" \ + "popf" \ + "dec al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 dec_word_asm(u32 * flags, u16 d); +#pragma aux dec_word_asm = \ + "push [edi]" \ + "popf" \ + "dec ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 dec_long_asm(u32 * flags, u32 d); +#pragma aux dec_long_asm = \ + "push [edi]" \ + "popf" \ + "dec eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 inc_byte_asm(u32 * flags, u8 d); +#pragma aux inc_byte_asm = \ + "push [edi]" \ + "popf" \ + "inc al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 inc_word_asm(u32 * flags, u16 d); +#pragma aux inc_word_asm = \ + "push [edi]" \ + "popf" \ + "inc ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 inc_long_asm(u32 * flags, u32 d); +#pragma aux inc_long_asm = \ + "push [edi]" \ + "popf" \ + "inc eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 or_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux or_byte_asm = \ + "push [edi]" \ + "popf" \ + "or al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 or_word_asm(u32 * flags, u16 d, u16 s); +#pragma aux or_word_asm = \ + "push [edi]" \ + "popf" \ + "or ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 or_long_asm(u32 * flags, u32 d, u32 s); +#pragma aux or_long_asm = \ + "push [edi]" \ + "popf" \ + "or eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 neg_byte_asm(u32 * flags, u8 d); +#pragma aux neg_byte_asm = \ + "push [edi]" \ + "popf" \ + "neg al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 neg_word_asm(u32 * flags, u16 d); +#pragma aux neg_word_asm = \ + "push [edi]" \ + "popf" \ + "neg ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 neg_long_asm(u32 * flags, u32 d); +#pragma aux neg_long_asm = \ + "push [edi]" \ + "popf" \ + "neg eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 not_byte_asm(u32 * flags, u8 d); +#pragma aux not_byte_asm = \ + "push [edi]" \ + "popf" \ + "not al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 not_word_asm(u32 * flags, u16 d); +#pragma aux not_word_asm = \ + "push [edi]" \ + "popf" \ + "not ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 not_long_asm(u32 * flags, u32 d); +#pragma aux not_long_asm = \ + "push [edi]" \ + "popf" \ + "not eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 rcl_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux rcl_byte_asm = \ + "push [edi]" \ + "popf" \ + "rcl al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rcl_word_asm(u32 * flags, u16 d, u8 s); +#pragma aux rcl_word_asm = \ + "push [edi]" \ + "popf" \ + "rcl ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rcl_long_asm(u32 * flags, u32 d, u8 s); +#pragma aux rcl_long_asm = \ + "push [edi]" \ + "popf" \ + "rcl eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 rcr_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux rcr_byte_asm = \ + "push [edi]" \ + "popf" \ + "rcr al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rcr_word_asm(u32 * flags, u16 d, u8 s); +#pragma aux rcr_word_asm = \ + "push [edi]" \ + "popf" \ + "rcr ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rcr_long_asm(u32 * flags, u32 d, u8 s); +#pragma aux rcr_long_asm = \ + "push [edi]" \ + "popf" \ + "rcr eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 rol_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux rol_byte_asm = \ + "push [edi]" \ + "popf" \ + "rol al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rol_word_asm(u32 * flags, u16 d, u8 s); +#pragma aux rol_word_asm = \ + "push [edi]" \ + "popf" \ + "rol ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rol_long_asm(u32 * flags, u32 d, u8 s); +#pragma aux rol_long_asm = \ + "push [edi]" \ + "popf" \ + "rol eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 ror_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux ror_byte_asm = \ + "push [edi]" \ + "popf" \ + "ror al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 ror_word_asm(u32 * flags, u16 d, u8 s); +#pragma aux ror_word_asm = \ + "push [edi]" \ + "popf" \ + "ror ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 ror_long_asm(u32 * flags, u32 d, u8 s); +#pragma aux ror_long_asm = \ + "push [edi]" \ + "popf" \ + "ror eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 shl_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux shl_byte_asm = \ + "push [edi]" \ + "popf" \ + "shl al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 shl_word_asm(u32 * flags, u16 d, u8 s); +#pragma aux shl_word_asm = \ + "push [edi]" \ + "popf" \ + "shl ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 shl_long_asm(u32 * flags, u32 d, u8 s); +#pragma aux shl_long_asm = \ + "push [edi]" \ + "popf" \ + "shl eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 shr_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux shr_byte_asm = \ + "push [edi]" \ + "popf" \ + "shr al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 shr_word_asm(u32 * flags, u16 d, u8 s); +#pragma aux shr_word_asm = \ + "push [edi]" \ + "popf" \ + "shr ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 shr_long_asm(u32 * flags, u32 d, u8 s); +#pragma aux shr_long_asm = \ + "push [edi]" \ + "popf" \ + "shr eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 sar_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux sar_byte_asm = \ + "push [edi]" \ + "popf" \ + "sar al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 sar_word_asm(u32 * flags, u16 d, u8 s); +#pragma aux sar_word_asm = \ + "push [edi]" \ + "popf" \ + "sar ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 sar_long_asm(u32 * flags, u32 d, u8 s); +#pragma aux sar_long_asm = \ + "push [edi]" \ + "popf" \ + "sar eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u16 shld_word_asm(u32 * flags, u16 d, u16 fill, u8 s); +#pragma aux shld_word_asm = \ + "push [edi]" \ + "popf" \ + "shld ax,dx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [dx] [cl] \ + value [ax] \ + modify exact [ax dx cl]; + +u32 shld_long_asm(u32 * flags, u32 d, u32 fill, u8 s); +#pragma aux shld_long_asm = \ + "push [edi]" \ + "popf" \ + "shld eax,edx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [edx] [cl] \ + value [eax] \ + modify exact [eax edx cl]; + +u16 shrd_word_asm(u32 * flags, u16 d, u16 fill, u8 s); +#pragma aux shrd_word_asm = \ + "push [edi]" \ + "popf" \ + "shrd ax,dx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [dx] [cl] \ + value [ax] \ + modify exact [ax dx cl]; + +u32 shrd_long_asm(u32 * flags, u32 d, u32 fill, u8 s); +#pragma aux shrd_long_asm = \ + "push [edi]" \ + "popf" \ + "shrd eax,edx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [edx] [cl] \ + value [eax] \ + modify exact [eax edx cl]; + +u8 sbb_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux sbb_byte_asm = \ + "push [edi]" \ + "popf" \ + "sbb al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 sbb_word_asm(u32 * flags, u16 d, u16 s); +#pragma aux sbb_word_asm = \ + "push [edi]" \ + "popf" \ + "sbb ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 sbb_long_asm(u32 * flags, u32 d, u32 s); +#pragma aux sbb_long_asm = \ + "push [edi]" \ + "popf" \ + "sbb eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 sub_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux sub_byte_asm = \ + "push [edi]" \ + "popf" \ + "sub al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 sub_word_asm(u32 * flags, u16 d, u16 s); +#pragma aux sub_word_asm = \ + "push [edi]" \ + "popf" \ + "sub ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 sub_long_asm(u32 * flags, u32 d, u32 s); +#pragma aux sub_long_asm = \ + "push [edi]" \ + "popf" \ + "sub eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +void test_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux test_byte_asm = \ + "push [edi]" \ + "popf" \ + "test al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + modify exact [al bl]; + +void test_word_asm(u32 * flags, u16 d, u16 s); +#pragma aux test_word_asm = \ + "push [edi]" \ + "popf" \ + "test ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + modify exact [ax bx]; + +void test_long_asm(u32 * flags, u32 d, u32 s); +#pragma aux test_long_asm = \ + "push [edi]" \ + "popf" \ + "test eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + modify exact [eax ebx]; + +u8 xor_byte_asm(u32 * flags, u8 d, u8 s); +#pragma aux xor_byte_asm = \ + "push [edi]" \ + "popf" \ + "xor al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 xor_word_asm(u32 * flags, u16 d, u16 s); +#pragma aux xor_word_asm = \ + "push [edi]" \ + "popf" \ + "xor ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 xor_long_asm(u32 * flags, u32 d, u32 s); +#pragma aux xor_long_asm = \ + "push [edi]" \ + "popf" \ + "xor eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +void imul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s); +#pragma aux imul_byte_asm = \ + "push [edi]" \ + "popf" \ + "imul bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + parm [edi] [esi] [al] [bl] \ + modify exact [esi ax bl]; + +void imul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s); +#pragma aux imul_word_asm = \ + "push [edi]" \ + "popf" \ + "imul bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [bx]\ + modify exact [esi edi ax bx dx]; + +void imul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s); +#pragma aux imul_long_asm = \ + "push [edi]" \ + "popf" \ + "imul ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [ebx] \ + modify exact [esi edi eax ebx edx]; + +void mul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s); +#pragma aux mul_byte_asm = \ + "push [edi]" \ + "popf" \ + "mul bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + parm [edi] [esi] [al] [bl] \ + modify exact [esi ax bl]; + +void mul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s); +#pragma aux mul_word_asm = \ + "push [edi]" \ + "popf" \ + "mul bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [bx]\ + modify exact [esi edi ax bx dx]; + +void mul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s); +#pragma aux mul_long_asm = \ + "push [edi]" \ + "popf" \ + "mul ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [ebx] \ + modify exact [esi edi eax ebx edx]; + +void idiv_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s); +#pragma aux idiv_byte_asm = \ + "push [edi]" \ + "popf" \ + "idiv bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],al" \ + "mov [ecx],ah" \ + parm [edi] [esi] [ecx] [ax] [bl]\ + modify exact [esi edi ax bl]; + +void idiv_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s); +#pragma aux idiv_word_asm = \ + "push [edi]" \ + "popf" \ + "idiv bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [dx] [bx]\ + modify exact [esi edi ax dx bx]; + +void idiv_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s); +#pragma aux idiv_long_asm = \ + "push [edi]" \ + "popf" \ + "idiv ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ + modify exact [esi edi eax edx ebx]; + +void div_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s); +#pragma aux div_byte_asm = \ + "push [edi]" \ + "popf" \ + "div bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],al" \ + "mov [ecx],ah" \ + parm [edi] [esi] [ecx] [ax] [bl]\ + modify exact [esi edi ax bl]; + +void div_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s); +#pragma aux div_word_asm = \ + "push [edi]" \ + "popf" \ + "div bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [dx] [bx]\ + modify exact [esi edi ax dx bx]; + +void div_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s); +#pragma aux div_long_asm = \ + "push [edi]" \ + "popf" \ + "div ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ + modify exact [esi edi eax edx ebx]; + +#endif + +#endif /* __X86EMU_PRIM_ASM_H */ diff --git a/drivers/bios_emulator/include/x86emu/prim_ops.h b/drivers/bios_emulator/include/x86emu/prim_ops.h new file mode 100644 index 00000000000..0ea825d3c1a --- /dev/null +++ b/drivers/bios_emulator/include/x86emu/prim_ops.h @@ -0,0 +1,142 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for primitive operation functions. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_OPS_H +#define __X86EMU_PRIM_OPS_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +u16 aaa_word (u16 d); +u16 aas_word (u16 d); +u16 aad_word (u16 d); +u16 aam_word (u8 d); +u8 adc_byte (u8 d, u8 s); +u16 adc_word (u16 d, u16 s); +u32 adc_long (u32 d, u32 s); +u8 add_byte (u8 d, u8 s); +u16 add_word (u16 d, u16 s); +u32 add_long (u32 d, u32 s); +u8 and_byte (u8 d, u8 s); +u16 and_word (u16 d, u16 s); +u32 and_long (u32 d, u32 s); +u8 cmp_byte (u8 d, u8 s); +u16 cmp_word (u16 d, u16 s); +u32 cmp_long (u32 d, u32 s); +u8 daa_byte (u8 d); +u8 das_byte (u8 d); +u8 dec_byte (u8 d); +u16 dec_word (u16 d); +u32 dec_long (u32 d); +u8 inc_byte (u8 d); +u16 inc_word (u16 d); +u32 inc_long (u32 d); +u8 or_byte (u8 d, u8 s); +u16 or_word (u16 d, u16 s); +u32 or_long (u32 d, u32 s); +u8 neg_byte (u8 s); +u16 neg_word (u16 s); +u32 neg_long (u32 s); +u8 not_byte (u8 s); +u16 not_word (u16 s); +u32 not_long (u32 s); +u8 rcl_byte (u8 d, u8 s); +u16 rcl_word (u16 d, u8 s); +u32 rcl_long (u32 d, u8 s); +u8 rcr_byte (u8 d, u8 s); +u16 rcr_word (u16 d, u8 s); +u32 rcr_long (u32 d, u8 s); +u8 rol_byte (u8 d, u8 s); +u16 rol_word (u16 d, u8 s); +u32 rol_long (u32 d, u8 s); +u8 ror_byte (u8 d, u8 s); +u16 ror_word (u16 d, u8 s); +u32 ror_long (u32 d, u8 s); +u8 shl_byte (u8 d, u8 s); +u16 shl_word (u16 d, u8 s); +u32 shl_long (u32 d, u8 s); +u8 shr_byte (u8 d, u8 s); +u16 shr_word (u16 d, u8 s); +u32 shr_long (u32 d, u8 s); +u8 sar_byte (u8 d, u8 s); +u16 sar_word (u16 d, u8 s); +u32 sar_long (u32 d, u8 s); +u16 shld_word (u16 d, u16 fill, u8 s); +u32 shld_long (u32 d, u32 fill, u8 s); +u16 shrd_word (u16 d, u16 fill, u8 s); +u32 shrd_long (u32 d, u32 fill, u8 s); +u8 sbb_byte (u8 d, u8 s); +u16 sbb_word (u16 d, u16 s); +u32 sbb_long (u32 d, u32 s); +u8 sub_byte (u8 d, u8 s); +u16 sub_word (u16 d, u16 s); +u32 sub_long (u32 d, u32 s); +void test_byte (u8 d, u8 s); +void test_word (u16 d, u16 s); +void test_long (u32 d, u32 s); +u8 xor_byte (u8 d, u8 s); +u16 xor_word (u16 d, u16 s); +u32 xor_long (u32 d, u32 s); +void imul_byte (u8 s); +void imul_word (u16 s); +void imul_long (u32 s); +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s); +void mul_byte (u8 s); +void mul_word (u16 s); +void mul_long (u32 s); +void idiv_byte (u8 s); +void idiv_word (u16 s); +void idiv_long (u32 s); +void div_byte (u8 s); +void div_word (u16 s); +void div_long (u32 s); +void ins (int size); +void outs (int size); +u16 mem_access_word (int addr); +void push_word (u16 w); +void push_long (u32 w); +u16 pop_word (void); +u32 pop_long (void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_PRIM_OPS_H */ + diff --git a/drivers/bios_emulator/include/x86emu/regs.h b/drivers/bios_emulator/include/x86emu/regs.h new file mode 100644 index 00000000000..9dbed503175 --- /dev/null +++ b/drivers/bios_emulator/include/x86emu/regs.h @@ -0,0 +1,340 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_REGS_H +#define __X86EMU_REGS_H + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/* + * General EAX, EBX, ECX, EDX type registers. Note that for + * portability, and speed, the issue of byte swapping is not addressed + * in the registers. All registers are stored in the default format + * available on the host machine. The only critical issue is that the + * registers should line up EXACTLY in the same manner as they do in + * the 386. That is: + * + * EAX & 0xff === AL + * EAX & 0xffff == AX + * + * etc. The result is that alot of the calculations can then be + * done using the native instruction set fully. + */ + +#ifdef __BIG_ENDIAN__ + +typedef struct { + u32 e_reg; +} I32_reg_t; + +typedef struct { + u16 filler0, x_reg; +} I16_reg_t; + +typedef struct { + u8 filler0, filler1, h_reg, l_reg; +} I8_reg_t; + +#else /* !__BIG_ENDIAN__ */ + +typedef struct { + u32 e_reg; +} I32_reg_t; + +typedef struct { + u16 x_reg; +} I16_reg_t; + +typedef struct { + u8 l_reg, h_reg; +} I8_reg_t; + +#endif /* BIG_ENDIAN */ + +typedef union { + I32_reg_t I32_reg; + I16_reg_t I16_reg; + I8_reg_t I8_reg; +} i386_general_register; + +struct i386_general_regs { + i386_general_register A, B, C, D; +}; + +typedef struct i386_general_regs Gen_reg_t; + +struct i386_special_regs { + i386_general_register SP, BP, SI, DI, IP; + u32 FLAGS; +}; + +/* + * Segment registers here represent the 16 bit quantities + * CS, DS, ES, SS. + */ + +#undef CS +#undef DS +#undef SS +#undef ES +#undef FS +#undef GS + +struct i386_segment_regs { + u16 CS, DS, SS, ES, FS, GS; +}; + +/* 8 bit registers */ +#define R_AH gen.A.I8_reg.h_reg +#define R_AL gen.A.I8_reg.l_reg +#define R_BH gen.B.I8_reg.h_reg +#define R_BL gen.B.I8_reg.l_reg +#define R_CH gen.C.I8_reg.h_reg +#define R_CL gen.C.I8_reg.l_reg +#define R_DH gen.D.I8_reg.h_reg +#define R_DL gen.D.I8_reg.l_reg + +/* 16 bit registers */ +#define R_AX gen.A.I16_reg.x_reg +#define R_BX gen.B.I16_reg.x_reg +#define R_CX gen.C.I16_reg.x_reg +#define R_DX gen.D.I16_reg.x_reg + +/* 32 bit extended registers */ +#define R_EAX gen.A.I32_reg.e_reg +#define R_EBX gen.B.I32_reg.e_reg +#define R_ECX gen.C.I32_reg.e_reg +#define R_EDX gen.D.I32_reg.e_reg + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_ESP spc.SP.I32_reg.e_reg +#define R_EBP spc.BP.I32_reg.e_reg +#define R_ESI spc.SI.I32_reg.e_reg +#define R_EDI spc.DI.I32_reg.e_reg +#define R_EIP spc.IP.I32_reg.e_reg +#define R_EFLG spc.FLAGS + +/* segment registers */ +#define R_CS seg.CS +#define R_DS seg.DS +#define R_SS seg.SS +#define R_ES seg.ES +#define R_FS seg.FS +#define R_GS seg.GS + +/* flag conditions */ +#define FB_CF 0x0001 /* CARRY flag */ +#define FB_PF 0x0004 /* PARITY flag */ +#define FB_AF 0x0010 /* AUX flag */ +#define FB_ZF 0x0040 /* ZERO flag */ +#define FB_SF 0x0080 /* SIGN flag */ +#define FB_TF 0x0100 /* TRAP flag */ +#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define FB_DF 0x0400 /* DIR flag */ +#define FB_OF 0x0800 /* OVERFLOW flag */ + +/* 80286 and above always have bit#1 set */ +#define F_ALWAYS_ON (0x0002) /* flag bits always on */ + +/* + * Define a mask for only those flag bits we will ever pass back + * (via PUSHF) + */ +#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) + +/* following bits masked in to a 16bit quantity */ + +#define F_CF 0x0001 /* CARRY flag */ +#define F_PF 0x0004 /* PARITY flag */ +#define F_AF 0x0010 /* AUX flag */ +#define F_ZF 0x0040 /* ZERO flag */ +#define F_SF 0x0080 /* SIGN flag */ +#define F_TF 0x0100 /* TRAP flag */ +#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define F_DF 0x0400 /* DIR flag */ +#define F_OF 0x0800 /* OVERFLOW flag */ + +#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) +#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) +#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) +#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) +#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) + +#define CONDITIONAL_SET_FLAG(COND,FLAG) \ + if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) + +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ + +#define F_ALL_CALC 0xff0000 /* All have been calced */ + +/* + * Emulator machine state. + * Segment usage control. + */ +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000 + +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS) +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS | \ + SYSMODE_PREFIX_DATA | \ + SYSMODE_PREFIX_ADDR) + +#define INTR_SYNCH 0x1 +#define INTR_ASYNCH 0x2 +#define INTR_HALTED 0x4 + +typedef struct { + struct i386_general_regs gen; + struct i386_special_regs spc; + struct i386_segment_regs seg; + /* + * MODE contains information on: + * REPE prefix 2 bits repe,repne + * SEGMENT overrides 5 bits normal,DS,SS,CS,ES + * Delayed flag set 3 bits (zero, signed, parity) + * reserved 6 bits + * interrupt # 8 bits instruction raised interrupt + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits + * Extern interrupt 1 bits + * Halted 1 bits + */ + long mode; + u8 intno; + volatile int intr; /* mask of pending interrupts */ + int debug; +#ifdef DEBUG + int check; + u16 saved_ip; + u16 saved_cs; + int enc_pos; + int enc_str_pos; + char decode_buf[32]; /* encoded byte stream */ + char decoded_buf[256]; /* disassembled strings */ +#endif +} X86EMU_regs; + +/**************************************************************************** +REMARKS: +Structure maintaining the emulator machine state. + +MEMBERS: +x86 - X86 registers +mem_base - Base real mode memory for the emulator +mem_size - Size of the real mode memory block for the emulator +****************************************************************************/ +#undef x86 +typedef struct { + X86EMU_regs x86; + u8 *mem_base; + u32 mem_size; + void *private; +} X86EMU_sysEnv; + +#pragma pack() + +/*----------------------------- Global Variables --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Global emulator machine state. + * + * We keep it global to avoid pointer dereferences in the code for speed. + */ + + extern X86EMU_sysEnv _X86EMU_env; +#define M _X86EMU_env + +/*-------------------------- Function Prototypes --------------------------*/ + +/* Function to log information at runtime */ + +#ifndef __KERNEL__ + void printk(const char *fmt, ...); +#endif + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif +#endif /* __X86EMU_REGS_H */ diff --git a/drivers/bios_emulator/include/x86emu/x86emui.h b/drivers/bios_emulator/include/x86emu/x86emui.h new file mode 100644 index 00000000000..a74957d992a --- /dev/null +++ b/drivers/bios_emulator/include/x86emu/x86emui.h @@ -0,0 +1,101 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for system specific functions. These functions +* are always compiled and linked in the OS depedent libraries, +* and never in a binary portable driver. +* +****************************************************************************/ + +#ifndef __X86EMU_X86EMUI_H +#define __X86EMU_X86EMUI_H + +/* If we are compiling in C++ mode, we can compile some functions as + * inline to increase performance (however the code size increases quite + * dramatically in this case). + */ + +#if defined(__cplusplus) && !defined(_NO_INLINE) +#define _INLINE inline +#else +#define _INLINE static +#endif + +/* Get rid of unused parameters in C++ compilation mode */ + +#ifdef __cplusplus +#define X86EMU_UNUSED(v) +#else +#define X86EMU_UNUSED(v) v +#endif + +#include "x86emu.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/decode.h" +#include "x86emu/ops.h" +#include "x86emu/prim_ops.h" +#ifndef __KERNEL__ +#include +#include +#include +#endif + +#define printk printf + + +/*--------------------------- Inline Functions ----------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + + extern u8(X86APIP sys_rdb) (u32 addr); + extern u16(X86APIP sys_rdw) (u32 addr); + extern u32(X86APIP sys_rdl) (u32 addr); + extern void (X86APIP sys_wrb) (u32 addr, u8 val); + extern void (X86APIP sys_wrw) (u32 addr, u16 val); + extern void (X86APIP sys_wrl) (u32 addr, u32 val); + + extern u8(X86APIP sys_inb) (X86EMU_pioAddr addr); + extern u16(X86APIP sys_inw) (X86EMU_pioAddr addr); + extern u32(X86APIP sys_inl) (X86EMU_pioAddr addr); + extern void (X86APIP sys_outb) (X86EMU_pioAddr addr, u8 val); + extern void (X86APIP sys_outw) (X86EMU_pioAddr addr, u16 val); + extern void (X86APIP sys_outl) (X86EMU_pioAddr addr, u32 val); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif +#endif /* __X86EMU_X86EMUI_H */ diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c new file mode 100644 index 00000000000..0f58a6963f2 --- /dev/null +++ b/drivers/bios_emulator/x86emu/debug.c @@ -0,0 +1,461 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to handle debugging of the +* emulator. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" +#include + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef DEBUG + +static void print_encoded_bytes(u16 s, u16 o); +static void print_decoded_instruction(void); +static int parse_line(char *s, int *ps, int *n); + +/* should look something like debug's output. */ +void X86EMU_trace_regs(void) +{ + if (DEBUG_TRACE()) { + x86emu_dump_regs(); + } + if (DEBUG_DECODE() && !DEBUG_DECODE_NOPRINT()) { + printk("%04x:%04x ", M.x86.saved_cs, M.x86.saved_ip); + print_encoded_bytes(M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); + } +} + +void X86EMU_trace_xregs(void) +{ + if (DEBUG_TRACE()) { + x86emu_dump_xregs(); + } +} + +void x86emu_just_disassemble(void) +{ + /* + * This routine called if the flag DEBUG_DISASSEMBLE is set kind + * of a hack! + */ + printk("%04x:%04x ", M.x86.saved_cs, M.x86.saved_ip); + print_encoded_bytes(M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); +} + +static void disassemble_forward(u16 seg, u16 off, int n) +{ + X86EMU_sysEnv tregs; + int i; + u8 op1; + /* + * hack, hack, hack. What we do is use the exact machinery set up + * for execution, except that now there is an additional state + * flag associated with the "execution", and we are using a copy + * of the register struct. All the major opcodes, once fully + * decoded, have the following two steps: TRACE_REGS(r,m); + * SINGLE_STEP(r,m); which disappear if DEBUG is not defined to + * the preprocessor. The TRACE_REGS macro expands to: + * + * if (debug&DEBUG_DISASSEMBLE) + * {just_disassemble(); goto EndOfInstruction;} + * if (debug&DEBUG_TRACE) trace_regs(r,m); + * + * ...... and at the last line of the routine. + * + * EndOfInstruction: end_instr(); + * + * Up to the point where TRACE_REG is expanded, NO modifications + * are done to any register EXCEPT the IP register, for fetch and + * decoding purposes. + * + * This was done for an entirely different reason, but makes a + * nice way to get the system to help debug codes. + */ + tregs = M; + tregs.x86.R_IP = off; + tregs.x86.R_CS = seg; + + /* reset the decoding buffers */ + tregs.x86.enc_str_pos = 0; + tregs.x86.enc_pos = 0; + + /* turn on the "disassemble only, no execute" flag */ + tregs.x86.debug |= DEBUG_DISASSEMBLE_F; + + /* DUMP NEXT n instructions to screen in straight_line fashion */ + /* + * This looks like the regular instruction fetch stream, except + * that when this occurs, each fetched opcode, upon seeing the + * DEBUG_DISASSEMBLE flag set, exits immediately after decoding + * the instruction. XXX --- CHECK THAT MEM IS NOT AFFECTED!!! + * Note the use of a copy of the register structure... + */ + for (i = 0; i < n; i++) { + op1 = (*sys_rdb) (((u32) M.x86.R_CS << 4) + (M.x86.R_IP++)); + (x86emu_optab[op1]) (op1); + } + /* end major hack mode. */ +} + +void x86emu_check_ip_access(void) +{ + /* NULL as of now */ +} + +void x86emu_check_sp_access(void) +{ +} + +void x86emu_check_mem_access(u32 dummy) +{ + /* check bounds, etc */ +} + +void x86emu_check_data_access(uint dummy1, uint dummy2) +{ + /* check bounds, etc */ +} + +void x86emu_inc_decoded_inst_len(int x) +{ + M.x86.enc_pos += x; +} + +void x86emu_decode_printf(char *x) +{ + sprintf(M.x86.decoded_buf + M.x86.enc_str_pos, "%s", x); + M.x86.enc_str_pos += strlen(x); +} + +void x86emu_decode_printf2(char *x, int y) +{ + char temp[100]; + sprintf(temp, x, y); + sprintf(M.x86.decoded_buf + M.x86.enc_str_pos, "%s", temp); + M.x86.enc_str_pos += strlen(temp); +} + +void x86emu_end_instr(void) +{ + M.x86.enc_str_pos = 0; + M.x86.enc_pos = 0; +} + +static void print_encoded_bytes(u16 s, u16 o) +{ + int i; + char buf1[64]; + for (i = 0; i < M.x86.enc_pos; i++) { + sprintf(buf1 + 2 * i, "%02x", fetch_data_byte_abs(s, o + i)); + } + printk("%-20s", buf1); +} + +static void print_decoded_instruction(void) +{ + printk("%s", M.x86.decoded_buf); +} + +void x86emu_print_int_vect(u16 iv) +{ + u16 seg, off; + + if (iv > 256) + return; + seg = fetch_data_word_abs(0, iv * 4); + off = fetch_data_word_abs(0, iv * 4 + 2); + printk("%04x:%04x ", seg, off); +} + +void X86EMU_dump_memory(u16 seg, u16 off, u32 amt) +{ + u32 start = off & 0xfffffff0; + u32 end = (off + 16) & 0xfffffff0; + u32 i; + u32 current; + + current = start; + while (end <= off + amt) { + printk("%04x:%04x ", seg, start); + for (i = start; i < off; i++) + printk(" "); + for (; i < end; i++) + printk("%02x ", fetch_data_byte_abs(seg, i)); + printk("\n"); + start = end; + end = start + 16; + } +} + +void x86emu_single_step(void) +{ + char s[1024]; + int ps[10]; + int ntok; + int cmd; + int done; + int segment; + int offset; + static int breakpoint; + static int noDecode = 1; + + char *p; + + if (DEBUG_BREAK()) { + if (M.x86.saved_ip != breakpoint) { + return; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + M.x86.debug |= DEBUG_TRACE_F; + M.x86.debug &= ~DEBUG_BREAK_F; + print_decoded_instruction(); + X86EMU_trace_regs(); + } + } + done = 0; + offset = M.x86.saved_ip; + while (!done) { + printk("-"); + cmd = parse_line(s, ps, &ntok); + switch (cmd) { + case 'u': + disassemble_forward(M.x86.saved_cs, (u16) offset, 10); + break; + case 'd': + if (ntok == 2) { + segment = M.x86.saved_cs; + offset = ps[1]; + X86EMU_dump_memory(segment, (u16) offset, 16); + offset += 16; + } else if (ntok == 3) { + segment = ps[1]; + offset = ps[2]; + X86EMU_dump_memory(segment, (u16) offset, 16); + offset += 16; + } else { + segment = M.x86.saved_cs; + X86EMU_dump_memory(segment, (u16) offset, 16); + offset += 16; + } + break; + case 'c': + M.x86.debug ^= DEBUG_TRACECALL_F; + break; + case 's': + M.x86.debug ^= + DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F; + break; + case 'r': + X86EMU_trace_regs(); + break; + case 'x': + X86EMU_trace_xregs(); + break; + case 'g': + if (ntok == 2) { + breakpoint = ps[1]; + if (noDecode) { + M.x86.debug |= DEBUG_DECODE_NOPRINT_F; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + } + M.x86.debug &= ~DEBUG_TRACE_F; + M.x86.debug |= DEBUG_BREAK_F; + done = 1; + } + break; + case 'q': + M.x86.debug |= DEBUG_EXIT; + return; + case 'P': + noDecode = (noDecode) ? 0 : 1; + printk("Toggled decoding to %s\n", + (noDecode) ? "FALSE" : "TRUE"); + break; + case 't': + case 0: + done = 1; + break; + } + } +} + +int X86EMU_trace_on(void) +{ + return M.x86.debug |= DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F; +} + +int X86EMU_trace_off(void) +{ + return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F); +} + +static int parse_line(char *s, int *ps, int *n) +{ + int cmd; + + *n = 0; + while (*s == ' ' || *s == '\t') + s++; + ps[*n] = *s; + switch (*s) { + case '\n': + *n += 1; + return 0; + default: + cmd = *s; + *n += 1; + } + + while (1) { + while (*s != ' ' && *s != '\t' && *s != '\n') + s++; + + if (*s == '\n') + return cmd; + + while (*s == ' ' || *s == '\t') + s++; + + *n += 1; + } +} + +#endif /* DEBUG */ + +void x86emu_dump_regs(void) +{ + printk("\tAX=%04x ", M.x86.R_AX); + printk("BX=%04x ", M.x86.R_BX); + printk("CX=%04x ", M.x86.R_CX); + printk("DX=%04x ", M.x86.R_DX); + printk("SP=%04x ", M.x86.R_SP); + printk("BP=%04x ", M.x86.R_BP); + printk("SI=%04x ", M.x86.R_SI); + printk("DI=%04x\n", M.x86.R_DI); + printk("\tDS=%04x ", M.x86.R_DS); + printk("ES=%04x ", M.x86.R_ES); + printk("SS=%04x ", M.x86.R_SS); + printk("CS=%04x ", M.x86.R_CS); + printk("IP=%04x ", M.x86.R_IP); + if (ACCESS_FLAG(F_OF)) + printk("OV "); /* CHECKED... */ + else + printk("NV "); + if (ACCESS_FLAG(F_DF)) + printk("DN "); + else + printk("UP "); + if (ACCESS_FLAG(F_IF)) + printk("EI "); + else + printk("DI "); + if (ACCESS_FLAG(F_SF)) + printk("NG "); + else + printk("PL "); + if (ACCESS_FLAG(F_ZF)) + printk("ZR "); + else + printk("NZ "); + if (ACCESS_FLAG(F_AF)) + printk("AC "); + else + printk("NA "); + if (ACCESS_FLAG(F_PF)) + printk("PE "); + else + printk("PO "); + if (ACCESS_FLAG(F_CF)) + printk("CY "); + else + printk("NC "); + printk("\n"); +} + +void x86emu_dump_xregs(void) +{ + printk("\tEAX=%08x ", M.x86.R_EAX); + printk("EBX=%08x ", M.x86.R_EBX); + printk("ECX=%08x ", M.x86.R_ECX); + printk("EDX=%08x \n", M.x86.R_EDX); + printk("\tESP=%08x ", M.x86.R_ESP); + printk("EBP=%08x ", M.x86.R_EBP); + printk("ESI=%08x ", M.x86.R_ESI); + printk("EDI=%08x\n", M.x86.R_EDI); + printk("\tDS=%04x ", M.x86.R_DS); + printk("ES=%04x ", M.x86.R_ES); + printk("SS=%04x ", M.x86.R_SS); + printk("CS=%04x ", M.x86.R_CS); + printk("EIP=%08x\n\t", M.x86.R_EIP); + if (ACCESS_FLAG(F_OF)) + printk("OV "); /* CHECKED... */ + else + printk("NV "); + if (ACCESS_FLAG(F_DF)) + printk("DN "); + else + printk("UP "); + if (ACCESS_FLAG(F_IF)) + printk("EI "); + else + printk("DI "); + if (ACCESS_FLAG(F_SF)) + printk("NG "); + else + printk("PL "); + if (ACCESS_FLAG(F_ZF)) + printk("ZR "); + else + printk("NZ "); + if (ACCESS_FLAG(F_AF)) + printk("AC "); + else + printk("NA "); + if (ACCESS_FLAG(F_PF)) + printk("PE "); + else + printk("PO "); + if (ACCESS_FLAG(F_CF)) + printk("CY "); + else + printk("NC "); + printk("\n"); +} diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c new file mode 100644 index 00000000000..b4dbb20797d --- /dev/null +++ b/drivers/bios_emulator/x86emu/decode.c @@ -0,0 +1,1148 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines which are related to +* instruction decoding and accessess of immediate data via IP. etc. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Handles any pending asychronous interrupts. +****************************************************************************/ +static void x86emu_intr_handle(void) +{ + u8 intno; + + if (M.x86.intr & INTR_SYNCH) { + intno = M.x86.intno; + if (_X86EMU_intrTab[intno]) { + (*_X86EMU_intrTab[intno])(intno); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intno * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intno * 4); + M.x86.intr = 0; + } + } +} + +/**************************************************************************** +PARAMETERS: +intrnum - Interrupt number to raise + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. +****************************************************************************/ +void x86emu_intr_raise( + u8 intrnum) +{ + M.x86.intno = intrnum; + M.x86.intr |= INTR_SYNCH; +} + +/**************************************************************************** +REMARKS: +Main execution loop for the emulator. We return from here when the system +halts, which is normally caused by a stack fault when we return from the +original real mode call. +****************************************************************************/ +void X86EMU_exec(void) +{ + u8 op1; + + M.x86.intr = 0; + DB(x86emu_end_instr();) + + for (;;) { +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + /* If debugging, save the IP and CS values. */ + SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); + INC_DECODED_INST_LEN(1); + if (M.x86.intr) { + if (M.x86.intr & INTR_HALTED) { +DB( if (M.x86.R_SP != 0) { + printk("halted\n"); + X86EMU_trace_regs(); + } + else { + if (M.x86.debug) + printk("Service completed successfully\n"); + }) + return; + } + if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || + !ACCESS_FLAG(F_IF)) { + x86emu_intr_handle(); + } + } + op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + (*x86emu_optab[op1])(op1); + if (M.x86.debug & DEBUG_EXIT) { + M.x86.debug &= ~DEBUG_EXIT; + return; + } + } +} + +/**************************************************************************** +REMARKS: +Halts the system by setting the halted system flag. +****************************************************************************/ +void X86EMU_halt_sys(void) +{ + M.x86.intr |= INTR_HALTED; +} + +/**************************************************************************** +PARAMETERS: +mod - Mod value from decoded byte +regh - Reg h value from decoded byte +regl - Reg l value from decoded byte + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. + +NOTE: Do not inline this function, as (*sys_rdb) is already inline! +****************************************************************************/ +void fetch_decode_modrm( + int *mod, + int *regh, + int *regl) +{ + int fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + *mod = (fetched >> 6) & 0x03; + *regh = (fetched >> 3) & 0x07; + *regl = (fetched >> 0) & 0x07; +} + +/**************************************************************************** +RETURNS: +Immediate byte value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdb) is already inline! +****************************************************************************/ +u8 fetch_byte_imm(void) +{ + u8 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + return fetched; +} + +/**************************************************************************** +RETURNS: +Immediate word value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdw) is already inline! +****************************************************************************/ +u16 fetch_word_imm(void) +{ + u16 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); + M.x86.R_IP += 2; + INC_DECODED_INST_LEN(2); + return fetched; +} + +/**************************************************************************** +RETURNS: +Immediate lone value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdw) is already inline! +****************************************************************************/ +u32 fetch_long_imm(void) +{ + u32 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); + M.x86.R_IP += 4; + INC_DECODED_INST_LEN(4); + return fetched; +} + +/**************************************************************************** +RETURNS: +Value of the default data segment + +REMARKS: +Inline function that returns the default data segment for the current +instruction. + +On the x86 processor, the default segment is not always DS if there is +no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to +addresses relative to SS (ie: on the stack). So, at the minimum, all +decodings of addressing modes would have to set/clear a bit describing +whether the access is relative to DS or SS. That is the function of the +cpu-state-varible M.x86.mode. There are several potential states: + + repe prefix seen (handled elsewhere) + repne prefix seen (ditto) + + cs segment override + ds segment override + es segment override + fs segment override + gs segment override + ss segment override + + ds/ss select (in absense of override) + +Each of the above 7 items are handled with a bit in the mode field. +****************************************************************************/ +_INLINE u32 get_data_segment(void) +{ +#define GET_SEGMENT(segment) + switch (M.x86.mode & SYSMODE_SEGMASK) { + case 0: /* default case: use ds register */ + case SYSMODE_SEGOVR_DS: + case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: + return M.x86.R_DS; + case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ + return M.x86.R_SS; + case SYSMODE_SEGOVR_CS: + case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: + return M.x86.R_CS; + case SYSMODE_SEGOVR_ES: + case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: + return M.x86.R_ES; + case SYSMODE_SEGOVR_FS: + case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: + return M.x86.R_FS; + case SYSMODE_SEGOVR_GS: + case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: + return M.x86.R_GS; + case SYSMODE_SEGOVR_SS: + case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: + return M.x86.R_SS; + default: +#ifdef DEBUG + printk("error: should not happen: multiple overrides.\n"); +#endif + HALT_SYS(); + return 0; + } +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u8 fetch_data_byte( + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdb)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u16 fetch_data_word( + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdw)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u32 fetch_data_long( + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdl)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u8 fetch_data_byte_abs( + uint segment, + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdb)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u16 fetch_data_word_abs( + uint segment, + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdw)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u32 fetch_data_long_abs( + uint segment, + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdl)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_byte( + uint offset, + u8 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrb)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_word( + uint offset, + u16 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrw)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_long( + uint offset, + u32 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrl)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a byte value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_byte_abs( + uint segment, + uint offset, + u8 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrb)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_word_abs( + uint segment, + uint offset, + u16 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrw)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_long_abs( + uint segment, + uint offset, + u32 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrl)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for byte operands. Also enables the decoding of instructions. +****************************************************************************/ +u8* decode_rm_byte_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("AL"); + return &M.x86.R_AL; + case 1: + DECODE_PRINTF("CL"); + return &M.x86.R_CL; + case 2: + DECODE_PRINTF("DL"); + return &M.x86.R_DL; + case 3: + DECODE_PRINTF("BL"); + return &M.x86.R_BL; + case 4: + DECODE_PRINTF("AH"); + return &M.x86.R_AH; + case 5: + DECODE_PRINTF("CH"); + return &M.x86.R_CH; + case 6: + DECODE_PRINTF("DH"); + return &M.x86.R_DH; + case 7: + DECODE_PRINTF("BH"); + return &M.x86.R_BH; + } + HALT_SYS(); + return NULL; /* NOT REACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands. Also enables the decoding of instructions. +****************************************************************************/ +u16* decode_rm_word_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("AX"); + return &M.x86.R_AX; + case 1: + DECODE_PRINTF("CX"); + return &M.x86.R_CX; + case 2: + DECODE_PRINTF("DX"); + return &M.x86.R_DX; + case 3: + DECODE_PRINTF("BX"); + return &M.x86.R_BX; + case 4: + DECODE_PRINTF("SP"); + return &M.x86.R_SP; + case 5: + DECODE_PRINTF("BP"); + return &M.x86.R_BP; + case 6: + DECODE_PRINTF("SI"); + return &M.x86.R_SI; + case 7: + DECODE_PRINTF("DI"); + return &M.x86.R_DI; + } + HALT_SYS(); + return NULL; /* NOTREACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for dword operands. Also enables the decoding of instructions. +****************************************************************************/ +u32* decode_rm_long_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("EAX"); + return &M.x86.R_EAX; + case 1: + DECODE_PRINTF("ECX"); + return &M.x86.R_ECX; + case 2: + DECODE_PRINTF("EDX"); + return &M.x86.R_EDX; + case 3: + DECODE_PRINTF("EBX"); + return &M.x86.R_EBX; + case 4: + DECODE_PRINTF("ESP"); + return &M.x86.R_ESP; + case 5: + DECODE_PRINTF("EBP"); + return &M.x86.R_EBP; + case 6: + DECODE_PRINTF("ESI"); + return &M.x86.R_ESI; + case 7: + DECODE_PRINTF("EDI"); + return &M.x86.R_EDI; + } + HALT_SYS(); + return NULL; /* NOTREACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands, modified from above for the weirdo +special case of segreg operands. Also enables the decoding of instructions. +****************************************************************************/ +u16* decode_rm_seg_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("ES"); + return &M.x86.R_ES; + case 1: + DECODE_PRINTF("CS"); + return &M.x86.R_CS; + case 2: + DECODE_PRINTF("SS"); + return &M.x86.R_SS; + case 3: + DECODE_PRINTF("DS"); + return &M.x86.R_DS; + case 4: + DECODE_PRINTF("FS"); + return &M.x86.R_FS; + case 5: + DECODE_PRINTF("GS"); + return &M.x86.R_GS; + case 6: + case 7: + DECODE_PRINTF("ILLEGAL SEGREG"); + break; + } + HALT_SYS(); + return NULL; /* NOT REACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +scale - scale value of SIB byte +index - index value of SIB byte + +RETURNS: +Value of scale * index + +REMARKS: +Decodes scale/index of SIB byte and returns relevant offset part of +effective address. +****************************************************************************/ +unsigned decode_sib_si( + int scale, + int index) +{ + scale = 1 << scale; + if (scale > 1) { + DECODE_PRINTF2("[%d*", scale); + } else { + DECODE_PRINTF("["); + } + switch (index) { + case 0: + DECODE_PRINTF("EAX]"); + return M.x86.R_EAX * index; + case 1: + DECODE_PRINTF("ECX]"); + return M.x86.R_ECX * index; + case 2: + DECODE_PRINTF("EDX]"); + return M.x86.R_EDX * index; + case 3: + DECODE_PRINTF("EBX]"); + return M.x86.R_EBX * index; + case 4: + DECODE_PRINTF("0]"); + return 0; + case 5: + DECODE_PRINTF("EBP]"); + return M.x86.R_EBP * index; + case 6: + DECODE_PRINTF("ESI]"); + return M.x86.R_ESI * index; + case 7: + DECODE_PRINTF("EDI]"); + return M.x86.R_EDI * index; + } + HALT_SYS(); + return 0; /* NOT REACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +mod - MOD value of preceding ModR/M byte + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Decodes SIB addressing byte and returns calculated effective address. +****************************************************************************/ +unsigned decode_sib_address( + int mod) +{ + int sib = fetch_byte_imm(); + int ss = (sib >> 6) & 0x03; + int index = (sib >> 3) & 0x07; + int base = sib & 0x07; + int offset = 0; + int displacement; + + switch (base) { + case 0: + DECODE_PRINTF("[EAX]"); + offset = M.x86.R_EAX; + break; + case 1: + DECODE_PRINTF("[ECX]"); + offset = M.x86.R_ECX; + break; + case 2: + DECODE_PRINTF("[EDX]"); + offset = M.x86.R_EDX; + break; + case 3: + DECODE_PRINTF("[EBX]"); + offset = M.x86.R_EBX; + break; + case 4: + DECODE_PRINTF("[ESP]"); + offset = M.x86.R_ESP; + break; + case 5: + switch (mod) { + case 0: + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d]", displacement); + offset = displacement; + break; + case 1: + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("[%d][EBP]", displacement); + offset = M.x86.R_EBP + displacement; + break; + case 2: + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d][EBP]", displacement); + offset = M.x86.R_EBP + displacement; + break; + default: + HALT_SYS(); + } + DECODE_PRINTF("[EAX]"); + offset = M.x86.R_EAX; + break; + case 6: + DECODE_PRINTF("[ESI]"); + offset = M.x86.R_ESI; + break; + case 7: + DECODE_PRINTF("[EDI]"); + offset = M.x86.R_EDI; + break; + default: + HALT_SYS(); + } + offset += decode_sib_si(ss, index); + return offset; + +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=00 addressing. Also enables the +decoding of instructions. + +NOTE: The code which specifies the corresponding segment (ds vs ss) + below in the case of [BP+..]. The assumption here is that at the + point that this subroutine is called, the bit corresponding to + SYSMODE_SEG_DS_SS will be zero. After every instruction + except the segment override instructions, this bit (as well + as any bits indicating segment overrides) will be clear. So + if a SS access is needed, set this bit. Otherwise, DS access + occurs (unless any of the segment override bits are set). +****************************************************************************/ +unsigned decode_rm00_address( + int rm) +{ + unsigned offset; + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[EAX]"); + return M.x86.R_EAX; + case 1: + DECODE_PRINTF("[ECX]"); + return M.x86.R_ECX; + case 2: + DECODE_PRINTF("[EDX]"); + return M.x86.R_EDX; + case 3: + DECODE_PRINTF("[EBX]"); + return M.x86.R_EBX; + case 4: + return decode_sib_address(0); + case 5: + offset = fetch_long_imm(); + DECODE_PRINTF2("[%08x]", offset); + return offset; + case 6: + DECODE_PRINTF("[ESI]"); + return M.x86.R_ESI; + case 7: + DECODE_PRINTF("[EDI]"); + return M.x86.R_EDI; + } + } else { + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[BX+SI]"); + return (M.x86.R_BX + M.x86.R_SI) & 0xffff; + case 1: + DECODE_PRINTF("[BX+DI]"); + return (M.x86.R_BX + M.x86.R_DI) & 0xffff; + case 2: + DECODE_PRINTF("[BP+SI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI) & 0xffff; + case 3: + DECODE_PRINTF("[BP+DI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI) & 0xffff; + case 4: + DECODE_PRINTF("[SI]"); + return M.x86.R_SI; + case 5: + DECODE_PRINTF("[DI]"); + return M.x86.R_DI; + case 6: + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]", offset); + return offset; + case 7: + DECODE_PRINTF("[BX]"); + return M.x86.R_BX; + } + } + HALT_SYS(); + return 0; +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=01 addressing. Also enables the +decoding of instructions. +****************************************************************************/ +unsigned decode_rm01_address( + int rm) +{ + int displacement; + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + /* 32-bit addressing */ + if (rm != 4) + displacement = (s8)fetch_byte_imm(); + else + displacement = 0; + + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: { + int offset = decode_sib_address(1); + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("[%d]", displacement); + return offset + displacement; + } + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } + } else { + /* 16-bit addressing */ + displacement = (s8)fetch_byte_imm(); + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } + } + HALT_SYS(); + return 0; /* SHOULD NOT HAPPEN */ +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=10 addressing. Also enables the +decoding of instructions. +****************************************************************************/ +unsigned decode_rm10_address( + int rm) +{ + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + int displacement; + + /* 32-bit addressing */ + if (rm != 4) + displacement = (s32)fetch_long_imm(); + else + displacement = 0; + + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: { + int offset = decode_sib_address(2); + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d]", displacement); + return offset + displacement; + } + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } + } else { + int displacement = (s16)fetch_word_imm(); + + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } + } + HALT_SYS(); + return 0; /* SHOULD NOT HAPPEN */ +} + + +/**************************************************************************** +PARAMETERS: +mod - modifier +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding, multiplexing calls to +the decode_rmXX_address functions + +REMARKS: +Return the offset given by "mod" addressing. +****************************************************************************/ + +unsigned decode_rmXX_address(int mod, int rm) +{ + if(mod == 0) + return decode_rm00_address(rm); + if(mod == 1) + return decode_rm01_address(rm); + return decode_rm10_address(rm); +} + + + diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c new file mode 100644 index 00000000000..632979dd574 --- /dev/null +++ b/drivers/bios_emulator/x86emu/ops.c @@ -0,0 +1,5431 @@ +/**************************************************************************** +* Realmode X86 Emulator Library +* +* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. +* Jason Jin +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 processor instructions. +* +* There are approximately 250 subroutines in here, which correspond +* to the 256 byte-"opcodes" found on the 8086. The table which +* dispatches this is found in the files optab.[ch]. +* +* Each opcode proc has a comment preceeding it which gives it's table +* address. Several opcodes are missing (undefined) in the table. +* +* Each proc includes information for decoding (DECODE_PRINTF and +* DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc +* functions (START_OF_INSTR, END_OF_INSTR). +* +* Many of the procedures are *VERY* similar in coding. This has +* allowed for a very large amount of code to be generated in a fairly +* short amount of time (i.e. cut, paste, and modify). The result is +* that much of the code below could have been folded into subroutines +* for a large reduction in size of this file. The downside would be +* that there would be a penalty in execution speed. The file could +* also have been *MUCH* larger by inlining certain functions which +* were called. This could have resulted even faster execution. The +* prime directive I used to decide whether to inline the code or to +* modularize it, was basically: 1) no unnecessary subroutine calls, +* 2) no routines more than about 200 lines in size, and 3) modularize +* any code that I might not get right the first time. The fetch_* +* subroutines fall into the latter category. The The decode_* fall +* into the second category. The coding of the "switch(mod){ .... }" +* in many of the subroutines below falls into the first category. +* Especially, the coding of {add,and,or,sub,...}_{byte,word} +* subroutines are an especially glaring case of the third guideline. +* Since so much of the code is cloned from other modules (compare +* opcode #00 to opcode #01), making the basic operations subroutine +* calls is especially important; otherwise mistakes in coding an +* "add" would represent a nightmare in maintenance. +* +* Jason ported this file to u-boot. place all the function pointer in +* the got2 sector. Removed some opcode. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" +/*----------------------------- Implementation ----------------------------*/ + +/* constant arrays to do several instructions in just one function */ + +#ifdef DEBUG +static char *x86emu_GenOpName[8] = { + "ADD", "OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP"}; +#endif + +/* used by several opcodes */ +static u8 (*genop_byte_operation[])(u8 d, u8 s) __attribute__ ((section(".got2"))) = +{ + add_byte, /* 00 */ + or_byte, /* 01 */ + adc_byte, /* 02 */ + sbb_byte, /* 03 */ + and_byte, /* 04 */ + sub_byte, /* 05 */ + xor_byte, /* 06 */ + cmp_byte, /* 07 */ +}; + +static u16 (*genop_word_operation[])(u16 d, u16 s) __attribute__ ((section(".got2"))) = +{ + add_word, /*00 */ + or_word, /*01 */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 */ + sub_word, /*05 */ + xor_word, /*06 */ + cmp_word, /*07 */ +}; + +static u32 (*genop_long_operation[])(u32 d, u32 s) __attribute__ ((section(".got2"))) = +{ + add_long, /*00 */ + or_long, /*01 */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 */ + sub_long, /*05 */ + xor_long, /*06 */ + cmp_long, /*07 */ +}; + +/* used by opcodes 80, c0, d0, and d2. */ +static u8(*opcD0_byte_operation[])(u8 d, u8 s) __attribute__ ((section(".got2"))) = +{ + rol_byte, + ror_byte, + rcl_byte, + rcr_byte, + shl_byte, + shr_byte, + shl_byte, /* sal_byte === shl_byte by definition */ + sar_byte, +}; + +/* used by opcodes c1, d1, and d3. */ +static u16(*opcD1_word_operation[])(u16 s, u8 d) __attribute__ ((section(".got2"))) = +{ + rol_word, + ror_word, + rcl_word, + rcr_word, + shl_word, + shr_word, + shl_word, /* sal_byte === shl_byte by definition */ + sar_word, +}; + +/* used by opcodes c1, d1, and d3. */ +static u32 (*opcD1_long_operation[])(u32 s, u8 d) __attribute__ ((section(".got2"))) = +{ + rol_long, + ror_long, + rcl_long, + rcr_long, + shl_long, + shr_long, + shl_long, /* sal_byte === shl_byte by definition */ + sar_long, +}; + +#ifdef DEBUG + +static char *opF6_names[8] = + { "TEST\t", "", "NOT\t", "NEG\t", "MUL\t", "IMUL\t", "DIV\t", "IDIV\t" }; + +#endif + +/**************************************************************************** +PARAMETERS: +op1 - Instruction op code + +REMARKS: +Handles illegal opcodes. +****************************************************************************/ +void x86emuOp_illegal_op( + u8 op1) +{ + START_OF_INSTR(); + if (M.x86.R_SP != 0) { + DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); + TRACE_REGS(); + DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP-1,op1)); + HALT_SYS(); + } + else { + /* If we get here, it means the stack pointer is back to zero + * so we are just returning from an emulator service call + * so therte is no need to display an error message. We trap + * the emulator with an 0xF1 opcode to finish the service + * call. + */ + X86EMU_halt_sys(); + } + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcodes 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38 +****************************************************************************/ +void x86emuOp_genop_byte_RM_R(u8 op1) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg, *srcreg; + u8 destval; + + op1 = (op1 >> 3) & 0x7; + + START_OF_INSTR(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if(mod<3) + { destoffset = decode_rmXX_address(mod,rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_byte_operation[op1](destval, *srcreg); + store_data_byte(destoffset, destval); + } + else + { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_byte_operation[op1](*destreg, *srcreg); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcodes 0x01, 0x09, 0x11, 0x19, 0x21, 0x29, 0x31, 0x39 +****************************************************************************/ +void x86emuOp_genop_word_RM_R(u8 op1) +{ + int mod, rl, rh; + uint destoffset; + + op1 = (op1 >> 3) & 0x7; + + START_OF_INSTR(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + + if(mod<3) { + destoffset = decode_rmXX_address(mod,rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_long_operation[op1](destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_word_operation[op1](destval, *srcreg); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_long_operation[op1](*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, *srcreg); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcodes 0x02, 0x0a, 0x12, 0x1a, 0x22, 0x2a, 0x32, 0x3a +****************************************************************************/ +void x86emuOp_genop_byte_R_RM(u8 op1) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + op1 = (op1 >> 3) & 0x7; + + START_OF_INSTR(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod,rl); + srcval = fetch_data_byte(srcoffset); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + srcval = *srcreg; + } + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_byte_operation[op1](*destreg, srcval); + + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcodes 0x03, 0x0b, 0x13, 0x1b, 0x23, 0x2b, 0x33, 0x3b +****************************************************************************/ +void x86emuOp_genop_word_R_RM(u8 op1) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg32, srcval; + u16 *destreg; + + op1 = (op1 >> 3) & 0x7; + + START_OF_INSTR(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + srcoffset = decode_rmXX_address(mod,rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destreg32 = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = genop_long_operation[op1](*destreg32, srcval); + } else { + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, srcval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + destreg32 = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = genop_long_operation[op1](*destreg32, *srcreg); + } else { + u16 *srcreg; + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, *srcreg); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcodes 0x04, 0x0c, 0x14, 0x1c, 0x24, 0x2c, 0x34, 0x3c +****************************************************************************/ +void x86emuOp_genop_byte_AL_IMM(u8 op1) +{ + u8 srcval; + + op1 = (op1 >> 3) & 0x7; + + START_OF_INSTR(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = genop_byte_operation[op1](M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcodes 0x05, 0x0d, 0x15, 0x1d, 0x25, 0x2d, 0x35, 0x3d +****************************************************************************/ +void x86emuOp_genop_word_AX_IMM(u8 op1) +{ + u32 srcval; + + op1 = (op1 >> 3) & 0x7; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = genop_long_operation[op1](M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = genop_word_operation[op1](M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x06 +****************************************************************************/ +void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tES\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_ES); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x07 +****************************************************************************/ +void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tES\n"); + TRACE_AND_STEP(); + M.x86.R_ES = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0e +****************************************************************************/ +void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tCS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f. Escape for two-byte opcode (286 or better) +****************************************************************************/ +void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1)) +{ + u8 op2 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + (*x86emu_optab2[op2])(op2); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x16 +****************************************************************************/ +void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tSS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_SS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x17 +****************************************************************************/ +void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tSS\n"); + TRACE_AND_STEP(); + M.x86.R_SS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1e +****************************************************************************/ +void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tDS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_DS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1f +****************************************************************************/ +void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tDS\n"); + TRACE_AND_STEP(); + M.x86.R_DS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x26 +****************************************************************************/ +void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ES:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_ES; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x27 +****************************************************************************/ +void x86emuOp_daa(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DAA\n"); + TRACE_AND_STEP(); + M.x86.R_AL = daa_byte(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2e +****************************************************************************/ +void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("CS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_CS; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2f +****************************************************************************/ +void x86emuOp_das(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DAS\n"); + TRACE_AND_STEP(); + M.x86.R_AL = das_byte(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x36 +****************************************************************************/ +void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("SS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_SS; + /* no DECODE_CLEAR_SEGOVR ! */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x37 +****************************************************************************/ +void x86emuOp_aaa(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("AAA\n"); + TRACE_AND_STEP(); + M.x86.R_AX = aaa_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3e +****************************************************************************/ +void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_DS; + /* NO DECODE_CLEAR_SEGOVR! */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3f +****************************************************************************/ +void x86emuOp_aas(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("AAS\n"); + TRACE_AND_STEP(); + M.x86.R_AX = aas_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x40 - 0x47 +****************************************************************************/ +void x86emuOp_inc_register(u8 op1) +{ + START_OF_INSTR(); + op1 &= 0x7; + DECODE_PRINTF("INC\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = inc_long(*reg); + } else { + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = inc_word(*reg); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x48 - 0x4F +****************************************************************************/ +void x86emuOp_dec_register(u8 op1) +{ + START_OF_INSTR(); + op1 &= 0x7; + DECODE_PRINTF("DEC\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = dec_long(*reg); + } else { + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = dec_word(*reg); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x50 - 0x57 +****************************************************************************/ +void x86emuOp_push_register(u8 op1) +{ + START_OF_INSTR(); + op1 &= 0x7; + DECODE_PRINTF("PUSH\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*reg); + } else { + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*reg); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x58 - 0x5F +****************************************************************************/ +void x86emuOp_pop_register(u8 op1) +{ + START_OF_INSTR(); + op1 &= 0x7; + DECODE_PRINTF("POP\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = pop_long(); + } else { + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x60 +****************************************************************************/ +void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSHAD\n"); + } else { + DECODE_PRINTF("PUSHA\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 old_sp = M.x86.R_ESP; + + push_long(M.x86.R_EAX); + push_long(M.x86.R_ECX); + push_long(M.x86.R_EDX); + push_long(M.x86.R_EBX); + push_long(old_sp); + push_long(M.x86.R_EBP); + push_long(M.x86.R_ESI); + push_long(M.x86.R_EDI); + } else { + u16 old_sp = M.x86.R_SP; + + push_word(M.x86.R_AX); + push_word(M.x86.R_CX); + push_word(M.x86.R_DX); + push_word(M.x86.R_BX); + push_word(old_sp); + push_word(M.x86.R_BP); + push_word(M.x86.R_SI); + push_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x61 +****************************************************************************/ +void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POPAD\n"); + } else { + DECODE_PRINTF("POPA\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = pop_long(); + M.x86.R_ESI = pop_long(); + M.x86.R_EBP = pop_long(); + M.x86.R_ESP += 4; /* skip ESP */ + M.x86.R_EBX = pop_long(); + M.x86.R_EDX = pop_long(); + M.x86.R_ECX = pop_long(); + M.x86.R_EAX = pop_long(); + } else { + M.x86.R_DI = pop_word(); + M.x86.R_SI = pop_word(); + M.x86.R_BP = pop_word(); + M.x86.R_SP += 2; /* skip SP */ + M.x86.R_BX = pop_word(); + M.x86.R_DX = pop_word(); + M.x86.R_CX = pop_word(); + M.x86.R_AX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ + +/**************************************************************************** +REMARKS: +Handles opcode 0x64 +****************************************************************************/ +void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("FS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_FS; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x65 +****************************************************************************/ +void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("GS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_GS; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x66 - prefix for 32-bit register +****************************************************************************/ +void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DATA:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_DATA; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x67 - prefix for 32-bit address +****************************************************************************/ +void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ADDR:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_ADDR; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x68 +****************************************************************************/ +void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 imm; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + imm = fetch_long_imm(); + } else { + imm = fetch_word_imm(); + } + DECODE_PRINTF2("PUSH\t%x\n", imm); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(imm); + } else { + push_word((u16)imm); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x69 +****************************************************************************/ +void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6a +****************************************************************************/ +void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + s16 imm; + + START_OF_INSTR(); + imm = (s8)fetch_byte_imm(); + DECODE_PRINTF2("PUSH\t%d\n", imm); + TRACE_AND_STEP(); + push_word(imm); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6b +****************************************************************************/ +void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + s8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)*srcreg * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6c +****************************************************************************/ +void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("INSB\n"); + ins(1); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6d +****************************************************************************/ +void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INSD\n"); + ins(4); + } else { + DECODE_PRINTF("INSW\n"); + ins(2); + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6e +****************************************************************************/ +void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("OUTSB\n"); + outs(1); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6f +****************************************************************************/ +void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OUTSD\n"); + outs(4); + } else { + DECODE_PRINTF("OUTSW\n"); + outs(2); + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x70 - 0x7F +****************************************************************************/ +int x86emu_check_jump_condition(u8 op); + +void x86emuOp_jump_near_cond(u8 op1) +{ + s8 offset; + u16 target; + int cond; + + /* jump to byte offset if overflow flag is set */ + START_OF_INSTR(); + cond = x86emu_check_jump_condition(op1 & 0xF); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (cond) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x80 +****************************************************************************/ +void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + u8 destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + if (mod < 3) { + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x81 +****************************************************************************/ +void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* + * Know operation, decode the mod byte to find the addressing + * mode. + */ + if (mod < 3) { + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x82 +****************************************************************************/ +void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + u8 destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + if (mod < 3) { + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x83 +****************************************************************************/ +void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + if (mod < 3) { + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod,rl); + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x84 +****************************************************************************/ +void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(*destreg, *srcreg); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x85 +****************************************************************************/ +void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(*destreg, *srcreg); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x86 +****************************************************************************/ +void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + u8 tmp; + + START_OF_INSTR(); + DECODE_PRINTF("XCHG\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x87 +****************************************************************************/ +void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XCHG\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 tmp; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } else { + u16 *destreg,*srcreg; + u16 tmp; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x88 +****************************************************************************/ +void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x89 +****************************************************************************/ +void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8a +****************************************************************************/ +void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8b +****************************************************************************/ +void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg, *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8c +****************************************************************************/ +void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *destreg, *srcreg; + uint destoffset; + u16 destval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8d +****************************************************************************/ +void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *srcreg; + uint destoffset; + +/* + * TODO: Need to handle address size prefix! + * + * lea eax,[eax+ebx*2] ?? + */ + + START_OF_INSTR(); + DECODE_PRINTF("LEA\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } + /* } else { undefined. Do nothing. } */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8e +****************************************************************************/ +void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *destreg, *srcreg; + uint srcoffset; + u16 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + /* + * Clean up, and reset all the R_xSP pointers to the correct + * locations. This is about 3x too much overhead (doing all the + * segreg ptrs when only one is needed, but this instruction + * *cannot* be that common, and this isn't too much work anyway. + */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8f +****************************************************************************/ +void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("POP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); + } + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_long(); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_word(); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x90 +****************************************************************************/ +void x86emuOp_nop(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("NOP\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x91-0x97 +****************************************************************************/ +void x86emuOp_xchg_word_AX_register(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + op1 &= 0x7; + + START_OF_INSTR(); + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *reg32; + DECODE_PRINTF("XCHG\tEAX,"); + reg32 = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = M.x86.R_EAX; + M.x86.R_EAX = *reg32; + *reg32 = tmp; + } else { + u16 *reg16; + DECODE_PRINTF("XCHG\tAX,"); + reg16 = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = M.x86.R_AX; + M.x86.R_EAX = *reg16; + *reg16 = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x98 +****************************************************************************/ +void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CWDE\n"); + } else { + DECODE_PRINTF("CBW\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.R_AX & 0x8000) { + M.x86.R_EAX |= 0xffff0000; + } else { + M.x86.R_EAX &= 0x0000ffff; + } + } else { + if (M.x86.R_AL & 0x80) { + M.x86.R_AH = 0xff; + } else { + M.x86.R_AH = 0x0; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x99 +****************************************************************************/ +void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CDQ\n"); + } else { + DECODE_PRINTF("CWD\n"); + } + DECODE_PRINTF("CWD\n"); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.R_EAX & 0x80000000) { + M.x86.R_EDX = 0xffffffff; + } else { + M.x86.R_EDX = 0x0; + } + } else { + if (M.x86.R_AX & 0x8000) { + M.x86.R_DX = 0xffff; + } else { + M.x86.R_DX = 0x0; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9a +****************************************************************************/ +void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 farseg, faroff; + + START_OF_INSTR(); + DECODE_PRINTF("CALL\t"); + faroff = fetch_word_imm(); + farseg = fetch_word_imm(); + DECODE_PRINTF2("%04x:", farseg); + DECODE_PRINTF2("%04x\n", faroff); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR "); + + /* XXX + * + * Hooked interrupt vectors calling into our "BIOS" will cause + * problems unless all intersegment stuff is checked for BIOS + * access. Check needed here. For moment, let it alone. + */ + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = farseg; + push_word(M.x86.R_IP); + M.x86.R_IP = faroff; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9b +****************************************************************************/ +void x86emuOp_wait(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("WAIT"); + TRACE_AND_STEP(); + /* NADA. */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9c +****************************************************************************/ +void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) +{ + u32 flags; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSHFD\n"); + } else { + DECODE_PRINTF("PUSHF\n"); + } + TRACE_AND_STEP(); + + /* clear out *all* bits not representing flags, and turn on real bits */ + flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(flags); + } else { + push_word((u16)flags); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9d +****************************************************************************/ +void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POPFD\n"); + } else { + DECODE_PRINTF("POPF\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EFLG = pop_long(); + } else { + M.x86.R_FLG = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9e +****************************************************************************/ +void x86emuOp_sahf(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("SAHF\n"); + TRACE_AND_STEP(); + /* clear the lower bits of the flag register */ + M.x86.R_FLG &= 0xffffff00; + /* or in the AH register into the flags register */ + M.x86.R_FLG |= M.x86.R_AH; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9f +****************************************************************************/ +void x86emuOp_lahf(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LAHF\n"); + TRACE_AND_STEP(); + M.x86.R_AH = (u8)(M.x86.R_FLG & 0xff); + /*undocumented TC++ behavior??? Nope. It's documented, but + you have too look real hard to notice it. */ + M.x86.R_AH |= 0x2; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa0 +****************************************************************************/ +void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAL,"); + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]\n", offset); + TRACE_AND_STEP(); + M.x86.R_AL = fetch_data_byte(offset); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa1 +****************************************************************************/ +void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + offset = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); + } else { + DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(offset); + } else { + M.x86.R_AX = fetch_data_word(offset); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa2 +****************************************************************************/ +void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x],AL\n", offset); + TRACE_AND_STEP(); + store_data_byte(offset, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa3 +****************************************************************************/ +void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + offset = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); + } else { + DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long(offset, M.x86.R_EAX); + } else { + store_data_word(offset, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa4 +****************************************************************************/ +void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) +{ + u8 val; + u32 count; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("MOVS\tBYTE\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + val = fetch_data_byte(M.x86.R_SI); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa5 +****************************************************************************/ +void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) +{ + u32 val; + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOVS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("MOVS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long(M.x86.R_SI); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); + } else { + val = fetch_data_word(M.x86.R_SI); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa6 +****************************************************************************/ +void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) +{ + s8 val1, val2; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("CMPS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && (ACCESS_FLAG(F_ZF) == 0) ) break; + if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa7 +****************************************************************************/ +void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) +{ + u32 val1,val2; + int inc; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CMPS\tDWORD\n"); + inc = 4; + } else { + DECODE_PRINTF("CMPS\tWORD\n"); + inc = 2; + } + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -inc; + + TRACE_AND_STEP(); + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && ACCESS_FLAG(F_ZF) == 0 ) break; + if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa8 +****************************************************************************/ +void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + int imm; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\tAL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%04x\n", imm); + TRACE_AND_STEP(); + test_byte(M.x86.R_AL, (u8)imm); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa9 +****************************************************************************/ +void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("TEST\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("TEST\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + test_long(M.x86.R_EAX, srcval); + } else { + test_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xaa +****************************************************************************/ +void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) +{ + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("STOS\tBYTE\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + TRACE_AND_STEP(); + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xab +****************************************************************************/ +void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("STOS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("STOS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); + } else { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); + } + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xac +****************************************************************************/ +void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) +{ + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("LODS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_SI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xad +****************************************************************************/ +void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("LODS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("LODS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(M.x86.R_SI); + } else { + M.x86.R_AX = fetch_data_word(M.x86.R_SI); + } + M.x86.R_SI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xae +****************************************************************************/ +void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) +{ + s8 val2; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("SCAS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xaf +****************************************************************************/ +void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 val; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SCAS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("SCAS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb0 - 0xb7 +****************************************************************************/ +void x86emuOp_mov_byte_register_IMM(u8 op1) +{ + u8 imm, *ptr; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + ptr = DECODE_RM_BYTE_REGISTER(op1 & 0x7); + DECODE_PRINTF(","); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + *ptr = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb8 - 0xbf +****************************************************************************/ +void x86emuOp_mov_word_register_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + op1 &= 0x7; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *reg32; + reg32 = DECODE_RM_LONG_REGISTER(op1); + srcval = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", srcval); + TRACE_AND_STEP(); + *reg32 = srcval; + } else { + u16 *reg16; + reg16 = DECODE_RM_WORD_REGISTER(op1); + srcval = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", srcval); + TRACE_AND_STEP(); + *reg16 = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc0 +****************************************************************************/ +void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + if (mod < 3) { + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc1 +****************************************************************************/ +void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + if (mod < 3) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc2 +****************************************************************************/ +void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 imm; + + START_OF_INSTR(); + DECODE_PRINTF("RET\t"); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_SP += imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc3 +****************************************************************************/ +void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("RET\n"); + RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc4 +****************************************************************************/ +void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LES\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + } + /* else UNDEFINED! register to register */ + + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc5 +****************************************************************************/ +void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LDS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + } + /* else UNDEFINED! */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc6 +****************************************************************************/ +void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); + HALT_SYS(); + } + if (mod < 3) { + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc7 +****************************************************************************/ +void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); + } + if (mod < 3) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } else { + u16 *destreg; + u16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc8 +****************************************************************************/ +void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) +{ + u16 local,frame_pointer; + u8 nesting; + int i; + + START_OF_INSTR(); + local = fetch_word_imm(); + nesting = fetch_byte_imm(); + DECODE_PRINTF2("ENTER %x\n", local); + DECODE_PRINTF2(",%x\n", nesting); + TRACE_AND_STEP(); + push_word(M.x86.R_BP); + frame_pointer = M.x86.R_SP; + if (nesting > 0) { + for (i = 1; i < nesting; i++) { + M.x86.R_BP -= 2; + push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); + } + push_word(frame_pointer); + } + M.x86.R_BP = frame_pointer; + M.x86.R_SP = (u16)(M.x86.R_SP - local); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc9 +****************************************************************************/ +void x86emuOp_leave(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LEAVE\n"); + TRACE_AND_STEP(); + M.x86.R_SP = M.x86.R_BP; + M.x86.R_BP = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xca +****************************************************************************/ +void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 imm; + + START_OF_INSTR(); + DECODE_PRINTF("RETF\t"); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_SP += imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcb +****************************************************************************/ +void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("RETF\n"); + RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcc +****************************************************************************/ +void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) +{ + u16 tmp; + + START_OF_INSTR(); + DECODE_PRINTF("INT 3\n"); + tmp = (u16) mem_access_word(3 * 4 + 2); + /* access the segment register */ + TRACE_AND_STEP(); + if (_X86EMU_intrTab[3]) { + (*_X86EMU_intrTab[3])(3); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(3 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(3 * 4); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcd +****************************************************************************/ +void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 tmp; + u8 intnum; + + START_OF_INSTR(); + DECODE_PRINTF("INT\t"); + intnum = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", intnum); + tmp = mem_access_word(intnum * 4 + 2); + TRACE_AND_STEP(); + if (_X86EMU_intrTab[intnum]) { + (*_X86EMU_intrTab[intnum])(intnum); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intnum * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intnum * 4); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xce +****************************************************************************/ +void x86emuOp_into(u8 X86EMU_UNUSED(op1)) +{ + u16 tmp; + + START_OF_INSTR(); + DECODE_PRINTF("INTO\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_OF)) { + tmp = mem_access_word(4 * 4 + 2); + if (_X86EMU_intrTab[4]) { + (*_X86EMU_intrTab[4])(4); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(4 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(4 * 4); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcf +****************************************************************************/ +void x86emuOp_iret(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("IRET\n"); + + TRACE_AND_STEP(); + + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_FLG = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd0 +****************************************************************************/ +void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + if (mod < 3) { + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, 1); + *destreg = destval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd1 +****************************************************************************/ +void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + if (mod < 3) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (*destreg, 1); + *destreg = destval; + } else { + u16 destval; + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (*destreg, 1); + *destreg = destval; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd2 +****************************************************************************/ +void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + amt = M.x86.R_CL; + if (mod < 3) { + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd3 +****************************************************************************/ +void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + amt = M.x86.R_CL; + if (mod < 3) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd4 +****************************************************************************/ +void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) +{ + u8 a; + + START_OF_INSTR(); + DECODE_PRINTF("AAM\n"); + a = fetch_byte_imm(); /* this is a stupid encoding. */ + if (a != 10) { + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); + } + TRACE_AND_STEP(); + /* note the type change here --- returning AL and AH in AX. */ + M.x86.R_AX = aam_word(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd5 +****************************************************************************/ +void x86emuOp_aad(u8 X86EMU_UNUSED(op1)) +{ + u8 a; + + START_OF_INSTR(); + DECODE_PRINTF("AAD\n"); + a = fetch_byte_imm(); + TRACE_AND_STEP(); + M.x86.R_AX = aad_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* opcode 0xd6 ILLEGAL OPCODE */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xd7 +****************************************************************************/ +void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) +{ + u16 addr; + + START_OF_INSTR(); + DECODE_PRINTF("XLAT\n"); + TRACE_AND_STEP(); + addr = (u16)(M.x86.R_BX + (u8)M.x86.R_AL); + M.x86.R_AL = fetch_data_byte(addr); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* instuctions D8 .. DF are in i87_ops.c */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xe0 +****************************************************************************/ +void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOPNE\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe1 +****************************************************************************/ +void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOPE\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe2 +****************************************************************************/ +void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOP\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0) + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe3 +****************************************************************************/ +void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) +{ + u16 target; + s8 offset; + + /* jump to byte offset if overflow flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JCXZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (M.x86.R_CX == 0) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe4 +****************************************************************************/ +void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("IN\t"); + port = (u8) fetch_byte_imm(); + DECODE_PRINTF2("%x,AL\n", port); + TRACE_AND_STEP(); + M.x86.R_AL = (*sys_inb)(port); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe5 +****************************************************************************/ +void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("IN\t"); + port = (u8) fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("EAX,%x\n", port); + } else { + DECODE_PRINTF2("AX,%x\n", port); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = (*sys_inl)(port); + } else { + M.x86.R_AX = (*sys_inw)(port); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe6 +****************************************************************************/ +void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("OUT\t"); + port = (u8) fetch_byte_imm(); + DECODE_PRINTF2("%x,AL\n", port); + TRACE_AND_STEP(); + (*sys_outb)(port, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe7 +****************************************************************************/ +void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("OUT\t"); + port = (u8) fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("%x,EAX\n", port); + } else { + DECODE_PRINTF2("%x,AX\n", port); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + (*sys_outl)(port, M.x86.R_EAX); + } else { + (*sys_outw)(port, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe8 +****************************************************************************/ +void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("CALL\t"); + ip = (s16) fetch_word_imm(); + ip += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", ip); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, ""); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe9 +****************************************************************************/ +void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + int ip; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\t"); + ip = (s16)fetch_word_imm(); + ip += (s16)M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_IP = (u16)ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xea +****************************************************************************/ +void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 cs, ip; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\tFAR "); + ip = fetch_word_imm(); + cs = fetch_word_imm(); + DECODE_PRINTF2("%04x:", cs); + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_IP = ip; + M.x86.R_CS = cs; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xeb +****************************************************************************/ +void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 target; + s8 offset; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xec +****************************************************************************/ +void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("IN\tAL,DX\n"); + TRACE_AND_STEP(); + M.x86.R_AL = (*sys_inb)(M.x86.R_DX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xed +****************************************************************************/ +void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("IN\tEAX,DX\n"); + } else { + DECODE_PRINTF("IN\tAX,DX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); + } else { + M.x86.R_AX = (*sys_inw)(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xee +****************************************************************************/ +void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("OUT\tDX,AL\n"); + TRACE_AND_STEP(); + (*sys_outb)(M.x86.R_DX, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xef +****************************************************************************/ +void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OUT\tDX,EAX\n"); + } else { + DECODE_PRINTF("OUT\tDX,AX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); + } else { + (*sys_outw)(M.x86.R_DX, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf0 +****************************************************************************/ +void x86emuOp_lock(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LOCK:\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*opcode 0xf1 ILLEGAL OPERATION */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xf2 +****************************************************************************/ +void x86emuOp_repne(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("REPNE\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_REPNE; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf3 +****************************************************************************/ +void x86emuOp_repe(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("REPE\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_REPE; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf4 +****************************************************************************/ +void x86emuOp_halt(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("HALT\n"); + TRACE_AND_STEP(); + HALT_SYS(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf5 +****************************************************************************/ +void x86emuOp_cmc(u8 X86EMU_UNUSED(op1)) +{ + /* complement the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("CMC\n"); + TRACE_AND_STEP(); + TOGGLE_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf6 +****************************************************************************/ +void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval, srcval; + + /* long, drawn out code follows. Double switch for a total + of 32 cases. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTF(opF6_names[rh]); + if (mod < 3) { + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_byte(destoffset); + + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(destval); + break; + default: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + } else { /* mod=11 */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_byte(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_byte(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(*destreg); + break; + default: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(*destreg); + break; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf7 +****************************************************************************/ +void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTF(opF6_names[rh]); + if (mod < 3) { + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval, srcval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_long(destoffset); + + switch (rh) { + case 0: + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(destval); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(destval); + break; + } + } else { + u16 destval, srcval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_word(destoffset); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(destval); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(destval); + break; + } + } + + } else { /* mod=11 */ + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rl); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_long(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_long(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(*destreg); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(*destreg); + break; + } + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rl); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_word(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_word(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(*destreg); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(*destreg); + break; + } + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf8 +****************************************************************************/ +void x86emuOp_clc(u8 X86EMU_UNUSED(op1)) +{ + /* clear the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("CLC\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf9 +****************************************************************************/ +void x86emuOp_stc(u8 X86EMU_UNUSED(op1)) +{ + /* set the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("STC\n"); + TRACE_AND_STEP(); + SET_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfa +****************************************************************************/ +void x86emuOp_cli(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("CLI\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_IF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfb +****************************************************************************/ +void x86emuOp_sti(u8 X86EMU_UNUSED(op1)) +{ + /* enable interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("STI\n"); + TRACE_AND_STEP(); + SET_FLAG(F_IF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfc +****************************************************************************/ +void x86emuOp_cld(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("CLD\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_DF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfd +****************************************************************************/ +void x86emuOp_std(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("STD\n"); + TRACE_AND_STEP(); + SET_FLAG(F_DF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfe +****************************************************************************/ +void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u8 destval; + uint destoffset; + u8 *destreg; + + /* Yet another special case instruction. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("INC\t"); + break; + case 1: + DECODE_PRINTF("DEC\t"); + break; + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + HALT_SYS(); + break; + } + } +#endif + if (mod < 3) { + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + if (rh == 0) + destval = inc_byte(destval); + else + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + } else { + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + if (rh == 0) + *destreg = inc_byte(*destreg); + else + *destreg = dec_byte(*destreg); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xff +****************************************************************************/ +void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + uint destoffset = 0; + u16 *destreg; + u16 destval,destval2; + + /* Yet another special case instruction. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tDWORD PTR "); + } else { + DECODE_PRINTF("INC\tWORD PTR "); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tDWORD PTR "); + } else { + DECODE_PRINTF("DEC\tWORD PTR "); + } + break; + case 2: + DECODE_PRINTF("CALL\t "); + break; + case 3: + DECODE_PRINTF("CALL\tFAR "); + break; + case 4: + DECODE_PRINTF("JMP\t"); + break; + case 5: + DECODE_PRINTF("JMP\tFAR "); + break; + case 6: + DECODE_PRINTF("PUSH\t"); + break; + case 7: + DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); + HALT_SYS(); + break; + } + } +#endif + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: /* dec word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + } else { + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_word(*destreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_word(*destreg); + } + break; + case 2: /* call word ptr ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = *destreg; + break; + case 3: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + + case 4: /* jmp ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + M.x86.R_IP = (u16) (*destreg); + break; + case 5: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*destreg); + } + break; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*************************************************************************** + * Single byte operation code table: + **************************************************************************/ +void (*x86emu_optab[256])(u8) __attribute__ ((section(".got2"))) = +{ +/* 0x00 */ x86emuOp_genop_byte_RM_R, +/* 0x01 */ x86emuOp_genop_word_RM_R, +/* 0x02 */ x86emuOp_genop_byte_R_RM, +/* 0x03 */ x86emuOp_genop_word_R_RM, +/* 0x04 */ x86emuOp_genop_byte_AL_IMM, +/* 0x05 */ x86emuOp_genop_word_AX_IMM, +/* 0x06 */ x86emuOp_push_ES, +/* 0x07 */ x86emuOp_pop_ES, + +/* 0x08 */ x86emuOp_genop_byte_RM_R, +/* 0x09 */ x86emuOp_genop_word_RM_R, +/* 0x0a */ x86emuOp_genop_byte_R_RM, +/* 0x0b */ x86emuOp_genop_word_R_RM, +/* 0x0c */ x86emuOp_genop_byte_AL_IMM, +/* 0x0d */ x86emuOp_genop_word_AX_IMM, +/* 0x0e */ x86emuOp_push_CS, +/* 0x0f */ x86emuOp_two_byte, + +/* 0x10 */ x86emuOp_genop_byte_RM_R, +/* 0x11 */ x86emuOp_genop_word_RM_R, +/* 0x12 */ x86emuOp_genop_byte_R_RM, +/* 0x13 */ x86emuOp_genop_word_R_RM, +/* 0x14 */ x86emuOp_genop_byte_AL_IMM, +/* 0x15 */ x86emuOp_genop_word_AX_IMM, +/* 0x16 */ x86emuOp_push_SS, +/* 0x17 */ x86emuOp_pop_SS, + +/* 0x18 */ x86emuOp_genop_byte_RM_R, +/* 0x19 */ x86emuOp_genop_word_RM_R, +/* 0x1a */ x86emuOp_genop_byte_R_RM, +/* 0x1b */ x86emuOp_genop_word_R_RM, +/* 0x1c */ x86emuOp_genop_byte_AL_IMM, +/* 0x1d */ x86emuOp_genop_word_AX_IMM, +/* 0x1e */ x86emuOp_push_DS, +/* 0x1f */ x86emuOp_pop_DS, + +/* 0x20 */ x86emuOp_genop_byte_RM_R, +/* 0x21 */ x86emuOp_genop_word_RM_R, +/* 0x22 */ x86emuOp_genop_byte_R_RM, +/* 0x23 */ x86emuOp_genop_word_R_RM, +/* 0x24 */ x86emuOp_genop_byte_AL_IMM, +/* 0x25 */ x86emuOp_genop_word_AX_IMM, +/* 0x26 */ x86emuOp_segovr_ES, +/* 0x27 */ x86emuOp_daa, + +/* 0x28 */ x86emuOp_genop_byte_RM_R, +/* 0x29 */ x86emuOp_genop_word_RM_R, +/* 0x2a */ x86emuOp_genop_byte_R_RM, +/* 0x2b */ x86emuOp_genop_word_R_RM, +/* 0x2c */ x86emuOp_genop_byte_AL_IMM, +/* 0x2d */ x86emuOp_genop_word_AX_IMM, +/* 0x2e */ x86emuOp_segovr_CS, +/* 0x2f */ x86emuOp_das, + +/* 0x30 */ x86emuOp_genop_byte_RM_R, +/* 0x31 */ x86emuOp_genop_word_RM_R, +/* 0x32 */ x86emuOp_genop_byte_R_RM, +/* 0x33 */ x86emuOp_genop_word_R_RM, +/* 0x34 */ x86emuOp_genop_byte_AL_IMM, +/* 0x35 */ x86emuOp_genop_word_AX_IMM, +/* 0x36 */ x86emuOp_segovr_SS, +/* 0x37 */ x86emuOp_aaa, + +/* 0x38 */ x86emuOp_genop_byte_RM_R, +/* 0x39 */ x86emuOp_genop_word_RM_R, +/* 0x3a */ x86emuOp_genop_byte_R_RM, +/* 0x3b */ x86emuOp_genop_word_R_RM, +/* 0x3c */ x86emuOp_genop_byte_AL_IMM, +/* 0x3d */ x86emuOp_genop_word_AX_IMM, +/* 0x3e */ x86emuOp_segovr_DS, +/* 0x3f */ x86emuOp_aas, + +/* 0x40 */ x86emuOp_inc_register, +/* 0x41 */ x86emuOp_inc_register, +/* 0x42 */ x86emuOp_inc_register, +/* 0x43 */ x86emuOp_inc_register, +/* 0x44 */ x86emuOp_inc_register, +/* 0x45 */ x86emuOp_inc_register, +/* 0x46 */ x86emuOp_inc_register, +/* 0x47 */ x86emuOp_inc_register, + +/* 0x48 */ x86emuOp_dec_register, +/* 0x49 */ x86emuOp_dec_register, +/* 0x4a */ x86emuOp_dec_register, +/* 0x4b */ x86emuOp_dec_register, +/* 0x4c */ x86emuOp_dec_register, +/* 0x4d */ x86emuOp_dec_register, +/* 0x4e */ x86emuOp_dec_register, +/* 0x4f */ x86emuOp_dec_register, + +/* 0x50 */ x86emuOp_push_register, +/* 0x51 */ x86emuOp_push_register, +/* 0x52 */ x86emuOp_push_register, +/* 0x53 */ x86emuOp_push_register, +/* 0x54 */ x86emuOp_push_register, +/* 0x55 */ x86emuOp_push_register, +/* 0x56 */ x86emuOp_push_register, +/* 0x57 */ x86emuOp_push_register, + +/* 0x58 */ x86emuOp_pop_register, +/* 0x59 */ x86emuOp_pop_register, +/* 0x5a */ x86emuOp_pop_register, +/* 0x5b */ x86emuOp_pop_register, +/* 0x5c */ x86emuOp_pop_register, +/* 0x5d */ x86emuOp_pop_register, +/* 0x5e */ x86emuOp_pop_register, +/* 0x5f */ x86emuOp_pop_register, + +/* 0x60 */ x86emuOp_push_all, +/* 0x61 */ x86emuOp_pop_all, +/* 0x62 */ x86emuOp_illegal_op, /* bound */ +/* 0x63 */ x86emuOp_illegal_op, /* arpl */ +/* 0x64 */ x86emuOp_segovr_FS, +/* 0x65 */ x86emuOp_segovr_GS, +/* 0x66 */ x86emuOp_prefix_data, +/* 0x67 */ x86emuOp_prefix_addr, + +/* 0x68 */ x86emuOp_push_word_IMM, +/* 0x69 */ x86emuOp_imul_word_IMM, +/* 0x6a */ x86emuOp_push_byte_IMM, +/* 0x6b */ x86emuOp_imul_byte_IMM, +/* 0x6c */ x86emuOp_ins_byte, +/* 0x6d */ x86emuOp_ins_word, +/* 0x6e */ x86emuOp_outs_byte, +/* 0x6f */ x86emuOp_outs_word, + +/* 0x70 */ x86emuOp_jump_near_cond, +/* 0x71 */ x86emuOp_jump_near_cond, +/* 0x72 */ x86emuOp_jump_near_cond, +/* 0x73 */ x86emuOp_jump_near_cond, +/* 0x74 */ x86emuOp_jump_near_cond, +/* 0x75 */ x86emuOp_jump_near_cond, +/* 0x76 */ x86emuOp_jump_near_cond, +/* 0x77 */ x86emuOp_jump_near_cond, + +/* 0x78 */ x86emuOp_jump_near_cond, +/* 0x79 */ x86emuOp_jump_near_cond, +/* 0x7a */ x86emuOp_jump_near_cond, +/* 0x7b */ x86emuOp_jump_near_cond, +/* 0x7c */ x86emuOp_jump_near_cond, +/* 0x7d */ x86emuOp_jump_near_cond, +/* 0x7e */ x86emuOp_jump_near_cond, +/* 0x7f */ x86emuOp_jump_near_cond, + +/* 0x80 */ x86emuOp_opc80_byte_RM_IMM, +/* 0x81 */ x86emuOp_opc81_word_RM_IMM, +/* 0x82 */ x86emuOp_opc82_byte_RM_IMM, +/* 0x83 */ x86emuOp_opc83_word_RM_IMM, +/* 0x84 */ x86emuOp_test_byte_RM_R, +/* 0x85 */ x86emuOp_test_word_RM_R, +/* 0x86 */ x86emuOp_xchg_byte_RM_R, +/* 0x87 */ x86emuOp_xchg_word_RM_R, + +/* 0x88 */ x86emuOp_mov_byte_RM_R, +/* 0x89 */ x86emuOp_mov_word_RM_R, +/* 0x8a */ x86emuOp_mov_byte_R_RM, +/* 0x8b */ x86emuOp_mov_word_R_RM, +/* 0x8c */ x86emuOp_mov_word_RM_SR, +/* 0x8d */ x86emuOp_lea_word_R_M, +/* 0x8e */ x86emuOp_mov_word_SR_RM, +/* 0x8f */ x86emuOp_pop_RM, + +/* 0x90 */ x86emuOp_nop, +/* 0x91 */ x86emuOp_xchg_word_AX_register, +/* 0x92 */ x86emuOp_xchg_word_AX_register, +/* 0x93 */ x86emuOp_xchg_word_AX_register, +/* 0x94 */ x86emuOp_xchg_word_AX_register, +/* 0x95 */ x86emuOp_xchg_word_AX_register, +/* 0x96 */ x86emuOp_xchg_word_AX_register, +/* 0x97 */ x86emuOp_xchg_word_AX_register, + +/* 0x98 */ x86emuOp_cbw, +/* 0x99 */ x86emuOp_cwd, +/* 0x9a */ x86emuOp_call_far_IMM, +/* 0x9b */ x86emuOp_wait, +/* 0x9c */ x86emuOp_pushf_word, +/* 0x9d */ x86emuOp_popf_word, +/* 0x9e */ x86emuOp_sahf, +/* 0x9f */ x86emuOp_lahf, + +/* 0xa0 */ x86emuOp_mov_AL_M_IMM, +/* 0xa1 */ x86emuOp_mov_AX_M_IMM, +/* 0xa2 */ x86emuOp_mov_M_AL_IMM, +/* 0xa3 */ x86emuOp_mov_M_AX_IMM, +/* 0xa4 */ x86emuOp_movs_byte, +/* 0xa5 */ x86emuOp_movs_word, +/* 0xa6 */ x86emuOp_cmps_byte, +/* 0xa7 */ x86emuOp_cmps_word, +/* 0xa8 */ x86emuOp_test_AL_IMM, +/* 0xa9 */ x86emuOp_test_AX_IMM, +/* 0xaa */ x86emuOp_stos_byte, +/* 0xab */ x86emuOp_stos_word, +/* 0xac */ x86emuOp_lods_byte, +/* 0xad */ x86emuOp_lods_word, +/* 0xac */ x86emuOp_scas_byte, +/* 0xad */ x86emuOp_scas_word, + +/* 0xb0 */ x86emuOp_mov_byte_register_IMM, +/* 0xb1 */ x86emuOp_mov_byte_register_IMM, +/* 0xb2 */ x86emuOp_mov_byte_register_IMM, +/* 0xb3 */ x86emuOp_mov_byte_register_IMM, +/* 0xb4 */ x86emuOp_mov_byte_register_IMM, +/* 0xb5 */ x86emuOp_mov_byte_register_IMM, +/* 0xb6 */ x86emuOp_mov_byte_register_IMM, +/* 0xb7 */ x86emuOp_mov_byte_register_IMM, + +/* 0xb8 */ x86emuOp_mov_word_register_IMM, +/* 0xb9 */ x86emuOp_mov_word_register_IMM, +/* 0xba */ x86emuOp_mov_word_register_IMM, +/* 0xbb */ x86emuOp_mov_word_register_IMM, +/* 0xbc */ x86emuOp_mov_word_register_IMM, +/* 0xbd */ x86emuOp_mov_word_register_IMM, +/* 0xbe */ x86emuOp_mov_word_register_IMM, +/* 0xbf */ x86emuOp_mov_word_register_IMM, + +/* 0xc0 */ x86emuOp_opcC0_byte_RM_MEM, +/* 0xc1 */ x86emuOp_opcC1_word_RM_MEM, +/* 0xc2 */ x86emuOp_ret_near_IMM, +/* 0xc3 */ x86emuOp_ret_near, +/* 0xc4 */ x86emuOp_les_R_IMM, +/* 0xc5 */ x86emuOp_lds_R_IMM, +/* 0xc6 */ x86emuOp_mov_byte_RM_IMM, +/* 0xc7 */ x86emuOp_mov_word_RM_IMM, +/* 0xc8 */ x86emuOp_enter, +/* 0xc9 */ x86emuOp_leave, +/* 0xca */ x86emuOp_ret_far_IMM, +/* 0xcb */ x86emuOp_ret_far, +/* 0xcc */ x86emuOp_int3, +/* 0xcd */ x86emuOp_int_IMM, +/* 0xce */ x86emuOp_into, +/* 0xcf */ x86emuOp_iret, + +/* 0xd0 */ x86emuOp_opcD0_byte_RM_1, +/* 0xd1 */ x86emuOp_opcD1_word_RM_1, +/* 0xd2 */ x86emuOp_opcD2_byte_RM_CL, +/* 0xd3 */ x86emuOp_opcD3_word_RM_CL, +/* 0xd4 */ x86emuOp_aam, +/* 0xd5 */ x86emuOp_aad, +/* 0xd6 */ x86emuOp_illegal_op, /* Undocumented SETALC instruction */ +/* 0xd7 */ x86emuOp_xlat, +/* 0xd8 */ NULL, /*x86emuOp_esc_coprocess_d8,*/ +/* 0xd9 */ NULL, /*x86emuOp_esc_coprocess_d9,*/ +/* 0xda */ NULL, /*x86emuOp_esc_coprocess_da,*/ +/* 0xdb */ NULL, /*x86emuOp_esc_coprocess_db,*/ +/* 0xdc */ NULL, /*x86emuOp_esc_coprocess_dc,*/ +/* 0xdd */ NULL, /*x86emuOp_esc_coprocess_dd,*/ +/* 0xde */ NULL, /*x86emuOp_esc_coprocess_de,*/ +/* 0xdf */ NULL, /*x86emuOp_esc_coprocess_df,*/ + +/* 0xe0 */ x86emuOp_loopne, +/* 0xe1 */ x86emuOp_loope, +/* 0xe2 */ x86emuOp_loop, +/* 0xe3 */ x86emuOp_jcxz, +/* 0xe4 */ x86emuOp_in_byte_AL_IMM, +/* 0xe5 */ x86emuOp_in_word_AX_IMM, +/* 0xe6 */ x86emuOp_out_byte_IMM_AL, +/* 0xe7 */ x86emuOp_out_word_IMM_AX, + +/* 0xe8 */ x86emuOp_call_near_IMM, +/* 0xe9 */ x86emuOp_jump_near_IMM, +/* 0xea */ x86emuOp_jump_far_IMM, +/* 0xeb */ x86emuOp_jump_byte_IMM, +/* 0xec */ x86emuOp_in_byte_AL_DX, +/* 0xed */ x86emuOp_in_word_AX_DX, +/* 0xee */ x86emuOp_out_byte_DX_AL, +/* 0xef */ x86emuOp_out_word_DX_AX, + +/* 0xf0 */ x86emuOp_lock, +/* 0xf1 */ x86emuOp_illegal_op, +/* 0xf2 */ x86emuOp_repne, +/* 0xf3 */ x86emuOp_repe, +/* 0xf4 */ x86emuOp_halt, +/* 0xf5 */ x86emuOp_cmc, +/* 0xf6 */ x86emuOp_opcF6_byte_RM, +/* 0xf7 */ x86emuOp_opcF7_word_RM, + +/* 0xf8 */ x86emuOp_clc, +/* 0xf9 */ x86emuOp_stc, +/* 0xfa */ x86emuOp_cli, +/* 0xfb */ x86emuOp_sti, +/* 0xfc */ x86emuOp_cld, +/* 0xfd */ x86emuOp_std, +/* 0xfe */ x86emuOp_opcFE_byte_RM, +/* 0xff */ x86emuOp_opcFF_word_RM, +}; diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c new file mode 100644 index 00000000000..2412b24cd80 --- /dev/null +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -0,0 +1,1770 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. +* Jason Jin +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 extended two-byte processor +* instructions. +* +* Jason port this file to u-boot. Put the function pointer into +* got2 sector. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +op1 - Instruction op code + +REMARKS: +Handles illegal opcodes. +****************************************************************************/ +void x86emuOp2_illegal_op( + u8 op2) +{ + START_OF_INSTR(); + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); + printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP-2,op2); + HALT_SYS(); + END_OF_INSTR(); +} + +#define xorl(a,b) ((a) && !(b)) || (!(a) && (b)) + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x80-0x8F +****************************************************************************/ +int x86emu_check_jump_condition(u8 op) +{ + switch (op) { + case 0x0: + DECODE_PRINTF("JO\t"); + return ACCESS_FLAG(F_OF); + case 0x1: + DECODE_PRINTF("JNO\t"); + return !ACCESS_FLAG(F_OF); + break; + case 0x2: + DECODE_PRINTF("JB\t"); + return ACCESS_FLAG(F_CF); + break; + case 0x3: + DECODE_PRINTF("JNB\t"); + return !ACCESS_FLAG(F_CF); + break; + case 0x4: + DECODE_PRINTF("JZ\t"); + return ACCESS_FLAG(F_ZF); + break; + case 0x5: + DECODE_PRINTF("JNZ\t"); + return !ACCESS_FLAG(F_ZF); + break; + case 0x6: + DECODE_PRINTF("JBE\t"); + return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; + case 0x7: + DECODE_PRINTF("JNBE\t"); + return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x8: + DECODE_PRINTF("JS\t"); + return ACCESS_FLAG(F_SF); + break; + case 0x9: + DECODE_PRINTF("JNS\t"); + return !ACCESS_FLAG(F_SF); + break; + case 0xa: + DECODE_PRINTF("JP\t"); + return ACCESS_FLAG(F_PF); + break; + case 0xb: + DECODE_PRINTF("JNP\t"); + return !ACCESS_FLAG(F_PF); + break; + case 0xc: + DECODE_PRINTF("JL\t"); + return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0xd: + DECODE_PRINTF("JNL\t"); + return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0xe: + DECODE_PRINTF("JLE\t"); + return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + default: + DECODE_PRINTF("JNLE\t"); + return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + } +} + +void x86emuOp2_long_jump(u8 op2) +{ + s32 target; + int cond; + + /* conditional jump to word offset. */ + START_OF_INSTR(); + cond = x86emu_check_jump_condition(op2 & 0xF); + target = (s16) fetch_word_imm(); + target += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", target); + TRACE_AND_STEP(); + if (cond) + M.x86.R_IP = (u16)target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x90-0x9F +****************************************************************************/ +void x86emuOp2_set_byte(u8 op2) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg; + char *name = 0; + int cond = 0; + + START_OF_INSTR(); + switch (op2) { + case 0x90: + name = "SETO\t"; + cond = ACCESS_FLAG(F_OF); + break; + case 0x91: + name = "SETNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; + case 0x92: + name = "SETB\t"; + cond = ACCESS_FLAG(F_CF); + break; + case 0x93: + name = "SETNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; + case 0x94: + name = "SETZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; + case 0x95: + name = "SETNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; + case 0x96: + name = "SETBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; + case 0x97: + name = "SETNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x98: + name = "SETS\t"; + cond = ACCESS_FLAG(F_SF); + break; + case 0x99: + name = "SETNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; + case 0x9a: + name = "SETP\t"; + cond = ACCESS_FLAG(F_PF); + break; + case 0x9b: + name = "SETNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; + case 0x9c: + name = "SETL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x9d: + name = "SETNL\t"; + cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x9e: + name = "SETLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + case 0x9f: + name = "SETNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + } + DECODE_PRINTF(name); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + TRACE_AND_STEP(); + *destreg = cond ? 0x01 : 0x00; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa0 +****************************************************************************/ +void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tFS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_FS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa1 +****************************************************************************/ +void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tFS\n"); + TRACE_AND_STEP(); + M.x86.R_FS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa3 +****************************************************************************/ +void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BT\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } else { + u16 *srcreg,*shiftreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa4 +****************************************************************************/ +void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + u8 shift; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,shift); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa5 +****************************************************************************/ +void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa8 +****************************************************************************/ +void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tGS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_GS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa9 +****************************************************************************/ +void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tGS\n"); + TRACE_AND_STEP(); + M.x86.R_GS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xaa +****************************************************************************/ +void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xac +****************************************************************************/ +void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + u8 shift; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,shift); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xad +****************************************************************************/ +void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xaf +****************************************************************************/ +void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_long(srcoffset); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + res = (s16)*destreg * (s16)*srcreg; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb2 +****************************************************************************/ +void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LSS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + } else { /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb3 +****************************************************************************/ +void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb4 +****************************************************************************/ +void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LFS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + } else { /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb5 +****************************************************************************/ +void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LGS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + } else { /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb6 +****************************************************************************/ +void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOVZX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb7 +****************************************************************************/ +void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg; + u32 srcval; + u16 *srcreg; + + START_OF_INSTR(); + DECODE_PRINTF("MOVZX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xba +****************************************************************************/ +void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u8 shift; + int bit; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (rh) { + case 4: + DECODE_PRINTF("BT\t"); + break; + case 5: + DECODE_PRINTF("BTS\t"); + break; + case 6: + DECODE_PRINTF("BTR\t"); + break; + case 7: + DECODE_PRINTF("BTC\t"); + break; + default: + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); + printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", + M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); + HALT_SYS(); + } + if (mod < 3) { + + srcoffset = decode_rmXX_address(mod, rl); + shift = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", shift); + TRACE_AND_STEP(); + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + shift = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", shift); + TRACE_AND_STEP(); + bit = shift & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } else { + u16 *srcreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + shift = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", shift); + TRACE_AND_STEP(); + bit = shift & 0xF; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbb +****************************************************************************/ +void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbc +****************************************************************************/ +void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("BSF\n"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg, *dstreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((*srcreg >> *dstreg) & 1) break; + } else { + u16 *srcreg, *dstreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((*srcreg >> *dstreg) & 1) break; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbd +****************************************************************************/ +void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("BSF\n"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg, *dstreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((*srcreg >> *dstreg) & 1) break; + } else { + u16 *srcreg, *dstreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((*srcreg >> *dstreg) & 1) break; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbe +****************************************************************************/ +void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOVSX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s8)*srcreg); + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s16)((s8)*srcreg); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbf +****************************************************************************/ +void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg; + u32 srcval; + u16 *srcreg; + + START_OF_INSTR(); + DECODE_PRINTF("MOVSX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (mod < 3) { + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s16)*srcreg); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*************************************************************************** + * Double byte operation code table: + **************************************************************************/ +void (*x86emu_optab2[256])(u8) __attribute__((section(".got2"))) = +{ +/* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ +/* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ +/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ +/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ +/* 0x04 */ x86emuOp2_illegal_op, +/* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ +/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ +/* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ +/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ +/* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */ +/* 0x0a */ x86emuOp2_illegal_op, +/* 0x0b */ x86emuOp2_illegal_op, +/* 0x0c */ x86emuOp2_illegal_op, +/* 0x0d */ x86emuOp2_illegal_op, +/* 0x0e */ x86emuOp2_illegal_op, +/* 0x0f */ x86emuOp2_illegal_op, + +/* 0x10 */ x86emuOp2_illegal_op, +/* 0x11 */ x86emuOp2_illegal_op, +/* 0x12 */ x86emuOp2_illegal_op, +/* 0x13 */ x86emuOp2_illegal_op, +/* 0x14 */ x86emuOp2_illegal_op, +/* 0x15 */ x86emuOp2_illegal_op, +/* 0x16 */ x86emuOp2_illegal_op, +/* 0x17 */ x86emuOp2_illegal_op, +/* 0x18 */ x86emuOp2_illegal_op, +/* 0x19 */ x86emuOp2_illegal_op, +/* 0x1a */ x86emuOp2_illegal_op, +/* 0x1b */ x86emuOp2_illegal_op, +/* 0x1c */ x86emuOp2_illegal_op, +/* 0x1d */ x86emuOp2_illegal_op, +/* 0x1e */ x86emuOp2_illegal_op, +/* 0x1f */ x86emuOp2_illegal_op, + +/* 0x20 */ x86emuOp2_illegal_op, /* mov reg32,creg (ring 0 PM) */ +/* 0x21 */ x86emuOp2_illegal_op, /* mov reg32,dreg (ring 0 PM) */ +/* 0x22 */ x86emuOp2_illegal_op, /* mov creg,reg32 (ring 0 PM) */ +/* 0x23 */ x86emuOp2_illegal_op, /* mov dreg,reg32 (ring 0 PM) */ +/* 0x24 */ x86emuOp2_illegal_op, /* mov reg32,treg (ring 0 PM) */ +/* 0x25 */ x86emuOp2_illegal_op, +/* 0x26 */ x86emuOp2_illegal_op, /* mov treg,reg32 (ring 0 PM) */ +/* 0x27 */ x86emuOp2_illegal_op, +/* 0x28 */ x86emuOp2_illegal_op, +/* 0x29 */ x86emuOp2_illegal_op, +/* 0x2a */ x86emuOp2_illegal_op, +/* 0x2b */ x86emuOp2_illegal_op, +/* 0x2c */ x86emuOp2_illegal_op, +/* 0x2d */ x86emuOp2_illegal_op, +/* 0x2e */ x86emuOp2_illegal_op, +/* 0x2f */ x86emuOp2_illegal_op, + +/* 0x30 */ x86emuOp2_illegal_op, +/* 0x31 */ x86emuOp2_illegal_op, +/* 0x32 */ x86emuOp2_illegal_op, +/* 0x33 */ x86emuOp2_illegal_op, +/* 0x34 */ x86emuOp2_illegal_op, +/* 0x35 */ x86emuOp2_illegal_op, +/* 0x36 */ x86emuOp2_illegal_op, +/* 0x37 */ x86emuOp2_illegal_op, +/* 0x38 */ x86emuOp2_illegal_op, +/* 0x39 */ x86emuOp2_illegal_op, +/* 0x3a */ x86emuOp2_illegal_op, +/* 0x3b */ x86emuOp2_illegal_op, +/* 0x3c */ x86emuOp2_illegal_op, +/* 0x3d */ x86emuOp2_illegal_op, +/* 0x3e */ x86emuOp2_illegal_op, +/* 0x3f */ x86emuOp2_illegal_op, + +/* 0x40 */ x86emuOp2_illegal_op, +/* 0x41 */ x86emuOp2_illegal_op, +/* 0x42 */ x86emuOp2_illegal_op, +/* 0x43 */ x86emuOp2_illegal_op, +/* 0x44 */ x86emuOp2_illegal_op, +/* 0x45 */ x86emuOp2_illegal_op, +/* 0x46 */ x86emuOp2_illegal_op, +/* 0x47 */ x86emuOp2_illegal_op, +/* 0x48 */ x86emuOp2_illegal_op, +/* 0x49 */ x86emuOp2_illegal_op, +/* 0x4a */ x86emuOp2_illegal_op, +/* 0x4b */ x86emuOp2_illegal_op, +/* 0x4c */ x86emuOp2_illegal_op, +/* 0x4d */ x86emuOp2_illegal_op, +/* 0x4e */ x86emuOp2_illegal_op, +/* 0x4f */ x86emuOp2_illegal_op, + +/* 0x50 */ x86emuOp2_illegal_op, +/* 0x51 */ x86emuOp2_illegal_op, +/* 0x52 */ x86emuOp2_illegal_op, +/* 0x53 */ x86emuOp2_illegal_op, +/* 0x54 */ x86emuOp2_illegal_op, +/* 0x55 */ x86emuOp2_illegal_op, +/* 0x56 */ x86emuOp2_illegal_op, +/* 0x57 */ x86emuOp2_illegal_op, +/* 0x58 */ x86emuOp2_illegal_op, +/* 0x59 */ x86emuOp2_illegal_op, +/* 0x5a */ x86emuOp2_illegal_op, +/* 0x5b */ x86emuOp2_illegal_op, +/* 0x5c */ x86emuOp2_illegal_op, +/* 0x5d */ x86emuOp2_illegal_op, +/* 0x5e */ x86emuOp2_illegal_op, +/* 0x5f */ x86emuOp2_illegal_op, + +/* 0x60 */ x86emuOp2_illegal_op, +/* 0x61 */ x86emuOp2_illegal_op, +/* 0x62 */ x86emuOp2_illegal_op, +/* 0x63 */ x86emuOp2_illegal_op, +/* 0x64 */ x86emuOp2_illegal_op, +/* 0x65 */ x86emuOp2_illegal_op, +/* 0x66 */ x86emuOp2_illegal_op, +/* 0x67 */ x86emuOp2_illegal_op, +/* 0x68 */ x86emuOp2_illegal_op, +/* 0x69 */ x86emuOp2_illegal_op, +/* 0x6a */ x86emuOp2_illegal_op, +/* 0x6b */ x86emuOp2_illegal_op, +/* 0x6c */ x86emuOp2_illegal_op, +/* 0x6d */ x86emuOp2_illegal_op, +/* 0x6e */ x86emuOp2_illegal_op, +/* 0x6f */ x86emuOp2_illegal_op, + +/* 0x70 */ x86emuOp2_illegal_op, +/* 0x71 */ x86emuOp2_illegal_op, +/* 0x72 */ x86emuOp2_illegal_op, +/* 0x73 */ x86emuOp2_illegal_op, +/* 0x74 */ x86emuOp2_illegal_op, +/* 0x75 */ x86emuOp2_illegal_op, +/* 0x76 */ x86emuOp2_illegal_op, +/* 0x77 */ x86emuOp2_illegal_op, +/* 0x78 */ x86emuOp2_illegal_op, +/* 0x79 */ x86emuOp2_illegal_op, +/* 0x7a */ x86emuOp2_illegal_op, +/* 0x7b */ x86emuOp2_illegal_op, +/* 0x7c */ x86emuOp2_illegal_op, +/* 0x7d */ x86emuOp2_illegal_op, +/* 0x7e */ x86emuOp2_illegal_op, +/* 0x7f */ x86emuOp2_illegal_op, + +/* 0x80 */ x86emuOp2_long_jump, +/* 0x81 */ x86emuOp2_long_jump, +/* 0x82 */ x86emuOp2_long_jump, +/* 0x83 */ x86emuOp2_long_jump, +/* 0x84 */ x86emuOp2_long_jump, +/* 0x85 */ x86emuOp2_long_jump, +/* 0x86 */ x86emuOp2_long_jump, +/* 0x87 */ x86emuOp2_long_jump, +/* 0x88 */ x86emuOp2_long_jump, +/* 0x89 */ x86emuOp2_long_jump, +/* 0x8a */ x86emuOp2_long_jump, +/* 0x8b */ x86emuOp2_long_jump, +/* 0x8c */ x86emuOp2_long_jump, +/* 0x8d */ x86emuOp2_long_jump, +/* 0x8e */ x86emuOp2_long_jump, +/* 0x8f */ x86emuOp2_long_jump, + +/* 0x90 */ x86emuOp2_set_byte, +/* 0x91 */ x86emuOp2_set_byte, +/* 0x92 */ x86emuOp2_set_byte, +/* 0x93 */ x86emuOp2_set_byte, +/* 0x94 */ x86emuOp2_set_byte, +/* 0x95 */ x86emuOp2_set_byte, +/* 0x96 */ x86emuOp2_set_byte, +/* 0x97 */ x86emuOp2_set_byte, +/* 0x98 */ x86emuOp2_set_byte, +/* 0x99 */ x86emuOp2_set_byte, +/* 0x9a */ x86emuOp2_set_byte, +/* 0x9b */ x86emuOp2_set_byte, +/* 0x9c */ x86emuOp2_set_byte, +/* 0x9d */ x86emuOp2_set_byte, +/* 0x9e */ x86emuOp2_set_byte, +/* 0x9f */ x86emuOp2_set_byte, + +/* 0xa0 */ x86emuOp2_push_FS, +/* 0xa1 */ x86emuOp2_pop_FS, +/* 0xa2 */ x86emuOp2_illegal_op, +/* 0xa3 */ x86emuOp2_bt_R, +/* 0xa4 */ x86emuOp2_shld_IMM, +/* 0xa5 */ x86emuOp2_shld_CL, +/* 0xa6 */ x86emuOp2_illegal_op, +/* 0xa7 */ x86emuOp2_illegal_op, +/* 0xa8 */ x86emuOp2_push_GS, +/* 0xa9 */ x86emuOp2_pop_GS, +/* 0xaa */ x86emuOp2_illegal_op, +/* 0xab */ x86emuOp2_bt_R, +/* 0xac */ x86emuOp2_shrd_IMM, +/* 0xad */ x86emuOp2_shrd_CL, +/* 0xae */ x86emuOp2_illegal_op, +/* 0xaf */ x86emuOp2_imul_R_RM, + +/* 0xb0 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ +/* 0xb1 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ +/* 0xb2 */ x86emuOp2_lss_R_IMM, +/* 0xb3 */ x86emuOp2_btr_R, +/* 0xb4 */ x86emuOp2_lfs_R_IMM, +/* 0xb5 */ x86emuOp2_lgs_R_IMM, +/* 0xb6 */ x86emuOp2_movzx_byte_R_RM, +/* 0xb7 */ x86emuOp2_movzx_word_R_RM, +/* 0xb8 */ x86emuOp2_illegal_op, +/* 0xb9 */ x86emuOp2_illegal_op, +/* 0xba */ x86emuOp2_btX_I, +/* 0xbb */ x86emuOp2_btc_R, +/* 0xbc */ x86emuOp2_bsf, +/* 0xbd */ x86emuOp2_bsr, +/* 0xbe */ x86emuOp2_movsx_byte_R_RM, +/* 0xbf */ x86emuOp2_movsx_word_R_RM, + +/* 0xc0 */ x86emuOp2_illegal_op, /* TODO: xadd */ +/* 0xc1 */ x86emuOp2_illegal_op, /* TODO: xadd */ +/* 0xc2 */ x86emuOp2_illegal_op, +/* 0xc3 */ x86emuOp2_illegal_op, +/* 0xc4 */ x86emuOp2_illegal_op, +/* 0xc5 */ x86emuOp2_illegal_op, +/* 0xc6 */ x86emuOp2_illegal_op, +/* 0xc7 */ x86emuOp2_illegal_op, +/* 0xc8 */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xc9 */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xca */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcb */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcc */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcd */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xce */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcf */ x86emuOp2_illegal_op, /* TODO: bswap */ + +/* 0xd0 */ x86emuOp2_illegal_op, +/* 0xd1 */ x86emuOp2_illegal_op, +/* 0xd2 */ x86emuOp2_illegal_op, +/* 0xd3 */ x86emuOp2_illegal_op, +/* 0xd4 */ x86emuOp2_illegal_op, +/* 0xd5 */ x86emuOp2_illegal_op, +/* 0xd6 */ x86emuOp2_illegal_op, +/* 0xd7 */ x86emuOp2_illegal_op, +/* 0xd8 */ x86emuOp2_illegal_op, +/* 0xd9 */ x86emuOp2_illegal_op, +/* 0xda */ x86emuOp2_illegal_op, +/* 0xdb */ x86emuOp2_illegal_op, +/* 0xdc */ x86emuOp2_illegal_op, +/* 0xdd */ x86emuOp2_illegal_op, +/* 0xde */ x86emuOp2_illegal_op, +/* 0xdf */ x86emuOp2_illegal_op, + +/* 0xe0 */ x86emuOp2_illegal_op, +/* 0xe1 */ x86emuOp2_illegal_op, +/* 0xe2 */ x86emuOp2_illegal_op, +/* 0xe3 */ x86emuOp2_illegal_op, +/* 0xe4 */ x86emuOp2_illegal_op, +/* 0xe5 */ x86emuOp2_illegal_op, +/* 0xe6 */ x86emuOp2_illegal_op, +/* 0xe7 */ x86emuOp2_illegal_op, +/* 0xe8 */ x86emuOp2_illegal_op, +/* 0xe9 */ x86emuOp2_illegal_op, +/* 0xea */ x86emuOp2_illegal_op, +/* 0xeb */ x86emuOp2_illegal_op, +/* 0xec */ x86emuOp2_illegal_op, +/* 0xed */ x86emuOp2_illegal_op, +/* 0xee */ x86emuOp2_illegal_op, +/* 0xef */ x86emuOp2_illegal_op, + +/* 0xf0 */ x86emuOp2_illegal_op, +/* 0xf1 */ x86emuOp2_illegal_op, +/* 0xf2 */ x86emuOp2_illegal_op, +/* 0xf3 */ x86emuOp2_illegal_op, +/* 0xf4 */ x86emuOp2_illegal_op, +/* 0xf5 */ x86emuOp2_illegal_op, +/* 0xf6 */ x86emuOp2_illegal_op, +/* 0xf7 */ x86emuOp2_illegal_op, +/* 0xf8 */ x86emuOp2_illegal_op, +/* 0xf9 */ x86emuOp2_illegal_op, +/* 0xfa */ x86emuOp2_illegal_op, +/* 0xfb */ x86emuOp2_illegal_op, +/* 0xfc */ x86emuOp2_illegal_op, +/* 0xfd */ x86emuOp2_illegal_op, +/* 0xfe */ x86emuOp2_illegal_op, +/* 0xff */ x86emuOp2_illegal_op, +}; diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c new file mode 100644 index 00000000000..dc8cea80039 --- /dev/null +++ b/drivers/bios_emulator/x86emu/prim_ops.c @@ -0,0 +1,2446 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to implement the primitive +* machine operations used by the emulation code in ops.c +* +* Carry Chain Calculation +* +* This represents a somewhat expensive calculation which is +* apparently required to emulate the setting of the OF343364 and AF flag. +* The latter is not so important, but the former is. The overflow +* flag is the XOR of the top two bits of the carry chain for an +* addition (similar for subtraction). Since we do not want to +* simulate the addition in a bitwise manner, we try to calculate the +* carry chain given the two operands and the result. +* +* So, given the following table, which represents the addition of two +* bits, we can derive a formula for the carry chain. +* +* a b cin r cout +* 0 0 0 0 0 +* 0 0 1 1 0 +* 0 1 0 1 0 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 1 +* 1 1 0 0 1 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 1 1 +* 1 | 0 0 1 0 +* +* By inspection, one gets: cc = ab + r'(a + b) +* +* That represents alot of operations, but NO CHOICE.... +* +* Borrow Chain Calculation. +* +* The following table represents the subtraction of two bits, from +* which we can derive a formula for the borrow chain. +* +* a b bin r bout +* 0 0 0 0 0 +* 0 0 1 1 1 +* 0 1 0 1 1 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 0 +* 1 1 0 0 0 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 0 0 +* 1 | 1 1 1 0 +* +* By inspection, one gets: bc = a'b + r(a' + b) +* +****************************************************************************/ + +#define PRIM_OPS_NO_REDEFINE_ASM +#include "x86emu/x86emui.h" + +/*------------------------- Global Variables ------------------------------*/ + +static u32 x86emu_parity_tab[8] = +{ + 0x96696996, + 0x69969669, + 0x69969669, + 0x96696996, + 0x69969669, + 0x96696996, + 0x96696996, + 0x69969669, +}; + +#define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) +#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) +/*----------------------------- Implementation ----------------------------*/ +int abs(int v) +{ + return (v>0)?v:-v; +} + +/*----------------------------- Implementation ----------------------------*/ + + +/*--------- Side effects helper functions -------*/ + +/**************************************************************************** +REMARKS: +implements side efects for byte operations that don't overflow +****************************************************************************/ + +static void set_parity_flag(u32 res) +{ + CONDITIONAL_SET_FLAG(PARITY(res & 0xFF), F_PF); +} + +static void set_szp_flags_8(u8 res) +{ + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + set_parity_flag(res); +} + +static void set_szp_flags_16(u16 res) +{ + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + set_parity_flag(res); +} + +static void set_szp_flags_32(u32 res) +{ + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + set_parity_flag(res); +} + +static void no_carry_byte_side_eff(u8 res) +{ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + set_szp_flags_8(res); +} + +static void no_carry_word_side_eff(u16 res) +{ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + set_szp_flags_16(res); +} + +static void no_carry_long_side_eff(u32 res) +{ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + set_szp_flags_32(res); +} + +static void calc_carry_chain(int bits, u32 d, u32 s, u32 res, int set_carry) +{ + u32 cc; + + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> (bits - 2)), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + if (set_carry) { + CONDITIONAL_SET_FLAG(res & (1 << bits), F_CF); + } +} + +static void calc_borrow_chain(int bits, u32 d, u32 s, u32 res, int set_carry) +{ + u32 bc; + + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(XOR2(bc >> (bits - 2)), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + if (set_carry) { + CONDITIONAL_SET_FLAG(bc & (1 << (bits - 1)), F_CF); + } +} + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +u16 aaa_word(u16 d) +{ + u16 res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d += 0x6; + d += 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (u16)(d & 0xFF0F); + set_szp_flags_16(res); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +u16 aas_word(u16 d) +{ + u16 res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d -= 0x6; + d -= 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (u16)(d & 0xFF0F); + set_szp_flags_16(res); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AAD instruction and side effects. +****************************************************************************/ +u16 aad_word(u16 d) +{ + u16 l; + u8 hb, lb; + + hb = (u8)((d >> 8) & 0xff); + lb = (u8)((d & 0xff)); + l = (u16)((lb + 10 * hb) & 0xFF); + + no_carry_byte_side_eff(l & 0xFF); + return l; +} + +/**************************************************************************** +REMARKS: +Implements the AAM instruction and side effects. +****************************************************************************/ +u16 aam_word(u8 d) +{ + u16 h, l; + + h = (u16)(d / 10); + l = (u16)(d % 10); + l |= (u16)(h << 8); + + no_carry_byte_side_eff(l & 0xFF); + return l; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u8 adc_byte(u8 d, u8 s) +{ + u32 res; /* all operands in native machine order */ + + res = d + s; + if (ACCESS_FLAG(F_CF)) res++; + + set_szp_flags_8(res); + calc_carry_chain(8,s,d,res,1); + + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u16 adc_word(u16 d, u16 s) +{ + u32 res; /* all operands in native machine order */ + + res = d + s; + if (ACCESS_FLAG(F_CF)) + res++; + + set_szp_flags_16((u16)res); + calc_carry_chain(16,s,d,res,1); + + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u32 adc_long(u32 d, u32 s) +{ + u32 lo; /* all operands in native machine order */ + u32 hi; + u32 res; + + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + + if (ACCESS_FLAG(F_CF)) { + lo++; + res++; + } + + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + set_szp_flags_32(res); + calc_carry_chain(32,s,d,res,0); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u8 add_byte(u8 d, u8 s) +{ + u32 res; /* all operands in native machine order */ + + res = d + s; + set_szp_flags_8((u8)res); + calc_carry_chain(8,s,d,res,1); + + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u16 add_word(u16 d, u16 s) +{ + u32 res; /* all operands in native machine order */ + + res = d + s; + set_szp_flags_16((u16)res); + calc_carry_chain(16,s,d,res,1); + + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u32 add_long(u32 d, u32 s) +{ + u32 res; + + res = d + s; + set_szp_flags_32(res); + calc_carry_chain(32,s,d,res,0); + + CONDITIONAL_SET_FLAG(res < d || res < s, F_CF); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u8 and_byte(u8 d, u8 s) +{ + u8 res; /* all operands in native machine order */ + + res = d & s; + + no_carry_byte_side_eff(res); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u16 and_word(u16 d, u16 s) +{ + u16 res; /* all operands in native machine order */ + + res = d & s; + + no_carry_word_side_eff(res); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u32 and_long(u32 d, u32 s) +{ + u32 res; /* all operands in native machine order */ + + res = d & s; + no_carry_long_side_eff(res); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u8 cmp_byte(u8 d, u8 s) +{ + u32 res; /* all operands in native machine order */ + + res = d - s; + set_szp_flags_8((u8)res); + calc_borrow_chain(8, d, s, res, 1); + + return d; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u16 cmp_word(u16 d, u16 s) +{ + u32 res; /* all operands in native machine order */ + + res = d - s; + set_szp_flags_16((u16)res); + calc_borrow_chain(16, d, s, res, 1); + + return d; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u32 cmp_long(u32 d, u32 s) +{ + u32 res; /* all operands in native machine order */ + + res = d - s; + set_szp_flags_32(res); + calc_borrow_chain(32, d, s, res, 1); + + return d; +} + +/**************************************************************************** +REMARKS: +Implements the DAA instruction and side effects. +****************************************************************************/ +u8 daa_byte(u8 d) +{ + u32 res = d; + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + res += 6; + SET_FLAG(F_AF); + } + if (res > 0x9F || ACCESS_FLAG(F_CF)) { + res += 0x60; + SET_FLAG(F_CF); + } + set_szp_flags_8((u8)res); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the DAS instruction and side effects. +****************************************************************************/ +u8 das_byte(u8 d) +{ + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + d -= 6; + SET_FLAG(F_AF); + } + if (d > 0x9F || ACCESS_FLAG(F_CF)) { + d -= 0x60; + SET_FLAG(F_CF); + } + set_szp_flags_8(d); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u8 dec_byte(u8 d) +{ + u32 res; /* all operands in native machine order */ + + res = d - 1; + set_szp_flags_8((u8)res); + calc_borrow_chain(8, d, 1, res, 0); + + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u16 dec_word(u16 d) +{ + u32 res; /* all operands in native machine order */ + + res = d - 1; + set_szp_flags_16((u16)res); + calc_borrow_chain(16, d, 1, res, 0); + + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u32 dec_long(u32 d) +{ + u32 res; /* all operands in native machine order */ + + res = d - 1; + + set_szp_flags_32(res); + calc_borrow_chain(32, d, 1, res, 0); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u8 inc_byte(u8 d) +{ + u32 res; /* all operands in native machine order */ + + res = d + 1; + set_szp_flags_8((u8)res); + calc_carry_chain(8, d, 1, res, 0); + + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u16 inc_word(u16 d) +{ + u32 res; /* all operands in native machine order */ + + res = d + 1; + set_szp_flags_16((u16)res); + calc_carry_chain(16, d, 1, res, 0); + + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u32 inc_long(u32 d) +{ + u32 res; /* all operands in native machine order */ + + res = d + 1; + set_szp_flags_32(res); + calc_carry_chain(32, d, 1, res, 0); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u8 or_byte(u8 d, u8 s) +{ + u8 res; /* all operands in native machine order */ + + res = d | s; + no_carry_byte_side_eff(res); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u16 or_word(u16 d, u16 s) +{ + u16 res; /* all operands in native machine order */ + + res = d | s; + no_carry_word_side_eff(res); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u32 or_long(u32 d, u32 s) +{ + u32 res; /* all operands in native machine order */ + + res = d | s; + no_carry_long_side_eff(res); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u8 neg_byte(u8 s) +{ + u8 res; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u8)-s; + set_szp_flags_8(res); + calc_borrow_chain(8, 0, s, res, 0); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u16 neg_word(u16 s) +{ + u16 res; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u16)-s; + set_szp_flags_16((u16)res); + calc_borrow_chain(16, 0, s, res, 0); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u32 neg_long(u32 s) +{ + u32 res; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u32)-s; + set_szp_flags_32(res); + calc_borrow_chain(32, 0, s, res, 0); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u8 not_byte(u8 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u16 not_word(u16 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u32 not_long(u32 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u8 rcl_byte(u8 d, u8 s) +{ + unsigned int res, cnt, mask, cf; + + /* s is the rotate distance. It varies from 0 - 8. */ + /* have + + CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + + want to rotate through the carry by "s" bits. We could + loop, but that's inefficient. So the width is 9, + and we split into three parts: + + The new carry flag (was B_n) + the stuff in B_n-1 .. B_0 + the stuff in B_7 .. B_n+1 + + The new rotate is done mod 9, and given this, + for a rotation of n bits (mod 9) the new carry flag is + then located n bits from the MSB. The low part is + then shifted up cnt bits, and the high part is or'd + in. Using CAPS for new values, and lowercase for the + original values, this can be expressed as: + + IF n > 0 + 1) CF <- b_(8-n) + 2) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 + 3) B_(n-1) <- cf + 4) B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) + */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(8-n) */ + cf = (d >> (8 - cnt)) & 0x1; + + /* get the low stuff which rotated + into the range B_7 .. B_cnt */ + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ + /* note that the right hand side done by the mask */ + res = (d << cnt) & 0xff; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (9 - cnt)) & mask; + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(n-1) <- cf */ + res |= 1 << (cnt - 1); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized this expression since it appears to + be causing OF to be misset */ + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), + F_OF); + + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u16 rcl_word(u16 d, u8 s) +{ + unsigned int res, cnt, mask, cf; + + res = d; + if ((cnt = s % 17) != 0) { + cf = (d >> (16 - cnt)) & 0x1; + res = (d << cnt) & 0xffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (17 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), + F_OF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u32 rcl_long(u32 d, u8 s) +{ + u32 res, cnt, mask, cf; + + res = d; + if ((cnt = s % 33) != 0) { + cf = (d >> (32 - cnt)) & 0x1; + res = (d << cnt) & 0xffffffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (33 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), + F_OF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u8 rcr_byte(u8 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + + The new rotate is done mod 9, and given this, + for a rotation of n bits (mod 9) the new carry flag is + then located n bits from the LSB. The low part is + then shifted up cnt bits, and the high part is or'd + in. Using CAPS for new values, and lowercase for the + original values, this can be expressed as: + + IF n > 0 + 1) CF <- b_(n-1) + 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 3) B_(8-n) <- cf + 4) B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) + */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(n-1) */ + if (cnt == 1) { + cf = d & 0x1; + /* note hackery here. Access_flag(..) evaluates to either + 0 if flag not set + non-zero if flag is set. + doing access_flag(..) != 0 casts that into either + 0..1 in any representation of the flags register + (i.e. packed bit array or unpacked.) + */ + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ + /* note that the right hand side done by the mask + This is effectively done by shifting the + object to the right. The result must be masked, + in case the object came in and was treated + as a negative number. Needed??? */ + + mask = (1 << (8 - cnt)) - 1; + res = (d >> cnt) & mask; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + res |= (d << (9 - cnt)); + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(8-n) <- cf */ + res |= 1 << (8 - cnt); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized... */ + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), + F_OF); + } + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u16 rcr_word(u16 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 17) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (16 - cnt)) - 1; + res = (d >> cnt) & mask; + res |= (d << (17 - cnt)); + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (16 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), + F_OF); + } + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u32 rcr_long(u32 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 33) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (32 - cnt)) - 1; + res = (d >> cnt) & mask; + if (cnt != 1) + res |= (d << (33 - cnt)); + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (32 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), + F_OF); + } + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u8 rol_byte(u8 d, u8 s) +{ + unsigned int res, cnt, mask; + + /* rotate left */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + CF B_7 ... B_0 + + The new rotate is done mod 8. + Much simpler than the "rcl" or "rcr" operations. + + IF n > 0 + 1) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) + 2) B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) + */ + res = d; + if ((cnt = s % 8) != 0) { + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ + res = (d << cnt); + + /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ + mask = (1 << cnt) - 1; + res |= (d >> (8 - cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of CF and the most significant bit. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 6) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u16 rol_word(u16 d, u8 s) +{ + unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (16 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 14) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u32 rol_long(u32 d, u8 s) +{ + u32 res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (32 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 30) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u8 ror_byte(u8 d, u8 s) +{ + unsigned int res, cnt, mask; + + /* rotate right */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + B_7 ... B_0 + + The rotate is done mod 8. + + IF n > 0 + 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 2) B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) + */ + res = d; + if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ + /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ + res = (d << (8 - cnt)); + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ + mask = (1 << (8 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of the two most significant bits. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u16 ror_word(u16 d, u8 s) +{ + unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << (16 - cnt)); + mask = (1 << (16 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u32 ror_long(u32 d, u8 s) +{ + u32 res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << (32 - cnt)); + mask = (1 << (32 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u8 shl_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + + /* last bit shifted out goes into carry flag */ + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (8 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_8((u8)res); + } else { + res = (u8) d; + } + + if (cnt == 1) { + /* Needs simplification. */ + CONDITIONAL_SET_FLAG( + (((res & 0x80) == 0x80) ^ + (ACCESS_FLAG(F_CF) != 0)), + /* was (M.x86.R_FLG&F_CF)==F_CF)), */ + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u16 shl_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = (u16) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG( + (((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u32 shl_long(u32 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u8 shr_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_8((u8)res); + } else { + res = (u8) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u16 shr_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u32 shr_long(u32 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u8 sar_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf, mask, sf; + + res = d; + sf = d & 0x80; + cnt = s % 8; + if (cnt > 0 && cnt < 8) { + mask = (1 << (8 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + set_szp_flags_8((u8)res); + } else if (cnt >= 8) { + if (sf) { + res = 0xff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u16 sar_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf, mask, sf; + + sf = d & 0x8000; + cnt = s % 16; + res = d; + if (cnt > 0 && cnt < 16) { + mask = (1 << (16 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + set_szp_flags_16((u16)res); + } else if (cnt >= 16) { + if (sf) { + res = 0xffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u32 sar_long(u32 d, u8 s) +{ + u32 cnt, res, cf, mask, sf; + + sf = d & 0x80000000; + cnt = s % 32; + res = d; + if (cnt > 0 && cnt < 32) { + mask = (1 << (32 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + set_szp_flags_32(res); + } else if (cnt >= 32) { + if (sf) { + res = 0xffffffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +u16 shld_word (u16 d, u16 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = (d << cnt) | (fill >> (16-cnt)); + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +u32 shld_long (u32 d, u32 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = (d << cnt) | (fill >> (32-cnt)); + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +u16 shrd_word (u16 d, u16 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +u32 shrd_long (u32 d, u32 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u8 sbb_byte(u8 d, u8 s) +{ + u32 res; /* all operands in native machine order */ + u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + set_szp_flags_8((u8)res); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u16 sbb_word(u16 d, u16 s) +{ + u32 res; /* all operands in native machine order */ + u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + set_szp_flags_16((u16)res); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u32 sbb_long(u32 d, u32 s) +{ + u32 res; /* all operands in native machine order */ + u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + + set_szp_flags_32(res); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u8 sub_byte(u8 d, u8 s) +{ + u32 res; /* all operands in native machine order */ + u32 bc; + + res = d - s; + set_szp_flags_8((u8)res); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u16 sub_word(u16 d, u16 s) +{ + u32 res; /* all operands in native machine order */ + u32 bc; + + res = d - s; + set_szp_flags_16((u16)res); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u32 sub_long(u32 d, u32 s) +{ + u32 res; /* all operands in native machine order */ + u32 bc; + + res = d - s; + set_szp_flags_32(res); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_byte(u8 d, u8 s) +{ + u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + set_szp_flags_8((u8)res); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_word(u16 d, u16 s) +{ + u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + set_szp_flags_16((u16)res); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_long(u32 d, u32 s) +{ + u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + set_szp_flags_32(res); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u8 xor_byte(u8 d, u8 s) +{ + u8 res; /* all operands in native machine order */ + + res = d ^ s; + no_carry_byte_side_eff(res); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u16 xor_word(u16 d, u16 s) +{ + u16 res; /* all operands in native machine order */ + + res = d ^ s; + no_carry_word_side_eff(res); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u32 xor_long(u32 d, u32 s) +{ + u32 res; /* all operands in native machine order */ + + res = d ^ s; + no_carry_long_side_eff(res); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_byte(u8 s) +{ + s16 res = (s16)((s8)M.x86.R_AL * (s8)s); + + M.x86.R_AX = res; + if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) || + ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_word(u16 s) +{ + s32 res = (s16)M.x86.R_AX * (s16)s; + + M.x86.R_AX = (u16)res; + M.x86.R_DX = (u16)(res >> 16); + if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x0000) || + ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFFFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) +{ +#ifdef __HAS_LONG_LONG__ + s64 res = (s32)d * (s32)s; + + *res_lo = (u32)res; + *res_hi = (u32)(res >> 32); +#else + u32 d_lo,d_hi,d_sign; + u32 s_lo,s_hi,s_sign; + u32 rlo_lo,rlo_hi,rhi_lo; + + if ((d_sign = d & 0x80000000) != 0) + d = -d; + d_lo = d & 0xFFFF; + d_hi = d >> 16; + if ((s_sign = s & 0x80000000) != 0) + s = -s; + s_lo = s & 0xFFFF; + s_hi = s >> 16; + rlo_lo = d_lo * s_lo; + rlo_hi = (d_hi * s_lo + d_lo * s_hi) + (rlo_lo >> 16); + rhi_lo = d_hi * s_hi + (rlo_hi >> 16); + *res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF); + *res_hi = rhi_lo; + if (d_sign != s_sign) { + d = ~*res_lo; + s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); + *res_lo = ~*res_lo+1; + *res_hi = ~*res_hi+(s >> 16); + } +#endif +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_long(u32 s) +{ + imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); + if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00000000) || + ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFFFFFFFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_byte(u8 s) +{ + u16 res = (u16)(M.x86.R_AL * s); + + M.x86.R_AX = res; + if (M.x86.R_AH == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_word(u16 s) +{ + u32 res = M.x86.R_AX * s; + + M.x86.R_AX = (u16)res; + M.x86.R_DX = (u16)(res >> 16); + if (M.x86.R_DX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + u64 res = (u32)M.x86.R_EAX * (u32)s; + + M.x86.R_EAX = (u32)res; + M.x86.R_EDX = (u32)(res >> 32); +#else + u32 a,a_lo,a_hi; + u32 s_lo,s_hi; + u32 rlo_lo,rlo_hi,rhi_lo; + + a = M.x86.R_EAX; + a_lo = a & 0xFFFF; + a_hi = a >> 16; + s_lo = s & 0xFFFF; + s_hi = s >> 16; + rlo_lo = a_lo * s_lo; + rlo_hi = (a_hi * s_lo + a_lo * s_hi) + (rlo_lo >> 16); + rhi_lo = a_hi * s_hi + (rlo_hi >> 16); + M.x86.R_EAX = (rlo_hi << 16) | (rlo_lo & 0xFFFF); + M.x86.R_EDX = rhi_lo; +#endif + if (M.x86.R_EDX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_byte(u8 s) +{ + s32 dvd, div, mod; + + dvd = (s16)M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s8)s; + mod = dvd % (s8)s; + if (abs(div) > 0x7f) { + x86emu_intr_raise(0); + return; + } + M.x86.R_AL = (s8) div; + M.x86.R_AH = (s8) mod; +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_word(u16 s) +{ + s32 dvd, div, mod; + + dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s16)s; + mod = dvd % (s16)s; + if (abs(div) > 0x7fff) { + x86emu_intr_raise(0); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + set_parity_flag(mod); + + M.x86.R_AX = (u16)div; + M.x86.R_DX = (u16)mod; +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + s64 dvd, div, mod; + + dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s32)s; + mod = dvd % (s32)s; + if (abs(div) > 0x7fffffff) { + x86emu_intr_raise(0); + return; + } +#else + s32 div = 0, mod; + s32 h_dvd = M.x86.R_EDX; + u32 l_dvd = M.x86.R_EAX; + u32 abs_s = s & 0x7FFFFFFF; + u32 abs_h_dvd = h_dvd & 0x7FFFFFFF; + u32 h_s = abs_s >> 1; + u32 l_s = abs_s << 31; + int counter = 31; + int carry; + + if (s == 0) { + x86emu_intr_raise(0); + return; + } + do { + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (abs_h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = abs_s << (--counter); + continue; + } else { + abs_h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = abs_s << (--counter); + div |= 1; + continue; + } + + } while (counter > -1); + /* overflow */ + if (abs_h_dvd || (l_dvd > abs_s)) { + x86emu_intr_raise(0); + return; + } + /* sign */ + div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000)); + mod = l_dvd; + +#endif + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + set_parity_flag(mod); + + M.x86.R_EAX = (u32)div; + M.x86.R_EDX = (u32)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_byte(u8 s) +{ + u32 dvd, div, mod; + + dvd = M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u8)s; + mod = dvd % (u8)s; + if (abs(div) > 0xff) { + x86emu_intr_raise(0); + return; + } + M.x86.R_AL = (u8)div; + M.x86.R_AH = (u8)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_word(u16 s) +{ + u32 dvd, div, mod; + + dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u16)s; + mod = dvd % (u16)s; + if (abs(div) > 0xffff) { + x86emu_intr_raise(0); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + set_parity_flag(mod); + + M.x86.R_AX = (u16)div; + M.x86.R_DX = (u16)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + u64 dvd, div, mod; + + dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u32)s; + mod = dvd % (u32)s; + if (abs(div) > 0xffffffff) { + x86emu_intr_raise(0); + return; + } +#else + s32 div = 0, mod; + s32 h_dvd = M.x86.R_EDX; + u32 l_dvd = M.x86.R_EAX; + + u32 h_s = s; + u32 l_s = 0; + int counter = 32; + int carry; + + if (s == 0) { + x86emu_intr_raise(0); + return; + } + do { + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = s << (--counter); + continue; + } else { + h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = s << (--counter); + div |= 1; + continue; + } + + } while (counter > -1); + /* overflow */ + if (h_dvd || (l_dvd > s)) { + x86emu_intr_raise(0); + return; + } + mod = l_dvd; +#endif + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + set_parity_flag(mod); + + M.x86.R_EAX = (u32)div; + M.x86.R_EDX = (u32)mod; +} + +/**************************************************************************** +REMARKS: +Implements the IN string instruction and side effects. +****************************************************************************/ + +static void single_in(int size) +{ + if(size == 1) + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inb)(M.x86.R_DX)); + else if (size == 2) + store_data_word_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inw)(M.x86.R_DX)); + else + store_data_long_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inl)(M.x86.R_DX)); +} + +void ins(int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* in until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + + while (count--) { + single_in(size); + M.x86.R_DI += inc; + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + single_in(size); + M.x86.R_DI += inc; + } +} + +/**************************************************************************** +REMARKS: +Implements the OUT string instruction and side effects. +****************************************************************************/ + +static void single_out(int size) +{ + if(size == 1) + (*sys_outb)(M.x86.R_DX,fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); + else if (size == 2) + (*sys_outw)(M.x86.R_DX,fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); + else + (*sys_outl)(M.x86.R_DX,fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); +} + +void outs(int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* out until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + while (count--) { + single_out(size); + M.x86.R_SI += inc; + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + single_out(size); + M.x86.R_SI += inc; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Address to fetch word from + +REMARKS: +Fetches a word from emulator memory using an absolute address. +****************************************************************************/ +u16 mem_access_word(int addr) +{ +DB( if (CHECK_MEM_ACCESS()) + x86emu_check_mem_access(addr);) + return (*sys_rdw)(addr); +} + +/**************************************************************************** +REMARKS: +Pushes a word onto the stack. + +NOTE: Do not inline this, as (*sys_wrX) is already inline! +****************************************************************************/ +void push_word(u16 w) +{ +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + M.x86.R_SP -= 2; + (*sys_wrw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); +} + +/**************************************************************************** +REMARKS: +Pushes a long onto the stack. + +NOTE: Do not inline this, as (*sys_wrX) is already inline! +****************************************************************************/ +void push_long(u32 w) +{ +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + M.x86.R_SP -= 4; + (*sys_wrl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); +} + +/**************************************************************************** +REMARKS: +Pops a word from the stack. + +NOTE: Do not inline this, as (*sys_rdX) is already inline! +****************************************************************************/ +u16 pop_word(void) +{ + u16 res; + +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + res = (*sys_rdw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); + M.x86.R_SP += 2; + return res; +} + +/**************************************************************************** +REMARKS: +Pops a long from the stack. + +NOTE: Do not inline this, as (*sys_rdX) is already inline! +****************************************************************************/ +u32 pop_long(void) +{ + u32 res; + +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + res = (*sys_rdl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); + M.x86.R_SP += 4; + return res; +} + diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c new file mode 100644 index 00000000000..bb7fcd93a94 --- /dev/null +++ b/drivers/bios_emulator/x86emu/sys.c @@ -0,0 +1,322 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines which are related to +* programmed I/O and memory access. Included in this module +* are default functions that do nothing. For real uses these +* functions will have to be overriden by the user library. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*------------------------- Global Variables ------------------------------*/ + +X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ +X86EMU_intrFuncs _X86EMU_intrTab[256]; + +int debug_intr; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Byte value read from emulator memory. + +REMARKS: +Reads a byte value from the emulator memory. +****************************************************************************/ +u8 X86API rdb(u32 addr) +{ + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Word value read from emulator memory. + +REMARKS: +Reads a word value from the emulator memory. +****************************************************************************/ +u16 X86API rdw(u32 addr) +{ + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Long value read from emulator memory. +REMARKS: +Reads a long value from the emulator memory. +****************************************************************************/ +u32 X86API rdl(u32 addr) +{ + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a byte value to emulator memory. +****************************************************************************/ +void X86API wrb(u32 addr, u8 val) +{ +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a word value to emulator memory. +****************************************************************************/ +void X86API wrw(u32 addr, u16 val) +{ +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a long value to emulator memory. +****************************************************************************/ +void X86API wrl(u32 addr, u32 val) +{ +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO byte read function. Doesn't perform real inb. +****************************************************************************/ +static u8 X86API p_inb(X86EMU_pioAddr addr) +{ + DB(if (DEBUG_IO_TRACE()) + printk("inb %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO word read function. Doesn't perform real inw. +****************************************************************************/ +static u16 X86API p_inw(X86EMU_pioAddr addr) +{ + DB(if (DEBUG_IO_TRACE()) + printk("inw %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO long read function. Doesn't perform real inl. +****************************************************************************/ +static u32 X86API p_inl(X86EMU_pioAddr addr) +{ + DB(if (DEBUG_IO_TRACE()) + printk("inl %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO byte write function. Doesn't perform real outb. +****************************************************************************/ +static void X86API p_outb(X86EMU_pioAddr addr, u8 val) +{ + DB(if (DEBUG_IO_TRACE()) + printk("outb %#02x -> %#04x \n", val, addr);) + return; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO word write function. Doesn't perform real outw. +****************************************************************************/ +static void X86API p_outw(X86EMU_pioAddr addr, u16 val) +{ + DB(if (DEBUG_IO_TRACE()) + printk("outw %#04x -> %#04x \n", val, addr);) + return; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO ;ong write function. Doesn't perform real outl. +****************************************************************************/ +static void X86API p_outl(X86EMU_pioAddr addr, u32 val) +{ + DB(if (DEBUG_IO_TRACE()) + printk("outl %#08x -> %#04x \n", val, addr);) + return; +} + +/*------------------------- Global Variables ------------------------------*/ + +u8(X86APIP sys_rdb) (u32 addr) = rdb; +u16(X86APIP sys_rdw) (u32 addr) = rdw; +u32(X86APIP sys_rdl) (u32 addr) = rdl; +void (X86APIP sys_wrb) (u32 addr, u8 val) = wrb; +void (X86APIP sys_wrw) (u32 addr, u16 val) = wrw; +void (X86APIP sys_wrl) (u32 addr, u32 val) = wrl; +u8(X86APIP sys_inb) (X86EMU_pioAddr addr) = p_inb; +u16(X86APIP sys_inw) (X86EMU_pioAddr addr) = p_inw; +u32(X86APIP sys_inl) (X86EMU_pioAddr addr) = p_inl; +void (X86APIP sys_outb) (X86EMU_pioAddr addr, u8 val) = p_outb; +void (X86APIP sys_outw) (X86EMU_pioAddr addr, u16 val) = p_outw; +void (X86APIP sys_outl) (X86EMU_pioAddr addr, u32 val) = p_outl; + +/*----------------------------- Setup -------------------------------------*/ + +/**************************************************************************** +PARAMETERS: +funcs - New memory function pointers to make active + +REMARKS: +This function is used to set the pointers to functions which access +memory space, allowing the user application to override these functions +and hook them out as necessary for their application. +****************************************************************************/ +void X86EMU_setupMemFuncs(X86EMU_memFuncs * funcs) +{ + sys_rdb = funcs->rdb; + sys_rdw = funcs->rdw; + sys_rdl = funcs->rdl; + sys_wrb = funcs->wrb; + sys_wrw = funcs->wrw; + sys_wrl = funcs->wrl; +} + +/**************************************************************************** +PARAMETERS: +funcs - New programmed I/O function pointers to make active + +REMARKS: +This function is used to set the pointers to functions which access +I/O space, allowing the user application to override these functions +and hook them out as necessary for their application. +****************************************************************************/ +void X86EMU_setupPioFuncs(X86EMU_pioFuncs * funcs) +{ + sys_inb = funcs->inb; + sys_inw = funcs->inw; + sys_inl = funcs->inl; + sys_outb = funcs->outb; + sys_outw = funcs->outw; + sys_outl = funcs->outl; +} + +/**************************************************************************** +PARAMETERS: +funcs - New interrupt vector table to make active + +REMARKS: +This function is used to set the pointers to functions which handle +interrupt processing in the emulator, allowing the user application to +hook interrupts as necessary for their application. Any interrupts that +are not hooked by the user application, and reflected and handled internally +in the emulator via the interrupt vector table. This allows the application +to get control when the code being emulated executes specific software +interrupts. +****************************************************************************/ +void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]) +{ + int i; + + for (i = 0; i < 256; i++) + _X86EMU_intrTab[i] = NULL; + if (funcs) { + for (i = 0; i < 256; i++) + _X86EMU_intrTab[i] = funcs[i]; + } +} + +/**************************************************************************** +PARAMETERS: +int - New software interrupt to prepare for + +REMARKS: +This function is used to set up the emulator state to exceute a software +interrupt. This can be used by the user application code to allow an +interrupt to be hooked, examined and then reflected back to the emulator +so that the code in the emulator will continue processing the software +interrupt as per normal. This essentially allows system code to actively +hook and handle certain software interrupts as necessary. +****************************************************************************/ +void X86EMU_prepareForInt(int num) +{ + push_word((u16) M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(num * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(num * 4); + M.x86.intr = 0; +} -- cgit v1.3.1 From 9c7e4b06214db61bb21f1bcbe57c97519669baae Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 6 Aug 2007 02:17:36 +0200 Subject: Coding style cleanup. Update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 61 + drivers/ati_ids.h | 1 - drivers/ati_radeon_fb.c | 6 +- drivers/ati_radeon_fb.h | 19 +- drivers/bios_emulator/atibios.c | 48 +- drivers/bios_emulator/besys.c | 243 +- drivers/bios_emulator/biosemu.c | 84 +- drivers/bios_emulator/biosemui.h | 58 +- drivers/bios_emulator/include/x86emu/debug.h | 166 +- drivers/bios_emulator/include/x86emu/prim_ops.h | 1 - drivers/bios_emulator/include/x86emu/regs.h | 148 +- drivers/bios_emulator/x86emu/decode.c | 874 +++-- drivers/bios_emulator/x86emu/ops.c | 4610 +++++++++++------------ drivers/bios_emulator/x86emu/ops2.c | 1874 ++++----- drivers/bios_emulator/x86emu/prim_ops.c | 1389 ++++--- include/radeon.h | 3686 +++++++++--------- 16 files changed, 6653 insertions(+), 6615 deletions(-) (limited to 'drivers') diff --git a/CHANGELOG b/CHANGELOG index 58ef66ecdc4..e07d243bf3f 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,64 @@ +commit 221838cc7eb178370ff62aa05920a582e12ac322 +Author: Jason Jin +Date: Tue Jul 10 09:03:22 2007 +0800 + + Remove the bios emulator from MAI board. + + The bios emulator in the MAI board can not pass compile + and have a lot of crap in it. remove it and will have a + clean and small bios emulator in the drivers directory + which can be uesed for every board. + + Signed-off-by: Jason Jin + +commit 5618332409bb96f4448d1712899369fc80c0b489 +Author: Jason Jin +Date: Fri Jul 13 12:14:59 2007 +0800 + + Fix some compile issues for MAI board. + + Signed-off-by: Jason Jin + +commit 0f460a1ee148b648ee242c3157650287d4296260 +Author: Jason Jin +Date: Fri Jul 13 12:14:58 2007 +0800 + + Configurations for ATI video card BIOS emulator + + This patch add definition of the BIOS emulator and the ATI framebuffer + driver for MPC8641HPCN board. + + Signed-off-by: Jason Jin + Signed-off-by: Zhang Wei + +commit ece92f85053b8df613edcf05b26a416cbc3d629c +Author: Jason Jin +Date: Fri Jul 6 08:34:56 2007 +0800 + + This is a BIOS emulator, porting from SciTech for u-boot, mainly for + ATI video card BIOS. and can be used for x86 code emulation by some + modifications. + + Signed-off-by: Jason Jin + +commit 5072188acabde3178fac7f5a597150e6e74fd40c +Author: Jason Jin +Date: Fri Jul 6 08:33:33 2007 +0800 + + This is a framebuffer driver for ATI video card, can work for PCI9200, + X300, X700, X800 ATI video cards. + + Signed-off-by: Zhang Wei + Signed-off-by: Jason Jin + +commit 5728be389e65fd47f34b33c2596271eb4db751ae +Author: Wolfgang Denk +Date: Mon Aug 6 01:01:49 2007 +0200 + + Coding style cleanup. Update CHANGELOG. + + Signed-off-by: Wolfgang Denk + commit 8092fef4c29b395958bb649647da7e3775731517 Author: Martin Krause Date: Tue Dec 12 14:26:01 2006 +0100 diff --git a/drivers/ati_ids.h b/drivers/ati_ids.h index 35fe505735f..3e72a7dd4c0 100644 --- a/drivers/ati_ids.h +++ b/drivers/ati_ids.h @@ -209,4 +209,3 @@ #define PCI_CHIP_R423_5D57 0x5D57 #define PCI_CHIP_RS350_7834 0x7834 #define PCI_CHIP_RS350_7835 0x7835 - diff --git a/drivers/ati_radeon_fb.c b/drivers/ati_radeon_fb.c index e15140ab38d..c174f37b3fa 100644 --- a/drivers/ati_radeon_fb.c +++ b/drivers/ati_radeon_fb.c @@ -137,7 +137,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo) } } else { tmp = INREG(CONFIG_MEMSIZE); - } + } /* mem size is bits [28:0], mask off the rest */ rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; @@ -209,13 +209,13 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg #if 0 /* Workaround from XFree */ if (rinfo->is_mobility) { - /* A temporal workaround for the occational blanking on certain laptop + /* A temporal workaround for the occational blanking on certain laptop * panels. This appears to related to the PLL divider registers * (fail to lock?). It occurs even when all dividers are the same * with their old settings. In this case we really don't need to * fiddle with PLL registers. By doing this we can avoid the blanking * problem with some panels. - */ + */ if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { diff --git a/drivers/ati_radeon_fb.h b/drivers/ati_radeon_fb.h index 1c3ba64cfb0..b5c4b8b5779 100644 --- a/drivers/ati_radeon_fb.h +++ b/drivers/ati_radeon_fb.h @@ -5,7 +5,6 @@ * Most of the definitions here are adapted right from XFree86 * ***************************************************************/ - /* * Chip families. Must fit in the low 16 bits of a long word */ @@ -38,14 +37,12 @@ enum radeon_family { ((rinfo)->family == CHIP_FAMILY_RV280) || \ ((rinfo)->family == CHIP_FAMILY_RS300)) - #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ ((rinfo)->family == CHIP_FAMILY_RV350) || \ ((rinfo)->family == CHIP_FAMILY_R350) || \ ((rinfo)->family == CHIP_FAMILY_RV380) || \ ((rinfo)->family == CHIP_FAMILY_R420)) - struct radeonfb_info { char name[20]; @@ -86,7 +83,6 @@ static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) - /* * 2D Engine helper routines */ @@ -106,7 +102,6 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo) printf("radeonfb: Flush Timeout !\n"); } - static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) { int i; @@ -119,7 +114,6 @@ static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) printf("radeonfb: FIFO Timeout !\n"); } - static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) { int i; @@ -137,7 +131,6 @@ static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) printf("radeonfb: Idle Timeout !\n"); } - #define radeon_engine_idle() _radeon_engine_idle(rinfo) #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) #define radeon_msleep(ms) _radeon_msleep(rinfo,ms) @@ -255,9 +248,9 @@ static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) u32 data; OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); - //radeon_pll_errata_after_index(rinfo); + /* radeon_pll_errata_after_index(rinfo); */ data = INREG(CLOCK_CNTL_DATA); - //radeon_pll_errata_after_data(rinfo); + /* radeon_pll_errata_after_data(rinfo); */ return data; } @@ -266,12 +259,11 @@ static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, { OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); - //radeon_pll_errata_after_index(rinfo); + /* radeon_pll_errata_after_index(rinfo); */ OUTREG(CLOCK_CNTL_DATA, val); - //radeon_pll_errata_after_data(rinfo); + /* radeon_pll_errata_after_data(rinfo); */ } - static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, u32 val, u32 mask) { @@ -283,11 +275,8 @@ static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, __OUTPLL(rinfo, index, tmp); } - #define INPLL(addr) __INPLL(rinfo, addr) #define OUTPLL(index, val) __OUTPLL(rinfo, index, val) #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) - - #endif diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index 084339c1b29..5779f99f1f6 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -1,6 +1,6 @@ /**************************************************************************** * -* Video BOOT Graphics Card POST Module +* Video BOOT Graphics Card POST Module * * ======================================================================== * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. @@ -30,20 +30,20 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Linux Kernel -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Linux Kernel +* Developer: Kendall Bennett * -* Description: Module to implement booting PCI/AGP controllers on the -* bus. We use the x86 real mode emulator to run the BIOS on -* graphics controllers to bring the cards up. +* Description: Module to implement booting PCI/AGP controllers on the +* bus. We use the x86 real mode emulator to run the BIOS on +* graphics controllers to bring the cards up. * -* Note that at present this module does *not* support -* multiple controllers. +* Note that at present this module does *not* support +* multiple controllers. * -* The orignal name of this file is warmboot.c. -* Jason ported this file to u-boot to run the ATI video card -* BIOS in u-boot. +* The orignal name of this file is warmboot.c. +* Jason ported this file to u-boot to run the ATI video card +* BIOS in u-boot. ****************************************************************************/ #include @@ -53,11 +53,11 @@ #include /* Length of the BIOS image */ -#define MAX_BIOSLEN (128 * 1024L) +#define MAX_BIOSLEN (128 * 1024L) /* Define some useful types and macros */ -#define true 1 -#define false 0 +#define true 1 +#define false 0 /* Place to save PCI BAR's that we change and later restore */ static u32 saveROMBaseAddress; @@ -68,7 +68,7 @@ static u32 saveBaseAddress20; /**************************************************************************** PARAMETERS: -pcidev - PCI device info for the video card on the bus to boot +pcidev - PCI device info for the video card on the bus to boot VGAInfo - BIOS emulator VGA info structure REMARKS: @@ -102,8 +102,8 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) /**************************************************************************** PARAMETERS: -pcidev - PCI device info for the video card on the bus -bar - Place to return the base address register offset to use +pcidev - PCI device info for the video card on the bus +bar - Place to return the base address register offset to use RETURNS: The address to use to map the secondary BIOS (AGP devices) @@ -166,7 +166,7 @@ static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base) /**************************************************************************** PARAMETERS: -pcidev - PCI device info for the video card on the bus +pcidev - PCI device info for the video card on the bus RETURNS: Pointers to the mapped BIOS image @@ -196,7 +196,7 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev) /* Some cards have problems that stop us from being able to read the BIOS image from the ROM BAR. To fix this we have to do some chipset specific programming for different cards to solve this problem. - */ + */ if ((BIOSImagePhys = PCI_findBIOSAddr(pcidev, &BIOSImageBAR)) == 0) { printf("Find bios addr error\n"); @@ -223,7 +223,7 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev) /**************************************************************************** PARAMETERS: -pcidev - PCI device info for the video card on the bus +pcidev - PCI device info for the video card on the bus REMARKS: Unmaps the BIOS image for the device and restores framebuffer mappings @@ -239,7 +239,7 @@ void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage) /**************************************************************************** PARAMETERS: -pcidev - PCI device info for the video card on the bus to boot +pcidev - PCI device info for the video card on the bus to boot VGAInfo - BIOS emulator VGA info structure RETURNS: @@ -294,9 +294,9 @@ static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) /**************************************************************************** PARAMETERS: -pcidev - PCI device info for the video card on the bus to boot +pcidev - PCI device info for the video card on the bus to boot pVGAInfo - Place to return VGA info structure is requested -cleanUp - True to clean up on exit, false to leave emulator active +cleanUp - True to clean up on exit, false to leave emulator active REMARKS: Boots the PCI/AGP video card on the bus using the Video ROM BIOS image diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c index 894012fa898..2a8e1a01c1f 100644 --- a/drivers/bios_emulator/besys.c +++ b/drivers/bios_emulator/besys.c @@ -251,71 +251,69 @@ hardware does not support mapping the VGA I/O and memory (such as some PowerPC systems), we emulate the VGA so that the BIOS will still be able to set NonVGA display modes such as on ATI hardware. ****************************************************************************/ -static u8 VGA_inpb( - const int port) +static u8 VGA_inpb (const int port) { - u8 val = 0xff; - - switch (port) { - case 0x3C0: - /* 3C0 has funky characteristics because it can act as either - a data register or index register depending on the state - of an internal flip flop in the hardware. Hence we have - to emulate that functionality in here. */ - if (_BE_env.flipFlop3C0 == 0) { - /* Access 3C0 as index register*/ - val = _BE_env.emu3C0; - } - else { - /* Access 3C0 as data register*/ - if (_BE_env.emu3C0 < ATT_C) - val = _BE_env.emu3C1[_BE_env.emu3C0]; - } - _BE_env.flipFlop3C0 ^= 1; - break; - case 0x3C1: - if (_BE_env.emu3C0 < ATT_C) - return _BE_env.emu3C1[_BE_env.emu3C0]; - break; - case 0x3CC: - return _BE_env.emu3C2; - case 0x3C4: - return _BE_env.emu3C4; - case 0x3C5: - if (_BE_env.emu3C4 < ATT_C) - return _BE_env.emu3C5[_BE_env.emu3C4]; - break; - case 0x3C6: - return _BE_env.emu3C6; - case 0x3C7: - return _BE_env.emu3C7; - case 0x3C8: - return _BE_env.emu3C8; - case 0x3C9: - if (_BE_env.emu3C7 < PAL_C) - return _BE_env.emu3C9[_BE_env.emu3C7++]; - break; - case 0x3CE: - return _BE_env.emu3CE; - case 0x3CF: - if (_BE_env.emu3CE < GRA_C) - return _BE_env.emu3CF[_BE_env.emu3CE]; - break; - case 0x3D4: - if (_BE_env.emu3C2 & 0x1) - return _BE_env.emu3D4; - break; - case 0x3D5: - if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C)) - return _BE_env.emu3D5[_BE_env.emu3D4]; - break; - case 0x3DA: - _BE_env.flipFlop3C0 = 0; - val = _BE_env.emu3DA; - _BE_env.emu3DA ^= 0x9; - break; - } - return val; + u8 val = 0xff; + + switch (port) { + case 0x3C0: + /* 3C0 has funky characteristics because it can act as either + a data register or index register depending on the state + of an internal flip flop in the hardware. Hence we have + to emulate that functionality in here. */ + if (_BE_env.flipFlop3C0 == 0) { + /* Access 3C0 as index register */ + val = _BE_env.emu3C0; + } else { + /* Access 3C0 as data register */ + if (_BE_env.emu3C0 < ATT_C) + val = _BE_env.emu3C1[_BE_env.emu3C0]; + } + _BE_env.flipFlop3C0 ^= 1; + break; + case 0x3C1: + if (_BE_env.emu3C0 < ATT_C) + return _BE_env.emu3C1[_BE_env.emu3C0]; + break; + case 0x3CC: + return _BE_env.emu3C2; + case 0x3C4: + return _BE_env.emu3C4; + case 0x3C5: + if (_BE_env.emu3C4 < ATT_C) + return _BE_env.emu3C5[_BE_env.emu3C4]; + break; + case 0x3C6: + return _BE_env.emu3C6; + case 0x3C7: + return _BE_env.emu3C7; + case 0x3C8: + return _BE_env.emu3C8; + case 0x3C9: + if (_BE_env.emu3C7 < PAL_C) + return _BE_env.emu3C9[_BE_env.emu3C7++]; + break; + case 0x3CE: + return _BE_env.emu3CE; + case 0x3CF: + if (_BE_env.emu3CE < GRA_C) + return _BE_env.emu3CF[_BE_env.emu3CE]; + break; + case 0x3D4: + if (_BE_env.emu3C2 & 0x1) + return _BE_env.emu3D4; + break; + case 0x3D5: + if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C)) + return _BE_env.emu3D5[_BE_env.emu3D4]; + break; + case 0x3DA: + _BE_env.flipFlop3C0 = 0; + val = _BE_env.emu3DA; + _BE_env.emu3DA ^= 0x9; + break; + } + return val; } /**************************************************************************** @@ -328,66 +326,65 @@ Performs an emulated write to one of the 8253 timer registers. For now we only emulate timer 0 which is the only timer that the BIOS code appears to use. ****************************************************************************/ -static void VGA_outpb( - int port, - u8 val) +static void VGA_outpb (int port, u8 val) { - switch (port) { - case 0x3C0: - /* 3C0 has funky characteristics because it can act as either - a data register or index register depending on the state - of an internal flip flop in the hardware. Hence we have - to emulate that functionality in here.*/ - if (_BE_env.flipFlop3C0 == 0) { - /* Access 3C0 as index register*/ - _BE_env.emu3C0 = val; - } - else { - /* Access 3C0 as data register*/ - if (_BE_env.emu3C0 < ATT_C) - _BE_env.emu3C1[_BE_env.emu3C0] = val; - } - _BE_env.flipFlop3C0 ^= 1; - break; - case 0x3C2: - _BE_env.emu3C2 = val; - break; - case 0x3C4: - _BE_env.emu3C4 = val; - break; - case 0x3C5: - if (_BE_env.emu3C4 < ATT_C) - _BE_env.emu3C5[_BE_env.emu3C4] = val; - break; - case 0x3C6: - _BE_env.emu3C6 = val; - break; - case 0x3C7: - _BE_env.emu3C7 = (int)val * 3; - break; - case 0x3C8: - _BE_env.emu3C8 = (int)val * 3; - break; - case 0x3C9: - if (_BE_env.emu3C8 < PAL_C) - _BE_env.emu3C9[_BE_env.emu3C8++] = val; - break; - case 0x3CE: - _BE_env.emu3CE = val; - break; - case 0x3CF: - if (_BE_env.emu3CE < GRA_C) - _BE_env.emu3CF[_BE_env.emu3CE] = val; - break; - case 0x3D4: - if (_BE_env.emu3C2 & 0x1) - _BE_env.emu3D4 = val; - break; - case 0x3D5: - if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C)) - _BE_env.emu3D5[_BE_env.emu3D4] = val; - break; - } + switch (port) { + case 0x3C0: + /* 3C0 has funky characteristics because it can act as either + a data register or index register depending on the state + of an internal flip flop in the hardware. Hence we have + to emulate that functionality in here. */ + if (_BE_env.flipFlop3C0 == 0) { + /* Access 3C0 as index register */ + _BE_env.emu3C0 = val; + } else { + /* Access 3C0 as data register */ + if (_BE_env.emu3C0 < ATT_C) + _BE_env.emu3C1[_BE_env.emu3C0] = val; + } + _BE_env.flipFlop3C0 ^= 1; + break; + case 0x3C2: + _BE_env.emu3C2 = val; + break; + case 0x3C4: + _BE_env.emu3C4 = val; + break; + case 0x3C5: + if (_BE_env.emu3C4 < ATT_C) + _BE_env.emu3C5[_BE_env.emu3C4] = val; + break; + case 0x3C6: + _BE_env.emu3C6 = val; + break; + case 0x3C7: + _BE_env.emu3C7 = (int) val *3; + + break; + case 0x3C8: + _BE_env.emu3C8 = (int) val *3; + + break; + case 0x3C9: + if (_BE_env.emu3C8 < PAL_C) + _BE_env.emu3C9[_BE_env.emu3C8++] = val; + break; + case 0x3CE: + _BE_env.emu3CE = val; + break; + case 0x3CF: + if (_BE_env.emu3CE < GRA_C) + _BE_env.emu3CF[_BE_env.emu3CE] = val; + break; + case 0x3D4: + if (_BE_env.emu3C2 & 0x1) + _BE_env.emu3D4 = val; + break; + case 0x3D5: + if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C)) + _BE_env.emu3D5[_BE_env.emu3D4] = val; + break; + } } /**************************************************************************** diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c index aca594ce711..06d4ad380f3 100644 --- a/drivers/bios_emulator/biosemu.c +++ b/drivers/bios_emulator/biosemu.c @@ -1,12 +1,12 @@ /**************************************************************************** * -* BIOS emulator and interface -* to Realmode X86 Emulator Library +* BIOS emulator and interface +* to Realmode X86 Emulator Library * * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. * Jason Jin * -* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) 1996-1999 SciTech Software, Inc. * * ======================================================================== * @@ -16,7 +16,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -30,18 +30,18 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: Module implementing the system specific functions. This -* module is always compiled and linked in the OS depedent -* libraries, and never in a binary portable driver. +* Description: Module implementing the system specific functions. This +* module is always compiled and linked in the OS depedent +* libraries, and never in a binary portable driver. * -* Jason ported this file to u-boot to run the ATI video card BIOS -* in u-boot. Made all the video memory be emulated during the -* BIOS runing process which may affect the VGA function but the -* frambuffer function can work after run the BIOS. +* Jason ported this file to u-boot to run the ATI video card BIOS +* in u-boot. Made all the video memory be emulated during the +* BIOS runing process which may affect the VGA function but the +* frambuffer function can work after run the BIOS. * ****************************************************************************/ @@ -67,14 +67,14 @@ static X86EMU_pioFuncs _BE_pio __attribute__((section(".got2"))) = { BE_outl, }; -#define OFF(addr) (u16)(((addr) >> 0) & 0xffff) -#define SEG(addr) (u16)(((addr) >> 4) & 0xf000) +#define OFF(addr) (u16)(((addr) >> 0) & 0xffff) +#define SEG(addr) (u16)(((addr) >> 4) & 0xf000) /**************************************************************************** PARAMETERS: debugFlags - Flags to enable debugging options (debug builds only) -memSize - Amount of memory to allocate for real mode machine -info - Pointer to default VGA device information +memSize - Amount of memory to allocate for real mode machine +info - Pointer to default VGA device information REMARKS: This functions initialises the BElib, and uses the passed in @@ -116,7 +116,7 @@ int X86API BE_init(u32 debugFlags, int memSize, BE_VGAInfo * info, int shared) /**************************************************************************** PARAMETERS: -info - Pointer to VGA device information to make current +info - Pointer to VGA device information to make current REMARKS: This function sets the VGA BIOS functions in the emulator to point to the @@ -150,7 +150,7 @@ void X86API BE_setVGA(BE_VGAInfo * info) /**************************************************************************** PARAMETERS: -info - Pointer to VGA device information to retrieve current +info - Pointer to VGA device information to retrieve current REMARKS: This function returns the VGA BIOS functions currently active in the @@ -172,16 +172,16 @@ void X86API BE_getVGA(BE_VGAInfo * info) /**************************************************************************** PARAMETERS: -r_seg - Segment for pointer to convert -r_off - Offset for pointer to convert +r_seg - Segment for pointer to convert +r_off - Offset for pointer to convert REMARKS: This function maps a real mode pointer in the emulator memory to a protected mode pointer that can be used to directly access the memory. -NOTE: The memory is *always* in little endian format, son on non-x86 - systems you will need to do endian translations to access this - memory. +NOTE: The memory is *always* in little endian format, son on non-x86 + systems you will need to do endian translations to access this + memory. ****************************************************************************/ void *X86API BE_mapRealPointer(uint r_seg, uint r_off) { @@ -197,9 +197,9 @@ void *X86API BE_mapRealPointer(uint r_seg, uint r_off) /**************************************************************************** PARAMETERS: -len - Return the length of the VESA buffer -rseg - Place to store VESA buffer segment -roff - Place to store VESA buffer offset +len - Return the length of the VESA buffer +rseg - Place to store VESA buffer segment +roff - Place to store VESA buffer offset REMARKS: This function returns the address of the VESA transfer buffer in real @@ -207,9 +207,9 @@ _BE_piomode emulator memory. The VESA transfer buffer is always 1024 bytes long, and located at 15Kb into the start of the real mode memory (16Kb is where we put the real mode code we execute for issuing interrupts). -NOTE: The memory is *always* in little endian format, son on non-x86 - systems you will need to do endian translations to access this - memory. +NOTE: The memory is *always* in little endian format, son on non-x86 + systems you will need to do endian translations to access this + memory. ****************************************************************************/ void *X86API BE_getVESABuf(uint * len, uint * rseg, uint * roff) { @@ -231,10 +231,10 @@ void X86API BE_exit(void) /**************************************************************************** PARAMETERS: -seg - Segment of code to call -off - Offset of code to call -regs - Real mode registers to load -sregs - Real mode segment registers to load +seg - Segment of code to call +off - Offset of code to call +regs - Real mode registers to load +sregs - Real mode segment registers to load REMARKS: This functions calls a real mode far function at the specified address, @@ -284,9 +284,9 @@ void X86API BE_callRealMode(uint seg, uint off, RMREGS * regs, RMSREGS * sregs) /**************************************************************************** PARAMETERS: -intno - Interrupt number to execute -in - Real mode registers to load -out - Place to store resulting real mode registers +intno - Interrupt number to execute +in - Real mode registers to load +out - Place to store resulting real mode registers REMARKS: This functions calls a real mode interrupt function at the specified address, @@ -323,10 +323,10 @@ int X86API BE_int86(int intno, RMREGS * in, RMREGS * out) /**************************************************************************** PARAMETERS: -intno - Interrupt number to execute -in - Real mode registers to load -out - Place to store resulting real mode registers -sregs - Real mode segment registers to load +intno - Interrupt number to execute +in - Real mode registers to load +out - Place to store resulting real mode registers +sregs - Real mode segment registers to load REMARKS: This functions calls a real mode interrupt function at the specified address, diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h index 3265ac15cb6..e85e656cb45 100644 --- a/drivers/bios_emulator/biosemui.h +++ b/drivers/bios_emulator/biosemui.h @@ -1,12 +1,12 @@ /**************************************************************************** * -* BIOS emulator and interface -* to Realmode X86 Emulator Library +* BIOS emulator and interface +* to Realmode X86 Emulator Library * * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. * Jason Jin * -* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) 1996-1999 SciTech Software, Inc. * * ======================================================================== * @@ -16,7 +16,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -30,14 +30,14 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: Internal header file for the BIOS emulator library. +* Description: Internal header file for the BIOS emulator library. * -* Jason ported this file to u-boot, Added some architecture -* related Macro. +* Jason ported this file to u-boot, Added some architecture +* related Macro. * ****************************************************************************/ @@ -49,14 +49,14 @@ /*---------------------- Macros and type definitions ----------------------*/ #ifdef DEBUG -#define DB(x) x +#define DB(x) x #else -#define DB(x) do{}while(0); +#define DB(x) do{}while(0); #endif -#define BIOS_SEG 0xfff0 +#define BIOS_SEG 0xfff0 extern X86EMU_sysEnv _X86EMU_env; -#define M _X86EMU_env +#define M _X86EMU_env /* Macros to read and write values to x86 emulator memory. Memory is always * considered to be little endian, so we use macros to do endian swapping @@ -64,21 +64,21 @@ extern X86EMU_sysEnv _X86EMU_env; */ #ifdef __BIG_ENDIAN__ -#define readb_le(base) *((u8*)(base)) -#define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8)) -#define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \ - ((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base) + 3) << 24)) +#define readb_le(base) *((u8*)(base)) +#define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8)) +#define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \ + ((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base) + 3) << 24)) #define writeb_le(base, v) *((u8*)(base)) = (v) -#define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ - writeb_le(base + 1, (v >> 8) & 0xff) -#define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ - writeb_le(base + 1, (v >> 8) & 0xff), \ - writeb_le(base + 2, (v >> 16) & 0xff), \ - writeb_le(base + 3, (v >> 24) & 0xff) +#define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ + writeb_le(base + 1, (v >> 8) & 0xff) +#define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ + writeb_le(base + 1, (v >> 8) & 0xff), \ + writeb_le(base + 2, (v >> 16) & 0xff), \ + writeb_le(base + 3, (v >> 24) & 0xff) #else -#define readb_le(base) *((u8*)(base)) -#define readw_le(base) *((u16*)(base)) -#define readl_le(base) *((u32*)(base)) +#define readb_le(base) *((u8*)(base)) +#define readw_le(base) *((u16*)(base)) +#define readl_le(base) *((u32*)(base)) #define writeb_le(base, v) *((u8*)(base)) = (v) #define writew_le(base, v) *((u16*)(base)) = (v) #define writel_le(base, v) *((u32*)(base)) = (v) @@ -118,8 +118,8 @@ HEADER: biosemu.h MEMBERS: -type - Type of port access (1 = byte, 2 = word, 3 = dword) -defVal - Default power on value +type - Type of port access (1 = byte, 2 = word, 3 = dword) +defVal - Default power on value finalVal - Final value ****************************************************************************/ typedef struct { diff --git a/drivers/bios_emulator/include/x86emu/debug.h b/drivers/bios_emulator/include/x86emu/debug.h index 35e1e9a92fb..268c9d391e2 100644 --- a/drivers/bios_emulator/include/x86emu/debug.h +++ b/drivers/bios_emulator/include/x86emu/debug.h @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -14,7 +14,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -28,11 +28,11 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: Header file for debug definitions. +* Description: Header file for debug definitions. * ****************************************************************************/ @@ -43,16 +43,16 @@ /* checks to be enabled for "runtime" */ -#define CHECK_IP_FETCH_F 0x1 -#define CHECK_SP_ACCESS_F 0x2 -#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ -#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset */ +#define CHECK_IP_FETCH_F 0x1 +#define CHECK_SP_ACCESS_F 0x2 +#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ +#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset */ #ifdef DEBUG -# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) -# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) -# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) -# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) +# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) +# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) +# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) +# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) #else # define CHECK_IP_FETCH() # define CHECK_SP_ACCESS() @@ -61,50 +61,50 @@ #endif #ifdef DEBUG -# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) -# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) -# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) -# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) -# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) -# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) -# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) -# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_CS_IP) - -# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) -# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) -# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) -# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) -# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) -# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) -# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) -# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) +# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) +# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) +# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) +# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) +# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) +# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) +# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) +# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_CS_IP) + +# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) +# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) +# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) +# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) +# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) +# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) +# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) +# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) # define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) #else -# define DEBUG_INSTRUMENT() 0 -# define DEBUG_DECODE() 0 -# define DEBUG_TRACE() 0 -# define DEBUG_STEP() 0 -# define DEBUG_DISASSEMBLE() 0 -# define DEBUG_BREAK() 0 -# define DEBUG_SVC() 0 -# define DEBUG_SAVE_IP_CS() 0 -# define DEBUG_FS() 0 -# define DEBUG_PROC() 0 -# define DEBUG_SYSINT() 0 -# define DEBUG_TRACECALL() 0 -# define DEBUG_TRACECALLREGS() 0 -# define DEBUG_SYS() 0 -# define DEBUG_MEM_TRACE() 0 -# define DEBUG_IO_TRACE() 0 +# define DEBUG_INSTRUMENT() 0 +# define DEBUG_DECODE() 0 +# define DEBUG_TRACE() 0 +# define DEBUG_STEP() 0 +# define DEBUG_DISASSEMBLE() 0 +# define DEBUG_BREAK() 0 +# define DEBUG_SVC() 0 +# define DEBUG_SAVE_IP_CS() 0 +# define DEBUG_FS() 0 +# define DEBUG_PROC() 0 +# define DEBUG_SYSINT() 0 +# define DEBUG_TRACECALL() 0 +# define DEBUG_TRACECALLREGS() 0 +# define DEBUG_SYS() 0 +# define DEBUG_MEM_TRACE() 0 +# define DEBUG_IO_TRACE() 0 # define DEBUG_DECODE_NOPRINT() 0 #endif #ifdef DEBUG -# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ - x86emu_decode_printf(x) -# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ - x86emu_decode_printf2(x,y) +# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ + x86emu_decode_printf(x) +# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ + x86emu_decode_printf2(x,y) /* * The following allow us to look at the bytes of an instruction. The @@ -112,15 +112,15 @@ * the decoding process. The SAVE_IP_CS is called initially when the * major opcode of the instruction is accessed. */ -#define INC_DECODED_INST_LEN(x) \ - if (DEBUG_DECODE()) \ - x86emu_inc_decoded_inst_len(x) +#define INC_DECODED_INST_LEN(x) \ + if (DEBUG_DECODE()) \ + x86emu_inc_decoded_inst_len(x) -#define SAVE_IP_CS(x,y) \ +#define SAVE_IP_CS(x,y) \ if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ - | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ - M.x86.saved_cs = x; \ - M.x86.saved_ip = y; \ + | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ + M.x86.saved_cs = x; \ + M.x86.saved_ip = y; \ } #else # define INC_DECODED_INST_LEN(x) @@ -130,29 +130,29 @@ #endif #ifdef DEBUG -#define TRACE_REGS() \ - if (DEBUG_DISASSEMBLE()) { \ - x86emu_just_disassemble(); \ - goto EndOfTheInstructionProcedure; \ - } \ +#define TRACE_REGS() \ + if (DEBUG_DISASSEMBLE()) { \ + x86emu_just_disassemble(); \ + goto EndOfTheInstructionProcedure; \ + } \ if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() #else # define TRACE_REGS() #endif #ifdef DEBUG -# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() +# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() #else # define SINGLE_STEP() #endif #define TRACE_AND_STEP() \ - TRACE_REGS(); \ + TRACE_REGS(); \ SINGLE_STEP() #ifdef DEBUG # define START_OF_INSTR() -# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); +# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); # define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); #else # define START_OF_INSTR() @@ -161,30 +161,30 @@ #endif #ifdef DEBUG -# define CALL_TRACE(u,v,w,x,s) \ - if (DEBUG_TRACECALLREGS()) \ - x86emu_dump_regs(); \ - if (DEBUG_TRACECALL()) \ - printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); -# define RETURN_TRACE(n,u,v) \ - if (DEBUG_TRACECALLREGS()) \ - x86emu_dump_regs(); \ - if (DEBUG_TRACECALL()) \ - printk("%04x:%04x: %s\n",u,v,n); +# define CALL_TRACE(u,v,w,x,s) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); +# define RETURN_TRACE(n,u,v) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: %s\n",u,v,n); #else # define CALL_TRACE(u,v,w,x,s) # define RETURN_TRACE(n,u,v) #endif #ifdef DEBUG -#define DB(x) x +#define DB(x) x #else #define DB(x) #endif /*-------------------------- Function Prototypes --------------------------*/ -#ifdef __cplusplus +#ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif @@ -203,7 +203,7 @@ extern "C" { /* Use "C" linkage when in C++ mode */ extern void x86emu_check_mem_access(u32 p); extern void x86emu_check_data_access(uint s, uint o); -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_DEBUG_H */ diff --git a/drivers/bios_emulator/include/x86emu/prim_ops.h b/drivers/bios_emulator/include/x86emu/prim_ops.h index 0ea825d3c1a..2291e8488a5 100644 --- a/drivers/bios_emulator/include/x86emu/prim_ops.h +++ b/drivers/bios_emulator/include/x86emu/prim_ops.h @@ -139,4 +139,3 @@ u32 pop_long (void); #endif #endif /* __X86EMU_PRIM_OPS_H */ - diff --git a/drivers/bios_emulator/include/x86emu/regs.h b/drivers/bios_emulator/include/x86emu/regs.h index 9dbed503175..a7fedd2f6ca 100644 --- a/drivers/bios_emulator/include/x86emu/regs.h +++ b/drivers/bios_emulator/include/x86emu/regs.h @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -14,7 +14,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -28,11 +28,11 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: Header file for x86 register definitions. +* Description: Header file for x86 register definitions. * ****************************************************************************/ @@ -54,11 +54,11 @@ * EAX & 0xff === AL * EAX & 0xffff == AX * - * etc. The result is that alot of the calculations can then be + * etc. The result is that alot of the calculations can then be * done using the native instruction set fully. */ -#ifdef __BIG_ENDIAN__ +#ifdef __BIG_ENDIAN__ typedef struct { u32 e_reg; @@ -178,7 +178,7 @@ struct i386_segment_regs { /* flag conditions */ #define FB_CF 0x0001 /* CARRY flag */ #define FB_PF 0x0004 /* PARITY flag */ -#define FB_AF 0x0010 /* AUX flag */ +#define FB_AF 0x0010 /* AUX flag */ #define FB_ZF 0x0040 /* ZERO flag */ #define FB_SF 0x0080 /* SIGN flag */ #define FB_TF 0x0100 /* TRAP flag */ @@ -199,7 +199,7 @@ struct i386_segment_regs { #define F_CF 0x0001 /* CARRY flag */ #define F_PF 0x0004 /* PARITY flag */ -#define F_AF 0x0010 /* AUX flag */ +#define F_AF 0x0010 /* AUX flag */ #define F_ZF 0x0040 /* ZERO flag */ #define F_SF 0x0080 /* SIGN flag */ #define F_TF 0x0100 /* TRAP flag */ @@ -207,60 +207,60 @@ struct i386_segment_regs { #define F_DF 0x0400 /* DIR flag */ #define F_OF 0x0800 /* OVERFLOW flag */ -#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) -#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) -#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) -#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) -#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) +#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) +#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) +#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) +#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) +#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) #define CONDITIONAL_SET_FLAG(COND,FLAG) \ if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) -#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ -#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ -#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ -#define F_ALL_CALC 0xff0000 /* All have been calced */ +#define F_ALL_CALC 0xff0000 /* All have been calced */ /* * Emulator machine state. * Segment usage control. */ -#define SYSMODE_SEG_DS_SS 0x00000001 -#define SYSMODE_SEGOVR_CS 0x00000002 -#define SYSMODE_SEGOVR_DS 0x00000004 -#define SYSMODE_SEGOVR_ES 0x00000008 -#define SYSMODE_SEGOVR_FS 0x00000010 -#define SYSMODE_SEGOVR_GS 0x00000020 -#define SYSMODE_SEGOVR_SS 0x00000040 -#define SYSMODE_PREFIX_REPE 0x00000080 -#define SYSMODE_PREFIX_REPNE 0x00000100 -#define SYSMODE_PREFIX_DATA 0x00000200 -#define SYSMODE_PREFIX_ADDR 0x00000400 -#define SYSMODE_INTR_PENDING 0x10000000 -#define SYSMODE_EXTRN_INTR 0x20000000 -#define SYSMODE_HALTED 0x40000000 - -#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ - SYSMODE_SEGOVR_CS | \ - SYSMODE_SEGOVR_DS | \ - SYSMODE_SEGOVR_ES | \ - SYSMODE_SEGOVR_FS | \ - SYSMODE_SEGOVR_GS | \ - SYSMODE_SEGOVR_SS) -#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ - SYSMODE_SEGOVR_CS | \ - SYSMODE_SEGOVR_DS | \ - SYSMODE_SEGOVR_ES | \ - SYSMODE_SEGOVR_FS | \ - SYSMODE_SEGOVR_GS | \ - SYSMODE_SEGOVR_SS | \ - SYSMODE_PREFIX_DATA | \ - SYSMODE_PREFIX_ADDR) - -#define INTR_SYNCH 0x1 -#define INTR_ASYNCH 0x2 -#define INTR_HALTED 0x4 +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000 + +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS) +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS | \ + SYSMODE_PREFIX_DATA | \ + SYSMODE_PREFIX_ADDR) + +#define INTR_SYNCH 0x1 +#define INTR_ASYNCH 0x2 +#define INTR_HALTED 0x4 typedef struct { struct i386_general_regs gen; @@ -268,15 +268,15 @@ typedef struct { struct i386_segment_regs seg; /* * MODE contains information on: - * REPE prefix 2 bits repe,repne - * SEGMENT overrides 5 bits normal,DS,SS,CS,ES - * Delayed flag set 3 bits (zero, signed, parity) - * reserved 6 bits - * interrupt # 8 bits instruction raised interrupt - * BIOS video segregs 4 bits - * Interrupt Pending 1 bits - * Extern interrupt 1 bits - * Halted 1 bits + * REPE prefix 2 bits repe,repne + * SEGMENT overrides 5 bits normal,DS,SS,CS,ES + * Delayed flag set 3 bits (zero, signed, parity) + * reserved 6 bits + * interrupt # 8 bits instruction raised interrupt + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits + * Extern interrupt 1 bits + * Halted 1 bits */ long mode; u8 intno; @@ -288,7 +288,7 @@ typedef struct { u16 saved_cs; int enc_pos; int enc_str_pos; - char decode_buf[32]; /* encoded byte stream */ + char decode_buf[32]; /* encoded byte stream */ char decoded_buf[256]; /* disassembled strings */ #endif } X86EMU_regs; @@ -298,9 +298,9 @@ REMARKS: Structure maintaining the emulator machine state. MEMBERS: -x86 - X86 registers -mem_base - Base real mode memory for the emulator -mem_size - Size of the real mode memory block for the emulator +x86 - X86 registers +mem_base - Base real mode memory for the emulator +mem_size - Size of the real mode memory block for the emulator ****************************************************************************/ #undef x86 typedef struct { @@ -314,7 +314,7 @@ typedef struct { /*----------------------------- Global Variables --------------------------*/ -#ifdef __cplusplus +#ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif @@ -324,7 +324,7 @@ extern "C" { /* Use "C" linkage when in C++ mode */ */ extern X86EMU_sysEnv _X86EMU_env; -#define M _X86EMU_env +#define M _X86EMU_env /*-------------------------- Function Prototypes --------------------------*/ @@ -334,7 +334,7 @@ extern "C" { /* Use "C" linkage when in C++ mode */ void printk(const char *fmt, ...); #endif -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_REGS_H */ diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c index b4dbb20797d..1e2dcfe4b2b 100644 --- a/drivers/bios_emulator/x86emu/decode.c +++ b/drivers/bios_emulator/x86emu/decode.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -14,7 +14,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -28,12 +28,12 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: This file includes subroutines which are related to -* instruction decoding and accessess of immediate data via IP. etc. +* Description: This file includes subroutines which are related to +* instruction decoding and accessess of immediate data via IP. etc. * ****************************************************************************/ @@ -47,22 +47,22 @@ Handles any pending asychronous interrupts. ****************************************************************************/ static void x86emu_intr_handle(void) { - u8 intno; + u8 intno; if (M.x86.intr & INTR_SYNCH) { - intno = M.x86.intno; - if (_X86EMU_intrTab[intno]) { - (*_X86EMU_intrTab[intno])(intno); - } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(intno * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(intno * 4); - M.x86.intr = 0; - } + intno = M.x86.intno; + if (_X86EMU_intrTab[intno]) { + (*_X86EMU_intrTab[intno])(intno); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intno * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intno * 4); + M.x86.intr = 0; + } } } @@ -95,34 +95,34 @@ void X86EMU_exec(void) DB(x86emu_end_instr();) for (;;) { -DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) - /* If debugging, save the IP and CS values. */ - SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); - INC_DECODED_INST_LEN(1); - if (M.x86.intr) { - if (M.x86.intr & INTR_HALTED) { -DB( if (M.x86.R_SP != 0) { - printk("halted\n"); - X86EMU_trace_regs(); - } - else { - if (M.x86.debug) - printk("Service completed successfully\n"); - }) - return; - } - if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || - !ACCESS_FLAG(F_IF)) { - x86emu_intr_handle(); - } - } - op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); - (*x86emu_optab[op1])(op1); - if (M.x86.debug & DEBUG_EXIT) { - M.x86.debug &= ~DEBUG_EXIT; - return; - } +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + /* If debugging, save the IP and CS values. */ + SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); + INC_DECODED_INST_LEN(1); + if (M.x86.intr) { + if (M.x86.intr & INTR_HALTED) { +DB( if (M.x86.R_SP != 0) { + printk("halted\n"); + X86EMU_trace_regs(); + } + else { + if (M.x86.debug) + printk("Service completed successfully\n"); + }) + return; + } + if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || + !ACCESS_FLAG(F_IF)) { + x86emu_intr_handle(); + } + } + op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + (*x86emu_optab[op1])(op1); + if (M.x86.debug & DEBUG_EXIT) { + M.x86.debug &= ~DEBUG_EXIT; + return; + } } } @@ -137,9 +137,9 @@ void X86EMU_halt_sys(void) /**************************************************************************** PARAMETERS: -mod - Mod value from decoded byte -regh - Reg h value from decoded byte -regl - Reg l value from decoded byte +mod - Mod value from decoded byte +regh - Reg h value from decoded byte +regl - Reg l value from decoded byte REMARKS: Raise the specified interrupt to be handled before the execution of the @@ -155,7 +155,7 @@ void fetch_decode_modrm( int fetched; DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); INC_DECODED_INST_LEN(1); *mod = (fetched >> 6) & 0x03; @@ -178,7 +178,7 @@ u8 fetch_byte_imm(void) u8 fetched; DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); INC_DECODED_INST_LEN(1); return fetched; @@ -199,7 +199,7 @@ u16 fetch_word_imm(void) u16 fetched; DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); M.x86.R_IP += 2; INC_DECODED_INST_LEN(2); @@ -221,7 +221,7 @@ u32 fetch_long_imm(void) u32 fetched; DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); M.x86.R_IP += 4; INC_DECODED_INST_LEN(4); @@ -261,39 +261,39 @@ _INLINE u32 get_data_segment(void) { #define GET_SEGMENT(segment) switch (M.x86.mode & SYSMODE_SEGMASK) { - case 0: /* default case: use ds register */ + case 0: /* default case: use ds register */ case SYSMODE_SEGOVR_DS: case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: - return M.x86.R_DS; - case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ - return M.x86.R_SS; + return M.x86.R_DS; + case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ + return M.x86.R_SS; case SYSMODE_SEGOVR_CS: case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: - return M.x86.R_CS; + return M.x86.R_CS; case SYSMODE_SEGOVR_ES: case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: - return M.x86.R_ES; + return M.x86.R_ES; case SYSMODE_SEGOVR_FS: case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: - return M.x86.R_FS; + return M.x86.R_FS; case SYSMODE_SEGOVR_GS: case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: - return M.x86.R_GS; + return M.x86.R_GS; case SYSMODE_SEGOVR_SS: case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: - return M.x86.R_SS; + return M.x86.R_SS; default: -#ifdef DEBUG - printk("error: should not happen: multiple overrides.\n"); +#ifdef DEBUG + printk("error: should not happen: multiple overrides.\n"); #endif - HALT_SYS(); - return 0; + HALT_SYS(); + return 0; } } /**************************************************************************** PARAMETERS: -offset - Offset to load data from +offset - Offset to load data from RETURNS: Byte value read from the absolute memory location. @@ -305,14 +305,14 @@ u8 fetch_data_byte( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdb)((get_data_segment() << 4) + offset); } /**************************************************************************** PARAMETERS: -offset - Offset to load data from +offset - Offset to load data from RETURNS: Word value read from the absolute memory location. @@ -324,14 +324,14 @@ u16 fetch_data_word( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdw)((get_data_segment() << 4) + offset); } /**************************************************************************** PARAMETERS: -offset - Offset to load data from +offset - Offset to load data from RETURNS: Long value read from the absolute memory location. @@ -343,7 +343,7 @@ u32 fetch_data_long( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdl)((get_data_segment() << 4) + offset); } @@ -351,7 +351,7 @@ u32 fetch_data_long( /**************************************************************************** PARAMETERS: segment - Segment to load data from -offset - Offset to load data from +offset - Offset to load data from RETURNS: Byte value read from the absolute memory location. @@ -364,7 +364,7 @@ u8 fetch_data_byte_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif return (*sys_rdb)(((u32)segment << 4) + offset); } @@ -372,7 +372,7 @@ u8 fetch_data_byte_abs( /**************************************************************************** PARAMETERS: segment - Segment to load data from -offset - Offset to load data from +offset - Offset to load data from RETURNS: Word value read from the absolute memory location. @@ -385,7 +385,7 @@ u16 fetch_data_word_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif return (*sys_rdw)(((u32)segment << 4) + offset); } @@ -393,7 +393,7 @@ u16 fetch_data_word_abs( /**************************************************************************** PARAMETERS: segment - Segment to load data from -offset - Offset to load data from +offset - Offset to load data from RETURNS: Long value read from the absolute memory location. @@ -406,15 +406,15 @@ u32 fetch_data_long_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif return (*sys_rdl)(((u32)segment << 4) + offset); } /**************************************************************************** PARAMETERS: -offset - Offset to store data at -val - Value to store +offset - Offset to store data at +val - Value to store REMARKS: Writes a word value to an segmented memory location. The segment used is @@ -428,15 +428,15 @@ void store_data_byte( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrb)((get_data_segment() << 4) + offset, val); } /**************************************************************************** PARAMETERS: -offset - Offset to store data at -val - Value to store +offset - Offset to store data at +val - Value to store REMARKS: Writes a word value to an segmented memory location. The segment used is @@ -450,15 +450,15 @@ void store_data_word( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrw)((get_data_segment() << 4) + offset, val); } /**************************************************************************** PARAMETERS: -offset - Offset to store data at -val - Value to store +offset - Offset to store data at +val - Value to store REMARKS: Writes a long value to an segmented memory location. The segment used is @@ -472,7 +472,7 @@ void store_data_long( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrl)((get_data_segment() << 4) + offset, val); } @@ -480,8 +480,8 @@ void store_data_long( /**************************************************************************** PARAMETERS: segment - Segment to store data at -offset - Offset to store data at -val - Value to store +offset - Offset to store data at +val - Value to store REMARKS: Writes a byte value to an absolute memory location. @@ -495,7 +495,7 @@ void store_data_byte_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif (*sys_wrb)(((u32)segment << 4) + offset, val); } @@ -503,8 +503,8 @@ void store_data_byte_abs( /**************************************************************************** PARAMETERS: segment - Segment to store data at -offset - Offset to store data at -val - Value to store +offset - Offset to store data at +val - Value to store REMARKS: Writes a word value to an absolute memory location. @@ -518,7 +518,7 @@ void store_data_word_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif (*sys_wrw)(((u32)segment << 4) + offset, val); } @@ -526,8 +526,8 @@ void store_data_word_abs( /**************************************************************************** PARAMETERS: segment - Segment to store data at -offset - Offset to store data at -val - Value to store +offset - Offset to store data at +val - Value to store REMARKS: Writes a long value to an absolute memory location. @@ -541,7 +541,7 @@ void store_data_long_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif (*sys_wrl)(((u32)segment << 4) + offset, val); } @@ -562,32 +562,32 @@ u8* decode_rm_byte_register( { switch (reg) { case 0: - DECODE_PRINTF("AL"); - return &M.x86.R_AL; + DECODE_PRINTF("AL"); + return &M.x86.R_AL; case 1: - DECODE_PRINTF("CL"); - return &M.x86.R_CL; + DECODE_PRINTF("CL"); + return &M.x86.R_CL; case 2: - DECODE_PRINTF("DL"); - return &M.x86.R_DL; + DECODE_PRINTF("DL"); + return &M.x86.R_DL; case 3: - DECODE_PRINTF("BL"); - return &M.x86.R_BL; + DECODE_PRINTF("BL"); + return &M.x86.R_BL; case 4: - DECODE_PRINTF("AH"); - return &M.x86.R_AH; + DECODE_PRINTF("AH"); + return &M.x86.R_AH; case 5: - DECODE_PRINTF("CH"); - return &M.x86.R_CH; + DECODE_PRINTF("CH"); + return &M.x86.R_CH; case 6: - DECODE_PRINTF("DH"); - return &M.x86.R_DH; + DECODE_PRINTF("DH"); + return &M.x86.R_DH; case 7: - DECODE_PRINTF("BH"); - return &M.x86.R_BH; + DECODE_PRINTF("BH"); + return &M.x86.R_BH; } HALT_SYS(); - return NULL; /* NOT REACHED OR REACHED ON ERROR */ + return NULL; /* NOT REACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -599,39 +599,39 @@ Pointer to the appropriate register REMARKS: Return a pointer to the register given by the R/RM field of the -modrm byte, for word operands. Also enables the decoding of instructions. +modrm byte, for word operands. Also enables the decoding of instructions. ****************************************************************************/ u16* decode_rm_word_register( int reg) { switch (reg) { case 0: - DECODE_PRINTF("AX"); - return &M.x86.R_AX; + DECODE_PRINTF("AX"); + return &M.x86.R_AX; case 1: - DECODE_PRINTF("CX"); - return &M.x86.R_CX; + DECODE_PRINTF("CX"); + return &M.x86.R_CX; case 2: - DECODE_PRINTF("DX"); - return &M.x86.R_DX; + DECODE_PRINTF("DX"); + return &M.x86.R_DX; case 3: - DECODE_PRINTF("BX"); - return &M.x86.R_BX; + DECODE_PRINTF("BX"); + return &M.x86.R_BX; case 4: - DECODE_PRINTF("SP"); - return &M.x86.R_SP; + DECODE_PRINTF("SP"); + return &M.x86.R_SP; case 5: - DECODE_PRINTF("BP"); - return &M.x86.R_BP; + DECODE_PRINTF("BP"); + return &M.x86.R_BP; case 6: - DECODE_PRINTF("SI"); - return &M.x86.R_SI; + DECODE_PRINTF("SI"); + return &M.x86.R_SI; case 7: - DECODE_PRINTF("DI"); - return &M.x86.R_DI; + DECODE_PRINTF("DI"); + return &M.x86.R_DI; } HALT_SYS(); - return NULL; /* NOTREACHED OR REACHED ON ERROR */ + return NULL; /* NOTREACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -643,39 +643,39 @@ Pointer to the appropriate register REMARKS: Return a pointer to the register given by the R/RM field of the -modrm byte, for dword operands. Also enables the decoding of instructions. +modrm byte, for dword operands. Also enables the decoding of instructions. ****************************************************************************/ u32* decode_rm_long_register( int reg) { switch (reg) { case 0: - DECODE_PRINTF("EAX"); - return &M.x86.R_EAX; + DECODE_PRINTF("EAX"); + return &M.x86.R_EAX; case 1: - DECODE_PRINTF("ECX"); - return &M.x86.R_ECX; + DECODE_PRINTF("ECX"); + return &M.x86.R_ECX; case 2: - DECODE_PRINTF("EDX"); - return &M.x86.R_EDX; + DECODE_PRINTF("EDX"); + return &M.x86.R_EDX; case 3: - DECODE_PRINTF("EBX"); - return &M.x86.R_EBX; + DECODE_PRINTF("EBX"); + return &M.x86.R_EBX; case 4: - DECODE_PRINTF("ESP"); - return &M.x86.R_ESP; + DECODE_PRINTF("ESP"); + return &M.x86.R_ESP; case 5: - DECODE_PRINTF("EBP"); - return &M.x86.R_EBP; + DECODE_PRINTF("EBP"); + return &M.x86.R_EBP; case 6: - DECODE_PRINTF("ESI"); - return &M.x86.R_ESI; + DECODE_PRINTF("ESI"); + return &M.x86.R_ESI; case 7: - DECODE_PRINTF("EDI"); - return &M.x86.R_EDI; + DECODE_PRINTF("EDI"); + return &M.x86.R_EDI; } HALT_SYS(); - return NULL; /* NOTREACHED OR REACHED ON ERROR */ + return NULL; /* NOTREACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -695,30 +695,30 @@ u16* decode_rm_seg_register( { switch (reg) { case 0: - DECODE_PRINTF("ES"); - return &M.x86.R_ES; + DECODE_PRINTF("ES"); + return &M.x86.R_ES; case 1: - DECODE_PRINTF("CS"); - return &M.x86.R_CS; + DECODE_PRINTF("CS"); + return &M.x86.R_CS; case 2: - DECODE_PRINTF("SS"); - return &M.x86.R_SS; + DECODE_PRINTF("SS"); + return &M.x86.R_SS; case 3: - DECODE_PRINTF("DS"); - return &M.x86.R_DS; + DECODE_PRINTF("DS"); + return &M.x86.R_DS; case 4: - DECODE_PRINTF("FS"); - return &M.x86.R_FS; + DECODE_PRINTF("FS"); + return &M.x86.R_FS; case 5: - DECODE_PRINTF("GS"); - return &M.x86.R_GS; + DECODE_PRINTF("GS"); + return &M.x86.R_GS; case 6: case 7: - DECODE_PRINTF("ILLEGAL SEGREG"); - break; + DECODE_PRINTF("ILLEGAL SEGREG"); + break; } HALT_SYS(); - return NULL; /* NOT REACHED OR REACHED ON ERROR */ + return NULL; /* NOT REACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -739,38 +739,38 @@ unsigned decode_sib_si( { scale = 1 << scale; if (scale > 1) { - DECODE_PRINTF2("[%d*", scale); + DECODE_PRINTF2("[%d*", scale); } else { - DECODE_PRINTF("["); + DECODE_PRINTF("["); } switch (index) { case 0: - DECODE_PRINTF("EAX]"); - return M.x86.R_EAX * index; + DECODE_PRINTF("EAX]"); + return M.x86.R_EAX * index; case 1: - DECODE_PRINTF("ECX]"); - return M.x86.R_ECX * index; + DECODE_PRINTF("ECX]"); + return M.x86.R_ECX * index; case 2: - DECODE_PRINTF("EDX]"); - return M.x86.R_EDX * index; + DECODE_PRINTF("EDX]"); + return M.x86.R_EDX * index; case 3: - DECODE_PRINTF("EBX]"); - return M.x86.R_EBX * index; + DECODE_PRINTF("EBX]"); + return M.x86.R_EBX * index; case 4: - DECODE_PRINTF("0]"); - return 0; + DECODE_PRINTF("0]"); + return 0; case 5: - DECODE_PRINTF("EBP]"); - return M.x86.R_EBP * index; + DECODE_PRINTF("EBP]"); + return M.x86.R_EBP * index; case 6: - DECODE_PRINTF("ESI]"); - return M.x86.R_ESI * index; + DECODE_PRINTF("ESI]"); + return M.x86.R_ESI * index; case 7: - DECODE_PRINTF("EDI]"); - return M.x86.R_EDI * index; + DECODE_PRINTF("EDI]"); + return M.x86.R_EDI * index; } HALT_SYS(); - return 0; /* NOT REACHED OR REACHED ON ERROR */ + return 0; /* NOT REACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -795,58 +795,58 @@ unsigned decode_sib_address( switch (base) { case 0: - DECODE_PRINTF("[EAX]"); - offset = M.x86.R_EAX; - break; + DECODE_PRINTF("[EAX]"); + offset = M.x86.R_EAX; + break; case 1: - DECODE_PRINTF("[ECX]"); - offset = M.x86.R_ECX; - break; + DECODE_PRINTF("[ECX]"); + offset = M.x86.R_ECX; + break; case 2: - DECODE_PRINTF("[EDX]"); - offset = M.x86.R_EDX; - break; + DECODE_PRINTF("[EDX]"); + offset = M.x86.R_EDX; + break; case 3: - DECODE_PRINTF("[EBX]"); - offset = M.x86.R_EBX; - break; + DECODE_PRINTF("[EBX]"); + offset = M.x86.R_EBX; + break; case 4: - DECODE_PRINTF("[ESP]"); - offset = M.x86.R_ESP; - break; + DECODE_PRINTF("[ESP]"); + offset = M.x86.R_ESP; + break; case 5: - switch (mod) { - case 0: - displacement = (s32)fetch_long_imm(); - DECODE_PRINTF2("[%d]", displacement); - offset = displacement; - break; - case 1: - displacement = (s8)fetch_byte_imm(); - DECODE_PRINTF2("[%d][EBP]", displacement); - offset = M.x86.R_EBP + displacement; - break; - case 2: - displacement = (s32)fetch_long_imm(); - DECODE_PRINTF2("[%d][EBP]", displacement); - offset = M.x86.R_EBP + displacement; - break; - default: - HALT_SYS(); - } - DECODE_PRINTF("[EAX]"); - offset = M.x86.R_EAX; - break; + switch (mod) { + case 0: + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d]", displacement); + offset = displacement; + break; + case 1: + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("[%d][EBP]", displacement); + offset = M.x86.R_EBP + displacement; + break; + case 2: + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d][EBP]", displacement); + offset = M.x86.R_EBP + displacement; + break; + default: + HALT_SYS(); + } + DECODE_PRINTF("[EAX]"); + offset = M.x86.R_EAX; + break; case 6: - DECODE_PRINTF("[ESI]"); - offset = M.x86.R_ESI; - break; + DECODE_PRINTF("[ESI]"); + offset = M.x86.R_ESI; + break; case 7: - DECODE_PRINTF("[EDI]"); - offset = M.x86.R_EDI; - break; + DECODE_PRINTF("[EDI]"); + offset = M.x86.R_EDI; + break; default: - HALT_SYS(); + HALT_SYS(); } offset += decode_sib_si(ss, index); return offset; @@ -864,14 +864,14 @@ REMARKS: Return the offset given by mod=00 addressing. Also enables the decoding of instructions. -NOTE: The code which specifies the corresponding segment (ds vs ss) - below in the case of [BP+..]. The assumption here is that at the - point that this subroutine is called, the bit corresponding to - SYSMODE_SEG_DS_SS will be zero. After every instruction - except the segment override instructions, this bit (as well - as any bits indicating segment overrides) will be clear. So - if a SS access is needed, set this bit. Otherwise, DS access - occurs (unless any of the segment override bits are set). +NOTE: The code which specifies the corresponding segment (ds vs ss) + below in the case of [BP+..]. The assumption here is that at the + point that this subroutine is called, the bit corresponding to + SYSMODE_SEG_DS_SS will be zero. After every instruction + except the segment override instructions, this bit (as well + as any bits indicating segment overrides) will be clear. So + if a SS access is needed, set this bit. Otherwise, DS access + occurs (unless any of the segment override bits are set). ****************************************************************************/ unsigned decode_rm00_address( int rm) @@ -879,64 +879,64 @@ unsigned decode_rm00_address( unsigned offset; if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - /* 32-bit addressing */ - switch (rm) { - case 0: - DECODE_PRINTF("[EAX]"); - return M.x86.R_EAX; - case 1: - DECODE_PRINTF("[ECX]"); - return M.x86.R_ECX; - case 2: - DECODE_PRINTF("[EDX]"); - return M.x86.R_EDX; - case 3: - DECODE_PRINTF("[EBX]"); - return M.x86.R_EBX; - case 4: - return decode_sib_address(0); - case 5: - offset = fetch_long_imm(); - DECODE_PRINTF2("[%08x]", offset); - return offset; - case 6: - DECODE_PRINTF("[ESI]"); - return M.x86.R_ESI; - case 7: - DECODE_PRINTF("[EDI]"); - return M.x86.R_EDI; - } + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[EAX]"); + return M.x86.R_EAX; + case 1: + DECODE_PRINTF("[ECX]"); + return M.x86.R_ECX; + case 2: + DECODE_PRINTF("[EDX]"); + return M.x86.R_EDX; + case 3: + DECODE_PRINTF("[EBX]"); + return M.x86.R_EBX; + case 4: + return decode_sib_address(0); + case 5: + offset = fetch_long_imm(); + DECODE_PRINTF2("[%08x]", offset); + return offset; + case 6: + DECODE_PRINTF("[ESI]"); + return M.x86.R_ESI; + case 7: + DECODE_PRINTF("[EDI]"); + return M.x86.R_EDI; + } } else { - /* 16-bit addressing */ - switch (rm) { - case 0: - DECODE_PRINTF("[BX+SI]"); - return (M.x86.R_BX + M.x86.R_SI) & 0xffff; - case 1: - DECODE_PRINTF("[BX+DI]"); - return (M.x86.R_BX + M.x86.R_DI) & 0xffff; - case 2: - DECODE_PRINTF("[BP+SI]"); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI) & 0xffff; - case 3: - DECODE_PRINTF("[BP+DI]"); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI) & 0xffff; - case 4: - DECODE_PRINTF("[SI]"); - return M.x86.R_SI; - case 5: - DECODE_PRINTF("[DI]"); - return M.x86.R_DI; - case 6: - offset = fetch_word_imm(); - DECODE_PRINTF2("[%04x]", offset); - return offset; - case 7: - DECODE_PRINTF("[BX]"); - return M.x86.R_BX; - } + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[BX+SI]"); + return (M.x86.R_BX + M.x86.R_SI) & 0xffff; + case 1: + DECODE_PRINTF("[BX+DI]"); + return (M.x86.R_BX + M.x86.R_DI) & 0xffff; + case 2: + DECODE_PRINTF("[BP+SI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI) & 0xffff; + case 3: + DECODE_PRINTF("[BP+DI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI) & 0xffff; + case 4: + DECODE_PRINTF("[SI]"); + return M.x86.R_SI; + case 5: + DECODE_PRINTF("[DI]"); + return M.x86.R_DI; + case 6: + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]", offset); + return offset; + case 7: + DECODE_PRINTF("[BX]"); + return M.x86.R_BX; + } } HALT_SYS(); return 0; @@ -959,76 +959,76 @@ unsigned decode_rm01_address( int displacement; if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - /* 32-bit addressing */ - if (rm != 4) - displacement = (s8)fetch_byte_imm(); - else - displacement = 0; - - switch (rm) { - case 0: - DECODE_PRINTF2("%d[EAX]", displacement); - return M.x86.R_EAX + displacement; - case 1: - DECODE_PRINTF2("%d[ECX]", displacement); - return M.x86.R_ECX + displacement; - case 2: - DECODE_PRINTF2("%d[EDX]", displacement); - return M.x86.R_EDX + displacement; - case 3: - DECODE_PRINTF2("%d[EBX]", displacement); - return M.x86.R_EBX + displacement; - case 4: { - int offset = decode_sib_address(1); - displacement = (s8)fetch_byte_imm(); - DECODE_PRINTF2("[%d]", displacement); - return offset + displacement; - } - case 5: - DECODE_PRINTF2("%d[EBP]", displacement); - return M.x86.R_EBP + displacement; - case 6: - DECODE_PRINTF2("%d[ESI]", displacement); - return M.x86.R_ESI + displacement; - case 7: - DECODE_PRINTF2("%d[EDI]", displacement); - return M.x86.R_EDI + displacement; - } + /* 32-bit addressing */ + if (rm != 4) + displacement = (s8)fetch_byte_imm(); + else + displacement = 0; + + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: { + int offset = decode_sib_address(1); + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("[%d]", displacement); + return offset + displacement; + } + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } } else { - /* 16-bit addressing */ - displacement = (s8)fetch_byte_imm(); - switch (rm) { - case 0: - DECODE_PRINTF2("%d[BX+SI]", displacement); - return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; - case 1: - DECODE_PRINTF2("%d[BX+DI]", displacement); - return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; - case 2: - DECODE_PRINTF2("%d[BP+SI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; - case 3: - DECODE_PRINTF2("%d[BP+DI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; - case 4: - DECODE_PRINTF2("%d[SI]", displacement); - return (M.x86.R_SI + displacement) & 0xffff; - case 5: - DECODE_PRINTF2("%d[DI]", displacement); - return (M.x86.R_DI + displacement) & 0xffff; - case 6: - DECODE_PRINTF2("%d[BP]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + displacement) & 0xffff; - case 7: - DECODE_PRINTF2("%d[BX]", displacement); - return (M.x86.R_BX + displacement) & 0xffff; - } + /* 16-bit addressing */ + displacement = (s8)fetch_byte_imm(); + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } } HALT_SYS(); - return 0; /* SHOULD NOT HAPPEN */ + return 0; /* SHOULD NOT HAPPEN */ } /**************************************************************************** @@ -1046,82 +1046,81 @@ unsigned decode_rm10_address( int rm) { if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - int displacement; - - /* 32-bit addressing */ - if (rm != 4) - displacement = (s32)fetch_long_imm(); - else - displacement = 0; - - switch (rm) { - case 0: - DECODE_PRINTF2("%d[EAX]", displacement); - return M.x86.R_EAX + displacement; - case 1: - DECODE_PRINTF2("%d[ECX]", displacement); - return M.x86.R_ECX + displacement; - case 2: - DECODE_PRINTF2("%d[EDX]", displacement); - return M.x86.R_EDX + displacement; - case 3: - DECODE_PRINTF2("%d[EBX]", displacement); - return M.x86.R_EBX + displacement; - case 4: { - int offset = decode_sib_address(2); - displacement = (s32)fetch_long_imm(); - DECODE_PRINTF2("[%d]", displacement); - return offset + displacement; - } - case 5: - DECODE_PRINTF2("%d[EBP]", displacement); - return M.x86.R_EBP + displacement; - case 6: - DECODE_PRINTF2("%d[ESI]", displacement); - return M.x86.R_ESI + displacement; - case 7: - DECODE_PRINTF2("%d[EDI]", displacement); - return M.x86.R_EDI + displacement; - } + int displacement; + + /* 32-bit addressing */ + if (rm != 4) + displacement = (s32)fetch_long_imm(); + else + displacement = 0; + + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: { + int offset = decode_sib_address(2); + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d]", displacement); + return offset + displacement; + } + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } } else { - int displacement = (s16)fetch_word_imm(); - - /* 16-bit addressing */ - switch (rm) { - case 0: - DECODE_PRINTF2("%d[BX+SI]", displacement); - return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; - case 1: - DECODE_PRINTF2("%d[BX+DI]", displacement); - return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; - case 2: - DECODE_PRINTF2("%d[BP+SI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; - case 3: - DECODE_PRINTF2("%d[BP+DI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; - case 4: - DECODE_PRINTF2("%d[SI]", displacement); - return (M.x86.R_SI + displacement) & 0xffff; - case 5: - DECODE_PRINTF2("%d[DI]", displacement); - return (M.x86.R_DI + displacement) & 0xffff; - case 6: - DECODE_PRINTF2("%d[BP]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + displacement) & 0xffff; - case 7: - DECODE_PRINTF2("%d[BX]", displacement); - return (M.x86.R_BX + displacement) & 0xffff; - } + int displacement = (s16)fetch_word_imm(); + + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } } HALT_SYS(); - return 0; /* SHOULD NOT HAPPEN */ + return 0; /* SHOULD NOT HAPPEN */ } - /**************************************************************************** PARAMETERS: mod - modifier @@ -1143,6 +1142,3 @@ unsigned decode_rmXX_address(int mod, int rm) return decode_rm01_address(rm); return decode_rm10_address(rm); } - - - diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index 632979dd574..d1380ceec00 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -4,9 +4,9 @@ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. * Jason Jin * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -16,7 +16,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -32,13 +32,13 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * -* Description: This file includes subroutines to implement the decoding -* and emulation of all the x86 processor instructions. +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 processor instructions. * * There are approximately 250 subroutines in here, which correspond -* to the 256 byte-"opcodes" found on the 8086. The table which +* to the 256 byte-"opcodes" found on the 8086. The table which * dispatches this is found in the files optab.[ch]. * * Each opcode proc has a comment preceeding it which gives it's table @@ -48,14 +48,14 @@ * DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc * functions (START_OF_INSTR, END_OF_INSTR). * -* Many of the procedures are *VERY* similar in coding. This has +* Many of the procedures are *VERY* similar in coding. This has * allowed for a very large amount of code to be generated in a fairly * short amount of time (i.e. cut, paste, and modify). The result is * that much of the code below could have been folded into subroutines * for a large reduction in size of this file. The downside would be * that there would be a penalty in execution speed. The file could * also have been *MUCH* larger by inlining certain functions which -* were called. This could have resulted even faster execution. The +* were called. This could have resulted even faster execution. The * prime directive I used to decide whether to inline the code or to * modularize it, was basically: 1) no unnecessary subroutine calls, * 2) no routines more than about 200 lines in size, and 3) modularize @@ -88,38 +88,38 @@ static char *x86emu_GenOpName[8] = { /* used by several opcodes */ static u8 (*genop_byte_operation[])(u8 d, u8 s) __attribute__ ((section(".got2"))) = { - add_byte, /* 00 */ - or_byte, /* 01 */ - adc_byte, /* 02 */ - sbb_byte, /* 03 */ - and_byte, /* 04 */ - sub_byte, /* 05 */ - xor_byte, /* 06 */ - cmp_byte, /* 07 */ + add_byte, /* 00 */ + or_byte, /* 01 */ + adc_byte, /* 02 */ + sbb_byte, /* 03 */ + and_byte, /* 04 */ + sub_byte, /* 05 */ + xor_byte, /* 06 */ + cmp_byte, /* 07 */ }; static u16 (*genop_word_operation[])(u16 d, u16 s) __attribute__ ((section(".got2"))) = { - add_word, /*00 */ - or_word, /*01 */ - adc_word, /*02 */ - sbb_word, /*03 */ - and_word, /*04 */ - sub_word, /*05 */ - xor_word, /*06 */ - cmp_word, /*07 */ + add_word, /*00 */ + or_word, /*01 */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 */ + sub_word, /*05 */ + xor_word, /*06 */ + cmp_word, /*07 */ }; static u32 (*genop_long_operation[])(u32 d, u32 s) __attribute__ ((section(".got2"))) = { - add_long, /*00 */ - or_long, /*01 */ - adc_long, /*02 */ - sbb_long, /*03 */ - and_long, /*04 */ - sub_long, /*05 */ - xor_long, /*06 */ - cmp_long, /*07 */ + add_long, /*00 */ + or_long, /*01 */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 */ + sub_long, /*05 */ + xor_long, /*06 */ + cmp_long, /*07 */ }; /* used by opcodes 80, c0, d0, and d2. */ @@ -131,7 +131,7 @@ static u8(*opcD0_byte_operation[])(u8 d, u8 s) __attribute__ ((section(".got2")) rcr_byte, shl_byte, shr_byte, - shl_byte, /* sal_byte === shl_byte by definition */ + shl_byte, /* sal_byte === shl_byte by definition */ sar_byte, }; @@ -144,7 +144,7 @@ static u16(*opcD1_word_operation[])(u16 s, u8 d) __attribute__ ((section(".got2" rcr_word, shl_word, shr_word, - shl_word, /* sal_byte === shl_byte by definition */ + shl_word, /* sal_byte === shl_byte by definition */ sar_word, }; @@ -157,7 +157,7 @@ static u32 (*opcD1_long_operation[])(u32 s, u8 d) __attribute__ ((section(".got2 rcr_long, shl_long, shr_long, - shl_long, /* sal_byte === shl_byte by definition */ + shl_long, /* sal_byte === shl_byte by definition */ sar_long, }; @@ -180,21 +180,21 @@ void x86emuOp_illegal_op( { START_OF_INSTR(); if (M.x86.R_SP != 0) { - DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); - TRACE_REGS(); - DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-1,op1)); - HALT_SYS(); - } + DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); + TRACE_REGS(); + DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP-1,op1)); + HALT_SYS(); + } else { - /* If we get here, it means the stack pointer is back to zero - * so we are just returning from an emulator service call - * so therte is no need to display an error message. We trap - * the emulator with an 0xF1 opcode to finish the service - * call. - */ - X86EMU_halt_sys(); - } + /* If we get here, it means the stack pointer is back to zero + * so we are just returning from an emulator service call + * so therte is no need to display an error message. We trap + * the emulator with an 0xF1 opcode to finish the service + * call. + */ + X86EMU_halt_sys(); + } END_OF_INSTR(); } @@ -216,24 +216,24 @@ void x86emuOp_genop_byte_RM_R(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); if(mod<3) - { destoffset = decode_rmXX_address(mod,rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = genop_byte_operation[op1](destval, *srcreg); - store_data_byte(destoffset, destval); - } + { destoffset = decode_rmXX_address(mod,rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_byte_operation[op1](destval, *srcreg); + store_data_byte(destoffset, destval); + } else - { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_byte_operation[op1](*destreg, *srcreg); - } + { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_byte_operation[op1](*destreg, *srcreg); + } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -255,50 +255,50 @@ void x86emuOp_genop_word_RM_R(u8 op1) FETCH_DECODE_MODRM(mod, rh, rl); if(mod<3) { - destoffset = decode_rmXX_address(mod,rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = genop_long_operation[op1](destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = genop_word_operation[op1](destval, *srcreg); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_long_operation[op1](*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_word_operation[op1](*destreg, *srcreg); - } + destoffset = decode_rmXX_address(mod,rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_long_operation[op1](destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_word_operation[op1](destval, *srcreg); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_long_operation[op1](*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, *srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -322,15 +322,15 @@ void x86emuOp_genop_byte_R_RM(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod,rl); - srcval = fetch_data_byte(srcoffset); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - srcval = *srcreg; + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod,rl); + srcval = fetch_data_byte(srcoffset); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + srcval = *srcreg; } DECODE_PRINTF("\n"); TRACE_AND_STEP(); @@ -358,40 +358,40 @@ void x86emuOp_genop_word_R_RM(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod,rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destreg32 = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg32 = genop_long_operation[op1](*destreg32, srcval); - } else { - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_word_operation[op1](*destreg, srcval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - destreg32 = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg32 = genop_long_operation[op1](*destreg32, *srcreg); - } else { - u16 *srcreg; - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_word_operation[op1](*destreg, *srcreg); - } + srcoffset = decode_rmXX_address(mod,rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destreg32 = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = genop_long_operation[op1](*destreg32, srcval); + } else { + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, srcval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + destreg32 = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = genop_long_operation[op1](*destreg32, *srcreg); + } else { + u16 *srcreg; + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, *srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -430,20 +430,20 @@ void x86emuOp_genop_word_AX_IMM(u8 op1) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF(x86emu_GenOpName[op1]); - DECODE_PRINTF("\tEAX,"); - srcval = fetch_long_imm(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\tEAX,"); + srcval = fetch_long_imm(); } else { - DECODE_PRINTF(x86emu_GenOpName[op1]); - DECODE_PRINTF("\tAX,"); - srcval = fetch_word_imm(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\tAX,"); + srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = genop_long_operation[op1](M.x86.R_EAX, srcval); + M.x86.R_EAX = genop_long_operation[op1](M.x86.R_EAX, srcval); } else { - M.x86.R_AX = genop_word_operation[op1](M.x86.R_AX, (u16)srcval); + M.x86.R_AX = genop_word_operation[op1](M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -683,17 +683,17 @@ void x86emuOp_inc_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("INC\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = inc_long(*reg); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = inc_long(*reg); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = inc_word(*reg); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = inc_word(*reg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -709,17 +709,17 @@ void x86emuOp_dec_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("DEC\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = dec_long(*reg); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = dec_long(*reg); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = dec_word(*reg); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = dec_word(*reg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -735,17 +735,17 @@ void x86emuOp_push_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("PUSH\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_long(*reg); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*reg); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(*reg); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*reg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -761,17 +761,17 @@ void x86emuOp_pop_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("POP\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = pop_long(); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = pop_long(); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = pop_word(); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -785,33 +785,33 @@ void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSHAD\n"); + DECODE_PRINTF("PUSHAD\n"); } else { - DECODE_PRINTF("PUSHA\n"); + DECODE_PRINTF("PUSHA\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 old_sp = M.x86.R_ESP; - - push_long(M.x86.R_EAX); - push_long(M.x86.R_ECX); - push_long(M.x86.R_EDX); - push_long(M.x86.R_EBX); - push_long(old_sp); - push_long(M.x86.R_EBP); - push_long(M.x86.R_ESI); - push_long(M.x86.R_EDI); + u32 old_sp = M.x86.R_ESP; + + push_long(M.x86.R_EAX); + push_long(M.x86.R_ECX); + push_long(M.x86.R_EDX); + push_long(M.x86.R_EBX); + push_long(old_sp); + push_long(M.x86.R_EBP); + push_long(M.x86.R_ESI); + push_long(M.x86.R_EDI); } else { - u16 old_sp = M.x86.R_SP; - - push_word(M.x86.R_AX); - push_word(M.x86.R_CX); - push_word(M.x86.R_DX); - push_word(M.x86.R_BX); - push_word(old_sp); - push_word(M.x86.R_BP); - push_word(M.x86.R_SI); - push_word(M.x86.R_DI); + u16 old_sp = M.x86.R_SP; + + push_word(M.x86.R_AX); + push_word(M.x86.R_CX); + push_word(M.x86.R_DX); + push_word(M.x86.R_BX); + push_word(old_sp); + push_word(M.x86.R_BP); + push_word(M.x86.R_SI); + push_word(M.x86.R_DI); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -825,36 +825,36 @@ void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POPAD\n"); + DECODE_PRINTF("POPAD\n"); } else { - DECODE_PRINTF("POPA\n"); + DECODE_PRINTF("POPA\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDI = pop_long(); - M.x86.R_ESI = pop_long(); - M.x86.R_EBP = pop_long(); - M.x86.R_ESP += 4; /* skip ESP */ - M.x86.R_EBX = pop_long(); - M.x86.R_EDX = pop_long(); - M.x86.R_ECX = pop_long(); - M.x86.R_EAX = pop_long(); + M.x86.R_EDI = pop_long(); + M.x86.R_ESI = pop_long(); + M.x86.R_EBP = pop_long(); + M.x86.R_ESP += 4; /* skip ESP */ + M.x86.R_EBX = pop_long(); + M.x86.R_EDX = pop_long(); + M.x86.R_ECX = pop_long(); + M.x86.R_EAX = pop_long(); } else { - M.x86.R_DI = pop_word(); - M.x86.R_SI = pop_word(); - M.x86.R_BP = pop_word(); - M.x86.R_SP += 2; /* skip SP */ - M.x86.R_BX = pop_word(); - M.x86.R_DX = pop_word(); - M.x86.R_CX = pop_word(); - M.x86.R_AX = pop_word(); + M.x86.R_DI = pop_word(); + M.x86.R_SI = pop_word(); + M.x86.R_BP = pop_word(); + M.x86.R_SP += 2; /* skip SP */ + M.x86.R_BX = pop_word(); + M.x86.R_DX = pop_word(); + M.x86.R_CX = pop_word(); + M.x86.R_AX = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } -/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ -/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ /**************************************************************************** REMARKS: @@ -928,16 +928,16 @@ void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - imm = fetch_long_imm(); + imm = fetch_long_imm(); } else { - imm = fetch_word_imm(); + imm = fetch_word_imm(); } DECODE_PRINTF2("PUSH\t%x\n", imm); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(imm); + push_long(imm); } else { - push_word((u16)imm); + push_word((u16)imm); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -956,95 +956,95 @@ void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - s32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_long(srcoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - s16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_word(srcoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - s32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - s16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - res = (s16)*srcreg * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1075,98 +1075,98 @@ void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; - s8 imm; + s8 imm; START_OF_INSTR(); DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_long(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_word(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)*srcreg * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)*srcreg * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1194,11 +1194,11 @@ void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INSD\n"); - ins(4); + DECODE_PRINTF("INSD\n"); + ins(4); } else { - DECODE_PRINTF("INSW\n"); - ins(2); + DECODE_PRINTF("INSW\n"); + ins(2); } TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); @@ -1227,11 +1227,11 @@ void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("OUTSD\n"); - outs(4); + DECODE_PRINTF("OUTSD\n"); + outs(4); } else { - DECODE_PRINTF("OUTSW\n"); - outs(2); + DECODE_PRINTF("OUTSW\n"); + outs(2); } TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); @@ -1258,7 +1258,7 @@ void x86emuOp_jump_near_cond(u8 op1) DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (cond) - M.x86.R_IP = target; + M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -1276,7 +1276,7 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) u8 destval; /* - * Weirdo special case instruction format. Part of the opcode + * Weirdo special case instruction format. Part of the opcode * held below in "RH". Doubly nested case would result, except * that the decoded instruction */ @@ -1284,61 +1284,61 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_byte_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1354,7 +1354,7 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) uint destoffset; /* - * Weirdo special case instruction format. Part of the opcode + * Weirdo special case instruction format. Part of the opcode * held below in "RH". Doubly nested case would result, except * that the decoded instruction */ @@ -1362,37 +1362,37 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* @@ -1400,57 +1400,57 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) * mode. */ if (mod < 3) { - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 destval,imm; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_long_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_long_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - } else { - u16 *destreg; - u16 destval,imm; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_word_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - } + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1469,7 +1469,7 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) u8 destval; /* - * Weirdo special case instruction format. Part of the opcode + * Weirdo special case instruction format. Part of the opcode * held below in "RH". Doubly nested case would result, except * that the decoded instruction Similar to opcode 81, except that * the immediate byte is sign extended to a word length. @@ -1478,58 +1478,58 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_byte_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1545,7 +1545,7 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) uint destoffset; /* - * Weirdo special case instruction format. Part of the opcode + * Weirdo special case instruction format. Part of the opcode * held below in "RH". Doubly nested case would result, except * that the decoded instruction Similar to opcode 81, except that * the immediate byte is sign extended to a word length. @@ -1554,89 +1554,89 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod,rl); - - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - destval = fetch_data_long(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - destval = fetch_data_word(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 destval,imm; - - destreg = DECODE_RM_LONG_REGISTER(rl); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_long_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - } else { - u16 *destreg; - u16 destval,imm; - - destreg = DECODE_RM_WORD_REGISTER(rl); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_word_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - } + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod,rl); + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1657,20 +1657,20 @@ void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("TEST\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_byte(destval, *srcreg); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_byte(*destreg, *srcreg); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(*destreg, *srcreg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1689,48 +1689,48 @@ void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("TEST\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_long(destval, *srcreg); - } else { - u16 destval; - u16 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_word(destval, *srcreg); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_word(*destreg, *srcreg); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(*destreg, *srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1752,25 +1752,25 @@ void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("XCHG\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1789,59 +1789,59 @@ void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("XCHG\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - u32 destval,tmp; - - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_long(destoffset, destval); - } else { - u16 *srcreg; - u16 destval,tmp; - - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 tmp; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; - } else { - u16 *destreg,*srcreg; - u16 tmp; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; - } + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 tmp; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } else { + u16 *destreg,*srcreg; + u16 tmp; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1861,19 +1861,19 @@ void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_byte(destoffset, *srcreg); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1892,44 +1892,44 @@ void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_long(destoffset, *srcreg); - } else { - u16 *srcreg; - - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_word(destoffset, *srcreg); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1950,20 +1950,20 @@ void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1982,49 +1982,49 @@ void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg, *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg, *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg, *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2045,20 +2045,20 @@ void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - srcreg = decode_rm_seg_register(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = *srcreg; - store_data_word(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = decode_rm_seg_register(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2077,20 +2077,20 @@ void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) /* * TODO: Need to handle address size prefix! * - * lea eax,[eax+ebx*2] ?? + * lea eax,[eax+ebx*2] ?? */ START_OF_INSTR(); DECODE_PRINTF("LEA\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *srcreg = (u16)destoffset; - } + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } /* } else { undefined. Do nothing. } */ DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2111,20 +2111,20 @@ void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = decode_rm_seg_register(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = decode_rm_seg_register(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } /* * Clean up, and reset all the R_xSP pointers to the correct @@ -2149,42 +2149,42 @@ void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("POP\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); } if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_long(); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_word(); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = pop_long(); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = pop_word(); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_long(); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_word(); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2216,23 +2216,23 @@ void x86emuOp_xchg_word_AX_register(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg32; - DECODE_PRINTF("XCHG\tEAX,"); - reg32 = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = M.x86.R_EAX; - M.x86.R_EAX = *reg32; - *reg32 = tmp; + u32 *reg32; + DECODE_PRINTF("XCHG\tEAX,"); + reg32 = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = M.x86.R_EAX; + M.x86.R_EAX = *reg32; + *reg32 = tmp; } else { - u16 *reg16; - DECODE_PRINTF("XCHG\tAX,"); - reg16 = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = M.x86.R_AX; - M.x86.R_EAX = *reg16; - *reg16 = (u16)tmp; + u16 *reg16; + DECODE_PRINTF("XCHG\tAX,"); + reg16 = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = M.x86.R_AX; + M.x86.R_EAX = *reg16; + *reg16 = (u16)tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2246,23 +2246,23 @@ void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CWDE\n"); + DECODE_PRINTF("CWDE\n"); } else { - DECODE_PRINTF("CBW\n"); + DECODE_PRINTF("CBW\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - if (M.x86.R_AX & 0x8000) { - M.x86.R_EAX |= 0xffff0000; - } else { - M.x86.R_EAX &= 0x0000ffff; - } + if (M.x86.R_AX & 0x8000) { + M.x86.R_EAX |= 0xffff0000; + } else { + M.x86.R_EAX &= 0x0000ffff; + } } else { - if (M.x86.R_AL & 0x80) { - M.x86.R_AH = 0xff; - } else { - M.x86.R_AH = 0x0; - } + if (M.x86.R_AL & 0x80) { + M.x86.R_AH = 0xff; + } else { + M.x86.R_AH = 0x0; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2276,24 +2276,24 @@ void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CDQ\n"); + DECODE_PRINTF("CDQ\n"); } else { - DECODE_PRINTF("CWD\n"); + DECODE_PRINTF("CWD\n"); } DECODE_PRINTF("CWD\n"); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - if (M.x86.R_EAX & 0x80000000) { - M.x86.R_EDX = 0xffffffff; - } else { - M.x86.R_EDX = 0x0; - } + if (M.x86.R_EAX & 0x80000000) { + M.x86.R_EDX = 0xffffffff; + } else { + M.x86.R_EDX = 0x0; + } } else { - if (M.x86.R_AX & 0x8000) { - M.x86.R_DX = 0xffff; - } else { - M.x86.R_DX = 0x0; - } + if (M.x86.R_AX & 0x8000) { + M.x86.R_DX = 0xffff; + } else { + M.x86.R_DX = 0x0; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2319,7 +2319,7 @@ void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) * * Hooked interrupt vectors calling into our "BIOS" will cause * problems unless all intersegment stuff is checked for BIOS - * access. Check needed here. For moment, let it alone. + * access. Check needed here. For moment, let it alone. */ TRACE_AND_STEP(); push_word(M.x86.R_CS); @@ -2354,18 +2354,18 @@ void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSHFD\n"); + DECODE_PRINTF("PUSHFD\n"); } else { - DECODE_PRINTF("PUSHF\n"); + DECODE_PRINTF("PUSHF\n"); } TRACE_AND_STEP(); /* clear out *all* bits not representing flags, and turn on real bits */ flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON; if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(flags); + push_long(flags); } else { - push_word((u16)flags); + push_word((u16)flags); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2379,15 +2379,15 @@ void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POPFD\n"); + DECODE_PRINTF("POPFD\n"); } else { - DECODE_PRINTF("POPF\n"); + DECODE_PRINTF("POPF\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EFLG = pop_long(); + M.x86.R_EFLG = pop_long(); } else { - M.x86.R_FLG = pop_word(); + M.x86.R_FLG = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2456,15 +2456,15 @@ void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); offset = fetch_word_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); + DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); } else { - DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); + DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = fetch_data_long(offset); + M.x86.R_EAX = fetch_data_long(offset); } else { - M.x86.R_AX = fetch_data_word(offset); + M.x86.R_AX = fetch_data_word(offset); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2499,15 +2499,15 @@ void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); offset = fetch_word_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); + DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); } else { - DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); + DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - store_data_long(offset, M.x86.R_EAX); + store_data_long(offset, M.x86.R_EAX); } else { - store_data_word(offset, M.x86.R_AX); + store_data_word(offset, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2519,30 +2519,30 @@ Handles opcode 0xa4 ****************************************************************************/ void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) { - u8 val; + u8 val; u32 count; int inc; START_OF_INSTR(); DECODE_PRINTF("MOVS\tBYTE\n"); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - count = M.x86.R_CX; - M.x86.R_CX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - val = fetch_data_byte(M.x86.R_SI); - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); - M.x86.R_SI += inc; - M.x86.R_DI += inc; + val = fetch_data_byte(M.x86.R_SI); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); + M.x86.R_SI += inc; + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2560,37 +2560,37 @@ void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOVS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("MOVS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("MOVS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("MOVS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - count = M.x86.R_CX; - M.x86.R_CX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long(M.x86.R_SI); - store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); - } else { - val = fetch_data_word(M.x86.R_SI); - store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); - } - M.x86.R_SI += inc; - M.x86.R_DI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long(M.x86.R_SI); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); + } else { + val = fetch_data_word(M.x86.R_SI); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2609,30 +2609,30 @@ void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("CMPS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* REPE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - val1 = fetch_data_byte(M.x86.R_SI); - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(val1, val2); - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && (ACCESS_FLAG(F_ZF) == 0) ) break; - if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && (ACCESS_FLAG(F_ZF) == 0) ) break; + if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - val1 = fetch_data_byte(M.x86.R_SI); - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(val1, val2); - M.x86.R_SI += inc; - M.x86.R_DI += inc; + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_SI += inc; + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2649,48 +2649,48 @@ void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CMPS\tDWORD\n"); - inc = 4; + DECODE_PRINTF("CMPS\tDWORD\n"); + inc = 4; } else { - DECODE_PRINTF("CMPS\tWORD\n"); - inc = 2; + DECODE_PRINTF("CMPS\tWORD\n"); + inc = 2; } if (ACCESS_FLAG(F_DF)) /* down */ - inc = -inc; + inc = -inc; TRACE_AND_STEP(); if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* REPE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val1 = fetch_data_long(M.x86.R_SI); - val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(val1, val2); - } else { - val1 = fetch_data_word(M.x86.R_SI); - val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word((u16)val1, (u16)val2); - } - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && ACCESS_FLAG(F_ZF) == 0 ) break; - if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && ACCESS_FLAG(F_ZF) == 0 ) break; + if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val1 = fetch_data_long(M.x86.R_SI); - val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(val1, val2); - } else { - val1 = fetch_data_word(M.x86.R_SI); - val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word((u16)val1, (u16)val2); - } - M.x86.R_SI += inc; - M.x86.R_DI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2724,18 +2724,18 @@ void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("TEST\tEAX,"); - srcval = fetch_long_imm(); + DECODE_PRINTF("TEST\tEAX,"); + srcval = fetch_long_imm(); } else { - DECODE_PRINTF("TEST\tAX,"); - srcval = fetch_word_imm(); + DECODE_PRINTF("TEST\tAX,"); + srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - test_long(M.x86.R_EAX, srcval); + test_long(M.x86.R_EAX, srcval); } else { - test_word(M.x86.R_AX, (u16)srcval); + test_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2752,22 +2752,22 @@ void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("STOS\tBYTE\n"); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; TRACE_AND_STEP(); if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); - M.x86.R_DI += inc; + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2784,34 +2784,34 @@ void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("STOS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("STOS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("STOS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("STOS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - count = M.x86.R_CX; - M.x86.R_CX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); - } else { - store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); - } - M.x86.R_DI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); + } else { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); + } + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2829,21 +2829,21 @@ void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LODS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - M.x86.R_AL = fetch_data_byte(M.x86.R_SI); - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - M.x86.R_AL = fetch_data_byte(M.x86.R_SI); - M.x86.R_SI += inc; + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_SI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2860,34 +2860,34 @@ void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("LODS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("LODS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("LODS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("LODS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - count = M.x86.R_CX; - M.x86.R_CX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = fetch_data_long(M.x86.R_SI); - } else { - M.x86.R_AX = fetch_data_word(M.x86.R_SI); - } - M.x86.R_SI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(M.x86.R_SI); + } else { + M.x86.R_AX = fetch_data_word(M.x86.R_SI); + } + M.x86.R_SI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2906,37 +2906,37 @@ void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("SCAS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; if (M.x86.mode & SYSMODE_PREFIX_REPE) { - /* REPE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF) == 0) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPE; + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { - /* REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF)) - break; /* zero flag set means equal */ - } - M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; } else { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - M.x86.R_DI += inc; + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2953,62 +2953,62 @@ void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("SCAS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("SCAS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("SCAS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("SCAS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_REPE) { - /* REPE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF) == 0) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPE; + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { - /* REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF)) - break; /* zero flag set means equal */ - } - M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; } else { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - M.x86.R_DI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3047,19 +3047,19 @@ void x86emuOp_mov_word_register_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("MOV\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg32; - reg32 = DECODE_RM_LONG_REGISTER(op1); - srcval = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", srcval); - TRACE_AND_STEP(); - *reg32 = srcval; + u32 *reg32; + reg32 = DECODE_RM_LONG_REGISTER(op1); + srcval = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", srcval); + TRACE_AND_STEP(); + *reg32 = srcval; } else { - u16 *reg16; - reg16 = DECODE_RM_WORD_REGISTER(op1); - srcval = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", srcval); - TRACE_AND_STEP(); - *reg16 = (u16)srcval; + u16 *reg16; + reg16 = DECODE_RM_WORD_REGISTER(op1); + srcval = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", srcval); + TRACE_AND_STEP(); + *reg16 = (u16)srcval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3086,57 +3086,57 @@ void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, amt); - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3161,83 +3161,83 @@ void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3292,15 +3292,15 @@ void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LES\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_ES = fetch_data_word(srcoffset + 2); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); } - /* else UNDEFINED! register to register */ + /* else UNDEFINED! register to register */ DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3320,13 +3320,13 @@ void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LDS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_DS = fetch_data_word(srcoffset + 2); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); } /* else UNDEFINED! */ DECODE_CLEAR_SEGOVR(); @@ -3348,22 +3348,22 @@ void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); + HALT_SYS(); } if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%2x\n", imm); - TRACE_AND_STEP(); - store_data_byte(destoffset, imm); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%2x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3382,49 +3382,49 @@ void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); } if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_long(destoffset, imm); - } else { - u16 imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_word(destoffset, imm); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 imm; - destreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; - } else { + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } else { u16 *destreg; u16 imm; - destreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; - } + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3437,7 +3437,7 @@ Handles opcode 0xc8 void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) { u16 local,frame_pointer; - u8 nesting; + u8 nesting; int i; START_OF_INSTR(); @@ -3449,12 +3449,12 @@ void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) push_word(M.x86.R_BP); frame_pointer = M.x86.R_SP; if (nesting > 0) { - for (i = 1; i < nesting; i++) { - M.x86.R_BP -= 2; - push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); - } - push_word(frame_pointer); - } + for (i = 1; i < nesting; i++) { + M.x86.R_BP -= 2; + push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); + } + push_word(frame_pointer); + } M.x86.R_BP = frame_pointer; M.x86.R_SP = (u16)(M.x86.R_SP - local); DECODE_CLEAR_SEGOVR(); @@ -3529,13 +3529,13 @@ void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) if (_X86EMU_intrTab[3]) { (*_X86EMU_intrTab[3])(3); } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(3 * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(3 * 4); + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(3 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(3 * 4); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3559,13 +3559,13 @@ void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) if (_X86EMU_intrTab[intnum]) { (*_X86EMU_intrTab[intnum])(intnum); } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(intnum * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(intnum * 4); + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intnum * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intnum * 4); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3583,18 +3583,18 @@ void x86emuOp_into(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("INTO\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_OF)) { - tmp = mem_access_word(4 * 4 + 2); + tmp = mem_access_word(4 * 4 + 2); if (_X86EMU_intrTab[4]) { (*_X86EMU_intrTab[4])(4); - } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(4 * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(4 * 4); - } + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(4 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(4 * 4); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3638,54 +3638,54 @@ void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, 1); - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, 1); - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, 1); + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3709,82 +3709,82 @@ void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, 1); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, 1); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *destreg; - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (*destreg, 1); - *destreg = destval; - } else { + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (*destreg, 1); + *destreg = destval; + } else { u16 destval; u16 *destreg; - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (*destreg, 1); - *destreg = destval; - } + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (*destreg, 1); + *destreg = destval; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3811,55 +3811,55 @@ void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ amt = M.x86.R_CL; if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, amt); - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3884,79 +3884,79 @@ void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ amt = M.x86.R_CL; if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3974,9 +3974,9 @@ void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("AAM\n"); a = fetch_byte_imm(); /* this is a stupid encoding. */ if (a != 10) { - DECODE_PRINTF("ERROR DECODING AAM\n"); - TRACE_REGS(); - HALT_SYS(); + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); } TRACE_AND_STEP(); /* note the type change here --- returning AL and AH in AX. */ @@ -4021,7 +4021,7 @@ void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) END_OF_INSTR(); } -/* instuctions D8 .. DF are in i87_ops.c */ +/* instuctions D8 .. DF are in i87_ops.c */ /**************************************************************************** REMARKS: @@ -4038,8 +4038,8 @@ void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); M.x86.R_CX -= 1; - if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ - M.x86.R_IP = ip; + if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ + M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4059,8 +4059,8 @@ void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); M.x86.R_CX -= 1; - if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ - M.x86.R_IP = ip; + if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ + M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4081,7 +4081,7 @@ void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); M.x86.R_CX -= 1; if (M.x86.R_CX != 0) - M.x86.R_IP = ip; + M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4093,7 +4093,7 @@ Handles opcode 0xe3 void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) { u16 target; - s8 offset; + s8 offset; /* jump to byte offset if overflow flag is set */ START_OF_INSTR(); @@ -4103,7 +4103,7 @@ void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (M.x86.R_CX == 0) - M.x86.R_IP = target; + M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4138,15 +4138,15 @@ void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("IN\t"); port = (u8) fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("EAX,%x\n", port); + DECODE_PRINTF2("EAX,%x\n", port); } else { - DECODE_PRINTF2("AX,%x\n", port); + DECODE_PRINTF2("AX,%x\n", port); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = (*sys_inl)(port); + M.x86.R_EAX = (*sys_inl)(port); } else { - M.x86.R_AX = (*sys_inw)(port); + M.x86.R_AX = (*sys_inw)(port); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4182,15 +4182,15 @@ void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("OUT\t"); port = (u8) fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("%x,EAX\n", port); + DECODE_PRINTF2("%x,EAX\n", port); } else { - DECODE_PRINTF2("%x,AX\n", port); + DECODE_PRINTF2("%x,AX\n", port); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - (*sys_outl)(port, M.x86.R_EAX); + (*sys_outl)(port, M.x86.R_EAX); } else { - (*sys_outw)(port, M.x86.R_AX); + (*sys_outw)(port, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4207,7 +4207,7 @@ void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("CALL\t"); ip = (s16) fetch_word_imm(); - ip += (s16) M.x86.R_IP; /* CHECK SIGN */ + ip += (s16) M.x86.R_IP; /* CHECK SIGN */ DECODE_PRINTF2("%04x\n", ip); CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, ""); TRACE_AND_STEP(); @@ -4299,15 +4299,15 @@ void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("IN\tEAX,DX\n"); + DECODE_PRINTF("IN\tEAX,DX\n"); } else { - DECODE_PRINTF("IN\tAX,DX\n"); + DECODE_PRINTF("IN\tAX,DX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); + M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); } else { - M.x86.R_AX = (*sys_inw)(M.x86.R_DX); + M.x86.R_AX = (*sys_inw)(M.x86.R_DX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4335,15 +4335,15 @@ void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("OUT\tDX,EAX\n"); + DECODE_PRINTF("OUT\tDX,EAX\n"); } else { - DECODE_PRINTF("OUT\tDX,AX\n"); + DECODE_PRINTF("OUT\tDX,AX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); + (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); } else { - (*sys_outw)(M.x86.R_DX, M.x86.R_AX); + (*sys_outw)(M.x86.R_DX, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4438,100 +4438,100 @@ void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); DECODE_PRINTF(opF6_names[rh]); if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_byte(destoffset); - - switch (rh) { - case 0: /* test byte imm */ - DECODE_PRINTF(","); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%02x\n", srcval); - TRACE_AND_STEP(); - test_byte(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = not_byte(destval); - store_data_byte(destoffset, destval); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = neg_byte(destval); - store_data_byte(destoffset, destval); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_byte(destval); - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_byte(destval); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_byte(destval); - break; - default: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_byte(destval); - break; - } - } else { /* mod=11 */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - switch (rh) { - case 0: /* test byte imm */ - DECODE_PRINTF(","); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%02x\n", srcval); - TRACE_AND_STEP(); - test_byte(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_byte(*destreg); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_byte(*destreg); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_byte(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_byte(*destreg); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_byte(*destreg); - break; - default: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_byte(*destreg); - break; - } + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_byte(destoffset); + + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(destval); + break; + default: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + } else { /* mod=11 */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_byte(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_byte(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(*destreg); + break; + default: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(*destreg); + break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4551,213 +4551,213 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF(opF6_names[rh]); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval, srcval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_long(destoffset); - - switch (rh) { - case 0: - DECODE_PRINTF(","); - srcval = fetch_long_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_long(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = not_long(destval); - store_data_long(destoffset, destval); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = neg_long(destval); - store_data_long(destoffset, destval); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_long(destval); - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_long(destval); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_long(destval); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_long(destval); - break; - } - } else { - u16 destval, srcval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_word(destoffset); - - switch (rh) { - case 0: /* test word imm */ - DECODE_PRINTF(","); - srcval = fetch_word_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_word(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = not_word(destval); - store_data_word(destoffset, destval); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = neg_word(destval); - store_data_word(destoffset, destval); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_word(destval); - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_word(destval); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_word(destval); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_word(destval); - break; - } - } - - } else { /* mod=11 */ - - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rl); - - switch (rh) { - case 0: /* test word imm */ - DECODE_PRINTF(","); - srcval = fetch_long_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_long(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_long(*destreg); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_long(*destreg); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_long(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_long(*destreg); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_long(*destreg); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_long(*destreg); - break; - } - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rl); - - switch (rh) { - case 0: /* test word imm */ - DECODE_PRINTF(","); - srcval = fetch_word_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_word(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_word(*destreg); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_word(*destreg); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_word(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_word(*destreg); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_word(*destreg); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_word(*destreg); - break; - } - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval, srcval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_long(destoffset); + + switch (rh) { + case 0: + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(destval); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(destval); + break; + } + } else { + u16 destval, srcval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_word(destoffset); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(destval); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(destval); + break; + } + } + + } else { /* mod=11 */ + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rl); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_long(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_long(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(*destreg); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(*destreg); + break; + } + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rl); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_word(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_word(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(*destreg); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(*destreg); + break; + } + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4869,49 +4869,49 @@ void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("INC\t"); - break; - case 1: - DECODE_PRINTF("DEC\t"); - break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); - HALT_SYS(); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("INC\t"); + break; + case 1: + DECODE_PRINTF("DEC\t"); + break; + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + HALT_SYS(); + break; + } } #endif if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - if (rh == 0) - destval = inc_byte(destval); - else - destval = dec_byte(destval); - store_data_byte(destoffset, destval); + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + if (rh == 0) + destval = inc_byte(destval); + else + destval = dec_byte(destval); + store_data_byte(destoffset, destval); } else { - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - if (rh == 0) - *destreg = inc_byte(*destreg); - else - *destreg = dec_byte(*destreg); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + if (rh == 0) + *destreg = inc_byte(*destreg); + else + *destreg = dec_byte(*destreg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4933,207 +4933,207 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tDWORD PTR "); - } else { - DECODE_PRINTF("INC\tWORD PTR "); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tDWORD PTR "); - } else { - DECODE_PRINTF("DEC\tWORD PTR "); - } - break; - case 2: - DECODE_PRINTF("CALL\t "); - break; - case 3: - DECODE_PRINTF("CALL\tFAR "); - break; - case 4: - DECODE_PRINTF("JMP\t"); - break; - case 5: - DECODE_PRINTF("JMP\tFAR "); - break; - case 6: - DECODE_PRINTF("PUSH\t"); - break; - case 7: - DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); - HALT_SYS(); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tDWORD PTR "); + } else { + DECODE_PRINTF("INC\tWORD PTR "); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tDWORD PTR "); + } else { + DECODE_PRINTF("DEC\tWORD PTR "); + } + break; + case 2: + DECODE_PRINTF("CALL\t "); + break; + case 3: + DECODE_PRINTF("CALL\tFAR "); + break; + case 4: + DECODE_PRINTF("JMP\t"); + break; + case 5: + DECODE_PRINTF("JMP\tFAR "); + break; + case 6: + DECODE_PRINTF("PUSH\t"); + break; + case 7: + DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); + HALT_SYS(); + break; + } } #endif if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - switch (rh) { - case 0: /* inc word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = inc_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = inc_word(destval); - store_data_word(destoffset, destval); - } - break; - case 1: /* dec word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = dec_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = dec_word(destval); - store_data_word(destoffset, destval); - } - break; - case 2: /* call word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 3: /* call far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - push_word(M.x86.R_CS); - M.x86.R_CS = destval2; - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 4: /* jmp word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - break; - case 5: /* jmp far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - M.x86.R_CS = destval2; - break; - case 6: /* push word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - push_long(destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(destval); - } - break; - } + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: /* dec word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } } else { - switch (rh) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = inc_long(*destreg); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = inc_word(*destreg); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = dec_long(*destreg); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = dec_word(*destreg); - } - break; - case 2: /* call word ptr ... */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = *destreg; - break; - case 3: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); - TRACE_AND_STEP(); - HALT_SYS(); - break; - - case 4: /* jmp ... */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - M.x86.R_IP = (u16) (*destreg); - break; - case 5: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); - TRACE_AND_STEP(); - HALT_SYS(); - break; - case 6: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_long(*destreg); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(*destreg); - } - break; - } + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_word(*destreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_word(*destreg); + } + break; + case 2: /* call word ptr ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = *destreg; + break; + case 3: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + + case 4: /* jmp ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + M.x86.R_IP = (u16) (*destreg); + break; + case 5: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*destreg); + } + break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index 2412b24cd80..631a340ed2b 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -1,13 +1,13 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. * Jason Jin * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -17,7 +17,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -31,16 +31,16 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: This file includes subroutines to implement the decoding -* and emulation of all the x86 extended two-byte processor -* instructions. +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 extended two-byte processor +* instructions. * -* Jason port this file to u-boot. Put the function pointer into -* got2 sector. +* Jason port this file to u-boot. Put the function pointer into +* got2 sector. * ****************************************************************************/ @@ -62,7 +62,7 @@ void x86emuOp2_illegal_op( DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); TRACE_REGS(); printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-2,op2); + M.x86.R_CS, M.x86.R_IP-2,op2); HALT_SYS(); END_OF_INSTR(); } @@ -77,69 +77,69 @@ int x86emu_check_jump_condition(u8 op) { switch (op) { case 0x0: - DECODE_PRINTF("JO\t"); - return ACCESS_FLAG(F_OF); + DECODE_PRINTF("JO\t"); + return ACCESS_FLAG(F_OF); case 0x1: - DECODE_PRINTF("JNO\t"); - return !ACCESS_FLAG(F_OF); - break; + DECODE_PRINTF("JNO\t"); + return !ACCESS_FLAG(F_OF); + break; case 0x2: - DECODE_PRINTF("JB\t"); - return ACCESS_FLAG(F_CF); - break; + DECODE_PRINTF("JB\t"); + return ACCESS_FLAG(F_CF); + break; case 0x3: - DECODE_PRINTF("JNB\t"); - return !ACCESS_FLAG(F_CF); - break; + DECODE_PRINTF("JNB\t"); + return !ACCESS_FLAG(F_CF); + break; case 0x4: - DECODE_PRINTF("JZ\t"); - return ACCESS_FLAG(F_ZF); - break; + DECODE_PRINTF("JZ\t"); + return ACCESS_FLAG(F_ZF); + break; case 0x5: - DECODE_PRINTF("JNZ\t"); - return !ACCESS_FLAG(F_ZF); - break; + DECODE_PRINTF("JNZ\t"); + return !ACCESS_FLAG(F_ZF); + break; case 0x6: - DECODE_PRINTF("JBE\t"); - return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); - break; + DECODE_PRINTF("JBE\t"); + return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; case 0x7: - DECODE_PRINTF("JNBE\t"); - return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); - break; + DECODE_PRINTF("JNBE\t"); + return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; case 0x8: - DECODE_PRINTF("JS\t"); - return ACCESS_FLAG(F_SF); - break; + DECODE_PRINTF("JS\t"); + return ACCESS_FLAG(F_SF); + break; case 0x9: - DECODE_PRINTF("JNS\t"); - return !ACCESS_FLAG(F_SF); - break; + DECODE_PRINTF("JNS\t"); + return !ACCESS_FLAG(F_SF); + break; case 0xa: - DECODE_PRINTF("JP\t"); - return ACCESS_FLAG(F_PF); - break; + DECODE_PRINTF("JP\t"); + return ACCESS_FLAG(F_PF); + break; case 0xb: - DECODE_PRINTF("JNP\t"); - return !ACCESS_FLAG(F_PF); - break; + DECODE_PRINTF("JNP\t"); + return !ACCESS_FLAG(F_PF); + break; case 0xc: - DECODE_PRINTF("JL\t"); - return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + DECODE_PRINTF("JL\t"); + return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0xd: - DECODE_PRINTF("JNL\t"); - return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + DECODE_PRINTF("JNL\t"); + return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0xe: - DECODE_PRINTF("JLE\t"); - return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; + DECODE_PRINTF("JLE\t"); + return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; default: - DECODE_PRINTF("JNLE\t"); - return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); + DECODE_PRINTF("JNLE\t"); + return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); } } @@ -156,7 +156,7 @@ void x86emuOp2_long_jump(u8 op2) DECODE_PRINTF2("%04x\n", target); TRACE_AND_STEP(); if (cond) - M.x86.R_IP = (u16)target; + M.x86.R_IP = (u16)target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -169,89 +169,89 @@ void x86emuOp2_set_byte(u8 op2) { int mod, rl, rh; uint destoffset; - u8 *destreg; + u8 *destreg; char *name = 0; int cond = 0; START_OF_INSTR(); switch (op2) { case 0x90: - name = "SETO\t"; - cond = ACCESS_FLAG(F_OF); - break; + name = "SETO\t"; + cond = ACCESS_FLAG(F_OF); + break; case 0x91: - name = "SETNO\t"; - cond = !ACCESS_FLAG(F_OF); - break; + name = "SETNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; case 0x92: - name = "SETB\t"; - cond = ACCESS_FLAG(F_CF); - break; + name = "SETB\t"; + cond = ACCESS_FLAG(F_CF); + break; case 0x93: - name = "SETNB\t"; - cond = !ACCESS_FLAG(F_CF); - break; + name = "SETNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; case 0x94: - name = "SETZ\t"; - cond = ACCESS_FLAG(F_ZF); - break; + name = "SETZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; case 0x95: - name = "SETNZ\t"; - cond = !ACCESS_FLAG(F_ZF); - break; + name = "SETNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; case 0x96: - name = "SETBE\t"; - cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); - break; + name = "SETBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; case 0x97: - name = "SETNBE\t"; - cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); - break; + name = "SETNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; case 0x98: - name = "SETS\t"; - cond = ACCESS_FLAG(F_SF); - break; + name = "SETS\t"; + cond = ACCESS_FLAG(F_SF); + break; case 0x99: - name = "SETNS\t"; - cond = !ACCESS_FLAG(F_SF); - break; + name = "SETNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; case 0x9a: - name = "SETP\t"; - cond = ACCESS_FLAG(F_PF); - break; + name = "SETP\t"; + cond = ACCESS_FLAG(F_PF); + break; case 0x9b: - name = "SETNP\t"; - cond = !ACCESS_FLAG(F_PF); - break; + name = "SETNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; case 0x9c: - name = "SETL\t"; - cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + name = "SETL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0x9d: - name = "SETNL\t"; - cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + name = "SETNL\t"; + cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0x9e: - name = "SETLE\t"; - cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; + name = "SETLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; case 0x9f: - name = "SETNLE\t"; - cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; + name = "SETNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; } DECODE_PRINTF(name); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - TRACE_AND_STEP(); - store_data_byte(destoffset, cond ? 0x01 : 0x00); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - TRACE_AND_STEP(); - *destreg = cond ? 0x01 : 0x00; + destoffset = decode_rmXX_address(mod, rl); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + TRACE_AND_STEP(); + *destreg = cond ? 0x01 : 0x00; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -299,50 +299,50 @@ void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BT\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); - } else { - u16 srcval; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); - } else { - u16 *srcreg,*shiftreg; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } else { + u16 *srcreg,*shiftreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -362,58 +362,58 @@ void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shld_long(destval,*shiftreg,shift); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shld_word(destval,*shiftreg,shift); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shld_long(*destreg,*shiftreg,shift); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shld_word(*destreg,*shiftreg,shift); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,shift); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -432,50 +432,50 @@ void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shld_long(destval,*shiftreg,M.x86.R_CL); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shld_word(destval,*shiftreg,M.x86.R_CL); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -523,60 +523,60 @@ void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BTS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval | mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, srcval | mask); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg |= mask; - } else { - u16 *srcreg,*shiftreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg |= mask; - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -596,58 +596,58 @@ void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shrd_long(destval,*shiftreg,shift); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shrd_word(destval,*shiftreg,shift); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shrd_long(*destreg,*shiftreg,shift); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shrd_word(*destreg,*shiftreg,shift); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,shift); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -666,49 +666,49 @@ void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shrd_long(destval,*shiftreg,M.x86.R_CL); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shrd_word(destval,*shiftreg,M.x86.R_CL); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); - } + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -727,80 +727,80 @@ void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_long(srcoffset); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - TRACE_AND_STEP(); - res = (s16)*destreg * (s16)srcval; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - res = (s16)*destreg * (s16)*srcreg; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_long(srcoffset); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + res = (s16)*destreg * (s16)*srcreg; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -820,16 +820,16 @@ void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("LSS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_SS = fetch_data_word(srcoffset + 2); - } else { /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + } else { /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -849,59 +849,59 @@ void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BTR\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval & ~mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg &= ~mask; - } else { - u16 *srcreg,*shiftreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg &= ~mask; - } + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -921,16 +921,16 @@ void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("LFS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_FS = fetch_data_word(srcoffset + 2); - } else { /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + } else { /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -950,16 +950,16 @@ void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("LGS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_GS = fetch_data_word(srcoffset + 2); - } else { /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + } else { /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -978,51 +978,51 @@ void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("MOVZX\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1044,20 +1044,20 @@ void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("MOVZX\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1078,122 +1078,122 @@ void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) FETCH_DECODE_MODRM(mod, rh, rl); switch (rh) { case 4: - DECODE_PRINTF("BT\t"); - break; + DECODE_PRINTF("BT\t"); + break; case 5: - DECODE_PRINTF("BTS\t"); - break; + DECODE_PRINTF("BTS\t"); + break; case 6: - DECODE_PRINTF("BTR\t"); - break; + DECODE_PRINTF("BTR\t"); + break; case 7: - DECODE_PRINTF("BTC\t"); - break; + DECODE_PRINTF("BTC\t"); + break; default: - DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); - TRACE_REGS(); - printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", - M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); + printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", + M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); + HALT_SYS(); } if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - shift = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", shift); - TRACE_AND_STEP(); - - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, mask; - - bit = shift & 0x1F; - srcval = fetch_data_long(srcoffset); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - switch (rh) { - case 5: - store_data_long(srcoffset, srcval | mask); - break; - case 6: - store_data_long(srcoffset, srcval & ~mask); - break; - case 7: - store_data_long(srcoffset, srcval ^ mask); - break; - default: - break; - } - } else { - u16 srcval, mask; - - bit = shift & 0xF; - srcval = fetch_data_word(srcoffset); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - switch (rh) { - case 5: - store_data_word(srcoffset, srcval | mask); - break; - case 6: - store_data_word(srcoffset, srcval & ~mask); - break; - case 7: - store_data_word(srcoffset, srcval ^ mask); - break; - default: - break; - } - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - shift = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", shift); - TRACE_AND_STEP(); - bit = shift & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - switch (rh) { - case 5: - *srcreg |= mask; - break; - case 6: - *srcreg &= ~mask; - break; - case 7: - *srcreg ^= mask; - break; - default: - break; - } - } else { - u16 *srcreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - shift = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", shift); - TRACE_AND_STEP(); - bit = shift & 0xF; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - switch (rh) { - case 5: - *srcreg |= mask; - break; - case 6: - *srcreg &= ~mask; - break; - case 7: - *srcreg ^= mask; - break; - default: - break; - } - } + srcoffset = decode_rmXX_address(mod, rl); + shift = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", shift); + TRACE_AND_STEP(); + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + shift = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", shift); + TRACE_AND_STEP(); + bit = shift & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } else { + u16 *srcreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + shift = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", shift); + TRACE_AND_STEP(); + bit = shift & 0xF; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1213,59 +1213,59 @@ void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BTC\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval ^ mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg ^= mask; - } else { - u16 *srcreg,*shiftreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg ^= mask; - } + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1284,49 +1284,49 @@ void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BSF\n"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_long(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 32; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_word(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 16; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg, *dstreg; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); - for(*dstreg = 0; *dstreg < 32; (*dstreg)++) - if ((*srcreg >> *dstreg) & 1) break; - } else { - u16 *srcreg, *dstreg; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); - for(*dstreg = 0; *dstreg < 16; (*dstreg)++) - if ((*srcreg >> *dstreg) & 1) break; - } + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg, *dstreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((*srcreg >> *dstreg) & 1) break; + } else { + u16 *srcreg, *dstreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((*srcreg >> *dstreg) & 1) break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1345,49 +1345,49 @@ void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BSF\n"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_long(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 31; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_word(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 15; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg, *dstreg; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); - for(*dstreg = 31; *dstreg > 0; (*dstreg)--) - if ((*srcreg >> *dstreg) & 1) break; - } else { - u16 *srcreg, *dstreg; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); - for(*dstreg = 15; *dstreg > 0; (*dstreg)--) - if ((*srcreg >> *dstreg) & 1) break; - } + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg, *dstreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((*srcreg >> *dstreg) & 1) break; + } else { + u16 *srcreg, *dstreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((*srcreg >> *dstreg) & 1) break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1406,51 +1406,51 @@ void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("MOVSX\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = (s32)((s8)fetch_data_byte(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = (s16)((s8)fetch_data_byte(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = (s32)((s8)*srcreg); - } else { - u16 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = (s16)((s8)*srcreg); - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s8)*srcreg); + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s16)((s8)*srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1472,20 +1472,20 @@ void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("MOVSX\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = (s32)((s16)fetch_data_word(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = (s32)((s16)*srcreg); + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s16)*srcreg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1498,13 +1498,13 @@ void (*x86emu_optab2[256])(u8) __attribute__((section(".got2"))) = { /* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ /* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ -/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ -/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ +/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ +/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ /* 0x04 */ x86emuOp2_illegal_op, /* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ -/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ +/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ /* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ -/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ +/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ /* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */ /* 0x0a */ x86emuOp2_illegal_op, /* 0x0b */ x86emuOp2_illegal_op, diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c index dc8cea80039..e0827d74782 100644 --- a/drivers/bios_emulator/x86emu/prim_ops.c +++ b/drivers/bios_emulator/x86emu/prim_ops.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -14,7 +14,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -28,12 +28,12 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: This file contains the code to implement the primitive -* machine operations used by the emulation code in ops.c +* Description: This file contains the code to implement the primitive +* machine operations used by the emulation code in ops.c * * Carry Chain Calculation * @@ -48,23 +48,23 @@ * So, given the following table, which represents the addition of two * bits, we can derive a formula for the carry chain. * -* a b cin r cout -* 0 0 0 0 0 -* 0 0 1 1 0 -* 0 1 0 1 0 -* 0 1 1 0 1 -* 1 0 0 1 0 -* 1 0 1 0 1 -* 1 1 0 0 1 -* 1 1 1 1 1 +* a b cin r cout +* 0 0 0 0 0 +* 0 0 1 1 0 +* 0 1 0 1 0 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 1 +* 1 1 0 0 1 +* 1 1 1 1 1 * * Construction of table for cout: * * ab -* r \ 00 01 11 10 +* r \ 00 01 11 10 * |------------------ -* 0 | 0 1 1 1 -* 1 | 0 0 1 0 +* 0 | 0 1 1 1 +* 1 | 0 0 1 0 * * By inspection, one gets: cc = ab + r'(a + b) * @@ -75,25 +75,25 @@ * The following table represents the subtraction of two bits, from * which we can derive a formula for the borrow chain. * -* a b bin r bout -* 0 0 0 0 0 -* 0 0 1 1 1 -* 0 1 0 1 1 -* 0 1 1 0 1 -* 1 0 0 1 0 -* 1 0 1 0 0 -* 1 1 0 0 0 -* 1 1 1 1 1 +* a b bin r bout +* 0 0 0 0 0 +* 0 0 1 1 1 +* 0 1 0 1 1 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 0 +* 1 1 0 0 0 +* 1 1 1 1 1 * * Construction of table for cout: * * ab -* r \ 00 01 11 10 +* r \ 00 01 11 10 * |------------------ -* 0 | 0 1 0 0 -* 1 | 1 1 1 0 +* 0 | 0 1 0 0 +* 1 | 1 1 1 0 * -* By inspection, one gets: bc = a'b + r(a' + b) +* By inspection, one gets: bc = a'b + r(a' + b) * ****************************************************************************/ @@ -115,7 +115,7 @@ static u32 x86emu_parity_tab[8] = }; #define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) -#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) +#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) /*----------------------------- Implementation ----------------------------*/ int abs(int v) { @@ -190,7 +190,7 @@ static void calc_carry_chain(int bits, u32 d, u32 s, u32 res, int set_carry) CONDITIONAL_SET_FLAG(XOR2(cc >> (bits - 2)), F_OF); CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); if (set_carry) { - CONDITIONAL_SET_FLAG(res & (1 << bits), F_CF); + CONDITIONAL_SET_FLAG(res & (1 << bits), F_CF); } } @@ -202,7 +202,7 @@ static void calc_borrow_chain(int bits, u32 d, u32 s, u32 res, int set_carry) CONDITIONAL_SET_FLAG(XOR2(bc >> (bits - 2)), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); if (set_carry) { - CONDITIONAL_SET_FLAG(bc & (1 << (bits - 1)), F_CF); + CONDITIONAL_SET_FLAG(bc & (1 << (bits - 1)), F_CF); } } @@ -214,13 +214,13 @@ u16 aaa_word(u16 d) { u16 res; if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { - d += 0x6; - d += 0x100; - SET_FLAG(F_AF); - SET_FLAG(F_CF); + d += 0x6; + d += 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); } res = (u16)(d & 0xFF0F); set_szp_flags_16(res); @@ -235,13 +235,13 @@ u16 aas_word(u16 d) { u16 res; if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { - d -= 0x6; - d -= 0x100; - SET_FLAG(F_AF); - SET_FLAG(F_CF); + d -= 0x6; + d -= 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); } res = (u16)(d & 0xFF0F); set_szp_flags_16(res); @@ -308,7 +308,7 @@ u16 adc_word(u16 d, u16 s) res = d + s; if (ACCESS_FLAG(F_CF)) - res++; + res++; set_szp_flags_16((u16)res); calc_carry_chain(16,s,d,res,1); @@ -330,8 +330,8 @@ u32 adc_long(u32 d, u32 s) res = d + s; if (ACCESS_FLAG(F_CF)) { - lo++; - res++; + lo++; + res++; } hi = (lo >> 16) + (d >> 16) + (s >> 16); @@ -485,12 +485,12 @@ u8 daa_byte(u8 d) { u32 res = d; if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { - res += 6; - SET_FLAG(F_AF); + res += 6; + SET_FLAG(F_AF); } if (res > 0x9F || ACCESS_FLAG(F_CF)) { - res += 0x60; - SET_FLAG(F_CF); + res += 0x60; + SET_FLAG(F_CF); } set_szp_flags_8((u8)res); return (u8)res; @@ -503,12 +503,12 @@ Implements the DAS instruction and side effects. u8 das_byte(u8 d) { if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { - d -= 6; - SET_FLAG(F_AF); + d -= 6; + SET_FLAG(F_AF); } if (d > 0x9F || ACCESS_FLAG(F_CF)) { - d -= 0x60; - SET_FLAG(F_CF); + d -= 0x60; + SET_FLAG(F_CF); } set_szp_flags_8(d); return d; @@ -749,45 +749,45 @@ u8 rcl_byte(u8 d, u8 s) original values, this can be expressed as: IF n > 0 - 1) CF <- b_(8-n) + 1) CF <- b_(8-n) 2) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 3) B_(n-1) <- cf 4) B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ res = d; if ((cnt = s % 9) != 0) { - /* extract the new CARRY FLAG. */ - /* CF <- b_(8-n) */ - cf = (d >> (8 - cnt)) & 0x1; - - /* get the low stuff which rotated - into the range B_7 .. B_cnt */ - /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ - /* note that the right hand side done by the mask */ - res = (d << cnt) & 0xff; - - /* now the high stuff which rotated around - into the positions B_cnt-2 .. B_0 */ - /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ - /* shift it downward, 7-(n-2) = 9-n positions. - and mask off the result before or'ing in. - */ - mask = (1 << (cnt - 1)) - 1; - res |= (d >> (9 - cnt)) & mask; - - /* if the carry flag was set, or it in. */ - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - /* B_(n-1) <- cf */ - res |= 1 << (cnt - 1); - } - /* set the new carry flag, based on the variable "cf" */ - CONDITIONAL_SET_FLAG(cf, F_CF); - /* OVERFLOW is set *IFF* cnt==1, then it is the - xor of CF and the most significant bit. Blecck. */ - /* parenthesized this expression since it appears to - be causing OF to be misset */ - CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), - F_OF); + /* extract the new CARRY FLAG. */ + /* CF <- b_(8-n) */ + cf = (d >> (8 - cnt)) & 0x1; + + /* get the low stuff which rotated + into the range B_7 .. B_cnt */ + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ + /* note that the right hand side done by the mask */ + res = (d << cnt) & 0xff; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (9 - cnt)) & mask; + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(n-1) <- cf */ + res |= 1 << (cnt - 1); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized this expression since it appears to + be causing OF to be misset */ + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), + F_OF); } return (u8)res; @@ -803,16 +803,16 @@ u16 rcl_word(u16 d, u8 s) res = d; if ((cnt = s % 17) != 0) { - cf = (d >> (16 - cnt)) & 0x1; - res = (d << cnt) & 0xffff; - mask = (1 << (cnt - 1)) - 1; - res |= (d >> (17 - cnt)) & mask; - if (ACCESS_FLAG(F_CF)) { - res |= 1 << (cnt - 1); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), - F_OF); + cf = (d >> (16 - cnt)) & 0x1; + res = (d << cnt) & 0xffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (17 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), + F_OF); } return (u16)res; } @@ -827,16 +827,16 @@ u32 rcl_long(u32 d, u8 s) res = d; if ((cnt = s % 33) != 0) { - cf = (d >> (32 - cnt)) & 0x1; - res = (d << cnt) & 0xffffffff; - mask = (1 << (cnt - 1)) - 1; - res |= (d >> (33 - cnt)) & mask; - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - res |= 1 << (cnt - 1); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), - F_OF); + cf = (d >> (32 - cnt)) & 0x1; + res = (d << cnt) & 0xffffffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (33 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), + F_OF); } return res; } @@ -867,60 +867,60 @@ u8 rcr_byte(u8 d, u8 s) original values, this can be expressed as: IF n > 0 - 1) CF <- b_(n-1) - 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 1) CF <- b_(n-1) + 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) 3) B_(8-n) <- cf 4) B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ res = d; if ((cnt = s % 9) != 0) { - /* extract the new CARRY FLAG. */ - /* CF <- b_(n-1) */ - if (cnt == 1) { - cf = d & 0x1; - /* note hackery here. Access_flag(..) evaluates to either - 0 if flag not set - non-zero if flag is set. - doing access_flag(..) != 0 casts that into either - 0..1 in any representation of the flags register - (i.e. packed bit array or unpacked.) - */ - ocf = ACCESS_FLAG(F_CF) != 0; - } else - cf = (d >> (cnt - 1)) & 0x1; - - /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ - /* note that the right hand side done by the mask - This is effectively done by shifting the - object to the right. The result must be masked, - in case the object came in and was treated - as a negative number. Needed??? */ - - mask = (1 << (8 - cnt)) - 1; - res = (d >> cnt) & mask; - - /* now the high stuff which rotated around - into the positions B_cnt-2 .. B_0 */ - /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ - /* shift it downward, 7-(n-2) = 9-n positions. - and mask off the result before or'ing in. - */ - res |= (d << (9 - cnt)); - - /* if the carry flag was set, or it in. */ - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - /* B_(8-n) <- cf */ - res |= 1 << (8 - cnt); - } - /* set the new carry flag, based on the variable "cf" */ - CONDITIONAL_SET_FLAG(cf, F_CF); - /* OVERFLOW is set *IFF* cnt==1, then it is the - xor of CF and the most significant bit. Blecck. */ - /* parenthesized... */ - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), - F_OF); - } + /* extract the new CARRY FLAG. */ + /* CF <- b_(n-1) */ + if (cnt == 1) { + cf = d & 0x1; + /* note hackery here. Access_flag(..) evaluates to either + 0 if flag not set + non-zero if flag is set. + doing access_flag(..) != 0 casts that into either + 0..1 in any representation of the flags register + (i.e. packed bit array or unpacked.) + */ + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ + /* note that the right hand side done by the mask + This is effectively done by shifting the + object to the right. The result must be masked, + in case the object came in and was treated + as a negative number. Needed??? */ + + mask = (1 << (8 - cnt)) - 1; + res = (d >> cnt) & mask; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + res |= (d << (9 - cnt)); + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(8-n) <- cf */ + res |= 1 << (8 - cnt); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized... */ + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), + F_OF); + } } return (u8)res; } @@ -937,22 +937,22 @@ u16 rcr_word(u16 d, u8 s) /* rotate right through carry */ res = d; if ((cnt = s % 17) != 0) { - if (cnt == 1) { - cf = d & 0x1; - ocf = ACCESS_FLAG(F_CF) != 0; - } else - cf = (d >> (cnt - 1)) & 0x1; - mask = (1 << (16 - cnt)) - 1; - res = (d >> cnt) & mask; - res |= (d << (17 - cnt)); - if (ACCESS_FLAG(F_CF)) { - res |= 1 << (16 - cnt); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), - F_OF); - } + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (16 - cnt)) - 1; + res = (d >> cnt) & mask; + res |= (d << (17 - cnt)); + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (16 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), + F_OF); + } } return (u16)res; } @@ -969,23 +969,23 @@ u32 rcr_long(u32 d, u8 s) /* rotate right through carry */ res = d; if ((cnt = s % 33) != 0) { - if (cnt == 1) { - cf = d & 0x1; - ocf = ACCESS_FLAG(F_CF) != 0; - } else - cf = (d >> (cnt - 1)) & 0x1; - mask = (1 << (32 - cnt)) - 1; - res = (d >> cnt) & mask; - if (cnt != 1) - res |= (d << (33 - cnt)); - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - res |= 1 << (32 - cnt); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), - F_OF); - } + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (32 - cnt)) - 1; + res = (d >> cnt) & mask; + if (cnt != 1) + res |= (d << (33 - cnt)); + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (32 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), + F_OF); + } } return res; } @@ -1016,25 +1016,25 @@ u8 rol_byte(u8 d, u8 s) */ res = d; if ((cnt = s % 8) != 0) { - /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ - res = (d << cnt); - - /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ - mask = (1 << cnt) - 1; - res |= (d >> (8 - cnt)) & mask; - - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - /* OVERFLOW is set *IFF* s==1, then it is the - xor of CF and the most significant bit. Blecck. */ - CONDITIONAL_SET_FLAG(s == 1 && - XOR2((res & 0x1) + ((res >> 6) & 0x2)), - F_OF); + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ + res = (d << cnt); + + /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ + mask = (1 << cnt) - 1; + res |= (d >> (8 - cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of CF and the most significant bit. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 6) & 0x2)), + F_OF); } if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); } return (u8)res; } @@ -1049,17 +1049,17 @@ u16 rol_word(u16 d, u8 s) res = d; if ((cnt = s % 16) != 0) { - res = (d << cnt); - mask = (1 << cnt) - 1; - res |= (d >> (16 - cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && - XOR2((res & 0x1) + ((res >> 14) & 0x2)), - F_OF); + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (16 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 14) & 0x2)), + F_OF); } if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); } return (u16)res; } @@ -1074,17 +1074,17 @@ u32 rol_long(u32 d, u8 s) res = d; if ((cnt = s % 32) != 0) { - res = (d << cnt); - mask = (1 << cnt) - 1; - res |= (d >> (32 - cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && - XOR2((res & 0x1) + ((res >> 30) & 0x2)), - F_OF); + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (32 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 30) & 0x2)), + F_OF); } if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); } return res; } @@ -1109,28 +1109,28 @@ u8 ror_byte(u8 d, u8 s) The rotate is done mod 8. IF n > 0 - 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) 2) B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ res = d; - if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ - /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ - res = (d << (8 - cnt)); - - /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ - mask = (1 << (8 - cnt)) - 1; - res |= (d >> (cnt)) & mask; - - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x80, F_CF); - /* OVERFLOW is set *IFF* s==1, then it is the - xor of the two most significant bits. Blecck. */ - CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); + if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ + /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ + res = (d << (8 - cnt)); + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ + mask = (1 << (8 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of the two most significant bits. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); } else if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); } return (u8)res; } @@ -1145,15 +1145,15 @@ u16 ror_word(u16 d, u8 s) res = d; if ((cnt = s % 16) != 0) { - res = (d << (16 - cnt)); - mask = (1 << (16 - cnt)) - 1; - res |= (d >> (cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); + res = (d << (16 - cnt)); + mask = (1 << (16 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); } else if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); } return (u16)res; } @@ -1168,15 +1168,15 @@ u32 ror_long(u32 d, u8 s) res = d; if ((cnt = s % 32) != 0) { - res = (d << (32 - cnt)); - mask = (1 << (32 - cnt)) - 1; - res |= (d >> (cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); + res = (d << (32 - cnt)); + mask = (1 << (32 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); } else if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); } return res; } @@ -1190,35 +1190,35 @@ u8 shl_byte(u8 d, u8 s) unsigned int cnt, res, cf; if (s < 8) { - cnt = s % 8; - - /* last bit shifted out goes into carry flag */ - if (cnt > 0) { - res = d << cnt; - cf = d & (1 << (8 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_8((u8)res); - } else { - res = (u8) d; - } - - if (cnt == 1) { - /* Needs simplification. */ - CONDITIONAL_SET_FLAG( - (((res & 0x80) == 0x80) ^ - (ACCESS_FLAG(F_CF) != 0)), - /* was (M.x86.R_FLG&F_CF)==F_CF)), */ - F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 8; + + /* last bit shifted out goes into carry flag */ + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (8 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_8((u8)res); + } else { + res = (u8) d; + } + + if (cnt == 1) { + /* Needs simplification. */ + CONDITIONAL_SET_FLAG( + (((res & 0x80) == 0x80) ^ + (ACCESS_FLAG(F_CF) != 0)), + /* was (M.x86.R_FLG&F_CF)==F_CF)), */ + F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return (u8)res; } @@ -1232,31 +1232,31 @@ u16 shl_word(u16 d, u8 s) unsigned int cnt, res, cf; if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - res = d << cnt; - cf = d & (1 << (16 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_16((u16)res); - } else { - res = (u16) d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG( - (((res & 0x8000) == 0x8000) ^ - (ACCESS_FLAG(F_CF) != 0)), - F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 16; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = (u16) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG( + (((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), + F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return (u16)res; } @@ -1270,28 +1270,28 @@ u32 shl_long(u32 d, u8 s) unsigned int cnt, res, cf; if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - res = d << cnt; - cf = d & (1 << (32 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_32((u32)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ - (ACCESS_FLAG(F_CF) != 0)), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 32; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return res; } @@ -1305,28 +1305,28 @@ u8 shr_byte(u8 d, u8 s) unsigned int cnt, res, cf; if (s < 8) { - cnt = s % 8; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = d >> cnt; - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_8((u8)res); - } else { - res = (u8) d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 8; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_8((u8)res); + } else { + res = (u8) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return (u8)res; } @@ -1340,28 +1340,28 @@ u16 shr_word(u16 d, u8 s) unsigned int cnt, res, cf; if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = d >> cnt; - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_16((u16)res); - } else { - res = d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); } return (u16)res; } @@ -1375,27 +1375,27 @@ u32 shr_long(u32 d, u8 s) unsigned int cnt, res, cf; if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = d >> cnt; - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_32((u32)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); } return res; } @@ -1412,28 +1412,28 @@ u8 sar_byte(u8 d, u8 s) sf = d & 0x80; cnt = s % 8; if (cnt > 0 && cnt < 8) { - mask = (1 << (8 - cnt)) - 1; - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) & mask; - CONDITIONAL_SET_FLAG(cf, F_CF); - if (sf) { - res |= ~mask; - } - set_szp_flags_8((u8)res); + mask = (1 << (8 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + set_szp_flags_8((u8)res); } else if (cnt >= 8) { - if (sf) { - res = 0xff; - SET_FLAG(F_CF); - CLEAR_FLAG(F_ZF); - SET_FLAG(F_SF); - SET_FLAG(F_PF); - } else { - res = 0; - CLEAR_FLAG(F_CF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } + if (sf) { + res = 0xff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } } return (u8)res; } @@ -1450,28 +1450,28 @@ u16 sar_word(u16 d, u8 s) cnt = s % 16; res = d; if (cnt > 0 && cnt < 16) { - mask = (1 << (16 - cnt)) - 1; - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) & mask; - CONDITIONAL_SET_FLAG(cf, F_CF); - if (sf) { - res |= ~mask; - } - set_szp_flags_16((u16)res); + mask = (1 << (16 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + set_szp_flags_16((u16)res); } else if (cnt >= 16) { - if (sf) { - res = 0xffff; - SET_FLAG(F_CF); - CLEAR_FLAG(F_ZF); - SET_FLAG(F_SF); - SET_FLAG(F_PF); - } else { - res = 0; - CLEAR_FLAG(F_CF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } + if (sf) { + res = 0xffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } } return (u16)res; } @@ -1488,28 +1488,28 @@ u32 sar_long(u32 d, u8 s) cnt = s % 32; res = d; if (cnt > 0 && cnt < 32) { - mask = (1 << (32 - cnt)) - 1; - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) & mask; - CONDITIONAL_SET_FLAG(cf, F_CF); - if (sf) { - res |= ~mask; - } - set_szp_flags_32(res); + mask = (1 << (32 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + set_szp_flags_32(res); } else if (cnt >= 32) { - if (sf) { - res = 0xffffffff; - SET_FLAG(F_CF); - CLEAR_FLAG(F_ZF); - SET_FLAG(F_SF); - SET_FLAG(F_PF); - } else { - res = 0; - CLEAR_FLAG(F_CF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } + if (sf) { + res = 0xffffffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } } return res; } @@ -1523,28 +1523,28 @@ u16 shld_word (u16 d, u16 fill, u8 s) unsigned int cnt, res, cf; if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - res = (d << cnt) | (fill >> (16-cnt)); - cf = d & (1 << (16 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_16((u16)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ - (ACCESS_FLAG(F_CF) != 0)), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 16; + if (cnt > 0) { + res = (d << cnt) | (fill >> (16-cnt)); + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return (u16)res; } @@ -1558,28 +1558,28 @@ u32 shld_long (u32 d, u32 fill, u8 s) unsigned int cnt, res, cf; if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - res = (d << cnt) | (fill >> (32-cnt)); - cf = d & (1 << (32 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_32((u32)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ - (ACCESS_FLAG(F_CF) != 0)), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 32; + if (cnt > 0) { + res = (d << cnt) | (fill >> (32-cnt)); + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return res; } @@ -1593,28 +1593,28 @@ u16 shrd_word (u16 d, u16 fill, u8 s) unsigned int cnt, res, cf; if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) | (fill << (16 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_16((u16)res); - } else { - res = d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); } return (u16)res; } @@ -1628,27 +1628,27 @@ u32 shrd_long (u32 d, u32 fill, u8 s) unsigned int cnt, res, cf; if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) | (fill << (32 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_32((u32)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); } return res; } @@ -1663,9 +1663,9 @@ u8 sbb_byte(u8 d, u8 s) u32 bc; if (ACCESS_FLAG(F_CF)) - res = d - s - 1; + res = d - s - 1; else - res = d - s; + res = d - s; set_szp_flags_8((u8)res); /* calculate the borrow chain. See note at top */ @@ -1686,9 +1686,9 @@ u16 sbb_word(u16 d, u16 s) u32 bc; if (ACCESS_FLAG(F_CF)) - res = d - s - 1; + res = d - s - 1; else - res = d - s; + res = d - s; set_szp_flags_16((u16)res); /* calculate the borrow chain. See note at top */ @@ -1709,9 +1709,9 @@ u32 sbb_long(u32 d, u32 s) u32 bc; if (ACCESS_FLAG(F_CF)) - res = d - s - 1; + res = d - s - 1; else - res = d - s; + res = d - s; set_szp_flags_32(res); @@ -1880,12 +1880,12 @@ void imul_byte(u8 s) M.x86.R_AX = res; if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) || - ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } } @@ -1900,12 +1900,12 @@ void imul_word(u16 s) M.x86.R_AX = (u16)res; M.x86.R_DX = (u16)(res >> 16); if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x0000) || - ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFFFF)) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFFFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } } @@ -1915,7 +1915,7 @@ Implements the IMUL instruction and side effects. ****************************************************************************/ void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) { -#ifdef __HAS_LONG_LONG__ +#ifdef __HAS_LONG_LONG__ s64 res = (s32)d * (s32)s; *res_lo = (u32)res; @@ -1926,11 +1926,11 @@ void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) u32 rlo_lo,rlo_hi,rhi_lo; if ((d_sign = d & 0x80000000) != 0) - d = -d; + d = -d; d_lo = d & 0xFFFF; d_hi = d >> 16; if ((s_sign = s & 0x80000000) != 0) - s = -s; + s = -s; s_lo = s & 0xFFFF; s_hi = s >> 16; rlo_lo = d_lo * s_lo; @@ -1939,11 +1939,11 @@ void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) *res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF); *res_hi = rhi_lo; if (d_sign != s_sign) { - d = ~*res_lo; - s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); - *res_lo = ~*res_lo+1; - *res_hi = ~*res_hi+(s >> 16); - } + d = ~*res_lo; + s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); + *res_lo = ~*res_lo+1; + *res_hi = ~*res_hi+(s >> 16); + } #endif } @@ -1955,12 +1955,12 @@ void imul_long(u32 s) { imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00000000) || - ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFFFFFFFF)) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFFFFFFFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } } @@ -1974,11 +1974,11 @@ void mul_byte(u8 s) M.x86.R_AX = res; if (M.x86.R_AH == 0) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } } @@ -1993,11 +1993,11 @@ void mul_word(u16 s) M.x86.R_AX = (u16)res; M.x86.R_DX = (u16)(res >> 16); if (M.x86.R_DX == 0) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } } @@ -2007,7 +2007,7 @@ Implements the MUL instruction and side effects. ****************************************************************************/ void mul_long(u32 s) { -#ifdef __HAS_LONG_LONG__ +#ifdef __HAS_LONG_LONG__ u64 res = (u32)M.x86.R_EAX * (u32)s; M.x86.R_EAX = (u32)res; @@ -2029,11 +2029,11 @@ void mul_long(u32 s) M.x86.R_EDX = rhi_lo; #endif if (M.x86.R_EDX == 0) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } } @@ -2047,14 +2047,14 @@ void idiv_byte(u8 s) dvd = (s16)M.x86.R_AX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (s8)s; mod = dvd % (s8)s; if (abs(div) > 0x7f) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } M.x86.R_AL = (s8) div; M.x86.R_AH = (s8) mod; @@ -2070,14 +2070,14 @@ void idiv_word(u16 s) dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (s16)s; mod = dvd % (s16)s; if (abs(div) > 0x7fff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } CLEAR_FLAG(F_CF); CLEAR_FLAG(F_SF); @@ -2094,19 +2094,19 @@ Implements the IDIV instruction and side effects. ****************************************************************************/ void idiv_long(u32 s) { -#ifdef __HAS_LONG_LONG__ +#ifdef __HAS_LONG_LONG__ s64 dvd, div, mod; dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (s32)s; mod = dvd % (s32)s; if (abs(div) > 0x7fffffff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } #else s32 div = 0, mod; @@ -2120,32 +2120,32 @@ void idiv_long(u32 s) int carry; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } do { - div <<= 1; - carry = (l_dvd >= l_s) ? 0 : 1; - - if (abs_h_dvd < (h_s + carry)) { - h_s >>= 1; - l_s = abs_s << (--counter); - continue; - } else { - abs_h_dvd -= (h_s + carry); - l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) - : (l_dvd - l_s); - h_s >>= 1; - l_s = abs_s << (--counter); - div |= 1; - continue; - } + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (abs_h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = abs_s << (--counter); + continue; + } else { + abs_h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = abs_s << (--counter); + div |= 1; + continue; + } } while (counter > -1); /* overflow */ if (abs_h_dvd || (l_dvd > abs_s)) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } /* sign */ div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000)); @@ -2172,14 +2172,14 @@ void div_byte(u8 s) dvd = M.x86.R_AX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (u8)s; mod = dvd % (u8)s; if (abs(div) > 0xff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } M.x86.R_AL = (u8)div; M.x86.R_AH = (u8)mod; @@ -2195,14 +2195,14 @@ void div_word(u16 s) dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (u16)s; mod = dvd % (u16)s; if (abs(div) > 0xffff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } CLEAR_FLAG(F_CF); CLEAR_FLAG(F_SF); @@ -2219,19 +2219,19 @@ Implements the DIV instruction and side effects. ****************************************************************************/ void div_long(u32 s) { -#ifdef __HAS_LONG_LONG__ +#ifdef __HAS_LONG_LONG__ u64 dvd, div, mod; dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (u32)s; mod = dvd % (u32)s; if (abs(div) > 0xffffffff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } #else s32 div = 0, mod; @@ -2244,32 +2244,32 @@ void div_long(u32 s) int carry; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } do { - div <<= 1; - carry = (l_dvd >= l_s) ? 0 : 1; - - if (h_dvd < (h_s + carry)) { - h_s >>= 1; - l_s = s << (--counter); - continue; - } else { - h_dvd -= (h_s + carry); - l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) - : (l_dvd - l_s); - h_s >>= 1; - l_s = s << (--counter); - div |= 1; - continue; - } + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = s << (--counter); + continue; + } else { + h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = s << (--counter); + div |= 1; + continue; + } } while (counter > -1); /* overflow */ if (h_dvd || (l_dvd > s)) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } mod = l_dvd; #endif @@ -2291,11 +2291,11 @@ Implements the IN string instruction and side effects. static void single_in(int size) { if(size == 1) - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inb)(M.x86.R_DX)); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inb)(M.x86.R_DX)); else if (size == 2) - store_data_word_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inw)(M.x86.R_DX)); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inw)(M.x86.R_DX)); else - store_data_long_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inl)(M.x86.R_DX)); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inl)(M.x86.R_DX)); } void ins(int size) @@ -2303,26 +2303,26 @@ void ins(int size) int inc = size; if (ACCESS_FLAG(F_DF)) { - inc = -size; + inc = -size; } if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* in until CX is ZERO. */ - u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? - M.x86.R_ECX : M.x86.R_CX); - - while (count--) { - single_in(size); - M.x86.R_DI += inc; - } - M.x86.R_CX = 0; - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ECX = 0; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* in until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + + while (count--) { + single_in(size); + M.x86.R_DI += inc; + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - single_in(size); - M.x86.R_DI += inc; + single_in(size); + M.x86.R_DI += inc; } } @@ -2346,31 +2346,31 @@ void outs(int size) int inc = size; if (ACCESS_FLAG(F_DF)) { - inc = -size; + inc = -size; } if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* out until CX is ZERO. */ - u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? - M.x86.R_ECX : M.x86.R_CX); - while (count--) { - single_out(size); - M.x86.R_SI += inc; - } - M.x86.R_CX = 0; - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ECX = 0; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* out until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + while (count--) { + single_out(size); + M.x86.R_SI += inc; + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - single_out(size); - M.x86.R_SI += inc; + single_out(size); + M.x86.R_SI += inc; } } /**************************************************************************** PARAMETERS: -addr - Address to fetch word from +addr - Address to fetch word from REMARKS: Fetches a word from emulator memory using an absolute address. @@ -2443,4 +2443,3 @@ DB( if (CHECK_SP_ACCESS()) M.x86.R_SP += 4; return res; } - diff --git a/include/radeon.h b/include/radeon.h index f4e24a7134b..3d11b0572b2 100644 --- a/include/radeon.h +++ b/include/radeon.h @@ -5,971 +5,971 @@ #define RADEON_REGSIZE 0x4000 -#define MM_INDEX 0x0000 -#define MM_DATA 0x0004 -#define BUS_CNTL 0x0030 -#define HI_STAT 0x004C -#define BUS_CNTL1 0x0034 -#define I2C_CNTL_1 0x0094 -#define CONFIG_CNTL 0x00E0 -#define CONFIG_MEMSIZE 0x00F8 -#define CONFIG_APER_0_BASE 0x0100 -#define CONFIG_APER_1_BASE 0x0104 -#define CONFIG_APER_SIZE 0x0108 -#define CONFIG_REG_1_BASE 0x010C -#define CONFIG_REG_APER_SIZE 0x0110 -#define PAD_AGPINPUT_DELAY 0x0164 -#define PAD_CTLR_STRENGTH 0x0168 -#define PAD_CTLR_UPDATE 0x016C -#define PAD_CTLR_MISC 0x0aa0 -#define AGP_CNTL 0x0174 -#define BM_STATUS 0x0160 -#define CAP0_TRIG_CNTL 0x0950 -#define CAP1_TRIG_CNTL 0x09c0 -#define VIPH_CONTROL 0x0C40 -#define VENDOR_ID 0x0F00 -#define DEVICE_ID 0x0F02 -#define COMMAND 0x0F04 -#define STATUS 0x0F06 -#define REVISION_ID 0x0F08 -#define REGPROG_INF 0x0F09 -#define SUB_CLASS 0x0F0A -#define BASE_CODE 0x0F0B -#define CACHE_LINE 0x0F0C -#define LATENCY 0x0F0D -#define HEADER 0x0F0E -#define BIST 0x0F0F -#define REG_MEM_BASE 0x0F10 -#define REG_IO_BASE 0x0F14 -#define REG_REG_BASE 0x0F18 -#define ADAPTER_ID 0x0F2C -#define BIOS_ROM 0x0F30 -#define CAPABILITIES_PTR 0x0F34 -#define INTERRUPT_LINE 0x0F3C -#define INTERRUPT_PIN 0x0F3D -#define MIN_GRANT 0x0F3E -#define MAX_LATENCY 0x0F3F -#define ADAPTER_ID_W 0x0F4C -#define PMI_CAP_ID 0x0F50 -#define PMI_NXT_CAP_PTR 0x0F51 -#define PMI_PMC_REG 0x0F52 -#define PM_STATUS 0x0F54 -#define PMI_DATA 0x0F57 -#define AGP_CAP_ID 0x0F58 -#define AGP_STATUS 0x0F5C -#define AGP_COMMAND 0x0F60 -#define AIC_CTRL 0x01D0 -#define AIC_STAT 0x01D4 -#define AIC_PT_BASE 0x01D8 -#define AIC_LO_ADDR 0x01DC -#define AIC_HI_ADDR 0x01E0 -#define AIC_TLB_ADDR 0x01E4 -#define AIC_TLB_DATA 0x01E8 -#define DAC_CNTL 0x0058 -#define DAC_CNTL2 0x007c -#define CRTC_GEN_CNTL 0x0050 -#define MEM_CNTL 0x0140 -#define MC_CNTL 0x0140 -#define EXT_MEM_CNTL 0x0144 -#define MC_TIMING_CNTL 0x0144 -#define MC_AGP_LOCATION 0x014C -#define MEM_IO_CNTL_A0 0x0178 -#define MEM_REFRESH_CNTL 0x0178 -#define MEM_INIT_LATENCY_TIMER 0x0154 -#define MC_INIT_GFX_LAT_TIMER 0x0154 -#define MEM_SDRAM_MODE_REG 0x0158 -#define AGP_BASE 0x0170 -#define MEM_IO_CNTL_A1 0x017C -#define MC_READ_CNTL_AB 0x017C -#define MEM_IO_CNTL_B0 0x0180 -#define MC_INIT_MISC_LAT_TIMER 0x0180 -#define MEM_IO_CNTL_B1 0x0184 -#define MC_IOPAD_CNTL 0x0184 -#define MC_DEBUG 0x0188 -#define MC_STATUS 0x0150 -#define MEM_IO_OE_CNTL 0x018C -#define MC_CHIP_IO_OE_CNTL_AB 0x018C -#define MC_FB_LOCATION 0x0148 -//#define MC_FB_LOCATION 0x0188 -#define HOST_PATH_CNTL 0x0130 -#define MEM_VGA_WP_SEL 0x0038 -#define MEM_VGA_RP_SEL 0x003C -#define HDP_DEBUG 0x0138 -#define SW_SEMAPHORE 0x013C -#define CRTC2_GEN_CNTL 0x03f8 -#define CRTC2_DISPLAY_BASE_ADDR 0x033c -#define SURFACE_CNTL 0x0B00 -#define SURFACE0_LOWER_BOUND 0x0B04 -#define SURFACE1_LOWER_BOUND 0x0B14 -#define SURFACE2_LOWER_BOUND 0x0B24 -#define SURFACE3_LOWER_BOUND 0x0B34 -#define SURFACE4_LOWER_BOUND 0x0B44 -#define SURFACE5_LOWER_BOUND 0x0B54 -#define SURFACE6_LOWER_BOUND 0x0B64 -#define SURFACE7_LOWER_BOUND 0x0B74 -#define SURFACE0_UPPER_BOUND 0x0B08 -#define SURFACE1_UPPER_BOUND 0x0B18 -#define SURFACE2_UPPER_BOUND 0x0B28 -#define SURFACE3_UPPER_BOUND 0x0B38 -#define SURFACE4_UPPER_BOUND 0x0B48 -#define SURFACE5_UPPER_BOUND 0x0B58 -#define SURFACE6_UPPER_BOUND 0x0B68 -#define SURFACE7_UPPER_BOUND 0x0B78 -#define SURFACE0_INFO 0x0B0C -#define SURFACE1_INFO 0x0B1C -#define SURFACE2_INFO 0x0B2C -#define SURFACE3_INFO 0x0B3C -#define SURFACE4_INFO 0x0B4C -#define SURFACE5_INFO 0x0B5C -#define SURFACE6_INFO 0x0B6C -#define SURFACE7_INFO 0x0B7C -#define SURFACE_ACCESS_FLAGS 0x0BF8 -#define SURFACE_ACCESS_CLR 0x0BFC -#define GEN_INT_CNTL 0x0040 -#define GEN_INT_STATUS 0x0044 -#define CRTC_EXT_CNTL 0x0054 -#define RB3D_CNTL 0x1C3C -#define WAIT_UNTIL 0x1720 -#define ISYNC_CNTL 0x1724 -#define RBBM_GUICNTL 0x172C -#define RBBM_STATUS 0x0E40 -#define RBBM_STATUS_alt_1 0x1740 -#define RBBM_CNTL 0x00EC -#define RBBM_CNTL_alt_1 0x0E44 -#define RBBM_SOFT_RESET 0x00F0 -#define RBBM_SOFT_RESET_alt_1 0x0E48 -#define NQWAIT_UNTIL 0x0E50 -#define RBBM_DEBUG 0x0E6C -#define RBBM_CMDFIFO_ADDR 0x0E70 -#define RBBM_CMDFIFO_DATAL 0x0E74 -#define RBBM_CMDFIFO_DATAH 0x0E78 -#define RBBM_CMDFIFO_STAT 0x0E7C -#define CRTC_STATUS 0x005C -#define GPIO_VGA_DDC 0x0060 -#define GPIO_DVI_DDC 0x0064 -#define GPIO_MONID 0x0068 -#define GPIO_CRT2_DDC 0x006c -#define PALETTE_INDEX 0x00B0 -#define PALETTE_DATA 0x00B4 -#define PALETTE_30_DATA 0x00B8 -#define CRTC_H_TOTAL_DISP 0x0200 -#define CRTC_H_SYNC_STRT_WID 0x0204 -#define CRTC_V_TOTAL_DISP 0x0208 -#define CRTC_V_SYNC_STRT_WID 0x020C -#define CRTC_VLINE_CRNT_VLINE 0x0210 -#define CRTC_CRNT_FRAME 0x0214 -#define CRTC_GUI_TRIG_VLINE 0x0218 -#define CRTC_DEBUG 0x021C -#define CRTC_OFFSET_RIGHT 0x0220 -#define CRTC_OFFSET 0x0224 -#define CRTC_OFFSET_CNTL 0x0228 -#define CRTC_PITCH 0x022C -#define OVR_CLR 0x0230 -#define OVR_WID_LEFT_RIGHT 0x0234 -#define OVR_WID_TOP_BOTTOM 0x0238 -#define DISPLAY_BASE_ADDR 0x023C -#define SNAPSHOT_VH_COUNTS 0x0240 -#define SNAPSHOT_F_COUNT 0x0244 -#define N_VIF_COUNT 0x0248 -#define SNAPSHOT_VIF_COUNT 0x024C -#define FP_CRTC_H_TOTAL_DISP 0x0250 -#define FP_CRTC_V_TOTAL_DISP 0x0254 -#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 -#define CRT_CRTC_V_SYNC_STRT_WID 0x025C -#define CUR_OFFSET 0x0260 -#define CUR_HORZ_VERT_POSN 0x0264 -#define CUR_HORZ_VERT_OFF 0x0268 -#define CUR_CLR0 0x026C -#define CUR_CLR1 0x0270 -#define FP_HORZ_VERT_ACTIVE 0x0278 -#define CRTC_MORE_CNTL 0x027C -#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) -#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) -#define DAC_EXT_CNTL 0x0280 -#define FP_GEN_CNTL 0x0284 -#define FP_HORZ_STRETCH 0x028C -#define FP_VERT_STRETCH 0x0290 -#define FP_H_SYNC_STRT_WID 0x02C4 -#define FP_V_SYNC_STRT_WID 0x02C8 -#define AUX_WINDOW_HORZ_CNTL 0x02D8 -#define AUX_WINDOW_VERT_CNTL 0x02DC -//#define DDA_CONFIG 0x02e0 -//#define DDA_ON_OFF 0x02e4 -#define DVI_I2C_CNTL_1 0x02e4 -#define GRPH_BUFFER_CNTL 0x02F0 -#define GRPH2_BUFFER_CNTL 0x03F0 -#define VGA_BUFFER_CNTL 0x02F4 -#define OV0_Y_X_START 0x0400 -#define OV0_Y_X_END 0x0404 -#define OV0_PIPELINE_CNTL 0x0408 -#define OV0_REG_LOAD_CNTL 0x0410 -#define OV0_SCALE_CNTL 0x0420 -#define OV0_V_INC 0x0424 -#define OV0_P1_V_ACCUM_INIT 0x0428 -#define OV0_P23_V_ACCUM_INIT 0x042C -#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 -#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 -#define OV0_BASE_ADDR 0x043C -#define OV0_VID_BUF0_BASE_ADRS 0x0440 -#define OV0_VID_BUF1_BASE_ADRS 0x0444 -#define OV0_VID_BUF2_BASE_ADRS 0x0448 -#define OV0_VID_BUF3_BASE_ADRS 0x044C -#define OV0_VID_BUF4_BASE_ADRS 0x0450 -#define OV0_VID_BUF5_BASE_ADRS 0x0454 -#define OV0_VID_BUF_PITCH0_VALUE 0x0460 -#define OV0_VID_BUF_PITCH1_VALUE 0x0464 -#define OV0_AUTO_FLIP_CNTRL 0x0470 -#define OV0_DEINTERLACE_PATTERN 0x0474 -#define OV0_SUBMIT_HISTORY 0x0478 -#define OV0_H_INC 0x0480 -#define OV0_STEP_BY 0x0484 -#define OV0_P1_H_ACCUM_INIT 0x0488 -#define OV0_P23_H_ACCUM_INIT 0x048C -#define OV0_P1_X_START_END 0x0494 -#define OV0_P2_X_START_END 0x0498 -#define OV0_P3_X_START_END 0x049C -#define OV0_FILTER_CNTL 0x04A0 -#define OV0_FOUR_TAP_COEF_0 0x04B0 -#define OV0_FOUR_TAP_COEF_1 0x04B4 -#define OV0_FOUR_TAP_COEF_2 0x04B8 -#define OV0_FOUR_TAP_COEF_3 0x04BC -#define OV0_FOUR_TAP_COEF_4 0x04C0 -#define OV0_FLAG_CNTRL 0x04DC -#define OV0_SLICE_CNTL 0x04E0 -#define OV0_VID_KEY_CLR_LOW 0x04E4 -#define OV0_VID_KEY_CLR_HIGH 0x04E8 -#define OV0_GRPH_KEY_CLR_LOW 0x04EC -#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 -#define OV0_KEY_CNTL 0x04F4 -#define OV0_TEST 0x04F8 -#define SUBPIC_CNTL 0x0540 -#define SUBPIC_DEFCOLCON 0x0544 -#define SUBPIC_Y_X_START 0x054C -#define SUBPIC_Y_X_END 0x0550 -#define SUBPIC_V_INC 0x0554 -#define SUBPIC_H_INC 0x0558 -#define SUBPIC_BUF0_OFFSET 0x055C -#define SUBPIC_BUF1_OFFSET 0x0560 -#define SUBPIC_LC0_OFFSET 0x0564 -#define SUBPIC_LC1_OFFSET 0x0568 -#define SUBPIC_PITCH 0x056C -#define SUBPIC_BTN_HLI_COLCON 0x0570 -#define SUBPIC_BTN_HLI_Y_X_START 0x0574 -#define SUBPIC_BTN_HLI_Y_X_END 0x0578 -#define SUBPIC_PALETTE_INDEX 0x057C -#define SUBPIC_PALETTE_DATA 0x0580 -#define SUBPIC_H_ACCUM_INIT 0x0584 -#define SUBPIC_V_ACCUM_INIT 0x0588 -#define DISP_MISC_CNTL 0x0D00 -#define DAC_MACRO_CNTL 0x0D04 -#define DISP_PWR_MAN 0x0D08 -#define DISP_TEST_DEBUG_CNTL 0x0D10 -#define DISP_HW_DEBUG 0x0D14 -#define DAC_CRC_SIG1 0x0D18 -#define DAC_CRC_SIG2 0x0D1C -#define OV0_LIN_TRANS_A 0x0D20 -#define OV0_LIN_TRANS_B 0x0D24 -#define OV0_LIN_TRANS_C 0x0D28 -#define OV0_LIN_TRANS_D 0x0D2C -#define OV0_LIN_TRANS_E 0x0D30 -#define OV0_LIN_TRANS_F 0x0D34 -#define OV0_GAMMA_0_F 0x0D40 -#define OV0_GAMMA_10_1F 0x0D44 -#define OV0_GAMMA_20_3F 0x0D48 -#define OV0_GAMMA_40_7F 0x0D4C -#define OV0_GAMMA_380_3BF 0x0D50 -#define OV0_GAMMA_3C0_3FF 0x0D54 -#define DISP_MERGE_CNTL 0x0D60 -#define DISP_OUTPUT_CNTL 0x0D64 -#define DISP_LIN_TRANS_GRPH_A 0x0D80 -#define DISP_LIN_TRANS_GRPH_B 0x0D84 -#define DISP_LIN_TRANS_GRPH_C 0x0D88 -#define DISP_LIN_TRANS_GRPH_D 0x0D8C -#define DISP_LIN_TRANS_GRPH_E 0x0D90 -#define DISP_LIN_TRANS_GRPH_F 0x0D94 -#define DISP_LIN_TRANS_VID_A 0x0D98 -#define DISP_LIN_TRANS_VID_B 0x0D9C -#define DISP_LIN_TRANS_VID_C 0x0DA0 -#define DISP_LIN_TRANS_VID_D 0x0DA4 -#define DISP_LIN_TRANS_VID_E 0x0DA8 -#define DISP_LIN_TRANS_VID_F 0x0DAC -#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 -#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 -#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 -#define RMX_HORZ_PHASE 0x0DBC -#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 -#define DAC_BROAD_PULSE 0x0DC4 -#define DAC_SKEW_CLKS 0x0DC8 -#define DAC_INCR 0x0DCC -#define DAC_NEG_SYNC_LEVEL 0x0DD0 -#define DAC_POS_SYNC_LEVEL 0x0DD4 -#define DAC_BLANK_LEVEL 0x0DD8 -#define CLOCK_CNTL_INDEX 0x0008 -#define CLOCK_CNTL_DATA 0x000C -#define CP_RB_CNTL 0x0704 -#define CP_RB_BASE 0x0700 -#define CP_RB_RPTR_ADDR 0x070C -#define CP_RB_RPTR 0x0710 -#define CP_RB_WPTR 0x0714 -#define CP_RB_WPTR_DELAY 0x0718 -#define CP_IB_BASE 0x0738 -#define CP_IB_BUFSZ 0x073C -#define SCRATCH_REG0 0x15E0 -#define GUI_SCRATCH_REG0 0x15E0 -#define SCRATCH_REG1 0x15E4 -#define GUI_SCRATCH_REG1 0x15E4 -#define SCRATCH_REG2 0x15E8 -#define GUI_SCRATCH_REG2 0x15E8 -#define SCRATCH_REG3 0x15EC -#define GUI_SCRATCH_REG3 0x15EC -#define SCRATCH_REG4 0x15F0 -#define GUI_SCRATCH_REG4 0x15F0 -#define SCRATCH_REG5 0x15F4 -#define GUI_SCRATCH_REG5 0x15F4 -#define SCRATCH_UMSK 0x0770 -#define SCRATCH_ADDR 0x0774 -#define DP_BRUSH_FRGD_CLR 0x147C -#define DP_BRUSH_BKGD_CLR 0x1478 -#define DST_LINE_START 0x1600 -#define DST_LINE_END 0x1604 -#define SRC_OFFSET 0x15AC -#define SRC_PITCH 0x15B0 -#define SRC_TILE 0x1704 -#define SRC_PITCH_OFFSET 0x1428 -#define SRC_X 0x1414 -#define SRC_Y 0x1418 -#define SRC_X_Y 0x1590 -#define SRC_Y_X 0x1434 +#define MM_INDEX 0x0000 +#define MM_DATA 0x0004 +#define BUS_CNTL 0x0030 +#define HI_STAT 0x004C +#define BUS_CNTL1 0x0034 +#define I2C_CNTL_1 0x0094 +#define CONFIG_CNTL 0x00E0 +#define CONFIG_MEMSIZE 0x00F8 +#define CONFIG_APER_0_BASE 0x0100 +#define CONFIG_APER_1_BASE 0x0104 +#define CONFIG_APER_SIZE 0x0108 +#define CONFIG_REG_1_BASE 0x010C +#define CONFIG_REG_APER_SIZE 0x0110 +#define PAD_AGPINPUT_DELAY 0x0164 +#define PAD_CTLR_STRENGTH 0x0168 +#define PAD_CTLR_UPDATE 0x016C +#define PAD_CTLR_MISC 0x0aa0 +#define AGP_CNTL 0x0174 +#define BM_STATUS 0x0160 +#define CAP0_TRIG_CNTL 0x0950 +#define CAP1_TRIG_CNTL 0x09c0 +#define VIPH_CONTROL 0x0C40 +#define VENDOR_ID 0x0F00 +#define DEVICE_ID 0x0F02 +#define COMMAND 0x0F04 +#define STATUS 0x0F06 +#define REVISION_ID 0x0F08 +#define REGPROG_INF 0x0F09 +#define SUB_CLASS 0x0F0A +#define BASE_CODE 0x0F0B +#define CACHE_LINE 0x0F0C +#define LATENCY 0x0F0D +#define HEADER 0x0F0E +#define BIST 0x0F0F +#define REG_MEM_BASE 0x0F10 +#define REG_IO_BASE 0x0F14 +#define REG_REG_BASE 0x0F18 +#define ADAPTER_ID 0x0F2C +#define BIOS_ROM 0x0F30 +#define CAPABILITIES_PTR 0x0F34 +#define INTERRUPT_LINE 0x0F3C +#define INTERRUPT_PIN 0x0F3D +#define MIN_GRANT 0x0F3E +#define MAX_LATENCY 0x0F3F +#define ADAPTER_ID_W 0x0F4C +#define PMI_CAP_ID 0x0F50 +#define PMI_NXT_CAP_PTR 0x0F51 +#define PMI_PMC_REG 0x0F52 +#define PM_STATUS 0x0F54 +#define PMI_DATA 0x0F57 +#define AGP_CAP_ID 0x0F58 +#define AGP_STATUS 0x0F5C +#define AGP_COMMAND 0x0F60 +#define AIC_CTRL 0x01D0 +#define AIC_STAT 0x01D4 +#define AIC_PT_BASE 0x01D8 +#define AIC_LO_ADDR 0x01DC +#define AIC_HI_ADDR 0x01E0 +#define AIC_TLB_ADDR 0x01E4 +#define AIC_TLB_DATA 0x01E8 +#define DAC_CNTL 0x0058 +#define DAC_CNTL2 0x007c +#define CRTC_GEN_CNTL 0x0050 +#define MEM_CNTL 0x0140 +#define MC_CNTL 0x0140 +#define EXT_MEM_CNTL 0x0144 +#define MC_TIMING_CNTL 0x0144 +#define MC_AGP_LOCATION 0x014C +#define MEM_IO_CNTL_A0 0x0178 +#define MEM_REFRESH_CNTL 0x0178 +#define MEM_INIT_LATENCY_TIMER 0x0154 +#define MC_INIT_GFX_LAT_TIMER 0x0154 +#define MEM_SDRAM_MODE_REG 0x0158 +#define AGP_BASE 0x0170 +#define MEM_IO_CNTL_A1 0x017C +#define MC_READ_CNTL_AB 0x017C +#define MEM_IO_CNTL_B0 0x0180 +#define MC_INIT_MISC_LAT_TIMER 0x0180 +#define MEM_IO_CNTL_B1 0x0184 +#define MC_IOPAD_CNTL 0x0184 +#define MC_DEBUG 0x0188 +#define MC_STATUS 0x0150 +#define MEM_IO_OE_CNTL 0x018C +#define MC_CHIP_IO_OE_CNTL_AB 0x018C +#define MC_FB_LOCATION 0x0148 +/* #define MC_FB_LOCATION 0x0188 */ +#define HOST_PATH_CNTL 0x0130 +#define MEM_VGA_WP_SEL 0x0038 +#define MEM_VGA_RP_SEL 0x003C +#define HDP_DEBUG 0x0138 +#define SW_SEMAPHORE 0x013C +#define CRTC2_GEN_CNTL 0x03f8 +#define CRTC2_DISPLAY_BASE_ADDR 0x033c +#define SURFACE_CNTL 0x0B00 +#define SURFACE0_LOWER_BOUND 0x0B04 +#define SURFACE1_LOWER_BOUND 0x0B14 +#define SURFACE2_LOWER_BOUND 0x0B24 +#define SURFACE3_LOWER_BOUND 0x0B34 +#define SURFACE4_LOWER_BOUND 0x0B44 +#define SURFACE5_LOWER_BOUND 0x0B54 +#define SURFACE6_LOWER_BOUND 0x0B64 +#define SURFACE7_LOWER_BOUND 0x0B74 +#define SURFACE0_UPPER_BOUND 0x0B08 +#define SURFACE1_UPPER_BOUND 0x0B18 +#define SURFACE2_UPPER_BOUND 0x0B28 +#define SURFACE3_UPPER_BOUND 0x0B38 +#define SURFACE4_UPPER_BOUND 0x0B48 +#define SURFACE5_UPPER_BOUND 0x0B58 +#define SURFACE6_UPPER_BOUND 0x0B68 +#define SURFACE7_UPPER_BOUND 0x0B78 +#define SURFACE0_INFO 0x0B0C +#define SURFACE1_INFO 0x0B1C +#define SURFACE2_INFO 0x0B2C +#define SURFACE3_INFO 0x0B3C +#define SURFACE4_INFO 0x0B4C +#define SURFACE5_INFO 0x0B5C +#define SURFACE6_INFO 0x0B6C +#define SURFACE7_INFO 0x0B7C +#define SURFACE_ACCESS_FLAGS 0x0BF8 +#define SURFACE_ACCESS_CLR 0x0BFC +#define GEN_INT_CNTL 0x0040 +#define GEN_INT_STATUS 0x0044 +#define CRTC_EXT_CNTL 0x0054 +#define RB3D_CNTL 0x1C3C +#define WAIT_UNTIL 0x1720 +#define ISYNC_CNTL 0x1724 +#define RBBM_GUICNTL 0x172C +#define RBBM_STATUS 0x0E40 +#define RBBM_STATUS_alt_1 0x1740 +#define RBBM_CNTL 0x00EC +#define RBBM_CNTL_alt_1 0x0E44 +#define RBBM_SOFT_RESET 0x00F0 +#define RBBM_SOFT_RESET_alt_1 0x0E48 +#define NQWAIT_UNTIL 0x0E50 +#define RBBM_DEBUG 0x0E6C +#define RBBM_CMDFIFO_ADDR 0x0E70 +#define RBBM_CMDFIFO_DATAL 0x0E74 +#define RBBM_CMDFIFO_DATAH 0x0E78 +#define RBBM_CMDFIFO_STAT 0x0E7C +#define CRTC_STATUS 0x005C +#define GPIO_VGA_DDC 0x0060 +#define GPIO_DVI_DDC 0x0064 +#define GPIO_MONID 0x0068 +#define GPIO_CRT2_DDC 0x006c +#define PALETTE_INDEX 0x00B0 +#define PALETTE_DATA 0x00B4 +#define PALETTE_30_DATA 0x00B8 +#define CRTC_H_TOTAL_DISP 0x0200 +#define CRTC_H_SYNC_STRT_WID 0x0204 +#define CRTC_V_TOTAL_DISP 0x0208 +#define CRTC_V_SYNC_STRT_WID 0x020C +#define CRTC_VLINE_CRNT_VLINE 0x0210 +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC_DEBUG 0x021C +#define CRTC_OFFSET_RIGHT 0x0220 +#define CRTC_OFFSET 0x0224 +#define CRTC_OFFSET_CNTL 0x0228 +#define CRTC_PITCH 0x022C +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define DISPLAY_BASE_ADDR 0x023C +#define SNAPSHOT_VH_COUNTS 0x0240 +#define SNAPSHOT_F_COUNT 0x0244 +#define N_VIF_COUNT 0x0248 +#define SNAPSHOT_VIF_COUNT 0x024C +#define FP_CRTC_H_TOTAL_DISP 0x0250 +#define FP_CRTC_V_TOTAL_DISP 0x0254 +#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 +#define CRT_CRTC_V_SYNC_STRT_WID 0x025C +#define CUR_OFFSET 0x0260 +#define CUR_HORZ_VERT_POSN 0x0264 +#define CUR_HORZ_VERT_OFF 0x0268 +#define CUR_CLR0 0x026C +#define CUR_CLR1 0x0270 +#define FP_HORZ_VERT_ACTIVE 0x0278 +#define CRTC_MORE_CNTL 0x027C +#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +#define DAC_EXT_CNTL 0x0280 +#define FP_GEN_CNTL 0x0284 +#define FP_HORZ_STRETCH 0x028C +#define FP_VERT_STRETCH 0x0290 +#define FP_H_SYNC_STRT_WID 0x02C4 +#define FP_V_SYNC_STRT_WID 0x02C8 +#define AUX_WINDOW_HORZ_CNTL 0x02D8 +#define AUX_WINDOW_VERT_CNTL 0x02DC +/* #define DDA_CONFIG 0x02e0 */ +/* #define DDA_ON_OFF 0x02e4 */ +#define DVI_I2C_CNTL_1 0x02e4 +#define GRPH_BUFFER_CNTL 0x02F0 +#define GRPH2_BUFFER_CNTL 0x03F0 +#define VGA_BUFFER_CNTL 0x02F4 +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_PIPELINE_CNTL 0x0408 +#define OV0_REG_LOAD_CNTL 0x0410 +#define OV0_SCALE_CNTL 0x0420 +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +#define OV0_P23_V_ACCUM_INIT 0x042C +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +#define OV0_BASE_ADDR 0x043C +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +#define OV0_VID_BUF3_BASE_ADRS 0x044C +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTRL 0x0470 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_SUBMIT_HISTORY 0x0478 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +#define OV0_FOUR_TAP_COEF_0 0x04B0 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +#define OV0_FOUR_TAP_COEF_3 0x04BC +#define OV0_FOUR_TAP_COEF_4 0x04C0 +#define OV0_FLAG_CNTRL 0x04DC +#define OV0_SLICE_CNTL 0x04E0 +#define OV0_VID_KEY_CLR_LOW 0x04E4 +#define OV0_VID_KEY_CLR_HIGH 0x04E8 +#define OV0_GRPH_KEY_CLR_LOW 0x04EC +#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +#define OV0_TEST 0x04F8 +#define SUBPIC_CNTL 0x0540 +#define SUBPIC_DEFCOLCON 0x0544 +#define SUBPIC_Y_X_START 0x054C +#define SUBPIC_Y_X_END 0x0550 +#define SUBPIC_V_INC 0x0554 +#define SUBPIC_H_INC 0x0558 +#define SUBPIC_BUF0_OFFSET 0x055C +#define SUBPIC_BUF1_OFFSET 0x0560 +#define SUBPIC_LC0_OFFSET 0x0564 +#define SUBPIC_LC1_OFFSET 0x0568 +#define SUBPIC_PITCH 0x056C +#define SUBPIC_BTN_HLI_COLCON 0x0570 +#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +#define SUBPIC_PALETTE_INDEX 0x057C +#define SUBPIC_PALETTE_DATA 0x0580 +#define SUBPIC_H_ACCUM_INIT 0x0584 +#define SUBPIC_V_ACCUM_INIT 0x0588 +#define DISP_MISC_CNTL 0x0D00 +#define DAC_MACRO_CNTL 0x0D04 +#define DISP_PWR_MAN 0x0D08 +#define DISP_TEST_DEBUG_CNTL 0x0D10 +#define DISP_HW_DEBUG 0x0D14 +#define DAC_CRC_SIG1 0x0D18 +#define DAC_CRC_SIG2 0x0D1C +#define OV0_LIN_TRANS_A 0x0D20 +#define OV0_LIN_TRANS_B 0x0D24 +#define OV0_LIN_TRANS_C 0x0D28 +#define OV0_LIN_TRANS_D 0x0D2C +#define OV0_LIN_TRANS_E 0x0D30 +#define OV0_LIN_TRANS_F 0x0D34 +#define OV0_GAMMA_0_F 0x0D40 +#define OV0_GAMMA_10_1F 0x0D44 +#define OV0_GAMMA_20_3F 0x0D48 +#define OV0_GAMMA_40_7F 0x0D4C +#define OV0_GAMMA_380_3BF 0x0D50 +#define OV0_GAMMA_3C0_3FF 0x0D54 +#define DISP_MERGE_CNTL 0x0D60 +#define DISP_OUTPUT_CNTL 0x0D64 +#define DISP_LIN_TRANS_GRPH_A 0x0D80 +#define DISP_LIN_TRANS_GRPH_B 0x0D84 +#define DISP_LIN_TRANS_GRPH_C 0x0D88 +#define DISP_LIN_TRANS_GRPH_D 0x0D8C +#define DISP_LIN_TRANS_GRPH_E 0x0D90 +#define DISP_LIN_TRANS_GRPH_F 0x0D94 +#define DISP_LIN_TRANS_VID_A 0x0D98 +#define DISP_LIN_TRANS_VID_B 0x0D9C +#define DISP_LIN_TRANS_VID_C 0x0DA0 +#define DISP_LIN_TRANS_VID_D 0x0DA4 +#define DISP_LIN_TRANS_VID_E 0x0DA8 +#define DISP_LIN_TRANS_VID_F 0x0DAC +#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 +#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 +#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 +#define RMX_HORZ_PHASE 0x0DBC +#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 +#define DAC_BROAD_PULSE 0x0DC4 +#define DAC_SKEW_CLKS 0x0DC8 +#define DAC_INCR 0x0DCC +#define DAC_NEG_SYNC_LEVEL 0x0DD0 +#define DAC_POS_SYNC_LEVEL 0x0DD4 +#define DAC_BLANK_LEVEL 0x0DD8 +#define CLOCK_CNTL_INDEX 0x0008 +#define CLOCK_CNTL_DATA 0x000C +#define CP_RB_CNTL 0x0704 +#define CP_RB_BASE 0x0700 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define SCRATCH_REG0 0x15E0 +#define GUI_SCRATCH_REG0 0x15E0 +#define SCRATCH_REG1 0x15E4 +#define GUI_SCRATCH_REG1 0x15E4 +#define SCRATCH_REG2 0x15E8 +#define GUI_SCRATCH_REG2 0x15E8 +#define SCRATCH_REG3 0x15EC +#define GUI_SCRATCH_REG3 0x15EC +#define SCRATCH_REG4 0x15F0 +#define GUI_SCRATCH_REG4 0x15F0 +#define SCRATCH_REG5 0x15F4 +#define GUI_SCRATCH_REG5 0x15F4 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DP_BRUSH_FRGD_CLR 0x147C +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DST_LINE_START 0x1600 +#define DST_LINE_END 0x1604 +#define SRC_OFFSET 0x15AC +#define SRC_PITCH 0x15B0 +#define SRC_TILE 0x1704 +#define SRC_PITCH_OFFSET 0x1428 +#define SRC_X 0x1414 +#define SRC_Y 0x1418 +#define SRC_X_Y 0x1590 +#define SRC_Y_X 0x1434 #define DST_Y_X 0x1438 -#define DST_WIDTH_HEIGHT 0x1598 -#define DST_HEIGHT_WIDTH 0x143c -#define DST_OFFSET 0x1404 -#define SRC_CLUT_ADDRESS 0x1780 -#define SRC_CLUT_DATA 0x1784 -#define SRC_CLUT_DATA_RD 0x1788 -#define HOST_DATA0 0x17C0 -#define HOST_DATA1 0x17C4 -#define HOST_DATA2 0x17C8 -#define HOST_DATA3 0x17CC -#define HOST_DATA4 0x17D0 -#define HOST_DATA5 0x17D4 -#define HOST_DATA6 0x17D8 -#define HOST_DATA7 0x17DC -#define HOST_DATA_LAST 0x17E0 -#define DP_SRC_ENDIAN 0x15D4 -#define DP_SRC_FRGD_CLR 0x15D8 -#define DP_SRC_BKGD_CLR 0x15DC -#define SC_LEFT 0x1640 -#define SC_RIGHT 0x1644 -#define SC_TOP 0x1648 -#define SC_BOTTOM 0x164C -#define SRC_SC_RIGHT 0x1654 -#define SRC_SC_BOTTOM 0x165C -#define DP_CNTL 0x16C0 -#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 -#define DP_DATATYPE 0x16C4 -#define DP_MIX 0x16C8 -#define DP_WRITE_MSK 0x16CC -#define DP_XOP 0x17F8 -#define CLR_CMP_CLR_SRC 0x15C4 -#define CLR_CMP_CLR_DST 0x15C8 -#define CLR_CMP_CNTL 0x15C0 -#define CLR_CMP_MSK 0x15CC -#define DSTCACHE_MODE 0x1710 -#define DSTCACHE_CTLSTAT 0x1714 -#define DEFAULT_PITCH_OFFSET 0x16E0 -#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 -#define DEFAULT_SC_TOP_LEFT 0x16EC -#define SRC_PITCH_OFFSET 0x1428 -#define DST_PITCH_OFFSET 0x142C -#define DP_GUI_MASTER_CNTL 0x146C -#define SC_TOP_LEFT 0x16EC -#define SC_BOTTOM_RIGHT 0x16F0 -#define SRC_SC_BOTTOM_RIGHT 0x16F4 -#define RB2D_DSTCACHE_MODE 0x3428 -#define RB2D_DSTCACHE_CTLSTAT 0x342C -#define LVDS_GEN_CNTL 0x02d0 -#define LVDS_PLL_CNTL 0x02d4 -#define FP2_GEN_CNTL 0x0288 -#define TMDS_CNTL 0x0294 -#define TMDS_CRC 0x02a0 -#define TMDS_TRANSMITTER_CNTL 0x02a4 -#define MPP_TB_CONFIG 0x01c0 -#define PAMAC0_DLY_CNTL 0x0a94 -#define PAMAC1_DLY_CNTL 0x0a98 -#define PAMAC2_DLY_CNTL 0x0a9c -#define FW_CNTL 0x0118 -#define FCP_CNTL 0x0910 -#define VGA_DDA_ON_OFF 0x02ec -#define TV_MASTER_CNTL 0x0800 - -//#define BASE_CODE 0x0f0b -#define BIOS_0_SCRATCH 0x0010 -#define BIOS_1_SCRATCH 0x0014 -#define BIOS_2_SCRATCH 0x0018 -#define BIOS_3_SCRATCH 0x001c -#define BIOS_4_SCRATCH 0x0020 -#define BIOS_5_SCRATCH 0x0024 -#define BIOS_6_SCRATCH 0x0028 -#define BIOS_7_SCRATCH 0x002c - -#define HDP_SOFT_RESET (1 << 26) - -#define TV_DAC_CNTL 0x088c -#define GPIOPAD_MASK 0x0198 -#define GPIOPAD_A 0x019c -#define GPIOPAD_EN 0x01a0 -#define GPIOPAD_Y 0x01a4 -#define ZV_LCDPAD_MASK 0x01a8 -#define ZV_LCDPAD_A 0x01ac -#define ZV_LCDPAD_EN 0x01b0 -#define ZV_LCDPAD_Y 0x01b4 +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_HEIGHT_WIDTH 0x143c +#define DST_OFFSET 0x1404 +#define SRC_CLUT_ADDRESS 0x1780 +#define SRC_CLUT_DATA 0x1784 +#define SRC_CLUT_DATA_RD 0x1788 +#define HOST_DATA0 0x17C0 +#define HOST_DATA1 0x17C4 +#define HOST_DATA2 0x17C8 +#define HOST_DATA3 0x17CC +#define HOST_DATA4 0x17D0 +#define HOST_DATA5 0x17D4 +#define HOST_DATA6 0x17D8 +#define HOST_DATA7 0x17DC +#define HOST_DATA_LAST 0x17E0 +#define DP_SRC_ENDIAN 0x15D4 +#define DP_SRC_FRGD_CLR 0x15D8 +#define DP_SRC_BKGD_CLR 0x15DC +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_BOTTOM 0x164C +#define SRC_SC_RIGHT 0x1654 +#define SRC_SC_BOTTOM 0x165C +#define DP_CNTL 0x16C0 +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 +#define DP_DATATYPE 0x16C4 +#define DP_MIX 0x16C8 +#define DP_WRITE_MSK 0x16CC +#define DP_XOP 0x17F8 +#define CLR_CMP_CLR_SRC 0x15C4 +#define CLR_CMP_CLR_DST 0x15C8 +#define CLR_CMP_CNTL 0x15C0 +#define CLR_CMP_MSK 0x15CC +#define DSTCACHE_MODE 0x1710 +#define DSTCACHE_CTLSTAT 0x1714 +#define DEFAULT_PITCH_OFFSET 0x16E0 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 +#define DEFAULT_SC_TOP_LEFT 0x16EC +#define SRC_PITCH_OFFSET 0x1428 +#define DST_PITCH_OFFSET 0x142C +#define DP_GUI_MASTER_CNTL 0x146C +#define SC_TOP_LEFT 0x16EC +#define SC_BOTTOM_RIGHT 0x16F0 +#define SRC_SC_BOTTOM_RIGHT 0x16F4 +#define RB2D_DSTCACHE_MODE 0x3428 +#define RB2D_DSTCACHE_CTLSTAT 0x342C +#define LVDS_GEN_CNTL 0x02d0 +#define LVDS_PLL_CNTL 0x02d4 +#define FP2_GEN_CNTL 0x0288 +#define TMDS_CNTL 0x0294 +#define TMDS_CRC 0x02a0 +#define TMDS_TRANSMITTER_CNTL 0x02a4 +#define MPP_TB_CONFIG 0x01c0 +#define PAMAC0_DLY_CNTL 0x0a94 +#define PAMAC1_DLY_CNTL 0x0a98 +#define PAMAC2_DLY_CNTL 0x0a9c +#define FW_CNTL 0x0118 +#define FCP_CNTL 0x0910 +#define VGA_DDA_ON_OFF 0x02ec +#define TV_MASTER_CNTL 0x0800 + +/* #define BASE_CODE 0x0f0b */ +#define BIOS_0_SCRATCH 0x0010 +#define BIOS_1_SCRATCH 0x0014 +#define BIOS_2_SCRATCH 0x0018 +#define BIOS_3_SCRATCH 0x001c +#define BIOS_4_SCRATCH 0x0020 +#define BIOS_5_SCRATCH 0x0024 +#define BIOS_6_SCRATCH 0x0028 +#define BIOS_7_SCRATCH 0x002c + +#define HDP_SOFT_RESET (1 << 26) + +#define TV_DAC_CNTL 0x088c +#define GPIOPAD_MASK 0x0198 +#define GPIOPAD_A 0x019c +#define GPIOPAD_EN 0x01a0 +#define GPIOPAD_Y 0x01a4 +#define ZV_LCDPAD_MASK 0x01a8 +#define ZV_LCDPAD_A 0x01ac +#define ZV_LCDPAD_EN 0x01b0 +#define ZV_LCDPAD_Y 0x01b4 /* PLL Registers */ -#define CLK_PIN_CNTL 0x0001 -#define PPLL_CNTL 0x0002 -#define PPLL_REF_DIV 0x0003 -#define PPLL_DIV_0 0x0004 -#define PPLL_DIV_1 0x0005 -#define PPLL_DIV_2 0x0006 -#define PPLL_DIV_3 0x0007 -#define VCLK_ECP_CNTL 0x0008 -#define HTOTAL_CNTL 0x0009 -#define M_SPLL_REF_FB_DIV 0x000a -#define AGP_PLL_CNTL 0x000b -#define SPLL_CNTL 0x000c -#define SCLK_CNTL 0x000d -#define MPLL_CNTL 0x000e -#define MDLL_CKO 0x000f -#define MDLL_RDCKA 0x0010 -#define MCLK_CNTL 0x0012 -#define AGP_PLL_CNTL 0x000b -#define PLL_TEST_CNTL 0x0013 -#define CLK_PWRMGT_CNTL 0x0014 -#define PLL_PWRMGT_CNTL 0x0015 -#define MCLK_MISC 0x001f -#define P2PLL_CNTL 0x002a -#define P2PLL_REF_DIV 0x002b -#define PIXCLKS_CNTL 0x002d -#define SCLK_MORE_CNTL 0x0035 +#define CLK_PIN_CNTL 0x0001 +#define PPLL_CNTL 0x0002 +#define PPLL_REF_DIV 0x0003 +#define PPLL_DIV_0 0x0004 +#define PPLL_DIV_1 0x0005 +#define PPLL_DIV_2 0x0006 +#define PPLL_DIV_3 0x0007 +#define VCLK_ECP_CNTL 0x0008 +#define HTOTAL_CNTL 0x0009 +#define M_SPLL_REF_FB_DIV 0x000a +#define AGP_PLL_CNTL 0x000b +#define SPLL_CNTL 0x000c +#define SCLK_CNTL 0x000d +#define MPLL_CNTL 0x000e +#define MDLL_CKO 0x000f +#define MDLL_RDCKA 0x0010 +#define MCLK_CNTL 0x0012 +#define AGP_PLL_CNTL 0x000b +#define PLL_TEST_CNTL 0x0013 +#define CLK_PWRMGT_CNTL 0x0014 +#define PLL_PWRMGT_CNTL 0x0015 +#define MCLK_MISC 0x001f +#define P2PLL_CNTL 0x002a +#define P2PLL_REF_DIV 0x002b +#define PIXCLKS_CNTL 0x002d +#define SCLK_MORE_CNTL 0x0035 /* MCLK_CNTL bit constants */ -#define FORCEON_MCLKA (1 << 16) -#define FORCEON_MCLKB (1 << 17) -#define FORCEON_YCLKA (1 << 18) -#define FORCEON_YCLKB (1 << 19) -#define FORCEON_MC (1 << 20) -#define FORCEON_AIC (1 << 21) +#define FORCEON_MCLKA (1 << 16) +#define FORCEON_MCLKB (1 << 17) +#define FORCEON_YCLKA (1 << 18) +#define FORCEON_YCLKB (1 << 19) +#define FORCEON_MC (1 << 20) +#define FORCEON_AIC (1 << 21) /* SCLK_CNTL bit constants */ -#define DYN_STOP_LAT_MASK 0x00007ff8 -#define CP_MAX_DYN_STOP_LAT 0x0008 -#define SCLK_FORCEON_MASK 0xffff8000 +#define DYN_STOP_LAT_MASK 0x00007ff8 +#define CP_MAX_DYN_STOP_LAT 0x0008 +#define SCLK_FORCEON_MASK 0xffff8000 /* SCLK_MORE_CNTL bit constants */ -#define SCLK_MORE_FORCEON 0x0700 +#define SCLK_MORE_FORCEON 0x0700 /* BUS_CNTL bit constants */ -#define BUS_DBL_RESYNC 0x00000001 -#define BUS_MSTR_RESET 0x00000002 -#define BUS_FLUSH_BUF 0x00000004 -#define BUS_STOP_REQ_DIS 0x00000008 -#define BUS_ROTATION_DIS 0x00000010 -#define BUS_MASTER_DIS 0x00000040 -#define BUS_ROM_WRT_EN 0x00000080 -#define BUS_DIS_ROM 0x00001000 -#define BUS_PCI_READ_RETRY_EN 0x00002000 -#define BUS_AGP_AD_STEPPING_EN 0x00004000 -#define BUS_PCI_WRT_RETRY_EN 0x00008000 -#define BUS_MSTR_RD_MULT 0x00100000 -#define BUS_MSTR_RD_LINE 0x00200000 -#define BUS_SUSPEND 0x00400000 -#define LAT_16X 0x00800000 -#define BUS_RD_DISCARD_EN 0x01000000 -#define BUS_RD_ABORT_EN 0x02000000 -#define BUS_MSTR_WS 0x04000000 -#define BUS_PARKING_DIS 0x08000000 -#define BUS_MSTR_DISCONNECT_EN 0x10000000 -#define BUS_WRT_BURST 0x20000000 -#define BUS_READ_BURST 0x40000000 -#define BUS_RDY_READ_DLY 0x80000000 +#define BUS_DBL_RESYNC 0x00000001 +#define BUS_MSTR_RESET 0x00000002 +#define BUS_FLUSH_BUF 0x00000004 +#define BUS_STOP_REQ_DIS 0x00000008 +#define BUS_ROTATION_DIS 0x00000010 +#define BUS_MASTER_DIS 0x00000040 +#define BUS_ROM_WRT_EN 0x00000080 +#define BUS_DIS_ROM 0x00001000 +#define BUS_PCI_READ_RETRY_EN 0x00002000 +#define BUS_AGP_AD_STEPPING_EN 0x00004000 +#define BUS_PCI_WRT_RETRY_EN 0x00008000 +#define BUS_MSTR_RD_MULT 0x00100000 +#define BUS_MSTR_RD_LINE 0x00200000 +#define BUS_SUSPEND 0x00400000 +#define LAT_16X 0x00800000 +#define BUS_RD_DISCARD_EN 0x01000000 +#define BUS_RD_ABORT_EN 0x02000000 +#define BUS_MSTR_WS 0x04000000 +#define BUS_PARKING_DIS 0x08000000 +#define BUS_MSTR_DISCONNECT_EN 0x10000000 +#define BUS_WRT_BURST 0x20000000 +#define BUS_READ_BURST 0x40000000 +#define BUS_RDY_READ_DLY 0x80000000 /* PIXCLKS_CNTL */ -#define PIX2CLK_SRC_SEL_MASK 0x03 -#define PIX2CLK_SRC_SEL_CPUCLK 0x00 -#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 -#define PIX2CLK_SRC_SEL_BYTECLK 0x02 -#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 -#define PIX2CLK_ALWAYS_ONb (1<<6) -#define PIX2CLK_DAC_ALWAYS_ONb (1<<7) -#define PIXCLK_TV_SRC_SEL (1 << 8) -#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) -#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) +#define PIX2CLK_SRC_SEL_MASK 0x03 +#define PIX2CLK_SRC_SEL_CPUCLK 0x00 +#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 +#define PIX2CLK_SRC_SEL_BYTECLK 0x02 +#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +#define PIX2CLK_ALWAYS_ONb (1<<6) +#define PIX2CLK_DAC_ALWAYS_ONb (1<<7) +#define PIXCLK_TV_SRC_SEL (1 << 8) +#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) /* CLOCK_CNTL_INDEX bit constants */ -#define PLL_WR_EN 0x00000080 +#define PLL_WR_EN 0x00000080 /* CONFIG_CNTL bit constants */ -#define CFG_VGA_RAM_EN 0x00000100 -#define CFG_ATI_REV_ID_MASK (0xf << 16) -#define CFG_ATI_REV_A11 (0 << 16) -#define CFG_ATI_REV_A12 (1 << 16) -#define CFG_ATI_REV_A13 (2 << 16) +#define CFG_VGA_RAM_EN 0x00000100 +#define CFG_ATI_REV_ID_MASK (0xf << 16) +#define CFG_ATI_REV_A11 (0 << 16) +#define CFG_ATI_REV_A12 (1 << 16) +#define CFG_ATI_REV_A13 (2 << 16) /* CRTC_EXT_CNTL bit constants */ -#define VGA_ATI_LINEAR 0x00000008 -#define VGA_128KAP_PAGING 0x00000010 -#define XCRT_CNT_EN (1 << 6) -#define CRTC_HSYNC_DIS (1 << 8) -#define CRTC_VSYNC_DIS (1 << 9) -#define CRTC_DISPLAY_DIS (1 << 10) -#define CRTC_CRT_ON (1 << 15) +#define VGA_ATI_LINEAR 0x00000008 +#define VGA_128KAP_PAGING 0x00000010 +#define XCRT_CNT_EN (1 << 6) +#define CRTC_HSYNC_DIS (1 << 8) +#define CRTC_VSYNC_DIS (1 << 9) +#define CRTC_DISPLAY_DIS (1 << 10) +#define CRTC_CRT_ON (1 << 15) /* DSTCACHE_CTLSTAT bit constants */ -#define RB2D_DC_FLUSH (3 << 0) -#define RB2D_DC_FLUSH_ALL 0xf -#define RB2D_DC_BUSY (1 << 31) +#define RB2D_DC_FLUSH (3 << 0) +#define RB2D_DC_FLUSH_ALL 0xf +#define RB2D_DC_BUSY (1 << 31) /* CRTC_GEN_CNTL bit constants */ -#define CRTC_DBL_SCAN_EN 0x00000001 -#define CRTC_CUR_EN 0x00010000 -#define CRTC_INTERLACE_EN (1 << 1) -#define CRTC_BYPASS_LUT_EN (1 << 14) -#define CRTC_EXT_DISP_EN (1 << 24) -#define CRTC_EN (1 << 25) -#define CRTC_DISP_REQ_EN_B (1 << 26) +#define CRTC_DBL_SCAN_EN 0x00000001 +#define CRTC_CUR_EN 0x00010000 +#define CRTC_INTERLACE_EN (1 << 1) +#define CRTC_BYPASS_LUT_EN (1 << 14) +#define CRTC_EXT_DISP_EN (1 << 24) +#define CRTC_EN (1 << 25) +#define CRTC_DISP_REQ_EN_B (1 << 26) /* CRTC_STATUS bit constants */ -#define CRTC_VBLANK 0x00000001 +#define CRTC_VBLANK 0x00000001 /* CRTC2_GEN_CNTL bit constants */ -#define CRT2_ON (1 << 7) -#define CRTC2_DISPLAY_DIS (1 << 23) -#define CRTC2_EN (1 << 25) -#define CRTC2_DISP_REQ_EN_B (1 << 26) +#define CRT2_ON (1 << 7) +#define CRTC2_DISPLAY_DIS (1 << 23) +#define CRTC2_EN (1 << 25) +#define CRTC2_DISP_REQ_EN_B (1 << 26) /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ -#define CUR_LOCK 0x80000000 +#define CUR_LOCK 0x80000000 /* GPIO bit constants */ -#define GPIO_A_0 (1 << 0) -#define GPIO_A_1 (1 << 1) -#define GPIO_Y_0 (1 << 8) -#define GPIO_Y_1 (1 << 9) -#define GPIO_EN_0 (1 << 16) -#define GPIO_EN_1 (1 << 17) -#define GPIO_MASK_0 (1 << 24) -#define GPIO_MASK_1 (1 << 25) -#define VGA_DDC_DATA_OUTPUT GPIO_A_0 -#define VGA_DDC_CLK_OUTPUT GPIO_A_1 -#define VGA_DDC_DATA_INPUT GPIO_Y_0 -#define VGA_DDC_CLK_INPUT GPIO_Y_1 -#define VGA_DDC_DATA_OUT_EN GPIO_EN_0 -#define VGA_DDC_CLK_OUT_EN GPIO_EN_1 +#define GPIO_A_0 (1 << 0) +#define GPIO_A_1 (1 << 1) +#define GPIO_Y_0 (1 << 8) +#define GPIO_Y_1 (1 << 9) +#define GPIO_EN_0 (1 << 16) +#define GPIO_EN_1 (1 << 17) +#define GPIO_MASK_0 (1 << 24) +#define GPIO_MASK_1 (1 << 25) +#define VGA_DDC_DATA_OUTPUT GPIO_A_0 +#define VGA_DDC_CLK_OUTPUT GPIO_A_1 +#define VGA_DDC_DATA_INPUT GPIO_Y_0 +#define VGA_DDC_CLK_INPUT GPIO_Y_1 +#define VGA_DDC_DATA_OUT_EN GPIO_EN_0 +#define VGA_DDC_CLK_OUT_EN GPIO_EN_1 /* FP bit constants */ -#define FP_CRTC_H_TOTAL_MASK 0x000003ff -#define FP_CRTC_H_DISP_MASK 0x01ff0000 -#define FP_CRTC_V_TOTAL_MASK 0x00000fff -#define FP_CRTC_V_DISP_MASK 0x0fff0000 -#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 -#define FP_H_SYNC_WID_MASK 0x003f0000 -#define FP_V_SYNC_STRT_MASK 0x00000fff -#define FP_V_SYNC_WID_MASK 0x001f0000 -#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 -#define FP_CRTC_H_DISP_SHIFT 0x00000010 -#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 -#define FP_CRTC_V_DISP_SHIFT 0x00000010 -#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 -#define FP_H_SYNC_WID_SHIFT 0x00000010 -#define FP_V_SYNC_STRT_SHIFT 0x00000000 -#define FP_V_SYNC_WID_SHIFT 0x00000010 +#define FP_CRTC_H_TOTAL_MASK 000003ff +#define FP_CRTC_H_DISP_MASK 0x01ff0000 +#define FP_CRTC_V_TOTAL_MASK 0x00000fff +#define FP_CRTC_V_DISP_MASK 0x0fff0000 +#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +#define FP_H_SYNC_WID_MASK 0x003f0000 +#define FP_V_SYNC_STRT_MASK 0x00000fff +#define FP_V_SYNC_WID_MASK 0x001f0000 +#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +#define FP_CRTC_H_DISP_SHIFT 0x00000010 +#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +#define FP_CRTC_V_DISP_SHIFT 0x00000010 +#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +#define FP_H_SYNC_WID_SHIFT 0x00000010 +#define FP_V_SYNC_STRT_SHIFT 0x00000000 +#define FP_V_SYNC_WID_SHIFT 0x00000010 /* FP_GEN_CNTL bit constants */ -#define FP_FPON (1 << 0) -#define FP_TMDS_EN (1 << 2) -#define FP_PANEL_FORMAT (1 << 3) -#define FP_EN_TMDS (1 << 7) -#define FP_DETECT_SENSE (1 << 8) -#define R200_FP_SOURCE_SEL_MASK (3 << 10) -#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) -#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) -#define R200_FP_SOURCE_SEL_RMX (2 << 10) -#define R200_FP_SOURCE_SEL_TRANS (3 << 10) -#define FP_SEL_CRTC1 (0 << 13) -#define FP_SEL_CRTC2 (1 << 13) -#define FP_USE_VGA_HSYNC (1 << 14) -#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) -#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) -#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) -#define FP_CRTC_USE_SHADOW_VEND (1 << 18) -#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) -#define FP_DFP_SYNC_SEL (1 << 21) -#define FP_CRTC_LOCK_8DOT (1 << 22) -#define FP_CRT_SYNC_SEL (1 << 23) -#define FP_USE_SHADOW_EN (1 << 24) -#define FP_CRT_SYNC_ALT (1 << 26) +#define FP_FPON (1 << 0) +#define FP_TMDS_EN (1 << 2) +#define FP_PANEL_FORMAT (1 << 3) +#define FP_EN_TMDS (1 << 7) +#define FP_DETECT_SENSE (1 << 8) +#define R200_FP_SOURCE_SEL_MASK (3 << 10) +#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) +#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) +#define R200_FP_SOURCE_SEL_RMX (2 << 10) +#define R200_FP_SOURCE_SEL_TRANS (3 << 10) +#define FP_SEL_CRTC1 (0 << 13) +#define FP_SEL_CRTC2 (1 << 13) +#define FP_USE_VGA_HSYNC (1 << 14) +#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +#define FP_CRTC_USE_SHADOW_VEND (1 << 18) +#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +#define FP_DFP_SYNC_SEL (1 << 21) +#define FP_CRTC_LOCK_8DOT (1 << 22) +#define FP_CRT_SYNC_SEL (1 << 23) +#define FP_USE_SHADOW_EN (1 << 24) +#define FP_CRT_SYNC_ALT (1 << 26) /* FP2_GEN_CNTL bit constants */ -#define FP2_BLANK_EN (1 << 1) -#define FP2_ON (1 << 2) -#define FP2_PANEL_FORMAT (1 << 3) -#define FP2_SOURCE_SEL_MASK (3 << 10) -#define FP2_SOURCE_SEL_CRTC2 (1 << 10) -#define FP2_SRC_SEL_MASK (3 << 13) -#define FP2_SRC_SEL_CRTC2 (1 << 13) -#define FP2_FP_POL (1 << 16) -#define FP2_LP_POL (1 << 17) -#define FP2_SCK_POL (1 << 18) -#define FP2_LCD_CNTL_MASK (7 << 19) -#define FP2_PAD_FLOP_EN (1 << 22) -#define FP2_CRC_EN (1 << 23) -#define FP2_CRC_READ_EN (1 << 24) -#define FP2_DV0_EN (1 << 25) -#define FP2_DV0_RATE_SEL_SDR (1 << 26) +#define FP2_BLANK_EN (1 << 1) +#define FP2_ON (1 << 2) +#define FP2_PANEL_FORMAT (1 << 3) +#define FP2_SOURCE_SEL_MASK (3 << 10) +#define FP2_SOURCE_SEL_CRTC2 (1 << 10) +#define FP2_SRC_SEL_MASK (3 << 13) +#define FP2_SRC_SEL_CRTC2 (1 << 13) +#define FP2_FP_POL (1 << 16) +#define FP2_LP_POL (1 << 17) +#define FP2_SCK_POL (1 << 18) +#define FP2_LCD_CNTL_MASK (7 << 19) +#define FP2_PAD_FLOP_EN (1 << 22) +#define FP2_CRC_EN (1 << 23) +#define FP2_CRC_READ_EN (1 << 24) +#define FP2_DV0_EN (1 << 25) +#define FP2_DV0_RATE_SEL_SDR (1 << 26) /* LVDS_GEN_CNTL bit constants */ -#define LVDS_ON (1 << 0) -#define LVDS_DISPLAY_DIS (1 << 1) -#define LVDS_PANEL_TYPE (1 << 2) -#define LVDS_PANEL_FORMAT (1 << 3) -#define LVDS_EN (1 << 7) -#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 -#define LVDS_BL_MOD_LEVEL_SHIFT 8 -#define LVDS_BL_MOD_EN (1 << 16) -#define LVDS_DIGON (1 << 18) -#define LVDS_BLON (1 << 19) -#define LVDS_SEL_CRTC2 (1 << 23) -#define LVDS_STATE_MASK \ +#define LVDS_ON (1 << 0) +#define LVDS_DISPLAY_DIS (1 << 1) +#define LVDS_PANEL_TYPE (1 << 2) +#define LVDS_PANEL_FORMAT (1 << 3) +#define LVDS_EN (1 << 7) +#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 +#define LVDS_BL_MOD_LEVEL_SHIFT 8 +#define LVDS_BL_MOD_EN (1 << 16) +#define LVDS_DIGON (1 << 18) +#define LVDS_BLON (1 << 19) +#define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_STATE_MASK \ (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) /* LVDS_PLL_CNTL bit constatns */ -#define HSYNC_DELAY_SHIFT 0x1c -#define HSYNC_DELAY_MASK (0xf << 0x1c) +#define HSYNC_DELAY_SHIFT 0x1c +#define HSYNC_DELAY_MASK (0xf << 0x1c) /* TMDS_TRANSMITTER_CNTL bit constants */ -#define TMDS_PLL_EN (1 << 0) -#define TMDS_PLLRST (1 << 1) -#define TMDS_RAN_PAT_RST (1 << 7) -#define TMDS_ICHCSEL (1 << 28) +#define TMDS_PLL_EN (1 << 0) +#define TMDS_PLLRST (1 << 1) +#define TMDS_RAN_PAT_RST (1 << 7) +#define TMDS_ICHCSEL (1 << 28) /* FP_HORZ_STRETCH bit constants */ -#define HORZ_STRETCH_RATIO_MASK 0xffff -#define HORZ_STRETCH_RATIO_MAX 4096 -#define HORZ_PANEL_SIZE (0x1ff << 16) -#define HORZ_PANEL_SHIFT 16 -#define HORZ_STRETCH_PIXREP (0 << 25) -#define HORZ_STRETCH_BLEND (1 << 26) -#define HORZ_STRETCH_ENABLE (1 << 25) -#define HORZ_AUTO_RATIO (1 << 27) -#define HORZ_FP_LOOP_STRETCH (0x7 << 28) -#define HORZ_AUTO_RATIO_INC (1 << 31) +#define HORZ_STRETCH_RATIO_MASK 0xffff +#define HORZ_STRETCH_RATIO_MAX 4096 +#define HORZ_PANEL_SIZE (0x1ff << 16) +#define HORZ_PANEL_SHIFT 16 +#define HORZ_STRETCH_PIXREP (0 << 25) +#define HORZ_STRETCH_BLEND (1 << 26) +#define HORZ_STRETCH_ENABLE (1 << 25) +#define HORZ_AUTO_RATIO (1 << 27) +#define HORZ_FP_LOOP_STRETCH (0x7 << 28) +#define HORZ_AUTO_RATIO_INC (1 << 31) /* FP_VERT_STRETCH bit constants */ -#define VERT_STRETCH_RATIO_MASK 0xfff -#define VERT_STRETCH_RATIO_MAX 4096 -#define VERT_PANEL_SIZE (0xfff << 12) -#define VERT_PANEL_SHIFT 12 -#define VERT_STRETCH_LINREP (0 << 26) -#define VERT_STRETCH_BLEND (1 << 26) -#define VERT_STRETCH_ENABLE (1 << 25) -#define VERT_AUTO_RATIO_EN (1 << 27) -#define VERT_FP_LOOP_STRETCH (0x7 << 28) -#define VERT_STRETCH_RESERVED 0xf1000000 +#define VERT_STRETCH_RATIO_MASK 0xfff +#define VERT_STRETCH_RATIO_MAX 4096 +#define VERT_PANEL_SIZE (0xfff << 12) +#define VERT_PANEL_SHIFT 12 +#define VERT_STRETCH_LINREP (0 << 26) +#define VERT_STRETCH_BLEND (1 << 26) +#define VERT_STRETCH_ENABLE (1 << 25) +#define VERT_AUTO_RATIO_EN (1 << 27) +#define VERT_FP_LOOP_STRETCH (0x7 << 28) +#define VERT_STRETCH_RESERVED 0xf1000000 /* DAC_CNTL bit constants */ -#define DAC_8BIT_EN 0x00000100 -#define DAC_4BPP_PIX_ORDER 0x00000200 -#define DAC_CRC_EN 0x00080000 -#define DAC_MASK_ALL (0xff << 24) -#define DAC_PDWN (1 << 15) -#define DAC_EXPAND_MODE (1 << 14) -#define DAC_VGA_ADR_EN (1 << 13) -#define DAC_RANGE_CNTL (3 << 0) -#define DAC_RANGE_CNTL_MASK 0x03 -#define DAC_BLANKING (1 << 2) -#define DAC_CMP_EN (1 << 3) -#define DAC_CMP_OUTPUT (1 << 7) +#define DAC_8BIT_EN 0x00000100 +#define DAC_4BPP_PIX_ORDER 0x00000200 +#define DAC_CRC_EN 0x00080000 +#define DAC_MASK_ALL (0xff << 24) +#define DAC_PDWN (1 << 15) +#define DAC_EXPAND_MODE (1 << 14) +#define DAC_VGA_ADR_EN (1 << 13) +#define DAC_RANGE_CNTL (3 << 0) +#define DAC_RANGE_CNTL_MASK 0x03 +#define DAC_BLANKING (1 << 2) +#define DAC_CMP_EN (1 << 3) +#define DAC_CMP_OUTPUT (1 << 7) /* DAC_CNTL2 bit constants */ -#define DAC2_EXPAND_MODE (1 << 14) -#define DAC2_CMP_EN (1 << 7) -#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) +#define DAC2_EXPAND_MODE (1 << 14) +#define DAC2_CMP_EN (1 << 7) +#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) /* DAC_EXT_CNTL bit constants */ -#define DAC_FORCE_BLANK_OFF_EN (1 << 4) -#define DAC_FORCE_DATA_EN (1 << 5) -#define DAC_FORCE_DATA_SEL_MASK (3 << 6) -#define DAC_FORCE_DATA_MASK 0x0003ff00 -#define DAC_FORCE_DATA_SHIFT 8 +#define DAC_FORCE_BLANK_OFF_EN (1 << 4) +#define DAC_FORCE_DATA_EN (1 << 5) +#define DAC_FORCE_DATA_SEL_MASK (3 << 6) +#define DAC_FORCE_DATA_MASK 0x0003ff00 +#define DAC_FORCE_DATA_SHIFT 8 /* GEN_RESET_CNTL bit constants */ -#define SOFT_RESET_GUI 0x00000001 -#define SOFT_RESET_VCLK 0x00000100 -#define SOFT_RESET_PCLK 0x00000200 -#define SOFT_RESET_ECP 0x00000400 -#define SOFT_RESET_DISPENG_XCLK 0x00000800 +#define SOFT_RESET_GUI 0x00000001 +#define SOFT_RESET_VCLK 0x00000100 +#define SOFT_RESET_PCLK 0x00000200 +#define SOFT_RESET_ECP 0x00000400 +#define SOFT_RESET_DISPENG_XCLK 0x00000800 /* MEM_CNTL bit constants */ -#define MEM_CTLR_STATUS_IDLE 0x00000000 -#define MEM_CTLR_STATUS_BUSY 0x00100000 -#define MEM_SEQNCR_STATUS_IDLE 0x00000000 -#define MEM_SEQNCR_STATUS_BUSY 0x00200000 -#define MEM_ARBITER_STATUS_IDLE 0x00000000 -#define MEM_ARBITER_STATUS_BUSY 0x00400000 -#define MEM_REQ_UNLOCK 0x00000000 -#define MEM_REQ_LOCK 0x00800000 -#define MEM_NUM_CHANNELS_MASK 0x00000001 -#define MEM_USE_B_CH_ONLY 0x00000002 -#define RV100_MEM_HALF_MODE 0x00000008 -#define R300_MEM_NUM_CHANNELS_MASK 0x00000003 -#define R300_MEM_USE_CD_CH_ONLY 0x00000004 +#define MEM_CTLR_STATUS_IDLE 0x00000000 +#define MEM_CTLR_STATUS_BUSY 0x00100000 +#define MEM_SEQNCR_STATUS_IDLE 0x00000000 +#define MEM_SEQNCR_STATUS_BUSY 0x00200000 +#define MEM_ARBITER_STATUS_IDLE 0x00000000 +#define MEM_ARBITER_STATUS_BUSY 0x00400000 +#define MEM_REQ_UNLOCK 0x00000000 +#define MEM_REQ_LOCK 0x00800000 +#define MEM_NUM_CHANNELS_MASK 0x00000001 +#define MEM_USE_B_CH_ONLY 0x00000002 +#define RV100_MEM_HALF_MODE 0x00000008 +#define R300_MEM_NUM_CHANNELS_MASK 0x00000003 +#define R300_MEM_USE_CD_CH_ONLY 0x00000004 /* RBBM_SOFT_RESET bit constants */ -#define SOFT_RESET_CP (1 << 0) -#define SOFT_RESET_HI (1 << 1) -#define SOFT_RESET_SE (1 << 2) -#define SOFT_RESET_RE (1 << 3) -#define SOFT_RESET_PP (1 << 4) -#define SOFT_RESET_E2 (1 << 5) -#define SOFT_RESET_RB (1 << 6) -#define SOFT_RESET_HDP (1 << 7) +#define SOFT_RESET_CP (1 << 0) +#define SOFT_RESET_HI (1 << 1) +#define SOFT_RESET_SE (1 << 2) +#define SOFT_RESET_RE (1 << 3) +#define SOFT_RESET_PP (1 << 4) +#define SOFT_RESET_E2 (1 << 5) +#define SOFT_RESET_RB (1 << 6) +#define SOFT_RESET_HDP (1 << 7) /* SURFACE_CNTL bit consants */ -#define SURF_TRANSLATION_DIS (1 << 8) -#define NONSURF_AP0_SWP_16BPP (1 << 20) -#define NONSURF_AP0_SWP_32BPP (1 << 21) -#define NONSURF_AP1_SWP_16BPP (1 << 22) -#define NONSURF_AP1_SWP_32BPP (1 << 23) +#define SURF_TRANSLATION_DIS (1 << 8) +#define NONSURF_AP0_SWP_16BPP (1 << 20) +#define NONSURF_AP0_SWP_32BPP (1 << 21) +#define NONSURF_AP1_SWP_16BPP (1 << 22) +#define NONSURF_AP1_SWP_32BPP (1 << 23) /* DEFAULT_SC_BOTTOM_RIGHT bit constants */ -#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) -#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) /* MM_INDEX bit constants */ -#define MM_APER 0x80000000 +#define MM_APER 0x80000000 /* CLR_CMP_CNTL bit constants */ -#define COMPARE_SRC_FALSE 0x00000000 -#define COMPARE_SRC_TRUE 0x00000001 -#define COMPARE_SRC_NOT_EQUAL 0x00000004 -#define COMPARE_SRC_EQUAL 0x00000005 -#define COMPARE_SRC_EQUAL_FLIP 0x00000007 -#define COMPARE_DST_FALSE 0x00000000 -#define COMPARE_DST_TRUE 0x00000100 -#define COMPARE_DST_NOT_EQUAL 0x00000400 -#define COMPARE_DST_EQUAL 0x00000500 -#define COMPARE_DESTINATION 0x00000000 -#define COMPARE_SOURCE 0x01000000 -#define COMPARE_SRC_AND_DST 0x02000000 +#define COMPARE_SRC_FALSE 0x00000000 +#define COMPARE_SRC_TRUE 0x00000001 +#define COMPARE_SRC_NOT_EQUAL 0x00000004 +#define COMPARE_SRC_EQUAL 0x00000005 +#define COMPARE_SRC_EQUAL_FLIP 0x00000007 +#define COMPARE_DST_FALSE 0x00000000 +#define COMPARE_DST_TRUE 0x00000100 +#define COMPARE_DST_NOT_EQUAL 0x00000400 +#define COMPARE_DST_EQUAL 0x00000500 +#define COMPARE_DESTINATION 0x00000000 +#define COMPARE_SOURCE 0x01000000 +#define COMPARE_SRC_AND_DST 0x02000000 /* DP_CNTL bit constants */ -#define DST_X_RIGHT_TO_LEFT 0x00000000 -#define DST_X_LEFT_TO_RIGHT 0x00000001 -#define DST_Y_BOTTOM_TO_TOP 0x00000000 -#define DST_Y_TOP_TO_BOTTOM 0x00000002 -#define DST_X_MAJOR 0x00000000 -#define DST_Y_MAJOR 0x00000004 -#define DST_X_TILE 0x00000008 -#define DST_Y_TILE 0x00000010 -#define DST_LAST_PEL 0x00000020 -#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 -#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 -#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 -#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 -#define DST_BRES_SIGN 0x00000100 -#define DST_HOST_BIG_ENDIAN_EN 0x00000200 -#define DST_POLYLINE_NONLAST 0x00008000 -#define DST_RASTER_STALL 0x00010000 -#define DST_POLY_EDGE 0x00040000 +#define DST_X_RIGHT_TO_LEFT 0x00000000 +#define DST_X_LEFT_TO_RIGHT 0x00000001 +#define DST_Y_BOTTOM_TO_TOP 0x00000000 +#define DST_Y_TOP_TO_BOTTOM 0x00000002 +#define DST_X_MAJOR 0x00000000 +#define DST_Y_MAJOR 0x00000004 +#define DST_X_TILE 0x00000008 +#define DST_Y_TILE 0x00000010 +#define DST_LAST_PEL 0x00000020 +#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +#define DST_BRES_SIGN 0x00000100 +#define DST_HOST_BIG_ENDIAN_EN 0x00000200 +#define DST_POLYLINE_NONLAST 0x00008000 +#define DST_RASTER_STALL 0x00010000 +#define DST_POLY_EDGE 0x00040000 /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ -#define DST_X_MAJOR_S 0x00000000 -#define DST_Y_MAJOR_S 0x00000001 -#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 -#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 -#define DST_X_RIGHT_TO_LEFT_S 0x00000000 -#define DST_X_LEFT_TO_RIGHT_S 0x80000000 +#define DST_X_MAJOR_S 0x00000000 +#define DST_Y_MAJOR_S 0x00000001 +#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 +#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 +#define DST_X_RIGHT_TO_LEFT_S 0x00000000 +#define DST_X_LEFT_TO_RIGHT_S 0x80000000 /* DP_DATATYPE bit constants */ -#define DST_8BPP 0x00000002 -#define DST_15BPP 0x00000003 -#define DST_16BPP 0x00000004 -#define DST_24BPP 0x00000005 -#define DST_32BPP 0x00000006 -#define DST_8BPP_RGB332 0x00000007 -#define DST_8BPP_Y8 0x00000008 -#define DST_8BPP_RGB8 0x00000009 -#define DST_16BPP_VYUY422 0x0000000b -#define DST_16BPP_YVYU422 0x0000000c -#define DST_32BPP_AYUV444 0x0000000e -#define DST_16BPP_ARGB4444 0x0000000f -#define BRUSH_SOLIDCOLOR 0x00000d00 -#define SRC_MONO 0x00000000 -#define SRC_MONO_LBKGD 0x00010000 -#define SRC_DSTCOLOR 0x00030000 -#define BYTE_ORDER_MSB_TO_LSB 0x00000000 -#define BYTE_ORDER_LSB_TO_MSB 0x40000000 -#define DP_CONVERSION_TEMP 0x80000000 -#define HOST_BIG_ENDIAN_EN (1 << 29) +#define DST_8BPP 0x00000002 +#define DST_15BPP 0x00000003 +#define DST_16BPP 0x00000004 +#define DST_24BPP 0x00000005 +#define DST_32BPP 0x00000006 +#define DST_8BPP_RGB332 0x00000007 +#define DST_8BPP_Y8 0x00000008 +#define DST_8BPP_RGB8 0x00000009 +#define DST_16BPP_VYUY422 0x0000000b +#define DST_16BPP_YVYU422 0x0000000c +#define DST_32BPP_AYUV444 0x0000000e +#define DST_16BPP_ARGB4444 0x0000000f +#define BRUSH_SOLIDCOLOR 0x00000d00 +#define SRC_MONO 0x00000000 +#define SRC_MONO_LBKGD 0x00010000 +#define SRC_DSTCOLOR 0x00030000 +#define BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define BYTE_ORDER_LSB_TO_MSB 0x40000000 +#define DP_CONVERSION_TEMP 0x80000000 +#define HOST_BIG_ENDIAN_EN (1 << 29) /* DP_GUI_MASTER_CNTL bit constants */ -#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 -#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 -#define GMC_SRC_CLIP_DEFAULT 0x00000000 -#define GMC_SRC_CLIP_LEAVE 0x00000004 -#define GMC_DST_CLIP_DEFAULT 0x00000000 -#define GMC_DST_CLIP_LEAVE 0x00000008 -#define GMC_BRUSH_8x8MONO 0x00000000 -#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 -#define GMC_BRUSH_8x1MONO 0x00000020 -#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 -#define GMC_BRUSH_1x8MONO 0x00000040 -#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 -#define GMC_BRUSH_32x1MONO 0x00000060 -#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 -#define GMC_BRUSH_32x32MONO 0x00000080 -#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 -#define GMC_BRUSH_8x8COLOR 0x000000a0 -#define GMC_BRUSH_8x1COLOR 0x000000b0 -#define GMC_BRUSH_1x8COLOR 0x000000c0 -#define GMC_BRUSH_SOLID_COLOR 0x000000d0 -#define GMC_DST_8BPP 0x00000200 -#define GMC_DST_15BPP 0x00000300 -#define GMC_DST_16BPP 0x00000400 -#define GMC_DST_24BPP 0x00000500 -#define GMC_DST_32BPP 0x00000600 -#define GMC_DST_8BPP_RGB332 0x00000700 -#define GMC_DST_8BPP_Y8 0x00000800 -#define GMC_DST_8BPP_RGB8 0x00000900 -#define GMC_DST_16BPP_VYUY422 0x00000b00 -#define GMC_DST_16BPP_YVYU422 0x00000c00 -#define GMC_DST_32BPP_AYUV444 0x00000e00 -#define GMC_DST_16BPP_ARGB4444 0x00000f00 -#define GMC_SRC_MONO 0x00000000 -#define GMC_SRC_MONO_LBKGD 0x00001000 -#define GMC_SRC_DSTCOLOR 0x00003000 -#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 -#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 -#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 -#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 -#define GMC_DP_SRC_RECT 0x02000000 -#define GMC_DP_SRC_HOST 0x03000000 -#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 -#define GMC_3D_FCN_EN_CLR 0x00000000 -#define GMC_3D_FCN_EN_SET 0x08000000 -#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 -#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 -#define GMC_AUX_CLIP_LEAVE 0x00000000 -#define GMC_AUX_CLIP_CLEAR 0x20000000 -#define GMC_WRITE_MASK_LEAVE 0x00000000 -#define GMC_WRITE_MASK_SET 0x40000000 -#define GMC_CLR_CMP_CNTL_DIS (1 << 28) -#define GMC_SRC_DATATYPE_COLOR (3 << 12) -#define ROP3_S 0x00cc0000 -#define ROP3_SRCCOPY 0x00cc0000 -#define ROP3_P 0x00f00000 -#define ROP3_PATCOPY 0x00f00000 -#define DP_SRC_SOURCE_MASK (7 << 24) -#define GMC_BRUSH_NONE (15 << 4) -#define DP_SRC_SOURCE_MEMORY (2 << 24) -#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 +#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 +#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 +#define GMC_SRC_CLIP_DEFAULT 0x00000000 +#define GMC_SRC_CLIP_LEAVE 0x00000004 +#define GMC_DST_CLIP_DEFAULT 0x00000000 +#define GMC_DST_CLIP_LEAVE 0x00000008 +#define GMC_BRUSH_8x8MONO 0x00000000 +#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 +#define GMC_BRUSH_8x1MONO 0x00000020 +#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 +#define GMC_BRUSH_1x8MONO 0x00000040 +#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 +#define GMC_BRUSH_32x1MONO 0x00000060 +#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 +#define GMC_BRUSH_32x32MONO 0x00000080 +#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 +#define GMC_BRUSH_8x8COLOR 0x000000a0 +#define GMC_BRUSH_8x1COLOR 0x000000b0 +#define GMC_BRUSH_1x8COLOR 0x000000c0 +#define GMC_BRUSH_SOLID_COLOR 0x000000d0 +#define GMC_DST_8BPP 0x00000200 +#define GMC_DST_15BPP 0x00000300 +#define GMC_DST_16BPP 0x00000400 +#define GMC_DST_24BPP 0x00000500 +#define GMC_DST_32BPP 0x00000600 +#define GMC_DST_8BPP_RGB332 0x00000700 +#define GMC_DST_8BPP_Y8 0x00000800 +#define GMC_DST_8BPP_RGB8 0x00000900 +#define GMC_DST_16BPP_VYUY422 0x00000b00 +#define GMC_DST_16BPP_YVYU422 0x00000c00 +#define GMC_DST_32BPP_AYUV444 0x00000e00 +#define GMC_DST_16BPP_ARGB4444 0x00000f00 +#define GMC_SRC_MONO 0x00000000 +#define GMC_SRC_MONO_LBKGD 0x00001000 +#define GMC_SRC_DSTCOLOR 0x00003000 +#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 +#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 +#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +#define GMC_DP_SRC_RECT 0x02000000 +#define GMC_DP_SRC_HOST 0x03000000 +#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 +#define GMC_3D_FCN_EN_CLR 0x00000000 +#define GMC_3D_FCN_EN_SET 0x08000000 +#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 +#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +#define GMC_AUX_CLIP_LEAVE 0x00000000 +#define GMC_AUX_CLIP_CLEAR 0x20000000 +#define GMC_WRITE_MASK_LEAVE 0x00000000 +#define GMC_WRITE_MASK_SET 0x40000000 +#define GMC_CLR_CMP_CNTL_DIS (1 << 28) +#define GMC_SRC_DATATYPE_COLOR (3 << 12) +#define ROP3_S 0x00cc0000 +#define ROP3_SRCCOPY 0x00cc0000 +#define ROP3_P 0x00f00000 +#define ROP3_PATCOPY 0x00f00000 +#define DP_SRC_SOURCE_MASK (7 << 24) +#define GMC_BRUSH_NONE (15 << 4) +#define DP_SRC_SOURCE_MEMORY (2 << 24) +#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 /* DP_MIX bit constants */ -#define DP_SRC_RECT 0x00000200 -#define DP_SRC_HOST 0x00000300 -#define DP_SRC_HOST_BYTEALIGN 0x00000400 +#define DP_SRC_RECT 0x00000200 +#define DP_SRC_HOST 0x00000300 +#define DP_SRC_HOST_BYTEALIGN 0x00000400 /* MPLL_CNTL bit constants */ -#define MPLL_RESET 0x00000001 +#define MPLL_RESET 0x00000001 /* MDLL_CKO bit constants */ -#define MCKOA_SLEEP 0x00000001 -#define MCKOA_RESET 0x00000002 -#define MCKOA_REF_SKEW_MASK 0x00000700 -#define MCKOA_FB_SKEW_MASK 0x00007000 +#define MCKOA_SLEEP 0x00000001 +#define MCKOA_RESET 0x00000002 +#define MCKOA_REF_SKEW_MASK 0x00000700 +#define MCKOA_FB_SKEW_MASK 0x00007000 /* MDLL_RDCKA bit constants */ -#define MRDCKA0_SLEEP 0x00000001 -#define MRDCKA0_RESET 0x00000002 -#define MRDCKA1_SLEEP 0x00010000 -#define MRDCKA1_RESET 0x00020000 +#define MRDCKA0_SLEEP 0x00000001 +#define MRDCKA0_RESET 0x00000002 +#define MRDCKA1_SLEEP 0x00010000 +#define MRDCKA1_RESET 0x00020000 /* VCLK_ECP_CNTL constants */ -#define VCLK_SRC_SEL_MASK 0x03 -#define VCLK_SRC_SEL_CPUCLK 0x00 -#define VCLK_SRC_SEL_PSCANCLK 0x01 -#define VCLK_SRC_SEL_BYTECLK 0x02 -#define VCLK_SRC_SEL_PPLLCLK 0x03 -#define PIXCLK_ALWAYS_ONb 0x00000040 -#define PIXCLK_DAC_ALWAYS_ONb 0x00000080 +#define VCLK_SRC_SEL_MASK 0x03 +#define VCLK_SRC_SEL_CPUCLK 0x00 +#define VCLK_SRC_SEL_PSCANCLK 0x01 +#define VCLK_SRC_SEL_BYTECLK 0x02 +#define VCLK_SRC_SEL_PPLLCLK 0x03 +#define PIXCLK_ALWAYS_ONb 0x00000040 +#define PIXCLK_DAC_ALWAYS_ONb 0x00000080 /* BUS_CNTL1 constants */ -#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 -#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 -#define BUS_CNTL1_AGPCLK_VALID 0x80000000 +#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 +#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 +#define BUS_CNTL1_AGPCLK_VALID 0x80000000 /* PLL_PWRMGT_CNTL constants */ -#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 -#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 -#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 -#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 -#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 -#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 -#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 +#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 +#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 +#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 +#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 +#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 +#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 +#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 /* TV_DAC_CNTL constants */ -#define TV_DAC_CNTL_BGSLEEP 0x00000040 -#define TV_DAC_CNTL_DETECT 0x00000010 -#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 -#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 -#define TV_DAC_CNTL_BGADJ__SHIFT 16 -#define TV_DAC_CNTL_DACADJ__SHIFT 20 -#define TV_DAC_CNTL_RDACPD 0x01000000 -#define TV_DAC_CNTL_GDACPD 0x02000000 -#define TV_DAC_CNTL_BDACPD 0x04000000 +#define TV_DAC_CNTL_BGSLEEP 0x00000040 +#define TV_DAC_CNTL_DETECT 0x00000010 +#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 +#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 +#define TV_DAC_CNTL_BGADJ__SHIFT 16 +#define TV_DAC_CNTL_DACADJ__SHIFT 20 +#define TV_DAC_CNTL_RDACPD 0x01000000 +#define TV_DAC_CNTL_GDACPD 0x02000000 +#define TV_DAC_CNTL_BDACPD 0x04000000 /* DISP_MISC_CNTL constants */ -#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) -#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) -#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) -#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) -#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) -#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) -#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) -#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) -#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) +#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) +#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) +#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) +#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) +#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) +#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) +#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) +#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) /* DISP_PWR_MAN constants */ -#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) -#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) -#define DISP_PWR_MAN_DISP_D3_RST (1 << 16) -#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) -#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) -#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) -#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) -#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) -#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) -#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) -#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) -#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) -#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) +#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) +#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) +#define DISP_PWR_MAN_DISP_D3_RST (1 << 16) +#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) +#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) +#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) +#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) +#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) +#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) +#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) +#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) +#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) +#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) /* masks */ @@ -978,1009 +978,1007 @@ #define DST_OFFSET_MASK 0x003fffff #define DST_PITCH_MASK 0x3fc00000 #define DEFAULT_TILE_MASK 0xc0000000 -#define PPLL_DIV_SEL_MASK 0x00000300 -#define PPLL_RESET 0x00000001 -#define PPLL_SLEEP 0x00000002 +#define PPLL_DIV_SEL_MASK 0x00000300 +#define PPLL_RESET 0x00000001 +#define PPLL_SLEEP 0x00000002 #define PPLL_ATOMIC_UPDATE_EN 0x00010000 #define PPLL_REF_DIV_MASK 0x000003ff -#define PPLL_FB3_DIV_MASK 0x000007ff -#define PPLL_POST3_DIV_MASK 0x00070000 +#define PPLL_FB3_DIV_MASK 0x000007ff +#define PPLL_POST3_DIV_MASK 0x00070000 #define PPLL_ATOMIC_UPDATE_R 0x00008000 #define PPLL_ATOMIC_UPDATE_W 0x00008000 -#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 +#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 #define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) #define R300_PPLL_REF_DIV_ACC_SHIFT 18 #define GUI_ACTIVE 0x80000000 -#define MC_IND_INDEX 0x01F8 -#define MC_IND_DATA 0x01FC +#define MC_IND_INDEX 0x01F8 +#define MC_IND_DATA 0x01FC /* PAD_CTLR_STRENGTH */ #define PAD_MANUAL_OVERRIDE 0x80000000 -// pllCLK_PIN_CNTL -#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L -#define CLK_PIN_CNTL__OSC_EN 0x00000001L -#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L -#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L -#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L -#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L -#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L -#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L -#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L -#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L -#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L -#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L -#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L -#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L -#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L -#define CLK_PIN_CNTL__CG_SPARE 0x00004000L -#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L -#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L -#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L -#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L -#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L -#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L -#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L -#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L - -// pllCLK_PWRMGT_CNTL -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 -#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 -#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c -#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f -#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 -#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 -#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 -#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 -#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 -#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 -#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f - -// pllP2PLL_CNTL -#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L -#define P2PLL_CNTL__P2PLL_RESET 0x00000001L -#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L -#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L -#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L -#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L -#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L -#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L -#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L -#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L -#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L -#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L -#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L -#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L -#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L -#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L -#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L -#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L -#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L - -// pllPIXCLKS_CNTL -#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 -#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 -#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 -#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 -#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 -#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 -#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b -#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c -#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d -#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e -#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f - - -// pllPIXCLKS_CNTL -#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L -#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L -#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L -#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L -#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L -#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L -#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L -#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L -#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L -#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L -#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L -#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) -#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) -#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) -#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) -#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) -#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) -#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) -#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) - - -// pllP2PLL_DIV_0 -#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L -#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L - -// pllSCLK_CNTL -#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L -#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L -#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L -#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L -#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L -#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L -#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L -#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L -#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L -#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L -#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L -#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L -#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L -#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 -#define SCLK_CNTL__FORCE_DISP2 0x00008000L -#define SCLK_CNTL__FORCE_CP 0x00010000L -#define SCLK_CNTL__FORCE_HDP 0x00020000L -#define SCLK_CNTL__FORCE_DISP1 0x00040000L -#define SCLK_CNTL__FORCE_TOP 0x00080000L -#define SCLK_CNTL__FORCE_E2 0x00100000L -#define SCLK_CNTL__FORCE_SE 0x00200000L -#define SCLK_CNTL__FORCE_IDCT 0x00400000L -#define SCLK_CNTL__FORCE_VIP 0x00800000L -#define SCLK_CNTL__FORCE_RE 0x01000000L -#define SCLK_CNTL__FORCE_PB 0x02000000L -#define SCLK_CNTL__FORCE_TAM 0x04000000L -#define SCLK_CNTL__FORCE_TDM 0x08000000L -#define SCLK_CNTL__FORCE_RB 0x10000000L -#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L -#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L -#define SCLK_CNTL__FORCE_OV0 0x80000000L -#define SCLK_CNTL__R300_FORCE_VAP (1<<21) -#define SCLK_CNTL__R300_FORCE_SR (1<<25) -#define SCLK_CNTL__R300_FORCE_PX (1<<26) -#define SCLK_CNTL__R300_FORCE_TX (1<<27) -#define SCLK_CNTL__R300_FORCE_US (1<<28) -#define SCLK_CNTL__R300_FORCE_SU (1<<30) -#define SCLK_CNTL__FORCEON_MASK 0xffff8000L - -// pllSCLK_CNTL2 -#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) -#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) -#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) -#define SCLK_CNTL2__R300_FORCE_TCL (1<<13) -#define SCLK_CNTL2__R300_FORCE_CBA (1<<14) -#define SCLK_CNTL2__R300_FORCE_GA (1<<15) - -// SCLK_MORE_CNTL -#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L -#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L -#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L -#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L -#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L -#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L -#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L -#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L -#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L -#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L -#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L -#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L -#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L -#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L -#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L -#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L -#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L -#define SCLK_MORE_CNTL__FORCEON 0x00000700L - -// MCLK_CNTL -#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L -#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L -#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L -#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L -#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L -#define MCLK_CNTL__FORCE_MCLKA 0x00010000L -#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L -#define MCLK_CNTL__FORCE_MCLKB 0x00020000L -#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L -#define MCLK_CNTL__FORCE_YCLKA 0x00040000L -#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L -#define MCLK_CNTL__FORCE_YCLKB 0x00080000L -#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L -#define MCLK_CNTL__FORCE_MC 0x00100000L -#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L -#define MCLK_CNTL__FORCE_AIC 0x00200000L -#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L -#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L -#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L -#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L -#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) -#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) - -// MCLK_MISC -#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L -#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L -#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L -#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L -#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L -#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L -#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L -#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L -#define MCLK_MISC__DLL_READY_LAT 0x00000100L -#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L -#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L -#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L -#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L -#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L -#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L -#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L -#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L -#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L -#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L -#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L -#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L -#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L -#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L -#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L -#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L -#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L -#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L -#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L - -// VCLK_ECP_CNTL -#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L -#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L -#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L -#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L -#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L -#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L -#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L -#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L +/* pllCLK_PIN_CNTL */ +#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L +#define CLK_PIN_CNTL__OSC_EN 0x00000001L +#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L +#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L +#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L +#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L +#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L +#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L +#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L +#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L +#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L +#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L +#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L +#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L +#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L +#define CLK_PIN_CNTL__CG_SPARE 0x00004000L +#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L +#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L +#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L +#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L +#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L +#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L +#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L +#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L + +/* pllCLK_PWRMGT_CNTL */ +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 +#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 +#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c +#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f +#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 +#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 +#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 +#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 +#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 +#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 +#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f + +/* pllP2PLL_CNTL */ +#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L +#define P2PLL_CNTL__P2PLL_RESET 0x00000001L +#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L +#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L +#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L +#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L +#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L +#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L +#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L +#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L +#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L +#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L +#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L +#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L +#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L +#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L +#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L +#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L +#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L + +/* pllPIXCLKS_CNTL */ +#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 +#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f + + +/* pllPIXCLKS_CNTL */ +#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L +#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L +#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) +#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) +#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) +#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) +#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) +#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) +#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) +#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) + + +/* pllP2PLL_DIV_0 */ +#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L +#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L + +/* pllSCLK_CNTL */ +#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L +#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L +#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L +#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L +#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L +#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L +#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L +#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L +#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L +#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L +#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L +#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L +#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L +#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 +#define SCLK_CNTL__FORCE_DISP2 0x00008000L +#define SCLK_CNTL__FORCE_CP 0x00010000L +#define SCLK_CNTL__FORCE_HDP 0x00020000L +#define SCLK_CNTL__FORCE_DISP1 0x00040000L +#define SCLK_CNTL__FORCE_TOP 0x00080000L +#define SCLK_CNTL__FORCE_E2 0x00100000L +#define SCLK_CNTL__FORCE_SE 0x00200000L +#define SCLK_CNTL__FORCE_IDCT 0x00400000L +#define SCLK_CNTL__FORCE_VIP 0x00800000L +#define SCLK_CNTL__FORCE_RE 0x01000000L +#define SCLK_CNTL__FORCE_PB 0x02000000L +#define SCLK_CNTL__FORCE_TAM 0x04000000L +#define SCLK_CNTL__FORCE_TDM 0x08000000L +#define SCLK_CNTL__FORCE_RB 0x10000000L +#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L +#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L +#define SCLK_CNTL__FORCE_OV0 0x80000000L +#define SCLK_CNTL__R300_FORCE_VAP (1<<21) +#define SCLK_CNTL__R300_FORCE_SR (1<<25) +#define SCLK_CNTL__R300_FORCE_PX (1<<26) +#define SCLK_CNTL__R300_FORCE_TX (1<<27) +#define SCLK_CNTL__R300_FORCE_US (1<<28) +#define SCLK_CNTL__R300_FORCE_SU (1<<30) +#define SCLK_CNTL__FORCEON_MASK 0xffff8000L + +/* pllSCLK_CNTL2 */ +#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) +#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) +#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) +#define SCLK_CNTL2__R300_FORCE_TCL (1<<13) +#define SCLK_CNTL2__R300_FORCE_CBA (1<<14) +#define SCLK_CNTL2__R300_FORCE_GA (1<<15) + +/* SCLK_MORE_CNTL */ +#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L +#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L +#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L +#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L +#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L +#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L +#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L +#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L +#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L +#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L +#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L +#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L +#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L +#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L +#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L +#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L +#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L +#define SCLK_MORE_CNTL__FORCEON 0x00000700L + +/* MCLK_CNTL */ +#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L +#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L +#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L +#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L +#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L +#define MCLK_CNTL__FORCE_MCLKA 0x00010000L +#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L +#define MCLK_CNTL__FORCE_MCLKB 0x00020000L +#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L +#define MCLK_CNTL__FORCE_YCLKA 0x00040000L +#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L +#define MCLK_CNTL__FORCE_YCLKB 0x00080000L +#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L +#define MCLK_CNTL__FORCE_MC 0x00100000L +#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L +#define MCLK_CNTL__FORCE_AIC 0x00200000L +#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L +#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L +#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L +#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L +#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) +#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) + +/* MCLK_MISC */ +#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L +#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L +#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L +#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L +#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L +#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L +#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L +#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L +#define MCLK_MISC__DLL_READY_LAT 0x00000100L +#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L +#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L +#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L +#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L +#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L +#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L +#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L +#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L +#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L +#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L +#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L +#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L +#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L +#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L +#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L +#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L +#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L +#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L +#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L + +/* VCLK_ECP_CNTL */ +#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L +#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L +#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L +#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L +#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L +#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L +#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L +#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L #define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) -// PLL_PWRMGT_CNTL -#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L -#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L -#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L -#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L -#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L -#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L -#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L -#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L -#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L -#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L -#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L -#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L -#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L -#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L -#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L -#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L -#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L -#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L -#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L -#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L -#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L -#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L -#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L -#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L -#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L -#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L -#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L -#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L -#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L -#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L -#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L -#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L - -// CLK_PWRMGT_CNTL -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L -#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L -#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L -#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L -#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L -#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L -#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L -#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L -#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L -#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L -#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L -#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L -#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L -#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L -#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L -#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L -#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L -#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L - -// BUS_CNTL1 -#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L -#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L -#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L -#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L -#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L -#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L -#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L -#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L -#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L -#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L -#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L -#define BUS_CNTL1__AGPCLK_VALID 0x80000000L - -// BUS_CNTL1 -#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 -#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 -#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 -#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b -#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a -#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c -#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f - -// CRTC_OFFSET_CNTL -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L +/* PLL_PWRMGT_CNTL */ +#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L +#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L +#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L +#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L +#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L +#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L +#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L +#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L +#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L +#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L +#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L +#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L +#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L +#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L +#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L +#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L +#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L +#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L +#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L +#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L +#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L +#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L +#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L +#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L +#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L +#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L +#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L +#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L +#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L +#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L +#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L +#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L + +/* CLK_PWRMGT_CNTL */ +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L +#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L +#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L +#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L +#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L +#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L +#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L +#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L +#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L +#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L +#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L +#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L +#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L +#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L +#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L +#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L +#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L +#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L + +/* BUS_CNTL1 */ +#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L +#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L +#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L +#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L +#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L +#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L +#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L +#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L +#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L +#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L +#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L +#define BUS_CNTL1__AGPCLK_VALID 0x80000000L + +/* BUS_CNTL1 */ +#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 +#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 +#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 +#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b +#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a +#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c +#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f + +/* CRTC_OFFSET_CNTL */ +#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL +#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L - -// CRTC_GEN_CNTL -#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L -#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L -#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L -#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L -#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L -#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L -#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L -#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L -#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L -#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L -#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L -#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L -#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L -#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L -#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L -#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L -#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L -#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L -#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L - -// CRTC2_GEN_CNTL -#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L -#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L -#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L -#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L -#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L -#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L -#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L -#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L -#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L -#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L -#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L -#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L -#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L -#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L -#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L -#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L -#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L -#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L -#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L - -// AGP_CNTL -#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL -#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L -#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L -#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L -#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L -#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L -#define AGP_CNTL__EN_2X_STBB 0x00000400L -#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L -#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L -#define AGP_CNTL__SBA_DIS_MASK 0x00001000L -#define AGP_CNTL__SBA_DIS 0x00001000L -#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L -#define AGP_CNTL__AGP_REV_ID 0x00002000L -#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L -#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L -#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L -#define AGP_CNTL__FORCE_INT_VREF 0x00010000L -#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L -#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L -#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L -#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L -#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L -#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L -#define AGP_CNTL__EN_RBFCALM 0x00800000L -#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L -#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L -#define AGP_CNTL__DIS_RBF_MASK 0x02000000L -#define AGP_CNTL__DIS_RBF 0x02000000L -#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L -#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L -#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L -#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L - -// AGP_CNTL -#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 -#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 -#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 -#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a -#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b -#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c -#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d -#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f -#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 -#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 -#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 -#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 -#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 -#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 -#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 -#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a -#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b -#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e - -// DISP_MISC_CNTL -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L -#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L -#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L -#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L -#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L -#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L -#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L -#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L -#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L -#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L -#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L -#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L -#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L -#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L -#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L - -// DISP_PWR_MAN -#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L -#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L -#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L -#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L -#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L -#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L -#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L -#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L -#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L -#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L -#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L -#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L -#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L -#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L -#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L -#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L -#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L -#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L -#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L -#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L -#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L -#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L -#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L -#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L -#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L -#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L -#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L - -// MC_IND_INDEX -#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL -#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L -#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L - -// MC_IND_DATA -#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL - -// MC_CHP_IO_CNTL_A1 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a -#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c -#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e -#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 -#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f - -// MC_CHP_IO_CNTL_B1 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a -#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c -#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e -#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 -#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f - -// MC_CHP_IO_CNTL_A1 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L -#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L - -// MC_CHP_IO_CNTL_B1 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L -#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L - -// MEM_SDRAM_MODE_REG -#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL -#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L -#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L - -// MEM_SDRAM_MODE_REG -#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 -#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 -#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f - -// MEM_REFRESH_CNTL -#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL -#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L -#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L -#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L -#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L -#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L -#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L -#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L -#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L -#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L -#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L -#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L -#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L -#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L -#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L -#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L -#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L -#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L -#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L -#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L -#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L - -// MC_STATUS -#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L -#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L -#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L -#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L -#define MC_STATUS__MC_IDLE_MASK 0x00000004L -#define MC_STATUS__MC_IDLE 0x00000004L -#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L -#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L -#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L -#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L -#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L -#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L -#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L -#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L -#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L -#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L - -// MDLL_CKO -#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L -#define MDLL_CKO__MCKOA_SLEEP 0x00000001L -#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L -#define MDLL_CKO__MCKOA_RESET 0x00000002L -#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL -#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L -#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L -#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L -#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L -#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L -#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L -#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L -#define MDLL_CKO__MCKOB_SLEEP 0x00010000L -#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L -#define MDLL_CKO__MCKOB_RESET 0x00020000L -#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L -#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L -#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L -#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L -#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L -#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L -#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L - -// MDLL_RDCKA -#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L -#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L -#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L -#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L -#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL -#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L -#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L -#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L -#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L -#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L -#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L -#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L -#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L -#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L -#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L -#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L -#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L -#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L -#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L -#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L -#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L -#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L -#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L -#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L -#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L -#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L - -// MDLL_RDCKB -#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L -#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L -#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L -#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L -#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL -#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L -#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L -#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L -#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L -#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L -#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L -#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L -#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L -#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L -#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L -#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L -#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L -#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L -#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L -#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L -#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L -#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L -#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L -#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L -#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L -#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L - -#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L -#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L -#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L -#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L -#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L -#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L -#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L -#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L - -#define pllCLK_PIN_CNTL 0x0001 -#define pllPPLL_CNTL 0x0002 -#define pllPPLL_REF_DIV 0x0003 -#define pllPPLL_DIV_0 0x0004 -#define pllPPLL_DIV_1 0x0005 -#define pllPPLL_DIV_2 0x0006 -#define pllPPLL_DIV_3 0x0007 -#define pllVCLK_ECP_CNTL 0x0008 -#define pllHTOTAL_CNTL 0x0009 -#define pllM_SPLL_REF_FB_DIV 0x000A -#define pllAGP_PLL_CNTL 0x000B -#define pllSPLL_CNTL 0x000C -#define pllSCLK_CNTL 0x000D -#define pllMPLL_CNTL 0x000E -#define pllMDLL_CKO 0x000F -#define pllMDLL_RDCKA 0x0010 -#define pllMDLL_RDCKB 0x0011 -#define pllMCLK_CNTL 0x0012 -#define pllPLL_TEST_CNTL 0x0013 -#define pllCLK_PWRMGT_CNTL 0x0014 -#define pllPLL_PWRMGT_CNTL 0x0015 -#define pllCG_TEST_MACRO_RW_WRITE 0x0016 -#define pllCG_TEST_MACRO_RW_READ 0x0017 -#define pllCG_TEST_MACRO_RW_DATA 0x0018 -#define pllCG_TEST_MACRO_RW_CNTL 0x0019 -#define pllDISP_TEST_MACRO_RW_WRITE 0x001A -#define pllDISP_TEST_MACRO_RW_READ 0x001B -#define pllDISP_TEST_MACRO_RW_DATA 0x001C -#define pllDISP_TEST_MACRO_RW_CNTL 0x001D -#define pllSCLK_CNTL2 0x001E -#define pllMCLK_MISC 0x001F -#define pllTV_PLL_FINE_CNTL 0x0020 -#define pllTV_PLL_CNTL 0x0021 -#define pllTV_PLL_CNTL1 0x0022 -#define pllTV_DTO_INCREMENTS 0x0023 -#define pllSPLL_AUX_CNTL 0x0024 -#define pllMPLL_AUX_CNTL 0x0025 -#define pllP2PLL_CNTL 0x002A -#define pllP2PLL_REF_DIV 0x002B -#define pllP2PLL_DIV_0 0x002C -#define pllPIXCLKS_CNTL 0x002D -#define pllHTOTAL2_CNTL 0x002E -#define pllSSPLL_CNTL 0x0030 -#define pllSSPLL_REF_DIV 0x0031 -#define pllSSPLL_DIV_0 0x0032 -#define pllSS_INT_CNTL 0x0033 -#define pllSS_TST_CNTL 0x0034 -#define pllSCLK_MORE_CNTL 0x0035 - -#define ixMC_PERF_CNTL 0x0000 -#define ixMC_PERF_SEL 0x0001 -#define ixMC_PERF_REGION_0 0x0002 -#define ixMC_PERF_REGION_1 0x0003 -#define ixMC_PERF_COUNT_0 0x0004 -#define ixMC_PERF_COUNT_1 0x0005 -#define ixMC_PERF_COUNT_2 0x0006 -#define ixMC_PERF_COUNT_3 0x0007 -#define ixMC_PERF_COUNT_MEMCH_A 0x0008 -#define ixMC_PERF_COUNT_MEMCH_B 0x0009 -#define ixMC_IMP_CNTL 0x000A -#define ixMC_CHP_IO_CNTL_A0 0x000B -#define ixMC_CHP_IO_CNTL_A1 0x000C -#define ixMC_CHP_IO_CNTL_B0 0x000D -#define ixMC_CHP_IO_CNTL_B1 0x000E -#define ixMC_IMP_CNTL_0 0x000F -#define ixTC_MISMATCH_1 0x0010 -#define ixTC_MISMATCH_2 0x0011 -#define ixMC_BIST_CTRL 0x0012 -#define ixREG_COLLAR_WRITE 0x0013 -#define ixREG_COLLAR_READ 0x0014 -#define ixR300_MC_IMP_CNTL 0x0018 -#define ixR300_MC_CHP_IO_CNTL_A0 0x0019 -#define ixR300_MC_CHP_IO_CNTL_A1 0x001a -#define ixR300_MC_CHP_IO_CNTL_B0 0x001b -#define ixR300_MC_CHP_IO_CNTL_B1 0x001c -#define ixR300_MC_CHP_IO_CNTL_C0 0x001d -#define ixR300_MC_CHP_IO_CNTL_C1 0x001e -#define ixR300_MC_CHP_IO_CNTL_D0 0x001f -#define ixR300_MC_CHP_IO_CNTL_D1 0x0020 -#define ixR300_MC_IMP_CNTL_0 0x0021 -#define ixR300_MC_ELPIDA_CNTL 0x0022 -#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 -#define ixR300_MC_READ_CNTL_CD 0x0024 -#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 -#define ixR300_MC_DEBUG_CNTL 0x0026 -#define ixR300_MC_BIST_CNTL_0 0x0028 -#define ixR300_MC_BIST_CNTL_1 0x0029 -#define ixR300_MC_BIST_CNTL_2 0x002a -#define ixR300_MC_BIST_CNTL_3 0x002b -#define ixR300_MC_BIST_CNTL_4 0x002c -#define ixR300_MC_BIST_CNTL_5 0x002d -#define ixR300_MC_IMP_STATUS 0x002e -#define ixR300_MC_DLL_CNTL 0x002f -#define NB_TOM 0x15C - +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L + +/* CRTC_GEN_CNTL */ +#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L +#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L +#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L +#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L +#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L +#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L +#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L +#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L +#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L +#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L +#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L +#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L +#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L +#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L +#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L +#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L +#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L +#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L +#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L + +/* CRTC2_GEN_CNTL */ +#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L +#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L +#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L +#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L +#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L +#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L +#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L +#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L +#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L +#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L +#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L +#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L +#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L +#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L +#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L +#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L +#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L +#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L +#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L + +/* AGP_CNTL */ +#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL +#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L +#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L +#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L +#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L +#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L +#define AGP_CNTL__EN_2X_STBB 0x00000400L +#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L +#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L +#define AGP_CNTL__SBA_DIS_MASK 0x00001000L +#define AGP_CNTL__SBA_DIS 0x00001000L +#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L +#define AGP_CNTL__AGP_REV_ID 0x00002000L +#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L +#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L +#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L +#define AGP_CNTL__FORCE_INT_VREF 0x00010000L +#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L +#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L +#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L +#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L +#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L +#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L +#define AGP_CNTL__EN_RBFCALM 0x00800000L +#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L +#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L +#define AGP_CNTL__DIS_RBF_MASK 0x02000000L +#define AGP_CNTL__DIS_RBF 0x02000000L +#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L +#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L +#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L +#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L + +/* AGP_CNTL */ +#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 +#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 +#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 +#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a +#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b +#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c +#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d +#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f +#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 +#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 +#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 +#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 +#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 +#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 +#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 +#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a +#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b +#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e + +/* DISP_MISC_CNTL */ +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L +#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L +#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L +#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L +#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L +#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L +#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L +#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L +#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L +#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L +#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L +#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L +#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L +#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L +#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L + +/* DISP_PWR_MAN */ +#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L +#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L +#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L +#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L +#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L +#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L +#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L +#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L +#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L +#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L +#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L +#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L +#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L +#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L +#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L +#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L +#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L +#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L +#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L +#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L +#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L +#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L +#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L +#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L +#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L +#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L +#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L + +/* MC_IND_INDEX */ +#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL +#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L +#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L + +/* MC_IND_DATA */ +#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL + +/* MC_CHP_IO_CNTL_A1 */ +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a +#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c +#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e +#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 +#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f + +/* MC_CHP_IO_CNTL_B1 */ +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a +#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c +#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e +#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 +#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f + +/* MC_CHP_IO_CNTL_A1 */ +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L +#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L + +/* MC_CHP_IO_CNTL_B1 */ +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L +#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L + +/* MEM_SDRAM_MODE_REG */ +#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL +#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L +#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L + +/* MEM_SDRAM_MODE_REG */ +#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 +#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 +#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f + +/* MEM_REFRESH_CNTL */ +#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL +#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L +#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L +#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L +#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L +#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L +#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L +#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L +#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L +#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L +#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L +#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L +#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L +#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L +#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L +#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L +#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L +#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L +#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L +#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L +#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L + +/* MC_STATUS */ +#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L +#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L +#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L +#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L +#define MC_STATUS__MC_IDLE_MASK 0x00000004L +#define MC_STATUS__MC_IDLE 0x00000004L +#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L +#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L +#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L +#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L +#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L +#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L +#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L +#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L +#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L +#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L + +/* MDLL_CKO */ +#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L +#define MDLL_CKO__MCKOA_SLEEP 0x00000001L +#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L +#define MDLL_CKO__MCKOA_RESET 0x00000002L +#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL +#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L +#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L +#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L +#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L +#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L +#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L +#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L +#define MDLL_CKO__MCKOB_SLEEP 0x00010000L +#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L +#define MDLL_CKO__MCKOB_RESET 0x00020000L +#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L +#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L +#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L +#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L +#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L +#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L +#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L + +/* MDLL_RDCKA */ +#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L +#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L +#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L +#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L +#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL +#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L +#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L +#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L +#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L +#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L +#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L +#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L +#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L +#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L +#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L +#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L +#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L +#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L +#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L +#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L +#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L +#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L +#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L +#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L +#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L +#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L + +/* MDLL_RDCKB */ +#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L +#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L +#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L +#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L +#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL +#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L +#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L +#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L +#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L +#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L +#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L +#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L +#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L +#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L +#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L +#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L +#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L +#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L +#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L +#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L +#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L +#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L +#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L +#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L +#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L +#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L + +#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L +#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L +#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L +#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L +#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L +#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L +#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L +#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L + +#define pllCLK_PIN_CNTL 0x0001 +#define pllPPLL_CNTL 0x0002 +#define pllPPLL_REF_DIV 0x0003 +#define pllPPLL_DIV_0 0x0004 +#define pllPPLL_DIV_1 0x0005 +#define pllPPLL_DIV_2 0x0006 +#define pllPPLL_DIV_3 0x0007 +#define pllVCLK_ECP_CNTL 0x0008 +#define pllHTOTAL_CNTL 0x0009 +#define pllM_SPLL_REF_FB_DIV 0x000A +#define pllAGP_PLL_CNTL 0x000B +#define pllSPLL_CNTL 0x000C +#define pllSCLK_CNTL 0x000D +#define pllMPLL_CNTL 0x000E +#define pllMDLL_CKO 0x000F +#define pllMDLL_RDCKA 0x0010 +#define pllMDLL_RDCKB 0x0011 +#define pllMCLK_CNTL 0x0012 +#define pllPLL_TEST_CNTL 0x0013 +#define pllCLK_PWRMGT_CNTL 0x0014 +#define pllPLL_PWRMGT_CNTL 0x0015 +#define pllCG_TEST_MACRO_RW_WRITE 0x0016 +#define pllCG_TEST_MACRO_RW_READ 0x0017 +#define pllCG_TEST_MACRO_RW_DATA 0x0018 +#define pllCG_TEST_MACRO_RW_CNTL 0x0019 +#define pllDISP_TEST_MACRO_RW_WRITE 0x001A +#define pllDISP_TEST_MACRO_RW_READ 0x001B +#define pllDISP_TEST_MACRO_RW_DATA 0x001C +#define pllDISP_TEST_MACRO_RW_CNTL 0x001D +#define pllSCLK_CNTL2 0x001E +#define pllMCLK_MISC 0x001F +#define pllTV_PLL_FINE_CNTL 0x0020 +#define pllTV_PLL_CNTL 0x0021 +#define pllTV_PLL_CNTL1 0x0022 +#define pllTV_DTO_INCREMENTS 0x0023 +#define pllSPLL_AUX_CNTL 0x0024 +#define pllMPLL_AUX_CNTL 0x0025 +#define pllP2PLL_CNTL 0x002A +#define pllP2PLL_REF_DIV 0x002B +#define pllP2PLL_DIV_0 0x002C +#define pllPIXCLKS_CNTL 0x002D +#define pllHTOTAL2_CNTL 0x002E +#define pllSSPLL_CNTL 0x0030 +#define pllSSPLL_REF_DIV 0x0031 +#define pllSSPLL_DIV_0 0x0032 +#define pllSS_INT_CNTL 0x0033 +#define pllSS_TST_CNTL 0x0034 +#define pllSCLK_MORE_CNTL 0x0035 + +#define ixMC_PERF_CNTL 0x0000 +#define ixMC_PERF_SEL 0x0001 +#define ixMC_PERF_REGION_0 0x0002 +#define ixMC_PERF_REGION_1 0x0003 +#define ixMC_PERF_COUNT_0 0x0004 +#define ixMC_PERF_COUNT_1 0x0005 +#define ixMC_PERF_COUNT_2 0x0006 +#define ixMC_PERF_COUNT_3 0x0007 +#define ixMC_PERF_COUNT_MEMCH_A 0x0008 +#define ixMC_PERF_COUNT_MEMCH_B 0x0009 +#define ixMC_IMP_CNTL 0x000A +#define ixMC_CHP_IO_CNTL_A0 0x000B +#define ixMC_CHP_IO_CNTL_A1 0x000C +#define ixMC_CHP_IO_CNTL_B0 0x000D +#define ixMC_CHP_IO_CNTL_B1 0x000E +#define ixMC_IMP_CNTL_0 0x000F +#define ixTC_MISMATCH_1 0x0010 +#define ixTC_MISMATCH_2 0x0011 +#define ixMC_BIST_CTRL 0x0012 +#define ixREG_COLLAR_WRITE 0x0013 +#define ixREG_COLLAR_READ 0x0014 +#define ixR300_MC_IMP_CNTL 0x0018 +#define ixR300_MC_CHP_IO_CNTL_A0 0x0019 +#define ixR300_MC_CHP_IO_CNTL_A1 0x001a +#define ixR300_MC_CHP_IO_CNTL_B0 0x001b +#define ixR300_MC_CHP_IO_CNTL_B1 0x001c +#define ixR300_MC_CHP_IO_CNTL_C0 0x001d +#define ixR300_MC_CHP_IO_CNTL_C1 0x001e +#define ixR300_MC_CHP_IO_CNTL_D0 0x001f +#define ixR300_MC_CHP_IO_CNTL_D1 0x0020 +#define ixR300_MC_IMP_CNTL_0 0x0021 +#define ixR300_MC_ELPIDA_CNTL 0x0022 +#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 +#define ixR300_MC_READ_CNTL_CD 0x0024 +#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 +#define ixR300_MC_DEBUG_CNTL 0x0026 +#define ixR300_MC_BIST_CNTL_0 0x0028 +#define ixR300_MC_BIST_CNTL_1 0x0029 +#define ixR300_MC_BIST_CNTL_2 0x002a +#define ixR300_MC_BIST_CNTL_3 0x002b +#define ixR300_MC_BIST_CNTL_4 0x002c +#define ixR300_MC_BIST_CNTL_5 0x002d +#define ixR300_MC_IMP_STATUS 0x002e +#define ixR300_MC_DLL_CNTL 0x002f +#define NB_TOM 0x15C #endif /* _RADEON_H */ - -- cgit v1.3.1