From 0f58f033d410e91466723bb288d555c710de49fc Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sun, 3 Apr 2022 00:16:59 +0200 Subject: mmc: fsl_esdhc_spl: pre-PBL: check for BOOT signature instead of MBR/DBR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pre-PBL BootROMs (MPC8536E, MPC8569E, P2020, P1011, P1012, P1013, P1020, P1021, P1022) require custom BOOT signature on sector 0 and MBR/DBR signature is not required at all. So add check for BOOT signature and remove check for MBR/DBR. This allows U-Boot SPL to load proper U-Boot on pre-PBL BootROMs platforms also from SD cards which do not have MBR/DBR signature on sector 0. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mmc/fsl_esdhc_spl.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index bee76572ac6..109f558dcad 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -14,6 +14,8 @@ * on SDCard, so we must read the MBR to get the start address and code * length of the u-boot image, then calculate the address of the env. */ +#define ESDHC_BOOT_SIGNATURE_OFF 0x40 +#define ESDHC_BOOT_SIGNATURE 0x424f4f54 #define ESDHC_BOOT_IMAGE_SIZE 0x48 #define ESDHC_BOOT_IMAGE_ADDR 0x50 #define MBRDBR_BOOT_SIG_55 0x1fe @@ -61,6 +63,9 @@ void __noreturn mmc_boot(void) uchar *tmp_buf; u32 blklen; uchar val; +#ifndef CONFIG_SPL_FSL_PBL + u32 val32; +#endif uint i, byte_num; #endif u32 offset, code_len; @@ -94,16 +99,34 @@ void __noreturn mmc_boot(void) hang(); } +#ifdef CONFIG_SPL_FSL_PBL val = *(tmp_buf + MBRDBR_BOOT_SIG_55); if (0x55 != val) { - puts("spl: mmc signature is not valid!!\n"); + puts("spl: mmc MBR/DBR signature is not valid!!\n"); hang(); } val = *(tmp_buf + MBRDBR_BOOT_SIG_AA); if (0xAA != val) { - puts("spl: mmc signature is not valid!!\n"); + puts("spl: mmc MBR/DBR signature is not valid!!\n"); hang(); } +#else + /* + * Booting from On-Chip ROM (eSDHC or eSPI), Document Number: AN3659, Rev. 2, 06/2012. + * Pre-PBL BootROMs (MPC8536E, MPC8569E, P2020, P1011, P1012, P1013, P1020, P1021, P1022) + * require custom BOOT signature on sector 0 and MBR/DBR signature is not required at all. + */ + byte_num = 4; + val32 = 0; + for (i = 0; i < byte_num; i++) { + val = *(tmp_buf + ESDHC_BOOT_SIGNATURE_OFF + i); + val32 = (val32 << 8) + val; + } + if (val32 != ESDHC_BOOT_SIGNATURE) { + puts("spl: mmc BOOT signature is not valid!!\n"); + hang(); + } +#endif byte_num = 4; offset = 0; -- cgit v1.3.1 From a91998d8affc0405bafeade583204f66db81e252 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sun, 3 Apr 2022 00:17:00 +0200 Subject: mmc: fsl_esdhc_spl: pre-PBL: fix determining U-Boot size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In pre-PBL header is stored size of code which BootROM copies from SD card to L2/SRAM. This size has upper limit of L2 cache size. In most cases this is size of U-Boot SPL or size of L2 cache. Therefore this size in pre-PBL header cannot be used for determining size of proper U-Boot. So always use CONFIG_SYS_MMC_U_BOOT_SIZE for determining size of proper U-Boot which stored on SD card. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mmc/fsl_esdhc_spl.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 109f558dcad..b87597a88e1 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -79,7 +79,6 @@ void __noreturn mmc_boot(void) #ifdef CONFIG_FSL_CORENET offset = CONFIG_SYS_MMC_U_BOOT_OFFS; - code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; #else blklen = mmc->read_bl_len; tmp_buf = malloc(blklen); @@ -135,18 +134,11 @@ void __noreturn mmc_boot(void) offset = (offset << 8) + val; } offset += CONFIG_SYS_MMC_U_BOOT_OFFS; - /* Get the code size from offset 0x48 */ - byte_num = 4; - code_len = 0; - for (i = 0; i < byte_num; i++) { - val = *(tmp_buf + ESDHC_BOOT_IMAGE_SIZE + i); - code_len = (code_len << 8) + val; - } - code_len -= CONFIG_SYS_MMC_U_BOOT_OFFS; +#endif /* * Load U-Boot image from mmc into RAM */ -#endif + code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len; err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, -- cgit v1.3.1 From 57d527e753bb5efe89fceea341e7d327bf58e312 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sun, 3 Apr 2022 00:17:01 +0200 Subject: mmc: fsl_esdhc_spl: Call mmc_init() before booting from SD card MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If env is stored on SD card then U-Boot SPL automatically calls mmc_init() before it is going to load proper U-Boot from SD card. If env is not stored on SD card then U-Boot SPL fails to read proper U-Boot from SD card due to missing mmc_init() call. So add missing mmc_init() call into fsl_esdhc_spl's mmc_boot() function. It fixes booting from SD card on P2020 boards without env support in SPL. mmc_init() returns early if card was already initialized, so there is no issue with calling this function more times. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mmc/fsl_esdhc_spl.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index b87597a88e1..0146a231b22 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -77,6 +77,11 @@ void __noreturn mmc_boot(void) hang(); } + if (mmc_init(mmc)) { + puts("spl: mmc device init failed!\n"); + hang(); + } + #ifdef CONFIG_FSL_CORENET offset = CONFIG_SYS_MMC_U_BOOT_OFFS; #else -- cgit v1.3.1 From 48467e47698a27a2a32961bf8bdf19b0e236704c Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sun, 3 Apr 2022 00:20:10 +0200 Subject: mmc: mmc_mode_name() is used also when LOGLEVEL >= LOGL_DEBUG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When CONFIG_LOGLEVEL is set to LOGL_DEBUG or higher then linker throws error about undefined symbol mmc_mode_name(). So compile mmc_mode_name() also when CONFIG_LOGLEVEL is set to LOGL_DEBUG or higher. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mmc/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index f6ccd837aa4..8a7d0739006 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -132,7 +132,7 @@ void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd) } #endif -#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) +#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) || CONFIG_VAL(LOGLEVEL) >= LOGL_DEBUG const char *mmc_mode_name(enum bus_mode mode) { static const char *const names[] = { -- cgit v1.3.1 From 78cdaf405311682281d9c5f58dc0b4455e72da61 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sun, 3 Apr 2022 00:24:26 +0200 Subject: ddr: fsl: Allow to compile it without env support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When env support is disabled then usage of env_get_f() generates linker errors. So do not compile env_get_f() when env support is disabled (for example when disabled only in SPL). Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/ddr/fsl/options.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index c000a45f8ea..9555b9a29d4 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -761,7 +761,9 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, * Extract hwconfig from environment since we have not properly setup * the environment but need it for ddr config params */ +#if CONFIG_IS_ENABLED(ENV_SUPPORT) if (env_get_f("hwconfig", buf, sizeof(buf)) < 0) +#endif buf[0] = '\0'; #if defined(CONFIG_SYS_FSL_DDR3) || \ @@ -1408,7 +1410,9 @@ int fsl_use_spd(void) * Extract hwconfig from environment since we have not properly setup * the environment but need it for ddr config params */ +#if CONFIG_IS_ENABLED(ENV_SUPPORT) if (env_get_f("hwconfig", buf, sizeof(buf)) < 0) +#endif buf[0] = '\0'; /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ -- cgit v1.3.1 From 974f66a4700ca4e433e0e39526ac5bd3012cbe43 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 4 Apr 2022 18:17:18 +0200 Subject: mtd: rawnand: fsl_elbc: Implement RNDOUT command MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is needed for SW ECC. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mtd/nand/raw/fsl_elbc_nand.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index ddfd75d32d0..f8698ec0158 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -312,6 +312,14 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, fsl_elbc_run_command(mtd); return; + /* RNDOUT moves the pointer inside the page */ + case NAND_CMD_RNDOUT: + vdbg("fsl_elbc_cmdfunc: NAND_CMD_RNDOUT, column: 0x%x.\n", + column); + + ctrl->index = column; + return; + /* READOOB reads only the OOB because no ECC is performed. */ case NAND_CMD_READOOB: vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" -- cgit v1.3.1 From da98ddaf732098b30ee4169f4fa01059261fa9ab Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 4 Apr 2022 18:17:19 +0200 Subject: mtd: rawnand: fsl_elbc: Add device tree support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows boards to specify NAND settings via standard DT properties. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mtd/nand/raw/Kconfig | 4 ++++ drivers/mtd/nand/raw/fsl_elbc_nand.c | 42 ++++++++++++++++++++++++++++++++++-- 2 files changed, 44 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 1eab21e2064..d75f371c951 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -158,6 +158,10 @@ config NAND_FSL_ELBC help Enable the Freescale Enhanced Local Bus Controller FCM NAND driver. +config NAND_FSL_ELBC_DT + bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)" + depends on NAND_FSL_ELBC + config NAND_FSL_IFC bool "Support Freescale Integrated Flash Controller NAND driver" select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index f8698ec0158..f8d2bdfb130 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -20,6 +20,10 @@ #include #include +#ifdef CONFIG_NAND_FSL_ELBC_DT +#include +#endif + #ifdef VERBOSE_DEBUG #define DEBUG_ELBC #define vdbg(format, arg...) printf("DEBUG: " format, ##arg) @@ -664,7 +668,7 @@ static void fsl_elbc_ctrl_init(void) elbc_ctrl->addr = NULL; } -static int fsl_elbc_chip_init(int devnum, u8 *addr) +static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node) { struct mtd_info *mtd; struct nand_chip *nand; @@ -712,6 +716,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) elbc_ctrl->chips[priv->bank] = priv; /* fill in nand_chip structure */ + nand->flash_node = flash_node; + /* set up function call table */ nand->read_byte = fsl_elbc_read_byte; nand->write_buf = fsl_elbc_write_buf; @@ -804,6 +810,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) return 0; } +#ifndef CONFIG_NAND_FSL_ELBC_DT + #ifndef CONFIG_SYS_NAND_BASE_LIST #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #endif @@ -816,5 +824,35 @@ void board_nand_init(void) int i; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - fsl_elbc_chip_init(i, (u8 *)base_address[i]); + fsl_elbc_chip_init(i, (u8 *)base_address[i], ofnode_null()); +} + +#else + +static int fsl_elbc_nand_probe(struct udevice *dev) +{ + return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev_ofnode(dev)); +} + +static const struct udevice_id fsl_elbc_nand_dt_ids[] = { + { .compatible = "fsl,elbc-fcm-nand", }, + {} +}; + +U_BOOT_DRIVER(fsl_elbc_nand) = { + .name = "fsl_elbc_nand", + .id = UCLASS_MTD, + .of_match = fsl_elbc_nand_dt_ids, + .probe = fsl_elbc_nand_probe, +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_GET(fsl_elbc_nand), &dev); + if (ret && ret != -ENODEV) + printf("Failed to initialize fsl_elbc_nand NAND controller. (error %d)\n", ret); } +#endif -- cgit v1.3.1 From c9ea9019c5aaeac474d2a243dc1482e1db2b7c6d Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 4 Apr 2022 18:17:20 +0200 Subject: mtd: rawnand: fsl_elbc: Use ECC configuration from device tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initialize ECC configuration after nand_scan_ident() call and only in case nand_scan_ident() have not done it. nand_scan_ident() fills ECC configuration from device tree. Fixes usage of NAND_ECC_SOFT_BCH when it is specified in device tree. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mtd/nand/raw/fsl_elbc_nand.c | 49 +++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index f8d2bdfb130..e734139b5ea 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -737,36 +737,39 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node) nand->controller = &elbc_ctrl->controller; nand_set_controller_data(nand, priv); - nand->ecc.read_page = fsl_elbc_read_page; - nand->ecc.write_page = fsl_elbc_write_page; - nand->ecc.write_subpage = fsl_elbc_write_subpage; - priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT); - /* If CS Base Register selects full hardware ECC then use it */ - if ((br & BR_DECC) == BR_DECC_CHK_GEN) { - nand->ecc.mode = NAND_ECC_HW; - - nand->ecc.layout = (priv->fmr & FMR_ECCM) ? - &fsl_elbc_oob_sp_eccm1 : - &fsl_elbc_oob_sp_eccm0; + ret = nand_scan_ident(mtd, 1, NULL); + if (ret) + return ret; - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.steps = 1; - nand->ecc.strength = 1; - } else { - /* otherwise fall back to software ECC */ + /* If nand_scan_ident() has not selected ecc.mode, do it now */ + if (nand->ecc.mode == NAND_ECC_NONE) { + /* If CS Base Register selects full hardware ECC then use it */ + if ((br & BR_DECC) == BR_DECC_CHK_GEN) { + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = (priv->fmr & FMR_ECCM) ? + &fsl_elbc_oob_sp_eccm1 : + &fsl_elbc_oob_sp_eccm0; + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.steps = 1; + nand->ecc.strength = 1; + } else { + /* otherwise fall back to software ECC */ #if defined(CONFIG_NAND_ECC_BCH) - nand->ecc.mode = NAND_ECC_SOFT_BCH; + nand->ecc.mode = NAND_ECC_SOFT_BCH; #else - nand->ecc.mode = NAND_ECC_SOFT; + nand->ecc.mode = NAND_ECC_SOFT; #endif + } } - ret = nand_scan_ident(mtd, 1, NULL); - if (ret) - return ret; + if (nand->ecc.mode == NAND_ECC_HW) { + nand->ecc.read_page = fsl_elbc_read_page; + nand->ecc.write_page = fsl_elbc_write_page; + nand->ecc.write_subpage = fsl_elbc_write_subpage; + } /* Large-page-specific setup */ if (mtd->writesize == 2048) { @@ -785,7 +788,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node) priv->fmr |= FMR_ECCM; /* adjust ecc setup if needed */ - if ((br & BR_DECC) == BR_DECC_CHK_GEN) { + if (nand->ecc.mode == NAND_ECC_HW) { nand->ecc.steps = 4; nand->ecc.layout = (priv->fmr & FMR_ECCM) ? &fsl_elbc_oob_lp_eccm1 : -- cgit v1.3.1 From 06ef911447fce6c3321e303e968dbb1945b23d38 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 4 Apr 2022 18:17:21 +0200 Subject: mtd: nand: raw: Add support for DT property nand-ecc-algo=bch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Linux kernel DT schema nand-controller.yaml, using DT property nand-ecc-algo=bch is the correct way for specifying BCH as ECC algorithm. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mtd/nand/raw/nand_base.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index a007603df14..6f81257cf1f 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4598,6 +4598,12 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode nod ecc_mode = NAND_ECC_SOFT_BCH; } + if (ecc_mode == NAND_ECC_SOFT) { + str = ofnode_read_string(node, "nand-ecc-algo"); + if (str && !strcmp(str, "bch")) + ecc_mode = NAND_ECC_SOFT_BCH; + } + ecc_strength = ofnode_read_s32_default(node, "nand-ecc-strength", -1); ecc_step = ofnode_read_s32_default(node, -- cgit v1.3.1 From 44564e79eb2eac4b38f5493748018906e7239e2e Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 4 Apr 2022 18:32:13 +0200 Subject: mmc: fsl_esdhc: Define macro ESDHCCTL_SNOOP for Snoop attribute MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mmc/fsl_esdhc.c | 2 +- include/fsl_esdhc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 05a6d0ce156..fdf2cc290e0 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -724,7 +724,7 @@ static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs) setbits_be32(&sysconf->sdhccr, 0x02000000); #else - esdhc_write32(®s->esdhcctl, 0x00000040); + esdhc_write32(®s->esdhcctl, ESDHCCTL_SNOOP); #endif } diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index f86afe5dad8..7ab1460abc6 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -76,6 +76,7 @@ /* eSDHC control register */ #define ESDHCCTL 0x0002e40c +#define ESDHCCTL_SNOOP (0x00000040) #define ESDHCCTL_PCS (0x00080000) #define ESDHCCTL_FAF (0x00040000) -- cgit v1.3.1 From 0980cbba7b3cdec23bafb9cf6dbedc22979a38a1 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 4 Apr 2022 18:33:11 +0200 Subject: mmc: fsl_esdhc_spl: pre-PBL: implement redundancy support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit QorIQ pre-PBL BootROM scans first 24 SD card sectors (each with fixed 512 bytes length) for boot signature. Implement same redundancy behavior in fsl_esdhc_spl driver to allow loading proper U-Boot when boot sector is not the first one. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mmc/fsl_esdhc_spl.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 0146a231b22..ea8f4cd6696 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -20,7 +20,6 @@ #define ESDHC_BOOT_IMAGE_ADDR 0x50 #define MBRDBR_BOOT_SIG_55 0x1fe #define MBRDBR_BOOT_SIG_AA 0x1ff -#define CONFIG_CFG_DATA_SECTOR 0 void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst) @@ -62,11 +61,13 @@ void __noreturn mmc_boot(void) #ifndef CONFIG_FSL_CORENET uchar *tmp_buf; u32 blklen; + u32 blk_off; uchar val; #ifndef CONFIG_SPL_FSL_PBL u32 val32; #endif uint i, byte_num; + u32 sector; #endif u32 offset, code_len; struct mmc *mmc; @@ -86,30 +87,37 @@ void __noreturn mmc_boot(void) offset = CONFIG_SYS_MMC_U_BOOT_OFFS; #else blklen = mmc->read_bl_len; + if (blklen < 512) + blklen = 512; tmp_buf = malloc(blklen); if (!tmp_buf) { puts("spl: malloc memory failed!!\n"); hang(); } + + sector = 0; +again: memset(tmp_buf, 0, blklen); /* * Read source addr from sd card */ - err = mmc->block_dev.block_read(&mmc->block_dev, - CONFIG_CFG_DATA_SECTOR, 1, tmp_buf); + blk_start = (sector * 512) / mmc->read_bl_len; + blk_off = (sector * 512) % mmc->read_bl_len; + blk_cnt = DIV_ROUND_UP(512, mmc->read_bl_len); + err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, tmp_buf); if (err != 1) { puts("spl: mmc read failed!!\n"); hang(); } #ifdef CONFIG_SPL_FSL_PBL - val = *(tmp_buf + MBRDBR_BOOT_SIG_55); + val = *(tmp_buf + blk_off + MBRDBR_BOOT_SIG_55); if (0x55 != val) { puts("spl: mmc MBR/DBR signature is not valid!!\n"); hang(); } - val = *(tmp_buf + MBRDBR_BOOT_SIG_AA); + val = *(tmp_buf + blk_off + MBRDBR_BOOT_SIG_AA); if (0xAA != val) { puts("spl: mmc MBR/DBR signature is not valid!!\n"); hang(); @@ -123,10 +131,13 @@ void __noreturn mmc_boot(void) byte_num = 4; val32 = 0; for (i = 0; i < byte_num; i++) { - val = *(tmp_buf + ESDHC_BOOT_SIGNATURE_OFF + i); + val = *(tmp_buf + blk_off + ESDHC_BOOT_SIGNATURE_OFF + i); val32 = (val32 << 8) + val; } if (val32 != ESDHC_BOOT_SIGNATURE) { + /* BOOT signature may be on the first 24 sectors (each being 512 bytes) */ + if (++sector < 24) + goto again; puts("spl: mmc BOOT signature is not valid!!\n"); hang(); } @@ -135,7 +146,7 @@ void __noreturn mmc_boot(void) byte_num = 4; offset = 0; for (i = 0; i < byte_num; i++) { - val = *(tmp_buf + ESDHC_BOOT_IMAGE_ADDR + i); + val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i); offset = (offset << 8) + val; } offset += CONFIG_SYS_MMC_U_BOOT_OFFS; -- cgit v1.3.1 From 95f8dfe8fb94d8de8abe8f5f7088c7c5ec234dd0 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Thu, 14 Apr 2022 22:52:03 +0200 Subject: pci: fsl: Change compatible string for mpc8548 to "fsl, mpc8548-pcie" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream Linux kernel uses for mpc8548-based PCIe controllers compatible string "fsl,mpc8548-pcie". So change U-Boot fsl PCIe driver and all DTS files to use "fsl,mpc8548-pcie" instead of "fsl,pcie-mpc8548" to be compatible with Linux kernel. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/mpc8548-post.dtsi | 2 +- drivers/pci/pcie_fsl.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi index 2206f2da9fe..97c3ce6e74d 100644 --- a/arch/powerpc/dts/mpc8548-post.dtsi +++ b/arch/powerpc/dts/mpc8548-post.dtsi @@ -27,7 +27,7 @@ }; &pcie { - compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,mpc8548-pcie", "fsl,pcie-fsl-qoriq"; law_trgt_if = <2>; #address-cells = <3>; #size-cells = <2>; diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index f5ba34970f1..59c38f90577 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -646,7 +646,7 @@ static struct fsl_pcie_data t2080_data = { }; static const struct udevice_id fsl_pcie_ids[] = { - { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data }, + { .compatible = "fsl,mpc8548-pcie", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, -- cgit v1.3.1 From 182d45ddff8944e291c805d94a01d7dd29d0d3b6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 22 Apr 2022 15:32:21 +0200 Subject: cpu: 83xx: Add missing dependency on CPU_MPC83XX It looks quite weird that for non PPC platforms cpu driver for MPC83xx can be selected. That's why define proper dependency. Signed-off-by: Michal Simek Reviewed-by: Tom Rini Reviewed-by: Priyanka Jain --- drivers/cpu/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig index 3d5729f6dca..789728167ce 100644 --- a/drivers/cpu/Kconfig +++ b/drivers/cpu/Kconfig @@ -9,7 +9,7 @@ config CPU config CPU_MPC83XX bool "Enable MPC83xx CPU driver" - depends on CPU + depends on CPU && MPC83xx select CLK_MPC83XX help Support CPU cores for SoCs of the MPC83xx series. -- cgit v1.3.1