From 8809a2713b1ceaf3da55d9d785470294f15de06a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 11 Dec 2007 11:46:01 +0100 Subject: rtc: Fix merging problem Signed-off-by: Stefan Roese --- drivers/rtc/x1205.c | 178 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 drivers/rtc/x1205.c (limited to 'drivers') diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c new file mode 100644 index 00000000000..319f0512ca8 --- /dev/null +++ b/drivers/rtc/x1205.c @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * based on a the Linux rtc-x1207.c driver which is: + * Copyright 2004 Karen Spearel + * Copyright 2005 Alessandro Zummo + * + * Information and datasheet: + * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for Xicor/Intersil X1205 RTC + */ + +/* #define DEBUG */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_RTC_X1205) && defined(CONFIG_CMD_DATE) + +#define CCR_SEC 0 +#define CCR_MIN 1 +#define CCR_HOUR 2 +#define CCR_MDAY 3 +#define CCR_MONTH 4 +#define CCR_YEAR 5 +#define CCR_WDAY 6 +#define CCR_Y2K 7 + +#define X1205_REG_SR 0x3F /* status register */ +#define X1205_REG_Y2K 0x37 +#define X1205_REG_DW 0x36 +#define X1205_REG_YR 0x35 +#define X1205_REG_MO 0x34 +#define X1205_REG_DT 0x33 +#define X1205_REG_HR 0x32 +#define X1205_REG_MN 0x31 +#define X1205_REG_SC 0x30 +#define X1205_REG_DTR 0x13 +#define X1205_REG_ATR 0x12 +#define X1205_REG_INT 0x11 +#define X1205_REG_0 0x10 +#define X1205_REG_Y2K1 0x0F +#define X1205_REG_DWA1 0x0E +#define X1205_REG_YRA1 0x0D +#define X1205_REG_MOA1 0x0C +#define X1205_REG_DTA1 0x0B +#define X1205_REG_HRA1 0x0A +#define X1205_REG_MNA1 0x09 +#define X1205_REG_SCA1 0x08 +#define X1205_REG_Y2K0 0x07 +#define X1205_REG_DWA0 0x06 +#define X1205_REG_YRA0 0x05 +#define X1205_REG_MOA0 0x04 +#define X1205_REG_DTA0 0x03 +#define X1205_REG_HRA0 0x02 +#define X1205_REG_MNA0 0x01 +#define X1205_REG_SCA0 0x00 + +#define X1205_CCR_BASE 0x30 /* Base address of CCR */ +#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */ + +#define X1205_SR_RTCF 0x01 /* Clock failure */ +#define X1205_SR_WEL 0x02 /* Write Enable Latch */ +#define X1205_SR_RWEL 0x04 /* Register Write Enable */ + +#define X1205_DTR_DTR0 0x01 +#define X1205_DTR_DTR1 0x02 +#define X1205_DTR_DTR2 0x04 + +#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */ + +static void rtc_write(int reg, u8 val) +{ + i2c_write(CFG_I2C_RTC_ADDR, reg, 2, &val, 1); +} + +/* + * In the routines that deal directly with the x1205 hardware, we use + * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch + * Epoch is initialized as 2000. Time is set to UTC. + */ +void rtc_get(struct rtc_time *tm) +{ + u8 buf[8]; + + i2c_read(CFG_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); + + debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " + "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", + __FUNCTION__, + buf[0], buf[1], buf[2], buf[3], + buf[4], buf[5], buf[6], buf[7]); + + tm->tm_sec = BCD2BIN(buf[CCR_SEC]); + tm->tm_min = BCD2BIN(buf[CCR_MIN]); + tm->tm_hour = BCD2BIN(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */ + tm->tm_mday = BCD2BIN(buf[CCR_MDAY]); + tm->tm_mon = BCD2BIN(buf[CCR_MONTH]); /* mon is 0-11 */ + tm->tm_year = BCD2BIN(buf[CCR_YEAR]) + + (BCD2BIN(buf[CCR_Y2K]) * 100); + tm->tm_wday = buf[CCR_WDAY]; + + debug("%s: tm is secs=%d, mins=%d, hours=%d, " + "mday=%d, mon=%d, year=%d, wday=%d\n", + __FUNCTION__, + tm->tm_sec, tm->tm_min, tm->tm_hour, + tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); +} + +void rtc_set(struct rtc_time *tm) +{ + int i; + u8 buf[8]; + + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + + buf[CCR_SEC] = BIN2BCD(tm->tm_sec); + buf[CCR_MIN] = BIN2BCD(tm->tm_min); + + /* set hour and 24hr bit */ + buf[CCR_HOUR] = BIN2BCD(tm->tm_hour) | X1205_HR_MIL; + + buf[CCR_MDAY] = BIN2BCD(tm->tm_mday); + + /* month, 1 - 12 */ + buf[CCR_MONTH] = BIN2BCD(tm->tm_mon); + + /* year, since the rtc epoch*/ + buf[CCR_YEAR] = BIN2BCD(tm->tm_year % 100); + buf[CCR_WDAY] = tm->tm_wday & 0x07; + buf[CCR_Y2K] = BIN2BCD(tm->tm_year / 100); + + /* this sequence is required to unlock the chip */ + rtc_write(X1205_REG_SR, X1205_SR_WEL); + rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL); + + /* write register's data */ + for (i = 0; i < 8; i++) + rtc_write(X1205_CCR_BASE + i, buf[i]); + + rtc_write(X1205_REG_SR, 0); +} + +void rtc_reset(void) +{ + /* + * Nothing to do + */ +} + +#endif -- cgit v1.3.1 From 12618278688ea9b3d76536960a5ad2e3790fac40 Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Sat, 22 Dec 2007 15:14:00 -0500 Subject: Add driver for STMicroelectronics M41T60 RTC This driver is based on the driver for the M41T11. In the intended application, the RTC will be powered by a large capacitor, rather than a battery. The driver therefore checks to see whether the RTC has lost power. The chip's OUT bit is normally reset from its power-up state. If the OUT bit is read as set, or if the date and time are not valid, then the RTC is assumed to have lost power, and its date and time are reset to 1900-01-01 00:00:00. Support for adjusting the speed of the clock to improve accuracy is provided through an environment variable. Signed-off-by: Larry Johnson --- drivers/rtc/Makefile | 1 + drivers/rtc/m41t60.c | 261 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 262 insertions(+) create mode 100644 drivers/rtc/m41t60.c (limited to 'drivers') diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 1d6016ef87f..e5ee6113506 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -40,6 +40,7 @@ COBJS-y += ds164x.o COBJS-y += ds174x.o COBJS-y += ds3231.o COBJS-y += m41t11.o +COBJS-y += m41t60.o COBJS-y += max6900.o COBJS-y += m48t35ax.o COBJS-y += mc146818.o diff --git a/drivers/rtc/m41t60.c b/drivers/rtc/m41t60.c new file mode 100644 index 00000000000..7c80143e684 --- /dev/null +++ b/drivers/rtc/m41t60.c @@ -0,0 +1,261 @@ +/* + * (C) Copyright 2007 + * Larry Johnson, lrj@acm.org + * + * based on rtc/m41t11.c which is ... + * + * (C) Copyright 2002 + * Andrew May, Viasat Inc, amay@viasat.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * STMicroelectronics M41T60 serial access real-time clock + */ + +/* #define DEBUG 1 */ + +#include +#include +#include +#include + +#if defined(CONFIG_RTC_M41T60) && defined(CFG_I2C_RTC_ADDR) && \ + defined(CONFIG_CMD_DATE) + +static unsigned bcd2bin(uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd(unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +/* + * Convert between century and "century bits" (CB1 and CB0). These routines + * assume years are in the range 1900 - 2299. + */ + +static unsigned char year2cb(unsigned const year) +{ + if (year < 1900 || year >= 2300) + printf("M41T60 RTC: year %d out of range\n", year); + + return (year / 100) & 0x3; +} + +static unsigned cb2year(unsigned const cb) +{ + return 1900 + 100 * ((cb + 1) & 0x3); +} + +/* + * These are simple defines for the chip local to here so they aren't too + * verbose. DAY/DATE aren't nice but that is how they are on the data sheet. + */ +#define RTC_SEC 0x0 +#define RTC_MIN 0x1 +#define RTC_HOUR 0x2 +#define RTC_DAY 0x3 +#define RTC_DATE 0x4 +#define RTC_MONTH 0x5 +#define RTC_YEAR 0x6 + +#define RTC_REG_CNT 7 + +#define RTC_CTRL 0x7 + +#if defined(DEBUG) +static void rtc_dump(char const *const label) +{ + uchar data[8]; + + if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { + printf("I2C read failed in rtc_dump()\n"); + return; + } + printf("RTC dump %s: %02X-%02X-%02X-%02X-%02X-%02X-%02X-%02X\n", + label, data[0], data[1], data[2], data[3], + data[4], data[5], data[6], data[7]); +} +#else +#define rtc_dump(label) +#endif + +static uchar *rtc_validate(void) +{ + /* + * This routine uses the OUT bit and the validity of the time values to + * determine whether there has been an initial power-up since the last + * time the routine was run. It assumes that the OUT bit is not being + * used for any other purpose. + */ + static const uchar daysInMonth[0x13] = { + 0x00, 0x31, 0x29, 0x31, 0x30, 0x31, 0x30, 0x31, + 0x31, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x30, 0x31 + }; + static uchar data[8]; + uchar min, date, month, years; + + rtc_dump("begin validate"); + if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { + printf("I2C read failed in rtc_validate()\n"); + return 0; + } + /* + * If the OUT bit is "1", there has been a loss of power, so stop the + * oscillator so it can be "kick-started" as per data sheet. + */ + if (0x00 != (data[RTC_CTRL] & 0x80)) { + printf("M41T60 RTC clock lost power.\n"); + data[RTC_SEC] = 0x80; + if (i2c_write(CFG_I2C_RTC_ADDR, RTC_SEC, 1, data, 1)) { + printf("I2C write failed in rtc_validate()\n"); + return 0; + } + } + /* + * If the oscillator is stopped or the date is invalid, then reset the + * OUT bit to "0", reset the date registers, and start the oscillator. + */ + min = data[RTC_MIN] & 0x7F; + date = data[RTC_DATE]; + month = data[RTC_MONTH] & 0x3F; + years = data[RTC_YEAR]; + if (0x59 < data[RTC_SEC] || 0x09 < (data[RTC_SEC] & 0x0F) || + 0x59 < min || 0x09 < (min & 0x0F) || + 0x23 < data[RTC_HOUR] || 0x09 < (data[RTC_HOUR] & 0x0F) || + 0x07 < data[RTC_DAY] || 0x00 == data[RTC_DAY] || + 0x12 < month || + 0x99 < years || 0x09 < (years & 0x0F) || + daysInMonth[month] < date || 0x09 < (date & 0x0F) || 0x00 == date || + (0x29 == date && 0x02 == month && + ((0x00 != (years & 0x03)) || + (0x00 == years && 0x00 != (data[RTC_MONTH] & 0xC0))))) { + printf("Resetting M41T60 RTC clock.\n"); + /* + * Set to 00:00:00 1900-01-01 (Monday) + */ + data[RTC_SEC] = 0x00; + data[RTC_MIN] &= 0x80; /* preserve OFIE bit */ + data[RTC_HOUR] = 0x00; + data[RTC_DAY] = 0x02; + data[RTC_DATE] = 0x01; + data[RTC_MONTH] = 0xC1; + data[RTC_YEAR] = 0x00; + data[RTC_CTRL] &= 0x7F; /* reset OUT bit */ + + if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { + printf("I2C write failed in rtc_validate()\n"); + return 0; + } + } + return data; +} + +void rtc_get(struct rtc_time *tmp) +{ + uchar const *const data = rtc_validate(); + + if (!data) + return; + + tmp->tm_sec = bcd2bin(data[RTC_SEC] & 0x7F); + tmp->tm_min = bcd2bin(data[RTC_MIN] & 0x7F); + tmp->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3F); + tmp->tm_mday = bcd2bin(data[RTC_DATE] & 0x3F); + tmp->tm_mon = bcd2bin(data[RTC_MONTH] & 0x1F); + tmp->tm_year = cb2year(data[RTC_MONTH] >> 6) + bcd2bin(data[RTC_YEAR]); + tmp->tm_wday = bcd2bin(data[RTC_DAY] & 0x07) - 1; + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + + debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +void rtc_set(struct rtc_time *tmp) +{ + uchar *const data = rtc_validate(); + + if (!data) + return; + + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + data[RTC_SEC] = (data[RTC_SEC] & 0x80) | (bin2bcd(tmp->tm_sec) & 0x7F); + data[RTC_MIN] = (data[RTC_MIN] & 0X80) | (bin2bcd(tmp->tm_min) & 0X7F); + data[RTC_HOUR] = bin2bcd(tmp->tm_hour) & 0x3F; + data[RTC_DATE] = bin2bcd(tmp->tm_mday) & 0x3F; + data[RTC_MONTH] = bin2bcd(tmp->tm_mon) & 0x1F; + data[RTC_YEAR] = bin2bcd(tmp->tm_year % 100); + data[RTC_MONTH] |= year2cb(tmp->tm_year) << 6; + data[RTC_DAY] = bin2bcd(tmp->tm_wday + 1) & 0x07; + if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, data, RTC_REG_CNT)) { + printf("I2C write failed in rtc_set()\n"); + return; + } +} + +void rtc_reset(void) +{ + uchar *const data = rtc_validate(); + char const *const s = getenv("rtccal"); + + if (!data) + return; + + rtc_dump("begin reset"); + /* + * If environmental variable "rtccal" is present, it must be a hex value + * between 0x00 and 0x3F, inclusive. The five least-significan bits + * represent the calibration magnitude, and the sixth bit the sign bit. + * If these do not match the contents of the hardware register, that + * register is updated. The value 0x00 imples no correction. Consult + * the M41T60 documentation for further details. + */ + if (s) { + unsigned long const l = simple_strtoul(s, 0, 16); + + if (l <= 0x3F) { + if ((data[RTC_CTRL] & 0x3F) != l) { + printf("Setting RTC calibration to 0x%02X\n", + l); + data[RTC_CTRL] &= 0xC0; + data[RTC_CTRL] |= (uchar) l; + } + } else + printf("environment parameter \"rtccal\" not valid: " + "ignoring\n"); + } + /* + * Turn off frequency test. + */ + data[RTC_CTRL] &= 0xBF; + if (i2c_write(CFG_I2C_RTC_ADDR, RTC_CTRL, 1, data + RTC_CTRL, 1)) { + printf("I2C write failed in rtc_reset()\n"); + return; + } + rtc_dump("end reset"); +} +#endif /* CONFIG_RTC_M41T60 && CFG_I2C_RTC_ADDR && CONFIG_CMD_DATE */ -- cgit v1.3.1 From 9e2c347151db5ae8acf5f18b99493cd53e6637e3 Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Thu, 27 Dec 2007 09:52:17 -0500 Subject: Add driver for National Semiconductor LM73 temperature sensor This driver is based on the driver for the LM75. Signed-off-by: Larry Johnson --- drivers/hwmon/Makefile | 1 + drivers/hwmon/lm73.c | 181 +++++++++++++++++++++++++++++++++++++++++++++++++ include/dtt.h | 12 +++- 3 files changed, 193 insertions(+), 1 deletion(-) create mode 100644 drivers/hwmon/lm73.c (limited to 'drivers') diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index cebb2ba6353..32e3f44a916 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -34,6 +34,7 @@ COBJS-y += adm1021.o COBJS-y += ds1621.o COBJS-y += ds1722.o COBJS-y += ds1775.o +COBJS-y += lm73.o COBJS-y += lm75.o COBJS-y += lm81.o diff --git a/drivers/hwmon/lm73.c b/drivers/hwmon/lm73.c new file mode 100644 index 00000000000..f9ae01297bc --- /dev/null +++ b/drivers/hwmon/lm73.c @@ -0,0 +1,181 @@ +/* + * (C) Copyright 2007 + * Larry Johnson, lrj@acm.org + * + * based on dtt/lm75.c which is ... + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * National Semiconductor LM73 Temperature Sensor + */ + +#include + +#ifdef CONFIG_DTT_LM73 +#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \ + (CFG_EEPROM_PAGE_WRITE_BITS < 1) +# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM73" +#endif + +#include +#include + +/* + * Device code + */ +#define DTT_I2C_DEV_CODE 0x48 /* National Semi's LM73 device */ + +int dtt_read(int sensor, int reg) +{ + int dlen; + uchar data[2]; + + /* + * Validate 'reg' param and get register size. + */ + switch (reg) { + case DTT_CONFIG: + case DTT_CONTROL: + dlen = 1; + break; + case DTT_READ_TEMP: + case DTT_TEMP_HIGH: + case DTT_TEMP_LOW: + case DTT_ID: + dlen = 2; + break; + default: + return -1; + } + /* + * Calculate sensor address and register. + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* calculate LM73 addr */ + /* + * Now try to read the register. + */ + if (i2c_read(sensor, reg, 1, data, dlen) != 0) + return -1; + /* + * Handle 2 byte result. + */ + if (2 == dlen) + return ((int)((short)data[1] + (((short)data[0]) << 8))); + + return (int)data[0]; +} /* dtt_read() */ + +int dtt_write(int sensor, int reg, int val) +{ + int dlen; + uchar data[2]; + + /* + * Validate 'reg' param and handle register size + */ + switch (reg) { + case DTT_CONFIG: + case DTT_CONTROL: + dlen = 1; + data[0] = (char)(val & 0xff); + break; + case DTT_TEMP_HIGH: + case DTT_TEMP_LOW: + dlen = 2; + data[0] = (char)((val >> 8) & 0xff); /* MSB first */ + data[1] = (char)(val & 0xff); + break; + default: + return -1; + } + /* + * Calculate sensor address and register. + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* calculate LM73 addr */ + /* + * Write value to register. + */ + return i2c_write(sensor, reg, 1, data, dlen) != 0; +} /* dtt_write() */ + +static int _dtt_init(int sensor) +{ + int val; + + /* + * Validate the Identification register + */ + if (0x0190 != dtt_read(sensor, DTT_ID)) + return 1; + /* + * Setup THIGH (upper-limit) and TLOW (lower-limit) registers + */ + val = CFG_DTT_MAX_TEMP << 7; + if (dtt_write(sensor, DTT_TEMP_HIGH, val)) + return 1; + + val = CFG_DTT_MIN_TEMP << 7; + if (dtt_write(sensor, DTT_TEMP_LOW, val)) + return 1; + /* + * Setup configuraton register + */ + /* config = alert active low, disabled, and reset */ + val = 0x64; + if (dtt_write(sensor, DTT_CONFIG, val)) + return 1; + /* + * Setup control/status register + */ + /* control = temp resolution 0.25C */ + val = 0x00; + if (dtt_write(sensor, DTT_CONTROL, val)) + return 1; + + dtt_read(sensor, DTT_CONTROL); /* clear temperature flags */ + return 0; +} /* _dtt_init() */ + +int dtt_init(void) +{ + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + const char *const header = "DTT: "; + + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf("%s%d FAILED INIT\n", header, i + 1); + else + printf("%s%d is %i C\n", header, i + 1, + dtt_get_temp(sensors[i])); + } + return 0; +} /* dtt_init() */ + +int dtt_get_temp(int sensor) +{ + return (dtt_read(sensor, DTT_READ_TEMP) + 0x0040) >> 7; +} /* dtt_get_temp() */ + +#endif /* CONFIG_DTT_LM73 */ diff --git a/include/dtt.h b/include/dtt.h index 2e8c690158f..4e8aaad87fe 100644 --- a/include/dtt.h +++ b/include/dtt.h @@ -31,7 +31,8 @@ defined(CONFIG_DTT_DS1621) || \ defined(CONFIG_DTT_DS1775) || \ defined(CONFIG_DTT_LM81) || \ - defined(CONFIG_DTT_ADM1021) + defined(CONFIG_DTT_ADM1021) || \ + defined(CONFIG_DTT_LM73) #define CONFIG_DTT /* We have a DTT */ @@ -119,4 +120,13 @@ extern int dtt_get_temp(int sensor); #define DTT_ADM1021_DEVID 0x41 #endif +#if defined(CONFIG_DTT_LM73) +#define DTT_READ_TEMP 0x0 +#define DTT_CONFIG 0x1 +#define DTT_TEMP_HIGH 0x2 +#define DTT_TEMP_LOW 0x3 +#define DTT_CONTROL 0x4 +#define DTT_ID 0x7 +#endif + #endif /* _DTT_H_ */ -- cgit v1.3.1 From ce37422d0002e10490e268392e0c4e3028e52cec Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 2 Jan 2008 14:06:26 +0100 Subject: cfi_flash: Fix bug in flash_isset() to use correct 32bit function This bug was detected on the LWMON5 target which has 2 Intel 16bit wide flash chips connected to a 32bit wide port. Signed-off-by: Stefan Roese --- drivers/mtd/cfi_flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index d1124d3439e..4f61e365e84 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -527,7 +527,7 @@ static int flash_isset (flash_info_t * info, flash_sect_t sect, retval = ((flash_read16(addr) & cword.w) == cword.w); break; case FLASH_CFI_32BIT: - retval = ((flash_read16(addr) & cword.l) == cword.l); + retval = ((flash_read32(addr) & cword.l) == cword.l); break; case FLASH_CFI_64BIT: retval = ((flash_read64(addr) & cword.ll) == cword.ll); -- cgit v1.3.1 From 19580e660cc8da49f16536a8bd78c047c7bc12e5 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 18 Sep 2007 12:37:57 +0800 Subject: mpc83xx: Add the support of MPC837xEMDS board The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu --- Makefile | 10 + board/freescale/mpc837xemds/Makefile | 50 +++ board/freescale/mpc837xemds/config.mk | 28 ++ board/freescale/mpc837xemds/mpc837xemds.c | 144 +++++++ board/freescale/mpc837xemds/pci.c | 65 ++++ cpu/mpc83xx/cpu_init.c | 6 +- cpu/mpc83xx/spd_sdram.c | 7 +- drivers/net/tsec.c | 10 + include/configs/MPC837XEMDS.h | 605 ++++++++++++++++++++++++++++++ 9 files changed, 922 insertions(+), 3 deletions(-) create mode 100644 board/freescale/mpc837xemds/Makefile create mode 100644 board/freescale/mpc837xemds/config.mk create mode 100644 board/freescale/mpc837xemds/mpc837xemds.c create mode 100644 board/freescale/mpc837xemds/pci.c create mode 100644 include/configs/MPC837XEMDS.h (limited to 'drivers') diff --git a/Makefile b/Makefile index 35e90315f4c..dd995d30581 100644 --- a/Makefile +++ b/Makefile @@ -1922,6 +1922,16 @@ MPC8360EMDS_ATM_config: unconfig fi ; @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale +MPC837XEMDS_config \ +MPC837XEMDS_HOST_config: unconfig + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ + if [ "$(findstring _HOST_,$@)" ] ; then \ + echo -n "... PCI HOST " ; \ + echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ + fi ; + @$(MKCONFIG) -a MPC837XEMDS ppc mpc83xx mpc837xemds freescale + sbc8349_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile new file mode 100644 index 00000000000..5ec7a871d4d --- /dev/null +++ b/board/freescale/mpc837xemds/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc837xemds/config.mk b/board/freescale/mpc837xemds/config.mk new file mode 100644 index 00000000000..63c5fc3c348 --- /dev/null +++ b/board/freescale/mpc837xemds/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC837xEMDS +# + +TEXT_BASE = 0xFE000000 diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c new file mode 100644 index 00000000000..0e4ec0213b5 --- /dev/null +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Dave Liu + * + * CREDITS: Kim Phillips contribute to LIBFDT code + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include +#if defined(CONFIG_SPD_EEPROM) +#include +#endif +#if defined(CONFIG_OF_FLAT_TREE) +#include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../common/pq-mds-pib.h" +#endif + +int board_early_init_f(void) +{ + u8 *bcsr = (u8 *)CFG_BCSR; + + /* Enable flash write */ + bcsr[0x9] &= ~0x04; + /* Clear all of the interrupt of BCSR */ + bcsr[0xe] = 0xff; + + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif +int fixed_sdram(void); + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + /* Initialize DDR ECC byte */ + ddr_enable_ecc(msize * 1024 * 1024); +#endif + + /* return total bus DDR size(bytes) */ + return (msize * 1024 * 1024); +} + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = CFG_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + + im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); + +#if (CFG_DDR_SIZE != 512) +#warning Currenly any ddr size other than 512 is not supported +#endif + im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + udelay(50000); + + im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; + udelay(1000); + + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + udelay(1000); + + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + __asm__ __volatile__("sync"); + udelay(1000); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + udelay(2000); + return CFG_DDR_SIZE; +} +#endif /*!CFG_SPD_EEPROM */ + +int checkboard(void) +{ + puts("Board: Freescale MPC837xEMDS\n"); + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_OF_FLAT_TREE) + u32 *p; + int len; + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c new file mode 100644 index 00000000000..ab909790e5d --- /dev/null +++ b/board/freescale/mpc837xemds/pci.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_PCI) +static struct pci_region pci_regions[] = { + { + bus_start: CFG_PCI_MEM_BASE, + phys_start: CFG_PCI_MEM_PHYS, + size: CFG_PCI_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI_MMIO_BASE, + phys_start: CFG_PCI_MMIO_PHYS, + size: CFG_PCI_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCI_IO_BASE, + phys_start: CFG_PCI_IO_PHYS, + size: CFG_PCI_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; + + /* Enable all 5 PCI_CLK_OUTPUTS */ + clk->occr |= 0xf8000000; + udelay(2000); + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + udelay(2000); + + mpc83xx_pci_init(1, reg, 0); +} +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 722497966a1..2b92be01ad9 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -155,6 +155,10 @@ void cpu_init_f (volatile immap_t * im) #ifdef CFG_DDRCDR im->sysconf.ddrcdr = CFG_DDRCDR; #endif + /* Output buffer impedance register */ +#ifdef CFG_OBIR + im->sysconf.obir = CFG_OBIR; +#endif #ifdef CONFIG_QE /* Config QE ioports */ diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index ee2d0385e45..29dd47078ec 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 Freescale Semiconductor, Inc. + * (C) Copyright 2006-2007 Freescale Semiconductor, Inc. * * (C) Copyright 2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -198,6 +198,7 @@ long int spd_sdram() if(spd.mem_type == SPD_MEMTYPE_DDR2) { immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE; } + udelay(50000); #endif /* @@ -576,7 +577,7 @@ long int spd_sdram() if (effective_data_rate == 266 || effective_data_rate == 333) { cpo = 0x7; /* READ_LAT + 5/4 */ } else if (effective_data_rate == 400) { - cpo = 0x9; /* READ_LAT + 7/4 */ + cpo = 0x7; /* READ_LAT + 5/4 */ } else { /* Automatic calibration */ cpo = 0x1f; @@ -705,9 +706,11 @@ long int spd_sdram() * SDRAM Cfg 2 */ odt_cfg = 0; +#ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU if (odt_rd_cfg | odt_wr_cfg) { odt_cfg = 0x2; /* ODT to IOs during reads */ } +#endif if (spd.mem_type == SPD_MEMTYPE_DDR2) { ddr->sdram_cfg2 = (0 | (0 << 26) /* True DQS */ diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index ca6284b7265..108cebd8797 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -674,6 +674,15 @@ uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) return MIIM_CIS8204_EPHYCON_INIT; } +uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) +{ + uint mii_data = read_phy_reg(priv, mii_reg); + + if (priv->flags & TSEC_REDUCED) + mii_data = (mii_data & 0xfff0) | 0x000b; + return mii_data; +} + /* Initialized required registers to appropriate values, zeroing * those we don't care about (unless zero is bad, in which case, * choose a more appropriate value) @@ -1034,6 +1043,7 @@ struct phy_info phy_info_M88E1111S = { (struct phy_cmd[]){ /* config */ /* Reset and configure the PHY */ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1b, 0x848f, &mii_m88e1111s_setmode}, {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h new file mode 100644 index 00000000000..7e344925ce3 --- /dev/null +++ b/include/configs/MPC837XEMDS.h @@ -0,0 +1,605 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Dave Liu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC837X 1 /* MPC837X CPU specific */ +#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ + +/* + * System Clock Setup + */ +#ifdef CONFIG_PCISLAVE +#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ +#else +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66000000 +#endif + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66MHz, then + * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz + */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_6X1 |\ + HRCWL_CORE_TO_CSB_1_5X1) + +#ifdef CONFIG_PCISLAVE +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_AGENT |\ + HRCWH_PCI1_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LDP_CLEAR) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LDP_CLEAR) +#endif + +/* + * eTSEC Clock Config + */ +#define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ +#define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ + +/* + * System IO Config + */ +#define CFG_SICRH 0x00000000 +#define CFG_SICRL 0x00000000 + +/* + * Output Buffer Impedance + */ +#define CFG_OBIR 0x31100000 + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R + +/* + * IMMR new address + */ +#define CFG_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CFG_83XX_DDR_USES_CS0 +#define CFG_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */ + +#undef CONFIG_DDR_ECC /* support DDR ECC function */ +#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ + +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ + +#if defined(CONFIG_SPD_EEPROM) +#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ +#else +/* + * Manually set up DDR parameters + * WHITE ELECTRONIC DESGGNS - W3HG64M72EEU403PD4 SO-DIMM + * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 + */ +#define CFG_DDR_SIZE 512 /* MB */ +#define CFG_DDR_CS0_BNDS 0x0000001f +#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ + | 0x00010000 /* ODT_WR to CSn */ \ + | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) + /* 0x80010202 */ +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ + | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ + | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) + /* 0x00620802 */ +#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ + | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ + | (13 << TIMING_CFG1_REFREC_SHIFT ) \ + | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) + /* 0x3935d322 */ +#define CFG_DDR_TIMING_2 ( ( 2 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | ( 6 << TIMING_CFG2_CPO_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ + | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ + | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ + | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x231088c8 */ +#define CFG_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) + /* 0x03E00100 */ +#define CFG_DDR_SDRAM_CFG 0x43000000 +#define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ +#define CFG_DDR_MODE ( ( 0x0450 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) + /* ODT 150ohm CL=3, AL=2 on SDRAM */ +#define CFG_DDR_MODE2 0x00000000 +#endif + +/* + * Memory test + */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00040000 /* memtest region */ +#define CFG_MEMTEST_END 0x00140000 + +/* + * The reserved memory + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CFG_LBC_LBCR 0x00000000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * BCSR on the Local Bus + */ +#define CFG_BCSR 0xF8000000 +#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ + +#define CFG_BR1_PRELIM (CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ +#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ + +/* + * NAND Flash on the Local Bus + */ +#define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ +#define CFG_BR3_PRELIM ( CFG_NAND_BASE \ + | (2< " +#endif + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_HAS_BD_T 1 +#define CONFIG_OF_HAS_UBOOT_ENV 1 + +#define OF_CPU "PowerPC,837x@0" +#define OF_SOC "soc837x@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc837x@e0000000/serial@4500" + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI_MEM_BASE 0x80000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_MMIO_BASE 0x90000000 +#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE +#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_PHYS 0xE0300000 +#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ + +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE +#define CFG_PCI_SLV_MEM_BUS 0x00000000 +#define CFG_PCI_SLV_MEM_SIZE 0x80000000 + +#ifdef CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ +#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#endif /* CONFIG_PCI */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 3 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC1" + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + +#if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS +#endif + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * Cache Config + */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if defined(CONFIG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CFG_SDRAM_LOWER CFG_SDRAM_BASE +#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) + +#define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +#define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ +#define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* BCSR: cache-inhibit and guarded */ +#define CFG_IBAT3L (CFG_BCSR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT3U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U CFG_IBAT4U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) +#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else +#define CFG_IBAT6L (0) +#define CFG_IBAT6U (0) +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:E0:0C:00:83:79 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:83:78 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc837xemds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From ccf21c311e68d48399eff1e72936052885f6e3f7 Mon Sep 17 00:00:00 2001 From: Joakim Tjernlund Date: Thu, 6 Dec 2007 16:43:40 +0100 Subject: Add support CONFIG_UEC_ETH3 in MPC83xx Signed-off-by: Joakim Tjernlund --- cpu/mpc83xx/cpu.c | 116 +++++++++++++++++++++++++++++++++++++++++++++++++++++- drivers/qe/uec.c | 23 +++++++++++ net/eth.c | 3 ++ 3 files changed, 141 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 8d69d229050..3d3f20a636d 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -520,6 +520,15 @@ static const struct { "local-mac-address", fdt_set_eth0 }, +#elif CFG_UEC1_UCC_NUM == 1 /* UCC2 */ + { "/" OF_QE "/ucc@3000", + "mac-address", + fdt_set_eth0 + }, + { "/" OF_QE "/ucc@3000", + "local-mac-address", + fdt_set_eth0 + }, #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */ { "/" OF_QE "/ucc@2200", "mac-address", @@ -529,10 +538,28 @@ static const struct { "local-mac-address", fdt_set_eth0 }, +#elif CFG_UEC1_UCC_NUM == 3 /* UCC4 */ + { "/" OF_QE "/ucc@3200", + "mac-address", + fdt_set_eth0 + }, + { "/" OF_QE "/ucc@3200", + "local-mac-address", + fdt_set_eth0 + }, #endif #endif /* CONFIG_UEC_ETH1 */ #ifdef CONFIG_UEC_ETH2 -#if CFG_UEC2_UCC_NUM == 1 /* UCC2 */ +#if CFG_UEC2_UCC_NUM == 0 /* UCC1 */ + { "/" OF_QE "/ucc@2000", + "mac-address", + fdt_set_eth1 + }, + { "/" OF_QE "/ucc@2000", + "local-mac-address", + fdt_set_eth1 + }, +#elif CFG_UEC2_UCC_NUM == 1 /* UCC2 */ { "/" OF_QE "/ucc@3000", "mac-address", fdt_set_eth1 @@ -541,6 +568,15 @@ static const struct { "local-mac-address", fdt_set_eth1 }, +#elif CFG_UEC2_UCC_NUM == 2 /* UCC3 */ + { "/" OF_QE "/ucc@2200", + "mac-address", + fdt_set_eth1 + }, + { "/" OF_QE "/ucc@2200", + "local-mac-address", + fdt_set_eth1 + }, #elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */ { "/" OF_QE "/ucc@3200", "mac-address", @@ -552,6 +588,84 @@ static const struct { }, #endif #endif /* CONFIG_UEC_ETH2 */ +#ifdef CONFIG_UEC_ETH3 +#if CFG_UEC3_UCC_NUM == 0 /* UCC1 */ + { "/" OF_QE "/ucc@2000", + "mac-address", + fdt_set_eth2 + }, + { "/" OF_QE "/ucc@2000", + "local-mac-address", + fdt_set_eth2 + }, +#elif CFG_UEC3_UCC_NUM == 1 /* UCC2 */ + { "/" OF_QE "/ucc@3000", + "mac-address", + fdt_set_eth2 + }, + { "/" OF_QE "/ucc@3000", + "local-mac-address", + fdt_set_eth2 + }, +#elif CFG_UEC3_UCC_NUM == 2 /* UCC3 */ + { "/" OF_QE "/ucc@2200", + "mac-address", + fdt_set_eth2 + }, + { "/" OF_QE "/ucc@2200", + "local-mac-address", + fdt_set_eth2 + }, +#elif CFG_UEC3_UCC_NUM == 3 /* UCC4 */ + { "/" OF_QE "/ucc@3200", + "mac-address", + fdt_set_eth2 + }, + { "/" OF_QE "/ucc@3200", + "local-mac-address", + fdt_set_eth2 + }, +#endif +#endif /* CONFIG_UEC_ETH3 */ +#ifdef CONFIG_UEC_ETH4 +#if CFG_UEC4_UCC_NUM == 0 /* UCC1 */ + { "/" OF_QE "/ucc@2000", + "mac-address", + fdt_set_eth3 + }, + { "/" OF_QE "/ucc@2000", + "local-mac-address", + fdt_set_eth3 + }, +#elif CFG_UEC4_UCC_NUM == 1 /* UCC2 */ + { "/" OF_QE "/ucc@3000", + "mac-address", + fdt_set_eth3 + }, + { "/" OF_QE "/ucc@3000", + "local-mac-address", + fdt_set_eth3 + }, +#elif CFG_UEC4_UCC_NUM == 2 /* UCC3 */ + { "/" OF_QE "/ucc@2200", + "mac-address", + fdt_set_eth3 + }, + { "/" OF_QE "/ucc@2200", + "local-mac-address", + fdt_set_eth3 + }, +#elif CFG_UEC4_UCC_NUM == 3 /* UCC4 */ + { "/" OF_QE "/ucc@3200", + "mac-address", + fdt_set_eth3 + }, + { "/" OF_QE "/ucc@3200", + "local-mac-address", + fdt_set_eth3 + }, +#endif +#endif /* CONFIG_UEC_ETH4 */ #endif /* CONFIG_QE */ }; diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index dc2765bb09e..a27c12aa2db 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -69,6 +69,25 @@ static uec_info_t eth2_uec_info = { }; #endif +#ifdef CONFIG_UEC_ETH3 +static uec_info_t eth3_uec_info = { + .uf_info = { + .ucc_num = CFG_UEC3_UCC_NUM, + .rx_clock = CFG_UEC3_RX_CLK, + .tx_clock = CFG_UEC3_TX_CLK, + .eth_type = CFG_UEC3_ETH_TYPE, + }, + .num_threads_tx = UEC_NUM_OF_THREADS_4, + .num_threads_rx = UEC_NUM_OF_THREADS_4, + .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .tx_bd_ring_len = 16, + .rx_bd_ring_len = 16, + .phy_address = CFG_UEC3_PHY_ADDR, + .enet_interface = CFG_UEC3_INTERFACE_MODE, +}; +#endif + static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode) { uec_t *uec_regs; @@ -1237,6 +1256,10 @@ int uec_initialize(int index) } else if (index == 1) { #ifdef CONFIG_UEC_ETH2 uec_info = ð2_uec_info; +#endif + } else if (index == 2) { +#ifdef CONFIG_UEC_ETH3 + uec_info = ð3_uec_info; #endif } else { printf("%s: index is illegal.\n", __FUNCTION__); diff --git a/net/eth.c b/net/eth.c index 3373a052521..d2fced8bbbc 100644 --- a/net/eth.c +++ b/net/eth.c @@ -214,6 +214,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_UEC_ETH2) uec_initialize(1); #endif +#if defined(CONFIG_UEC_ETH3) + uec_initialize(2); +#endif #if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC) fec_initialize(bis); -- cgit v1.3.1 From 95c6bc7d4a3588b452baca610f8c795a83630477 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Thu, 27 Dec 2007 16:55:17 +0100 Subject: Add Epson RX8025 RTC support Signed-off-by: Matthias Fuchs --- drivers/rtc/Makefile | 1 + drivers/rtc/rx8025.c | 227 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 228 insertions(+) create mode 100644 drivers/rtc/rx8025.c (limited to 'drivers') diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index e5ee6113506..8c7f1484b65 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -50,6 +50,7 @@ COBJS-y += mpc8xx.o COBJS-y += pcf8563.o COBJS-y += s3c24x0_rtc.o COBJS-y += rs5c372.o +COBJS-y += rx8025.o COBJS-y += mcfrtc.o COBJS-y += x1205.o diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c new file mode 100644 index 00000000000..6c94ae171d7 --- /dev/null +++ b/drivers/rtc/rx8025.c @@ -0,0 +1,227 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Epson RX8025 RTC driver. + */ + +#include +#include +#include +#include + +#if defined(CONFIG_RTC_RX8025) && defined(CONFIG_CMD_DATE) + +/*---------------------------------------------------------------------*/ +#undef DEBUG_RTC + +#ifdef DEBUG_RTC +#define DEBUGR(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGR(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +#ifndef CFG_I2C_RTC_ADDR +# define CFG_I2C_RTC_ADDR 0x32 +#endif + +/* + * RTC register addresses + */ +#define RTC_SEC_REG_ADDR 0x00 +#define RTC_MIN_REG_ADDR 0x01 +#define RTC_HR_REG_ADDR 0x02 +#define RTC_DAY_REG_ADDR 0x03 +#define RTC_DATE_REG_ADDR 0x04 +#define RTC_MON_REG_ADDR 0x05 +#define RTC_YR_REG_ADDR 0x06 + +#define RTC_CTL1_REG_ADDR 0x0e +#define RTC_CTL2_REG_ADDR 0x0f + +/* + * Control register 1 bits + */ +#define RTC_CTL1_BIT_2412 0x20 + +/* + * Control register 2 bits + */ +#define RTC_CTL2_BIT_PON 0x10 +#define RTC_CTL2_BIT_VDET 0x40 +#define RTC_CTL2_BIT_XST 0x20 +#define RTC_CTL2_BIT_VDSL 0x80 + +/* + * Note: the RX8025 I2C RTC requires register + * reads and write to consist of a single bus + * cycle. It is not allowed to write the register + * address in a first cycle that is terminated by + * a STOP condition. The chips needs a 'restart' + * sequence (start sequence without a prior stop). + * This driver has been written for a 4xx board. + * U-Boot's 4xx i2c driver is currently not capable + * to generate such cycles to some work arounds + * are used. + */ + +/* static uchar rtc_read (uchar reg); */ +#define rtc_read(reg) buf[((reg) + 1) & 0xf] + +static void rtc_write (uchar reg, uchar val); +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin (uchar c); + +/* + * Get the current time from the RTC + */ +void rtc_get (struct rtc_time *tmp) +{ + uchar sec, min, hour, mday, wday, mon, year, ctl2; + uchar buf[16]; + + if (i2c_read(CFG_I2C_RTC_ADDR, 0, 0, buf, 16)) + printf("Error reading from RTC\n"); + + sec = rtc_read(RTC_SEC_REG_ADDR); + min = rtc_read(RTC_MIN_REG_ADDR); + hour = rtc_read(RTC_HR_REG_ADDR); + wday = rtc_read(RTC_DAY_REG_ADDR); + mday = rtc_read(RTC_DATE_REG_ADDR); + mon = rtc_read(RTC_MON_REG_ADDR); + year = rtc_read(RTC_YR_REG_ADDR); + + DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, hour, min, sec); + + /* dump status */ + ctl2 = rtc_read(RTC_CTL2_REG_ADDR); + if (ctl2 & RTC_CTL2_BIT_PON) + printf("RTC: power-on detected\n"); + + if (ctl2 & RTC_CTL2_BIT_VDET) + printf("RTC: voltage drop detected\n"); + + if (!(ctl2 & RTC_CTL2_BIT_XST)) + printf("RTC: oscillator stop detected\n"); + + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon & 0x1F); + tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000); + tmp->tm_wday = bcd2bin (wday & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + + +/* + * Set the RTC + */ +void rtc_set (struct rtc_time *tmp) +{ + DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + if (tmp->tm_year < 1970 || tmp->tm_year > 2069) + printf("WARNING: year should be between 1970 and 2069!\n"); + + rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); + rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); + rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday)); + rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); + rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); + rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); + rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); + + rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412); +} + + +/* + * Reset the RTC. We setting the date back to 1970-01-01. + */ +void rtc_reset (void) +{ + struct rtc_time tmp; + uchar buf[16]; + uchar ctl2; + + if (i2c_read(CFG_I2C_RTC_ADDR, 0, 0, buf, 16)) + printf("Error reading from RTC\n"); + + ctl2 = rtc_read(RTC_CTL2_REG_ADDR); + ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET); + ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL; + rtc_write (RTC_CTL2_REG_ADDR, ctl2); + + tmp.tm_year = 1970; + tmp.tm_mon = 1; + tmp.tm_mday= 1; + tmp.tm_hour = 0; + tmp.tm_min = 0; + tmp.tm_sec = 0; + + rtc_set(&tmp); + + printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n", + tmp.tm_year, tmp.tm_mon, tmp.tm_mday, + tmp.tm_hour, tmp.tm_min, tmp.tm_sec); + + return; +} + + +/* + * Helper functions + */ +static void rtc_write (uchar reg, uchar val) +{ + uchar buf[2]; + buf[0] = reg << 4; + buf[1] = val; + if (i2c_write(CFG_I2C_RTC_ADDR, 0, 0, buf, 2) != 0) + printf("Error writing to RTC\n"); + +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +#endif /* CONFIG_RTC_RX8025 && (CFG_COMMANDS & CFG_CMD_DATE) */ -- cgit v1.3.1 From 6a5e1d75bf106fa157e9ce68bcaf4b13e8a1d214 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 20 Nov 2007 13:14:20 +0100 Subject: Fix endianness conversions in rtl8169 driver It is unclear on what platforms this driver has been tested, since noone up to now defines CONFIG_RTL8169 in the board configuration header. Now it has been fixed for a big-endian mpc8241 based linkstation platform. This patch presents the necessary endianness conversion fixes. Signed-off-by: Guennadi Liakhovetski --- drivers/net/rtl8169.c | 100 +++++++++++++++++++++++--------------------------- 1 file changed, 45 insertions(+), 55 deletions(-) (limited to 'drivers') diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 63ea2cca9b1..1d7f31cead4 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -48,7 +48,10 @@ * * Indent Options: indent -kr -i8 ***************************************************************************/ - +/* + * 26 August 2006 Mihai Georgian + * Modified to use le32_to_cpu and cpu_to_le32 properly + */ #include #include #include @@ -68,12 +71,7 @@ static u32 ioaddr; /* Condensed operations for readability. */ -#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) -#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) - #define currticks() get_timer(0) -#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) -#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) /* media options */ #define MAX_UNITS 8 @@ -102,7 +100,7 @@ static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; #define RTL_MIN_IO_SIZE 0x80 #define TX_TIMEOUT (6*HZ) -/* write/read MMIO register */ +/* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) @@ -218,7 +216,7 @@ enum RTL8169_register_content { PHY_Enable_Auto_Nego = 0x1000, /* PHY_STAT_REG = 1; */ - PHY_Auto_Neco_Comp = 0x0020, + PHY_Auto_Nego_Comp = 0x0020, /* PHY_AUTO_NEGO_REG = 4; */ PHY_Cap_10_Half = 0x0020, @@ -413,23 +411,23 @@ static int rtl_recv(struct eth_device *dev) ioaddr = dev->iobase; cur_rx = tpc->cur_rx; - if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) { - if (!(tpc->RxDescArray[cur_rx].status & RxRES)) { + if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { + if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { unsigned char rxdata[RX_BUF_LEN]; - length = (int) (tpc->RxDescArray[cur_rx]. - status & 0x00001FFF) - 4; + length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. + status) & 0x00001FFF) - 4; memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); NetReceive(rxdata, length); if (cur_rx == NUM_RX_DESC - 1) tpc->RxDescArray[cur_rx].status = - (OWNbit | EORbit) + RX_BUF_SIZE; + cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); else tpc->RxDescArray[cur_rx].status = - OWNbit + RX_BUF_SIZE; + cpu_to_le32(OWNbit + RX_BUF_SIZE); tpc->RxDescArray[cur_rx].buf_addr = - virt_to_bus(tpc->RxBufferRing[cur_rx]); + cpu_to_le32(tpc->RxBufferRing[cur_rx]); } else { puts("Error Rx"); } @@ -454,6 +452,7 @@ static int rtl_send(struct eth_device *dev, volatile void *packet, int length) u8 *ptxb; int entry = tpc->cur_tx % NUM_TX_DESC; u32 len = length; + int ret; #ifdef DEBUG_RTL8169_TX int stime = currticks(); @@ -470,34 +469,38 @@ static int rtl_send(struct eth_device *dev, volatile void *packet, int length) while (len < ETH_ZLEN) ptxb[len++] = '\0'; - tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb); + tpc->TxDescArray[entry].buf_addr = cpu_to_le32(ptxb); if (entry != (NUM_TX_DESC - 1)) { tpc->TxDescArray[entry].status = - (OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ? - len : ETH_ZLEN); + cpu_to_le32((OWNbit | FSbit | LSbit) | + ((len > ETH_ZLEN) ? len : ETH_ZLEN)); } else { tpc->TxDescArray[entry].status = - (OWNbit | EORbit | FSbit | LSbit) | - ((len > ETH_ZLEN) ? length : ETH_ZLEN); + cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | + ((len > ETH_ZLEN) ? len : ETH_ZLEN)); } RTL_W8(TxPoll, 0x40); /* set polling bit */ tpc->cur_tx++; to = currticks() + TX_TIMEOUT; - while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */ + while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) + && (currticks() < to)); /* wait */ if (currticks() >= to) { #ifdef DEBUG_RTL8169_TX puts ("tx timeout/error\n"); printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); #endif - return 0; + ret = 0; } else { #ifdef DEBUG_RTL8169_TX puts("tx done\n"); #endif - return length; + ret = length; } + /* Delay to make net console (nc) work properly */ + udelay(20); + return ret; } static void rtl8169_set_rx_mode(struct eth_device *dev) @@ -564,8 +567,8 @@ static void rtl8169_hw_start(struct eth_device *dev) tpc->cur_rx = 0; - RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray)); - RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray)); + RTL_W32(TxDescStartAddr, tpc->TxDescArray); + RTL_W32(RxDescStartAddr, tpc->RxDescArray); RTL_W8(Cfg9346, Cfg9346_Lock); udelay(10); @@ -603,13 +606,14 @@ static void rtl8169_init_ring(struct eth_device *dev) for (i = 0; i < NUM_RX_DESC; i++) { if (i == (NUM_RX_DESC - 1)) tpc->RxDescArray[i].status = - (OWNbit | EORbit) + RX_BUF_SIZE; + cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); else - tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE; + tpc->RxDescArray[i].status = + cpu_to_le32(OWNbit + RX_BUF_SIZE); tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; tpc->RxDescArray[i].buf_addr = - virt_to_bus(tpc->RxBufferRing[i]); + cpu_to_le32(tpc->RxBufferRing[i]); } #ifdef DEBUG_RTL8169 @@ -623,8 +627,6 @@ RESET - Finish setting up the ethernet interface static void rtl_reset(struct eth_device *dev, bd_t *bis) { int i; - u8 diff; - u32 TxPhyAddr, RxPhyAddr; #ifdef DEBUG_RTL8169 int stime = currticks(); @@ -632,25 +634,14 @@ static void rtl_reset(struct eth_device *dev, bd_t *bis) #endif tpc->TxDescArrays = tx_ring; - if (tpc->TxDescArrays == 0) - puts("Allot Error"); /* Tx Desscriptor needs 256 bytes alignment; */ - TxPhyAddr = virt_to_bus(tpc->TxDescArrays); - diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8)); - TxPhyAddr += diff; - tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff); + tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays + + 255) & ~255); tpc->RxDescArrays = rx_ring; /* Rx Desscriptor needs 256 bytes alignment; */ - RxPhyAddr = virt_to_bus(tpc->RxDescArrays); - diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8)); - RxPhyAddr += diff; - tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff); - - if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) { - puts("Allocate RxDescArray or TxDescArray failed\n"); - return; - } + tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays + + 255) & ~255); rtl8169_init_ring(dev); rtl8169_hw_start(dev); @@ -733,7 +724,7 @@ static int rtl_init(struct eth_device *dev, bd_t *bis) /* Get MAC address. FIXME: read EEPROM */ for (i = 0; i < MAC_ADDR_LEN; i++) - dev->enetaddr[i] = RTL_R8(MAC0 + i); + bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i); #ifdef DEBUG_RTL8169 printf("MAC Address"); @@ -808,7 +799,7 @@ static int rtl_init(struct eth_device *dev, bd_t *bis) /* wait for auto-negotiation process */ for (i = 10000; i > 0; i--) { /* check if auto-negotiation complete */ - if (mdio_read(PHY_STAT_REG) & PHY_Auto_Neco_Comp) { + if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { udelay(100); option = RTL_R8(PHYstatus); if (option & _1000bpsF) { @@ -818,13 +809,12 @@ static int rtl_init(struct eth_device *dev, bd_t *bis) #endif } else { #ifdef DEBUG_RTL8169 - printf - ("%s: %sMbps %s-duplex operation.\n", - dev->name, - (option & _100bps) ? "100" : - "10", - (option & FullDup) ? "Full" : - "Half"); + printf("%s: %sMbps %s-duplex operation.\n", + dev->name, + (option & _100bps) ? "100" : + "10", + (option & FullDup) ? "Full" : + "Half"); #endif } break; @@ -869,7 +859,7 @@ int rtl8169_initialize(bd_t *bis) sprintf (dev->name, "RTL8169#%d", card_number); dev->priv = (void *) devno; - dev->iobase = (int)bus_to_phys(iobase); + dev->iobase = (int)pci_mem_to_phys(devno, iobase); dev->init = rtl_reset; dev->halt = rtl_halt; -- cgit v1.3.1 From 7817cb2083d982923752fe0f12b67c0e7c09a027 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 30 Dec 2007 03:30:46 +0100 Subject: fix comments with new drivers organization Signed-off-by: Marcel Ziswiler --- README | 4 ++-- board/sc3/sc3.c | 2 +- board/ssv/common/cmd_sled.c | 4 ++-- common/env_nand.c | 2 +- cpu/ppc4xx/4xx_pci.c | 2 +- doc/README.generic_usb_ohci | 2 +- doc/README.modnet50 | 4 ++-- drivers/mtd/nand/nand_util.c | 2 +- drivers/net/sk98lin/Makefile | 2 +- drivers/usb/isp116x-hcd.c | 2 +- drivers/usb/usbdcore_mpc8xx.c | 3 ++- drivers/video/cfb_console.c | 8 ++++---- fs/jffs2/jffs2_1pass.c | 2 +- include/configs/CATcenter.h | 2 +- include/configs/MPC8313ERDB.h | 2 +- include/configs/PPChameleonEVB.h | 2 +- include/configs/SX1.h | 2 +- include/configs/integratorcp.h | 2 +- include/configs/omap1510inn.h | 2 +- include/configs/omap2420h4.h | 2 +- include/configs/omap5912osk.h | 2 +- nand_spl/board/amcc/acadia/Makefile | 2 +- nand_spl/board/amcc/bamboo/Makefile | 2 +- nand_spl/board/amcc/sequoia/Makefile | 2 +- 24 files changed, 31 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/README b/README index 9a8b3b903d1..57fc01a9096 100644 --- a/README +++ b/README @@ -924,7 +924,7 @@ The following options need to be configured: (i.e. setenv videomode 317; saveenv; reset;) - "videomode=bootargs" all the video parameters are parsed - from the bootargs. (See drivers/videomodes.c) + from the bootargs. (See drivers/video/videomodes.c) CONFIG_VIDEO_SED13806 @@ -1353,7 +1353,7 @@ The following options need to be configured: CONFIG_FSL_I2C Define this option if you want to use Freescale's I2C driver in - drivers/fsl_i2c.c. + drivers/i2c/fsl_i2c.c. - SPI Support: CONFIG_SPI diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c index 363a77d8a4e..09407647ab1 100644 --- a/board/sc3/sc3.c +++ b/board/sc3/sc3.c @@ -757,7 +757,7 @@ static struct pci_config_table pci_solidcard3_config_table[] = }; /*-------------------------------------------------------------------------+ - | pci_init_board (Called from pci_init() in drivers/pci.c) + | pci_init_board (Called from pci_init() in drivers/pci/pci.c) | | Init the PCI part of the SolidCard III | diff --git a/board/ssv/common/cmd_sled.c b/board/ssv/common/cmd_sled.c index 713ed65568c..2208580faec 100644 --- a/board/ssv/common/cmd_sled.c +++ b/board/ssv/common/cmd_sled.c @@ -32,8 +32,8 @@ * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! * !!!!! !!!!! * !!!!! Next type definition was coming from original !!!!! - * !!!!! status LED driver drivers/status_led.c and !!!!! - * !!!!! should exported for using here. !!!!! + * !!!!! status LED driver drivers/misc/status_led.c !!!!! + * !!!!! and should be exported for using it here. !!!!! * !!!!! !!!!! * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ diff --git a/common/env_nand.c b/common/env_nand.c index 38a07f8993f..ce0a2514db4 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -57,7 +57,7 @@ int nand_legacy_rw (struct nand_chip* nand, int cmd, size_t start, size_t len, size_t * retlen, u_char * buf); -/* info for NAND chips, defined in drivers/nand/nand.c */ +/* info for NAND chips, defined in drivers/mtd/nand/nand.c */ extern nand_info_t nand_info[]; /* references to names in env_common.c */ diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index a68c419b1ba..a5b9690bec3 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -339,7 +339,7 @@ void pci_405gp_init(struct pci_controller *hose) } /* - * drivers/pci.c skips every host bridge but the 405GP since it could + * drivers/pci/pci.c skips every host bridge but the 405GP since it could * be set as an Adapter. * * I (Andrew May) don't know what we should do here, but I don't want diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index 494dd1f5d92..c44c5014743 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -1,7 +1,7 @@ Notes on the the generic USB-OHCI driver ======================================== -This driver (drivers/usb_ohci.[ch]) is the result of the merge of +This driver (drivers/usb/usb_ohci.[ch]) is the result of the merge of various existing OHCI drivers that were basically identical beside cpu/board dependant initalization. This initalization has been moved into cpu/board directories and are called via the hooks below. diff --git a/doc/README.modnet50 b/doc/README.modnet50 index 30338ce8cc7..f7bb254e16d 100644 --- a/doc/README.modnet50 +++ b/doc/README.modnet50 @@ -51,8 +51,8 @@ board/modnet50/lowlevel_init.S .. memory setup for ModNET50 board/modnet50/flash.c .. flash routines board/modnet50/modnet50.c .. some board init stuff -drivers/netarm_eth.c .. ethernet driver for the NET+50 CPU -drivers/netarm_eth.h .. header for ethernet driver +drivers/net/netarm_eth.c .. ethernet driver for the NET+50 CPU +drivers/net/netarm_eth.h .. header for ethernet driver include/configs/modnet50.h .. configuration file for ModNET50 diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 4fd4e166e6a..6c5624a49a4 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -1,5 +1,5 @@ /* - * drivers/nand/nand_util.c + * drivers/mtd/nand/nand_util.c * * Copyright (C) 2006 by Weiss-Electronic GmbH. * All rights reserved. diff --git a/drivers/net/sk98lin/Makefile b/drivers/net/sk98lin/Makefile index a7d4a3b7a7e..8b83faeb15e 100644 --- a/drivers/net/sk98lin/Makefile +++ b/drivers/net/sk98lin/Makefile @@ -20,7 +20,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -# File: drivers/sk98lin/Makefile +# File: drivers/net/sk98lin/Makefile # # Makefile for the SysKonnect SK-98xx device driver. # diff --git a/drivers/usb/isp116x-hcd.c b/drivers/usb/isp116x-hcd.c index b21af10d0ba..ac6703056c9 100644 --- a/drivers/usb/isp116x-hcd.c +++ b/drivers/usb/isp116x-hcd.c @@ -20,7 +20,7 @@ * MA 02111-1307 USA * * - * Derived in part from the SL811 HCD driver "u-boot/drivers/sl811_usb.c" + * Derived in part from the SL811 HCD driver "u-boot/drivers/usb/sl811_usb.c" * (original copyright message follows): * * (C) Copyright 2004 diff --git a/drivers/usb/usbdcore_mpc8xx.c b/drivers/usb/usbdcore_mpc8xx.c index d4c40965656..122793c023c 100644 --- a/drivers/usb/usbdcore_mpc8xx.c +++ b/drivers/usb/usbdcore_mpc8xx.c @@ -3,7 +3,8 @@ * bodonoghue@CodeHermit.ie * * References - * DasUBoot/drivers/usbdcore_omap1510.c, for design and implementation ideas. + * DasUBoot/drivers/usb/usbdcore_omap1510.c, for design and implementation + * ideas. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index bcf877194e0..82cc0c76c30 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -187,9 +187,9 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the /*****************************************************************************/ /* Cursor definition: */ -/* CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/i8042.c) to */ -/* let the cursor blink. Uses the macros CURSOR_OFF */ -/* and CURSOR_ON. */ +/* CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/input/i8042.c) */ +/* to let the cursor blink. Uses the macros */ +/* CURSOR_OFF and CURSOR_ON. */ /* CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No */ /* blinking is provided. Uses the macros CURSOR_SET */ /* and CURSOR_OFF. */ @@ -217,7 +217,7 @@ void console_cursor (int state); #define CURSOR_OFF console_cursor(0); #define CURSOR_SET #ifndef CONFIG_I8042_KBD -#warning Cursor drawing on/off needs timer function s.a. drivers/i8042.c +#warning Cursor drawing on/off needs timer function s.a. drivers/input/i8042.c #endif #else #ifdef CONFIG_CONSOLE_TIME diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index 53166683fd0..69f53eabcf0 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -165,7 +165,7 @@ static struct part_info *current_part; int read_jffs2_nand(size_t start, size_t len, size_t * retlen, u_char * buf, int nanddev); #else -/* info for NAND chips, defined in drivers/nand/nand.c */ +/* info for NAND chips, defined in drivers/mtd/nand/nand.c */ extern nand_info_t nand_info[]; #endif diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 0321650f3d2..1603c9c0bda 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -473,7 +473,7 @@ #define CONFIG_VGA_AS_SINGLE_DEVICE /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ #define CFG_ISA_IO 0xE8000000 -/* see also drivers/videomodes.c */ +/* see also drivers/video/videomodes.c */ #define CFG_DEFAULT_VIDEO_MODE 0x303 #endif diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index c9a9c83f220..7bc4e274367 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -192,7 +192,7 @@ #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ -/* drivers/nand/nand.c */ +/* drivers/mtd/nand/nand.c */ #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index c2aa2cc0984..cf98324344c 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -496,7 +496,7 @@ #define CONFIG_VGA_AS_SINGLE_DEVICE /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ #define CFG_ISA_IO 0xE8000000 -/* see also drivers/videomodes.c */ +/* see also drivers/video/videomodes.c */ #define CFG_DEFAULT_VIDEO_MODE 0x303 #endif diff --git a/include/configs/SX1.h b/include/configs/SX1.h index 05cef873e5f..50ad7dd598d 100644 --- a/include/configs/SX1.h +++ b/include/configs/SX1.h @@ -181,7 +181,7 @@ * FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 69310d4dfbc..e1d1483b719 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -168,7 +168,7 @@ SIB at Block62 End Block62 address 0x24f80000 /* * Move up the U-Boot & monitor area if more flash is fitted. * If this U-Boot is to be run on Integrators with varying flash sizes, - * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG + * drivers/mtd/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG * register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE * - CFG_MONITOR_BASE is set to indicate that the environment is not * embedded in the boot monitor(s) area diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h index 8623ed3cc88..0be46eacec7 100644 --- a/include/configs/omap1510inn.h +++ b/include/configs/omap1510inn.h @@ -179,7 +179,7 @@ * FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 8ae8efeb817..88a3f6eb95b 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -283,7 +283,7 @@ * CFI FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h index 16ce2f61aec..e3bde4ff81d 100644 --- a/include/configs/omap5912osk.h +++ b/include/configs/omap5912osk.h @@ -174,7 +174,7 @@ * FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ #define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index 6e53bea0179..4272108b510 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -97,7 +97,7 @@ $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c -# from drivers/nand directory +# from drivers/mtd/nand directory $(obj)nand_ecc.c: @rm -f $(obj)nand_ecc.c ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile index 3a633fb8871..aed79607090 100644 --- a/nand_spl/board/amcc/bamboo/Makefile +++ b/nand_spl/board/amcc/bamboo/Makefile @@ -79,7 +79,7 @@ $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c -# from drivers/nand directory +# from drivers/mtd/nand directory $(obj)nand_ecc.c: @rm -f $(obj)nand_ecc.c ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile index dfa0ce39e82..93150aad1be 100644 --- a/nand_spl/board/amcc/sequoia/Makefile +++ b/nand_spl/board/amcc/sequoia/Makefile @@ -89,7 +89,7 @@ $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c -# from drivers/nand directory +# from drivers/mtd/nand directory $(obj)nand_ecc.c: @rm -f $(obj)nand_ecc.c ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c -- cgit v1.3.1 From 10c7382bc5d5e64c47f94ac2ca78cc574442e82d Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 30 Dec 2007 03:30:56 +0100 Subject: fix various comments Signed-off-by: Marcel Ziswiler --- cpu/pxa/start.S | 38 +++++++++++++++++++------------------- doc/README.nand | 2 +- drivers/net/ne2000.c | 7 +++---- include/linux/mtd/nand.h | 2 +- nand_spl/nand_boot.c | 2 +- 5 files changed, 25 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index b922485ed33..31f408dfa72 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -57,7 +57,7 @@ _fiq: .word fiq * Startup Code (reset vector) * * do important init only if we don't start from RAM! - * - relocate armboot to ram + * - relocate armboot to RAM * - setup stack * - jump to second stage */ @@ -90,7 +90,7 @@ IRQ_STACK_START: .globl FIQ_STACK_START FIQ_STACK_START: .word 0x0badc0de -#endif +#endif /* CONFIG_USE_IRQ */ /****************************************************************************/ @@ -100,18 +100,18 @@ FIQ_STACK_START: /****************************************************************************/ reset: - mrs r0,cpsr /* set the cpu to SVC32 mode */ + mrs r0,cpsr /* set the CPU to SVC32 mode */ bic r0,r0,#0x1f /* (superviser mode, M=10011) */ orr r0,r0,#0x13 msr cpsr,r0 /* * we do sys-critical inits only at reboot, - * not when booting from ram! + * not when booting from RAM! */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit /* we do sys-critical inits */ -#endif +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ @@ -130,7 +130,7 @@ copy_loop: stmia r1!, {r3-r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end addreee [r2] */ ble copy_loop -#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ +#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ stack_setup: @@ -139,7 +139,7 @@ stack_setup: sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif +#endif /* CONFIG_USE_IRQ */ sub sp, r0, #12 /* leave 3 words for abort-stack */ clear_bss: @@ -172,11 +172,11 @@ _start_armboot: .word start_armboot #undef OSCR #undef OWER #undef OIER -#endif +#endif /* CONFIG_PXA250 || CONFIG_CPU_MONAHANS */ #ifdef CONFIG_PXA250 #undef RCSR #undef CCCR -#endif +#endif /* CONFIG_PXA250 */ /* Interrupt-Controller base address */ IC_BASE: .word 0x40d00000 @@ -197,18 +197,18 @@ OSTIMER_BASE: .word 0x40a00000 #ifdef CONFIG_CPU_MONAHANS # ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO # error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!" -# endif +# endif /* !CFG_MONAHANS_RUN_MODE_OSC_RATIO */ # ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO # define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1 -# endif -#else /* ! CONFIG_CPU_MONAHANS */ +# endif /* !CFG_MONAHANS_TURBO_RUN_MODE_RATIO */ +#else /* !CONFIG_CPU_MONAHANS */ #ifdef CFG_CPUSPEED CC_BASE: .word 0x41300000 #define CCCR 0x00 cpuspeed: .word CFG_CPUSPEED -#else +#else /* !CFG_CPUSPEED */ #error "You have to define CFG_CPUSPEED!!" -#endif +#endif /* CFG_CPUSPEED */ #endif /* CONFIG_CPU_MONAHANS */ /* takes care the CP15 update has taken place */ @@ -225,7 +225,7 @@ cpu_init_crit: ldr r0, IC_BASE mov r1, #0x00 str r1, [r0, #ICMR] -#else +#else /* CONFIG_CPU_MONAHANS */ /* Step 1 - Enable CP6 permission */ mrc p15, 0, r1, c15, c1, 0 @ read CPAR orr r1, r1, #0x40 @@ -244,14 +244,14 @@ cpu_init_crit: ldr r1, =CKENB ldr r2, =(CKENB_6_IRQ) str r2, [r1] -#endif +#endif /* !CONFIG_CPU_MONAHANS */ /* set clock speed */ #ifdef CONFIG_CPU_MONAHANS ldr r0, =ACCR ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK)) str r1, [r0] -#else /* ! CONFIG_CPU_MONAHANS */ +#else /* !CONFIG_CPU_MONAHANS */ #ifdef CFG_CPUSPEED ldr r0, CC_BASE ldr r1, cpuspeed @@ -451,7 +451,7 @@ fiq: bl do_fiq /* effiction fiq_save_user_regs */ irq_restore_user_regs -#else +#else /* !CONFIG_USE_IRQ */ .align 5 irq: @@ -465,7 +465,7 @@ fiq: bad_save_user_regs bl do_fiq -#endif +#endif /* CONFIG_USE_IRQ */ /****************************************************************************/ /* */ diff --git a/doc/README.nand b/doc/README.nand index c5c5ef29e63..647a6b8e67f 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -79,7 +79,7 @@ Commands: nand write.jffs2 addr ofs|partition size Like `write', but blocks that are marked bad are skipped and the - is written to the next block instead. This allows writing writing + data is written to the next block instead. This allows writing a JFFS2 image, as long as the image is short enough to fit even after skipping the bad blocks. Compact images, such as those produced by mkfs.jffs2 should work well, but loading an image copied diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c index c978d62ef30..b1006575394 100644 --- a/drivers/net/ne2000.c +++ b/drivers/net/ne2000.c @@ -839,7 +839,7 @@ void uboot_push_packet_len(int len) { } dp83902a_recv(&pbuf[0], len); - /*Just pass it to the upper layer*/ + /* Just pass it to the upper layer */ NetReceive(&pbuf[0], len); } @@ -902,7 +902,6 @@ int eth_init(bd_t *bd) { } void eth_halt() { - PRINTK("### eth_halt\n"); if(initialized) dp83902a_stop(); @@ -910,8 +909,8 @@ void eth_halt() { } int eth_rx() { -dp83902a_poll(); -return 1; + dp83902a_poll(); + return 1; } int eth_send(volatile void *packet, int length) { diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 49ff80fd3aa..4cc4a7d1bb4 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -129,7 +129,7 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_ #define NAND_ECC_HW3_256 2 /* Hardware ECC 3 byte ECC per 512 Byte data */ #define NAND_ECC_HW3_512 3 -/* Hardware ECC 3 byte ECC per 512 Byte data */ +/* Hardware ECC 6 byte ECC per 512 Byte data */ #define NAND_ECC_HW6_512 4 /* Hardware ECC 8 byte ECC per 512 Byte data */ #define NAND_ECC_HW8_512 6 diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index 840a5965967..e2147cb909b 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -73,7 +73,7 @@ static int nand_is_bad_block(struct mtd_info *mtd, int block) nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); /* - * Read on byte + * Read one byte */ if (this->read_byte(mtd) != 0xff) return 1; -- cgit v1.3.1 From b8ec2385038c094b07ec5b49336289a46b6e9cc6 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 7 Jan 2008 13:31:19 -0600 Subject: 85xx: add ability to upload QE firmware Define the layout of a binary blob that contains a QE firmware and instructions on how to upload it. Add function qe_upload_firmware() to parse the blob and perform the actual upload. Add command-line command "qe fw" to take a firmware blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the 'firmware' device tree node if U-Boot has uploaded a firmware. Fully define 'struct rsp' in immap_qe.h to include the actual RISC Special Registers. Signed-off-by: Timur Tabi --- common/fdt_support.c | 48 ++++++++++ cpu/mpc85xx/fdt.c | 1 + drivers/qe/qe.c | 219 +++++++++++++++++++++++++++++++++++++++++++++ drivers/qe/qe.h | 56 ++++++++++++ include/asm-ppc/immap_qe.h | 33 ++++++- include/fdt_support.h | 1 + 6 files changed, 356 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/common/fdt_support.c b/common/fdt_support.c index 92f1c7f54fd..a13c140cff4 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -30,6 +30,9 @@ #include #include +#ifdef CONFIG_QE +#include "../drivers/qe/qe.h" +#endif /* * Global data (for the gd->bd) */ @@ -614,4 +617,49 @@ void fdt_fixup_ethernet(void *fdt, bd_t *bd) #endif } } + +#ifdef CONFIG_QE +/* + * If a QE firmware has been uploaded, then add the 'firmware' node under + * the 'qe' node. + */ +void fdt_fixup_qe_firmware(void *fdt) +{ + struct qe_firmware_info *qe_fw_info; + int node, ret; + + qe_fw_info = qe_get_firmware_info(); + if (!qe_fw_info) + return; + + node = fdt_path_offset(fdt, "/qe"); + if (node < 0) + return; + + /* We assume the node doesn't exist yet */ + node = fdt_add_subnode(fdt, node, "firmware"); + if (node < 0) + return; + + ret = fdt_setprop(fdt, node, "extended-modes", + &qe_fw_info->extended_modes, sizeof(u64)); + if (ret < 0) + goto error; + + ret = fdt_setprop_string(fdt, node, "id", qe_fw_info->id); + if (ret < 0) + goto error; + + ret = fdt_setprop(fdt, node, "virtual-traps", qe_fw_info->vtraps, + sizeof(qe_fw_info->vtraps)); + if (ret < 0) + goto error; + + return; + +error: + fdt_del_node(fdt, node); +} +#endif + #endif diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 737a6c485a2..0812c89a2e5 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -45,6 +45,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_QE do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); + fdt_fixup_qe_firmware(blob); #endif #ifdef CFG_NS16550 diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 7559e922272..276788c8574 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -21,6 +21,7 @@ */ #include "common.h" +#include #include "asm/errno.h" #include "asm/io.h" #include "asm/immap_qe.h" @@ -248,4 +249,222 @@ int qe_set_mii_clk_src(int ucc_num) return 0; } +/* The maximum number of RISCs we support */ +#define MAX_QE_RISC 2 + +/* Firmware information stored here for qe_get_firmware_info() */ +static struct qe_firmware_info qe_firmware_info; + +/* + * Set to 1 if QE firmware has been uploaded, and therefore + * qe_firmware_info contains valid data. + */ +static int qe_firmware_uploaded; + +/* + * Upload a QE microcode + * + * This function is a worker function for qe_upload_firmware(). It does + * the actual uploading of the microcode. + */ +static void qe_upload_microcode(const void *base, + const struct qe_microcode *ucode) +{ + const u32 *code = base + be32_to_cpu(ucode->code_offset); + unsigned int i; + + if (ucode->major || ucode->minor || ucode->revision) + printf("QE: uploading microcode '%s' version %u.%u.%u\n", + ucode->id, ucode->major, ucode->minor, ucode->revision); + else + printf("QE: uploading microcode '%s'\n", ucode->id); + + /* Use auto-increment */ + out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) | + QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR); + + for (i = 0; i < be32_to_cpu(ucode->count); i++) + out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i])); +} + +/* + * Upload a microcode to the I-RAM at a specific address. + * + * See docs/README.qe_firmware for information on QE microcode uploading. + * + * Currently, only version 1 is supported, so the 'version' field must be + * set to 1. + * + * The SOC model and revision are not validated, they are only displayed for + * informational purposes. + * + * 'calc_size' is the calculated size, in bytes, of the firmware structure and + * all of the microcode structures, minus the CRC. + * + * 'length' is the size that the structure says it is, including the CRC. + */ +int qe_upload_firmware(const struct qe_firmware *firmware) +{ + unsigned int i; + unsigned int j; + u32 crc; + size_t calc_size = sizeof(struct qe_firmware); + size_t length; + const struct qe_header *hdr; + + if (!firmware) { + printf("Invalid address\n"); + return -EINVAL; + } + + hdr = &firmware->header; + length = be32_to_cpu(hdr->length); + + /* Check the magic */ + if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || + (hdr->magic[2] != 'F')) { + printf("Not a microcode\n"); + return -EPERM; + } + + /* Check the version */ + if (hdr->version != 1) { + printf("Unsupported version\n"); + return -EPERM; + } + + /* Validate some of the fields */ + if ((firmware->count < 1) || (firmware->count >= MAX_QE_RISC)) { + printf("Invalid data\n"); + return -EINVAL; + } + + /* Validate the length and check if there's a CRC */ + calc_size += (firmware->count - 1) * sizeof(struct qe_microcode); + + for (i = 0; i < firmware->count; i++) + /* + * For situations where the second RISC uses the same microcode + * as the first, the 'code_offset' and 'count' fields will be + * zero, so it's okay to add those. + */ + calc_size += sizeof(u32) * + be32_to_cpu(firmware->microcode[i].count); + + /* Validate the length */ + if (length != calc_size + sizeof(u32)) { + printf("Invalid length\n"); + return -EPERM; + } + + /* + * Validate the CRC. We would normally call crc32_no_comp(), but that + * function isn't available unless you turn on JFFS support. + */ + crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size)); + if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) { + printf("Firmware CRC is invalid\n"); + return -EIO; + } + + /* + * If the microcode calls for it, split the I-RAM. + */ + if (!firmware->split) { + out_be16(&qe_immr->cp.cercr, + in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR); + } + + if (firmware->soc.model) + printf("Firmware '%s' for %u V%u.%u\n", + firmware->id, be16_to_cpu(firmware->soc.model), + firmware->soc.major, firmware->soc.minor); + else + printf("Firmware '%s'\n", firmware->id); + + /* + * The QE only supports one microcode per RISC, so clear out all the + * saved microcode information and put in the new. + */ + memset(&qe_firmware_info, 0, sizeof(qe_firmware_info)); + strcpy(qe_firmware_info.id, firmware->id); + qe_firmware_info.extended_modes = firmware->extended_modes; + memcpy(qe_firmware_info.vtraps, firmware->vtraps, + sizeof(firmware->vtraps)); + qe_firmware_uploaded = 1; + + /* Loop through each microcode. */ + for (i = 0; i < firmware->count; i++) { + const struct qe_microcode *ucode = &firmware->microcode[i]; + + /* Upload a microcode if it's present */ + if (ucode->code_offset) + qe_upload_microcode(firmware, ucode); + + /* Program the traps for this processor */ + for (j = 0; j < 16; j++) { + u32 trap = be32_to_cpu(ucode->traps[j]); + + if (trap) + out_be32(&qe_immr->rsp[i].tibcr[j], trap); + } + + /* Enable traps */ + out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr)); + } + + return 0; +} + +struct qe_firmware_info *qe_get_firmware_info(void) +{ + return qe_firmware_uploaded ? &qe_firmware_info : NULL; +} + +static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[1], "fw") == 0) { + addr = simple_strtoul(argv[2], NULL, 16); + + if (!addr) { + printf("Invalid address\n"); + return -EINVAL; + } + + /* + * If a length was supplied, compare that with the 'length' + * field. + */ + + if (argc > 3) { + ulong length = simple_strtoul(argv[3], NULL, 16); + struct qe_firmware *firmware = (void *) addr; + + if (length != be32_to_cpu(firmware->header.length)) { + printf("Length mismatch\n"); + return -EINVAL; + } + } + + return qe_upload_firmware((const struct qe_firmware *) addr); + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + qe, 4, 0, qe_cmd, + "qe - QUICC Engine commands\n", + "fw [] - Upload firmware binary at address to " + "the QE,\n\twith optional length verification.\n" + ); + #endif /* CONFIG_QE */ diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index 400b1a6f603..4c96c67ff34 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -222,6 +222,60 @@ typedef enum qe_clock { #define QE_SDEBCR_BA_MASK 0x01FFFFFF +/* Communication Processor */ +#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ +#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ +#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ + +/* I-RAM */ +#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ +#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ + +/* Structure that defines QE firmware binary files. + * + * See doc/README.qe_firmware for a description of these fields. + */ +struct qe_firmware { + struct qe_header { + u32 length; /* Length of the entire structure, in bytes */ + u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ + u8 version; /* Version of this layout. First ver is '1' */ + } header; + u8 id[62]; /* Null-terminated identifier string */ + u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ + u8 count; /* Number of microcode[] structures */ + struct { + u16 model; /* The SOC model */ + u8 major; /* The SOC revision major */ + u8 minor; /* The SOC revision minor */ + } __attribute__ ((packed)) soc; + u8 padding[4]; /* Reserved, for alignment */ + u64 extended_modes; /* Extended modes */ + u32 vtraps[8]; /* Virtual trap addresses */ + u8 reserved[4]; /* Reserved, for future expansion */ + struct qe_microcode { + u8 id[32]; /* Null-terminated identifier */ + u32 traps[16]; /* Trap addresses, 0 == ignore */ + u32 eccr; /* The value for the ECCR register */ + u32 iram_offset; /* Offset into I-RAM for the code */ + u32 count; /* Number of 32-bit words of the code */ + u32 code_offset; /* Offset of the actual microcode */ + u8 major; /* The microcode version major */ + u8 minor; /* The microcode version minor */ + u8 revision; /* The microcode version revision */ + u8 padding; /* Reserved, for alignment */ + u8 reserved[4]; /* Reserved, for future expansion */ + } __attribute__ ((packed)) microcode[1]; + /* All microcode binaries should be located here */ + /* CRC32 should be located here, after the microcode binaries */ +} __attribute__ ((packed)); + +struct qe_firmware_info { + char id[64]; /* Firmware name */ + u32 vtraps[8]; /* Virtual trap addresses */ + u64 extended_modes; /* Extended modes */ +}; + void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data); uint qe_muram_alloc(uint size, uint align); @@ -233,5 +287,7 @@ void qe_reset(void); void qe_assign_page(uint snum, uint para_ram_base); int qe_set_brg(uint brg, uint rate); int qe_set_mii_clk_src(int ucc_num); +int qe_upload_firmware(const struct qe_firmware *firmware); +struct qe_firmware_info *qe_get_firmware_info(void); #endif /* __QE_H__ */ diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index a16a6d3fc5f..39da3771c95 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -513,10 +513,39 @@ typedef struct dbg { u8 res2[0x48]; } __attribute__ ((packed)) dbg_t; -/* RISC Special Registers (Trap and Breakpoint) +/* + * RISC Special Registers (Trap and Breakpoint). These are described in + * the QE Developer's Handbook. */ typedef struct rsp { - u8 fixme[0x100]; + u32 tibcr[16]; /* Trap/instruction breakpoint control regs */ + u8 res0[64]; + u32 ibcr0; + u32 ibs0; + u32 ibcnr0; + u8 res1[4]; + u32 ibcr1; + u32 ibs1; + u32 ibcnr1; + u32 npcr; + u32 dbcr; + u32 dbar; + u32 dbamr; + u32 dbsr; + u32 dbcnr; + u8 res2[12]; + u32 dbdr_h; + u32 dbdr_l; + u32 dbdmr_h; + u32 dbdmr_l; + u32 bsr; + u32 bor; + u32 bior; + u8 res3[4]; + u32 iatr[4]; + u32 eccr; /* Exception control configuration register */ + u32 eicr; + u8 res4[0x100-0xf8]; } __attribute__ ((packed)) rsp_t; typedef struct qe_immap { diff --git a/include/fdt_support.h b/include/fdt_support.h index 58e26abf827..7836f28cda6 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -48,6 +48,7 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size); void fdt_fixup_ethernet(void *fdt, bd_t *bd); int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, const void *val, int len, int create); +void fdt_fixup_qe_firmware(void *fdt); #ifdef CONFIG_OF_HAS_UBOOT_ENV int fdt_env(void *fdt); -- cgit v1.3.1 From d3a6532cbe263d992f49e86ac95bede28e96f9c8 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 10 Jan 2008 00:55:14 +0100 Subject: Coding Style cleanup; update CHANGELOG Signed-off-by: Wolfgang Denk --- CHANGELOG | 372 ++++++++++++++++++++++++++++++++++++++++++++++ api/README | 2 +- api/api.c | 12 +- api/api_net.c | 2 +- api_examples/Makefile | 2 +- api_examples/demo.c | 2 +- api_examples/glue.c | 4 +- board/atum8548/atum8548.c | 6 +- board/atum8548/init.S | 22 +-- board/sbc8548/sbc8548.c | 1 - drivers/qe/qe.c | 18 +-- 11 files changed, 407 insertions(+), 36 deletions(-) (limited to 'drivers') diff --git a/CHANGELOG b/CHANGELOG index 43c0bd5bccd..7b9e34bdd16 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,297 @@ +commit 17a41e4492121ccf9fa2c10c2cb1a6d1c18d74f7 +Author: Kim Phillips +Date: Wed Jan 9 16:56:54 2008 -0600 + + Add QE brg freq and correct qe bus freq fdt update code + + Signed-off-by: Kim Phillips + Signed-off-by: Andy Fleming + +commit 890dfef06c2d169a3356359596890754dfb8ee1c +Author: Andy Fleming +Date: Wed Jan 9 16:34:51 2008 -0600 + + Remove cache config from ATUM8548 and sbc8548 configs + + These boards weren't updated by Kumar's config patch because they + weren't in the tree, yet. + + Signed-off-by: Andy Fleming + +commit b8ec2385038c094b07ec5b49336289a46b6e9cc6 +Author: Timur Tabi +Date: Mon Jan 7 13:31:19 2008 -0600 + + 85xx: add ability to upload QE firmware + + Define the layout of a binary blob that contains a QE firmware and instructions + on how to upload it. Add function qe_upload_firmware() to parse the blob and + perform the actual upload. Add command-line command "qe fw" to take a firmware + blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the + 'firmware' device tree node if U-Boot has uploaded a firmware. Fully define + 'struct rsp' in immap_qe.h to include the actual RISC Special Registers. + + Signed-off-by: Timur Tabi + +commit b009f3eca99bb7b9e6ba6639a8909a138dd5e9fe +Author: Kumar Gala +Date: Tue Jan 8 01:22:21 2008 -0600 + + 85xx: Remove cache config from configs.h + + Either use the standard defines in asm/cache.h or grab the information + at runtime from the L1CFG SPR. + + Also, minor cleanup in cache.h to make the code a bit more readable. + + Signed-off-by: Kumar Gala + +commit b964e9368f45372aaf1da0c13fe56f6d81ae8e96 +Author: robert lazarski +Date: Fri Dec 21 10:39:27 2007 -0500 + + mpc85xx: Add support for ATUM8548 (updated) + + Add support for Instituto Atlantico's ATUM8548 board + + Signed-off-by: robert lazarski + Signed-off-by: Andy Fleming + +commit 7bd6104b71de9bca80ac8e0936003443bb42f2fc +Author: robert lazarski +Date: Fri Dec 21 10:36:37 2007 -0500 + + mpc85xx: Add support for ATUM8548 (updated) + + Add support for Instituto Atlantico's ATUM8548 board + + Signed-off-by: robert lazarski + +commit 9e3ed392d2c8965e24c942b58796c31c644c2f70 +Author: Joe Hamman +Date: Thu Dec 13 06:45:14 2007 -0600 + + mpc85xx: Add support for SBC8548 (updated) + + Add support for Wind River's SBC8548 reference board. + + Signed-off by: Joe Hamman + +commit 11c45ebd46d6517b51b7a92dd52a618b2f4e5586 +Author: Joe Hamman +Date: Thu Dec 13 06:45:08 2007 -0600 + + mpc85xx: Add support for SBC8548 (updated) + + Add support for Wind River's SBC8548 reference board. + + Signed-off by: Joe Hamman + Signed-off by: Andy Fleming + +commit 64d4bcb087c2ece1c4d0de8efe85e0075e5b1594 +Author: Anton Vorontsov +Date: Mon Oct 22 19:58:19 2007 +0400 + + MPC8568E-MDS: set up QE pario for UART1 + + To use UART1 on the MPC8568E-MDS, QE pario pins PC[0:3] should + be set up appropriately. + + Signed-off-by: Anton Vorontsov + +commit ad162249cb371e9e38971676f09be791e5f3cf4a +Author: Anton Vorontsov +Date: Mon Oct 22 18:12:46 2007 +0400 + + MPC8568E-MDS: reset UCCs to use them reliably + + In order to use GETH1 and GETH2 on the MPC8568E-MDS, we should reset + UCCs. + + p.s Similar code exists in the Linux kernel board file (for capability + reasons with older U-Boots), but should be removed some day. + + Signed-off-by: Anton Vorontsov + +commit 2146cf56821c3364786ca94a7306008c5824b238 +Author: Kumar Gala +Date: Wed Dec 19 01:18:15 2007 -0600 + + Reworked FSL Book-E TLB macros to be more readable + + The old macros made it difficult to know what WIMGE and perm bits + were set for a TLB entry. Actually use the bit masks for these items + since they are only a single bit. + + Also moved the macros into mmu.h out of e500.h since they aren't specific + to e500. + + Signed-off-by: Kumar Gala + +commit 1d47273d46925929f8f2c1913cd96d7257aade88 +Author: Kumar Gala +Date: Tue Dec 18 23:21:51 2007 -0600 + + Use FSL Book-E MMU macros from Linux Kernel + + Grab the FSL Book-E MAS register macros from Linux. Also added + defines for page sizes up to 4TB and removed SHAREN since it doesnt + really exist. + + Signed-off-by: Kumar Gala + +commit 02df4a270f817ef6ec39047a01b55fecdc5f3b37 +Author: Andy Fleming +Date: Wed Jan 9 13:51:32 2008 -0600 + + Fix my own merge stupidity + + Way back in August I merged Heiko's patch: + 566a494f592: [PCS440EP] upgrade the PCS440EP board + + with Jon's CONFIG_COMMANDS patches. + + This was done in commit: 6bf6f114dcdd97ec3f80c2761ed40e31229d6b78 + + However, in the process, I left out some of Heiko's good changes. + + Now Heiko's and Jon's patches are properly merged in fat_register_device() + + Signed-off-by: Andy Fleming + +commit 6636b62a6efc7f14e6e788788631ae7a7fca4537 +Author: James Yang +Date: Wed Jan 9 11:17:49 2008 -0600 + + Expose parse_line() globally. + + Add new function readline_into_buffer() that allows the + output of readline to be put into a pointer to char buffer. + + This refactoring allows other functions besides the + main command loop to also use the same input mechanism. + + Signed-off-by: James Yang + Acked-by: Jon Loeliger + +commit 7ca90513486abd4ae50bd1b7403f47cc58c5ad25 +Author: Guennadi Liakhovetski +Date: Wed Jan 9 01:15:25 2008 +0100 + + trivial: fix consequences of a bad merge + + Fix what looks like a merge artifact. + + Signed-off-by: Guennadi Liakhovetski + +commit 4785a694c0045996ccf0ac5b8edf531efc1b730e +Author: Zhang Wei +Date: Thu Jan 3 10:51:15 2008 +0800 + + Add Ctrl combo key support to usb keyboard driver. + + Ctrl combo key support is added, which is very useful to input Ctrl-C + for interrupt current job. + Also add usb_event_poll() calling to usb_kbd_testc(), which can get + key input when tstc() is called. + + Signed-off-by: Zhang Wei + +commit 10c7382bc5d5e64c47f94ac2ca78cc574442e82d +Author: Marcel Ziswiler +Date: Sun Dec 30 03:30:56 2007 +0100 + + fix various comments + + Signed-off-by: Marcel Ziswiler + +commit 7817cb2083d982923752fe0f12b67c0e7c09a027 +Author: Marcel Ziswiler +Date: Sun Dec 30 03:30:46 2007 +0100 + + fix comments with new drivers organization + + Signed-off-by: Marcel Ziswiler + +commit a9b410dc7d2a4721c408b13abfc037988150f145 +Author: Shinya Kuribayashi +Date: Fri Dec 28 12:50:59 2007 +0900 + + Remove the obsolete terse version of do_mii() + + We now have more useful version of do_mii() and everybody use it. + Gerald Van Baren says: + + > When I originally wrote the mii command 6(!) years ago, I wrote a + > verbose version that printed human readable decomposition of the flags, + > etc., and a terse one that didn't print as much stuff and thus had a + > smaller memory footprint. + > + > It sounds like the terse version has withered and died, apparently + > people are only using the verbose version (which is very understandable, + > I do myself). + + Signed-off-by: Shinya Kuribayashi + Signed-off-by: Gerald Van Baren + +commit 01c687aa6e065bd4faf80f723361e798941dd6b0 +Author: Mike Frysinger +Date: Thu Dec 27 13:42:56 2007 -0500 + + Do not reference sha1.c when building mkimage. + + remove sha1.o from mkimage linking since it isn't actually used. + + Signed-Off-By: Mike Frysinger + +commit b9173af73e524d37c812f210173cf83385c5171a +Author: Shinya Kuribayashi +Date: Thu Dec 27 15:39:54 2007 +0900 + + common/cmd_mii.c: Add sanity argc check + + If type mii command without arguments, we suffer from uninitialized argv[] + entries; for example we MIPS get stuck by TLB error. + + Signed-off-by: Shinya Kuribayashi + +commit 500856eb1707ed17d9204baa61dd59948d3b2899 +Author: Rafal Jaworowski +Date: Wed Jan 9 19:39:36 2008 +0100 + + API for external applications. + + This is an API for external (standalone) applications running on top of + U-Boot, and is meant to be more extensible and robust than the existing + jumptable mechanism. It is similar to UNIX syscall approach. See api/README + for more details. + + Included is the demo application using this new framework (api_examples). + + Please note this is still an experimental feature, and is turned off by + default. + + Signed-off-by: Rafal Jaworowski + +commit 26a41790f8eba19ad450e18ae91351daf485b3e2 +Author: Rafal Jaworowski +Date: Wed Jan 9 18:05:27 2008 +0100 + + Globalize envmatch() + + The newly introduced API (routines related to env vars) will need to call + it. + + Signed-off-by: Rafal Zabdyr + +commit 6007f3251c0967adc13f2ed8be1b924ddc30124d +Author: Wolfgang Denk +Date: Wed Jan 9 15:14:46 2008 +0100 + + Coding Style cleanup, update CHANGELOG + + Signed-off-by: Wolfgang Denk + commit fc6414eca55f1fc108fb12fc8cdc43bd8b4463f9 Author: Mike Frysinger Date: Tue Dec 18 04:29:55 2007 -0500 @@ -98,6 +392,20 @@ Date: Tue Nov 20 13:14:20 2007 +0100 Signed-off-by: Guennadi Liakhovetski +commit 58694f9709c0c3e3178e349ae748d98cfb0c639a +Author: Zhang Wei +Date: Thu Jan 3 10:51:15 2008 +0800 + + Add Ctrl combo key support to usb keyboard driver. + + Ctrl combo key support is added, which is very useful to input Ctrl-C + for interrupt current job. + Also add usb_event_poll() calling to usb_kbd_testc(), which can get + key input when tstc() is called. + + Signed-off-by: Zhang Wei + Signed-off-by: Markus Klotzbuecher + commit 07eb02687f008721974a2fb54cd7fdc28033ab3c Author: Wolfgang Denk Date: Wed Jan 9 13:43:38 2008 +0100 @@ -411,6 +719,28 @@ Date: Tue Jan 8 11:13:09 2008 +0100 Signed-off-by: Matthias Fuchs +commit c83d7ca4dadd44ae430235077f63b64a11f36f6e +Author: Wolfgang Denk +Date: Tue Jan 8 22:58:27 2008 +0100 + + Fix compile problem with new env code. + + Signed-off-by: Wolfgang Denk + +commit 6de66b35426312a21174a9bf0576a094e2904bea +Author: Markus Klotzbücher +Date: Tue Nov 27 10:23:20 2007 +0100 + + tools: fix fw_printenv tool to compile again + + This patch updates the fw_printenv/fw_setenv userspace tool to include + the correct MTD header in order to compile against current kernel + headers. Backward compatibility is preserved by introducing an option + MTD_VERSION which can be set to "old" for compilation using the old MTD + headers. Along with this a number of warnings are fixed. + + Signed-off-by: Markus Klotzbuecher + commit ad3006fe7e84667021753b74247b0bafd97ba35f Author: Gerald Van Baren Date: Mon Jan 7 23:47:32 2008 -0500 @@ -4521,6 +4851,48 @@ Date: Wed Oct 3 07:34:10 2007 +0200 Signed-off-by: Stefan Roese +commit 245a362ad3c0c1b84fccc9fec7b623eb14f6e502 +Author: Marian Balakowicz +Date: Wed Oct 24 01:37:36 2007 +0200 + + TQM5200: Call usb_cpu_init() during board init + + usb_cpu_init() configures GPS USB pins, clocks, etc. and + is required for proper operation of kernel USB subsystem. + This setup was previously done in the kernel by the fixup + code which is being removed, thus low level init must be + done by U-boot now. + + Signed-off-by: Marian Balakowicz + Signed-off-by: Markus Klotzbuecher + +commit b5af773f8d92677e06f3295b45557c9d0a487c24 +Author: Zhang Wei +Date: Thu Oct 25 17:51:27 2007 +0800 + + Fix the issue of usb_kbd driver missing the scan code of key 'z'. + + The scan code of the key 'z' is 0x1d, which should be handled. + + The change has be tested on NOVATEK USB keyboard and ULI PCI OHCI + controller. + + Signed-off-by: Zhang Wei + Signed-off-by: Markus Klotzbuecher + +commit 85ac988e86f9414fa645b0148dc66c3520a1eb84 +Author: Rodolfo Giometti +Date: Mon Oct 15 11:59:17 2007 +0200 + + PXA USB OHCI: "usb stop" implementation. + + Some USB keys need to be switched off before loading the kernel + otherwise they can remain in an undefined status which prevents them + to be correctly recognized by the kernel. + + Signed-off-by: Rodolfo Giometti + Signed-off-by: Markus Klotzbuecher + commit 31548249decf18a6b877a18436b6139dd483fe4a Author: Justin Flammia Date: Mon Oct 29 17:40:35 2007 -0400 diff --git a/api/README b/api/README index c8f9c457c44..6df225f584b 100644 --- a/api/README +++ b/api/README @@ -22,7 +22,7 @@ U-Boot machine/arch independent API for external apps - the U-Boot integral part of the API is meant to be thin and non-intrusive, leaving as much processing as possible on the consumer application side, for example it doesn't keep states, but relies on hints from the app and - so on + so on - optional (CONFIG_API) diff --git a/api/api.c b/api/api.c index 10f83eb691c..0598d9082dc 100644 --- a/api/api.c +++ b/api/api.c @@ -231,7 +231,7 @@ static int API_dev_enum(va_list ap) /* start over - clean up enumeration */ dev_enum_reset(); /* XXX shouldn't the name contain 'stor'? */ debugf("RESTART ENUM\n"); - + /* net device enumeration first */ if (dev_enum_net(di)) return 0; @@ -365,7 +365,7 @@ static int API_dev_write(va_list ap) return API_EINVAL; if (di->type & DEV_TYP_STOR) - /* + /* * write to storage is currently not supported by U-Boot: * no storage device implements block_write() method */ @@ -523,7 +523,7 @@ static int API_env_enum(va_list ap) char *last, **next; last = (char *)va_arg(ap, u_int32_t); - + if ((next = (char **)va_arg(ap, u_int32_t)) == NULL) return API_EINVAL; @@ -540,7 +540,7 @@ static int API_env_enum(va_list ap) return 0; } } - + if (envmatch((uchar *)last, i) < 0) continue; @@ -567,7 +567,7 @@ static cfp_t calls_table[API_MAXCALL] = { NULL, }; * serviced until finished. * * e.g. syscall(1, int *, u_int32_t, u_int32_t, u_int32_t, u_int32_t); - * + * * call: syscall number * * retval: points to the return value placeholder, this is the place the @@ -655,7 +655,7 @@ void platform_set_mr(struct sys_info *si, unsigned long start, unsigned long siz if (!si->mr || !size || (flags == 0)) return; - + /* find free slot */ for (i = 0; i < si->mr_no; i++) if (si->mr[i].flags == 0) { diff --git a/api/api_net.c b/api/api_net.c index 9b20a1740c7..9611ab0dda9 100644 --- a/api/api_net.c +++ b/api/api_net.c @@ -75,7 +75,7 @@ int dev_close_net(void *cookie) return 0; } -/* +/* * There can only be one active eth interface at a time - use what is * currently set to eth_current */ diff --git a/api_examples/Makefile b/api_examples/Makefile index 5812bcd3370..cb49a9ea797 100644 --- a/api_examples/Makefile +++ b/api_examples/Makefile @@ -71,7 +71,7 @@ $(BIN): $(obj)%.bin: $(obj)% $(OBJCOPY) -O binary $< $@ 2>/dev/null -$(obj)crc32.c: +$(obj)crc32.c: @rm -f $(obj)crc32.c ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c diff --git a/api_examples/demo.c b/api_examples/demo.c index a4aeef183b5..eae9712b71f 100644 --- a/api_examples/demo.c +++ b/api_examples/demo.c @@ -88,7 +88,7 @@ int main(int argc, char *argv[]) /* enumerate devices */ printf("\n*** Enumerate devices ***\n"); devs_no = ub_dev_enum(); - + printf("Number of devices found: %d\n", devs_no); if (devs_no == 0) return -1; diff --git a/api_examples/glue.c b/api_examples/glue.c index 75983691fde..2bf47ae3d21 100644 --- a/api_examples/glue.c +++ b/api_examples/glue.c @@ -150,7 +150,7 @@ struct sys_info * ub_get_sys_info(void) * timing * ****************************************/ - + void ub_udelay(unsigned long usec) { syscall(API_UDELAY, NULL, &usec); @@ -298,7 +298,7 @@ int ub_dev_read(int handle, void *buf, lbasize_t len, lbastart_t start) if (!syscall(API_DEV_READ, &err, di, buf, &len, &start, &act_len)) return -1; - if (err) + if (err) return err; if (act_len != len) diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 4d7dc7728cb..f11abd816bb 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -140,7 +140,7 @@ testdram(void) for (p = pstart; p < pend; p++) { printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p); *p = 0xaaaaaaaa; - } + } for (p = pstart; p < pend; p++) { if (*p != 0xaaaaaaaa) { @@ -191,7 +191,7 @@ pci_init_board(void) debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", devdisr, io_sel, host_agent); - /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */ + /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */ gur->clkocr |= MPC85xx_ATUM_CLKOCR; if (io_sel & 1) { @@ -376,7 +376,7 @@ pci_init_board(void) int last_stage_init(void) { - int ic = icache_status (); + int ic = icache_status (); printf ("icache_status: %d\n", ic); return 0; } diff --git a/board/atum8548/init.S b/board/atum8548/init.S index a410e2e568c..654a5699078 100644 --- a/board/atum8548/init.S +++ b/board/atum8548/init.S @@ -70,7 +70,7 @@ tlb1_entry: /* * Number of TLB0 and TLB1 entries in the following table */ - .long (2f-1f)/16 + .long (2f-1f)/16 1: #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) @@ -182,15 +182,15 @@ tlb1_entry: /* * LAW(Local Access Window) configuration: * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCIe MEM 512M - * 0xc000_0000 0xdfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe10f_ffff PCI1 IO 1M - * 0xe280_0000 0xe20f_ffff PCI2 IO 1M - * 0xe300_0000 0xe30f_ffff PCIe IO 1M - * 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M + * 0xc000_0000 0xdfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe10f_ffff PCI1 IO 1M + * 0xe280_0000 0xe20f_ffff PCI2 IO 1M + * 0xe300_0000 0xe30f_ffff PCIe IO 1M + * 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. @@ -227,7 +227,7 @@ law_entry: .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M) - /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 5e258f5d691..65052e60c87 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -566,4 +566,3 @@ ft_board_setup(void *blob, bd_t *bd) #endif } #endif - diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 276788c8574..c802014a50b 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) { - u32 cecr; + u32 cecr; if (cmd == QE_RESET) { out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG)); @@ -357,10 +357,10 @@ int qe_upload_firmware(const struct qe_firmware *firmware) return -EPERM; } - /* - * Validate the CRC. We would normally call crc32_no_comp(), but that - * function isn't available unless you turn on JFFS support. - */ + /* + * Validate the CRC. We would normally call crc32_no_comp(), but that + * function isn't available unless you turn on JFFS support. + */ crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size)); if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) { printf("Firmware CRC is invalid\n"); @@ -438,10 +438,10 @@ static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return -EINVAL; } - /* - * If a length was supplied, compare that with the 'length' - * field. - */ + /* + * If a length was supplied, compare that with the 'length' + * field. + */ if (argc > 3) { ulong length = simple_strtoul(argv[3], NULL, 16); -- cgit v1.3.1 From 422b1a01602b6e2fbf8444a1192c7ba31461fd4c Mon Sep 17 00:00:00 2001 From: Ben Warren Date: Wed, 9 Jan 2008 18:15:53 -0500 Subject: Fix Ethernet init() return codes Change return values of init() functions in all Ethernet drivers to conform to the following: >=0: Success <0: Failure All drivers going forward should return 0 on success. Current drivers that return 1 on success were left as-is to minimize changes. Signed-off-by: Ben Warren Acked-by: Stefan Roese Acked-by: Jean-Christophe PLAGNIOL-VILLARD Acked-by: Kim Phillips Acked-by: Haavard Skinnemoen Acked-By: Timur Tabi --- cpu/ixp/npe/npe.c | 8 ++++---- cpu/mpc8xx/fec.c | 4 ++-- drivers/net/dc2114x.c | 4 ++-- drivers/net/eepro100.c | 4 ++-- drivers/net/macb.c | 4 ++-- drivers/net/pcnet.c | 4 ++-- drivers/net/rtl8139.c | 4 ++-- drivers/net/rtl8169.c | 3 ++- drivers/net/tsec.c | 2 +- drivers/net/tsi108_eth.c | 4 ++-- drivers/net/uli526x.c | 6 +++--- drivers/qe/uec.c | 6 +++--- net/eth.c | 2 +- 13 files changed, 28 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/cpu/ixp/npe/npe.c b/cpu/ixp/npe/npe.c index 7e4af441054..a33b956975e 100644 --- a/cpu/ixp/npe/npe.c +++ b/cpu/ixp/npe/npe.c @@ -408,25 +408,25 @@ static int npe_init(struct eth_device *dev, bd_t * bis) if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback, (u32)p_npe) != IX_ETH_ACC_SUCCESS) { printf("can't register RX callback!\n"); - return 0; + return -1; } if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback, (u32)p_npe) != IX_ETH_ACC_SUCCESS) { printf("can't register TX callback!\n"); - return 0; + return -1; } npe_set_mac_address(dev); if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) { printf("can't enable port!\n"); - return 0; + return -1; } p_npe->active = 1; - return 1; + return 0; } #if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */ diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index da473ca0b1f..5a314137d91 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -727,7 +727,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) if (efis->actual_phy_addr == -1) { printf ("Unable to discover phy!\n"); - return 0; + return -1; } #else efis->actual_phy_addr = -1; @@ -763,7 +763,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) efis->initialized = 1; - return 1; + return 0; } diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index d5275dceb0f..72389226146 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -332,7 +332,7 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis) if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { printf("Error: Cannot reset ethernet controller.\n"); - return 0; + return -1; } #ifdef CONFIG_TULIP_SELECT_MEDIA @@ -382,7 +382,7 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis) send_setup_frame(dev, bis); - return 1; + return 0; } static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length) diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index 738146e6618..96ed2710c21 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -485,7 +485,7 @@ int eepro100_initialize (bd_t * bis) static int eepro100_init (struct eth_device *dev, bd_t * bis) { - int i, status = 0; + int i, status = -1; int tx_cur; struct descriptor *ias_cmd, *cfg_cmd; @@ -598,7 +598,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis) goto Done; } - status = 1; + status = 0; Done: return status; diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 95cdc496cba..6657d22926b 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -423,12 +423,12 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) #endif if (!macb_phy_init(macb)) - return 0; + return -1; /* Enable TX and RX */ macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); - return 1; + return 0; } static void macb_halt(struct eth_device *netdev) diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 2af0e8f244f..4e270c9f7b3 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -402,7 +402,7 @@ static int pcnet_init(struct eth_device* dev, bd_t *bis) if (i <= 0) { printf("%s: TIMEOUT: controller init failed\n", dev->name); pcnet_reset (dev); - return 0; + return -1; } /* @@ -410,7 +410,7 @@ static int pcnet_init(struct eth_device* dev, bd_t *bis) */ pcnet_write_csr (dev, 0, 0x0002); - return 1; + return 0; } static int pcnet_send(struct eth_device* dev, volatile void *packet, int pkt_len) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 23671800579..4c248054c3e 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -273,10 +273,10 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) if (inb(ioaddr + MediaStatus) & MSRLinkFail) { printf("Cable not connected or other link failure\n"); - return(0); + return -1 ; } - return 1; + return 0; } /* Serial EEPROM section. */ diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 1d7f31cead4..57ccbd964f7 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -624,7 +624,7 @@ static void rtl8169_init_ring(struct eth_device *dev) /************************************************************************** RESET - Finish setting up the ethernet interface ***************************************************************************/ -static void rtl_reset(struct eth_device *dev, bd_t *bis) +static int rtl_reset(struct eth_device *dev, bd_t *bis) { int i; @@ -660,6 +660,7 @@ static void rtl_reset(struct eth_device *dev, bd_t *bis) #ifdef DEBUG_RTL8169 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); #endif + return 0; } /************************************************************************** diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 108cebd8797..25392f68622 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -232,7 +232,7 @@ int tsec_init(struct eth_device *dev, bd_t * bd) startup_tsec(dev); /* If there's no link, fail */ - return priv->link; + return (priv->link ? 0 : -1); } diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c index 524e9daa4cb..a09115e6ddd 100644 --- a/drivers/net/tsi108_eth.c +++ b/drivers/net/tsi108_eth.c @@ -792,7 +792,7 @@ static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis) (dev->enetaddr[0] << 16); if (marvell_88e_phy_config(dev, &speed, &duplex) == 0) - return 0; + return -1; value = MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC | @@ -864,7 +864,7 @@ static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis) /* enable TX queue */ reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01; - return 1; + return 0; } /* diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c index 1267c5798f0..8460f6928de 100644 --- a/drivers/net/uli526x.c +++ b/drivers/net/uli526x.c @@ -279,12 +279,12 @@ static int uli526x_init_one(struct eth_device *dev, bd_t *bis) db->desc_pool_ptr = (uchar *)&desc_pool_array[0]; db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0]; if (db->desc_pool_ptr == NULL) - return 0; + return -1; db->buf_pool_ptr = &buf_pool[0]; db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0]; if (db->buf_pool_ptr == NULL) - return 0; + return -1; db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; db->first_tx_desc_dma = db->desc_pool_dma_ptr; @@ -331,7 +331,7 @@ static int uli526x_init_one(struct eth_device *dev, bd_t *bis) db->cr6_data |= ULI526X_TXTH_256; db->cr0_data = CR0_DEFAULT; uli526x_init(dev); - return 1; + return 0; } static void uli526x_disable(struct eth_device *dev) diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index a27c12aa2db..44cbea57856 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1129,7 +1129,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd) if (dev->enetaddr[0] & 0x01) { printf("%s: MacAddress is multcast address\n", __FUNCTION__); - return 0; + return -1; } uec_set_mac_address(uec, dev->enetaddr); uec->the_first_run = 1; @@ -1138,10 +1138,10 @@ static int uec_init(struct eth_device* dev, bd_t *bd) err = uec_open(uec, COMM_DIR_RX_AND_TX); if (err) { printf("%s: cannot enable UEC device\n", dev->name); - return 0; + return -1; } - return uec->mii_info->link; + return (uec->mii_info->link ? 0 : -1); } static void uec_halt(struct eth_device* dev) diff --git a/net/eth.c b/net/eth.c index d2fced8bbbc..5d9e9c18898 100644 --- a/net/eth.c +++ b/net/eth.c @@ -433,7 +433,7 @@ int eth_init(bd_t *bis) do { debug ("Trying %s\n", eth_current->name); - if (!eth_current->init(eth_current,bis)) { + if (eth_current->init(eth_current,bis) >= 0) { eth_current->state = ETH_STATE_ACTIVE; return 0; -- cgit v1.3.1 From 20c450ef61ef2eb1c96f9b59ba0eb8d849bba058 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Fri, 11 Jan 2008 02:39:47 +0100 Subject: Fix video console newline and carriage return handling Lines of the lenght CONSOLE_COLS or greater than CONSOLE_COLS are not displayed correctly. This is an attempt to fix this issue. Also add carriage return handling. Signed-off-by: Anatolij Gustschin Signed-off-by: Rodolfo Giometti --- drivers/video/cfb_console.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 82cc0c76c30..6262d02510c 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -647,7 +647,14 @@ static void console_back (void) static void console_newline (void) { - CURSOR_OFF console_row++; + /* Check if last character in the line was just drawn. If so, cursor was + overwriten and need not to be cleared. Cursor clearing without this + check causes overwriting the 1st character of the line if line lenght + is >= CONSOLE_COLS + */ + if (console_col < CONSOLE_COLS) + CURSOR_OFF + console_row++; console_col = 0; /* Check if we need to scroll the terminal */ @@ -660,16 +667,26 @@ static void console_newline (void) } } +static void console_cr (void) +{ + CURSOR_OFF console_col = 0; +} + /*****************************************************************************/ void video_putc (const char c) { + static int nl = 1; + switch (c) { - case 13: /* ignore */ + case 13: /* back to first column */ + console_cr (); break; case '\n': /* next line */ - console_newline (); + if (console_col || (!console_col && nl)) + console_newline (); + nl = 1; break; case 9: /* tab 8 */ @@ -691,8 +708,10 @@ void video_putc (const char c) console_col++; /* check for newline */ - if (console_col >= CONSOLE_COLS) + if (console_col >= CONSOLE_COLS) { console_newline (); + nl = 0; + } } CURSOR_SET} -- cgit v1.3.1 From bed53753dd1d7e6bcbea4339be0fb7760214cc35 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Fri, 11 Jan 2008 14:30:01 +0100 Subject: Add Fujitsu CoralP/Lime video driver Signed-off-by: Anatolij Gustschin Signed-off-by: Rodolfo Giometti --- drivers/video/Makefile | 1 + drivers/video/cfb_console.c | 42 +++++ drivers/video/mb862xx.c | 414 ++++++++++++++++++++++++++++++++++++++++++++ include/mb862xx.h | 44 +++++ 4 files changed, 501 insertions(+) create mode 100644 drivers/video/mb862xx.c create mode 100644 include/mb862xx.h (limited to 'drivers') diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 36611ecdda9..0e40f2afa98 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libvideo.a COBJS-y += ati_radeon_fb.o COBJS-y += cfb_console.o COBJS-y += ct69000.o +COBJS-y += mb862xx.o COBJS-y += sed13806.o COBJS-y += sed156x.o COBJS-y += sm501.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 6262d02510c..4f73067251e 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -140,6 +140,18 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #endif #endif +/*****************************************************************************/ +/* Defines for the MB862xx driver */ +/*****************************************************************************/ +#ifdef CONFIG_VIDEO_MB862xx + +#ifdef CONFIG_VIDEO_CORALP +#define VIDEO_FB_LITTLE_ENDIAN +#endif +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT +#endif + /*****************************************************************************/ /* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */ /*****************************************************************************/ @@ -304,7 +316,11 @@ void console_cursor (int state); #else #define SWAP16(x) (x) #define SWAP32(x) (x) +#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP) #define SHORTSWAP32(x) (x) +#else +#define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) ) +#endif #endif #if defined(DEBUG) || defined(DEBUG_CFB_CONSOLE) @@ -735,10 +751,24 @@ void video_puts (const char *s) fb ++; \ } +#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP) #define FILL_15BIT_555RGB(r,g,b) { \ *(unsigned short *)fb = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \ fb += 2; \ } +#else +static int tgl; +static unsigned short p0; +#define FILL_15BIT_555RGB(r,g,b) { \ + if (!tgl++) { \ + p0 = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \ + } else { \ + tgl=0; \ + *(unsigned long *)(fb-2) = (SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3)))<<16) | p0; \ + } \ + fb += 2; \ +} +#endif #define FILL_16BIT_565RGB(r,g,b) { \ *(unsigned short *)fb = SWAP16((unsigned short)((((r)>>3)<<11) | (((g)>>2)<<5) | ((b)>>3))); \ @@ -1080,8 +1110,20 @@ void logo_plot (void *screen, int width, int x, int y) *dest = ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6); break; case GDF_15BIT_555RGB: +#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP) *(unsigned short *) dest = SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3))); +#else + { + if (!tgl++) { + p0 = SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3))); + } else { + *(unsigned long *)(dest-2) = + (SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3)))<<16) | p0; + tgl=0; + } + } +#endif break; case GDF_16BIT_565RGB: *(unsigned short *) dest = diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c new file mode 100644 index 00000000000..bfb057f513b --- /dev/null +++ b/drivers/video/mb862xx.c @@ -0,0 +1,414 @@ +/* + * (C) Copyright 2007 + * DENX Software Engineering, Anatolij Gustschin, agust@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime + * PCI and video mode code was derived from smiLynxEM driver. + */ + +#include + +#if defined(CONFIG_VIDEO_MB862xx) + +#include +#include +#include +#include "videomodes.h" +#include + +/* + * Graphic Device + */ +GraphicDevice mb862xx; + +/* + * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ; + */ +#define VIDEO_MEM_SIZE 0x01FC0000 + +#if defined(CONFIG_PCI) +#if defined(CONFIG_VIDEO_CORALP) + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P }, + { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA }, + { } +}; + +/* Internal clock frequency divider table, index is mode number */ +unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; +#endif +#endif + +#if defined(CONFIG_VIDEO_CORALP) +#define rd_io in32r +#define wr_io out32r +#else +#define rd_io(addr) in_be32((volatile unsigned*)(addr)) +#define wr_io(addr,val) out_be32((volatile unsigned*)(addr), (val)) +#endif + +#define HOST_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fc0000 + (off))) +#define HOST_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fc0000 + (off)), (val)) +#define DISP_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fd0000 + (off))) +#define DISP_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fd0000 + (off)), (val)) +#define DE_RD_REG(off) rd_io((pGD->dprBase + (off))) +#define DE_WR_REG(off, val) wr_io((pGD->dprBase + (off)), (val)) + +#if defined(CONFIG_VIDEO_CORALP) +#define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x8400)), (val)) +#else +#define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x04a0)), (val)) +#endif + +#define L0PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2))) +#define L0PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)), (val)) +#define L1PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2))) +#define L1PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)), (val)) +#define L2PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2))) +#define L2PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)), (val)) +#define L3PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2))) +#define L3PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)), (val)) + +static void gdc_sw_reset(void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + HOST_WR_REG (0x002c, 0x00000001); + udelay (500); + video_hw_init (); +} + + +static void de_wait(void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + int lc = 0x10000; + + /* Sync with software writes to framebuffer, + try to reset if engine locked */ + while (DE_RD_REG (0x0400) & 0x00000131) + if (lc-- < 0) { + gdc_sw_reset (); + printf ("gdc reset done after drawing engine lock...\n"); + break; + } +} + +static void de_wait_slots(int slots) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + int lc = 0x10000; + + /* Wait for free fifo slots */ + while (DE_RD_REG (0x0408) < slots) + if (lc-- < 0) { + gdc_sw_reset (); + printf ("gdc reset done after drawing engine lock...\n"); + break; + } +} + +#if !defined(CONFIG_VIDEO_CORALP) +static void board_disp_init(void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + const gdc_regs *regs = board_get_regs (); + + while (regs->index) { + DISP_WR_REG (regs->index, regs->value); + regs++; + } +} +#endif + +/* + * Init drawing engine + */ +static void de_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + int cf = (pGD->gdfBytesPP == 1) ? 0x0000 : 0x8000; + + pGD->dprBase = pGD->frameAdrs + 0x01ff0000; + + /* Setup mode and fbbase, xres, fg, bg */ + de_wait_slots (2); + DE_WR_FIFO (0xf1010108); + DE_WR_FIFO (cf | 0x0300); + DE_WR_REG (0x0440, 0x0000); + DE_WR_REG (0x0444, pGD->winSizeX); + DE_WR_REG (0x0480, 0x0000); + DE_WR_REG (0x0484, 0x0000); + /* Reset clipping */ + DE_WR_REG (0x0454, 0x0000); + DE_WR_REG (0x0458, pGD->winSizeX); + DE_WR_REG (0x045c, 0x0000); + DE_WR_REG (0x0460, pGD->winSizeY); + + /* Clear framebuffer using drawing engine */ + de_wait_slots (3); + DE_WR_FIFO (0x09410000); + DE_WR_FIFO (0x00000000); + DE_WR_FIFO (pGD->winSizeY<<16 | pGD->winSizeX); +} + +#if defined(CONFIG_VIDEO_CORALP) +unsigned int pci_video_init(void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + pci_dev_t devbusfn; + + if ((devbusfn = pci_find_devices(supported, 0)) < 0) + { + printf ("PCI video controller not found!\n"); + return 0; + } + + /* PCI setup */ + pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pGD->frameAdrs); + pGD->frameAdrs = pci_mem_to_phys (devbusfn, pGD->frameAdrs); + + if (pGD->frameAdrs == 0) { + printf ("PCI config: failed to get base address\n"); + return 0; + } + + pGD->pciBase = pGD->frameAdrs; + + /* Setup clocks and memory mode for Coral-P Eval. Board */ + HOST_WR_REG (0x0038, 0x00090000); + udelay (200); + HOST_WR_REG (0xfffc, 0x11d7fa13); + udelay (100); + return pGD->frameAdrs; +} + +unsigned int card_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + unsigned int cf, videomode, div = 0; + unsigned long t1, hsync, vsync; + char *penv; + int tmp, i, bpp; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; + + memset (pGD, 0, sizeof (GraphicDevice)); + + if (!pci_video_init ()) { + return 0; + } + + printf ("CoralP\n"); + + tmp = 0; + videomode = 0x310; + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* deceide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("\tno VESA Mode found, switching to mode 0x%x \n", videomode); + i = 0; + } + res_mode = + (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; + if (vesa_modes[i].resindex > 2) { + printf ("\tUnsupported resolution, switching to default\n"); + bpp = vesa_modes[1].bits_per_pixel; + div = fr_div[1]; + } + bpp = vesa_modes[i].bits_per_pixel; + div = fr_div[vesa_modes[i].resindex]; + } else { + + res_mode = (struct ctfb_res_modes *) &var_mode; + bpp = video_get_params (res_mode, penv); + } + + /* calculate hsync and vsync freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsync = 1000000000L / t1; + t1 *= (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsync = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bpp, (hsync / 1000), (vsync / 1000)); + printf ("\t%s\n", pGD->modeIdent); + pGD->winSizeX = res_mode->xres; + pGD->winSizeY = res_mode->yres; + pGD->memSize = VIDEO_MEM_SIZE; + + switch (bpp) { + case 8: + pGD->gdfIndex = GDF__8BIT_INDEX; + pGD->gdfBytesPP = 1; + break; + case 15: + case 16: + pGD->gdfIndex = GDF_15BIT_555RGB; + pGD->gdfBytesPP = 2; + break; + default: + printf ("\t%d bpp configured, but only 8,15 and 16 supported.\n", bpp); + printf ("\tSwitching back to 15bpp\n"); + pGD->gdfIndex = GDF_15BIT_555RGB; + pGD->gdfBytesPP = 2; + } + + /* Setup dot clock (internal pll, division rate) */ + DISP_WR_REG (0x0100, div); + /* L0 init */ + cf = (pGD->gdfBytesPP == 1) ? 0x00000000 : 0x80000000; + DISP_WR_REG (0x0020, ((pGD->winSizeX * pGD->gdfBytesPP)/64)<<16 | + (pGD->winSizeY-1) | + cf); + DISP_WR_REG (0x0024, 0x00000000); + DISP_WR_REG (0x0028, 0x00000000); + DISP_WR_REG (0x002c, 0x00000000); + DISP_WR_REG (0x0110, 0x00000000); + DISP_WR_REG (0x0114, 0x00000000); + DISP_WR_REG (0x0118, (pGD->winSizeY-1)<<16 | pGD->winSizeX); + + /* Display timing init */ + DISP_WR_REG (0x0004, (pGD->winSizeX+res_mode->left_margin+res_mode->right_margin+res_mode->hsync_len-1)<<16); + DISP_WR_REG (0x0008, (pGD->winSizeX-1) << 16 | (pGD->winSizeX-1)); + DISP_WR_REG (0x000c, (res_mode->vsync_len-1)<<24|(res_mode->hsync_len-1)<<16|(pGD->winSizeX+res_mode->right_margin-1)); + DISP_WR_REG (0x0010, (pGD->winSizeY+res_mode->lower_margin+res_mode->upper_margin+res_mode->vsync_len-1)<<16); + DISP_WR_REG (0x0014, (pGD->winSizeY-1) << 16 | (pGD->winSizeY+res_mode->lower_margin-1)); + DISP_WR_REG (0x0018, 0x00000000); + DISP_WR_REG (0x001c, pGD->winSizeY << 16 | pGD->winSizeX); + /* Display enable, L0 layer */ + DISP_WR_REG (0x0100, 0x80010000 | div); + + return pGD->frameAdrs; +} +#endif + +void *video_hw_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + + printf ("Video: Fujitsu "); + + memset (pGD, 0, sizeof (GraphicDevice)); + +#if defined(CONFIG_VIDEO_CORALP) + if (card_init () == 0) { + return (NULL); + } +#else + /* Preliminary init of the onboard graphic controller, + retrieve base address */ + if ((pGD->frameAdrs = board_video_init ()) == 0) { + printf ("Controller not found!\n"); + return (NULL); + } else + printf("Lime\n"); +#endif + + de_init (); + +#if !defined(CONFIG_VIDEO_CORALP) + board_disp_init(); +#endif + +#if defined(CONFIG_LWMON5) + /* Lamp on */ + board_backlight_switch (1); +#endif + + return pGD; +} + +/* + * Set a RGB color in the LUT + */ +void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsigned char b) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + + L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b)); +} + +/* + * Drawing engine Fill and BitBlt screen region + */ +void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, unsigned int dst_y, + unsigned int dim_x, unsigned int dim_y, unsigned int color) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + + de_wait_slots (3); + DE_WR_REG (0x0480, color); + DE_WR_FIFO (0x09410000); + DE_WR_FIFO ((dst_y << 16) | dst_x); + DE_WR_FIFO ((dim_y << 16) | dim_x); + de_wait (); +} + +void video_hw_bitblt (unsigned int bpp, unsigned int src_x, unsigned int src_y, + unsigned int dst_x, unsigned int dst_y, unsigned int width, + unsigned int height) +{ + GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + unsigned int ctrl = 0x0d000000L; + + if (src_x >= dst_x && src_y >= dst_y) + ctrl |= 0x00440000L; + else if (src_x >= dst_x && src_y <= dst_y) + ctrl |= 0x00460000L; + else if (src_x <= dst_x && src_y >= dst_y) + ctrl |= 0x00450000L; + else + ctrl |= 0x00470000L; + + de_wait_slots (4); + DE_WR_FIFO (ctrl); + DE_WR_FIFO ((src_y << 16) | src_x); + DE_WR_FIFO ((dst_y << 16) | dst_x); + DE_WR_FIFO ((height << 16) | width); + de_wait (); /* sync */ +} +#endif /* CONFIG_VIDEO_MB862xx */ diff --git a/include/mb862xx.h b/include/mb862xx.h new file mode 100644 index 00000000000..1af567002eb --- /dev/null +++ b/include/mb862xx.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2007 + * DENX Software Engineering, Anatolij Gustschin, agust@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mb862xx.h - Graphic interface for Fujitsu CoralP/Lime + */ + +#ifndef _MB862XX_H_ +#define _MB862XX_H_ + +#define PCI_VENDOR_ID_FUJITSU 0x10CF +#define PCI_DEVICE_ID_CORAL_P 0x2019 +#define PCI_DEVICE_ID_CORAL_PA 0x201E + +typedef struct { + unsigned int index; + unsigned int value; +} gdc_regs; + +const gdc_regs *board_get_regs (void); +unsigned int board_video_init (void); +void board_backlight_switch(int); + +#endif /* _MB862XX_H_ */ -- cgit v1.3.1 From 92fa37eac530860643afa26ae347af3d23d67309 Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Wed, 9 Jan 2008 12:42:35 -0500 Subject: Remove superfluous preprocessor conditionals from LM73 driver (1) Remove unused symbol "CFG_EEPROM_PAGE_WRITE_ENABLE". (2) Use conditional Makefile.o. Signed-off-by: Larry Johnson --- drivers/hwmon/Makefile | 2 +- drivers/hwmon/lm73.c | 9 --------- include/configs/korat.h | 1 - 3 files changed, 1 insertion(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 32e3f44a916..065433a6088 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -34,7 +34,7 @@ COBJS-y += adm1021.o COBJS-y += ds1621.o COBJS-y += ds1722.o COBJS-y += ds1775.o -COBJS-y += lm73.o +COBJS-$(CONFIG_DTT_LM73) += lm73.o COBJS-y += lm75.o COBJS-y += lm81.o diff --git a/drivers/hwmon/lm73.c b/drivers/hwmon/lm73.c index f9ae01297bc..db8ef662adc 100644 --- a/drivers/hwmon/lm73.c +++ b/drivers/hwmon/lm73.c @@ -31,13 +31,6 @@ */ #include - -#ifdef CONFIG_DTT_LM73 -#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \ - (CFG_EEPROM_PAGE_WRITE_BITS < 1) -# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM73" -#endif - #include #include @@ -177,5 +170,3 @@ int dtt_get_temp(int sensor) { return (dtt_read(sensor, DTT_READ_TEMP) + 0x0040) >> 7; } /* dtt_get_temp() */ - -#endif /* CONFIG_DTT_LM73 */ diff --git a/include/configs/korat.h b/include/configs/korat.h index 7d0640bbcf8..5182972829b 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -156,7 +156,6 @@ #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) #define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE #define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -- cgit v1.3.1 From 3afac79ec27b91df185f090b31dad9620779f440 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Fri, 11 Jan 2008 20:42:58 -0600 Subject: USB: Add Philips 1561 PCI-OHCI ids (needed for M5475EVB) Signed-off-by: TsiChungLiew --- drivers/usb/usb_ohci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/usb/usb_ohci.c b/drivers/usb/usb_ohci.c index cfa384eff6f..fb4726f2839 100644 --- a/drivers/usb/usb_ohci.c +++ b/drivers/usb/usb_ohci.c @@ -98,6 +98,7 @@ static struct pci_device_id ohci_pci_ids[] = { {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ + {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ /* Please add supported PCI OHCI controller ids here */ {0, 0} }; -- cgit v1.3.1