From e3f2a93362c823fc1feb5e8a40ff3c120716a05b Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Wed, 3 Mar 2010 15:27:21 +0530 Subject: net: Kirkwood_egiga.c: fixed build warnings This patch fixes following build warnings for kirkwood_egiga.c kirkwood_egiga.c: In function "kwgbe_init": kirkwood_egiga.c:448: warning: dereferencing type-punned pointer will break strict-aliasing rules kirkwood_egiga.c: In function "kwgbe_recv": kirkwood_egiga.c:609: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Prafulla Wadaskar Signed-off-by: Ben Warren --- drivers/net/kirkwood_egiga.c | 4 ++-- drivers/net/kirkwood_egiga.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index 2ad7feac816..25c72df9cb1 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -445,7 +445,7 @@ static int kwgbe_init(struct eth_device *dev) KWGBEREG_WR(regs->pmtu, 0); /* Assignment of Rx CRDB of given RXUQ */ - KWGBEREG_WR(regs->rxcdp[RXUQ].rxcdp, (u32) dkwgbe->p_rxdesc_curr); + KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr); /* Enable port Rx. */ KWGBEREG_WR(regs->rqc, (1 << RXUQ)); @@ -606,7 +606,7 @@ static int kwgbe_recv(struct eth_device *dev) p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; p_rxdesc_curr->byte_cnt = 0; - writel((unsigned)p_rxdesc_curr->nxtdesc_p, &dkwgbe->p_rxdesc_curr); + writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr); return 0; } diff --git a/drivers/net/kirkwood_egiga.h b/drivers/net/kirkwood_egiga.h index 16d52141ed1..30c773ca5c9 100644 --- a/drivers/net/kirkwood_egiga.h +++ b/drivers/net/kirkwood_egiga.h @@ -418,7 +418,7 @@ struct kwgbe_registers { u32 pmtbs; u8 pad14[0x60c - 0x4ec - 4]; struct kwgbe_rxcdp rxcdp[7]; - u32 rxcdp7; + struct kwgbe_rxdesc *rxcdp7; u32 rqc; struct kwgbe_txdesc *tcsdp; u8 pad15[0x6c0 - 0x684 - 4]; -- cgit v1.3.1 From 6f5f89f01195e2d009b317df27197a38fcab3553 Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Thu, 1 Apr 2010 14:16:41 +0200 Subject: Remove unused "local_crc32" function. For code archeologists, this is a nice example of copy and paste history. Signed-off-by: Detlev Zundel Signed-off-by: Ben Warren --- arch/powerpc/cpu/mpc8220/fec.c | 41 +---------------------------------------- drivers/net/mpc512x_fec.c | 41 +---------------------------------------- drivers/net/mpc5xxx_fec.c | 41 +---------------------------------------- 3 files changed, 3 insertions(+), 120 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc8220/fec.c b/arch/powerpc/cpu/mpc8220/fec.c index 992e0ffbc46..5df97353328 100644 --- a/arch/powerpc/cpu/mpc8220/fec.c +++ b/arch/powerpc/cpu/mpc8220/fec.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003 + * (C) Copyright 2003-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * This file is based on mpc4200fec.c, @@ -27,10 +27,6 @@ static void tfifo_print (char *devname, mpc8220_fec_priv * fec); static void rfifo_print (char *devname, mpc8220_fec_priv * fec); #endif /* DEBUG */ -#ifdef DEBUG -static u32 local_crc32 (char *string, unsigned int crc_value, int len); -#endif - typedef struct { u8 data[1500]; /* actual data */ int length; /* actual length */ @@ -962,39 +958,4 @@ int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data) return 0; } -#ifdef DEBUG -static u32 local_crc32 (char *string, unsigned int crc_value, int len) -{ - int i; - char c; - unsigned int crc, count; - - /* - * crc32 algorithm - */ - /* - * crc = 0xffffffff; * The initialized value should be 0xffffffff - */ - crc = crc_value; - - for (i = len; --i >= 0;) { - c = *string++; - for (count = 0; count < 8; count++) { - if ((c & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - c >>= 1; - } - } - - /* - * In big endian system, do byte swaping for crc value - */ - return crc; -} -#endif /* DEBUG */ - #endif /* CONFIG_MPC8220_FEC */ diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c index fb2c19a71b8..3aba748aa1b 100644 --- a/drivers/net/mpc512x_fec.c +++ b/drivers/net/mpc512x_fec.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2009 + * (C) Copyright 2003-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * Derived from the MPC8xx FEC driver. @@ -25,10 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; #error "CONFIG_MII has to be defined!" #endif -#if (DEBUG & 0x40) -static u32 local_crc32(char *string, unsigned int crc_value, int len); -#endif - int fec512x_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal); int fec512x_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data); int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis); @@ -775,39 +771,4 @@ int fec512x_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data) return 0; } -#if (DEBUG & 0x40) -static u32 local_crc32 (char *string, unsigned int crc_value, int len) -{ - int i; - char c; - unsigned int crc, count; - - /* - * crc32 algorithm - */ - /* - * crc = 0xffffffff; * The initialized value should be 0xffffffff - */ - crc = crc_value; - - for (i = len; --i >= 0;) { - c = *string++; - for (count = 0; count < 8; count++) { - if ((c & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - c >>= 1; - } - } - - /* - * In big endian system, do byte swaping for crc value - */ - /**/ return crc; -} -#endif /* DEBUG */ - #endif /* CONFIG_MPC512x_FEC */ diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c index c2b1bbdc7b1..1681e267243 100644 --- a/drivers/net/mpc5xxx_fec.c +++ b/drivers/net/mpc5xxx_fec.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2005 + * (C) Copyright 2003-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * This file is based on mpc4200fec.c, @@ -28,10 +28,6 @@ static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec); static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec); #endif /* DEBUG */ -#if (DEBUG & 0x40) -static uint32 local_crc32(char *string, unsigned int crc_value, int len); -#endif - typedef struct { uint8 data[1500]; /* actual data */ int length; /* actual length */ @@ -1019,38 +1015,3 @@ int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 dat return 0; } - -#if (DEBUG & 0x40) -static uint32 local_crc32(char *string, unsigned int crc_value, int len) -{ - int i; - char c; - unsigned int crc, count; - - /* - * crc32 algorithm - */ - /* - * crc = 0xffffffff; * The initialized value should be 0xffffffff - */ - crc = crc_value; - - for (i = len; --i >= 0;) { - c = *string++; - for (count = 0; count < 8; count++) { - if ((c & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - c >>= 1; - } - } - - /* - * In big endian system, do byte swaping for crc value - */ - /**/ return crc; -} -#endif /* DEBUG */ -- cgit v1.3.1 From 23c34af48ff0dbff3bbaa8e94df3bf40350a709f Mon Sep 17 00:00:00 2001 From: Richard Retanubun Date: Wed, 17 Jun 2009 16:00:41 -0400 Subject: 83xx: UEC: Added support for bitBang MII driver access to PHYs This patch enabled support for having PHYs on bitBang MII and uec MII operating at the same time. Modeled after the MPC8360ADS implementation. Added the ability to specify which ethernet interfaces have bitbang SMI on the board header file. Signed-off-by: Richard Retanubun Signed-off-by: Ben Warren --- drivers/qe/uec.c | 6 ++---- drivers/qe/uec_phy.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 27dc5009c80..ccbf27d0be9 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -595,8 +595,7 @@ static void phy_change(struct eth_device *dev) adjust_link(dev); } -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ - && !defined(BITBANGMII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /* * Find a device index from the devlist by name @@ -1388,8 +1387,7 @@ int uec_initialize(bd_t *bis, uec_info_t *uec_info) return err; } -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ - && !defined(BITBANGMII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write); #endif diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index fa48feaf042..3baffe42fbc 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -93,6 +93,27 @@ static const struct fixed_phy_port fixed_phy_port[] = { CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ }; +/*--------------------------------------------------------------------+ + * BitBang MII support for ethernet ports + * + * Based from MPC8560ADS implementation + *--------------------------------------------------------------------*/ +/* + * Example board header file to define bitbang ethernet ports: + * + * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name, + * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("FSL UEC0") +*/ +#ifndef CONFIG_SYS_BITBANG_PHY_PORTS +#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */ +#endif + +#if defined(CONFIG_BITBANGMII) +static const char *bitbang_phy_port[] = { + CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */ +}; +#endif /* CONFIG_BITBANGMII */ + static void config_genmii_advert (struct uec_mii_info *mii_info); static void genmii_setup_forced (struct uec_mii_info *mii_info); static void genmii_restart_aneg (struct uec_mii_info *mii_info); @@ -113,6 +134,19 @@ void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int valu enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; u32 tmp_reg; + +#if defined(CONFIG_BITBANGMII) + u32 i = 0; + + for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) { + if (strncmp(dev->name, bitbang_phy_port[i], + sizeof(dev->name)) == 0) { + (void)bb_miiphy_write(NULL, mii_id, regnum, value); + return; + } + } +#endif /* CONFIG_BITBANGMII */ + ug_regs = ugeth->uec_mii_regs; /* Stop the MII management read cycle */ @@ -140,6 +174,19 @@ int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum) u32 tmp_reg; u16 value; + +#if defined(CONFIG_BITBANGMII) + u32 i = 0; + + for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) { + if (strncmp(dev->name, bitbang_phy_port[i], + sizeof(dev->name)) == 0) { + (void)bb_miiphy_read(NULL, mii_id, regnum, &value); + return (value); + } + } +#endif /* CONFIG_BITBANGMII */ + ug_regs = ugeth->uec_mii_regs; /* Setting up the MII Mangement Address Register */ -- cgit v1.3.1 From 33f684d6d512992ed1ae37ec46e76bdeb0773bac Mon Sep 17 00:00:00 2001 From: Wolfgang Wegner Date: Tue, 6 Apr 2010 11:13:02 +0200 Subject: fix lockup in mcfmii/mii_discover_phy() in case communication fails Signed-off-by: Wolfgang Wegner Signed-off-by: Ben Warren --- drivers/net/mcfmii.c | 45 +++++++++++++++++++++++---------------------- 1 file changed, 23 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 4acc29e42cb..060bdd73971 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -175,38 +175,39 @@ int mii_discover_phy(struct eth_device *dev) #ifdef ET_DEBUG printf("PHY type 0x%x pass %d type\n", phytype, pass); #endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + if (phytype == 0xffff) + continue; + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); #ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d\n", phyno, pass); + printf("PHY @ 0x%x pass %d\n", phyno, pass); #endif - for (i = 0; i < (sizeof(phyinfo) / sizeof(phy_info_t)); i++) { - if (phyinfo[i].phyid == phytype) { + for (i = 0; (i < (sizeof(phyinfo) / sizeof(phy_info_t))) + && (phyinfo[i].phyid != 0); i++) { + if (phyinfo[i].phyid == phytype) { #ifdef ET_DEBUG - printf("phyid %x - %s\n", - phyinfo[i].phyid, - phyinfo[i].strid); + printf("phyid %x - %s\n", + phyinfo[i].phyid, + phyinfo[i].strid); #endif - strcpy(info->phy_name, phyinfo[i].strid); - info->phyname_init = 1; - found = 1; - break; - } + strcpy(info->phy_name, phyinfo[i].strid); + info->phyname_init = 1; + found = 1; + break; } + } - if (!found) { + if (!found) { #ifdef ET_DEBUG - printf("0x%08x\n", phytype); + printf("0x%08x\n", phytype); #endif - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; } } } -- cgit v1.3.1 From 910119b3c462fd6367536899ee43de1eb7d22d8e Mon Sep 17 00:00:00 2001 From: John Rigby Date: Wed, 7 Apr 2010 23:29:40 -0600 Subject: fec_mxc don't use internal eeprom on MX25 Avoid using the internal eeprom on MX25 like MX51 already does. Signed-off-by: John Rigby Signed-off-by: Ben Warren --- drivers/net/fec_mxc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 8c4ade5ab5b..fdc288c63a7 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -314,9 +314,9 @@ static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) { /* * The MX27 can store the mac address in internal eeprom - * This mechanism is not supported now by MX51 + * This mechanism is not supported now by MX51 or MX25 */ -#ifdef CONFIG_MX51 +#if defined(CONFIG_MX51) || defined(CONFIG_MX25) return -1; #else struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; -- cgit v1.3.1 From 5525856d59910c72687ab6201f39cdf1c04cfc15 Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Thu, 8 Apr 2010 11:49:59 +0200 Subject: mpc512x_fec: Move PHY initialization from probe into init routine. This saves the autonegotation delay when not using ethernet in U-Boot Signed-off-by: Detlev Zundel Signed-off-by: Ben Warren --- drivers/net/mpc512x_fec.c | 29 +++++++---------------------- 1 file changed, 7 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c index 3aba748aa1b..c580c827a6e 100644 --- a/drivers/net/mpc512x_fec.c +++ b/drivers/net/mpc512x_fec.c @@ -160,7 +160,7 @@ static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec) } /********************************************************************/ -static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac) +static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, unsigned char *mac) { u8 currByte; /* byte for which to compute the CRC */ int byte; /* loop - counter */ @@ -226,6 +226,12 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) printf ("mpc512x_fec_init... Begin\n"); #endif + mpc512x_fec_set_hwaddr (fec, dev->enetaddr); + out_be32(&fec->eth->gaddr1, 0x00000000); + out_be32(&fec->eth->gaddr2, 0x00000000); + + mpc512x_fec_init_phy (dev, bis); + /* Set interrupt mask register */ out_be32(&fec->eth->imask, 0x00000000); @@ -611,8 +617,6 @@ int mpc512x_fec_initialize (bd_t * bis) volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; mpc512x_fec_priv *fec; struct eth_device *dev; - int i; - char *tmp, *end, env_enetaddr[6]; void * bd; fec = (mpc512x_fec_priv *) malloc (sizeof(*fec)); @@ -663,25 +667,6 @@ int mpc512x_fec_initialize (bd_t * bis) */ out_be32(&fec->eth->ievent, 0xffffffff); - /* - * Try to set the mac address now. The fec mac address is - * a garbage after reset. When not using fec for booting - * the Linux fec driver will try to work with this garbage. - */ - tmp = getenv ("ethaddr"); - if (tmp) { - for (i=0; i<6; i++) { - env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end+1 : end; - } - mpc512x_fec_set_hwaddr (fec, env_enetaddr); - out_be32(&fec->eth->gaddr1, 0x00000000); - out_be32(&fec->eth->gaddr2, 0x00000000); - } - - mpc512x_fec_init_phy (dev, bis); - return 1; } -- cgit v1.3.1 From a45dde2293c816138e53c26eca6fd0322583f9a6 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 14 Apr 2010 16:29:06 -0400 Subject: net: dm9000x: use standard I/O accessors The current dm9000x driver accesses its memory mapped registers directly instead of using the standard I/O accessors. This can cause problems on Blackfin systems as the accesses can get out of order. So convert the direct volatile dereferences to use the normal in/out macros. Signed-off-by: Mike Frysinger Signed-off-by: Ben Warren --- drivers/net/dm9000x.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index a7fef56030f..f121286812f 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -117,12 +117,12 @@ static void DM9000_iow(int reg, u8 value); /* DM9000 network board routine ---------------------------- */ -#define DM9000_outb(d,r) ( *(volatile u8 *)r = d ) -#define DM9000_outw(d,r) ( *(volatile u16 *)r = d ) -#define DM9000_outl(d,r) ( *(volatile u32 *)r = d ) -#define DM9000_inb(r) (*(volatile u8 *)r) -#define DM9000_inw(r) (*(volatile u16 *)r) -#define DM9000_inl(r) (*(volatile u32 *)r) +#define DM9000_outb(d,r) outb(d, r) +#define DM9000_outw(d,r) outw(d, r) +#define DM9000_outl(d,r) outl(d, r) +#define DM9000_inb(r) inb(r) +#define DM9000_inw(r) inw(r) +#define DM9000_inl(r) inl(r) #ifdef CONFIG_DM9000_DEBUG static void -- cgit v1.3.1 From 538be58568542aac2ed4bdf4c05398cfa67e98f0 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 19 Apr 2010 14:54:49 -0500 Subject: tsec: Wait for both RX and TX to stop When gracefully stopping the controller, the driver was continuing if *either* RX or TX had stopped. We need to wait for both, or the controller could get into an invalid state. Signed-off-by: Andy Fleming Signed-off-by: Ben Warren --- drivers/net/tsec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index fd49eff183d..3e4c3bd31b9 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -1082,7 +1082,8 @@ static void tsec_halt(struct eth_device *dev) regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); - while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; + while ((regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)) + != (IEVENT_GRSC | IEVENT_GTSC)) ; regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); -- cgit v1.3.1 From 2e236bf28e729aca28e60c153dd8f913d1b3d058 Mon Sep 17 00:00:00 2001 From: Eric Jarrige Date: Fri, 16 Apr 2010 00:03:19 +0200 Subject: fec_mxc.c: Fix MX27 FEC MAC validity check Fix MX27 FEC logic to check validity of the MAC address in fuse. Only null (empty fuse) or invalid MAC address was retrieved from mx27 fuses before this change. Signed-off-by: Eric Jarrige Signed-off-by: Ben Warren --- drivers/net/fec_mxc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index fdc288c63a7..68be74775c6 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -325,7 +325,7 @@ static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) for (i = 0; i < 6; i++) mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]); - return is_valid_ether_addr(mac); + return !is_valid_ether_addr(mac); #endif } -- cgit v1.3.1 From f0588fdf921c63f84051923bb29eb4255d62a6e7 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Tue, 6 Apr 2010 21:33:08 +0530 Subject: net: Kirkwood_egiga.c bugfixes for rx path Cosmetic changes: Few comments updated Functionality: Rx packet frame size is programming should be done when port is in disabled state. this is corrected Signed-off-by: Prafulla Wadaskar Signed-off-by: Ben Warren --- drivers/net/kirkwood_egiga.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index 25c72df9cb1..dd711e4a105 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -424,8 +424,6 @@ static int kwgbe_init(struct eth_device *dev) KWGBEREG_WR(regs->pxc, PRT_CFG_VAL); KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); - /* Disable port initially */ - KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN); /* Assign port SDMA configuration */ KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); @@ -438,6 +436,9 @@ static int kwgbe_init(struct eth_device *dev) KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE | (KWGBEREG_RD(regs->psc0) & MRU_MASK)); + /* Enable port initially */ + KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN); + /* * Set ethernet MTU for leaky bucket mechanism to 0 - this will * disable the leaky bucket mechanism . @@ -480,7 +481,7 @@ static int kwgbe_halt(struct eth_device *dev) stop_queue(®s->tqc); stop_queue(®s->rqc); - /* Enable port */ + /* Disable port */ KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN); /* Set port is not reset */ KWGBEREG_BITS_RESET(regs->psc1, 1 << 4); @@ -525,7 +526,7 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr, p_txdesc->buf_ptr = (u8 *) p; p_txdesc->byte_cnt = datasize; - /* Apply send command using zeroth RXUQ */ + /* Apply send command using zeroth TXUQ */ KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc); KWGBEREG_WR(regs->tqc, (1 << TXUQ)); -- cgit v1.3.1 From bd75db3feb9a8e4123b76006dbe582b71adbf22f Mon Sep 17 00:00:00 2001 From: Valentin Yakovenkov Date: Fri, 23 Apr 2010 09:40:23 +0400 Subject: smc911x driver frame alignment patch SMSC911x chips have alignment function to allow frame payload data (which comes after 14-bytes ethernet header) to be aligned at some boundary when reading it from fifo (usually - 4 bytes boundary). This is done by inserting fake zeros bytes BEFORE actual frame data when reading from SMSC's fifo. This function controlled by RX_CFG register. There are bits that represents amount of fake bytes to be inserted. Linux uses alignment of 4 bytes. Ethernet frame header is 14 bytes long, so we need to add 2 fake bytes to get payload data aligned at 4-bytes boundary. Linux driver does this by adding IP_ALIGNMENT constant (defined at skb.h) when calculating fifo data length. All network subsystem of Linux uses this constant too when calculating different offsets. But u-boot does not use any packet data alignment, so we don't need to add anything when calculating fifo data length. Moreover, driver zeros the RX_CFG register just one line up, so chip does not insert any fake data at the beginig. So calculated data length is always bigger by 1 word. It seems that at almost every packet read we get an underflow condition at fifo and possible corruption of data. Especially at continuous transfers, such as tftp. Just after removing this magic addition, I've got tftp transfer speed as it aught to be at 100Mbps. It was really slow before. It seems that fifo underflow occurs only when using byte packing on 32-bit blackfin bus (may be because of very small delay between reads). Signed-off-by: Valentin Yakovenkov Signed-off-by: Ben Warren --- drivers/net/smc911x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index cac08d0a7cc..f2fc88b71d5 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -220,7 +220,7 @@ static int smc911x_rx(struct eth_device *dev) smc911x_reg_write(dev, RX_CFG, 0); - tmplen = (pktlen + 2+ 3) / 4; + tmplen = (pktlen + 3) / 4; while (tmplen--) *data++ = pkt_data_pull(dev, RX_DATA_FIFO); -- cgit v1.3.1 From f6569884b45e480e2c575d85ce86a2636a41c66b Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Thu, 15 Apr 2010 22:32:38 +0800 Subject: net: add opencore 10/100 ethernet mac driver This patch ports the opencore 10/100 ethernet mac driver ethoc.c from linux kernel to u-boot. Signed-off-by: Thomas Chou Signed-off-by: Ben Warren --- drivers/net/Makefile | 1 + drivers/net/ethoc.c | 511 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/netdev.h | 1 + 3 files changed, 513 insertions(+) create mode 100644 drivers/net/ethoc.c (limited to 'drivers') diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 1ec0ba13a6d..0e68e521b05 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_E1000) += e1000.o COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o +COBJS-$(CONFIG_ETHOC) += ethoc.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c new file mode 100644 index 00000000000..b912e446506 --- /dev/null +++ b/drivers/net/ethoc.c @@ -0,0 +1,511 @@ +/* + * Opencore 10/100 ethernet mac driver + * + * Copyright (C) 2007-2008 Avionic Design Development GmbH + * Copyright (C) 2008-2009 Avionic Design GmbH + * Thierry Reding + * Copyright (C) 2010 Thomas Chou + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* register offsets */ +#define MODER 0x00 +#define INT_SOURCE 0x04 +#define INT_MASK 0x08 +#define IPGT 0x0c +#define IPGR1 0x10 +#define IPGR2 0x14 +#define PACKETLEN 0x18 +#define COLLCONF 0x1c +#define TX_BD_NUM 0x20 +#define CTRLMODER 0x24 +#define MIIMODER 0x28 +#define MIICOMMAND 0x2c +#define MIIADDRESS 0x30 +#define MIITX_DATA 0x34 +#define MIIRX_DATA 0x38 +#define MIISTATUS 0x3c +#define MAC_ADDR0 0x40 +#define MAC_ADDR1 0x44 +#define ETH_HASH0 0x48 +#define ETH_HASH1 0x4c +#define ETH_TXCTRL 0x50 + +/* mode register */ +#define MODER_RXEN (1 << 0) /* receive enable */ +#define MODER_TXEN (1 << 1) /* transmit enable */ +#define MODER_NOPRE (1 << 2) /* no preamble */ +#define MODER_BRO (1 << 3) /* broadcast address */ +#define MODER_IAM (1 << 4) /* individual address mode */ +#define MODER_PRO (1 << 5) /* promiscuous mode */ +#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */ +#define MODER_LOOP (1 << 7) /* loopback */ +#define MODER_NBO (1 << 8) /* no back-off */ +#define MODER_EDE (1 << 9) /* excess defer enable */ +#define MODER_FULLD (1 << 10) /* full duplex */ +#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */ +#define MODER_DCRC (1 << 12) /* delayed CRC enable */ +#define MODER_CRC (1 << 13) /* CRC enable */ +#define MODER_HUGE (1 << 14) /* huge packets enable */ +#define MODER_PAD (1 << 15) /* padding enabled */ +#define MODER_RSM (1 << 16) /* receive small packets */ + +/* interrupt source and mask registers */ +#define INT_MASK_TXF (1 << 0) /* transmit frame */ +#define INT_MASK_TXE (1 << 1) /* transmit error */ +#define INT_MASK_RXF (1 << 2) /* receive frame */ +#define INT_MASK_RXE (1 << 3) /* receive error */ +#define INT_MASK_BUSY (1 << 4) +#define INT_MASK_TXC (1 << 5) /* transmit control frame */ +#define INT_MASK_RXC (1 << 6) /* receive control frame */ + +#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) +#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) + +#define INT_MASK_ALL ( \ + INT_MASK_TXF | INT_MASK_TXE | \ + INT_MASK_RXF | INT_MASK_RXE | \ + INT_MASK_TXC | INT_MASK_RXC | \ + INT_MASK_BUSY \ + ) + +/* packet length register */ +#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16) +#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0) +#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \ + PACKETLEN_MAX(max)) + +/* transmit buffer number register */ +#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80) + +/* control module mode register */ +#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */ +#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */ +#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */ + +/* MII mode register */ +#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */ +#define MIIMODER_NOPRE (1 << 8) /* no preamble */ + +/* MII command register */ +#define MIICOMMAND_SCAN (1 << 0) /* scan status */ +#define MIICOMMAND_READ (1 << 1) /* read status */ +#define MIICOMMAND_WRITE (1 << 2) /* write control data */ + +/* MII address register */ +#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0) +#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8) +#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \ + MIIADDRESS_RGAD(reg)) + +/* MII transmit data register */ +#define MIITX_DATA_VAL(x) ((x) & 0xffff) + +/* MII receive data register */ +#define MIIRX_DATA_VAL(x) ((x) & 0xffff) + +/* MII status register */ +#define MIISTATUS_LINKFAIL (1 << 0) +#define MIISTATUS_BUSY (1 << 1) +#define MIISTATUS_INVALID (1 << 2) + +/* TX buffer descriptor */ +#define TX_BD_CS (1 << 0) /* carrier sense lost */ +#define TX_BD_DF (1 << 1) /* defer indication */ +#define TX_BD_LC (1 << 2) /* late collision */ +#define TX_BD_RL (1 << 3) /* retransmission limit */ +#define TX_BD_RETRY_MASK (0x00f0) +#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4) +#define TX_BD_UR (1 << 8) /* transmitter underrun */ +#define TX_BD_CRC (1 << 11) /* TX CRC enable */ +#define TX_BD_PAD (1 << 12) /* pad enable */ +#define TX_BD_WRAP (1 << 13) +#define TX_BD_IRQ (1 << 14) /* interrupt request enable */ +#define TX_BD_READY (1 << 15) /* TX buffer ready */ +#define TX_BD_LEN(x) (((x) & 0xffff) << 16) +#define TX_BD_LEN_MASK (0xffff << 16) + +#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \ + TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR) + +/* RX buffer descriptor */ +#define RX_BD_LC (1 << 0) /* late collision */ +#define RX_BD_CRC (1 << 1) /* RX CRC error */ +#define RX_BD_SF (1 << 2) /* short frame */ +#define RX_BD_TL (1 << 3) /* too long */ +#define RX_BD_DN (1 << 4) /* dribble nibble */ +#define RX_BD_IS (1 << 5) /* invalid symbol */ +#define RX_BD_OR (1 << 6) /* receiver overrun */ +#define RX_BD_MISS (1 << 7) +#define RX_BD_CF (1 << 8) /* control frame */ +#define RX_BD_WRAP (1 << 13) +#define RX_BD_IRQ (1 << 14) /* interrupt request enable */ +#define RX_BD_EMPTY (1 << 15) +#define RX_BD_LEN(x) (((x) & 0xffff) << 16) + +#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \ + RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS) + +#define ETHOC_BUFSIZ 1536 +#define ETHOC_ZLEN 64 +#define ETHOC_BD_BASE 0x400 +#define ETHOC_TIMEOUT (HZ / 2) +#define ETHOC_MII_TIMEOUT (1 + (HZ / 5)) + +/** + * struct ethoc - driver-private device structure + * @num_tx: number of send buffers + * @cur_tx: last send buffer written + * @dty_tx: last buffer actually sent + * @num_rx: number of receive buffers + * @cur_rx: current receive buffer + */ +struct ethoc { + u32 num_tx; + u32 cur_tx; + u32 dty_tx; + u32 num_rx; + u32 cur_rx; +}; + +/** + * struct ethoc_bd - buffer descriptor + * @stat: buffer statistics + * @addr: physical memory address + */ +struct ethoc_bd { + u32 stat; + u32 addr; +}; + +static inline u32 ethoc_read(struct eth_device *dev, loff_t offset) +{ + return readl(dev->iobase + offset); +} + +static inline void ethoc_write(struct eth_device *dev, loff_t offset, u32 data) +{ + writel(data, dev->iobase + offset); +} + +static inline void ethoc_read_bd(struct eth_device *dev, int index, + struct ethoc_bd *bd) +{ + loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); + bd->stat = ethoc_read(dev, offset + 0); + bd->addr = ethoc_read(dev, offset + 4); +} + +static inline void ethoc_write_bd(struct eth_device *dev, int index, + const struct ethoc_bd *bd) +{ + loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); + ethoc_write(dev, offset + 0, bd->stat); + ethoc_write(dev, offset + 4, bd->addr); +} + +static inline void ethoc_set_mac_address(struct eth_device *dev) +{ + u8 *mac = dev->enetaddr; + + ethoc_write(dev, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | + (mac[4] << 8) | (mac[5] << 0)); + ethoc_write(dev, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); +} + +static inline void ethoc_ack_irq(struct eth_device *dev, u32 mask) +{ + ethoc_write(dev, INT_SOURCE, mask); +} + +static inline void ethoc_enable_rx_and_tx(struct eth_device *dev) +{ + u32 mode = ethoc_read(dev, MODER); + mode |= MODER_RXEN | MODER_TXEN; + ethoc_write(dev, MODER, mode); +} + +static inline void ethoc_disable_rx_and_tx(struct eth_device *dev) +{ + u32 mode = ethoc_read(dev, MODER); + mode &= ~(MODER_RXEN | MODER_TXEN); + ethoc_write(dev, MODER, mode); +} + +static int ethoc_init_ring(struct eth_device *dev) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + struct ethoc_bd bd; + int i; + + priv->cur_tx = 0; + priv->dty_tx = 0; + priv->cur_rx = 0; + + /* setup transmission buffers */ + bd.stat = TX_BD_IRQ | TX_BD_CRC; + + for (i = 0; i < priv->num_tx; i++) { + if (i == priv->num_tx - 1) + bd.stat |= TX_BD_WRAP; + + ethoc_write_bd(dev, i, &bd); + } + + bd.stat = RX_BD_EMPTY | RX_BD_IRQ; + + for (i = 0; i < priv->num_rx; i++) { + bd.addr = (u32)NetRxPackets[i]; + if (i == priv->num_rx - 1) + bd.stat |= RX_BD_WRAP; + + flush_dcache(bd.addr, PKTSIZE_ALIGN); + ethoc_write_bd(dev, priv->num_tx + i, &bd); + } + + return 0; +} + +static int ethoc_reset(struct eth_device *dev) +{ + u32 mode; + + /* TODO: reset controller? */ + + ethoc_disable_rx_and_tx(dev); + + /* TODO: setup registers */ + + /* enable FCS generation and automatic padding */ + mode = ethoc_read(dev, MODER); + mode |= MODER_CRC | MODER_PAD; + ethoc_write(dev, MODER, mode); + + /* set full-duplex mode */ + mode = ethoc_read(dev, MODER); + mode |= MODER_FULLD; + ethoc_write(dev, MODER, mode); + ethoc_write(dev, IPGT, 0x15); + + ethoc_ack_irq(dev, INT_MASK_ALL); + ethoc_enable_rx_and_tx(dev); + return 0; +} + +static int ethoc_init(struct eth_device *dev, bd_t * bd) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + printf("ethoc\n"); + + ethoc_set_mac_address(dev); + + priv->num_tx = 1; + priv->num_rx = PKTBUFSRX; + ethoc_write(dev, TX_BD_NUM, priv->num_tx); + ethoc_init_ring(dev); + ethoc_reset(dev); + + return 0; +} + +static int ethoc_update_rx_stats(struct ethoc_bd *bd) +{ + int ret = 0; + + if (bd->stat & RX_BD_TL) { + debug("ETHOC: " "RX: frame too long\n"); + ret++; + } + + if (bd->stat & RX_BD_SF) { + debug("ETHOC: " "RX: frame too short\n"); + ret++; + } + + if (bd->stat & RX_BD_DN) + debug("ETHOC: " "RX: dribble nibble\n"); + + if (bd->stat & RX_BD_CRC) { + debug("ETHOC: " "RX: wrong CRC\n"); + ret++; + } + + if (bd->stat & RX_BD_OR) { + debug("ETHOC: " "RX: overrun\n"); + ret++; + } + + if (bd->stat & RX_BD_LC) { + debug("ETHOC: " "RX: late collision\n"); + ret++; + } + + return ret; +} + +static int ethoc_rx(struct eth_device *dev, int limit) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + int count; + + for (count = 0; count < limit; ++count) { + u32 entry; + struct ethoc_bd bd; + + entry = priv->num_tx + (priv->cur_rx % priv->num_rx); + ethoc_read_bd(dev, entry, &bd); + if (bd.stat & RX_BD_EMPTY) + break; + + debug("%s(): RX buffer %d, %x received\n", + __func__, priv->cur_rx, bd.stat); + if (ethoc_update_rx_stats(&bd) == 0) { + int size = bd.stat >> 16; + size -= 4; /* strip the CRC */ + NetReceive((void *)bd.addr, size); + } + + /* clear the buffer descriptor so it can be reused */ + flush_dcache(bd.addr, PKTSIZE_ALIGN); + bd.stat &= ~RX_BD_STATS; + bd.stat |= RX_BD_EMPTY; + ethoc_write_bd(dev, entry, &bd); + priv->cur_rx++; + } + + return count; +} + +static int ethoc_update_tx_stats(struct ethoc_bd *bd) +{ + if (bd->stat & TX_BD_LC) + debug("ETHOC: " "TX: late collision\n"); + + if (bd->stat & TX_BD_RL) + debug("ETHOC: " "TX: retransmit limit\n"); + + if (bd->stat & TX_BD_UR) + debug("ETHOC: " "TX: underrun\n"); + + if (bd->stat & TX_BD_CS) + debug("ETHOC: " "TX: carrier sense lost\n"); + + return 0; +} + +static void ethoc_tx(struct eth_device *dev) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + u32 entry = priv->dty_tx % priv->num_tx; + struct ethoc_bd bd; + + ethoc_read_bd(dev, entry, &bd); + if ((bd.stat & TX_BD_READY) == 0) + (void)ethoc_update_tx_stats(&bd); +} + +static int ethoc_send(struct eth_device *dev, volatile void *packet, int length) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + struct ethoc_bd bd; + u32 entry; + u32 pending; + int tmo; + + entry = priv->cur_tx % priv->num_tx; + ethoc_read_bd(dev, entry, &bd); + if (unlikely(length < ETHOC_ZLEN)) + bd.stat |= TX_BD_PAD; + else + bd.stat &= ~TX_BD_PAD; + bd.addr = (u32)packet; + + flush_dcache(bd.addr, length); + bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK); + bd.stat |= TX_BD_LEN(length); + ethoc_write_bd(dev, entry, &bd); + + /* start transmit */ + bd.stat |= TX_BD_READY; + ethoc_write_bd(dev, entry, &bd); + + /* wait for transfer to succeed */ + tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; + while (1) { + pending = ethoc_read(dev, INT_SOURCE); + ethoc_ack_irq(dev, pending & ~INT_MASK_RX); + if (pending & INT_MASK_BUSY) + debug("%s(): packet dropped\n", __func__); + + if (pending & INT_MASK_TX) { + ethoc_tx(dev); + break; + } + if (get_timer(0) >= tmo) { + debug("%s(): timed out\n", __func__); + return -1; + } + } + + debug("%s(): packet sent\n", __func__); + return 0; +} + +static void ethoc_halt(struct eth_device *dev) +{ + ethoc_disable_rx_and_tx(dev); +} + +static int ethoc_recv(struct eth_device *dev) +{ + u32 pending; + + pending = ethoc_read(dev, INT_SOURCE); + ethoc_ack_irq(dev, pending); + if (pending & INT_MASK_BUSY) + debug("%s(): packet dropped\n", __func__); + if (pending & INT_MASK_RX) { + debug("%s(): rx irq\n", __func__); + ethoc_rx(dev, PKTBUFSRX); + } + + return 0; +} + +int ethoc_initialize(u8 dev_num, int base_addr) +{ + struct ethoc *priv; + struct eth_device *dev; + + priv = malloc(sizeof(*priv)); + if (!priv) + return 0; + dev = malloc(sizeof(*dev)); + if (!dev) { + free(priv); + return 0; + } + + memset(dev, 0, sizeof(*dev)); + dev->priv = priv; + dev->iobase = base_addr; + dev->init = ethoc_init; + dev->halt = ethoc_halt; + dev->send = ethoc_send; + dev->recv = ethoc_recv; + sprintf(dev->name, "%s-%hu", "ETHOC", dev_num); + + eth_register(dev); + return 1; +} diff --git a/include/netdev.h b/include/netdev.h index 1dd80f05937..605edf10436 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -51,6 +51,7 @@ int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis); int ep93xx_eth_initialize(u8 dev_num, int base_addr); +int ethoc_initialize(u8 dev_num, int base_addr); int eth_3com_initialize (bd_t * bis); int fec_initialize (bd_t *bis); int fecmxc_initialize (bd_t *bis); -- cgit v1.3.1 From c960b13ed22d9ea570957379f9f7f2f37d87ef08 Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Tue, 20 Apr 2010 12:49:52 +0800 Subject: net: add altera triple speeds ethernet mac driver This driver supports the Altera triple speeds 10/100/1000 ethernet mac. Signed-off-by: Thomas Chou Signed-off-by: Ben Warren --- drivers/net/Makefile | 1 + drivers/net/altera_tse.c | 935 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/altera_tse.h | 494 +++++++++++++++++++++++++ include/netdev.h | 2 + 4 files changed, 1432 insertions(+) create mode 100644 drivers/net/altera_tse.c create mode 100644 drivers/net/altera_tse.h (limited to 'drivers') diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 0e68e521b05..b75c02f8c23 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libnet.a COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o +COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c new file mode 100644 index 00000000000..59279049aa3 --- /dev/null +++ b/drivers/net/altera_tse.c @@ -0,0 +1,935 @@ +/* + * Altera 10/100/1000 triple speed ethernet mac driver + * + * Copyright (C) 2008 Altera Corporation. + * Copyright (C) 2010 Thomas Chou + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "altera_tse.h" + +/* sgdma debug - print descriptor */ +static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor *desc) +{ + debug("SGDMA DEBUG :\n"); + debug("desc->source : 0x%x \n", (unsigned int)desc->source); + debug("desc->destination : 0x%x \n", (unsigned int)desc->destination); + debug("desc->next : 0x%x \n", (unsigned int)desc->next); + debug("desc->source_pad : 0x%x \n", (unsigned int)desc->source_pad); + debug("desc->destination_pad : 0x%x \n", + (unsigned int)desc->destination_pad); + debug("desc->next_pad : 0x%x \n", (unsigned int)desc->next_pad); + debug("desc->bytes_to_transfer : 0x%x \n", + (unsigned int)desc->bytes_to_transfer); + debug("desc->actual_bytes_transferred : 0x%x \n", + (unsigned int)desc->actual_bytes_transferred); + debug("desc->descriptor_status : 0x%x \n", + (unsigned int)desc->descriptor_status); + debug("desc->descriptor_control : 0x%x \n", + (unsigned int)desc->descriptor_control); +} + +/* This is a generic routine that the SGDMA mode-specific routines + * call to populate a descriptor. + * arg1 :pointer to first SGDMA descriptor. + * arg2 :pointer to next SGDMA descriptor. + * arg3 :Address to where data to be written. + * arg4 :Address from where data to be read. + * arg5 :no of byte to transaction. + * arg6 :variable indicating to generate start of packet or not + * arg7 :read fixed + * arg8 :write fixed + * arg9 :read burst + * arg10 :write burst + * arg11 :atlantic_channel number + */ +static void alt_sgdma_construct_descriptor_burst( + volatile struct alt_sgdma_descriptor *desc, + volatile struct alt_sgdma_descriptor *next, + unsigned int *read_addr, + unsigned int *write_addr, + unsigned short length_or_eop, + int generate_eop, + int read_fixed, + int write_fixed_or_sop, + int read_burst, + int write_burst, + unsigned char atlantic_channel) +{ + /* + * Mark the "next" descriptor as "not" owned by hardware. This prevents + * The SGDMA controller from continuing to process the chain. This is + * done as a single IO write to bypass cache, without flushing + * the entire descriptor, since only the 8-bit descriptor status must + * be flushed. + */ + if (!next) + debug("Next descriptor not defined!!\n"); + + next->descriptor_control = (next->descriptor_control & + ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK); + + desc->source = (unsigned int *)((unsigned int)read_addr & 0x1FFFFFFF); + desc->destination = + (unsigned int *)((unsigned int)write_addr & 0x1FFFFFFF); + desc->next = (unsigned int *)((unsigned int)next & 0x1FFFFFFF); + desc->source_pad = 0x0; + desc->destination_pad = 0x0; + desc->next_pad = 0x0; + desc->bytes_to_transfer = length_or_eop; + desc->actual_bytes_transferred = 0; + desc->descriptor_status = 0x0; + + /* SGDMA burst not currently supported */ + desc->read_burst = 0; + desc->write_burst = 0; + + /* + * Set the descriptor control block as follows: + * - Set "owned by hardware" bit + * - Optionally set "generate EOP" bit + * - Optionally set the "read from fixed address" bit + * - Optionally set the "write to fixed address bit (which serves + * serves as a "generate SOP" control bit in memory-to-stream mode). + * - Set the 4-bit atlantic channel, if specified + * + * Note this step is performed after all other descriptor information + * has been filled out so that, if the controller already happens to be + * pointing at this descriptor, it will not run (via the "owned by + * hardware" bit) until all other descriptor has been set up. + */ + + desc->descriptor_control = + ((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK) | + (generate_eop ? + ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK : 0x0) | + (read_fixed ? + ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK : 0x0) | + (write_fixed_or_sop ? + ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK : 0x0) | + (atlantic_channel ? ((atlantic_channel & 0x0F) << 3) : 0) + ); +} + +static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers *dev, + volatile struct alt_sgdma_descriptor *desc) +{ + unsigned int status; + int counter = 0; + + /* Wait for any pending transfers to complete */ + alt_sgdma_print_desc(desc); + status = dev->status; + + counter = 0; + while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) { + if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + debug("Timeout waiting sgdma in do sync!\n"); + + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + dev->status = 0xFF; + + /* Point the controller at the descriptor */ + dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF; + debug("next desc in sgdma 0x%x\n", + (unsigned int)dev->next_descriptor_pointer); + + /* + * Set up SGDMA controller to: + * - Disable interrupt generation + * - Run once a valid descriptor is written to controller + * - Stop on an error with any particular descriptor + */ + dev->control = (ALT_SGDMA_CONTROL_RUN_MSK | + ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK); + + /* Wait for the descriptor (chain) to complete */ + status = dev->status; + debug("wait for sgdma...."); + while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) + ; + debug("done\n"); + + /* Clear Run */ + dev->control = (dev->control & (~ALT_SGDMA_CONTROL_RUN_MSK)); + + /* Get & clear status register contents */ + status = dev->status; + dev->status = 0xFF; + + /* we really should check if the transfer completes properly */ + debug("tx sgdma status = 0x%x", status); + return 0; +} + +static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev, + volatile struct alt_sgdma_descriptor *desc) +{ + unsigned int status; + int counter = 0; + + /* Wait for any pending transfers to complete */ + alt_sgdma_print_desc(desc); + status = dev->status; + + counter = 0; + while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) { + if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + debug("Timeout waiting sgdma in do async!\n"); + + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + dev->status = 0xFF; + + /* Point the controller at the descriptor */ + dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF; + + /* + * Set up SGDMA controller to: + * - Disable interrupt generation + * - Run once a valid descriptor is written to controller + * - Stop on an error with any particular descriptor + */ + dev->control = (ALT_SGDMA_CONTROL_RUN_MSK | + ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK); + + /* we really should check if the transfer completes properly */ + return 0; +} + +/* u-boot interface */ +static int tse_adjust_link(struct altera_tse_priv *priv) +{ + unsigned int refvar; + + refvar = priv->mac_dev->command_config.image; + + if (!(priv->duplexity)) + refvar |= ALTERA_TSE_CMD_HD_ENA_MSK; + else + refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK; + + switch (priv->speed) { + case 1000: + refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK; + refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; + break; + case 100: + refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; + refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; + break; + case 10: + refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; + refvar |= ALTERA_TSE_CMD_ENA_10_MSK; + break; + } + priv->mac_dev->command_config.image = refvar; + + return 0; +} + +static int tse_eth_send(struct eth_device *dev, + volatile void *packet, int length) +{ + struct altera_tse_priv *priv = dev->priv; + volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; + volatile struct alt_sgdma_descriptor *tx_desc = + (volatile struct alt_sgdma_descriptor *)priv->tx_desc; + + volatile struct alt_sgdma_descriptor *tx_desc_cur = + (volatile struct alt_sgdma_descriptor *)&tx_desc[0]; + + flush_dcache((unsigned long)packet, length); + alt_sgdma_construct_descriptor_burst( + (volatile struct alt_sgdma_descriptor *)&tx_desc[0], + (volatile struct alt_sgdma_descriptor *)&tx_desc[1], + (unsigned int *)packet, /* read addr */ + (unsigned int *)0, + length, /* length or EOP ,will change for each tx */ + 0x1, /* gen eop */ + 0x0, /* read fixed */ + 0x1, /* write fixed or sop */ + 0x0, /* read burst */ + 0x0, /* write burst */ + 0x0 /* channel */ + ); + debug("TX Packet @ 0x%x,0x%x bytes", (unsigned int)packet, length); + + /* send the packet */ + debug("sending packet\n"); + alt_sgdma_do_sync_transfer(tx_sgdma, tx_desc_cur); + debug("sent %d bytes\n", tx_desc_cur->actual_bytes_transferred); + return tx_desc_cur->actual_bytes_transferred; +} + +static int tse_eth_rx(struct eth_device *dev) +{ + int packet_length = 0; + struct altera_tse_priv *priv = dev->priv; + volatile struct alt_sgdma_descriptor *rx_desc = + (volatile struct alt_sgdma_descriptor *)priv->rx_desc; + volatile struct alt_sgdma_descriptor *rx_desc_cur = &rx_desc[0]; + + if (rx_desc_cur->descriptor_status & + ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) { + debug("got packet\n"); + packet_length = rx_desc->actual_bytes_transferred; + NetReceive(NetRxPackets[0], packet_length); + + /* start descriptor again */ + flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); + alt_sgdma_construct_descriptor_burst( + (volatile struct alt_sgdma_descriptor *)&rx_desc[0], + (volatile struct alt_sgdma_descriptor *)&rx_desc[1], + (unsigned int)0x0, /* read addr */ + (unsigned int *)NetRxPackets[0], + 0x0, /* length or EOP */ + 0x0, /* gen eop */ + 0x0, /* read fixed */ + 0x0, /* write fixed or sop */ + 0x0, /* read burst */ + 0x0, /* write burst */ + 0x0 /* channel */ + ); + + /* setup the sgdma */ + alt_sgdma_do_async_transfer(priv->sgdma_rx, &rx_desc[0]); + } + + return -1; +} + +static void tse_eth_halt(struct eth_device *dev) +{ + /* don't do anything! */ + /* this gets called after each uboot */ + /* network command. don't need to reset the thing all of the time */ +} + +static void tse_eth_reset(struct eth_device *dev) +{ + /* stop sgdmas, disable tse receive */ + struct altera_tse_priv *priv = dev->priv; + volatile struct alt_tse_mac *mac_dev = priv->mac_dev; + volatile struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx; + volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; + int counter; + volatile struct alt_sgdma_descriptor *rx_desc = + (volatile struct alt_sgdma_descriptor *)&priv->rx_desc[0]; + + /* clear rx desc & wait for sgdma to complete */ + rx_desc->descriptor_control = 0; + rx_sgdma->control = 0; + counter = 0; + while (rx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) { + if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { + debug("Timeout waiting for rx sgdma!\n"); + rx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + rx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + } + + counter = 0; + tx_sgdma->control = 0; + while (tx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) { + if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { + debug("Timeout waiting for tx sgdma!\n"); + tx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + tx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + } + /* reset the mac */ + mac_dev->command_config.bits.transmit_enable = 1; + mac_dev->command_config.bits.receive_enable = 1; + mac_dev->command_config.bits.software_reset = 1; + + counter = 0; + while (mac_dev->command_config.bits.software_reset) { + if (counter++ > ALT_TSE_SW_RESET_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SW_RESET_WATCHDOG_CNTR) + debug("TSEMAC SW reset bit never cleared!\n"); +} + +static int tse_mdio_read(struct altera_tse_priv *priv, unsigned int regnum) +{ + volatile struct alt_tse_mac *mac_dev; + unsigned int *mdio_regs; + unsigned int data; + u16 value; + + mac_dev = priv->mac_dev; + + /* set mdio address */ + mac_dev->mdio_phy1_addr = priv->phyaddr; + mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; + + /* get the data */ + data = mdio_regs[regnum]; + + value = data & 0xffff; + + return value; +} + +static int tse_mdio_write(struct altera_tse_priv *priv, unsigned int regnum, + unsigned int value) +{ + volatile struct alt_tse_mac *mac_dev; + unsigned int *mdio_regs; + unsigned int data; + + mac_dev = priv->mac_dev; + + /* set mdio address */ + mac_dev->mdio_phy1_addr = priv->phyaddr; + mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; + + /* get the data */ + data = (unsigned int)value; + + mdio_regs[regnum] = data; + + return 0; +} + +/* MDIO access to phy */ +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) +static int altera_tse_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct eth_device *dev; + struct altera_tse_priv *priv; + dev = eth_get_dev_by_name(devname); + priv = dev->priv; + + tse_mdio_write(priv, (uint) reg, (uint) value); + + return 0; +} + +static int altera_tse_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + struct eth_device *dev; + struct altera_tse_priv *priv; + volatile struct alt_tse_mac *mac_dev; + unsigned int *mdio_regs; + + dev = eth_get_dev_by_name(devname); + priv = dev->priv; + + mac_dev = priv->mac_dev; + mac_dev->mdio_phy1_addr = (int)addr; + mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; + + *value = 0xffff & mdio_regs[reg]; + + return 0; + +} +#endif + +/* + * Also copied from tsec.c + */ +/* Parse the status register for link, and then do + * auto-negotiation + */ +static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv) +{ + /* + * Wait if the link is up, and autonegotiation is in progress + * (ie - we're capable and it's not done) + */ + mii_reg = tse_mdio_read(priv, MIIM_STATUS); + + if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) + && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + int i = 0; + + puts("Waiting for PHY auto negotiation to complete"); + while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { + /* + * Timeout reached ? + */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + priv->link = 0; + return 0; + } + + if ((i++ % 1000) == 0) + putc('.'); + udelay(1000); /* 1 ms */ + mii_reg = tse_mdio_read(priv, MIIM_STATUS); + } + puts(" done\n"); + priv->link = 1; + udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & MIIM_STATUS_LINK) { + debug("Link is up\n"); + priv->link = 1; + } else { + debug("Link is down\n"); + priv->link = 0; + } + } + + return 0; +} + +/* Parse the 88E1011's status register for speed and duplex + * information + */ +static uint mii_parse_88E1011_psr(uint mii_reg, struct altera_tse_priv *priv) +{ + uint speed; + + mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS); + + if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && + !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { + int i = 0; + + puts("Waiting for PHY realtime link"); + while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { + /* Timeout reached ? */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + priv->link = 0; + break; + } + + if ((i++ == 1000) == 0) { + i = 0; + puts("."); + } + udelay(1000); /* 1 ms */ + mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS); + } + puts(" done\n"); + udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) + priv->link = 1; + else + priv->link = 0; + } + + if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) + priv->duplexity = 1; + else + priv->duplexity = 0; + + speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); + + switch (speed) { + case MIIM_88E1011_PHYSTAT_GBIT: + priv->speed = 1000; + debug("PHY Speed is 1000Mbit\n"); + break; + case MIIM_88E1011_PHYSTAT_100: + debug("PHY Speed is 100Mbit\n"); + priv->speed = 100; + break; + default: + debug("PHY Speed is 10Mbit\n"); + priv->speed = 10; + } + + return 0; +} + +static uint mii_m88e1111s_setmode_sr(uint mii_reg, struct altera_tse_priv *priv) +{ + uint mii_data = tse_mdio_read(priv, mii_reg); + mii_data &= 0xfff0; + mii_data |= 0xb; + return mii_data; +} + +static uint mii_m88e1111s_setmode_cr(uint mii_reg, struct altera_tse_priv *priv) +{ + uint mii_data = tse_mdio_read(priv, mii_reg); + mii_data &= ~0x82; + mii_data |= 0x82; + return mii_data; +} + +/* + * Returns which value to write to the control register. + * For 10/100, the value is slightly different + */ +static uint mii_cr_init(uint mii_reg, struct altera_tse_priv *priv) +{ + return MIIM_CONTROL_INIT; +} + +/* + * PHY & MDIO code + * Need to add SGMII stuff + * + */ + +static struct phy_info phy_info_M88E1111S = { + 0x01410cc, + "Marvell 88E1111S", + 4, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_88E1111_PHY_EXT_SR, 0x848f, + &mii_m88e1111s_setmode_sr}, + /* Delay RGMII TX and RX */ + {MIIM_88E1111_PHY_EXT_CR, 0x0cd2, + &mii_m88e1111s_setmode_cr}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, +}; + +/* a generic flavor. */ +static struct phy_info phy_info_generic = { + 0, + "Unknown/Generic PHY", + 32, + (struct phy_cmd[]){ /* config */ + {PHY_BMCR, PHY_BMCR_RESET, NULL}, + {PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG, NULL}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + {PHY_BMSR, miim_read, NULL}, + {PHY_BMSR, miim_read, &mii_parse_sr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + } +}; + +static struct phy_info *phy_info[] = { + &phy_info_M88E1111S, + NULL +}; + + /* Grab the identifier of the device's PHY, and search through + * all of the known PHYs to see if one matches. If so, return + * it, if not, return NULL + */ +static struct phy_info *get_phy_info(struct eth_device *dev) +{ + struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv; + uint phy_reg, phy_ID; + int i; + struct phy_info *theInfo = NULL; + + /* Grab the bits from PHYIR1, and put them in the upper half */ + phy_reg = tse_mdio_read(priv, MIIM_PHYIR1); + phy_ID = (phy_reg & 0xffff) << 16; + + /* Grab the bits from PHYIR2, and put them in the lower half */ + phy_reg = tse_mdio_read(priv, MIIM_PHYIR2); + phy_ID |= (phy_reg & 0xffff); + + /* loop through all the known PHY types, and find one that */ + /* matches the ID we read from the PHY. */ + for (i = 0; phy_info[i]; i++) { + if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { + theInfo = phy_info[i]; + break; + } + } + + if (theInfo == NULL) { + theInfo = &phy_info_generic; + debug("%s: No support for PHY id %x; assuming generic\n", + dev->name, phy_ID); + } else + debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); + + return theInfo; +} + +/* Execute the given series of commands on the given device's + * PHY, running functions as necessary + */ +static void phy_run_commands(struct altera_tse_priv *priv, struct phy_cmd *cmd) +{ + int i; + uint result; + + for (i = 0; cmd->mii_reg != miim_end; i++) { + if (cmd->mii_data == miim_read) { + result = tse_mdio_read(priv, cmd->mii_reg); + + if (cmd->funct != NULL) + (*(cmd->funct)) (result, priv); + + } else { + if (cmd->funct != NULL) + result = (*(cmd->funct)) (cmd->mii_reg, priv); + else + result = cmd->mii_data; + + tse_mdio_write(priv, cmd->mii_reg, result); + + } + cmd++; + } +} + +/* Phy init code */ +static int init_phy(struct eth_device *dev) +{ + struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv; + struct phy_info *curphy; + + /* Get the cmd structure corresponding to the attached + * PHY */ + curphy = get_phy_info(dev); + + if (curphy == NULL) { + priv->phyinfo = NULL; + debug("%s: No PHY found\n", dev->name); + + return 0; + } else + debug("%s found\n", curphy->name); + priv->phyinfo = curphy; + + phy_run_commands(priv, priv->phyinfo->config); + + return 1; +} + +static int tse_eth_init(struct eth_device *dev, bd_t * bd) +{ + int dat; + struct altera_tse_priv *priv = dev->priv; + volatile struct alt_tse_mac *mac_dev = priv->mac_dev; + volatile struct alt_sgdma_descriptor *tx_desc = priv->tx_desc; + volatile struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; + volatile struct alt_sgdma_descriptor *rx_desc_cur = + (volatile struct alt_sgdma_descriptor *)&rx_desc[0]; + + /* stop controller */ + debug("Reseting TSE & SGDMAs\n"); + tse_eth_reset(dev); + + /* start the phy */ + debug("Configuring PHY\n"); + phy_run_commands(priv, priv->phyinfo->startup); + + /* need to create sgdma */ + debug("Configuring tx desc\n"); + alt_sgdma_construct_descriptor_burst( + (volatile struct alt_sgdma_descriptor *)&tx_desc[0], + (volatile struct alt_sgdma_descriptor *)&tx_desc[1], + (unsigned int *)NULL, /* read addr */ + (unsigned int *)0, + 0, /* length or EOP ,will change for each tx */ + 0x1, /* gen eop */ + 0x0, /* read fixed */ + 0x1, /* write fixed or sop */ + 0x0, /* read burst */ + 0x0, /* write burst */ + 0x0 /* channel */ + ); + debug("Configuring rx desc\n"); + flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); + alt_sgdma_construct_descriptor_burst( + (volatile struct alt_sgdma_descriptor *)&rx_desc[0], + (volatile struct alt_sgdma_descriptor *)&rx_desc[1], + (unsigned int)0x0, /* read addr */ + (unsigned int *)NetRxPackets[0], + 0x0, /* length or EOP */ + 0x0, /* gen eop */ + 0x0, /* read fixed */ + 0x0, /* write fixed or sop */ + 0x0, /* read burst */ + 0x0, /* write burst */ + 0x0 /* channel */ + ); + /* start rx async transfer */ + debug("Starting rx sgdma\n"); + alt_sgdma_do_async_transfer(priv->sgdma_rx, rx_desc_cur); + + /* start TSE */ + debug("Configuring TSE Mac\n"); + /* Initialize MAC registers */ + mac_dev->max_frame_length = PKTSIZE_ALIGN; + mac_dev->rx_almost_empty_threshold = 8; + mac_dev->rx_almost_full_threshold = 8; + mac_dev->tx_almost_empty_threshold = 8; + mac_dev->tx_almost_full_threshold = 3; + mac_dev->tx_sel_empty_threshold = + CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16; + mac_dev->tx_sel_full_threshold = 0; + mac_dev->rx_sel_empty_threshold = + CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16; + mac_dev->rx_sel_full_threshold = 0; + + /* NO Shift */ + mac_dev->rx_cmd_stat.bits.rx_shift16 = 0; + mac_dev->tx_cmd_stat.bits.tx_shift16 = 0; + + /* enable MAC */ + dat = 0; + dat = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK; + + mac_dev->command_config.image = dat; + + /* Set the MAC address */ + debug("Setting MAC address to 0x%x%x%x%x%x%x\n", + dev->enetaddr[5], dev->enetaddr[4], + dev->enetaddr[3], dev->enetaddr[2], + dev->enetaddr[1], dev->enetaddr[0]); + mac_dev->mac_addr_0 = ((dev->enetaddr[3]) << 24 | + (dev->enetaddr[2]) << 16 | + (dev->enetaddr[1]) << 8 | (dev->enetaddr[0])); + + mac_dev->mac_addr_1 = ((dev->enetaddr[5] << 8 | + (dev->enetaddr[4])) & 0xFFFF); + + /* Set the MAC address */ + mac_dev->supp_mac_addr_0_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_0_1 = mac_dev->mac_addr_1; + + /* Set the MAC address */ + mac_dev->supp_mac_addr_1_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_1_1 = mac_dev->mac_addr_1; + + /* Set the MAC address */ + mac_dev->supp_mac_addr_2_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_2_1 = mac_dev->mac_addr_1; + + /* Set the MAC address */ + mac_dev->supp_mac_addr_3_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_3_1 = mac_dev->mac_addr_1; + + /* configure the TSE core */ + /* -- output clocks, */ + /* -- and later config stuff for SGMII */ + if (priv->link) { + debug("Adjusting TSE to link speed\n"); + tse_adjust_link(priv); + } + + return priv->link ? 0 : -1; +} + +/* TSE init code */ +int altera_tse_initialize(u8 dev_num, int mac_base, + int sgdma_rx_base, int sgdma_tx_base) +{ + struct altera_tse_priv *priv; + struct eth_device *dev; + struct alt_sgdma_descriptor *rx_desc; + struct alt_sgdma_descriptor *tx_desc; + unsigned long dma_handle; + + dev = (struct eth_device *)malloc(sizeof *dev); + + if (NULL == dev) + return 0; + + memset(dev, 0, sizeof *dev); + + priv = malloc(sizeof(*priv)); + + if (!priv) { + free(dev); + return 0; + } + tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX), + &dma_handle); + rx_desc = tx_desc + 2; + debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc); + debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc); + + if (!tx_desc) { + free(priv); + free(dev); + return 0; + } + memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1)); + memset(tx_desc, 0, (sizeof *tx_desc) * 2); + + /* initialize tse priv */ + priv->mac_dev = (volatile struct alt_tse_mac *)mac_base; + priv->sgdma_rx = (volatile struct alt_sgdma_registers *)sgdma_rx_base; + priv->sgdma_tx = (volatile struct alt_sgdma_registers *)sgdma_tx_base; + priv->phyaddr = CONFIG_SYS_ALTERA_TSE_PHY_ADDR; + priv->flags = CONFIG_SYS_ALTERA_TSE_FLAGS; + priv->rx_desc = rx_desc; + priv->tx_desc = tx_desc; + + /* init eth structure */ + dev->priv = priv; + dev->init = tse_eth_init; + dev->halt = tse_eth_halt; + dev->send = tse_eth_send; + dev->recv = tse_eth_rx; + sprintf(dev->name, "%s-%hu", "ALTERA_TSE", dev_num); + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) + miiphy_register(dev->name, altera_tse_miiphy_read, + altera_tse_miiphy_write); +#endif + + init_phy(dev); + + return 1; +} diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h new file mode 100644 index 00000000000..c1cb79e88aa --- /dev/null +++ b/drivers/net/altera_tse.h @@ -0,0 +1,494 @@ +/* + * Altera 10/100/1000 triple speed ethernet mac + * + * Copyright (C) 2008 Altera Corporation. + * Copyright (C) 2010 Thomas Chou + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _ALTERA_TSE_H_ +#define _ALTERA_TSE_H_ + +#define __packed_1_ __attribute__ ((packed, aligned(1))) + +/* PHY Stuff */ +#define miim_end -2 +#define miim_read -1 + +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ + +#ifndef CONFIG_SYS_TBIPA_VALUE +#define CONFIG_SYS_TBIPA_VALUE 0x1f +#endif +#define MIIMCFG_INIT_VALUE 0x00000003 +#define MIIMCFG_RESET 0x80000000 + +#define MIIMIND_BUSY 0x00000001 +#define MIIMIND_NOTVALID 0x00000004 + +#define MIIM_CONTROL 0x00 +#define MIIM_CONTROL_RESET 0x00009140 +#define MIIM_CONTROL_INIT 0x00001140 +#define MIIM_CONTROL_RESTART 0x00001340 +#define MIIM_ANEN 0x00001000 + +#define MIIM_CR 0x00 +#define MIIM_CR_RST 0x00008000 +#define MIIM_CR_INIT 0x00001000 + +#define MIIM_STATUS 0x1 +#define MIIM_STATUS_AN_DONE 0x00000020 +#define MIIM_STATUS_LINK 0x0004 +#define PHY_BMSR_AUTN_ABLE 0x0008 +#define PHY_BMSR_AUTN_COMP 0x0020 + +#define MIIM_PHYIR1 0x2 +#define MIIM_PHYIR2 0x3 + +#define MIIM_ANAR 0x4 +#define MIIM_ANAR_INIT 0x1e1 + +#define MIIM_TBI_ANLPBPA 0x5 +#define MIIM_TBI_ANLPBPA_HALF 0x00000040 +#define MIIM_TBI_ANLPBPA_FULL 0x00000020 + +#define MIIM_TBI_ANEX 0x6 +#define MIIM_TBI_ANEX_NP 0x00000004 +#define MIIM_TBI_ANEX_PRX 0x00000002 + +#define MIIM_GBIT_CONTROL 0x9 +#define MIIM_GBIT_CONTROL_INIT 0xe00 + +#define MIIM_EXT_PAGE_ACCESS 0x1f + +/* 88E1011 PHY Status Register */ +#define MIIM_88E1011_PHY_STATUS 0x11 +#define MIIM_88E1011_PHYSTAT_SPEED 0xc000 +#define MIIM_88E1011_PHYSTAT_GBIT 0x8000 +#define MIIM_88E1011_PHYSTAT_100 0x4000 +#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 +#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 +#define MIIM_88E1011_PHYSTAT_LINK 0x0400 + +#define MIIM_88E1011_PHY_SCR 0x10 +#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 + +#define MIIM_88E1111_PHY_EXT_CR 0x14 +#define MIIM_88E1111_PHY_EXT_SR 0x1b + +/* 88E1111 PHY LED Control Register */ +#define MIIM_88E1111_PHY_LED_CONTROL 24 +#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 +#define MIIM_88E1111_PHY_LED_COMBINE 0x411C + +#define MIIM_READ_COMMAND 0x00000001 + +/* struct phy_info: a structure which defines attributes for a PHY + * id will contain a number which represents the PHY. During + * startup, the driver will poll the PHY to find out what its + * UID--as defined by registers 2 and 3--is. The 32-bit result + * gotten from the PHY will be shifted right by "shift" bits to + * discard any bits which may change based on revision numbers + * unimportant to functionality + * + * The struct phy_cmd entries represent pointers to an arrays of + * commands which tell the driver what to do to the PHY. + */ +struct phy_info { + uint id; + char *name; + uint shift; + /* Called to configure the PHY, and modify the controller + * based on the results */ + struct phy_cmd *config; + + /* Called when starting up the controller */ + struct phy_cmd *startup; + + /* Called when bringing down the controller */ + struct phy_cmd *shutdown; +}; + +/* SGDMA Stuff */ +#define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001) +#define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002) +#define ALT_SGDMA_STATUS_DESC_COMPLETED_MSK (0x00000004) +#define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008) +#define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010) + +#define ALT_SGDMA_CONTROL_IE_ERROR_MSK (0x00000001) +#define ALT_SGDMA_CONTROL_IE_EOP_ENCOUNTERED_MSK (0x00000002) +#define ALT_SGDMA_CONTROL_IE_DESC_COMPLETED_MSK (0x00000004) +#define ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK (0x00000008) +#define ALT_SGDMA_CONTROL_IE_GLOBAL_MSK (0x00000010) +#define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020) +#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040) +#define ALT_SGDMA_CONTROL_IE_MAX_DESC_PROCESSED_MSK (0x00000080) +#define ALT_SGDMA_CONTROL_MAX_DESC_PROCESSED_MSK (0x0000FF00) +#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000) +#define ALT_SGDMA_CONTROL_PARK_MSK (0x00020000) +#define ALT_SGDMA_CONTROL_CLEAR_INTERRUPT_MSK (0x80000000) + +#define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \ + | ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \ + | ALT_SGDMA_CONTROL_IE_GLOBAL_MSK) + +/* + * Descriptor control bit masks & offsets + * + * Note: The control byte physically occupies bits [31:24] in memory. + * The following bit-offsets are expressed relative to the LSB of + * the control register bitfield. + */ +#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x00000008) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080) + +/* + * Descriptor status bit masks & offsets + * + * Note: The status byte physically occupies bits [23:16] in memory. + * The following bit-offsets are expressed relative to the LSB of + * the status register bitfield. + */ +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x00000001) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x00000002) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x00000004) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x00000008) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x00000010) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x00000020) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x00000040) +#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080) +#define ALT_SGDMA_DESCRIPTOR_STATUS_ERROR_MSK (0x0000007F) + +/* + * The SGDMA controller buffer descriptor allocates + * 64 bits for each address. To support ANSI C, the + * struct implementing a descriptor places 32-bits + * of padding directly above each address; each pad must + * be cleared when initializing a descriptor. + */ + +/* + * Buffer Descriptor data structure + * + */ +struct alt_sgdma_descriptor { + unsigned int *source; /* the address of data to be read. */ + unsigned int source_pad; + + unsigned int *destination; /* the address to write data */ + unsigned int destination_pad; + + unsigned int *next; /* the next descriptor in the list. */ + unsigned int next_pad; + + unsigned short bytes_to_transfer; /* the number of bytes to transfer */ + unsigned char read_burst; + unsigned char write_burst; + + unsigned short actual_bytes_transferred;/* bytes transferred by DMA */ + unsigned char descriptor_status; + unsigned char descriptor_control; + +} __packed_1_; + +/* SG-DMA Control/Status Slave registers map */ + +struct alt_sgdma_registers { + unsigned int status; + unsigned int status_pad[3]; + unsigned int control; + unsigned int control_pad[3]; + unsigned int next_descriptor_pointer; + unsigned int descriptor_pad[3]; +}; + +/* TSE Stuff */ +#define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001) +#define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002) +#define ALTERA_TSE_CMD_XON_GEN_MSK (0x00000004) +#define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008) +#define ALTERA_TSE_CMD_PROMIS_EN_MSK (0x00000010) +#define ALTERA_TSE_CMD_PAD_EN_MSK (0x00000020) +#define ALTERA_TSE_CMD_CRC_FWD_MSK (0x00000040) +#define ALTERA_TSE_CMD_PAUSE_FWD_MSK (0x00000080) +#define ALTERA_TSE_CMD_PAUSE_IGNORE_MSK (0x00000100) +#define ALTERA_TSE_CMD_TX_ADDR_INS_MSK (0x00000200) +#define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400) +#define ALTERA_TSE_CMD_EXCESS_COL_MSK (0x00000800) +#define ALTERA_TSE_CMD_LATE_COL_MSK (0x00001000) +#define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000) +#define ALTERA_TSE_CMD_MHASH_SEL_MSK (0x00004000) +#define ALTERA_TSE_CMD_LOOPBACK_MSK (0x00008000) +/* Bits (18:16) = address select */ +#define ALTERA_TSE_CMD_TX_ADDR_SEL_MSK (0x00070000) +#define ALTERA_TSE_CMD_MAGIC_ENA_MSK (0x00080000) +#define ALTERA_TSE_CMD_SLEEP_MSK (0x00100000) +#define ALTERA_TSE_CMD_WAKEUP_MSK (0x00200000) +#define ALTERA_TSE_CMD_XOFF_GEN_MSK (0x00400000) +#define ALTERA_TSE_CMD_CNTL_FRM_ENA_MSK (0x00800000) +#define ALTERA_TSE_CMD_NO_LENGTH_CHECK_MSK (0x01000000) +#define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000) +#define ALTERA_TSE_CMD_RX_ERR_DISC_MSK (0x04000000) +/* Bits (30..27) reserved */ +#define ALTERA_TSE_CMD_CNT_RESET_MSK (0x80000000) + +#define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 (0x00040000) +#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC (0x00020000) + +#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000) + +#define ALT_TSE_SW_RESET_WATCHDOG_CNTR 10000 +#define ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR 90000000 + +/* Command_Config Register Bit Definitions */ + +typedef volatile union __alt_tse_command_config { + unsigned int image; + struct { + unsigned int + transmit_enable:1, /* bit 0 */ + receive_enable:1, /* bit 1 */ + pause_frame_xon_gen:1, /* bit 2 */ + ethernet_speed:1, /* bit 3 */ + promiscuous_enable:1, /* bit 4 */ + pad_enable:1, /* bit 5 */ + crc_forward:1, /* bit 6 */ + pause_frame_forward:1, /* bit 7 */ + pause_frame_ignore:1, /* bit 8 */ + set_mac_address_on_tx:1, /* bit 9 */ + halfduplex_enable:1, /* bit 10 */ + excessive_collision:1, /* bit 11 */ + late_collision:1, /* bit 12 */ + software_reset:1, /* bit 13 */ + multicast_hash_mode_sel:1, /* bit 14 */ + loopback_enable:1, /* bit 15 */ + src_mac_addr_sel_on_tx:3, /* bit 18:16 */ + magic_packet_detect:1, /* bit 19 */ + sleep_mode_enable:1, /* bit 20 */ + wake_up_request:1, /* bit 21 */ + pause_frame_xoff_gen:1, /* bit 22 */ + control_frame_enable:1, /* bit 23 */ + payload_len_chk_disable:1, /* bit 24 */ + enable_10mbps_intf:1, /* bit 25 */ + rx_error_discard_enable:1, /* bit 26 */ + reserved_bits:4, /* bit 30:27 */ + self_clear_counter_reset:1; /* bit 31 */ + } __packed_1_ bits; +} __packed_1_ alt_tse_command_config; + +/* Tx_Cmd_Stat Register Bit Definitions */ + +typedef volatile union __alt_tse_tx_cmd_stat { + unsigned int image; + struct { + unsigned int reserved_lsbs:17, /* bit 16:0 */ + omit_crc:1, /* bit 17 */ + tx_shift16:1, /* bit 18 */ + reserved_msbs:13; /* bit 31:19 */ + + } __packed_1_ bits; +} alt_tse_tx_cmd_stat; + +/* Rx_Cmd_Stat Register Bit Definitions */ + +typedef volatile union __alt_tse_rx_cmd_stat { + unsigned int image; + struct { + unsigned int reserved_lsbs:25, /* bit 24:0 */ + rx_shift16:1, /* bit 25 */ + reserved_msbs:6; /* bit 31:26 */ + + } __packed_1_ bits; +} alt_tse_rx_cmd_stat; + +struct alt_tse_mdio { + unsigned int control; /*PHY device operation control register */ + unsigned int status; /*PHY device operation status register */ + unsigned int phy_id1; /*Bits 31:16 of PHY identifier. */ + unsigned int phy_id2; /*Bits 15:0 of PHY identifier. */ + unsigned int auto_negotiation_advertisement; + unsigned int remote_partner_base_page_ability; + + unsigned int reg6; + unsigned int reg7; + unsigned int reg8; + unsigned int reg9; + unsigned int rega; + unsigned int regb; + unsigned int regc; + unsigned int regd; + unsigned int rege; + unsigned int regf; + unsigned int reg10; + unsigned int reg11; + unsigned int reg12; + unsigned int reg13; + unsigned int reg14; + unsigned int reg15; + unsigned int reg16; + unsigned int reg17; + unsigned int reg18; + unsigned int reg19; + unsigned int reg1a; + unsigned int reg1b; + unsigned int reg1c; + unsigned int reg1d; + unsigned int reg1e; + unsigned int reg1f; +}; + +/* MAC register Space */ + +struct alt_tse_mac { + unsigned int megacore_revision; + unsigned int scratch_pad; + alt_tse_command_config command_config; + unsigned int mac_addr_0; + unsigned int mac_addr_1; + unsigned int max_frame_length; + unsigned int pause_quanta; + unsigned int rx_sel_empty_threshold; + unsigned int rx_sel_full_threshold; + unsigned int tx_sel_empty_threshold; + unsigned int tx_sel_full_threshold; + unsigned int rx_almost_empty_threshold; + unsigned int rx_almost_full_threshold; + unsigned int tx_almost_empty_threshold; + unsigned int tx_almost_full_threshold; + unsigned int mdio_phy0_addr; + unsigned int mdio_phy1_addr; + + /* only if 100/1000 BaseX PCS, reserved otherwise */ + unsigned int reservedx44[5]; + + unsigned int reg_read_access_status; + unsigned int min_tx_ipg_length; + + /* IEEE 802.3 oEntity Managed Object Support */ + unsigned int aMACID_1; /*The MAC addresses */ + unsigned int aMACID_2; + unsigned int aFramesTransmittedOK; + unsigned int aFramesReceivedOK; + unsigned int aFramesCheckSequenceErrors; + unsigned int aAlignmentErrors; + unsigned int aOctetsTransmittedOK; + unsigned int aOctetsReceivedOK; + + /* IEEE 802.3 oPausedEntity Managed Object Support */ + unsigned int aTxPAUSEMACCtrlFrames; + unsigned int aRxPAUSEMACCtrlFrames; + + /* IETF MIB (MIB-II) Object Support */ + unsigned int ifInErrors; + unsigned int ifOutErrors; + unsigned int ifInUcastPkts; + unsigned int ifInMulticastPkts; + unsigned int ifInBroadcastPkts; + unsigned int ifOutDiscards; + unsigned int ifOutUcastPkts; + unsigned int ifOutMulticastPkts; + unsigned int ifOutBroadcastPkts; + + /* IETF RMON MIB Object Support */ + unsigned int etherStatsDropEvent; + unsigned int etherStatsOctets; + unsigned int etherStatsPkts; + unsigned int etherStatsUndersizePkts; + unsigned int etherStatsOversizePkts; + unsigned int etherStatsPkts64Octets; + unsigned int etherStatsPkts65to127Octets; + unsigned int etherStatsPkts128to255Octets; + unsigned int etherStatsPkts256to511Octets; + unsigned int etherStatsPkts512to1023Octets; + unsigned int etherStatsPkts1024to1518Octets; + + unsigned int etherStatsPkts1519toXOctets; + unsigned int etherStatsJabbers; + unsigned int etherStatsFragments; + + unsigned int reservedxE4; + + /*FIFO control register. */ + alt_tse_tx_cmd_stat tx_cmd_stat; + alt_tse_rx_cmd_stat rx_cmd_stat; + + unsigned int ipaccTxConf; + unsigned int ipaccRxConf; + unsigned int ipaccRxStat; + unsigned int ipaccRxStatSum; + + /*Multicast address resolution table */ + unsigned int hash_table[64]; + + /*Registers 0 to 31 within PHY device 0/1 */ + struct alt_tse_mdio mdio_phy0; + struct alt_tse_mdio mdio_phy1; + + /*4 Supplemental MAC Addresses */ + unsigned int supp_mac_addr_0_0; + unsigned int supp_mac_addr_0_1; + unsigned int supp_mac_addr_1_0; + unsigned int supp_mac_addr_1_1; + unsigned int supp_mac_addr_2_0; + unsigned int supp_mac_addr_2_1; + unsigned int supp_mac_addr_3_0; + unsigned int supp_mac_addr_3_1; + + unsigned int reservedx320[56]; +}; + +/* flags: TSE MII modes */ +/* GMII/MII = 0 */ +/* RGMII = 1 */ +/* RGMII_ID = 2 */ +/* RGMII_TXID = 3 */ +/* RGMII_RXID = 4 */ +/* SGMII = 5 */ +struct altera_tse_priv { + char devname[16]; + volatile struct alt_tse_mac *mac_dev; + volatile struct alt_sgdma_registers *sgdma_rx; + volatile struct alt_sgdma_registers *sgdma_tx; + unsigned int rx_sgdma_irq; + unsigned int tx_sgdma_irq; + unsigned int has_descriptor_mem; + unsigned int descriptor_mem_base; + unsigned int descriptor_mem_size; + volatile struct alt_sgdma_descriptor *rx_desc; + volatile struct alt_sgdma_descriptor *tx_desc; + volatile unsigned char *rx_buf; + struct phy_info *phyinfo; + unsigned int phyaddr; + unsigned int flags; + unsigned int link; + unsigned int duplexity; + unsigned int speed; +}; + +/* Phy stuff continued */ +/* + * struct phy_cmd: A command for reading or writing a PHY register + * + * mii_reg: The register to read or write + * + * mii_data: For writes, the value to put in the register. + * A value of -1 indicates this is a read. + * + * funct: A function pointer which is invoked for each command. + * For reads, this function will be passed the value read + * from the PHY, and process it. + * For writes, the result of this function will be written + * to the PHY register + */ +struct phy_cmd { + uint mii_reg; + uint mii_data; + uint(*funct) (uint mii_reg, struct altera_tse_priv *priv); +}; +#endif /* _ALTERA_TSE_H_ */ diff --git a/include/netdev.h b/include/netdev.h index 605edf10436..882642a2c44 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -41,6 +41,8 @@ int board_eth_init(bd_t *bis); int cpu_eth_init(bd_t *bis); /* Driver initialization prototypes */ +int altera_tse_initialize(u8 dev_num, int mac_base, + int sgdma_rx_base, int sgdma_tx_base); int au1x00_enet_initialize(bd_t*); int at91emac_register(bd_t *bis, unsigned long iobase); int bfin_EMAC_initialize(bd_t *bis); -- cgit v1.3.1 From b5ce63ed12b4cd81d211621aca0c222b20d2a691 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Tue, 6 Apr 2010 22:21:33 +0530 Subject: net:kirkwood_egiga.c: MAC addresses programming using write_hwaddr Added a new function kwgbe_write_hwaddr for programming egiga controller's hardware address. This function will be called for each egiga port being used Signed-off-by: Prafulla Wadaskar Signed-off-by: Ben Warren --- drivers/net/kirkwood_egiga.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index dd711e4a105..932792e364a 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -498,6 +498,16 @@ static int kwgbe_halt(struct eth_device *dev) return 0; } +static int kwgbe_write_hwaddr(struct eth_device *dev) +{ + struct kwgbe_device *dkwgbe = to_dkwgbe(dev); + struct kwgbe_registers *regs = dkwgbe->regs; + + /* Programs net device MAC address after initialization */ + port_uc_addr_set(regs, dkwgbe->dev.enetaddr); + return 0; +} + static int kwgbe_send(struct eth_device *dev, volatile void *dataptr, int datasize) { @@ -694,6 +704,7 @@ int kirkwood_egiga_initialize(bd_t * bis) dev->halt = (void *)kwgbe_halt; dev->send = (void *)kwgbe_send; dev->recv = (void *)kwgbe_recv; + dev->write_hwaddr = (void *)kwgbe_write_hwaddr; eth_register(dev); -- cgit v1.3.1 From fb57ec97b90291c589087167f100483a089837bf Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 27 Apr 2010 07:43:52 +0200 Subject: net: fec_mxc: add write_hwaddr support tested on the magnesium board. Signed-off-by: Heiko Schocher Signed-off-by: Ben Warren --- drivers/net/fec_mxc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 68be74775c6..57f89a37a6c 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -505,7 +505,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd) miiphy_restart_aneg(dev); fec_open(dev); - fec_set_hwaddr(dev); return 0; } @@ -713,6 +712,7 @@ static int fec_probe(bd_t *bd) edev->send = fec_send; edev->recv = fec_recv; edev->halt = fec_halt; + edev->write_hwaddr = fec_set_hwaddr; fec->eth = (struct ethernet_regs *)IMX_FEC_BASE; fec->bd = bd; -- cgit v1.3.1 From 6c7c444786fc4022999362fce119c8b731eedcb4 Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Tue, 27 Apr 2010 20:15:10 +0800 Subject: net: altera_tse: add write_hwaddr support Signed-off-by: Thomas Chou Signed-off-by: Ben Warren --- drivers/net/altera_tse.c | 63 +++++++++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 28 deletions(-) (limited to 'drivers') diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c index 59279049aa3..5c0c274ba3a 100644 --- a/drivers/net/altera_tse.c +++ b/drivers/net/altera_tse.c @@ -752,6 +752,40 @@ static int init_phy(struct eth_device *dev) return 1; } +static int tse_set_mac_address(struct eth_device *dev) +{ + struct altera_tse_priv *priv = dev->priv; + volatile struct alt_tse_mac *mac_dev = priv->mac_dev; + + debug("Setting MAC address to 0x%02x%02x%02x%02x%02x%02x\n", + dev->enetaddr[5], dev->enetaddr[4], + dev->enetaddr[3], dev->enetaddr[2], + dev->enetaddr[1], dev->enetaddr[0]); + mac_dev->mac_addr_0 = ((dev->enetaddr[3]) << 24 | + (dev->enetaddr[2]) << 16 | + (dev->enetaddr[1]) << 8 | (dev->enetaddr[0])); + + mac_dev->mac_addr_1 = ((dev->enetaddr[5] << 8 | + (dev->enetaddr[4])) & 0xFFFF); + + /* Set the MAC address */ + mac_dev->supp_mac_addr_0_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_0_1 = mac_dev->mac_addr_1; + + /* Set the MAC address */ + mac_dev->supp_mac_addr_1_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_1_1 = mac_dev->mac_addr_1; + + /* Set the MAC address */ + mac_dev->supp_mac_addr_2_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_2_1 = mac_dev->mac_addr_1; + + /* Set the MAC address */ + mac_dev->supp_mac_addr_3_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_3_1 = mac_dev->mac_addr_1; + return 0; +} + static int tse_eth_init(struct eth_device *dev, bd_t * bd) { int dat; @@ -829,34 +863,6 @@ static int tse_eth_init(struct eth_device *dev, bd_t * bd) mac_dev->command_config.image = dat; - /* Set the MAC address */ - debug("Setting MAC address to 0x%x%x%x%x%x%x\n", - dev->enetaddr[5], dev->enetaddr[4], - dev->enetaddr[3], dev->enetaddr[2], - dev->enetaddr[1], dev->enetaddr[0]); - mac_dev->mac_addr_0 = ((dev->enetaddr[3]) << 24 | - (dev->enetaddr[2]) << 16 | - (dev->enetaddr[1]) << 8 | (dev->enetaddr[0])); - - mac_dev->mac_addr_1 = ((dev->enetaddr[5] << 8 | - (dev->enetaddr[4])) & 0xFFFF); - - /* Set the MAC address */ - mac_dev->supp_mac_addr_0_0 = mac_dev->mac_addr_0; - mac_dev->supp_mac_addr_0_1 = mac_dev->mac_addr_1; - - /* Set the MAC address */ - mac_dev->supp_mac_addr_1_0 = mac_dev->mac_addr_0; - mac_dev->supp_mac_addr_1_1 = mac_dev->mac_addr_1; - - /* Set the MAC address */ - mac_dev->supp_mac_addr_2_0 = mac_dev->mac_addr_0; - mac_dev->supp_mac_addr_2_1 = mac_dev->mac_addr_1; - - /* Set the MAC address */ - mac_dev->supp_mac_addr_3_0 = mac_dev->mac_addr_0; - mac_dev->supp_mac_addr_3_1 = mac_dev->mac_addr_1; - /* configure the TSE core */ /* -- output clocks, */ /* -- and later config stuff for SGMII */ @@ -920,6 +926,7 @@ int altera_tse_initialize(u8 dev_num, int mac_base, dev->halt = tse_eth_halt; dev->send = tse_eth_send; dev->recv = tse_eth_rx; + dev->write_hwaddr = tse_set_mac_address; sprintf(dev->name, "%s-%hu", "ALTERA_TSE", dev_num); eth_register(dev); -- cgit v1.3.1 From 3ac9d6c650d94c51645efa446c1d914c5440990d Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Tue, 27 Apr 2010 20:20:27 +0800 Subject: net: ethoc: add write_hwaddr support Signed-off-by: Thomas Chou Signed-off-by: Ben Warren --- drivers/net/ethoc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index b912e446506..34cc47f3923 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -215,13 +215,14 @@ static inline void ethoc_write_bd(struct eth_device *dev, int index, ethoc_write(dev, offset + 4, bd->addr); } -static inline void ethoc_set_mac_address(struct eth_device *dev) +static int ethoc_set_mac_address(struct eth_device *dev) { u8 *mac = dev->enetaddr; ethoc_write(dev, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0)); ethoc_write(dev, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); + return 0; } static inline void ethoc_ack_irq(struct eth_device *dev, u32 mask) @@ -308,8 +309,6 @@ static int ethoc_init(struct eth_device *dev, bd_t * bd) struct ethoc *priv = (struct ethoc *)dev->priv; printf("ethoc\n"); - ethoc_set_mac_address(dev); - priv->num_tx = 1; priv->num_rx = PKTBUFSRX; ethoc_write(dev, TX_BD_NUM, priv->num_tx); @@ -504,6 +503,7 @@ int ethoc_initialize(u8 dev_num, int base_addr) dev->halt = ethoc_halt; dev->send = ethoc_send; dev->recv = ethoc_recv; + dev->write_hwaddr = ethoc_set_mac_address; sprintf(dev->name, "%s-%hu", "ETHOC", dev_num); eth_register(dev); -- cgit v1.3.1 From 4324dc72df5879e5b614c4a3f326884723ede9b7 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 27 Apr 2010 14:15:28 -0400 Subject: Blackfin: bfin_mac: hook up new write_hwaddr function Signed-off-by: Mike Frysinger Signed-off-by: Ben Warren --- drivers/net/bfin_mac.c | 28 +++++++++++++++------------- drivers/net/bfin_mac.h | 3 +-- 2 files changed, 16 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index ec45b6355a6..720e12605ec 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -106,6 +106,7 @@ int bfin_EMAC_initialize(bd_t *bis) dev->halt = bfin_EMAC_halt; dev->send = bfin_EMAC_send; dev->recv = bfin_EMAC_recv; + dev->write_hwaddr = bfin_EMAC_setup_addr; eth_register(dev); @@ -303,6 +304,19 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) return 0; } +static int bfin_EMAC_setup_addr(struct eth_device *dev) +{ + *pEMAC_ADDRLO = + dev->enetaddr[0] | + dev->enetaddr[1] << 8 | + dev->enetaddr[2] << 16 | + dev->enetaddr[3] << 24; + *pEMAC_ADDRHI = + dev->enetaddr[4] | + dev->enetaddr[5] << 8; + return 0; +} + static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd) { u32 opmode; @@ -318,7 +332,7 @@ static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd) return -1; /* Initialize EMAC address */ - bfin_EMAC_setup_addr(dev->enetaddr); + bfin_EMAC_setup_addr(dev); /* Initialize TX and RX buffer */ for (i = 0; i < PKTBUFSRX; i++) { @@ -376,18 +390,6 @@ static void bfin_EMAC_halt(struct eth_device *dev) } -void bfin_EMAC_setup_addr(uchar *enetaddr) -{ - *pEMAC_ADDRLO = - enetaddr[0] | - enetaddr[1] << 8 | - enetaddr[2] << 16 | - enetaddr[3] << 24; - *pEMAC_ADDRHI = - enetaddr[4] | - enetaddr[5] << 8; -} - ADI_ETHER_BUFFER *SetupRxBuffer(int no) { ADI_ETHER_FRAME_BUFFER *frmbuf; diff --git a/drivers/net/bfin_mac.h b/drivers/net/bfin_mac.h index 8f467a309e1..c731c179b53 100644 --- a/drivers/net/bfin_mac.h +++ b/drivers/net/bfin_mac.h @@ -60,7 +60,6 @@ static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd); static void bfin_EMAC_halt(struct eth_device *dev); static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, int length); static int bfin_EMAC_recv(struct eth_device *dev); - -void bfin_EMAC_setup_addr(uchar *enetaddr); +static int bfin_EMAC_setup_addr(struct eth_device *dev); #endif -- cgit v1.3.1 From 28bb6d34d3f431b7b00444e2f829b2c04f5daf4d Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 4 Apr 2010 23:08:03 +0200 Subject: MX: Added Freescale Power Management Driver The patch add supports for the Freescale's Power Management Controller (known as Atlas) used together with i.MX31/51 processors. It was tested with a MC13783 (MX31) and MC13892 (MX51). Signed-off-by: Stefano Babic --- drivers/misc/Makefile | 1 + drivers/misc/fsl_pmic.c | 200 ++++++++++++++++++++++++++++++++++++++++++++++++ include/fsl_pmic.h | 128 +++++++++++++++++++++++++++++++ 3 files changed, 329 insertions(+) create mode 100644 drivers/misc/fsl_pmic.c create mode 100644 include/fsl_pmic.h (limited to 'drivers') diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index f6df60faef9..96aa331be0a 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -31,6 +31,7 @@ COBJS-$(CONFIG_FSL_LAW) += fsl_law.o COBJS-$(CONFIG_NS87308) += ns87308.o COBJS-$(CONFIG_STATUS_LED) += status_led.o COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o +COBJS-$(CONFIG_FSL_PMIC) += fsl_pmic.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/misc/fsl_pmic.c b/drivers/misc/fsl_pmic.c new file mode 100644 index 00000000000..87f0aedeb68 --- /dev/null +++ b/drivers/misc/fsl_pmic.c @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +static struct spi_slave *slave; + +struct spi_slave *pmic_spi_probe(void) +{ + return spi_setup_slave(CONFIG_FSL_PMIC_BUS, + CONFIG_FSL_PMIC_CS, + CONFIG_FSL_PMIC_CLK, + CONFIG_FSL_PMIC_MODE); +} + +void pmic_spi_free(struct spi_slave *slave) +{ + if (slave) + spi_free_slave(slave); +} + +u32 pmic_reg(u32 reg, u32 val, u32 write) +{ + u32 pmic_tx, pmic_rx; + + if (!slave) { + slave = pmic_spi_probe(); + + if (!slave) + return -1; + } + + if (reg > 63 || write > 1) { + printf(" = %d is invalid. Should be less then 63\n", + reg); + return -1; + } + + if (spi_claim_bus(slave)) + return -1; + + pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF); + + if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx, + SPI_XFER_BEGIN | SPI_XFER_END)) { + spi_release_bus(slave); + return -1; + } + + if (write) { + pmic_tx &= ~(1 << 31); + if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx, + SPI_XFER_BEGIN | SPI_XFER_END)) { + spi_release_bus(slave); + return -1; + } + } + + spi_release_bus(slave); + return pmic_rx; +} + +void pmic_reg_write(u32 reg, u32 value) +{ + pmic_reg(reg, value, 1); +} + +u32 pmic_reg_read(u32 reg) +{ + return pmic_reg(reg, 0, 0); +} + +void pmic_show_pmic_info(void) +{ + u32 rev_id; + + rev_id = pmic_reg_read(REG_IDENTIFICATION); + printf("PMIC ID: 0x%08x [Rev: ", rev_id); + switch (rev_id & 0x1F) { + case 0x1: + puts("1.0"); + break; + case 0x9: + puts("1.1"); + break; + case 0xA: + puts("1.2"); + break; + case 0x10: + puts("2.0"); + break; + case 0x11: + puts("2.1"); + break; + case 0x18: + puts("3.0"); + break; + case 0x19: + puts("3.1"); + break; + case 0x1A: + puts("3.2"); + break; + case 0x2: + puts("3.2A"); + break; + case 0x1B: + puts("3.3"); + break; + case 0x1D: + puts("3.5"); + break; + default: + puts("unknown"); + break; + } + puts("]\n"); +} + +static void pmic_dump(int numregs) +{ + u32 val; + int i; + + pmic_show_pmic_info(); + for (i = 0; i < numregs; i++) { + val = pmic_reg_read(i); + if (!(i % 8)) + printf ("\n0x%02x: ", i); + printf("%08x ", val); + } + puts("\n"); +} + +int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *cmd; + int nregs; + u32 val; + + /* at least two arguments please */ + if (argc < 2) { + cmd_usage(cmdtp); + return 1; + } + + cmd = argv[1]; + if (strcmp(cmd, "dump") == 0) { + if (argc < 3) { + cmd_usage(cmdtp); + return 1; + } + nregs = simple_strtoul(argv[2], NULL, 16); + pmic_dump(nregs); + return 0; + } + if (strcmp(cmd, "write") == 0) { + if (argc < 4) { + cmd_usage(cmdtp); + return 1; + } + nregs = simple_strtoul(argv[2], NULL, 16); + val = simple_strtoul(argv[3], NULL, 16); + pmic_reg_write(nregs, val); + return 0; + } + /* No subcommand found */ + return 1; +} + +U_BOOT_CMD( + pmic, CONFIG_SYS_MAXARGS, 1, do_pmic, + "Freescale PMIC (Atlas)", + "dump [numregs] dump registers\n" + "pmic write - write register" +); diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h new file mode 100644 index 00000000000..e3abde6e4d7 --- /dev/null +++ b/include/fsl_pmic.h @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_PMIC_H__ +#define __FSL_PMIC_H__ + +/* + * The registers of different PMIC has the same meaning + * but the bit positions of the fields can differ or + * some fields has a meaning only on some devices. + * You have to check with the internal SPI bitmap + * (see Freescale Documentation) to set the registers + * for the device you are using + */ +enum { + REG_INT_STATUS0 = 0, + REG_INT_MASK0, + REG_INT_SENSE0, + REG_INT_STATUS1, + REG_INT_MASK1, + REG_INT_SENSE1, + REG_PU_MODE_S, + REG_IDENTIFICATION, + REG_UNUSED0, + REG_ACC0, + REG_ACC1, /*10 */ + REG_UNUSED1, + REG_UNUSED2, + REG_POWER_CTL0, + REG_POWER_CTL1, + REG_POWER_CTL2, + REG_REGEN_ASSIGN, + REG_UNUSED3, + REG_MEM_A, + REG_MEM_B, + REG_RTC_TIME, /*20 */ + REG_RTC_ALARM, + REG_RTC_DAY, + REG_RTC_DAY_ALARM, + REG_SW_0, + REG_SW_1, + REG_SW_2, + REG_SW_3, + REG_SW_4, + REG_SW_5, + REG_SETTING_0, /*30 */ + REG_SETTING_1, + REG_MODE_0, + REG_MODE_1, + REG_POWER_MISC, + REG_UNUSED4, + REG_UNUSED5, + REG_UNUSED6, + REG_UNUSED7, + REG_UNUSED8, + REG_UNUSED9, /*40 */ + REG_UNUSED10, + REG_UNUSED11, + REG_ADC0, + REG_ADC1, + REG_ADC2, + REG_ADC3, + REG_ADC4, + REG_CHARGE, + REG_USB0, + REG_USB1, /*50 */ + REG_LED_CTL0, + REG_LED_CTL1, + REG_LED_CTL2, + REG_LED_CTL3, + REG_UNUSED12, + REG_UNUSED13, + REG_TRIM0, + REG_TRIM1, + REG_TEST0, + REG_TEST1, /*60 */ + REG_TEST2, + REG_TEST3, + REG_TEST4, +}; + +/* REG_POWER_MISC */ +#define GPO1EN (1 << 6) +#define GPO1STBY (1 << 7) +#define GPO2EN (1 << 8) +#define GPO2STBY (1 << 9) +#define GPO3EN (1 << 10) +#define GPO3STBY (1 << 11) +#define GPO4EN (1 << 12) +#define GPO4STBY (1 << 13) +#define PWGT1SPIEN (1 << 15) +#define PWGT2SPIEN (1 << 16) +#define PWUP (1 << 21) + +/* Power Control 0 */ +#define COINCHEN (1 << 23) +#define BATTDETEN (1 << 19) + +/* Interrupt status 1 */ +#define RTCRSTI (1 << 7) + +void pmic_show_pmic_info(void); +void pmic_reg_write(u32 reg, u32 value); +u32 pmic_reg_read(u32 reg); + +#endif -- cgit v1.3.1 From dfe5e14fa263eb8f1a9f087f0284788e7559821d Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 16 Apr 2010 17:11:19 +0200 Subject: MX: RTC13783 uses general function to access PMIC The RTC is part of the Freescale's PMIC controller. Use general function to access to PMIC internal registers. Signed-off-by: Stefano Babic Tested-by: Magnus Lilja --- drivers/rtc/mc13783-rtc.c | 72 +++++++++-------------------------------- include/configs/imx31_litekit.h | 9 ++++-- include/configs/mx31ads.h | 8 +++-- include/configs/mx31pdk.h | 9 +++--- 4 files changed, 31 insertions(+), 67 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/mc13783-rtc.c b/drivers/rtc/mc13783-rtc.c index 416f50d01f9..4e18f80e93b 100644 --- a/drivers/rtc/mc13783-rtc.c +++ b/drivers/rtc/mc13783-rtc.c @@ -23,53 +23,30 @@ #include #include #include - -static struct spi_slave *slave; +#include int rtc_get(struct rtc_time *rtc) { u32 day1, day2, time; - u32 reg; - int err, tim, i = 0; - - if (!slave) { - /* FIXME: Verify the max SCK rate */ - slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS, - CONFIG_MC13783_SPI_CS, 1000000, - SPI_MODE_2 | SPI_CS_HIGH); - if (!slave) - return -1; - } - - if (spi_claim_bus(slave)) - return -1; + int tim, i = 0; do { - reg = 0x2c000000; - err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day1, - SPI_XFER_BEGIN | SPI_XFER_END); - - if (err) - return err; - - reg = 0x28000000; - err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&time, - SPI_XFER_BEGIN | SPI_XFER_END); + day1 = pmic_reg_read(REG_RTC_DAY); + if (day1 < 0) + return -1; - if (err) - return err; + time = pmic_reg_read(REG_RTC_TIME); + if (time < 0) + return -1; - reg = 0x2c000000; - err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day2, - SPI_XFER_BEGIN | SPI_XFER_END); + day2 = pmic_reg_read(REG_RTC_DAY); + if (day2 < 0) + return -1; - if (err) - return err; } while (day1 != day2 && i++ < 3); - spi_release_bus(slave); - tim = day1 * 86400 + time; + to_tm(tim, rtc); rtc->tm_yday = 0; @@ -80,34 +57,15 @@ int rtc_get(struct rtc_time *rtc) int rtc_set(struct rtc_time *rtc) { - u32 time, day, reg; - - if (!slave) { - /* FIXME: Verify the max SCK rate */ - slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS, - CONFIG_MC13783_SPI_CS, 1000000, - SPI_MODE_2 | SPI_CS_HIGH); - if (!slave) - return -1; - } + u32 time, day; time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday, rtc->tm_hour, rtc->tm_min, rtc->tm_sec); day = time / 86400; time %= 86400; - if (spi_claim_bus(slave)) - return -1; - - reg = 0x2c000000 | day | 0x80000000; - spi_xfer(slave, 32, (uchar *)®, (uchar *)&day, - SPI_XFER_BEGIN | SPI_XFER_END); - - reg = 0x28000000 | time | 0x80000000; - spi_xfer(slave, 32, (uchar *)®, (uchar *)&time, - SPI_XFER_BEGIN | SPI_XFER_END); - - spi_release_bus(slave); + pmic_reg_write(REG_RTC_DAY, day); + pmic_reg_write(REG_RTC_TIME, time); return 0; } diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index d58ca8a2a10..49048563cb5 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -68,10 +68,13 @@ #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 1 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 1000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) + #define CONFIG_RTC_MC13783 1 -/* MC13783 connected to CSPI2 and SS0 */ -#define CONFIG_MC13783_SPI_BUS 1 -#define CONFIG_MC13783_SPI_CS 0 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index ec1c9054034..dedecd7fb6a 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -65,10 +65,12 @@ #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 1 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 1000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 -/* MC13783 connected to CSPI2 and SS0 */ -#define CONFIG_MC13783_SPI_BUS 1 -#define CONFIG_MC13783_SPI_CS 0 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index bee2f45a158..0414cc37a7a 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -69,12 +69,13 @@ #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 1 +#define CONFIG_FSL_PMIC_CS 2 +#define CONFIG_FSL_PMIC_CLK 1000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 -/* MC13783 connected to CSPI2 and SS2 */ -#define CONFIG_MC13783_SPI_BUS 1 -#define CONFIG_MC13783_SPI_CS 2 - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -- cgit v1.3.1 From d205ddcfc5b905eff023d5acac395721d80a92c7 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sun, 4 Apr 2010 22:43:38 +0200 Subject: SPI: added support for MX51 to mxc_spi This patch add SPI support for the MX51 processor. Signed-off-by: Stefano Babic --- drivers/spi/mxc_spi.c | 231 +++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 211 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 3a452003ccc..e15a63caca9 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -31,7 +31,7 @@ #error "i.MX27 CSPI not supported due to drastic differences in register definisions" \ "See linux mxc_spi driver from Freescale for details." -#else +#elif defined(CONFIG_MX31) #include @@ -56,6 +56,9 @@ #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 8) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0x1f #define MXC_CSPIPERIOD_32KHZ (1 << 15) @@ -65,12 +68,63 @@ static unsigned long spi_bases[] = { 0x53f84000, }; +#define OUT MX31_GPIO_DIRECTION_OUT +#define mxc_gpio_direction mx31_gpio_direction +#define mxc_gpio_set mx31_gpio_set +#elif defined(CONFIG_MX51) +#include +#include + +#define MXC_CSPIRXDATA 0x00 +#define MXC_CSPITXDATA 0x04 +#define MXC_CSPICTRL 0x08 +#define MXC_CSPICON 0x0C +#define MXC_CSPIINT 0x10 +#define MXC_CSPIDMA 0x14 +#define MXC_CSPISTAT 0x18 +#define MXC_CSPIPERIOD 0x1C +#define MXC_CSPIRESET 0x00 +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_POL 4 +#define MXC_CSPICON_PHA 0 +#define MXC_CSPICON_SSPOL 12 + +static unsigned long spi_bases[] = { + CSPI1_BASE_ADDR, + CSPI2_BASE_ADDR, + CSPI3_BASE_ADDR, +}; +#define mxc_gpio_direction(gpio, dir) (0) +#define mxc_gpio_set(gpio, value) {} +#define OUT 1 +#else +#error "Unsupported architecture" #endif struct mxc_spi_slave { struct spi_slave slave; unsigned long base; u32 ctrl_reg; +#if defined(CONFIG_MX51) + u32 cfg_reg; +#endif int gpio; }; @@ -89,34 +143,161 @@ static inline void reg_write(unsigned long addr, u32 val) *(volatile unsigned long*)addr = val; } +void spi_cs_activate(struct spi_slave *slave) +{ + struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + if (mxcs->gpio > 0) + mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + if (mxcs->gpio > 0) + mxc_gpio_set(mxcs->gpio, + !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL)); +} + +#ifdef CONFIG_MX51 +static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); + s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config; + u32 ss_pol = 0, sclkpol = 0, sclkpha = 0; + + if (max_hz == 0) { + printf("Error: desired clock is 0\n"); + return -1; + } + + reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL); + + /* Reset spi */ + reg_write(mxcs->base + MXC_CSPICTRL, 0); + reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1)); + + /* + * The following computation is taken directly from Freescale's code. + */ + if (clk_src > max_hz) { + pre_div = clk_src / max_hz; + if (pre_div > 16) { + post_div = pre_div / 16; + pre_div = 15; + } + if (post_div != 0) { + for (i = 0; i < 16; i++) { + if ((1 << i) >= post_div) + break; + } + if (i == 16) { + printf("Error: no divider for the freq: %d\n", + max_hz); + return -1; + } + post_div = i; + } + } + + debug("pre_div = %d, post_div=%d\n", pre_div, post_div); + reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | + MXC_CSPICTRL_SELCHAN(cs); + reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | + MXC_CSPICTRL_PREDIV(pre_div); + reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | + MXC_CSPICTRL_POSTDIV(post_div); + + /* always set to master mode */ + reg_ctrl |= 1 << (cs + 4); + + /* We need to disable SPI before changing registers */ + reg_ctrl &= ~MXC_CSPICTRL_EN; + + if (mode & SPI_CS_HIGH) + ss_pol = 1; + + if (!(mode & SPI_CPOL)) + sclkpol = 1; + + if (mode & SPI_CPHA) + sclkpha = 1; + + reg_config = reg_read(mxcs->base + MXC_CSPICON); + + /* + * Configuration register setup + * The MX51 has support different setup for each SS + */ + reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | + (ss_pol << (cs + MXC_CSPICON_SSPOL)); + reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | + (sclkpol << (cs + MXC_CSPICON_POL)); + reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | + (sclkpha << (cs + MXC_CSPICON_PHA)); + + debug("reg_ctrl = 0x%x\n", reg_ctrl); + reg_write(mxcs->base + MXC_CSPICTRL, reg_ctrl); + debug("reg_config = 0x%x\n", reg_config); + reg_write(mxcs->base + MXC_CSPICON, reg_config); + + /* save config register and control register */ + mxcs->ctrl_reg = reg_ctrl; + mxcs->cfg_reg = reg_config; + + /* clear interrupt reg */ + reg_write(mxcs->base + MXC_CSPIINT, 0); + reg_write(mxcs->base + MXC_CSPISTAT, + MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); + + return 0; +} +#endif + static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, unsigned long flags) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); - unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL); - mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) | + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + mxcs->ctrl_reg = (mxcs->ctrl_reg & + ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | MXC_CSPICTRL_BITCOUNT(bitlen - 1); - if (cfg_reg != mxcs->ctrl_reg) - reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg); + reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_EN); +#ifdef CONFIG_MX51 + reg_write(mxcs->base + MXC_CSPICON, mxcs->cfg_reg); +#endif - if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN)) - mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL); + /* Clear interrupt register */ + reg_write(mxcs->base + MXC_CSPISTAT, + MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); + debug("Sending SPI 0x%x\n", data); reg_write(mxcs->base + MXC_CSPITXDATA, data); - reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_XCH); + /* FIFO is written, now starts the transfer setting the XCH bit */ + reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | + MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); - while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH) + /* Wait until the TC (Transfer completed) bit is set */ + while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) ; - if (mxcs->gpio > 0 && (flags & SPI_XFER_END)) { - mx31_gpio_set(mxcs->gpio, - !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL)); - } + /* Transfer completed, clear any pending request */ + reg_write(mxcs->base + MXC_CSPISTAT, + MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); + + data = reg_read(mxcs->base + MXC_CSPIRXDATA); + debug("SPI Rx: 0x%x\n", data); + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return data; - return reg_read(mxcs->base + MXC_CSPIRXDATA); } int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, @@ -176,7 +357,7 @@ static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) if (cs > 3) { mxcs->gpio = cs >> 8; cs &= 3; - ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT); + ret = mxc_gpio_direction(mxcs->gpio, OUT); if (ret) { printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); return -EINVAL; @@ -210,6 +391,20 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, cs = ret; + mxcs->slave.bus = bus; + mxcs->slave.cs = cs; + mxcs->base = spi_bases[bus]; + +#ifdef CONFIG_MX51 + /* Can be used for i.MX31 too ? */ + ctrl_reg = 0; + ret = spi_cfg(mxcs, cs, max_hz, mode); + if (ret) { + printf("mxc_spi: cannot setup SPI controller\n"); + free(mxcs); + return NULL; + } +#else ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | MXC_CSPICTRL_BITCOUNT(31) | MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ @@ -222,12 +417,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, ctrl_reg |= MXC_CSPICTRL_POL; if (mode & SPI_CS_HIGH) ctrl_reg |= MXC_CSPICTRL_SSPOL; - - mxcs->slave.bus = bus; - mxcs->slave.cs = cs; - mxcs->base = spi_bases[bus]; mxcs->ctrl_reg = ctrl_reg; - +#endif return &mxcs->slave; } -- cgit v1.3.1 From b5cebb4fd60fefc7700a486bb74fecc66c07acff Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 5 May 2010 03:20:30 -0400 Subject: Blackfin: TWI/I2C: implement multibus support In order to do this cleanly, the register accesses have to be converted to a C struct (base pointer), so do that in the process. Signed-off-by: Mike Frysinger --- drivers/i2c/bfin-twi_i2c.c | 169 +++++++++++++++++++++++++++++---------------- 1 file changed, 108 insertions(+), 61 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c index 73a78d2237d..b3a04d32074 100644 --- a/drivers/i2c/bfin-twi_i2c.c +++ b/drivers/i2c/bfin-twi_i2c.c @@ -1,7 +1,7 @@ /* * i2c.c - driver for Blackfin on-chip TWI/I2C * - * Copyright (c) 2006-2008 Analog Devices Inc. + * Copyright (c) 2006-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -12,6 +12,35 @@ #include #include +/* Every register is 32bit aligned, but only 16bits in size */ +#define ureg(name) u16 name; u16 __pad_##name; +struct twi_regs { + ureg(clkdiv); + ureg(control); + ureg(slave_ctl); + ureg(slave_stat); + ureg(slave_addr); + ureg(master_ctl); + ureg(master_stat); + ureg(master_addr); + ureg(int_stat); + ureg(int_mask); + ureg(fifo_ctl); + ureg(fifo_stat); + char __pad[0x50]; + ureg(xmt_data8); + ureg(xmt_data16); + ureg(rcv_data8); + ureg(rcv_data16); +}; +#undef ureg + +/* U-Boot I2C framework allows only one active device at a time. */ +#ifdef TWI_CLKDIV +#define TWI0_CLKDIV TWI_CLKDIV +#endif +static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV; + #ifdef DEBUG # define dmemset(s, c, n) memset(s, c, n) #else @@ -19,29 +48,10 @@ #endif #define debugi(fmt, args...) \ debug( \ - "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t" \ - "%-20s:%-3i: " fmt "\n", \ - bfin_read_TWI_MASTER_STAT(), bfin_read_TWI_FIFO_STAT(), bfin_read_TWI_INT_STAT(), \ + "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \ + twi->master_stat, twi->fifo_stat, twi->int_stat, \ __func__, __LINE__, ## args) -#ifdef TWI0_CLKDIV -#define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val) -#define bfin_read_TWI_CLKDIV(val) bfin_read_TWI0_CLKDIV(val) -#define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val) -#define bfin_read_TWI_CONTROL(val) bfin_read_TWI0_CONTROL(val) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write_TWI0_XMT_DATA8(val) -#define bfin_read_TWI_RCV_DATA8() bfin_read_TWI0_RCV_DATA8() -#define bfin_read_TWI_INT_STAT() bfin_read_TWI0_INT_STAT() -#define bfin_write_TWI_INT_STAT(val) bfin_write_TWI0_INT_STAT(val) -#define bfin_read_TWI_MASTER_STAT() bfin_read_TWI0_MASTER_STAT() -#define bfin_write_TWI_MASTER_STAT(val) bfin_write_TWI0_MASTER_STAT(val) -#define bfin_read_TWI_MASTER_CTL() bfin_read_TWI0_MASTER_CTL() -#define bfin_write_TWI_MASTER_CTL(val) bfin_write_TWI0_MASTER_CTL(val) -#define bfin_write_TWI_INT_MASK(val) bfin_write_TWI0_INT_MASK(val) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write_TWI0_FIFO_CTL(val) -#endif - #ifdef CONFIG_TWICLK_KHZ # error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED #endif @@ -87,49 +97,48 @@ static int wait_for_completion(struct i2c_msg *msg) ulong timebase = get_timer(0); do { - int_stat = bfin_read_TWI_INT_STAT(); + int_stat = twi->int_stat; if (int_stat & XMTSERV) { debugi("processing XMTSERV"); - bfin_write_TWI_INT_STAT(XMTSERV); + twi->int_stat = XMTSERV; SSYNC(); if (msg->alen) { - bfin_write_TWI_XMT_DATA8(*(msg->abuf++)); + twi->xmt_data8 = *(msg->abuf++); --msg->alen; } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { - bfin_write_TWI_XMT_DATA8(*(msg->buf++)); + twi->xmt_data8 = *(msg->buf++); --msg->len; } else { - bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | - (msg->flags & I2C_M_COMBO ? RSTART | MDIR : STOP)); + twi->master_ctl |= (msg->flags & I2C_M_COMBO) ? RSTART | MDIR : STOP; SSYNC(); } } if (int_stat & RCVSERV) { debugi("processing RCVSERV"); - bfin_write_TWI_INT_STAT(RCVSERV); + twi->int_stat = RCVSERV; SSYNC(); if (msg->len) { - *(msg->buf++) = bfin_read_TWI_RCV_DATA8(); + *(msg->buf++) = twi->rcv_data8; --msg->len; } else if (msg->flags & I2C_M_STOP) { - bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | STOP); + twi->master_ctl |= STOP; SSYNC(); } } if (int_stat & MERR) { debugi("processing MERR"); - bfin_write_TWI_INT_STAT(MERR); + twi->int_stat = MERR; SSYNC(); return msg->len; } if (int_stat & MCOMP) { debugi("processing MCOMP"); - bfin_write_TWI_INT_STAT(MCOMP); + twi->int_stat = MCOMP; SSYNC(); if (msg->flags & I2C_M_COMBO && msg->len) { - bfin_write_TWI_MASTER_CTL((bfin_read_TWI_MASTER_CTL() & ~RSTART) | - (min(msg->len, 0xff) << 6) | MEN | MDIR); + twi->master_ctl = (twi->master_ctl & ~RSTART) | + (min(msg->len, 0xff) << 6) | MEN | MDIR; SSYNC(); } else break; @@ -172,55 +181,54 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr")); /* wait for things to settle */ - while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) + while (twi->master_stat & BUSBUSY) if (ctrlc()) return 1; /* Set Transmit device address */ - bfin_write_TWI_MASTER_ADDR(chip); + twi->master_addr = chip; /* Clear the FIFO before starting things */ - bfin_write_TWI_FIFO_CTL(XMTFLUSH | RCVFLUSH); + twi->fifo_ctl = XMTFLUSH | RCVFLUSH; SSYNC(); - bfin_write_TWI_FIFO_CTL(0); + twi->fifo_ctl = 0; SSYNC(); /* prime the pump */ if (msg.alen) { len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; debugi("first byte=0x%02x", *msg.abuf); - bfin_write_TWI_XMT_DATA8(*(msg.abuf++)); + twi->xmt_data8 = *(msg.abuf++); --msg.alen; } else if (!(msg.flags & I2C_M_READ) && msg.len) { debugi("first byte=0x%02x", *msg.buf); - bfin_write_TWI_XMT_DATA8(*(msg.buf++)); + twi->xmt_data8 = *(msg.buf++); --msg.len; } /* clear int stat */ - bfin_write_TWI_MASTER_STAT(-1); - bfin_write_TWI_INT_STAT(-1); - bfin_write_TWI_INT_MASK(0); + twi->master_stat = -1; + twi->int_stat = -1; + twi->int_mask = 0; SSYNC(); /* Master enable */ - bfin_write_TWI_MASTER_CTL( - (bfin_read_TWI_MASTER_CTL() & FAST) | + twi->master_ctl = + (twi->master_ctl & FAST) | (min(len, 0xff) << 6) | MEN | - ((msg.flags & I2C_M_READ) ? MDIR : 0) - ); + ((msg.flags & I2C_M_READ) ? MDIR : 0); SSYNC(); - debugi("CTL=0x%04x", bfin_read_TWI_MASTER_CTL()); + debugi("CTL=0x%04x", twi->master_ctl); /* process the rest */ ret = wait_for_completion(&msg); debugi("ret=%d", ret); if (ret) { - bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() & ~MEN); - bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA); + twi->master_ctl &= ~MEN; + twi->control &= ~TWI_ENA; SSYNC(); - bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA); + twi->control |= TWI_ENA; SSYNC(); } @@ -238,10 +246,10 @@ int i2c_set_bus_speed(unsigned int speed) /* Set TWI interface clock */ if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) return -1; - bfin_write_TWI_CLKDIV((clkdiv << 8) | (clkdiv & 0xff)); + twi->clkdiv = (clkdiv << 8) | (clkdiv & 0xff); /* Don't turn it on */ - bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0); + twi->master_ctl = (speed > 100000 ? FAST : 0); return 0; } @@ -253,7 +261,7 @@ int i2c_set_bus_speed(unsigned int speed) unsigned int i2c_get_bus_speed(void) { /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */ - return 5000000 / (bfin_read_TWI_CLKDIV() & 0xff); + return 5000000 / (twi->clkdiv & 0xff); } /** @@ -269,24 +277,23 @@ void i2c_init(int speed, int slaveaddr) uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F; /* Set TWI internal clock as 10MHz */ - bfin_write_TWI_CONTROL(prescale); + twi->control = prescale; /* Set TWI interface clock as specified */ i2c_set_bus_speed(speed); /* Enable it */ - bfin_write_TWI_CONTROL(TWI_ENA | prescale); + twi->control = TWI_ENA | prescale; SSYNC(); - debugi("CONTROL:0x%04x CLKDIV:0x%04x", - bfin_read_TWI_CONTROL(), bfin_read_TWI_CLKDIV()); + debugi("CONTROL:0x%04x CLKDIV:0x%04x", twi->control, twi->clkdiv); #if CONFIG_SYS_I2C_SLAVE # error I2C slave support not tested/supported /* If they want us as a slave, do it */ if (slaveaddr) { - bfin_write_TWI_SLAVE_ADDR(slaveaddr); - bfin_write_TWI_SLAVE_CTL(SEN); + twi->slave_addr = slaveaddr; + twi->slave_ctl = SEN; } #endif } @@ -329,3 +336,43 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { return i2c_transfer(chip, addr, alen, buffer, len, 0); } + +/** + * i2c_set_bus_num - change active I2C bus + * @bus: bus index, zero based + * @returns: 0 on success, non-0 on failure + */ +int i2c_set_bus_num(unsigned int bus) +{ + switch (bus) { +#if CONFIG_SYS_MAX_I2C_BUS > 0 + case 0: twi = (void *)TWI0_CLKDIV; return 0; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 1 + case 1: twi = (void *)TWI1_CLKDIV; return 0; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 2 + case 2: twi = (void *)TWI2_CLKDIV; return 0; +#endif + default: return -1; + } +} + +/** + * i2c_get_bus_num - returns index of active I2C bus + */ +unsigned int i2c_get_bus_num(void) +{ + switch ((unsigned long)twi) { +#if CONFIG_SYS_MAX_I2C_BUS > 0 + case TWI0_CLKDIV: return 0; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 1 + case TWI1_CLKDIV: return 1; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 2 + case TWI2_CLKDIV: return 2; +#endif + default: return -1; + } +} -- cgit v1.3.1 From 167cdad1372917bc11c636c359aad02625291fa9 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:46 +1000 Subject: SERIAL: Enable port-mapped access The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and drop the custom serial port driver Signed-off-by: Graeme Russ --- drivers/serial/ns16550.c | 69 +++++++++++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 23c0f76ddea..7e833fde5fd 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ @@ -14,28 +16,35 @@ #define UART_FCRVAL (UART_FCR_FIFO_EN | \ UART_FCR_RXSR | \ UART_FCR_TXSR) /* Clear & enable FIFOs */ +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED +#define serial_out(x,y) outb(x,(ulong)y) +#define serial_in(y) inb((ulong)y) +#else +#define serial_out(x,y) writeb(x,y) +#define serial_in(y) readb(y) +#endif void NS16550_init (NS16550_t com_port, int baud_divisor) { - com_port->ier = 0x00; + serial_out(0x00, &com_port->ier); #if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2) - com_port->mdr1 = 0x7; /* mode select reset TL16C750*/ + serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif - com_port->lcr = UART_LCR_BKSE | UART_LCRVAL; - com_port->dll = 0; - com_port->dlm = 0; - com_port->lcr = UART_LCRVAL; - com_port->mcr = UART_MCRVAL; - com_port->fcr = UART_FCRVAL; - com_port->lcr = UART_LCR_BKSE | UART_LCRVAL; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = UART_LCRVAL; + serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr); + serial_out(0, &com_port->dll); + serial_out(0, &com_port->dlm); + serial_out(UART_LCRVAL, &com_port->lcr); + serial_out(UART_MCRVAL, &com_port->mcr); + serial_out(UART_FCRVAL, &com_port->fcr); + serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); + serial_out(baud_divisor & 0xff, &com_port->dll); + serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); + serial_out(UART_LCRVAL, &com_port->lcr); #if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2) #if defined(CONFIG_APTIX) - com_port->mdr1 = 3; /* /13 mode so Aptix 6MHz can hit 115200 */ + serial_out(3, &com_port->mdr1); /* /13 mode so Aptix 6MHz can hit 115200 */ #else - com_port->mdr1 = 0; /* /16 is proper to hit 115200 with 48MHz */ + serial_out(0, &com_port->mdr1); /* /16 is proper to hit 115200 with 48MHz */ #endif #endif /* CONFIG_OMAP */ } @@ -43,42 +52,42 @@ void NS16550_init (NS16550_t com_port, int baud_divisor) #ifndef CONFIG_NS16550_MIN_FUNCTIONS void NS16550_reinit (NS16550_t com_port, int baud_divisor) { - com_port->ier = 0x00; - com_port->lcr = UART_LCR_BKSE | UART_LCRVAL; - com_port->dll = 0; - com_port->dlm = 0; - com_port->lcr = UART_LCRVAL; - com_port->mcr = UART_MCRVAL; - com_port->fcr = UART_FCRVAL; - com_port->lcr = UART_LCR_BKSE; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = UART_LCRVAL; + serial_out(0x00, &com_port->ier); + serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); + serial_out(0, &com_port->dll); + serial_out(0, &com_port->dlm); + serial_out(UART_LCRVAL, &com_port->lcr); + serial_out(UART_MCRVAL, &com_port->mcr); + serial_out(UART_FCRVAL, &com_port->fcr); + serial_out(UART_LCR_BKSE, &com_port->lcr); + serial_out(baud_divisor & 0xff, &com_port->dll); + serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); + serial_out(UART_LCRVAL, &com_port->lcr); } #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ void NS16550_putc (NS16550_t com_port, char c) { - while ((com_port->lsr & UART_LSR_THRE) == 0); - com_port->thr = c; + while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0); + serial_out(c, &com_port->thr); } #ifndef CONFIG_NS16550_MIN_FUNCTIONS char NS16550_getc (NS16550_t com_port) { - while ((com_port->lsr & UART_LSR_DR) == 0) { + while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { #ifdef CONFIG_USB_TTY extern void usbtty_poll(void); usbtty_poll(); #endif WATCHDOG_RESET(); } - return (com_port->rbr); + return serial_in(&com_port->rbr); } int NS16550_tstc (NS16550_t com_port) { - return ((com_port->lsr & UART_LSR_DR) != 0); + return ((serial_in(&com_port->lsr) & UART_LSR_DR) != 0); } #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ -- cgit v1.3.1 From 767fdc4af684770f5e97a6c5e19a8ac2616b8329 Mon Sep 17 00:00:00 2001 From: "Ender.Dai" Date: Thu, 22 Apr 2010 15:24:25 +0800 Subject: drivers/*/Makefile: fix conditional compile rule. Fix conditional compile rule for twl4030.c and videomodes.c. Signed-off-by: Ender.Dai --- drivers/usb/phy/Makefile | 1 - drivers/video/Makefile | 9 ++++----- 2 files changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile index 200b907d974..f09e55fd4c3 100644 --- a/drivers/usb/phy/Makefile +++ b/drivers/usb/phy/Makefile @@ -23,7 +23,6 @@ include $(TOPDIR)/config.mk LIB := $(obj)libusb_phy.a COBJS-$(CONFIG_TWL4030_USB) += twl4030.o -COBJS-y := twl4030.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/video/Makefile b/drivers/video/Makefile index a5e339a21b2..7d84fc71a6e 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -25,20 +25,19 @@ include $(TOPDIR)/config.mk LIB := $(obj)libvideo.a -COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o +COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o COBJS-$(CONFIG_S6E63D6) += s6e63d6.o COBJS-$(CONFIG_VIDEO_AMBA) += amba.o -COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o -COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o +COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o +COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o COBJS-$(CONFIG_SED156X) += sed156x.o COBJS-$(CONFIG_VIDEO_SM501) += sm501.o -COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o +COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o -COBJS-y += videomodes.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) -- cgit v1.3.1 From f54fe87acedbbad7d29ad18cab31d2b323717514 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 20 Apr 2010 10:21:25 -0500 Subject: 85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled On the MPC85xx platform if we have SATA its connected on SERDES. Determing if SATA is enabled via sata_initialize should not be board specific and thus we move it out of the MPC8536DS board code. Additionally, now that we have is_serdes_configured() we can determine if the given SATA port is enabled and error out if its not in the driver. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 14 +++++++++++++- board/freescale/mpc8536ds/mpc8536ds.c | 11 ----------- drivers/block/fsl_sata.c | 14 +++++++++++++- 3 files changed, 26 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index e578b296dfa..99431dc1a76 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com @@ -30,9 +30,11 @@ #include #include #include +#include #include #include #include +#include #include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -418,3 +420,13 @@ void arch_preboot_os(void) setup_ivors(); } + +#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) +int sata_initialize(void) +{ + if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) + return __sata_initialize(); + + return 1; +} +#endif diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 8daa0c359a6..1968106711e 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -498,17 +498,6 @@ get_board_ddr_clk(ulong dummy) } #endif -int sata_initialize(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint sdrs2_io_sel = - (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; - if (sdrs2_io_sel & 0x04) - return 1; - - return __sata_initialize(); -} - int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 88785605fa7..4b97a0e226a 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008 Freescale Semiconductor, Inc. + * Copyright (C) 2008,2010 Freescale Semiconductor, Inc. * Dave Liu * * This program is free software; you can redistribute it and/or @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -129,6 +130,17 @@ int init_sata(int dev) return -1; } +#ifdef CONFIG_MPC85xx + if ((dev == 0) && (!is_serdes_configured(SATA1))) { + printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev); + return -1; + } + if ((dev == 1) && (!is_serdes_configured(SATA2))) { + printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev); + return -1; + } +#endif + /* Allocate SATA device driver struct */ sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t)); if (!sata) { -- cgit v1.3.1 From 7b43db92110ec2f15c5f7187a165f2928464966b Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 9 May 2010 23:52:59 +0200 Subject: drivers/mmc/fsl_esdhc.c: fix compiler warnings Commit 77c1458d caused the following compiler warnings: fsl_esdhc.c: In function 'esdhc_pio_read_write': fsl_esdhc.c:142: warning: assignment discards qualifiers from pointer target type fsl_esdhc.c: In function 'esdhc_setup_data': fsl_esdhc.c:169: warning: unused variable 'wml_value' fsl_esdhc.c: In function 'esdhc_pio_read_write': fsl_esdhc.c:164: warning: control reaches end of non-void function Fix these. Signed-off-by: Wolfgang Denk Cc: Dipen Dudhat Cc: Andy Fleming --- drivers/mmc/fsl_esdhc.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a9b07a97c7d..a368fe60db4 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -103,7 +103,7 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) /* * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. */ -static int +static void esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) { struct fsl_esdhc *regs = mmc->priv; @@ -125,7 +125,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) && --timeout); if (timeout <= 0) { printf("\nData Read Failed in PIO Mode."); - return timeout; + return; } while (size && (!(irqstat & IRQSTAT_TC))) { udelay(100); /* Wait before last byte transfer complete */ @@ -139,7 +139,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) } } else { blocks = data->blocks; - buffer = data->src; + buffer = (char *)data->src; while (blocks) { timeout = PIO_TIMEOUT; size = data->blocksize; @@ -148,7 +148,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) && --timeout); if (timeout <= 0) { printf("\nData Write Failed in PIO Mode."); - return timeout; + return; } while (size && (!(irqstat & IRQSTAT_TC))) { udelay(100); /* Wait before last byte transfer complete */ @@ -166,22 +166,12 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) { - uint wml_value; int timeout; struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO + uint wml_value; -#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO - if (!(data->flags & MMC_DATA_READ)) { - if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { - printf("\nThe SD card is locked. " - "Can not write to a locked card.\n\n"); - return TIMEOUT; - } - esdhc_write32(®s->dsaddr, (u32)data->src); - } else - esdhc_write32(®s->dsaddr, (u32)data->dest); -#else wml_value = data->blocksize/4; if (data->flags & MMC_DATA_READ) { @@ -202,7 +192,17 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) wml_value << 16); esdhc_write32(®s->dsaddr, (u32)data->src); } -#endif +#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ + if (!(data->flags & MMC_DATA_READ)) { + if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { + printf("\nThe SD card is locked. " + "Can not write to a locked card.\n\n"); + return TIMEOUT; + } + esdhc_write32(®s->dsaddr, (u32)data->src); + } else + esdhc_write32(®s->dsaddr, (u32)data->dest); +#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); -- cgit v1.3.1 From a599cde7698acc5ae3d0f731b4a7d63a931aae63 Mon Sep 17 00:00:00 2001 From: Serge Ziryukin Date: Mon, 10 May 2010 17:40:49 +0300 Subject: lan91c96, smc911x: remove useless free(ptr) calls on NULL ptr Signed-off-by: Serge Ziryukin --- drivers/net/lan91c96.c | 1 - drivers/net/smc911x.c | 1 - 2 files changed, 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c index 90e40024951..810079f0326 100644 --- a/drivers/net/lan91c96.c +++ b/drivers/net/lan91c96.c @@ -795,7 +795,6 @@ int lan91c96_initialize(u8 dev_num, int base_addr) dev = malloc(sizeof(*dev)); if (!dev) { - free(dev); return 0; } memset(dev, 0, sizeof(*dev)); diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index f2fc88b71d5..3da4c35fc29 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -242,7 +242,6 @@ int smc911x_initialize(u8 dev_num, int base_addr) dev = malloc(sizeof(*dev)); if (!dev) { - free(dev); return -1; } memset(dev, 0, sizeof(*dev)); -- cgit v1.3.1 From 03af5abd85637d27e96fb999ce6e3992293570b0 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 13 May 2010 10:26:40 +0200 Subject: MX31: Added support for the Casio COM57H5M10XRC to QONG The patch adds setup to connect a CASIO COM57H5M10XRC (640x480 TFT display) to the QONG module. Signed-off-by: Stefano Babic --- drivers/video/mx3fb.c | 47 +++++++++++++++++++++++++++++++---------------- include/configs/qong.h | 2 +- 2 files changed, 32 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c index 99a595e8820..7f04b4944f2 100644 --- a/drivers/video/mx3fb.c +++ b/drivers/video/mx3fb.c @@ -56,22 +56,7 @@ void lcd_panel_disable(void) #define msleep(a) udelay(a * 1000) -#ifndef CONFIG_DISPLAY_VBEST_VGG322403 -#define XRES 240 -#define YRES 320 -#define PANEL_TYPE IPU_PANEL_TFT -#define PIXEL_CLK 185925 -#define PIXEL_FMT IPU_PIX_FMT_RGB666 -#define H_START_WIDTH 9 /* left_margin */ -#define H_SYNC_WIDTH 1 /* hsync_len */ -#define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */ -#define V_START_WIDTH 7 /* upper_margin */ -#define V_SYNC_WIDTH 1 /* vsync_len */ -#define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */ -#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) -#define IF_CONF 0 -#define IF_CLK_DIV 0x175 -#else /* Display Vbest VGG322403 */ +#if defined(CONFIG_DISPLAY_VBEST_VGG322403) #define XRES 320 #define YRES 240 #define PANEL_TYPE IPU_PANEL_TFT @@ -86,6 +71,36 @@ void lcd_panel_disable(void) #define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) #define IF_CONF 0 #define IF_CLK_DIV 0x175 +#elif defined(CONFIG_DISPLAY_COM57H5M10XRC) +#define XRES 640 +#define YRES 480 +#define PANEL_TYPE IPU_PANEL_TFT +#define PIXEL_CLK 40000 +#define PIXEL_FMT IPU_PIX_FMT_RGB666 +#define H_START_WIDTH 120 /* left_margin */ +#define H_SYNC_WIDTH 30 /* hsync_len */ +#define H_END_WIDTH (10 + 30) /* right_margin + hsync_len */ +#define V_START_WIDTH 35 /* upper_margin */ +#define V_SYNC_WIDTH 3 /* vsync_len */ +#define V_END_WIDTH (7 + 3) /* lower_margin + vsync_len */ +#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) +#define IF_CONF 0 +#define IF_CLK_DIV 0x175 +#else +#define XRES 240 +#define YRES 320 +#define PANEL_TYPE IPU_PANEL_TFT +#define PIXEL_CLK 185925 +#define PIXEL_FMT IPU_PIX_FMT_RGB666 +#define H_START_WIDTH 9 /* left_margin */ +#define H_SYNC_WIDTH 1 /* hsync_len */ +#define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */ +#define V_START_WIDTH 7 /* upper_margin */ +#define V_SYNC_WIDTH 1 /* vsync_len */ +#define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */ +#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) +#define IF_CONF 0 +#define IF_CLK_DIV 0x175 #endif #define LCD_COLOR_IPU LCD_COLOR16 diff --git a/include/configs/qong.h b/include/configs/qong.h index eb4669ba716..100fa3f8aca 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -84,7 +84,7 @@ #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP -#define CONFIG_DISPLAY_VBEST_VGG322403 +#define CONFIG_DISPLAY_COM57H5M10XRC /* * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the -- cgit v1.3.1 From 1b1f9a9d00447d9eab32ae5633f60a106196b75f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 17 May 2010 10:00:51 +0200 Subject: UBI: Ensure that "background thread" operations are really executed The current U-Boot UBI implementation is copied from Linux. In this porting the UBI background thread was not handled correctly. Upon write operations ubi_wl_flush() makes sure, that all queued operations, like page-erase, are completed. But this is missing for read operations. This patch now makes sure that such operations (like scrubbing upon bit-flip errors) are not queued, but executed directly. Signed-off-by: Stefan Roese --- drivers/mtd/ubi/wl.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index 2f9a5e3653e..88b867a0c17 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -696,8 +696,13 @@ static void schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk) list_add_tail(&wrk->list, &ubi->works); ubi_assert(ubi->works_count >= 0); ubi->works_count += 1; - if (ubi->thread_enabled) - wake_up_process(ubi->bgt_thread); + + /* + * U-Boot special: We have no bgt_thread in U-Boot! + * So just call do_work() here directly. + */ + do_work(ubi); + spin_unlock(&ubi->wl_lock); } -- cgit v1.3.1 From d74dda09f0178079705ee1d641444bac44d3ecd9 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 26 May 2010 22:19:35 +0200 Subject: dm9000x.c: fix compile problems Use readX() / writeX() accessors instead of inX() / outX(). Suggested-by: Mike Frysinger Signed-off-by: Wolfgang Denk --- drivers/net/dm9000x.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index f121286812f..137e41fef50 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -117,12 +117,12 @@ static void DM9000_iow(int reg, u8 value); /* DM9000 network board routine ---------------------------- */ -#define DM9000_outb(d,r) outb(d, r) -#define DM9000_outw(d,r) outw(d, r) -#define DM9000_outl(d,r) outl(d, r) -#define DM9000_inb(r) inb(r) -#define DM9000_inw(r) inw(r) -#define DM9000_inl(r) inl(r) +#define DM9000_outb(d,r) writeb(d, r) +#define DM9000_outw(d,r) writew(d, r) +#define DM9000_outl(d,r) writel(d, r) +#define DM9000_inb(r) readb(r) +#define DM9000_inw(r) readw(r) +#define DM9000_inl(r) readl(r) #ifdef CONFIG_DM9000_DEBUG static void -- cgit v1.3.1 From c4976807cbbabd281f45466ac5e47e5639bcc9cb Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 26 May 2010 23:51:22 +0200 Subject: Coding style cleanup, update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 4045 +++++++++++++++++++++++++++++++++++++ arch/i386/include/asm/bootparam.h | 3 - drivers/serial/opencores_yanu.c | 22 +- 3 files changed, 4057 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/CHANGELOG b/CHANGELOG index d4cd8f121cd..c67da40d502 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,3592 @@ +commit c7da8c19b5f7fd58b5b4b1d247648851af56e1f0 +Author: Andreas Biessmann +Date: Sat May 22 13:17:21 2010 +0200 + + config.mk: use different host compiler for OS X 10.6 + + Compiling tools subdirectory on Mac OS X 10.6 (Snow Leopard) complains about + wrong syntax in system includes. + + In file included from /usr/include/stdio.h:444, + from ../source/u-boot/include/compiler.h:26, + from ../source/u-boot/lib/crc32.c:15: + /usr/include/secure/_stdio.h:46: error: syntax error in macro parameter list + + This can be fixed by reverting the workaround for prior OS X releases in + config.mk conditionally for OS X 10.6+. + + Signed-off-by: Andreas Bießmann + Acked-by: Mike Frysinger + +commit 6ece2550d1c0c5c811b302b1639ea35c2e485203 +Author: Kumar Gala +Date: Fri May 21 04:17:48 2010 -0500 + + Convert Makefiles from COBJS-${} to COBJS-$() + + Match style we use almost everywhere else + + Signed-off-by: Kumar Gala + +commit 59dde44acb82e571808190ccd3cd6b82dc9d7001 +Author: Michael Weiss +Date: Thu May 20 16:09:35 2010 +0200 + + powerpc/bootcount: Fix endianness problem + + For CONFIG_SYS_BOOTCOUNT_SINGLEWORD the code had an endianness problem. + + Signed-off-by: Michael Weiss + Signed-off-by: Detlev Zundel + +commit d74dda09f0178079705ee1d641444bac44d3ecd9 +Author: Wolfgang Denk +Date: Wed May 26 22:19:35 2010 +0200 + + dm9000x.c: fix compile problems + + Use readX() / writeX() accessors instead of inX() / outX(). + + Suggested-by: Mike Frysinger + Signed-off-by: Wolfgang Denk + +commit 40792d675a609c83621d098e48a89de07463b3cd +Author: Wolfgang Denk +Date: Fri May 21 23:14:53 2010 +0200 + + a320evb: fix udelay / __udelay confusion + + Fix the following compiler problems: + + arch/arm/cpu/arm920t/a320/liba320.a(timer.o): In function `udelay': + /home/wd/git/u-boot/work/arch/arm/cpu/arm920t/a320/timer.c:160: multiple definition of `udelay' + lib/libgeneric.a(time.o):/home/wd/git/u-boot/work/lib/time.c:34: first defined here + lib/libgeneric.a(time.o): In function `udelay': + time.c:(.text+0x1c): undefined reference to `__udelay' + + Signed-off-by: Wolfgang Denk + +commit 92381c41c718d260476d5c636c473f50e3b5a79c +Author: Wolfgang Denk +Date: Fri May 21 23:13:18 2010 +0200 + + ARM: */timer.c: fix spelling and vertical alignment + + Signed-off-by: Wolfgang Denk + +commit 3f786bb8542ee85ea898152b40b1f0d98f0801df +Author: Mahavir Jain <[mjain@marvell.com]> +Date: Fri May 21 14:37:48 2010 +0530 + + bugfix: Guruplug: Use standard miiphy + + call to reset PHY chip. + + Current PHY Software Reset operation in guruplug does not + poll reset bit in control register to go to 0(auto clearing) + for making sure reset was successful.This patch uses standard + miiphy call miiphy_reset to make sure proper PHY reset operation. + + Signed-off-by: Mahavir Jain + +commit 71bd860cce4493c5def07804723661e75271052b +Author: Kim Phillips +Date: Wed May 19 17:06:46 2010 -0500 + + mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c + + commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: + retain POR values of non-configured ACR, SPCR, SCCR, and LCRR + bitfields" incorrectly shifted _ (e.g. + ACR_PIPE_DEP) values that were preshifted by their + definition in mpc83xx.h. + + this patch removes the unnecessary shifting for the newly + utilized mask values in cpu_init.c, and prevents seemingly + unrelated symptoms such as an mpc8379erdb board from + locking up whilst performing a networking operation, + e.g. a tftp. + + Signed-off-by: Kim Phillips + +commit f6970d0c545b9134af3b347c75ee3d13545b36d8 +Author: Horst Kronstorfer +Date: Tue May 18 10:37:05 2010 +0200 + + Fixed two typos in arch/powerpc/cpu/mpc83xx/start.S. + + Signed-off-by: Horst Kronstorfer + Signed-off-by: Kim Phillips + +commit 445093d175b06226549680b6894923bb0f5e50fa +Author: Wolfgang Denk +Date: Tue Nov 17 21:27:39 2009 +0100 + + Fix "par[t]ition" typo. + + Signed-off-by: Wolfgang Denk + +commit bdc5f06789c5a0c3a9a2c0eb33ec4d177dbdaa22 +Author: Stefan Roese +Date: Mon May 17 10:01:05 2010 +0200 + + UBI: Fix problem in UBI/Linux "compatibility layer" + + "down_write_trylock" needs to return 1 instead of 0 for success. + Otherwise copying a block with a read error (e.g. bit-flip on read) + won't work correctly. + + Signed-off-by: Stefan Roese + +commit 1b1f9a9d00447d9eab32ae5633f60a106196b75f +Author: Stefan Roese +Date: Mon May 17 10:00:51 2010 +0200 + + UBI: Ensure that "background thread" operations are really executed + + The current U-Boot UBI implementation is copied from Linux. In this + porting the UBI background thread was not handled correctly. Upon write + operations ubi_wl_flush() makes sure, that all queued operations, like + page-erase, are completed. But this is missing for read operations. + + This patch now makes sure that such operations (like scrubbing upon + bit-flip errors) are not queued, but executed directly. + + Signed-off-by: Stefan Roese + +commit 03af5abd85637d27e96fb999ce6e3992293570b0 +Author: Stefano Babic +Date: Thu May 13 10:26:40 2010 +0200 + + MX31: Added support for the Casio COM57H5M10XRC to QONG + + The patch adds setup to connect a CASIO COM57H5M10XRC + (640x480 TFT display) to the QONG module. + + Signed-off-by: Stefano Babic + +commit 2f05e394fccf62a4693c6b8323de725f90d1f003 +Author: Wolfgang Denk +Date: Mon May 17 23:34:18 2010 +0200 + + fsl_diu_fb.c: fix build warnings + + Commit 15351855 "fsl-diu: Using I/O accessor to CCSR space" caused a + number of "passing argument 2 of 'out_be32' makes integer from pointer + without a cast" warnings; fix these. + + Signed-off-by: Wolfgang Denk + Cc: Dave Liu + Cc: Jerry Huang + Cc: Kumar Gala + +commit f2d76ae4fdde180e120ea2d29d6ef881360b3cba +Author: Nick Thompson +Date: Tue May 11 11:29:52 2010 +0100 + + Avoid use of divides in print_size + + Modification of print_size to avoid use of divides and especially + long long divides. Keep the binary scale factor in terms of bit + shifts instead. This should be faster, since the previous code + gave the compiler no clues that the divides where always powers + of two, preventing optimisation. + + Signed-off-by: Nick Thompson + Acked-by: Timur Tabi + +commit a599cde7698acc5ae3d0f731b4a7d63a931aae63 +Author: Serge Ziryukin +Date: Mon May 10 17:40:49 2010 +0300 + + lan91c96, smc911x: remove useless free(ptr) calls on NULL ptr + + Signed-off-by: Serge Ziryukin + +commit b1e1a42bb1ea2f0ddaaea7f4c9d67c98ab38709e +Author: Ron Madrid +Date: Fri May 14 16:27:48 2010 -0700 + + Fix SICRL setting in SIMPC8313 + + This patch sets the SICRL_LBC bits in SICRL to change the function of the + associated pins to GPIO functionality. + + Signed-off-by: Ron Madrid + +commit a4bfc4cc466473b97c7fe84bdf261b2935887e3f +Author: Kim Phillips +Date: Fri May 14 13:18:54 2010 -0500 + + mpc83xx: fix NAND bootstrap too big error + + commit 167cdad1372917bc11c636c359aad02625291fa9 "SERIAL: Enable + port-mapped access" inadvertently broke 83xx nand boards by + converting NS16550_init to use io accessors, which expanded + the size of the generated code. + + this patch fixes the problem by removing icache functions from + the nand builds, which somewhat follows commit + 1a2e203b31d33fb720f2cf1033b241ad36ab405a "mpc83xx: turn on icache + in core initialization to improve u-boot boot time" + + Signed-off-by: Kim Phillips + +commit e74244c5a1c8bcea9b047217277dcd3235a285f4 +Author: Ron Madrid +Date: Mon May 10 15:23:20 2010 -0700 + + Removal of checkboard from spl bootstrap build for SIMPC8313 + + This patch removes the checkboard function from the build of + the 4k bootstrap section for the SIMPC8313 as it is not needed + in the spl build. This will allow > 100 bytes of extra room + for other uses. + + Signed-off-by: Ron Madrid + Signed-off-by: Kim Phillips + +commit 9c3f2d6670e6151f4f6329f572a62b0d2d6768ce +Author: Matthias Fuchs +Date: Tue May 11 09:54:00 2010 +0200 + + ppc4xx: Fix building PLU405 board + + Due to some overlapping sections it's time to update TEXT_BASE + for this board. + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + +commit a2a0a7171303de5d8ce099344efde2e29ee36eb0 +Author: Wolfgang Denk +Date: Sat May 15 21:23:51 2010 +0200 + + Makefile: fix out-of-tree building of "u-boot.img" target + + Signed-off-by: Wolfgang Denk + +commit 2e4f35dbd8e11c3121af99ea8e04ce4fb39e9a4e +Author: Wolfgang Denk +Date: Sat May 15 20:22:21 2010 +0200 + + MVBLM7, MVSMR: fix Makefile (cleanup bootscript.img) + + Fix MVBLM7 and MVSMR Makefiles for correct out-of-tree building + (create "bootscript.img" in build directory instead of source + directory) and cleanup (remove "bootscript.img" when cleaning up). + + Signed-off-by: Wolfgang Denk + Cc: Andre Schwarz + +commit cd4b02be1bb732f3990801ff81b57bd597b1d5b6 +Author: Wolfgang Denk +Date: Mon May 10 23:08:02 2010 +0200 + + ARM: add __aeabi_unwind_cpp_pr0() function to avoid linker complaints + + Signed-off-by: Wolfgang Denk + Tested-by: Thomas Weber + +commit 7b43db92110ec2f15c5f7187a165f2928464966b +Author: Wolfgang Denk +Date: Sun May 9 23:52:59 2010 +0200 + + drivers/mmc/fsl_esdhc.c: fix compiler warnings + + Commit 77c1458d caused the following compiler warnings: + + fsl_esdhc.c: In function 'esdhc_pio_read_write': + fsl_esdhc.c:142: warning: assignment discards qualifiers from pointer target type + fsl_esdhc.c: In function 'esdhc_setup_data': + fsl_esdhc.c:169: warning: unused variable 'wml_value' + fsl_esdhc.c: In function 'esdhc_pio_read_write': + fsl_esdhc.c:164: warning: control reaches end of non-void function + + Fix these. + + Signed-off-by: Wolfgang Denk + Cc: Dipen Dudhat + Cc: Andy Fleming + +commit bcb6c2bb84705bfd73eed5c9a31e9ff24833ee8c +Author: York Sun +Date: Fri May 7 09:12:01 2010 -0500 + + Enabled support for Rev 1.3 SPD for DDR2 DIMMs + + SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3. + The difference has ben examined and the code is compatible. + Speed bins is not verified on hardware for CL7 at this moment. + + This patch also enables SPD Rev 1.x where x is up to "F". According to SPD + spec, the lower nibble is optionally used to determine which additinal bytes + or attribute bits have been defined. Software can safely use defaults. However, + the upper nibble should always be checked. + + Signed-off-by: York Sun + Signed-off-by: Kumar Gala + +commit f54fe87acedbbad7d29ad18cab31d2b323717514 +Author: Kumar Gala +Date: Tue Apr 20 10:21:25 2010 -0500 + + 85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled + + On the MPC85xx platform if we have SATA its connected on SERDES. + Determing if SATA is enabled via sata_initialize should not be board + specific and thus we move it out of the MPC8536DS board code. + + Additionally, now that we have is_serdes_configured() we can determine + if the given SATA port is enabled and error out if its not in the + driver. + + Signed-off-by: Kumar Gala + +commit 54648985e2a64e29784e3ed37cd45b637305cd65 +Author: Kumar Gala +Date: Tue Apr 20 10:21:12 2010 -0500 + + 85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled + + The new is_serdes_configured covers a broader range of devices than the + PCI specific code. Use it instead as we convert away from the + is_fsl_pci_cfg() code. + + Additionally move to setting LAWs for PCI based on if its configured. + Also updated PCI FDT fixup code to remove PCI controllers from dtb if + they are configured. + + Signed-off-by: Kumar Gala + +commit 6ab4011b796e0af130ca160ea3c674d462f3bec4 +Author: Kumar Gala +Date: Tue Apr 20 10:20:33 2010 -0500 + + 85xx: Add is_serdes_configured() support to MPC8536 SERDES + + Add the ability to determine if a given IP block connected on SERDES is + configured. This is useful for things like PCIe and SRIO since they are + only ever connected on SERDES. + + Signed-off-by: Kumar Gala + +commit 15351855776f32d40d9c336c0dc6d22a7bcf40c2 +Author: Jerry Huang +Date: Thu Apr 8 15:56:07 2010 +0800 + + fsl-diu: Using I/O accessor to CCSR space + + Using PPC I/O accessor to DIU I/O space instead of directly + read/write. It will prevent the dozen of compiler order issue + and PPC hardware order issue for accessing I/O space. + + Using the toolchain(tc-fsl-x86lnx-e500-dp-4.3.74-2.i386.rpm) + can show up the order issue of DIU driver. + + Signed-off-by: Dave Liu + Signed-off-by: Jerry Huang + Signed-off-by: Kumar Gala + +commit fd194f82d1c30802f0597a3e359fdc03ed397367 +Author: Andre Schwarz +Date: Mon May 3 13:22:31 2010 +0200 + + mpc83xx/mvBLM7: add usb commands and cleanup. + + Add USB commands. + Rename autoscript to bootscript. + Add automatic bootscript image generation to makefile. + + Signed-off-by: Andre Schwarz + Signed-off-by: Kim Phillips + +commit 3b439792b0781921c599d8af9bed6a771d295b53 +Author: Ron Madrid +Date: Wed Apr 28 16:04:43 2010 -0700 + + mpc83xx: Add UPMA configuration to SIMPC8313 + + Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313 + + Signed-off-by: Ron Madrid + Signed-off-by: Kim Phillips + +commit 5794619e29c5e22280b0b09b2ea6bc3d2e00da3f +Author: Mike Frysinger +Date: Wed May 5 04:32:43 2010 -0400 + + serial: punt unused serial_addr() + + Only one file apparently defines this function, and it merely stubs + it out. So if no one is defining/calling it, punt it. + + Signed-off-by: Mike Frysinger + +commit f745817e741e4251afbd9d5d7f04b2419f4aa9d9 +Author: Mike Frysinger +Date: Tue Apr 27 14:15:34 2010 -0400 + + update include/asm/ gitignore after move + + With the cpu include paths moved, the gitignore paths need updating. + + Signed-off-by: Mike Frysinger + Tested-by: Tom Rix + +commit d0179083a9c9e12c8c5400b107156c14c7da1222 +Author: Kumar Gala +Date: Wed Apr 28 02:52:02 2010 -0500 + + Fixup native builds on powerpc + + When we changed ARCH from ppc to powerpc we need to treat HOSTARCH the + same way. We use HOSTARCH == ARCH to determine if a build is native. + + Signed-off-by: Kumar Gala + +commit 65d342541e78ab9a22bf480cc4fe2f659f94bad4 +Author: Serge Ziryukin +Date: Sun Apr 25 21:32:36 2010 +0300 + + cmd_usb.c: show cmd usage if no args given + + Signed-off-by: Serge Ziryukin + +commit e4a95d112e5ea8368bfbdac6ff963d1b8dc63cf0 +Author: Stefan Roese +Date: Wed Apr 28 10:47:36 2010 +0200 + + powerpc: Consolidate bootcount_{store|load} for PowerPC + + This patch consolidates bootcount_{store|load} for PowerPC by + implementing a common version in arch/powerpc/lib/bootcount.c. This + code is now used by all PowerPC variants that currently have these + functions implemented. + + The functions now use the proper IO-accessor functions to read/write the + values. + + This code also supports two different bootcount versions: + + a) Use 2 separate words (2 * 32bit) to store the bootcounter + b) Use only 1 word (2 * 16bit) to store the bootcounter + + Version b) was already used by MPC5xxx. + + Signed-off-by: Stefan Roese + Acked-by: Detlev Zundel + Acked-by: Kim Phillips + for 83xx parts + Cc: Michael Zaidman + Cc: Wolfgang Denk + Cc: Kim Phillips + Cc: Anatolij Gustschin + +commit 767fdc4af684770f5e97a6c5e19a8ac2616b8329 +Author: Ender.Dai +Date: Thu Apr 22 15:24:25 2010 +0800 + + drivers/*/Makefile: fix conditional compile rule. + + Fix conditional compile rule for twl4030.c and videomodes.c. + + Signed-off-by: Ender.Dai + +commit 54fa2c5b51c564cce716942d26492437457980a4 +Author: Larry Johnson +Date: Tue Apr 20 08:09:43 2010 -0400 + + Move test for unnecessary memmove to memmove_wd() + + Signed-off-by: Larry Johnson + +commit b050c72d52c4e30d5b978ab6758f8dcdbe5c690c +Author: Mike Frysinger +Date: Tue Apr 20 05:49:30 2010 -0400 + + compiler.h: add uint typedef + + Recent crc changes started using the "uint" type in headers that are used + on the build system. This subsequently broke mingw targets as they do not + provide such a type. So add this basic typedef to compiler.h so that we + do not have to worry about this breaking again in the future. + + Signed-off-by: Mike Frysinger + +commit 39f7aacf3fd285b42b92c2c2d66d95339a3569cc +Author: Trübenbach, Ralf +Date: Wed Apr 14 11:15:16 2010 +0200 + + command.c: Enable auto tab for the editenv command + + Enable the auto completion (with TAB) of the environment variable name + after the editenv command. + + Signed-off-by: Ralf Trübenbach + +commit 0738e24e2c1d95bb94455d44485dc5d7b9c9d707 +Author: Reinhard Arlt +Date: Tue Apr 13 09:59:09 2010 +0200 + + 74xx_7xx: CPCI750: Add ECC support on esd CPCI-CPU/750 board + + Add ECC support for DDR RAM for MV64360 on esd CPCI-CPU/750 board. + + This patch also adds the "pldver" command to display the CPLD + revision. + + Signed-off-by: Reinhard Arlt + Signed-off-by: Stefan Roese + +commit 1f9f3cf6ccbccae1c1edff01ec20fe2a586b9701 +Author: Graeme Russ +Date: Sat Apr 24 00:06:00 2010 +1000 + + sc520: Fix minor DRAM Controller Setup bug + + Signed-off-by: Graeme Russ + +commit d20053efdf328d97a018536689fc55df4faf1094 +Author: Graeme Russ +Date: Sat Apr 24 00:05:59 2010 +1000 + + sc520: Update to new AMD Copyright + + AMD recently changed the licensing of the RAM sizing code to the + GPLv2 (or at your option any later version) + + Signed-off-by: Graeme Russ + +commit 880c59e5add3681bd4dca14d2fd20152bee7ad14 +Author: Graeme Russ +Date: Sat Apr 24 00:05:58 2010 +1000 + + eNET: Implement eNET Watchdog + + Signed-off-by: Graeme Russ + +commit f2a55055e9b19f3eba9de97ff454cf8bfef25468 +Author: Graeme Russ +Date: Sat Apr 24 00:05:57 2010 +1000 + + eNET: Use SC520 MMCR to reset eNET board + + Signed-off-by: Graeme Russ + +commit 4a4c31ae08d4dcabe348013e135de28b01c29bf0 +Author: Graeme Russ +Date: Sat Apr 24 00:05:56 2010 +1000 + + eNET: Add PC/AT compatibility setup function + + The eNET uses the sc520 software timers rather than the PC/AT clones + + Set all interrupts and timers up to be PC/AT compatible + + Signed-off-by: Graeme Russ + +commit 8fd805632f95e5e834f312a51aa969bf1d99c41b +Author: Graeme Russ +Date: Sat Apr 24 00:05:55 2010 +1000 + + eNET: Add support for onboard RTL8100B (RTL8139) chips + + Signed-off-by: Graeme Russ + +commit 21e67e796bb1d59a484dce2b4203d61bf1fd5be8 +Author: Graeme Russ +Date: Sat Apr 24 00:05:54 2010 +1000 + + sc520: Board Specific PCI Init + + Signed-off-by: Graeme Russ + +commit 0278216b76fc1e5dbf4cbd10d5d734323039c36f +Author: Graeme Russ +Date: Sat Apr 24 00:05:53 2010 +1000 + + sc520: Move PCI defines to PCI include file + + Signed-off-by: Graeme Russ + +commit 4f197c30e5cb3005909402b7fc630cb092eef02f +Author: Graeme Russ +Date: Sat Apr 24 00:05:52 2010 +1000 + + eNET: Fix CONFIG_SYS_HZ to be 1000 + + The clock interupt has always been 1kHz as per timer_init() in + /arch/i386/cpu/sc520/sc520_timer.c + + Signed-off-by: Graeme Russ + +commit 6fd445c32860bb06e9a68b516845a1bbf7c37889 +Author: Graeme Russ +Date: Sat Apr 24 00:05:51 2010 +1000 + + eNET: Fix Flash Write + + Onboard AMD Flash chip does not support buffered writes + + Signed-off-by: Graeme Russ + +commit 5204566e53a3c519e8795480d056635bc64b11cd +Author: Graeme Russ +Date: Sat Apr 24 00:05:50 2010 +1000 + + sc520: Allow boards to override udelay + + If the board has a high precision mico-second timer, it maked sense to use + it instead of the on-chip one + + Signed-off-by: Graeme Russ + +commit 95ffaba39042064c5eb68404894fd6b0f1d6a3e3 +Author: Graeme Russ +Date: Sat Apr 24 00:05:49 2010 +1000 + + x86: Fix support for booting bzImage + + Add support for newer (up to 2.6.33) kernels + + Add zboot command which takes the address of a bzImage as its first + argument and (optionally) the size of the bzImage as the second argument + (the second argument is needed for older kernels which do not include + the bzImage size in the header) + + Signed-off-by: Graeme Russ + +commit 79ea6b87011c0524ced31359e2be7aac97c29d0a +Author: Graeme Russ +Date: Sat Apr 24 00:05:48 2010 +1000 + + x86: Provide weak PC/AT compatibility setup function + + It is possibly to setup x86 boards to use non-PC/AT configurations. For + example, the sc520 is an x86 CPU with PC/AT and non-PC/AT peripherals. + This function allows the board to set itself up for maximum PC/AT + compatibility just before booting the Linux kernel (the Linux kernel + 'just works' if everything is PC/AT compliant) + + Signed-off-by: Graeme Russ + +commit bf16500f79fdf2653a286b40bb601cb185ac4675 +Author: Graeme Russ +Date: Sat Apr 24 00:05:47 2010 +1000 + + x86: Use CONFIG_SERIAL_MULTI + + Signed-off-by: Graeme Russ + +commit 167cdad1372917bc11c636c359aad02625291fa9 +Author: Graeme Russ +Date: Sat Apr 24 00:05:46 2010 +1000 + + SERIAL: Enable port-mapped access + + The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access + the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped + and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and + drop the custom serial port driver + + Signed-off-by: Graeme Russ + +commit 153c2d9f2397e8b6ca03cfebb4e9666ea0b0637c +Author: Graeme Russ +Date: Sat Apr 24 00:05:45 2010 +1000 + + x86: Fix copying of Real-Mode code into RAM + + Signed-off-by: Graeme Russ + +commit 2fb1bc4f53618743b92a48763d7aaa0ece9ad98f +Author: Graeme Russ +Date: Sat Apr 24 00:05:44 2010 +1000 + + x86: Pass relocation offset into Global Data + + In order to locate the 16-bit BIOS code, we need to know the reloaction + offset. + + Signed-off-by: Graeme Russ + +commit c14a3669b22d3e430b416cdee92b751f13697a1f +Author: Graeme Russ +Date: Sat Apr 24 00:05:43 2010 +1000 + + x86: Move GDT to a safe location in RAM + + Currently, the GDT is either located in FLASH or in the non-relocated + U-Boot image in RAM. Both of these locations are unsafe as those + locations can be erased during a U-Boot update. Move the GDT into the + highest available memory location and relocate U-Boot to just below it + + Signed-off-by: Graeme Russ + +commit 077e1958ca4afe12d88043b123ded058c51b89f7 +Author: Graeme Russ +Date: Sat Apr 24 00:05:42 2010 +1000 + + x86: Add RAM bootstrap functionality + + Add a parameter to the 32-bit entry to indicate if entry is from Real + Mode or not. If entry is from Real Mode, execute the destructive 'sizer' + routine to determine memory size as we are booting cold and running in + Flash. If not entering from Real Mode, we are executing a U-Boot image + from RAM and therefore the memory size is already known (and running + 'sizer' will destroy the running image) + + There are now two 32-bit entry points. The first is the 'in RAM' entry + point which exists at the start of the U-Boot binary image. As such, + you can load u-boot.bin in RAM and jump directly to the load address + without needing to calculate any offsets. The second entry point is + used by the real-to-protected mode switch + + This patch also changes TEXT_BASE to 0x6000000 (in RAM). You can load + the resulting image at 0x6000000 and simple go 0x6000000 from the u-boot + prompt + + Hopefully a later patch will completely elliminate any dependency on + TEXT_BASE like a relocatable linux kernel (perfect world) + + Signed-off-by: Graeme Russ + +commit 759598f82f02cc84614450807cb5de43ca18a339 +Author: Graeme Russ +Date: Sat Apr 24 00:05:41 2010 +1000 + + x86: Split sc520 memory sizing versus reporting + + This patch allows the low-level assembler boot-strap to obtain the RAM + size without calling the destructive 'sizer' routine. This allows + boot-strapping from a U-Boot image loaded in RAM + + Signed-off-by: Graeme Russ + +commit 4dba333b3c7b34073b0439cc942877f98403632c +Author: Graeme Russ +Date: Sat Apr 24 00:05:40 2010 +1000 + + x86: Fix sc520 memory size reporting + + There is an error in how the assembler version of the sc520 memory size + reporting code works. As a result, it will only ever report at most the + size of one bank of RAM + + Signed-off-by: Graeme Russ + +commit 9e08efcfee22570bb3a9ea384bf4d60b378f6092 +Author: Graeme Russ +Date: Sat Apr 24 00:05:39 2010 +1000 + + x86: Fix do_go_exec() + + This was broken a long time ago by a49864593e083a5d0779fb9ca98e5a0f2053183d + which munged the NIOS and x86 do_go_exec() + + Signed-off-by: Graeme Russ + +commit 433ff2bdbccc5190189528305e4ed6f7205dbafd +Author: Graeme Russ +Date: Sat Apr 24 00:05:38 2010 +1000 + + x86: Add register dump to crash handlers + + Shamelessly steal the Linux x86 crash handling code and shove it into + U-Boot (cool - it fits). Be sure to include suitable attribution to + Linus + + Signed-off-by: Graeme Russ + +commit 64a0a4995e79ef9813bb51d5f1ff35ae5dabfc7e +Author: Graeme Russ +Date: Sat Apr 24 00:05:37 2010 +1000 + + x86: Fix MMCR Access + + Change sc520 MMCR Access to use memory accessor functions + + Signed-off-by: Graeme Russ + +commit 535ad2db069aae6d1d36fc05c31cbd8a2b3d8831 +Author: Graeme Russ +Date: Sat Apr 24 00:05:36 2010 +1000 + + x86: #ifdef out getenv_IPaddr() + + Signed-off-by: Graeme Russ + +commit 721c36705a9efc7b67f78d0c3e8485e4f1b8bcc9 +Author: Graeme Russ +Date: Sat Apr 24 00:05:35 2010 +1000 + + x86: Add unaligned.h + + Signed-off-by: Graeme Russ + +commit 93c7e70f648fb817e519f6e163b7ef9befc27349 +Author: Michael Zaidman +Date: Wed Apr 7 18:30:08 2010 +0300 + + POST: Added ECC memory test for mpc83xx. + + Signed-off-by: Michael Zaidman + + Fixed minor coding style issue. + Signed-off-by: Wolfgang Denk + +commit 8cd852824d91e232f1f820a0772c3c1d8af84b05 +Author: Frans Meulenbroeks +Date: Sat Mar 27 17:14:36 2010 +0100 + + cmd_onenand.c: moved to standard subcommand handling + + On the fly also fixed the following things: + - write help talked about a parameter oob, but that one was not used, so + removed it from the help message. + - the test command also allowed a force subcommand but didn't use it. + eliminated the code. + - do_onenand made static + - do_onenand contained + int blocksize; + ... + mtd = &onenand_mtd; + this = mtd->priv; + blocksize = (1 << this->erase_shift); + As blocksize was not used the last two statements were unneeded so + removed them. + The first statement (mtd = ....) assigns to a global. Not sure if it + is needed, and since I could not test this, left the line for now + + Signed-off-by: Frans Meulenbroeks + +commit 3882d7a5a57eb8d1f41570522445bab61c628e6f +Author: Norbert van Bolhuis +Date: Fri Mar 19 15:34:25 2010 +0100 + + ppc: unused memory region too close to current stack pointer + + This avoids a possible overwrite of the (end of) ramdisk by u-boot. + The unused memory region for ppc boot currently starts 1k below the + do_bootm->bootm_start->arch_lmb_reserve stack ptr. This isn't enough since + do_bootm->do_bootm_linux->boot_relocate_fdt calls printf which may + very well use more than 1k stack space. + + Signed-off-by: Norbert van Bolhuis + +commit 4b42c9059e165500353174601a8e97b2cf81d3f4 +Author: Timur Tabi +Date: Tue Apr 13 13:16:03 2010 -0500 + + allow print_size to print large numbers on 32-bit systems + + Modify print_size() so that it can accept numbers larger than 4GB on 32-bit + systems. + + Add support for display terabyte, petabyte, and exabyte sizes. Change the + output to use International Electrotechnical Commission binary prefix standard. + + Signed-off-by: Timur Tabi + +commit 52dbac69c27dee67a4c051b1055d93b0ac4e2062 +Author: Timur Tabi +Date: Tue Apr 13 13:16:02 2010 -0500 + + fix print_size printing fractional gigabyte numbers on 32-bit platforms + + In print_size(), the math that calculates the fractional remainder of a number + used the same integer size as a physical address. However, the "10 *" factor + of the algorithm means that a large number (e.g. 1.5GB) can overflow the + integer if we're running on a 32-bit system. Therefore, we need to + disassociate this function from the size of a physical address. + + Signed-off-by: Timur Tabi + +commit b5cebb4fd60fefc7700a486bb74fecc66c07acff +Author: Mike Frysinger +Date: Wed May 5 03:20:30 2010 -0400 + + Blackfin: TWI/I2C: implement multibus support + + In order to do this cleanly, the register accesses have to be converted to + a C struct (base pointer), so do that in the process. + + Signed-off-by: Mike Frysinger + +commit b4377e12e9aa0b3bf2dcae0a0f02ec9086338506 +Author: Stefano Babic +Date: Tue Mar 16 17:22:21 2010 +0100 + + Add SPI support to mx51evk board + + The patch adds SPI devices to the mx51evk board. + The MC13892 chip (PMIC) is supported. + + Signed-off-by: Stefano Babic + +commit d3588a55d4a041f2208290b8b6f9cecbdad179ac +Author: Stefano Babic +Date: Sun Apr 18 19:27:44 2010 +0200 + + MX: Added definition file for MC13892 + + The MC13892 is a Power Controller used with processors + of the family MX.51. The file adds definitions to be used to setup + the internal registers via SPI. + + Signed-off-by: Stefano Babic + +commit d205ddcfc5b905eff023d5acac395721d80a92c7 +Author: Stefano Babic +Date: Sun Apr 4 22:43:38 2010 +0200 + + SPI: added support for MX51 to mxc_spi + + This patch add SPI support for the MX51 processor. + + Signed-off-by: Stefano Babic + +commit e98ecd71102de9d97bd82be247ed909260fb671b +Author: Stefano Babic +Date: Fri Apr 16 17:13:54 2010 +0200 + + MX31: Add support for PMIC to the QONG module + + Add support for the PMIC (MC13783) controller + and enables charging of the RTC battery. + + Signed-off-by: Stefano Babic + +commit dfe5e14fa263eb8f1a9f087f0284788e7559821d +Author: Stefano Babic +Date: Fri Apr 16 17:11:19 2010 +0200 + + MX: RTC13783 uses general function to access PMIC + + The RTC is part of the Freescale's PMIC controller. + Use general function to access to PMIC internal registers. + + Signed-off-by: Stefano Babic + Tested-by: Magnus Lilja + +commit 28bb6d34d3f431b7b00444e2f829b2c04f5daf4d +Author: Stefano Babic +Date: Sun Apr 4 23:08:03 2010 +0200 + + MX: Added Freescale Power Management Driver + + The patch add supports for the Freescale's Power + Management Controller (known as Atlas) used together with i.MX31/51 + processors. It was tested with a MC13783 (MX31) and + MC13892 (MX51). + + Signed-off-by: Stefano Babic + +commit ba6adeb48e71f7f1b791b6e98999a5680d919b26 +Author: Magnus Lilja +Date: Fri Apr 23 20:30:49 2010 +0200 + + i.MX31: Activate NAND support for i.MX31 Litekit board. + + Signed-off-by: Magnus Lilja + +commit 60381d687885c0e2100657ca73e97e38c4604f5e +Author: Fabio Estevam +Date: Fri Apr 23 06:32:01 2010 -0700 + + MX51: Fix MX51 CPU detect message + + Fix MX51 CPU detect message. + + Original string was: + CPU: Freescale i.MX51 family 3.0V at 800 MHz + + which can be misinterpreted as 3.0 Volts instead of the silicon revision. + + ,change it to: + CPU: Freescale i.MX51 family rev3.0 at 800 MHz + + Signed-off-by: Fabio Estevam + +commit 68c07a0c215a64826ed13c2f9b00a6d3b298822e +Author: Stefano Babic +Date: Sun Apr 18 20:01:01 2010 +0200 + + MX51evk: Removed warnings + + Changes reflect modifications in the fsl_esdhc driver + (the clk_enable field war removed in the configuration structure). + + Signed-off-by: Stefano Babic + +commit 87db58dca47f93f9fb3b4ed0196dd7a3f5df1cb9 +Author: Anatolij Gustschin +Date: Wed Apr 21 13:52:38 2010 +0200 + + tx25: fix crash while booting Linux + + Currently booting Linux on TX25 board doesn't work + since there is no correct mach-id and boot parameters + setup for tx25 board. Fix it now. + + Signed-off-by: Anatolij Gustschin + Cc: John Rigby + Cc: Stefano Babic + +commit b88c5988db176a0f9de5598d5167ee2498637d40 +Author: Kim Phillips +Date: Tue Apr 13 21:11:53 2010 -0500 + + configs: remove unused CONFIG_COMMAND_HISTORY + + $ git grep CONFIG_COMMAND_HISTORY + CHANGELOG: CONFIG_COMMAND_HISTORY + include/configs/AP1000.h:#define CONFIG_COMMAND_HISTORY 1 + include/configs/keymile-common.h:#define CONFIG_COMMAND_HISTORY 1 + include/configs/manroland/common.h:#define CONFIG_COMMAND_HISTORY 1 + $ + + Signed-off-by: Kim Phillips + Acked-by: Heiko Schocher + +commit 7769c5bc06615293870d00fc81366cd43ba0623a +Author: Anatolij Gustschin +Date: Tue Apr 13 14:47:32 2010 +0200 + + mvsmr: fix link error + + MVSMR board support doesn't link since recent rework + of U-Boot directory structure. Fix it now. + + Signed-off-by: Anatolij Gustschin + Cc: Andre Schwarz + Acked-by: Andre Schwarz + Fixed merge conflict + Signed-off-by: Wolfgang Denk + +commit 4324dc72df5879e5b614c4a3f326884723ede9b7 +Author: Mike Frysinger +Date: Tue Apr 27 14:15:28 2010 -0400 + + Blackfin: bfin_mac: hook up new write_hwaddr function + + Signed-off-by: Mike Frysinger + Signed-off-by: Ben Warren + +commit 3ac9d6c650d94c51645efa446c1d914c5440990d +Author: Thomas Chou +Date: Tue Apr 27 20:20:27 2010 +0800 + + net: ethoc: add write_hwaddr support + + Signed-off-by: Thomas Chou + Signed-off-by: Ben Warren + +commit 6c7c444786fc4022999362fce119c8b731eedcb4 +Author: Thomas Chou +Date: Tue Apr 27 20:15:10 2010 +0800 + + net: altera_tse: add write_hwaddr support + + Signed-off-by: Thomas Chou + Signed-off-by: Ben Warren + +commit fb57ec97b90291c589087167f100483a089837bf +Author: Heiko Schocher +Date: Tue Apr 27 07:43:52 2010 +0200 + + net: fec_mxc: add write_hwaddr support + + tested on the magnesium board. + + Signed-off-by: Heiko Schocher + Signed-off-by: Ben Warren + +commit b5ce63ed12b4cd81d211621aca0c222b20d2a691 +Author: Prafulla Wadaskar +Date: Tue Apr 6 22:21:33 2010 +0530 + + net:kirkwood_egiga.c: MAC addresses programming using write_hwaddr + + Added a new function kwgbe_write_hwaddr for programming egiga + controller's hardware address. + This function will be called for each egiga port being used + + Signed-off-by: Prafulla Wadaskar + Signed-off-by: Ben Warren + +commit ecee9324d73555e744593f3e0d387bec4c566f55 +Author: Ben Warren +Date: Mon Apr 26 11:11:46 2010 -0700 + + Program net device MAC addresses after initializing + + Add a new function to the eth_device struct for programming a network + controller's hardware address. + + After all network devices have been initialized and the proper MAC address + for each has been determined, make a device driver call to program the + address into the device. Only device instances with valid unicast addresses + will be programmed. + + Signed-off-by: Ben Warren + Acked-by: Detlev Zundel + Tested-by: Prafulla Wadaskar + Tested-by: Heiko Schocher + Tested-by: Thomas Chou + +commit c960b13ed22d9ea570957379f9f7f2f37d87ef08 +Author: Thomas Chou +Date: Tue Apr 20 12:49:52 2010 +0800 + + net: add altera triple speeds ethernet mac driver + + This driver supports the Altera triple speeds 10/100/1000 ethernet + mac. + + Signed-off-by: Thomas Chou + Signed-off-by: Ben Warren + +commit f6569884b45e480e2c575d85ce86a2636a41c66b +Author: Thomas Chou +Date: Thu Apr 15 22:32:38 2010 +0800 + + net: add opencore 10/100 ethernet mac driver + + This patch ports the opencore 10/100 ethernet mac driver ethoc.c + from linux kernel to u-boot. + + Signed-off-by: Thomas Chou + Signed-off-by: Ben Warren + +commit bd75db3feb9a8e4123b76006dbe582b71adbf22f +Author: Valentin Yakovenkov +Date: Fri Apr 23 09:40:23 2010 +0400 + + smc911x driver frame alignment patch + + SMSC911x chips have alignment function to allow frame payload data + (which comes after 14-bytes ethernet header) to be aligned at some + boundary when reading it from fifo (usually - 4 bytes boundary). + This is done by inserting fake zeros bytes BEFORE actual frame data when + reading from SMSC's fifo. + This function controlled by RX_CFG register. There are bits that + represents amount of fake bytes to be inserted. + + Linux uses alignment of 4 bytes. Ethernet frame header is 14 bytes long, + so we need to add 2 fake bytes to get payload data aligned at 4-bytes + boundary. + Linux driver does this by adding IP_ALIGNMENT constant (defined at + skb.h) when calculating fifo data length. All network subsystem of Linux + uses this constant too when calculating different offsets. + + But u-boot does not use any packet data alignment, so we don't need to + add anything when calculating fifo data length. + Moreover, driver zeros the RX_CFG register just one line up, so chip + does not insert any fake data at the beginig. So calculated data length + is always bigger by 1 word. + + It seems that at almost every packet read we get an underflow condition + at fifo and possible corruption of data. Especially at continuous + transfers, such as tftp. + + Just after removing this magic addition, I've got tftp transfer speed as + it aught to be at 100Mbps. It was really slow before. + + It seems that fifo underflow occurs only when using byte packing on + 32-bit blackfin bus (may be because of very small delay between reads). + + Signed-off-by: Valentin Yakovenkov + Signed-off-by: Ben Warren + +commit f0588fdf921c63f84051923bb29eb4255d62a6e7 +Author: Prafulla Wadaskar +Date: Tue Apr 6 21:33:08 2010 +0530 + + net: Kirkwood_egiga.c bugfixes for rx path + + Cosmetic changes: Few comments updated + Functionality: Rx packet frame size is programming should + be done when port is in disabled state. this is corrected + + Signed-off-by: Prafulla Wadaskar + Signed-off-by: Ben Warren + +commit 2e236bf28e729aca28e60c153dd8f913d1b3d058 +Author: Eric Jarrige +Date: Fri Apr 16 00:03:19 2010 +0200 + + fec_mxc.c: Fix MX27 FEC MAC validity check + + Fix MX27 FEC logic to check validity of the MAC address in fuse. + Only null (empty fuse) or invalid MAC address was retrieved from mx27 fuses before this change. + + Signed-off-by: Eric Jarrige + Signed-off-by: Ben Warren + +commit 538be58568542aac2ed4bdf4c05398cfa67e98f0 +Author: Andy Fleming +Date: Mon Apr 19 14:54:49 2010 -0500 + + tsec: Wait for both RX and TX to stop + + When gracefully stopping the controller, the driver was continuing if + *either* RX or TX had stopped. We need to wait for both, or the + controller could get into an invalid state. + + Signed-off-by: Andy Fleming + Signed-off-by: Ben Warren + +commit a45dde2293c816138e53c26eca6fd0322583f9a6 +Author: Mike Frysinger +Date: Wed Apr 14 16:29:06 2010 -0400 + + net: dm9000x: use standard I/O accessors + + The current dm9000x driver accesses its memory mapped registers directly + instead of using the standard I/O accessors. This can cause problems on + Blackfin systems as the accesses can get out of order. So convert the + direct volatile dereferences to use the normal in/out macros. + + Signed-off-by: Mike Frysinger + Signed-off-by: Ben Warren + +commit 5525856d59910c72687ab6201f39cdf1c04cfc15 +Author: Detlev Zundel +Date: Thu Apr 8 11:49:59 2010 +0200 + + mpc512x_fec: Move PHY initialization from probe into init routine. + + This saves the autonegotation delay when not using ethernet in U-Boot + + Signed-off-by: Detlev Zundel + Signed-off-by: Ben Warren + +commit 910119b3c462fd6367536899ee43de1eb7d22d8e +Author: John Rigby +Date: Wed Apr 7 23:29:40 2010 -0600 + + fec_mxc don't use internal eeprom on MX25 + + Avoid using the internal eeprom on MX25 like MX51 already does. + + Signed-off-by: John Rigby + Signed-off-by: Ben Warren + +commit 33f684d6d512992ed1ae37ec46e76bdeb0773bac +Author: Wolfgang Wegner +Date: Tue Apr 6 11:13:02 2010 +0200 + + fix lockup in mcfmii/mii_discover_phy() in case communication fails + + Signed-off-by: Wolfgang Wegner + Signed-off-by: Ben Warren + +commit 23c34af48ff0dbff3bbaa8e94df3bf40350a709f +Author: Richard Retanubun +Date: Wed Jun 17 16:00:41 2009 -0400 + + 83xx: UEC: Added support for bitBang MII driver access to PHYs + + This patch enabled support for having PHYs on bitBang MII and uec MII + operating at the same time. Modeled after the MPC8360ADS implementation. + + Added the ability to specify which ethernet interfaces have bitbang SMI + on the board header file. + + Signed-off-by: Richard Retanubun + Signed-off-by: Ben Warren + +commit 9739946cc5b616c026d433bd07d193cf452ddea0 +Author: Robin Getz +Date: Mon Mar 8 14:07:00 2010 -0500 + + ./net/net.c - make Microsoft dns servers happy with random_port() numbers + + For some reason, (which I can't find any documentation on), if U-Boot + gives a port number higher than 17500 to a Microsoft DNS server, the + server will reply to port 17500, and U-Boot will ignore things (since + that isn't the port it asked the DNS server to reply to). + + This fixes that by ensuring the random port number is less than 17500. + + Signed-off-by: Robin Getz + Signed-off-by: Ben Warren + +commit 6f5f89f01195e2d009b317df27197a38fcab3553 +Author: Detlev Zundel +Date: Thu Apr 1 14:16:41 2010 +0200 + + Remove unused "local_crc32" function. + + For code archeologists, this is a nice example of copy and paste history. + + Signed-off-by: Detlev Zundel + Signed-off-by: Ben Warren + +commit aba4b69d01457ab2988e91c8592e5d2ffb10f569 +Author: Detlev Zundel +Date: Wed Mar 31 17:56:08 2010 +0200 + + net: Trivial coding style issue with empty for statement + + Signed-off-by: Detlev Zundel + Signed-off-by: Ben Warren + +commit e3f2a93362c823fc1feb5e8a40ff3c120716a05b +Author: Prafulla Wadaskar +Date: Wed Mar 3 15:27:21 2010 +0530 + + net: Kirkwood_egiga.c: fixed build warnings + + This patch fixes following build warnings for kirkwood_egiga.c + + kirkwood_egiga.c: In function "kwgbe_init": + kirkwood_egiga.c:448: warning: dereferencing type-punned pointer will break strict-aliasing rules + kirkwood_egiga.c: In function "kwgbe_recv": + kirkwood_egiga.c:609: warning: dereferencing type-punned pointer will break strict-aliasing rules + + Signed-off-by: Prafulla Wadaskar + Signed-off-by: Ben Warren + +commit 20d98c2cea3398ad93beccd4727a371f41514086 +Author: Asen Dimov +Date: Mon Apr 19 14:18:43 2010 +0300 + + pm9263 converted to at91 soc access + + Signed-off-by: Asen Dimov + +commit d6b91e30d32871eb20b6227519fd2f3a6ea073fd +Author: Asen Dimov +Date: Mon Apr 19 14:17:22 2010 +0300 + + at91: define matrix registers bit fields + + Signed-off-by: Asen Dimov + +commit eeb50ce193453951529015f50e5c1ccd7b55aad2 +Author: Stefano Babic +Date: Tue Apr 13 12:19:06 2010 +0200 + + MX31: Removed erroneous board name from QONG + + QONG is a module that can be installed on several boards, + not only on the QONG-EVB manufactured by Dave srl. + + Signed-off-by: Stefano Babic + +commit c9d944d35e7904229c5333e761bce9d4324971f8 +Author: Stefano Babic +Date: Thu Apr 8 17:23:52 2010 +0200 + + MX31: Add UBI support to QONG module + + The UBI/UBIFS support is added to the QONG module. + + Signed-off-by: Stefano Babic + +commit eab40f819ddd50eef465619db1386c053b59a95b +Author: Stefano Babic +Date: Wed Mar 31 10:27:47 2010 +0200 + + MX31: Support 128MB RAM on QONG module + + The QONG module can be downsized and delivered + with 128MB instead of 256MB. The patch adds + run time support for the two different memory + configurations. + + Signed-off-by: Stefano Babic + +commit 45997e0a86ee8d8abec6d791a241cb20011fe0e3 +Author: Stefano Babic +Date: Mon Mar 29 16:43:39 2010 +0200 + + MX31: Add support for NAND to QONG board + + The NAND device is connected to the FPGA of the QONG board + and not to the NFC controller. For this reason, the FPGA must + be set and initialized before accessing to the NAND itself. + + Signed-off-by: Stefano Babic + +commit efb9591069ee276f7fa27a821240c7511f72fe65 +Author: Stefano Babic +Date: Mon Mar 29 15:56:10 2010 +0200 + + MX31: add pin definitions for NAND controller + + Add pin definitions ralted to the NAND controller to be used + to set up the pin multiplexer. + + Signed-off-by: Stefano Babic + +commit 7d27cd08b4c1adfd58c54aaa8b8c8f4eeb3c7021 +Author: Stefano Babic +Date: Tue Apr 13 12:07:00 2010 +0200 + + MX31: add accessor function to get a gpio + + The patch adds an accessor function to get the value of a gpio. + + Signed-off-by: Stefano Babic + +commit dfe83352cb58c55dfdbd5b535cb335526cb1c581 +Author: Stefano Babic +Date: Tue Apr 13 12:38:43 2010 +0200 + + mx51evk: correct list of possible BOOT_FROM values + + Signed-off-by: Stefano Babic + +commit f581e3a2157fbd736e7dd2378465ae242fba545c +Author: Stefano Babic +Date: Tue Apr 13 12:38:22 2010 +0200 + + mkimage: correct spelling error in imximage + + Signed-off-by: Stefano Babic + +commit 34196b0a8bd7ab6d472e2e6f6c90b73e915a1fae +Author: John Rigby +Date: Wed Apr 7 23:30:09 2010 -0600 + + MX25 print arm clock instead of mpllclk on boot + + Replace call to imx_get_mpllclk with imx_get_armclk + to show frequency of ARM core instead of mpll internal + bus in print_cpuinfo. + + Signed-off-by: John Rigby + CC: Stefano Babic + +commit 1c9d91aca649f17762bae2c0e38f5101d62ed0b5 +Author: Frans Meulenbroeks <[fransmeulenbroeks@gmail.com]> +Date: Tue Apr 6 19:06:11 2010 +0530 + + configs/openrd_base.h: reordered macros + + moved CONFIG_CMD_FAT to filesystem section + swapped CONFIG_CMD_NAND and CONFIG_CMD_MII so they are alpha correct + + Signed-off-by: Frans Meulenbroeks + +commit 5414fec85ff558af8823d4391f03977288871fe4 +Author: Frans Meulenbroeks <[fransmeulenbroeks@gmail.com]> +Date: Tue Apr 6 18:26:19 2010 +0530 + + configs/sheevaplug: added a few additional commands + + This patch includes a few additional commands in the sheevaplug + version of u-boot: + - support for LONGHELP so you can get help messages + - auto completion and command editing + - ubi and mii support + - ext2 filesystem (convenient if you have an ext2 from which you want to boot) + - jffs2 and ubifs filesystems (if you want to use these in NAND) + + This also makes it more similar to openrd client. + + Side effect of this patch is that the code now needs 3 sectors i.s.o. 2 + so an existing env is overwritten + + Signed-off-by: Frans Meulenbroeks + +commit 16b76705d36ac137fa9231cedfe1355561639e47 +Author: Siddarth Gore <[gores@marvell.com]> +Date: Thu Mar 18 20:25:40 2010 +0530 + + Marvell GuruPlug Board Support + + GuruPlug Standard: 1 Gb Ethernet, 2 USB 2.0 + GuruPlug Plus: 2 Gb Ethernet, 2 USB 2.0, 1 eSATA, 1 uSD slot + + References: + http://www.globalscaletechnologies.com/t-guruplugdetails.aspx + http://plugcomputer.org + + This patch is for GuruPlug Plus, but it supports Standard version + as well. + + Signed-off-by: Siddarth Gore + +commit 5e1fe88fe3df2555a8a0cba7d2ffaf2b03041dfb +Author: Stefano Babic +Date: Sun Mar 28 13:43:26 2010 +0200 + + Moved board specific values in config file + + The lowlevel_init file contained some hard-coded values + to setup the RAM. These board related values are moved into + the board configuration file. + + Signed-off-by: Stefano Babic + +commit 272017853339f5b9685f9488bdaf5405812d12a4 +Author: Fabio Estevam +Date: Wed Mar 31 06:32:56 2010 -0700 + + MX51EVK: Remove CPLD related code + + There is no CPLD on MX51EVK board, so remove CPLD related function. + + Signed-off-by: Fabio Estevam + +commit bbe310922f4d0b12c8aba97b45ed979db9c0ec9a +Author: Heiko Schocher +Date: Fri Mar 5 07:36:33 2010 +0100 + + arm, i.mx27: add support for magnesium board from projectiondesign + + This patch adds support for the magnesium board from + projectiondesign. This board uses i.MX27 SoC and has + 8MB NOR flash, 128MB NAND flash, FEC ethernet controller + integrated into i.MX27. As this port is based on + the imx27lite port, common config options are collected + in include/configs/imx27lite-common.h + + Signed-off-by: Heiko Schocher + +commit 1e65c2beb5805f975cd5d0ab7d853040a716d51b +Author: Heiko Schocher +Date: Thu Mar 4 08:12:05 2010 +0100 + + arm, mx27: add support for SDHC1 pin init + + Signed-off-by: Heiko Schocher + +commit 3bb6b037e8557fd3c0f3b3d9840c8b5996651dcb +Author: Minkyu Kang +Date: Wed Mar 24 15:31:06 2010 +0900 + + SAMSUNG: make s5p common gpio functions + + Because of s5pc1xx gpio is same as s5p seires SoC, + move gpio functions to drvier/gpio/ + and modify structure's name from s5pc1xx_ to s5p_. + + Signed-off-by: Minkyu Kang + +commit 46a3b5c8df939f5547bcd3684030072c94d06bd8 +Author: Minkyu Kang +Date: Wed Mar 24 16:59:30 2010 +0900 + + SAMSUNG: serial: modify name from s5pc1xx to s5p + + Because of other s5p series SoC will use these serial functions, + modify function's name and structure's name. + + Signed-off-by: Minkyu Kang + +commit da0f2af279563ddc75eff304ad5389f7f0e79381 +Author: Asen Dimov +Date: Wed Apr 7 12:33:11 2010 +0300 + + pm9263: remove CONFIG_CMD_AUTOSCRIPT + + Signed-off-by: Asen Dimov + +commit 47eb08a97eb166e93d0495848b0c7582a0639fbc +Author: Alexander Holler +Date: Mon Mar 29 21:39:43 2010 +0200 + + at91: add defines for RTT and GPBR + + Signed-off-by: Alexander Holler + +commit dc8cab87459d682fc272444044592d20243da2f0 +Author: Asen Dimov +Date: Tue Apr 6 16:17:34 2010 +0300 + + pm9261: remove CONFIG_CMD_AUTOSCRIPT + + Signed-off-by: Asen Dimov + +commit e3150c77617c7d452420e6c87769b79b6671b12d +Author: Asen Dimov +Date: Tue Apr 6 16:18:04 2010 +0300 + + pm9261 converted to at91 soc access + + Signed-off-by: Asen Dimov + +commit 7bc8768039948e50cc149bea2ec214bde3245c4a +Author: trix +Date: Sat Apr 10 12:46:49 2010 -0500 + + ARM Update mach-types + + Fetched from http://www.arm.linux.org.uk/developer/machines/download.php + And built with + + repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm + commit 85b3cce880a19e78286570d5fd004cc3cac06f57 + + Signed-off-by: Tom Rix + +commit d3061c692155412aa87e7f4f66b4a2c7b77ee417 +Author: Stefan Roese +Date: Wed Apr 28 11:09:59 2010 +0200 + + ppc4xx: Fix APC405 build breakage + + This patch fixes APC405 build, by defining CONFIG_PPC4XX_I2C. This is + needed since the move of the PPC4xx I2C driver into the drivers/i2c + directory. + + Signed-off-by: Stefan Roese + Cc: Matthias Fuchs + +commit 029faf3e85e9406f32f133e6f2a114ed26b02fb4 +Author: Stefan Roese +Date: Tue Apr 27 11:37:28 2010 +0200 + + ppc4xx: Add support for ICON board (PPC440SPe) + + This patch adds support for the Mosaix Technologies, Inc. ICON board, + based on the AppliedMicro (AMCC) PPC440SPe. It's equipped with an SODIMM + (512MB standard) and 64MByte of NOR FLASH. + + Support for the onboard SM502 will be added later. + + Signed-off-by: Stefan Roese + +commit 96a0d6235db4c93c03d41c492f5960b18547b7a7 +Author: Stefan Roese +Date: Mon Apr 26 13:31:08 2010 +0200 + + ppc4xx: Add missing APC405 to MAKEALL + + Signed-off-by: Stefan Roese + Cc: Matthias Fuchs + +commit 64123e3f06f74dd09b86e2a41d77d31044f495fb +Author: Larry Johnson +Date: Tue Apr 20 08:11:40 2010 -0400 + + Fix typos in Korat board console output + + Signed-off-by: Larry Johnson + Signed-off-by: Stefan Roese + +commit 8a1cdaa9d54c93db300e8565191d60712aa481dc +Author: Wolfgang Denk +Date: Wed Apr 28 12:54:43 2010 +0200 + + QONG: Adapt flash addresses and mtdparts to grown image size + + Also enable HUSH shell. + + Signed-off-by: Wolfgang Denk + +commit e1d2950d0f5aaa7ab6609ffa96dde2e163fc2902 +Author: Wolfgang Denk +Date: Wed Apr 28 10:58:10 2010 +0200 + + mtdparts: get rid of custom DEBUG macro, use debug() + + Signed-off-by: Wolfgang Denk + +commit 2697eff1af136c6424c065cba994aa9aceadbcd1 +Author: Wolfgang Denk +Date: Wed Apr 28 10:53:47 2010 +0200 + + mtdparts: fix write through NULL pointer + + The "mtdparts add" command wrote through a NULL pointer - on many + systems this went unnoticed (PowerPC has writable RAM there, some ARM + systems have ROM where a write has no effect), but on arm1136 + (i.MX31) it crashed the system. + + Add appropriate checks. + + Signed-off-by: Wolfgang Denk + +commit 68651683593958cedcdfb9d06a5fe0a524f8dd6e +Author: Stefano Babic +Date: Wed Apr 21 09:47:19 2010 +0200 + + ubifsmount fails due to not initialized list + + ubifsmount is not working and causes an access with + a pointer set to zero because the ubifs_fs_type + is not initialized correctly. + + Signed-off-by: Stefano Babic + Signed-off-by: Stefan Roese + +commit 7c8cf0d0c7b12c7c63765e936cf760dc2c7d7306 +Author: Stefano Babic +Date: Wed Apr 21 09:56:31 2010 +0200 + + MX31: Added LCD support for QONG module + + Added support for LCD and splash image to the QONG module. + The supported display is VBEST-VGG322403. + + Signed-off-by: Stefano Babic + +commit 7e1afb62a7e68843248b9a76a265c9193e716768 +Author: Kumar Gala +Date: Tue Apr 20 10:02:24 2010 -0500 + + ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQ + + The MPC83xx SERDES control is different from the other FSL PPC chips. + For now lets split it out so we can standardize on interfaces for + determining of a device on SERDES is configured. + + Signed-off-by: Kumar Gala + Acked-by: Kim Phillips + +commit 3f0202ed13add5fd6e2ed66fcb3f5e1228cdf766 +Author: Lan Chunhe +Date: Wed Apr 21 07:40:50 2010 -0500 + + mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flash + + Signed-off-by: Lan Chunhe + Signed-off-by: Roy Zang + Signed-off-by: Kumar Gala + +commit 0c955dafab495fef5a76f5383387281d0408056c +Author: Dave Liu +Date: Wed Apr 14 19:05:06 2010 +0800 + + 85xx: clean up the io_sel for PCI express of P1022 + + clean up the wrong io_sel for PCI express according to latest manual. + + Signed-off-by: Dave Liu + Signed-off-by: Kumar Gala + +commit 47106ce168890d637fd849682ba88ecfdb9c35de +Author: Detlev Zundel +Date: Wed Apr 14 11:32:20 2010 +0200 + + 85xx/socrates: Remove NFS support to fit image size. + + This fixes an overflow during the link phase. + + Signed-off-by: Detlev Zundel + Signed-off-by: Kumar Gala + +commit 9ce3c228276b0f85105da8c39b164f2b6c84ea34 +Author: Kumar Gala +Date: Tue Apr 13 11:07:57 2010 -0500 + + 85xx: Fix compile warning + + cpu.c: In function 'checkcpu': + cpu.c:47: warning: unused variable 'gur' + + Signed-off-by: Kumar Gala + +commit 4db9708b94b6745f5c1eaa699d4d76477de8588a +Author: Kumar Gala +Date: Tue Apr 13 23:56:23 2010 -0500 + + 85xx: Convert cpu_init_f code to use out_be32 for LBC registers + + Signed-off-by: Kumar Gala + +commit cd3abcfa2d4dc8df09f6d01e735e4dc2f6c87ebc +Author: Dave Liu +Date: Mon Apr 12 14:23:35 2010 +0800 + + fsl_sata: Move the snoop bit to another place + + For P1022 SATA host controller, the data snoop bit of DW3 in PRDT + is moved to bit28. + + Signed-off-by: Dave Liu + Signed-off-by: Kumar Gala + +commit e4773debb735323a9eedf353239e8e88e03d7c58 +Author: Dave Liu +Date: Mon Apr 12 14:23:25 2010 +0800 + + fsl_sata: Add the workaround for errata SATA-A001 + + After power on, the SATA host controller of P1022 Rev1 is configured + in legacy mode instead of the expected enterprise mode. + + Software needs to clear bit[28] of HControl register to change to + enterprise mode after bringing the host offline. + + Signed-off-by: Dave Liu + Signed-off-by: Kumar Gala + +commit 99bac479dd183529f4e259a0de8d31644219d487 +Author: Dave Liu +Date: Tue Dec 8 11:56:48 2009 +0800 + + fsl-ddr: Add extra cycle to turnaround times + + Add an extra cycle turnaround time to read->write to ensure stability + at high DDR frequencies. + + Signed-off-by: Dave Liu + Signed-off-by: Kumar Gala + +commit f8d05e5e5888d88ab42524d699924936e8e77970 +Author: Dave Liu +Date: Fri Mar 5 12:23:00 2010 +0800 + + fsl-ddr: add the macro for Rtt_Nom definition + + add the macro definition for Rtt_Nom termination value for DDR3 + + Signed-off-by: Dave Liu + Signed-off-by: Kumar Gala + +commit 1231c498e016b5bfe85f1eb87c2e044d3389d7da +Author: Kumar Gala +Date: Wed Apr 7 10:39:46 2010 -0500 + + ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines + + Added some needed fines and some misc additional defines + used by p4080 initialization. + + Signed-off-by: Kumar Gala + +commit 17d90f31a810a19ade1a1c534fde9f65d4d66390 +Author: Dave Liu +Date: Fri Mar 5 12:23:00 2010 +0800 + + ppc/p4080: Extend the GUTS memory map + + Extend pin control and clock control to GUTS memory map + + Signed-off-by: Dave Liu + Signed-off-by: Kumar Gala + +commit ab48ca1a661b9ab8e3fee9fe2df65432b09ed073 +Author: Srikanth Srinivasan +Date: Wed Feb 10 17:32:43 2010 +0800 + + ppc/p4080: Fix synchronous frequency calculations + + When DDR is in synchronous mode, the existing code assigns sysclk + frequency to DDR frequency. It should be synchronous with the platform + frequency. CPU frequency is based on platform frequency in synchronous + mode. + + Also fix: + + * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) + * Corrects the detection of synchronous mode. + + Signed-off-by: Srikanth Srinivasan + Signed-off-by: Dave Liu + Signed-off-by: Ed Swarthout + Signed-off-by: Kumar Gala + +commit 1749c3da8d8445cdf78d70120a803e3e9553113c +Author: Kumar Gala +Date: Wed Apr 7 02:49:12 2010 -0500 + + ppc/85xx: Fixup PCI nodes for P1_P2_RDB + + While we had ft_pci_board_setup it wasn't being called by + ft_board_setup. Fix that so we actually update the device tree PCI + nodes on P1_P2_RDB boards. + + Signed-off-by: Kumar Gala + +commit 8cbb0ddd7e696c6a4be1ae3ab3c95d3c8f6a7031 +Author: Thomas Chou +Date: Wed Apr 21 08:40:59 2010 +0800 + + nios2: add nios2-generic board + + This is a generic approach to port u-boot for nios2 boards. + You may find the usage of this approach on the nioswiki, + http://nioswiki.com/DasUBoot + + A fpga parameter file, which contains base address information + and drivers declaration, is generated from Altera's hardware system + description sopc file using tools. + + The example fpga parameter file is compatible with EP1C20, EP1S10 + and EP1S40 boards. So these boards can be removed after this commit. + Though epcs controller is removed to cut the dependency of altera_spi + driver. + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit 441cac10d8a9438b144ab0ad46280780b58f638b +Author: Thomas Chou +Date: Thu Apr 22 17:27:16 2010 +0800 + + nios2: fix no flash, add nand and mmc init in board.c + + This patch fixes error when CONFIG_SYS_NO_FLASH. And adds + nand flash and mmc initialization, which should go before + env initialization. + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit fd2712d0b1d4c1624bef35b784ee64451ee5a017 +Author: Thomas Chou +Date: Tue Apr 20 11:01:11 2010 +0800 + + nios2: consolidate reset initialization + + Global interrupt should be disabled from the beginning. + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit 994852966d2e6cf98c1dbeea8ee62c233b305ffb +Author: Thomas Chou +Date: Wed Mar 31 08:30:08 2010 +0800 + + altera_jtag_uart: bypass when no jtag connection + + This patch adds an option to bypass output waiting when there + is no jtag connection. This allows the jtag uart work similar + to a serial uart, ie, boot even without connection. + + This option is enabled with CONFIG_ALTERA_JTAG_UART_BYPASS + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit 7e812f2e9cdac80f6287d4aee5deb434597c4f8b +Author: Thomas Chou +Date: Sat Apr 17 23:34:40 2010 +0800 + + nios2: add dma_alloc_coherent + + This function return cache-line aligned allocation which is mapped + to uncached io region. + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit 0dc1c7f692c15fe1745e3eeab918e98ee6126677 +Author: Thomas Chou +Date: Sat Apr 17 23:10:09 2010 +0800 + + nios2: add 64 bits swab support + + This patch adds 64 bits swab support. Most 32 bits processors use + this. We need 64 bits swab for UBI. + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit e4bf588609d8d9cefbc312a6c6b8bb309b194fd5 +Author: Thomas Chou +Date: Wed Mar 31 08:36:24 2010 +0800 + + nios2: add altera cf reset + + This patch toggles power to reset the cf card. + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit dd168ef5b82255401e46a27faae09e39c66967fe +Author: Thomas Chou +Date: Sat Apr 17 17:39:12 2010 +0800 + + nios2: allow link script overriding from boards + + This patch allow boards to override the default link script. + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit 29fd7ceb3c1cb7ffaffce1047e806d1e85e3ab4b +Author: Anatolij Gustschin +Date: Sat Apr 24 19:27:11 2010 +0200 + + mpc5121: pdm360ng: add coprocessor POST + + Adds coprocessor communication POST code + + Signed-off-by: Anatolij Gustschin + +commit 2ebdb9a9d7abcb17fdbfdc4bbb71b4ef538fc713 +Author: Anatolij Gustschin +Date: Sat Apr 24 19:27:10 2010 +0200 + + mpc5121: add common post_word_load/store code + + Add common post_word_load/post_word_store routines + for all mpc5121 boards. pdm360ng board POST support + added by subsequent patch needs them. + + Signed-off-by: Anatolij Gustschin + +commit a3921eefa1440d23f22751704cd7df999769f169 +Author: Anatolij Gustschin +Date: Sat Apr 24 19:27:09 2010 +0200 + + mpc5121: add support for PDM360NG board + + PDM360NG is a MPC5121E based board by ifm ecomatic gmbh. + + Signed-off-by: Michael Weiss + Signed-off-by: Detlev Zundel + Signed-off-by: Anatolij Gustschin + +commit b9947bbb08d0483be03004bdbce283b644471cb7 +Author: Anatolij Gustschin +Date: Sat Apr 24 19:27:08 2010 +0200 + + mpc5121: determine RAM size using get_ram_size() + + Configure CONFIG_SYS_MAX_RAM_SIZE address range in + DDR Local Access Window and determine the RAM size. + Fix DDR LAW afterwards using detected RAM size. + + Signed-off-by: Anatolij Gustschin + +commit 5d937e8b59f27d8c300a2e78c168a4c22ec6922a +Author: Anatolij Gustschin +Date: Sat Apr 24 19:27:07 2010 +0200 + + mpc512x: make MEM IO Control configuration a board config option + + Signed-off-by: Anatolij Gustschin + +commit 8e234e33bf60a850685c7e81ea92d383c643486b +Author: Anatolij Gustschin +Date: Sat Apr 24 19:27:06 2010 +0200 + + mpc5121: add PSC serial communication routines + + Signed-off-by: Anatolij Gustschin + +commit e3b28e67329de99a315d509920760dcbc565f8c6 +Author: Anatolij Gustschin +Date: Sat Apr 24 19:27:05 2010 +0200 + + mpc512x: add multi serial PSC support + + Extend mpc512x serial driver to support multiple PSC ports. + + Subsequent patches for PDM360NG board support make use of this + functionality by defining CONFIG_SERIAL_MULTI in the board config + file. Additionally the used PSC devices are specified by defining + e.g. CONFIG_SYS_PSC1, CONFIG_SYS_PSC4 and CONFIG_SYS_PSC6. + + Support for PSC devices other than 1, 3, 4 and 6 is not added + by this patch because these aren't used currently. In the future + it can be easily added using DECLARE_PSC_SERIAL_FUNCTIONS(N) and + INIT_PSC_SERIAL_STRUCTURE(N) macros in cpu/mpc512x/serial.c. + Additionally you have to add code for registering added + devices in serial_initialize() in common/serial.c. + + Signed-off-by: Anatolij Gustschin + +commit fbb0030e3894119c089256f16626edd166c7629c +Author: Anatolij Gustschin +Date: Sat Apr 24 19:27:04 2010 +0200 + + serial: struct serial_device: add uninit() entry for drivers + + Subsequent patch extends mpc512x serial driver to support + multiple PSC ports. The driver will provide an uninit() + function to stop the serial controller and to disable the + controller's clock. Adding uninit() entry to struct serial_device + allows disabling the serial controller after usage of + a stdio serial device. + + This patch adds uninit() entry to the struct serial_device + and fixes initialization of this structure in the code + accordingly. + + Signed-off-by: Anatolij Gustschin + +commit 77c1458d130d33704472db9c88d2310c8fc90f4c +Author: Dipen Dudhat +Date: Mon Oct 5 15:41:58 2009 +0530 + + ppc/85xx: PIO Support for FSL eSDHC Controller Driver + + On some Freescale SoC Internal DMA of eSDHC controller has bug. + So PIO Mode has been introduced to do data transfer using CPU. + + Signed-off-by: Dipen Dudhat + +commit 1a2e203b31d33fb720f2cf1033b241ad36ab405a +Author: Kim Phillips +Date: Tue Apr 20 19:37:54 2010 -0500 + + mpc83xx: turn on icache in core initialization to improve u-boot boot time + + before, MPC8349ITX boots u-boot in 4.3sec: + + column1 is elapsed time since first message + column2 is elapsed time since previous message + column3 is the message + 0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX + 0.000 0.000: + 0.000 0.000: Reset Status: + 0.000 0.000: + 0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz + 0.032 0.000: Board: Freescale MPC8349E-mITX + 0.032 0.000: UPMA: Configured for compact flash + 0.032 0.000: I2C: ready + 0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) + 1.516 1.456: FLASH: 16 MB + 2.641 1.125: PCI: Bus Dev VenId DevId Class Int + 2.652 0.011: 00 10 1095 3114 0180 00 + 2.652 0.000: PCI: Bus Dev VenId DevId Class Int + 2.652 0.000: In: serial + 2.652 0.000: Out: serial + 2.652 0.000: Err: serial + 2.682 0.030: Board revision: 1.0 (PCF8475A) + 3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic + 3.080 0.000: TSEC0, TSEC1 + 4.300 1.219: IDE: Bus 0: .** Timeout ** + + after, MPC8349ITX boots u-boot in 3.0sec: + + 0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX + 0.010 0.000: + 0.010 0.000: Reset Status: + 0.010 0.000: + 0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz + 0.017 0.000: Board: Freescale MPC8349E-mITX + 0.038 0.020: UPMA: Configured for compact flash + 0.038 0.000: I2C: ready + 0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) + 0.260 0.222: FLASH: 16 MB + 1.390 1.130: PCI: Bus Dev VenId DevId Class Int + 1.390 0.000: 00 10 1095 3114 0180 00 + 1.390 0.000: PCI: Bus Dev VenId DevId Class Int + 1.400 0.010: In: serial + 1.400 0.000: Out: serial + 1.400 0.000: Err: serial + 1.400 0.000: Board revision: 1.0 (PCF8475A) + 1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic + 1.832 0.000: TSEC0, TSEC1 + 3.038 1.205: IDE: Bus 0: .** Timeout ** + + also tested on these boards (albeit with a less accurate + boottime measurement method): + + seconds: before after + 8349MDS ~2.6 ~2.2 + 8360MDS ~2.8 ~2.6 + 8313RDB ~2.5 ~2.3 #nand boot + 837xRDB ~3.1 ~2.3 + + also tested on an 8323ERDB. + + v2: also remove the delayed icache enablement assumption in arch ppc's + board.c, and add a CONFIG_MPC83xx define in the ITX config file for + consistency (even though it was already being defined in 83xx' + config.mk). + + Signed-off-by: Kim Phillips + +commit a059e90e16e126e25da33ce23a37e2acce84284c +Author: Kim Phillips +Date: Thu Apr 15 17:36:05 2010 -0500 + + mpc83xx: enable command line autocompletion + + because it's convenient. + + Signed-off-by: Kim Phillips + +commit dfe812c744ee6dacae3b4d553694642668d9ac9d +Author: Kim Phillips +Date: Thu Apr 15 17:36:02 2010 -0500 + + mpc83xx: use "A" nomenclature only on mpc834x and mpc836x families + + marketing didn't extend their postpend-with-an-A naming strategy + on rev.2's and higher beyond the first two 83xx families. This + patch stops us from misreporting we're running e.g., on an MPC8313EA, + when such a name doesn't exist. + + Signed-off-by: Kim Phillips + +commit 27ef578df7b9c7862c36a31b819c652f8b0aeea0 +Author: Rini van Zetten +Date: Thu Apr 15 16:03:05 2010 +0200 + + mpc83xx: Use CONFIG_FSL_ESDHC to enable sdhc clk + + Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define + instead of a platform define. This will enable all the 83xx + platforms to use sdhc_clk based on CONFIG_FSL_ESDHC. It's + the same patch as commit 6b9ea08c5010eab5ad1056bc9bf033afb672d9cc + for the ppc/85xx. + + Signed-off-by: Rini + Signed-off-by: Kim Phillips + +commit a47a12becf66f02a56da91c161e2edb625e9f20c +Author: Stefan Roese +Date: Thu Apr 15 16:07:28 2010 +0200 + + Move arch/ppc to arch/powerpc + + As discussed on the list, move "arch/ppc" to "arch/powerpc" to + better match the Linux directory structure. + + Please note that this patch also changes the "ppc" target in + MAKEALL to "powerpc" to match this new infrastructure. But "ppc" + is kept as an alias for now, to not break compatibility with + scripts using this name. + + Signed-off-by: Stefan Roese + Acked-by: Wolfgang Denk + Acked-by: Detlev Zundel + Acked-by: Kim Phillips + Cc: Peter Tyser + Cc: Anatolij Gustschin + +commit cf6eb6da433179674571f9370566b1ec8989a41a +Author: Stefan Roese +Date: Wed Apr 14 13:57:18 2010 +0200 + + ppc4xx: TLB init file cleanup + + This patch adds new macros, with frequently used combinations of the + 4xx TLB access control and storage attibutes. Additionally the 4xx init.S + files are updated to make use of these new macros. Resulting in easier + to read TLB definitions. + + Additionally some init.S files are updated to use the mmu header for the + TLB defines, instead of defining their own macros. + + Signed-off-by: Stefan Roese + +commit 26a33504a55e4882520f2e9da96ba6c22badb353 +Author: Richard Retanubun +Date: Mon Apr 12 15:08:17 2010 -0400 + + fsl_i2c: Added a callpoint for i2c_board_late_init + + This patch adds a callpoint in i2c_init that allows board specific + i2c board initialization (typically for i2c bus reset) that is called + after i2c_init operations, allowing the i2c_board_late_init function + to use the pre-configured i2c bus speed and slave address. + +commit 254ab7bd464657600aba69d840406f9358f3e116 +Author: Scott McNutt +Date: Fri Apr 16 16:12:39 2010 -0400 + + nios2: Move individual board linker scripts to common script in cpu tree. + + Signed-off-by: Scott McNutt + +commit 8ff972c6e99938f1a033e5500dccc9a37ce3406f +Author: Michal Simek +Date: Fri Apr 16 12:56:33 2010 +0200 + + microblaze: Consolidate cache code + + Merge cpu and lib cache code. + Flush cache before disabling. + + Signed-off-by: Michal Simek + +commit 9b4d90569028604bc491ea419187c31e4467bdca +Author: Michal Simek +Date: Fri Apr 16 12:01:32 2010 +0200 + + microblaze: Flush cache before jumping to kernel + + There is used max cache size on system which doesn't define + cache size. + + Signed-off-by: Michal Simek + +commit 70524883b0424277e5b3ff3768c0c5628b5fce44 +Author: Michal Simek +Date: Fri Apr 16 11:59:29 2010 +0200 + + microblaze: Support system with WB cache + + WB cache use different instruction that WT cache but the major code + is that same. That means that wdc.flush on system with WT cache + do the same thing as before. + + You need newer toolchain with wdc.flush support. + + Signed-off-by: Michal Simek + +commit 9769b73f60fc0fb8de7ab16ff6300eae56505020 +Author: Michal Simek +Date: Fri Apr 16 11:57:35 2010 +0200 + + microblaze: Change initialization sequence + + env_relocation should be called first. + Added stdio_init too. + + Signed-off-by: Michal Simek + +commit e6177b36b87d0ce627651e407b91245f16e5382e +Author: Michal Simek +Date: Fri Apr 16 11:55:01 2010 +0200 + + microblaze: Change cache report messages + + It is more accurate to show that caches are OFF instead of FAIL. + + Signed-off-by: Michal Simek + +commit 8125c980cc282000cbddb415f8ddbebf96e4edb4 +Author: Michal Simek +Date: Fri Apr 16 11:51:59 2010 +0200 + + microblaze: Fix interrupt handler code + + It is better to read ivr and react on it than do long parsing from + two regs. Interrupt controller returs actual irq number. + + Signed-off-by: Michal Simek + +commit b26640971a7ba8800f0eb32af145ff0727fe21fe +Author: Michal Simek +Date: Fri Apr 16 11:43:43 2010 +0200 + + microblaze: Move FSL initialization to board.c + + Move FSL out of interrupt controller. + + Signed-off-by: Michal Simek + +commit 5bbcb6cf22b1121d8c3e56b0e1fb84366e903ac7 +Author: Michal Simek +Date: Fri Apr 16 11:37:41 2010 +0200 + + microblaze: Move timer initialization to board.c + + I would like to handle case where system doesn't contain + intc that's why I need timer initialization out of intc code. + + Signed-off-by: Michal Simek + +commit cc53690e05f47b4c25e0a528de50e024fc0164ad +Author: Michal Simek +Date: Fri Apr 16 11:30:16 2010 +0200 + + microblaze: Fix irq.S code + + It is ancient code. There is possible to save several instructions + just if we use offset instead of addik + + Signed-off-by: Michal Simek + +commit 398b1d57a6a56aada1f77198746a7dd1b038cd5d +Author: Arun Bhanu +Date: Thu Apr 15 18:27:17 2010 +0800 + + microblaze: Add FDT support + + This patch adds FDT (flattened device tree) support to microblaze arch. + + Tested with Linux arch/microblaze kernels with and without compiled in + FDT on Xilinx ML506 board. + + Signed-off-by: Arun Bhanu + Signed-off-by: Michal Simek + +commit 2a72e9ed18d2164eb7fe569119342eb631b568da +Author: Stefan Roese +Date: Fri Apr 9 14:03:59 2010 +0200 + + ppc4xx: Add option for PPC440SPe ports without old Rev. A support + + The 440SPe Rev. A is quite old and newer 440SPe boards don't need support + for this CPU revision. Since removing support for this older version + simplifies the creation for newer U-Boot ports, this patch now enables + 440SPe > Rev. A support by creating the CONFIG_440SPE_REVA define. By + defining this in the board config header, Rev. A will still be supported. + Otherwise (default for newer board ports), Rev. A will not be supported. + + Signed-off-by: Stefan Roese + +commit 288991c93fdd150ef3817e676c657cb487468d38 +Author: Stefan Roese +Date: Thu Apr 8 09:33:13 2010 +0200 + + ppc4xx: alpr: Remove some not needed commands to make image fit again + + The latest changes increased the size of the alpr image a bit more. + Now it doesn't fit into the 256k reserved for it. This patch now removes + the commands "loads" and "loadb" which are not needed in the production + systems. + + Signed-off-by: Stefan Roese + Cc: Pieter Voorthuijsen + +commit 8d321b81c5441db93425ee37cb79cc51d9ce2fb0 +Author: Peter Tyser +Date: Mon Apr 12 22:28:21 2010 -0500 + + Update README to reflect new directory structure + + Also fix up some whitespace issues that were introduced when moving + directory locations. + + Signed-off-by: Peter Tyser + +commit 37e4dafaae96ccc970a896f90186fadcf858aad0 +Author: Peter Tyser +Date: Mon Apr 12 22:28:20 2010 -0500 + + nios2: Move cpu/nios2/* to arch/nios2/cpu/* + + Signed-off-by: Peter Tyser + +commit 6a8a2b7058a398fe207021259cb2c529fb225eff +Author: Peter Tyser +Date: Mon Apr 12 22:28:19 2010 -0500 + + nios: Move cpu/nios/* to arch/nios/cpu/* + + Signed-off-by: Peter Tyser + +commit 1e9c26578ebbeecbaf3d8fb574957405eff17c86 +Author: Peter Tyser +Date: Mon Apr 12 22:28:18 2010 -0500 + + sparc: Move cpu/leon[23] to arch/sparc/cpu/leon[23] + + Signed-off-by: Peter Tyser + +commit e9a882803eb59f482ca4aa6ffd6fa21e4c53d618 +Author: Peter Tyser +Date: Mon Apr 12 22:28:17 2010 -0500 + + i386: Move cpu/i386/* to arch/i386/cpu/* + + Signed-off-by: Peter Tyser + +commit 6260fb0458d94c83aa5b180745b1946c0c94d364 +Author: Peter Tyser +Date: Mon Apr 12 22:28:16 2010 -0500 + + microblaze: Move cpu/microblaze/* to arch/microblaze/cpu/* + + Signed-off-by: Peter Tyser + +commit 8a15c2d10b0b784f0cfba1240f06a4d933b975fa +Author: Peter Tyser +Date: Mon Apr 12 22:28:15 2010 -0500 + + avr32: Move cpu/at32ap/* to arch/avr32/cpu/* + + Signed-off-by: Peter Tyser + +commit 1e3827d9cf9442e188604fd1099ac38375135125 +Author: Peter Tyser +Date: Mon Apr 12 22:28:14 2010 -0500 + + mips: Move cpu/mips/* to arch/mips/cpu/* + + Signed-off-by: Peter Tyser + +commit c6fb83d21729321426308c3acff2a3dfb20d250b +Author: Peter Tyser +Date: Mon Apr 12 22:28:13 2010 -0500 + + blackfin: Move cpu/blackfin/* to arch/blackfin/cpu/* + + Signed-off-by: Peter Tyser + +commit a4145534851bf74619cb373a942613a74547bb82 +Author: Peter Tyser +Date: Mon Apr 12 22:28:12 2010 -0500 + + m68k: Move cpu/$CPU to arch/m68k/cpu/$CPU + + Signed-off-by: Peter Tyser + +commit 84ad688473bec2875e171b71040eb9e033c6c206 +Author: Peter Tyser +Date: Mon Apr 12 22:28:11 2010 -0500 + + arm: Move cpu/$CPU to arch/arm/cpu/$CPU + + Signed-off-by: Peter Tyser + +commit 8f0fec74ac6d0f3a7134ccebafa1ed9bd8c712ba +Author: Peter Tyser +Date: Mon Apr 12 22:28:10 2010 -0500 + + sh: Move cpu/$CPU to arch/sh/cpu/$CPU + + Signed-off-by: Peter Tyser + +commit 8d1f268204b07e172f3cb5cee0a3974d605b0b98 +Author: Peter Tyser +Date: Mon Apr 12 22:28:09 2010 -0500 + + ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU + + Signed-off-by: Peter Tyser + +commit 819833af39a91fa1c1e8252862bbda6f5a602f7b +Author: Peter Tyser +Date: Mon Apr 12 22:28:08 2010 -0500 + + Move architecture-specific includes to arch/$ARCH/include/asm + + This helps to clean up the include/ directory so that it only contains + non-architecture-specific headers and also matches Linux's directory + layout which many U-Boot developers are already familiar with. + + Signed-off-by: Peter Tyser + +commit 61f2b38a17f5b21c59f2afe6cf1cbb5f28638cf9 +Author: Peter Tyser +Date: Mon Apr 12 22:28:07 2010 -0500 + + Replace "#include " with "#include " + + The appropriate include/asm-$ARCH directory should already by symlinked + to include/asm so using the whole "asm-$ARCH" path is unnecessary. + + This change should also allow us to move the include/asm-$ARCH + directories into their appropriate lib/$ARCH/ directories. + + Signed-off-by: Peter Tyser + +commit 0de71d507157c4bd4fddcd3a419140d2b986eed2 +Author: Peter Tyser +Date: Mon Apr 12 22:28:06 2010 -0500 + + Move libfdt/ into lib/ + + Move the libfdt directory into the common lib/ directory to clean up the + top-level directory. + + Signed-off-by: Peter Tyser + +commit 78acc472d9719316f22e002a009a998d9ceec29d +Author: Peter Tyser +Date: Mon Apr 12 22:28:05 2010 -0500 + + Rename lib_generic/ to lib/ + + Now that the other architecture-specific lib directories have been + moved out of the top-level directory there's not much reason to have the + '_generic' suffix on the common lib directory. + + Signed-off-by: Peter Tyser + +commit ea0364f1bbfed1e3ea711147420875cf338fe77a +Author: Peter Tyser +Date: Mon Apr 12 22:28:04 2010 -0500 + + Move lib_$ARCH directories to arch/$ARCH/lib + + Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk + + This change is intended to clean up the top-level directory structure + and more closely mimic Linux's directory organization. + + Signed-off-by: Peter Tyser + +commit 89f39e177e7b0152aa1d3152baa25d986e36cdcf +Author: Peter Tyser +Date: Mon Apr 12 22:28:03 2010 -0500 + + Change directory-specific CFLAGS to use full path + + Previously, a specific file or directory could be compiled with custom + CFLAGS by adding a Makefile variable such as: + CFLAGS_dlmalloc.o = + or + CFLAGS_lib = + + This method breaks down once multiple files or directories share the + same path. Eg FLAGS_fileA = would incorrectly result in + both dir1/fileA.c and dir2/fileA.c being compiled with . + + This change allows finer grained control which we need once we move + lib_$ARCH to arch/$ARCH/lib/ and lib_generic/ to lib/. Without this + change all lib/ directories would share the same custom CFLAGS. + + Signed-off-by: Peter Tyser + +commit 03b7004ddafc70d83904d790abaa50843868130e +Author: Peter Tyser +Date: Mon Apr 12 22:28:02 2010 -0500 + + Create CPUDIR variable + + The CPUDIR variable points to the location of a target's CPU directory. + Currently, it is set to cpu/$CPU. However, using $CPUDIR will allow for + more flexibility in the future. It lays the groundwork for reorganizing + U-Boot's directory structure to support a layout such as: + + arch/$ARCH/cpu/$CPU/* (architecture with multiple CPU types) + arch/$ARCH/cpu/* (architecture with one CPU type) + + Signed-off-by: Peter Tyser + +commit 30dc165a76b5165af77219189bc05d0fa4229d8b +Author: Jens Scharsig +Date: Fri Apr 9 19:02:38 2010 +0200 + + FIX: watchdog timeout, while waiting for input + + * add WATCHDOG_RESET to !tstc() loops + * prevents watchdog timeout, while waiting for input, + if CONFIG_BOOT_RETRY_TIME or CONFIG_SHOW_ACTIVITY defined + + Signed-off-by: Jens Scharsig + +commit 8178110bc28249f3ff1c22b15d7dcdee50be69eb +Author: Detlev Zundel +Date: Thu Apr 8 17:55:48 2010 +0200 + + config_cmd_all.h: Sort entries alphabetically + + Signed-off-by: Detlev Zundel + +commit 9157e9c40ab3a942bdd0679bb433cd9ed485f434 +Author: Frans Meulenbroeks +Date: Thu Apr 8 17:55:47 2010 +0200 + + config_cmd_all.h: added missing CONFIG_CMD_UBI and CONFIG_CMD_UBIFS + + Signed-off-by: Frans Meulenbroeks + +commit ae30b8c200dc071d719ad649d0bf5635d61754f3 +Author: karl.beldan@gmail.com +Date: Tue Apr 6 22:18:08 2010 +0200 + + malloc: sbrk() should return MORECORE_FAILURE instead of NULL on failure + + Signed-off-by: Karl Beldan + +commit a2513e27e8df2b7bf481d03e7719f91ce19e89d5 +Author: Peter Tyser +Date: Sun Apr 4 22:36:03 2010 -0500 + + mkimage: Fix strict-aliasing compiler warning + + Version 4.2.4 of gcc produces the following warnings without this change: + mkimage.c: In function ‘main’: + mkimage.c:204: warning: dereferencing type-punned pointer will break strict-aliasing rules + mkimage.c:222: warning: dereferencing type-punned pointer will break strict-aliasing rules + + Signed-off-by: Peter Tyser + +commit 1f2463d7642c582339c9f9d96471d5d2a169b9bb +Author: Andre Schwarz +Date: Thu Apr 1 21:26:55 2010 +0200 + + Add initial support for Matrix Vision mvSMR board based on MPC5200B. + + Signed-off-by: Andre Schwarz + +commit 9acd4f0e914913796e4e56f550726d216f7b16e5 +Author: Frans Meulenbroeks +Date: Sat Mar 27 11:16:10 2010 +0100 + + cmd_bmp.c: add standard subcommand handling + + Signed-off-by: Frans Meulenbroeks + Acked-by: Detlev Zundel + +commit f852a0c3bfe0b30b4816135b9a0d2aaae7e5de6a +Author: Albin Tonnerre +Date: Sun Mar 14 18:47:23 2010 +0100 + + drivers/mtd/spi/eeprom_m95xxx.c: add missing error checking + + Signed-off-by: Albin Tonnerre + +commit 3b653fdb322028b27c5ae3d60ecb0eea2d58837f +Author: Peter Tyser +Date: Sun Apr 4 22:40:50 2010 -0500 + + cmd_ubi: Fix uninitialized variable warning + + gcc 3.4.6 previously reported the following error on many MIPS boards + which utilize UBI: + cmd_ubi.c:193: warning: 'vol' might be used uninitialized in this function + + The current code is structured such that 'vol' will never be used when + it is NULL anyway, but gcc isn't smart enough to figure this out. + + Signed-off-by: Peter Tyser + Signed-off-by: Stefan Roese + +commit fac71cc49f93db7d460dbc957dfbbadefa2ca0e9 +Author: Kim B. Heino +Date: Fri Mar 12 10:07:00 2010 +0200 + + USB storage probe + + While debugging one ill behaving USB device I found two bugs in USB + storage probe. + + usb_stor_get_info() returns -1 (error), 0 (skip) or 1 (ok). First part + of this patch fixes error case. + + Second part fixes usb_inquiry()'s retry counter handling. Original code + had retry = -1 on error case, not retry = 0 as checked in the next line. + + Signed-off-by: Kim B. Heino + +commit aaad108b889c6980a2d05262a2f7febb14f94d68 +Author: Kim B. Heino +Date: Fri Mar 12 15:46:56 2010 +0200 + + USB storage count + + Here's another USB storage patch. Currently U-Boot handles storage + devices #0 - #4 as valid devices, even if there is none connected. This + patch fixes usb_stor_get_dev() to check detected device count instead + of MAX-define. + + This is very important for ill behaving devices. usb_dev_desc[] can be + partially initialized if device probe fails. + + After fixing get_dev() it was easy to fix "usb part" etc commands. + Previously it outputed "Unknown partition table" five times, now it's + "no USB devices available". + + Signed-off-by: Kim B. Heino + +commit d7a22a364ceea97133c1fb7aff073953c7a61228 +Author: Sergei Shtylyov +Date: Sat Feb 27 21:34:41 2010 +0300 + + EHCI: add NEC PCI ID + + Add NEC EHCI controller to the list of the supported devices. + + Signed-off-by: Sergei Shtylyov + + drivers/usb/host/ehci-pci.c | 1 + + 1 file changed, 1 insertion(+) + +commit c8b2d1dc0f1667029f42c3fa21f70906414af325 +Author: Sergei Shtylyov +Date: Sat Feb 27 21:33:21 2010 +0300 + + EHCI: fix port reset reporting + + Commit b416191a14770c6bcc6fd67be7decf8159b2baee (Fix EHCI port reset.) didn't + move the code that checked for successful clearing of the port reset bit from + ehci_submit_root(), relying on wait_ms() call instead. The mentioned code also + erroneously reported port reset state when the reset was already completed. + + Signed-off-by: Sergei Shtylyov + +commit e06a055bcd966adf62a5653c84db781915392e41 +Author: Sergei Shtylyov +Date: Sat Feb 27 21:32:17 2010 +0300 + + EHCI: fix off-by-one error in ehci_submit_root() + + USB devices on the 2nd port are not detected and I get the following message: + + The request port(1) is not configured + + That's with default CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS value of 2. 'req->index' + is 1-based, so the comparison in ehci_submit_root() can't be correct. + + Signed-off-by: Sergei Shtylyov + +commit 6d313c84ded168427240e62d108b6ba9afdcf535 +Author: Sergei Shtylyov +Date: Sat Feb 27 21:29:42 2010 +0300 + + EHCI: fix root hub device descriptor + + On little endian machines, EHCI root hub's USB revision is reported as 0.2 -- + cpu_to_le16() was missed in the initializer for the 'bcdUSB' descriptor field. + The same should be done for the 'bcdDevice' field. + + Signed-off-by: Sergei Shtylyov + +commit 760bce07f182f678d42f2a85a0e47b59e831ba25 +Author: Anatolij Gustschin +Date: Thu Apr 8 15:50:55 2010 +0200 + + video: ati_radeon_fb.c: fix warning while compiling with DEBUG + + Fixes this warning: + + ati_radeon_fb.c: In function 'radeon_probe': + ati_radeon_fb.c:598: warning: format '%x' expects type 'unsigned int', + but argument 2 has type 'void *' + + Signed-off-by: Anatolij Gustschin + +commit f6a7a2e88854666e6a9ede50891fe415e803ace2 +Author: Ed Swarthout +Date: Wed Mar 31 15:52:40 2010 -0500 + + ati_radeon: Support PCI virtual not eq bus mapping. + + Use pci_bus_to_virt() to convert the bus address from the BARs to + virtual address' to eliminate the direct mapping requirement. + + Rename variables to better match usage (_phys -> _bus or no-suffix) + + This fixes the mpc8572ds CONFIG_PHYS_64BIT mode failure: + "videoboot: Video ROM failed to map!" + + Tested on mpc8572ds with and without CONFIG_PHYS_64BIT. + + Signed-off-by: Ed Swarthout + +commit 9624f6d9eb4b7223e97a27844ec4489ab953a2e2 +Author: Ed Swarthout +Date: Wed Mar 31 09:54:28 2010 -0500 + + ati_radeon: return with error when emulator fails + + Console was being switched to video even if emulator fails and + causing this hang: + + Scanning PCI bus 04 + 04 00 1095 3132 0104 00 + PCIE3 on bus 03 - 04 + Video: ATI Radeon video card (1002, 5b60) found @(2:0:0) + videoboot: Booting PCI video card bus 2, function 0, device 0 + videoboot: Video ROM failed to map! + 640x480x8 31kHz 59Hz + radeonfb: FIFO Timeout ! + + Signed-off-by: Ed Swarthout + Tested-by: Anatolij Gustschin + +commit d5011762f53ada9cc7cdf1f89f3a722f887af577 +Author: Anatolij Gustschin +Date: Mon Mar 15 14:50:25 2010 +0100 + + video: cfb_console.c: add support for RLE8 bitmaps + + Allow displaying 8-bit RLE BMP images. + + Signed-off-by: Anatolij Gustschin + +commit 22d6c8faac4e9fa43232b0cf4da427ec14d72ad3 +Author: Thomas Chou +Date: Thu Apr 1 11:15:05 2010 +0800 + + cfi_flash: reset timer in flash status check + + This patch adds reset_timer() before the flash status check + waiting loop. + + Since the timer is basically running asynchronous to the cfi + code, it is possible to call get_timer(0), then only a few + _SYSCLK_ cycles later an interrupt is generated. This causes + timeout even though much less time has elapsed. So the timer + period registers should be reset before get_timer(0) is + called. + + There is similar usage in nand_base.c. + + Signed-off-by: Thomas Chou + Signed-off-by: Stefan Roese + +commit 933419096e857275b8b01f1ae577162231b143ff +Author: Kumar Gala +Date: Wed Apr 7 01:34:11 2010 -0500 + + ppc/85xx: Use CONFIG_NS16550_MIN_FUNCTIONS to reduce NAND_SPL size + + The MPC8536DS_NAND SPL build was failing due to code size increase + introduced by commit: + + commit 33f57bd553edf29dffef5a6c7d76e169c79a6049 + Author: Kumar Gala + Date: Fri Mar 26 15:14:43 2010 -0500 + + 85xx: Fix enabling of L1 cache parity on secondary cores + + We built in some NS16550 functions that we dont need and can get + rid of them via CONFIG_NS16550_MIN_FUNCTIONS. + + Signed-off-by: Kumar Gala + +commit 5a4696088376fff82629e7e4a2444294dc589c96 +Author: Timur Tabi +Date: Thu Apr 1 10:49:42 2010 -0500 + + p2020ds: add alternate boot bank support using the ngPIXIS FPGA + + The Freescale P2020DS board uses a new type of PIXIS FPGA, called the ngPIXIS. + The ngPIXIS has one distinct new feature: the values of the on-board switches + can be selectively overridden with shadow registers. This feature is used to + boot from a different NOR flash bank, instead of having a register dedicated + for this purpose. Because the ngPIXIS is so different from the previous PIXIS, + a new file is introduced: ngpixis.c. + + Also update the P2020DS checkboard() function to use the new macros defined + in the header file. + + Signed-off-by: Timur Tabi + Signed-off-by: Kumar Gala + +commit 2feb4af001a0be5ccad6e6a6eb072207cbef6e3f +Author: Timur Tabi +Date: Wed Mar 31 17:44:13 2010 -0500 + + fsl: improve the PIXIS code and fix a few bugs + + Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx + boards. This makes the code easier to read and more flexible. + + Delete pixis.h, because none of the exported functions were actually being + used by any other file. Make all of the functions in pixis.c 'static'. + Remove "#include pixis.h" from every file that has it. + + Remove some unnecessary #includes. + + Make 'pixis_base' into a macro, so that we don't need to define it in every + function. + + Add "while(1);" loops at the end of functions that reset the board, so that + execution doesn't continue while the reset is in progress. + + Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where + appropriate. + + Replace ulong/uint with their spelled-out equivalents. Remove unnecessary + typecasts, changing the types of some variables if necessary. + + Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make + it easier for specific boards to support variations in the PIXIS registers + sets. No current boards appears to need this feature. + + Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD. + Apparently, "pixis_reset altbank" has never worked on this board. + + Signed-off-by: Timur Tabi + Signed-off-by: Kumar Gala + +commit ff8473e90a018c2bb19a196176c1f2e9602d6354 +Author: Sandeep Gopalpet +Date: Fri Mar 12 10:45:02 2010 +0530 + + 85xx: Set HID1[mbdd] on e500v2 rev5.0 or greater + + The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize + the performance of mbar/eieio instructions. + + Signed-off-by: Sandeep Gopalpet + +commit 216082754f6da5359ea0db9b0cc03ad531ac6e45 +Author: Kumar Gala +Date: Tue Mar 30 23:06:53 2010 -0500 + + 85xx: Added various P1012/P1013/P1021/P1022 defines + + There are various locations that we have chip specific info: + + * Makefile for which ddr code to build + * Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list + * Added number of LAWs for P1012/P1013/P1021/P1022 + * Set CONFIG_MAX_CPUS to 2 for P1021/P1022 + * PCI port config + + Signed-off-by: Haiying Wang + Signed-off-by: Srikanth Srinivasan + Signed-off-by: Kumar Gala + +commit 5a85a3096940b0a0cd016c8acf4944421c64f8c7 +Author: Kumar Gala +Date: Tue Mar 30 10:07:12 2010 -0500 + + ppc/8xxx: Delete PCI nodes from device tree if not configured + + If the PCI controller wasn't configured or enabled delete from the + device tree (include its alias). + + For the case that we didn't even configure u-boot with knowledge of + the controller we can use the fact that the pci_controller pointer + is NULL to delete the node in the device tree. We determine that + a controller was not setup (because of HW config) based on the fact + that cfg_addr wasn't setup. + + Signed-off-by: Kumar Gala + +commit 3f1a5c1655d32b7ab8ae74c79934ce100ebcd2bf +Author: Brent Kandetzki +Date: Wed Mar 24 17:41:33 2010 -0400 + + Blackfin: IP04: new board port + + A low cost 4 port IP-PBX board. + + Signed-off-by: Brent Kandetzki + Signed-off-by: Mike Frysinger + +commit a3c08363b927b84dee911bfcb29ab45d53c98f62 +Author: Mike Frysinger +Date: Tue Mar 23 16:23:39 2010 -0400 + + Blackfin: drop bfin #undef in linker script + + Now that the linker script is preprocessed with -ansi, there is no need to + manually undef the bfin define. + + Signed-off-by: Mike Frysinger + +commit 0c080aa753eb92e1c0033d3fd33033b2b4813884 +Author: Mike Frysinger +Date: Thu Feb 11 20:19:10 2010 -0500 + + Blackfin: call watchdog_init() for external watchdogs + + Signed-off-by: Mike Frysinger + +commit b874ed17472de492cfbf58c8e362364bc80e3dcd +Author: Mike Frysinger +Date: Wed Feb 10 01:20:44 2010 -0500 + + Blackfin: link with normal ABI target + + If someone uses the FDPIC toolchain to compile U-Boot, make sure the + linker knows to use the normal ABI target rather than the FDPIC one. + This wasn't needed with older toolchains, but when we fixed the linker + such that the default target changed based on tuple, this broke. + + Signed-off-by: Mike Frysinger + +commit dd97022cbeaae5fd4bce25cf7e86019101a040ef +Author: Mike Frysinger +Date: Fri Jan 29 15:48:28 2010 -0500 + + Blackfin: sync ptrace headers with linux + + Scrub a lot of dead cruft in the process. + + Signed-off-by: Mike Frysinger + +commit 6a0be8f8fe6d72a30e69d08decb72dc3bec5484c +Author: Harald Krapfenbauer +Date: Fri Jan 22 17:15:55 2010 -0500 + + Blackfin: cm-bf561: update network/env settings + + Switch to the SMC911X driver by default now, and fix LDR env settings. + + Signed-off-by: Harald Krapfenbauer + Signed-off-by: Mike Frysinger + +commit 216818c1a2d03b1c0994f00993c99af38c5b1e83 +Author: Mike Frysinger +Date: Thu Jan 21 23:29:18 2010 -0500 + + Blackfin: bf537-stamp: add board test defines + + We tweak the configs a little when doing automated hardware tests. + + Signed-off-by: Mike Frysinger + +commit 38b9b7446ecd3a728bad3e1913a984628a7363fb +Author: Mike Frysinger +Date: Tue Jan 19 21:02:00 2010 -0500 + + Blackfin: relax .data alignment + + The strictest alignment on Blackfin systems is 32bits (since that is the + largest load instruction), so don't force 256byte alignment here. + + Signed-off-by: Mike Frysinger + +commit 03f7053f70bc55b50c9d23e54f90d772419300a6 +Author: Mike Frysinger +Date: Tue Jan 19 15:39:07 2010 -0500 + + Blackfin: drop reference to gd->reloc_off + + The reloc_off member no longer exists, so drop it. Also change this + function so that it is always compiled and prevents latent issues like + this in the future. + + Reported-by: Peter Meerwald + Signed-off-by: Mike Frysinger + +commit 49b97d9c8ea7b11c4fc9e457cc2cd9fd6ebf0c21 +Author: Kumar Gala +Date: Tue Mar 30 10:19:26 2010 -0500 + + fdt: Add fdt_del_node_and_alias helper + + Add a helper function that given an alias will delete both the node + the alias points to and the alias itself + + Signed-off-by: Kumar Gala + Acked-by: Gerald Van Baren + +commit 459c41a8e1be96edeba1c0afeccacafd93b2c4e6 +Author: Mike Frysinger +Date: Tue Nov 3 15:53:12 2009 -0500 + + Blackfin: disable NetBSD bootm support by default + + There is no Blackfin/NetBSD port, so enabling support for it by default + doesn't make any sense. + + Signed-off-by: Mike Frysinger + +commit 69bcf5bc80a47acbd62b8cfff932cb12d47997d7 +Author: Kumar Gala +Date: Mon Mar 29 13:50:31 2010 -0500 + + 85xx: Add defines for BUCSR bits to make code more readable + + Signed-off-by: Kumar Gala + +commit 22c9de064a218ae617bfeea35d2164532df91597 +Author: Dave Liu +Date: Fri Mar 5 12:22:00 2010 +0800 + + fsl-ddr: change the default burst mode for DDR3 + + For 64B cacheline SoC, set the fixed 8-beat burst len, + for 32B cacheline SoC, set the On-The-Fly as default. + + Signed-off-by: Dave Liu + +commit ec145e87b80f6764d17a6b0aebf521fe758c3fdc +Author: Dave Liu +Date: Fri Mar 5 12:22:00 2010 +0800 + + fsl-ddr: Fix the turnaround timing for TIMING_CFG_4 + + Read-to-read/Write-to-write turnaround for same chip select + of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and + OTF case, BL/2 cycles is enough for fixed BL8. + Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 + will improve the memory performance. + + Signed-off-by: Dave Liu + +commit ab467c512e79dbd14f02352655f054a4304c457e +Author: Roy Zang +Date: Tue Feb 9 18:23:33 2010 +0800 + + fsl_esdhc: Only modify the field we are changing in WML + + When we set the read or write watermark in WML we should maintain the + rest of the register as is, rather than using some hard coded value. + + Signed-off-by: Roy Zang + Acked-by: Stefano Babic + Signed-off-by: Kumar Gala + +commit 48bb3bb5ac4dd21e931ae157caad6449bcb2d0d4 +Author: Jerry Huang +Date: Thu Mar 18 15:57:06 2010 -0500 + + fsl_esdhc: Add function to reset the eSDHC controller + + To support multiple block read command we must set abort or use auto + CMD12. If we booted from eSDHC controller neither of these are used + and thus we need to reset the controller to allow multiple block read + to function. + + Signed-off-by: Jerry Huang + Signed-off-by: Roy Zang + Acked-by: Stefano Babic + Signed-off-by: Kumar Gala + +commit cc4d1226585fa2544b5116702b02eacbb7aa48a1 +Author: Kumar Gala +Date: Thu Mar 18 15:51:05 2010 -0500 + + fsl_esdhc: Always stop clock before changing frequency + + We need to stop the clocks on 83xx/85xx as well as imx. No need to make + this code conditional to just imx. + + Signed-off-by: Kumar Gala + Acked-by: Stefano Babic + +commit d0b0dcaa220549999d6ea74cf87487846c186a0f +Author: Stefan Roese +Date: Thu Apr 1 14:37:24 2010 +0200 + + i2c: Move PPC4xx I2C driver into drivers/i2c directory + + This patch moves the PPC4xx specific I2C device driver into the I2C + drivers directory. All 4xx config headers are updated to include this + driver. + + Signed-off-by: Stefan Roese + +commit b5045cdda556c73e2697cd1d3ea6563315cbf490 +Author: Detlev Zundel +Date: Wed Mar 31 15:38:55 2010 +0200 + + arm/integrator: Remove unneccessary CONFIG_PCI check. + + pci_eth_init() is already conditional to CONFIG_PCI so not every caller + needs to have conditionals. + + This is the only place in the current code base where such a check is + still at the calling site. + + Signed-off-by: Detlev Zundel + CC: Ben Warren + CC: Peter Pearse + +commit 0701f730cebc8dd065b70812ca0332055dcf10f8 +Author: Matthias Fuchs +Date: Thu Mar 25 14:30:13 2010 +0100 + + at91: use C structs for AT91 OHCI code + + This patch is part of migrating the AT91 support towards + using C struct for all SOC access. + + It removes one more CONFIG_AT91_LEGACY warning. + + at91_pmc.h needs cleanup after migration of the drivers + has been done. + + Signed-off-by: Matthias Fuchs + +commit e99056e3877d1f04a36991aa48f1c690547f5ab9 +Author: Asen Dimov +Date: Thu Mar 18 13:46:45 2010 +0200 + + using AT91_PMC_MCKR_MDIV_ instead of LEGACY one in at91/clock.c + + Signed-off-by: Asen Dimov + +commit 4b894a97d307c3207af40031d9e820e2960de57f +Author: Alessandro Rubini +Date: Wed Nov 25 23:41:51 2009 +0100 + + Nomadik: fix reset_timer() + + Previous code was failing when reading back the timer less than + 400us after resetting it. This lead nand operations to incorrectly + timeout any now and then. Moreover, writing the load register isn't + immediately reflected in the value register. We must wait for a clock + edge, so read_timer now waits for the value to change at least once, + otherwise nand operation would timeout anyways (though less frequently). + + Signed-off-by: Alessandro Rubini + Acked-by: Andrea Gallo + +commit f936aa0528fe4f5d86168575528e0c52b485c642 +Author: Achim Ehrlich +Date: Wed Mar 17 14:50:29 2010 +0100 + + Convert at91 watchdog driver to new SoC access + + This converts the at91 watchdog driver to new c structure + type to access registers of the SoC + + Signed-off-by: Achim Ehrlich + +commit c9f72b3da8855c3c9679c821127cccd91e0380ed +Author: Daniel Gorsulowski +Date: Wed Mar 17 08:21:11 2010 +0100 + + at91: boards cleanup for deprecated CONFIG_CMD_AUTOSCRIPT + + CONFIG_CMD_AUTOSCRIPT support is deprecated and non-existing + This clean up patch removes the references for esd boards + + Signed-off-by: Daniel Gorsulowski + +commit b032698ff687034286c98c09fd4830d804cd1786 +Author: Matthias Kaehlcke +Date: Tue Mar 9 22:13:56 2010 +0100 + + ep93xx timer: refactoring + + ep93xx timer: Simplified the timer code by eliminating clk_to_systicks() and + performing (almost) all manipulation of the timer structure in read_timer() + + Signed-off-by: Matthias Kaehlcke + +commit 33eef04bf8541f7b15d4f694ad10f9b912b9caa6 +Author: Matthias Kaehlcke +Date: Tue Mar 9 22:13:47 2010 +0100 + + ep93xx timer: Rename struct timer_reg pointers + + ep93xx timer: Renamed pointers to struct timer_regs from name 'timer' to + 'timer_regs' in order to avoid confusion with the global variable 'timer' + + Signed-off-by: Matthias Kaehlcke + +commit 2528dc52361bea49e6bd4a95ce2374d0004ca56f +Author: Naveen Krishna CH +Date: Fri Mar 5 17:16:05 2010 +0900 + + SAMSUNG: SMDKC100: Adds ethernet support. + + Add setup for ethernet on SMDKC100, allowing kernel/ramdisk to be + loaded over tftp. + + The preinit function will configure GPIO (GPK0CON) & SROMC to look + for environment in SROM Bank 3. + + Signed-off-by: Naveen Krishna Ch + Signed-off-by: Minkyu Kang + +commit 01802e0d22a4bb3903b342ff2357ea3bbcccd289 +Author: Naveen Krishna CH +Date: Fri Mar 5 17:15:38 2010 +0900 + + S5PC100: Function to configure the SROMC registers. + + Nand Flash, Ethernet, other features might need to configure the + SROMC registers accordingly. + The config_sromc() functions helps with this. + + Signed-off-by: Naveen Krishna Ch + Signed-off-by: Minkyu Kang + +commit a28bec89ccc17b56a50d841c8f0778e927434d1c +Author: Naveen Krishna CH +Date: Fri Mar 5 17:15:13 2010 +0900 + + S5PC100: Memory SubSystem Header file, register description(SROMC). + + Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand, + NAND Flash, DDRs. + smc.h is a common place for the register description of Memory subsystem + of S5PC100. + Note: Only SROM related registers are descibed now. + + Signed-off-by: Naveen Krishna Ch + Signed-off-by: Minkyu Kang + +commit abbe18c353c297a40c428ba92f3e1a85e8e694fc +Author: Minkyu Kang +Date: Fri Feb 12 18:21:17 2010 +0900 + + s5pc1xx: update the README file + + Because adds support the GPIO Interface, README file is updated. + + Signed-off-by: Minkyu Kang + +commit ab693e9c4c06b42d1746a0d7a03541968fb55bb9 +Author: Minkyu Kang +Date: Fri Feb 12 18:17:52 2010 +0900 + + s5pc1xx: support the GPIO interface + + This patch adds support the GPIO interface + + Signed-off-by: Minkyu Kang + +commit 7b92159bd9fc0acaddd65b314da252b715d1b44e +Author: Joonyoung Shim +Date: Mon Feb 8 22:00:52 2010 +0900 + + s3c64xx: Add ifdef at the S3C64XX only codes + + The s3c6400.h file is only for S3C64XX cpu and the pheripheral port + address(0x70000000 - 0x7fffffff) exists at only S3C64XX cpu, so they + should be included by only S3C64XX cpu. + + Signed-off-by: Joonyoung Shim + Signed-off-by: Minkyu Kang + +commit 6c71a8fec95a9e0f90fbc47469c389c6f35d96bc +Author: Naveen Krishna CH +Date: Thu Feb 4 14:17:38 2010 +0900 + + S5PC100: Moves the Macros to a common header file + + The get_pll_clk(int) API returns the PLL frequency based on + the (int) argument which is defined locally in clock.c + + Moving that #define to common header file (clk.h) would + be helpful when using the API from other files. + + Signed-off-by: Naveen Krishna Ch + Signed-off-by: Minkyu Kang + +commit 2ca551dd7ad6ec11418f113b1b50c96fdd15a370 +Author: Minkyu Kang +Date: Mon Mar 8 16:22:33 2010 +0900 + + MAINTAINERS: sort the list of ARM Maintainers by last name + + Signed-off-by: Minkyu Kang + +commit c937c42431923c96a617e9462e2c0ecbaf2ad72d +Author: Vipin KUMAR +Date: Mon Mar 8 10:46:07 2010 +0530 + + SPEAr : Adding maintainer name for spear SoCs + + Signed-off-by: Vipin Kumar + +commit d8bc0a2889700ba063598de6d4e7d135360b537e +Author: Scott McNutt +Date: Thu Apr 1 00:00:56 2010 -0400 + + nios2: Reload timer count in reset_timer() + + When the timestamp is incremented via interrupt and the interrupt + period is greater than 1 msec, successive calls to get_timer() can + produce inaccurate timing since the interrupts are asynchronous + to the timing loop. For example, with an interrupt period of 10 msec + two successive calls to get_timer() could indicate an elapsed time + of 10 msec after only several hundred usecs -- depending on when + the next interrupt actually occurs. This behavior can cause + reliability issues with components such as CFI and NAND. + + This can be remedied by calling reset_timer() prior to establishing + the base timestamp with get_timer(0), provided reset_timer() + resets the hardware timer (rather than simply resetting only the + timestamp). This has the effect of synchronizing the interrupts + (and the advance of the timestamp) with the timing loop. + + Signed-off-by: Scott McNutt + +commit ed2941578480d30b413e081b6f1a5675d4afd9e2 +Author: Thomas Chou +Date: Wed Mar 24 11:41:46 2010 +0800 + + nios2: pass command line and initrd to linux in bootm.c + + This patch adds bootargs passing to nios2 linux. + + The args passing is enabled with, + r4 : 'NIOS' magic + r5 : pointer to initrd start + r6 : pointer to initrd end + r7 : pointer to command line + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit 9e486ab1c98ea7ab357520307fe5d5a0847cd1bb +Author: Scott McNutt +Date: Tue Mar 30 20:26:15 2010 -0400 + + nios2: Fix AMDLV065D flash write bug in altera board common tree. + + Signed-off-by: Scott McNutt + +commit 3a89a91a10fed545af458418e63d911953a9849c +Author: Scott McNutt +Date: Tue Mar 30 20:23:04 2010 -0400 + + nios2: Set CONFIG_SYS_HZ to 1000 all nios2 boards. + + CONFIG_SYS_HZ was being calculated (incorrectly) in nios2 configuration + headers. Updated comments to accurately describe timebase macros. + + Signed-off-by: Scott McNutt + +commit 3ea0037f2337de692b5fd2b6a4449db1de3067a2 +Author: Scott McNutt +Date: Sun Mar 21 21:24:43 2010 -0400 + + nios2: Fix outx/writex parameter order in io.h + + The outx/writex macros were using writex(addr, val) rather than + the standard writex(val, addr), resulting in incompatibilty with + architecture independent components. This change set uses standard + parameter order. + + Signed-off-by: Scott McNutt + +commit 64da04d24ea685483f9afa07088f76931b6c0e01 +Author: Scott McNutt +Date: Sun Mar 21 15:36:44 2010 -0400 + + nios2: Add support for EPCS16 and EPCS64 configuration devices. + + Signed-off-by: Scott McNutt + +commit 3fd2a1f3eb83a0bbb84a1397ff9c2af7e6f5d069 +Author: Scott McNutt +Date: Sun Mar 21 13:26:33 2010 -0400 + + nios2: Add missing Ethernet initialization to board_init(). + + Signed-off-by: Scott McNutt + +commit c72bfafbc94e61ea3ff3915c84aa7f9d91a045a0 +Author: Thomas Chou +Date: Sat Mar 20 07:05:47 2010 +0800 + + nios2: add struct stat support in linux/stat.h + + This is needed for jffs2 support. + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit 3bef253f0802c6292b8e2acc0089894019e99e62 +Author: Thomas Chou +Date: Sat Mar 20 07:05:46 2010 +0800 + + nios2: use bitops from linux-2.6 asm-generic + + These are needed to use ubi/ubifs. + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit d8b73dffa9866d6de3c05c8a2d07ecd4bc0d5d7e +Author: Thomas Chou +Date: Sat Mar 20 07:05:45 2010 +0800 + + nios2: add local_irq_enable/disable to asm-nios2/system.h + + Copy from linux header. This is needed for generic bitops. + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit 54d809e7553939629e8941ab9eef1f762463a2b3 +Author: Thomas Chou +Date: Sat Mar 20 07:05:44 2010 +0800 + + nios2: add asm-nios2/errno.h + + Just pull in asm-generic. + + Signed-off-by: Thomas Chou + Signed-off-by: Scott McNutt + +commit c9d4f46b5d639a45747d5eaabd31d35856cb918f +Author: Scott McNutt +Date: Fri Mar 19 19:03:28 2010 -0400 + + nios2: Move serial drivers to individual files in drivers/serial + + The standard Altera UART & JTAG UART as well as the OpenCores + YANU driver are now in individual files in drivers/serial + rather than a single file uner cpu/nios2. + + Signed-off-by: Scott McNutt + +commit ca6e1c136ddb720c3bb2cc043b99f7f06bc46c55 +Author: Wolfgang Denk +Date: Wed Mar 31 23:54:39 2010 +0200 + + Prepare v2010.03 + + Signed-off-by: Wolfgang Denk + commit 8e64d6efd8d778a5f83d8bff9cd273a86dcc182f Author: Heiko Schocher Date: Wed Mar 31 08:34:51 2010 +0200 @@ -140,6 +3729,53 @@ Date: Mon Mar 29 13:15:48 2010 +0200 Signed-off-by: Heiko Schocher +commit fd03ea89641d6f6ade6d1a8580c1bb9f52b8542c +Author: Frans Meulenbroeks +Date: Fri Mar 26 09:46:42 2010 +0100 + + i2c: made unused function i2c_mux_add_device static + + and removed it from the .h file + + Signed-off-by: Frans Meulenbroeks + +commit 2c0dc990202c69a6231122ec2463c4e3076a16f3 +Author: Frans Meulenbroeks +Date: Fri Mar 26 09:46:41 2010 +0100 + + cmd_i2c: introduced get_alen helper function + + The code to parse alen appeared 6 times in the function. + Factored this out in a small helper function + + Signed-off-by: Frans Meulenbroeks + +commit a266fe955a55bb7a03a67f3c91033068f317b337 +Author: Frans Meulenbroeks +Date: Fri Mar 26 09:46:40 2010 +0100 + + cmd_i2c: moved a define to before the functions + + Signed-off-by: Frans Meulenbroeks + +commit 4a8cf3382a6fea5cccc1e2ae61a4601bf26490c3 +Author: Frans Meulenbroeks +Date: Fri Mar 26 09:46:39 2010 +0100 + + cmd_i2c: moved mispositioned comment for i2c md + + Signed-off-by: Frans Meulenbroeks + +commit 3a6dcb988eee3fd3cd9c5ef96855a8da729a290e +Author: Frans Meulenbroeks +Date: Fri Mar 26 09:46:38 2010 +0100 + + cmd_i2c.c: declared local functions as static + + Declared all functions that were not called outside the file as static + + Signed-off-by: Frans Meulenbroeks + commit 2883cc2d48e99fd1873ef8af03fee7966611b735 Author: Wolfgang Denk Date: Sun Mar 28 00:25:14 2010 +0100 @@ -183,6 +3819,27 @@ Date: Sat Mar 27 23:37:46 2010 +0100 Signed-off-by: Wolfgang Denk +commit e5720823f6f81a0f3a9e3404dbc37059bf6644f1 +Author: Thomas Chou +Date: Fri Mar 26 08:17:00 2010 +0800 + + cfi flash: add status polling method for amd flash + + This patch adds status polling method to offer an alternative to + data toggle method for amd flash chips. + + This patch is needed for nios2 cfi flash interface, where the bus + controller performs 4 bytes read cycles for a single byte read + instruction. The data toggle method can not detect chip busy + status correctly. So we have to poll DQ7, which will be inverted + when the chip is busy. + + This feature is enabled with the config def, + CONFIG_SYS_CFI_FLASH_STATUS_POLL + + Signed-off-by: Thomas Chou + Signed-off-by: Stefan Roese + commit c40c94a3d20a8616264c2dfcda85279185d69aeb Author: Renato Andreola Date: Wed Mar 24 23:00:47 2010 +0800 @@ -196,6 +3853,205 @@ Date: Wed Mar 24 23:00:47 2010 +0800 Signed-off-by: Thomas Chou Signed-off-by: Stefan Roese +commit 9d3a86aec52cb3c0e9badd12167d9292184ce4dd +Author: TsiChung Liew +Date: Tue Mar 16 12:39:36 2010 -0500 + + ColdFire: Fix m54455EVB save environment bug + + The ATMEL flash does not have buffer write feature. Assgined + buffer_size = 1, so that when there is a write to the flash + will not use buffer write function. + + Signed-off-by: TsiChung Liew + +commit f26a247308568e32857a5cc054f7219510a7d44e +Author: TsiChung Liew +Date: Mon Mar 15 19:39:21 2010 -0500 + + ColdFire: Fix incorrect M5253DEMO default environment + + The flash location is at 0xff800000, not 0 + + Signed-off-by: TsiChung Liew + +commit dd9f054ede433de73b137987fb3dc066e8d24ebb +Author: TsiChung Liew +Date: Thu Mar 11 22:12:53 2010 -0600 + + ColdFire: Cache update for all platforms + + The CF will call cache functions in lib_m68/cache.c and the + cache settings are defined in platform configuration file. + + Signed-off-by: TsiChung Liew + +commit f628e2f72daee810aa568619b6629da68ad042d6 +Author: TsiChung Liew +Date: Wed Mar 10 18:50:22 2010 -0600 + + ColdFire: Fix SDRAM size on M5208evb rev E + + The proper SDRAM size is 32MB not 64MB + + Signed-off-by: Jingchang Lu + +commit 9e8e927023582231b034e199568e49f84ac032a9 +Author: TsiChung Liew +Date: Wed Mar 10 18:24:07 2010 -0600 + + ColdFire: Misc update for M53017 + + Reside Ethernet buffer descriptors in SRAM instead of DRAM. Add + CONFIG_SYS_TX_ETH_BUFFER in platform configuration file. Update + DRAM control and SRAM control register setting. Update cache + setting where size does not write to proper region. + + Signed-off-by: TsiChung Liew + Signed-off-by: Jason Jin + +commit f9d877a6479878ca96688671f37d87b620c3e77c +Author: TsiChung Liew +Date: Wed Mar 10 17:32:13 2010 -0600 + + ColdFire: Add CPU compile flag for mcf5301x and mcf532x + + Add CPU compile flag -mcpu=53015 in cpu/config.mk + + Signed-off-by: TsiChung Liew + +commit 0e8a75550695aba9d8cfe9c7f7713da42c1f3e89 +Author: TsiChung Liew +Date: Wed Mar 10 16:33:03 2010 -0600 + + ColdFire: Update Extra environment Data for M5275EVB + + Provide extra environment Data. Remove default network + address and MAC address. + + Signed-off-by: TsiChung Liew + +commit 53e4290f20b5f73c95717f47f4c04ed6932ff931 +Author: TsiChung Liew +Date: Wed Mar 10 16:14:01 2010 -0600 + + ColdFire: M5271EVB DRAM Bring up issue + + Fix proper portsize: The register for portsize is either 00b, 01b, + or 1xb. The value that previous assigned is 32d. + Fix DRAM bring up: insert asm("nop") for every DRAM register setup + + Signed-off-by: TsiChung Liew + +commit ac265f7fcab1a09b9a837a34ef8b10acc101695e +Author: TsiChung Liew +Date: Wed Mar 10 11:56:36 2010 -0600 + + ColdFire: Update M5253DEMO configuration file + + Fix incorrect default environment for flash erase or protect + range. Change offset from 0 to 0xff80nnnn. Remove default + ethernet setup and MAC address. + + Signed-off-by: TsiChung Liew + +commit 68e4e76af55746a4330865f56476e58ce4140ca8 +Author: TsiChung Liew +Date: Thu Mar 11 15:04:21 2010 -0600 + + ColdFire: Relocate vector table - mcf5445x + + Newer ColdFire processors family boot from address 0 instead of + 0xFFnn_nnnn. When the boot flash base chip select is set at new + location instead of 0, an un-predictable error will occur if + there is an vector being trigger and refer it to an invalid + address or the vector table handler is not existed at address + 0. + + Signed-off-by: TsiChung Liew + +commit fa9da596212d7f28eb26a3257d79d9515f9838cd +Author: TsiChung Liew +Date: Tue Mar 9 19:24:43 2010 -0600 + + ColdFire: Update uart_port_conf in serial driver + + Provide proper port passing from serial_init to uart_part_conf. + + Signed-off-by: TsiChung Liew + +commit 52affe04fa5493597d8a5f6202507190950a32e6 +Author: TsiChung Liew +Date: Tue Mar 9 19:17:52 2010 -0600 + + ColdFire: Update processors' serial port configuration + + Provide parameter passing to uart_port_config(). Update port + configuration - un-mask it before enable the bits. + + Signed-off-by: TsiChung Liew + +commit d04c1efae3d834db6e21e9976e338bf1e588e987 +Author: TsiChung Liew +Date: Tue Mar 9 18:32:16 2010 -0600 + + ColdFire: Correct bit definition + + Use correct definition for _MASK and _UNMASK. It was combined in + the previous used and causes confusion. + + Signed-off-by: TsiChung Liew + +commit 116095eb1f0f7017ea8062aa8a8ba8ceecb430b5 +Author: Philippe De Muyter +Date: Mon Sep 21 22:20:29 2009 -0600 + + fix cmd_bdinfo.c:354: warning: 'print_eth' defined but not used + + This fixes the following warnings when running MAKEALL for coldfire : + cmd_bdinfo.c:354: warning: 'print_eth' defined but not used + + Signed-off-by: Philippe De Muyter + +commit dfc2b7697dc07862da804c1be084f96301884bc7 +Author: Michael Durrant +Date: Wed Jan 20 19:33:02 2010 -0600 + + Adding EP2500 MCF5282 board [PATCH] + + Mercury-EP2500.patch + - added Mercury's EP2500 board uses the mcf5282 processor + + CREDITS.patch + + Signed-off-by: David Wu + Signed-off-by: Michael Durrant + +commit 89083346d0627a5e6e271e61bd34ab5121f9462b +Author: Wolfgang Wegner +Date: Fri Oct 30 16:55:02 2009 +0100 + + add block write function to spartan3 slave serial load + + Using seperate function calls for each bit-bang of slave serial + load can be painfully slow. This patch adds the possibility to + supply a block write function that loads the complete block of + data in one call (like it can already be done with Altera FPGAs). + On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load + time from around 15 seconds to around 3 seconds + + Signed-off-by: Wolfgang Wegner + +commit 9d79e5758c3a6776be9a86856823d28e7154a481 +Author: Wolfgang Wegner +Date: Mon Jan 25 11:27:44 2010 +0100 + + add ASTRO MCF5373L board + + This patch adds support for ASTRO board(s) based on MCF5373L. + + Signed-off-by: Wolfgang Wegner + commit c550afada5fcad426aa6a219a329feb9eedae8b2 Author: Rupjyoti Sarmah Date: Wed Mar 24 16:52:02 2010 +0530 @@ -240,6 +4096,41 @@ Date: Sat Mar 13 17:44:08 2010 +0100 Acked-by: Andrea Gallo Signed-off-by: Anatolij Gustschin +commit 6b94b4962211c16ee2197048faa887e1f92f3757 +Author: Florian Fainelli +Date: Sat Mar 20 19:02:58 2010 +0100 + + cmd_nand: show nand scrub confirmation character + + When issuing a nand scrub command, the entered character is not displayed + this may be confusing. This patch makes the input character being + displayed if it is a 'y' so that an user knows he is about to scrub his + nand. + + Signed-off-by: Florian Fainelli + +commit 7c27b7b1eac43cdcda735bad6231cdfc1f602284 +Author: Nikolay Petukhov +Date: Fri Mar 19 10:49:27 2010 +0500 + + at91: add hwecc method for nand + + This is a patch to use the hardware ECC controller of + the AT91SAM9260 for the AT91 nand. Taken from the kernel 2.6.33. + + Signed-off-by: Nikolay Petukhov + +commit cc41a59a74ca9095d518d6d69655c6735dd00809 +Author: Cyril Chemparathy +Date: Wed Mar 17 10:03:10 2010 -0400 + + TI: Davinci: NAND Driver Cleanup + + Modified to use IO accessor routines consistently. Eliminated volatile usage + to keep checkpatch.pl happy. + + Signed-off-by: Cyril Chemparathy + commit 152dda3d94e97ede7af3f9560a59a659384d4585 Author: Wolfgang Denk Date: Mon Mar 22 23:25:00 2010 +0100 @@ -272,6 +4163,160 @@ Date: Tue Mar 9 22:13:20 2010 +0100 Signed-off-by: Matthias Kaehlcke +commit 3c950e2ebfde083084cc926b020e3a22a536bf85 +Author: Anatolij Gustschin +Date: Tue Mar 16 17:10:05 2010 +0100 + + fdt_support: add partitions fixup in mtd node + + Allow overwriting defined partitions in the device tree blob + using partition info defined in the 'mtdparts' environment + variable. + + Signed-off-by: Anatolij Gustschin + Cc: Gerald Van Baren + +commit d611295032c30e6c533cb356005fa82ab7992824 +Author: John Schmoller +Date: Fri Mar 12 09:49:24 2010 -0600 + + cmd history: Match history buffer size to console buffer + + Match history buffer size to console buffer size. History buffer size + was hard coded to 256, artificially limiting the command buffer size. + The history buffer now tracks CONFIG_SYS_CBSIZE. + + Signed-off-by: John Schmoller + +commit 6475b9f91bd33bfd38418469cabdcfc0fefbd848 +Author: John Schmoller +Date: Fri Mar 12 09:49:23 2010 -0600 + + console: Fix console buffer overrun + + When CONFIG_SYS_CBSIZE equals MAX_CMDBUF_SIZE, a command string of + maximum length will overwrite part of the history buffer, causing the + board to die. Expand the console_buffer and hist_lines buffer by one + character each to hold the missing NULL char. + + Signed-off-by: John Schmoller + +commit e070a56c777f1fd05950e1bc63483c19decd6f78 +Author: Michael Zaidman +Date: Mon Mar 1 11:47:36 2010 +0200 + + POST: add progress API + + Add POST progress API implemented as weak calls before and after + each call to the POST test callback in the post_run_single routine + of the post.c file. + + Signed-off-by: Michael Zaidman + Acked-by: Detlev Zundel + +commit 47ab5ad14575531798431f0d1e8f83ee9bb0a87e +Author: Frans Meulenbroeks +Date: Fri Feb 26 14:00:19 2010 +0100 + + cmd_setexpr: allow memory addresses in expressions + + This patch add functionality to use memory addresses in expressions. + This increases the power of expressions substantially + + It adheres to the standard convemtions: memory addresses can be given + in the format *address (e.g. *1000) + + Rationale for this change is that it allows masking off bits from a + byte that is obtained by reading data from e.g. i2c. + + Signed-off-by: Frans Meulenbroeks + + Fix warning: control reaches end of non-void function + Signed-off-by: Wolfgang Denk + +commit 652e53546b23c25f80756287eaf607b713afdc87 +Author: Frans Meulenbroeks +Date: Thu Feb 25 10:12:16 2010 +0100 + + cmd_i2c.c: added i2c read to memory function + + Signed-off-by: Frans Meulenbroeks + +commit fb0070e9101a1f288d7054f7e80b3d808fd7ead2 +Author: Frans Meulenbroeks +Date: Thu Feb 25 10:12:15 2010 +0100 + + cmd_i2c.c: sorted commands alphabetically + + Signed-off-by: Frans Meulenbroeks + +commit bfc3b77ebe68435b46e988e3a440bc4857bc7cf4 +Author: Frans Meulenbroeks +Date: Thu Feb 25 10:12:14 2010 +0100 + + cmd_i2c.c: reworked subcommand handling + + Signed-off-by: Frans Meulenbroeks + +commit f74d9bd2a248efa229f0f3478fe331e2a319588c +Author: Frans Meulenbroeks +Date: Thu Feb 25 10:12:13 2010 +0100 + + cmd_bootm.c: made subcommand array static + + Signed-off-by: Frans Meulenbroeks + +commit faffe14f016db10f33836b018c4b304d939cf586 +Author: Frans Meulenbroeks +Date: Thu Feb 25 10:12:12 2010 +0100 + + cmd_i2c.c: reduced subaddress length to 3 bytes + + according to some of the comments the subaddress length is 1 or 2, but we are being + prepared for the case it becomes 3. However the code also accepted 4. + This repairs this by changing the constand 4 to 3. + + Signed-off-by: Frans Meulenbroeks + +commit a6a04967bc2957d20799f4bb2a6b3dd0353c1cfd +Author: Renato Andreola +Date: Tue Mar 16 16:01:29 2010 -0400 + + nios2: Added support to YANU UART + + Signed-off-by: Scott McNutt + +commit 352745ad487f72e839986ddbb020e1fe86c1d482 +Author: Thomas Chou +Date: Tue Mar 16 12:12:48 2010 -0400 + + nios2: use generic unaligned.h + + Signed-off-by: Scott McNutt + +commit fd428c05c863aefb575b12b2a1916b02d5bfa759 +Author: Detlev Zundel +Date: Fri Mar 12 10:01:12 2010 +0100 + + mpc5xxx: Remove all references to MGT5100 + + We do not support a processor that never reached a real customer. + + Signed-off-by: Detlev Zundel + +commit c0c316569f70055eb7c70864aaa6d48666782600 +Author: Matthias Weisser +Date: Tue Jan 12 12:06:31 2010 +0100 + + video: Fix console display when splashscreen is used + + If a splashscreen is used the console scrolling used the + scroll size as needed when a logo was displayed. This + patch sets the scroll size to the whole screen if + a splashscreen is shown. + + Signed-off-by: Matthias Weisser + commit daa989b47297c9f73426783599c286ef3a1f3f49 Author: Asen Dimov Date: Thu Mar 18 13:41:47 2010 +0200 diff --git a/arch/i386/include/asm/bootparam.h b/arch/i386/include/asm/bootparam.h index 64d2e1f1367..140095117e5 100644 --- a/arch/i386/include/asm/bootparam.h +++ b/arch/i386/include/asm/bootparam.h @@ -117,7 +117,4 @@ enum { X86_SUBARCH_MRST, X86_NR_SUBARCHS, }; - - - #endif /* _ASM_X86_BOOTPARAM_H */ diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c index f18f7f444e1..f3830112aa6 100644 --- a/drivers/serial/opencores_yanu.c +++ b/drivers/serial/opencores_yanu.c @@ -69,7 +69,7 @@ void serial_setbrg (void) #else void serial_setbrg (void) -{ +{ int n, k; const unsigned max_uns = 0xFFFFFFFF; unsigned best_n, best_m, baud; @@ -114,12 +114,14 @@ int serial_init (void) YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR; writel(action, &uart->action); - - /* control register cleanup */ - /* no interrupts enabled */ - /* one stop bit */ - /* hardware flow control disabled */ - /* 8 bits */ + + /* + * control register cleanup + * no interrupts enabled + * one stop bit + * hardware flow control disabled + * 8 bits + */ control = (0x7 << YANU_CONTROL_BITS_POS); /* enven parity just to be clean */ control |= YANU_CONTROL_PAREVEN; @@ -146,7 +148,7 @@ void serial_putc (char c) if (c == '\n') serial_putc ('\r'); - + while (1) { status = readl(&uart->status); tx_chars = (status>>YANU_TFIFO_CHARS_POS) @@ -174,13 +176,13 @@ int serial_tstc(void) status = readl(&uart->status); return (((status >> YANU_RFIFO_CHARS_POS) & ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0); -} +} int serial_getc (void) { while (serial_tstc() == 0) WATCHDOG_RESET (); - + /* first we pull the char */ writel(YANU_ACTION_RFIFO_PULL, &uart->action); -- cgit v1.3.1