From 4cc25cd5ce6923ccd0a6164703bcbde0216fd77d Mon Sep 17 00:00:00 2001 From: Nate Drude Date: Thu, 19 May 2022 12:31:56 +0300 Subject: phy: adin: fix broken support for adi, phy-mode-override Currently, the adin driver fails to compile. The original patch introducing the adin driver used the function phy_get_interface_by_name to support the adi,phy-mode-override property. Unfortunately, a few days before the adin patch was accepted, another patch removed support for phy_get_interface_by_name: https://github.com/u-boot/u-boot/commit/123ca114e07ecf28aa2538748d733e2b22d8b8b5 This patch refactors adin_get_phy_mode_override, implementing the logic in the new function, ofnode_read_phy_mode, from the patch above. Signed-off-by: Nate Drude Tested-by: Josua Mayer Signed-off-by: Josua Mayer --- drivers/net/phy/adin.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index cff841ab3dd..e60f288b9b6 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -100,27 +100,27 @@ static u32 adin_get_reg_value(struct phy_device *phydev, * The function gets phy-mode string from property 'adi,phy-mode-override' * and return its index in phy_interface_strings table, or -1 in error case. */ -int adin_get_phy_mode_override(struct phy_device *phydev) +phy_interface_t adin_get_phy_mode_override(struct phy_device *phydev) { ofnode node = phy_get_ofnode(phydev); const char *phy_mode_override; const char *prop_phy_mode_override = "adi,phy-mode-override"; - int override_interface; + int i; phy_mode_override = ofnode_read_string(node, prop_phy_mode_override); if (!phy_mode_override) - return -ENODEV; + return PHY_INTERFACE_MODE_NA; debug("%s: %s = '%s'\n", __func__, prop_phy_mode_override, phy_mode_override); - override_interface = phy_get_interface_by_name(phy_mode_override); + for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) + if (!strcmp(phy_mode_override, phy_interface_strings[i])) + return (phy_interface_t) i; - if (override_interface < 0) - printf("%s: %s = '%s' is not valid\n", - __func__, prop_phy_mode_override, phy_mode_override); + printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode_override); - return override_interface; + return PHY_INTERFACE_MODE_NA; } static u16 adin_ext_read(struct phy_device *phydev, const u32 regnum) @@ -148,10 +148,10 @@ static int adin_config_rgmii_mode(struct phy_device *phydev) { u16 reg_val; u32 val; - int phy_mode_override = adin_get_phy_mode_override(phydev); + phy_interface_t phy_mode_override = adin_get_phy_mode_override(phydev); - if (phy_mode_override >= 0) { - phydev->interface = (phy_interface_t) phy_mode_override; + if (phy_mode_override != PHY_INTERFACE_MODE_NA) { + phydev->interface = phy_mode_override; } reg_val = adin_ext_read(phydev, ADIN1300_GE_RGMII_CFG); -- cgit v1.3.1 From 54337abb141d898ae114f51619531cf905d5b0b5 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 19 May 2022 12:31:57 +0300 Subject: phy: adin: add support for clock output The ADIN1300 supports generating certain clocks on its GP_CLK pin, as well as providing the reference clock on CLK25_REF. Add support for selecting the clock via device-tree properties. This patch is based on the Linux implementation for this feature, which has been added to netdev/net-next.git [1]. [2] https://patchwork.kernel.org/project/netdevbpf/cover/20220517085143.3749-1-josua@solid-run.com/ Signed-off-by: Josua Mayer --- drivers/net/phy/adin.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'drivers') diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index e60f288b9b6..a5bfd960d9c 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -4,6 +4,7 @@ * * Copyright 2019 Analog Devices Inc. * Copyright 2022 Variscite Ltd. + * Copyright 2022 Josua Mayer */ #include #include @@ -13,6 +14,16 @@ #define PHY_ID_ADIN1300 0x0283bc30 #define ADIN1300_EXT_REG_PTR 0x10 #define ADIN1300_EXT_REG_DATA 0x11 + +#define ADIN1300_GE_CLK_CFG_REG 0xff1f +#define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0) +#define ADIN1300_GE_CLK_CFG_RCVR_125 BIT(5) +#define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4) +#define ADIN1300_GE_CLK_CFG_REF_EN BIT(3) +#define ADIN1300_GE_CLK_CFG_HRT_RCVR BIT(2) +#define ADIN1300_GE_CLK_CFG_HRT_FREE BIT(1) +#define ADIN1300_GE_CLK_CFG_25 BIT(0) + #define ADIN1300_GE_RGMII_CFG 0xff23 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6) #define ADIN1300_GE_RGMII_RX_SEL(x) \ @@ -144,6 +155,33 @@ static int adin_ext_write(struct phy_device *phydev, const u32 regnum, const u16 return phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_DATA, val); } +static int adin_config_clk_out(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); + const char *val = NULL; + u8 sel = 0; + + val = ofnode_read_string(node, "adi,phy-output-clock"); + if (!val) { + /* property not present, do not enable GP_CLK pin */ + } else if (strcmp(val, "25mhz-reference") == 0) { + sel |= ADIN1300_GE_CLK_CFG_25; + } else if (strcmp(val, "125mhz-free-running") == 0) { + sel |= ADIN1300_GE_CLK_CFG_FREE_125; + } else if (strcmp(val, "adaptive-free-running") == 0) { + sel |= ADIN1300_GE_CLK_CFG_HRT_FREE; + } else { + pr_err("%s: invalid adi,phy-output-clock\n", __func__); + return -EINVAL; + } + + if (ofnode_read_bool(node, "adi,phy-output-reference-clock")) + sel |= ADIN1300_GE_CLK_CFG_REF_EN; + + return adin_ext_write(phydev, ADIN1300_GE_CLK_CFG_REG, + ADIN1300_GE_CLK_CFG_MASK & sel); +} + static int adin_config_rgmii_mode(struct phy_device *phydev) { u16 reg_val; @@ -202,6 +240,10 @@ static int adin1300_config(struct phy_device *phydev) printf("ADIN1300 PHY detected at addr %d\n", phydev->addr); + ret = adin_config_clk_out(phydev); + if (ret < 0) + return ret; + ret = adin_config_rgmii_mode(phydev); if (ret < 0) -- cgit v1.3.1 From 698c0411cfabcd245027400961d184d0e072a22c Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Fri, 3 Jun 2022 17:15:21 +0200 Subject: clk: imx8mp: fix root clock names for ecspi Root clock name contained underscore, which does not match to the actual clock name. Correct the name to match what is present in the FDT. Fixes: 87f958810fcb ("clk: imx8mp: Add ECSPI clocks") Signed-off-by: Andrey Zhizhikin Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Cc: uboot-imx Reviewed-by: Fabio Estevam --- drivers/clk/imx/clk-imx8mp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index ac727b7e404..cbed86a6843 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -122,15 +122,15 @@ static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_p "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_500m", "clk_ext4", "audio_pll2_out" }; -static const char *imx8mp_ecspi1_sels[] = {"clock-osc_24m", "sys_pll2_200m", "sys_pll1_40m", +static const char *imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char *imx8mp_ecspi2_sels[] = {"clock-osc_24m", "sys_pll2_200m", "sys_pll1_40m", +static const char *imx8mp_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char *imx8mp_ecspi3_sels[] = {"clock-osc_24m", "sys_pll2_200m", "sys_pll1_40m", +static const char *imx8mp_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -- cgit v1.3.1 From 65d5931d02d47eacdb26b879a252064bf728ae12 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Fri, 3 Jun 2022 17:15:22 +0200 Subject: clk: imx8mp: use usb_core_ref for usb_root_clk Upstream commit 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") added usb_core_ref for USB Controller but never set it to be used as a clock source, using rather "osc_32k" instead. This produces following boot log message: "clk_register: failed to get osc_32k device (parent of usb_root_clk)" Fix the USB controller clock source by using usb_core_ref instead of osc_32k. Fixes: 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") Signed-off-by: Andrey Zhizhikin Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Reviewed-by: Fabio Estevam --- drivers/clk/imx/clk-imx8mp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index cbed86a6843..ffbc1d1ba9f 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -300,7 +300,7 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); - clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "osc_32k", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "usb_core_ref", base + 0x44d0, 0)); clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); -- cgit v1.3.1 From 1a558fafbbdff80cb6a7c8e883addec7f02fe8e5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 13 Jun 2022 14:35:25 +0200 Subject: spi: nxp_fspi: Fix clock imbalance The nxp_fspi_default_setup() is only ever called from nxp_fspi_probe(), where the IP clock are initially disabled. Drop the second disabling of clock to prevent clock enable/disable imbalance reported by clock core: " clk qspi_root_clk already disabled " Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Reviewed-by: Peng Fan --- drivers/spi/nxp_fspi.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 607c953987b..579d6bac9b1 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -866,9 +866,6 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) u32 reg; #if CONFIG_IS_ENABLED(CLK) - /* disable and unprepare clock to avoid glitch pass to controller */ - nxp_fspi_clk_disable_unprep(f); - /* the default frequency, we will change it later if necessary. */ ret = clk_set_rate(&f->clk, 20000000); if (ret < 0) -- cgit v1.3.1