From 27059c3e4d99c134d050be62601afe43171173b3 Mon Sep 17 00:00:00 2001 From: "mario.six@gdsys.cc" Date: Mon, 23 May 2016 10:12:11 +0200 Subject: i2c: fsl: Fix driver initialization Due to a oversight in testing, the initialization of the recently introduced Freescale I2C DM driver works only for 36 bit mode of e.g. the MPC85XX SoCs (specifically, if the physical addresses are 64 bit wide and the DT addresses 32 bit wide). This patch corrects the initialization so that it will work in a more general setting. Signed-off-by: Mario Six Reviewed-by: York Sun --- drivers/i2c/fsl_i2c.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index b8cc647bd39..407c4a7b10b 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -583,12 +583,11 @@ static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) static int fsl_i2c_ofdata_to_platdata(struct udevice *bus) { struct fsl_i2c_dev *dev = dev_get_priv(bus); - u64 reg; - u32 addr, size; + fdt_addr_t addr; + fdt_size_t size; - reg = fdtdec_get_addr(gd->fdt_blob, bus->of_offset, "reg"); - addr = reg >> 32; - size = reg & 0xFFFFFFFF; + addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, bus->of_offset, + "reg", 0, &size); dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size); -- cgit v1.2.3 From 7f0a0e4c58e9099016eda6f1f24507c2e6173c8a Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Tue, 14 Jun 2016 13:52:37 -0400 Subject: DM: crypto/fsl: Enable rsa DM driver usage before relocation Enable rsa signature verification in SPL framework before relocation for verification of main u-boot. Reviewed-by: Aneesh Bansal Signed-off-by: Sumit Garg Reviewed-by: Simon Glass Reviewed-by: York Sun --- drivers/crypto/fsl/fsl_rsa.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/crypto/fsl/fsl_rsa.c b/drivers/crypto/fsl/fsl_rsa.c index cf1c4c1d458..5471504b6e9 100644 --- a/drivers/crypto/fsl/fsl_rsa.c +++ b/drivers/crypto/fsl/fsl_rsa.c @@ -53,6 +53,7 @@ U_BOOT_DRIVER(fsl_rsa_mod_exp) = { .name = "fsl_rsa_mod_exp", .id = UCLASS_MOD_EXP, .ops = &fsl_mod_exp_ops, + .flags = DM_FLAG_PRE_RELOC, }; U_BOOT_DEVICE(fsl_rsa) = { -- cgit v1.2.3 From 9d3b8bd166e6c23ab83d0dcd49d81c6f0bf39e17 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 5 Jul 2016 16:01:56 +0800 Subject: drivers: net/fm: Add Fman support for LS1046A The Fman module on LS1046A is similiar with that on LS1043A but LS1046A has one more XFI (10GbE) interface. Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- drivers/net/fm/Makefile | 1 + drivers/net/fm/ls1046.c | 123 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 drivers/net/fm/ls1046.c (limited to 'drivers') diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 493cdc6d48e..344fbe20a56 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_PPC_T4080) += t4240.o obj-$(CONFIG_PPC_B4420) += b4860.o obj-$(CONFIG_PPC_B4860) += b4860.o obj-$(CONFIG_LS1043A) += ls1043.o +obj-$(CONFIG_LS1046A) += ls1046.o diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c new file mode 100644 index 00000000000..bf555548b7b --- /dev/null +++ b/drivers/net/fm/ls1046.c @@ -0,0 +1,123 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */ +#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 +#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000 +#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000 +#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */ +#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 +#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000 +#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000 +#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000 + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5, + [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6, + [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9, + [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10, + [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1, + [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2, + [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3, + [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4, +}; + +static int is_device_disabled(enum fm_port port) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9))) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10))) + return PHY_INTERFACE_MODE_NONE; + + if (port == FM1_DTSEC3) + if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == + FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) + return PHY_INTERFACE_MODE_RGMII; + + if (port == FM1_DTSEC4) + if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == + FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + + /* handle SGMII, only MAC 2/5/6/9/10 available */ + switch (port) { + case FM1_DTSEC2: + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + break; + } + + /* handle 2.5G SGMII, only MAC 5/9/10 available */ + switch (port) { + case FM1_DTSEC5: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 + + port - FM1_DTSEC5)) + return PHY_INTERFACE_MODE_SGMII_2500; + break; + default: + break; + } + + /* handle QSGMII, only MAC 1/5/6/10 available */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC10: + if (is_serdes_configured(QSGMII_FM1_A)) + return PHY_INTERFACE_MODE_QSGMII; + break; + default: + break; + } + + return PHY_INTERFACE_MODE_NONE; +} -- cgit v1.2.3