From 4b422a12df73aacd961318b99072470e5b15755e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 9 Dec 2022 16:19:29 +0100 Subject: net: zynq_gem: Add support for new compatible str with xlnx prefix cdns prefix was deprecated and replaced by xlnx one. Acked-by: Krzysztof Kozlowski Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7d1312d741349451b36558baa3e9132247303992.1670599167.git.michal.simek@amd.com --- drivers/net/zynq_gem.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 507b19b7597..fe98bcfb2b6 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -821,7 +821,8 @@ static int zynq_gem_probe(struct udevice *dev) if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) { if (IS_ENABLED(CONFIG_DM_ETH_PHY)) { - if (device_is_compatible(dev, "cdns,zynqmp-gem")) { + if (device_is_compatible(dev, "cdns,zynqmp-gem") || + device_is_compatible(dev, "xlnx,zynqmp-gem")) { ret = gem_zynqmp_set_dynamic_config(dev); if (ret) { dev_err @@ -922,8 +923,11 @@ static int zynq_gem_of_to_plat(struct udevice *dev) } static const struct udevice_id zynq_gem_ids[] = { + { .compatible = "xlnx,versal-gem", .data = RXCLK_EN }, { .compatible = "cdns,versal-gem", .data = RXCLK_EN }, + { .compatible = "xlnx,zynqmp-gem" }, { .compatible = "cdns,zynqmp-gem" }, + { .compatible = "xlnx,zynq-gem" }, { .compatible = "cdns,zynq-gem" }, { .compatible = "cdns,gem" }, { } -- cgit v1.3.1 From e72023c490668299cbab3a8d5f100cbdf0d6124d Mon Sep 17 00:00:00 2001 From: Victor Lim Date: Mon, 9 Jan 2023 15:49:43 -0800 Subject: mtd: spi-nor-ids: add gigadevice part # adding gigadevice part numbers Signed-off-by: Victor Lim Link: https://lore.kernel.org/r/20230109234946.14540-2-vlim@gigadevice.com Signed-off-by: Michal Simek --- drivers/mtd/spi/spi-nor-ids.c | 68 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'drivers') diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 5f8f3ec955d..f97e10da876 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -118,6 +118,36 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + /* adding these 3V QSPI flash parts */ + {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) }, + {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25f128", 0xc84318, 0, 64 * 1024, 256, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25f256", 0xc84319, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55f512", 0xc8431A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25t512", 0xc8461A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55t02g", 0xc8461C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + /* adding these 3V OSPI flash parts */ + {INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, { INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -128,10 +158,48 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + /* adding these 1.8V QSPI flash parts */ + {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + /* adding these 1.8V OSPI flash parts */ + {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ -- cgit v1.3.1 From 29b58bba91147c3c03dcb998a1efe4a4d026d7e1 Mon Sep 17 00:00:00 2001 From: Jay Buddhabhatti Date: Tue, 10 Jan 2023 08:23:44 +0100 Subject: clk: versal: Return error in case if clock setup failed Currently probe is getting success even if clock setup is failed because of that u-boot is trying to access invalid clocks. So return error if clock setup failed. Signed-off-by: Jay Buddhabhatti Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fa78e71211e5f68f8dc1353b357f96e6283f65a8.1673335422.git.michal.simek@amd.com --- drivers/clk/clk_versal.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 76fde00491b..faebbab1c6d 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -657,7 +657,9 @@ static int versal_clk_probe(struct udevice *dev) if (ret < 0) return -EINVAL; - versal_clock_setup(); + ret = versal_clock_setup(); + if (ret < 0) + return ret; priv->clk = clock; -- cgit v1.3.1 From 988b3fa08da197e97363f4caff37a6568dfc07fc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 Jan 2023 09:25:26 +0100 Subject: soc: zynqmp: Fix IDcode for xck24 ID code was added by commit ddf8deabc39d ("arm64: zynqmp: Add support for SVD devices") based on documentation but after receiving part new ID code came up. That's why fix IDcode to match xck24 module. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7b39aeeec211458ba4132a10beb7ad295eedb87f.1674030324.git.michal.simek@amd.com --- drivers/soc/soc_xilinx_zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index a51bcdb478f..afa277f6049 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -186,7 +186,7 @@ static const struct zynqmp_device zynqmp_devices[] = { .variants = ZYNQMP_VARIANT_DR, }, { - .id = 0x04714093, + .id = 0x04712093, .device = 24, .variants = 0, }, -- cgit v1.3.1 From 508e1aa58c8f02a6b1a1013e3ff79d3e76015104 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Thu, 19 Jan 2023 22:36:15 -0700 Subject: gpio: zynqmp: Handle error from get_gpio_modepin There is a unused variable ret, due to which we are getting sparse warning as below. warning: variable 'ret' set but not used [-Wunused-but-set-variable]. Return ret incase of error. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230120053617.32463-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/gpio/zynqmp_gpio_modepin.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpio/zynqmp_gpio_modepin.c b/drivers/gpio/zynqmp_gpio_modepin.c index 078fd833959..e9565ff5430 100644 --- a/drivers/gpio/zynqmp_gpio_modepin.c +++ b/drivers/gpio/zynqmp_gpio_modepin.c @@ -48,6 +48,9 @@ static int modepin_gpio_set_value(struct udevice *dev, unsigned int offset, int ret; ret = get_gpio_modepin(ret_payload); + if (ret) + return ret; + if (value) out_val = OUTVAL(offset) | ret_payload[1]; else -- cgit v1.3.1 From b387c258240c761f61fbcd0c9b33039275219002 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Thu, 19 Jan 2023 22:36:17 -0700 Subject: drivers: mmc: Change datatype of tuning_loop_counter to int tuning_loop_counter is of char type, which is not capable of handling the entire data range of this variable. This is pointed by below sparse warning. Change datatype to int to fix this. warning: comparison is always false due to limited range of data type. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230120053617.32463-5-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/mmc/zynq_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 7dcf6ad8422..be4075c97a4 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -249,7 +249,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) u32 ctrl; struct sdhci_host *host; struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev); - char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; + int tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; dev_dbg(mmc->dev, "%s\n", __func__); -- cgit v1.3.1 From a33ad8051e0fdcc2af34259006c470899ad8cd77 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 25 Jan 2023 08:09:08 +0100 Subject: net: zynq_gem: Wait for SGMII PCS link in zynq_gem_init() In our system using ZynqMP with an external SGMII PHY it's necessary to wait for the PCS link and auto negotiation to finish before the xfer starts. Otherwise the first packet(s) might get dropped, resulting in a delay at the start of the ethernet transfers. This is only done when the PHY link is already up, which is done in phy_startup(). As waiting for the PHY link bits via pcsstatus does not make much sense, when the link is not available in general (e.g. no cable connected). This patch adds the necessary code including a minimal delay of 1 ms which fixes problems of dropped first packages. Signed-off-by: Stefan Roese Cc: Michal Simek Cc: Katakam Harini Cc: Ramon Fried Cc: Sean Anderson Link: https://lore.kernel.org/r/20230125070908.1343256-1-sr@denx.de Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index fe98bcfb2b6..cc49788012f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -125,6 +125,10 @@ */ #define PHY_DETECT_MASK 0x1808 +/* PCS (SGMII) Link Status */ +#define ZYNQ_GEM_PCSSTATUS_LINK BIT(2) +#define ZYNQ_GEM_PCSSTATUS_ANEG_COMPL BIT(5) + /* TX BD status masks */ #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 @@ -164,7 +168,8 @@ struct zynq_gem_regs { u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ u32 reserved9[20]; u32 pcscntrl; - u32 rserved12[36]; + u32 pcsstatus; + u32 rserved12[35]; u32 dcfg6; /* 0x294 Design config reg6 */ u32 reserved7[106]; u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ @@ -491,12 +496,37 @@ static int zynq_gem_init(struct udevice *dev) * Must be written after PCS_SEL is set in nwconfig, * otherwise writes will not take effect. */ - if (priv->phydev->phy_id != PHY_FIXED_ID) + if (priv->phydev->phy_id != PHY_FIXED_ID) { writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, ®s->pcscntrl); - else + /* + * When the PHY link is already up, the PCS link needs + * to get re-checked + */ + if (priv->phydev->link) { + u32 pcsstatus; + + pcsstatus = ZYNQ_GEM_PCSSTATUS_LINK | + ZYNQ_GEM_PCSSTATUS_ANEG_COMPL; + ret = wait_for_bit_le32(®s->pcsstatus, + pcsstatus, + true, 5000, true); + if (ret) { + dev_warn(dev, + "no PCS (SGMII) link\n"); + } else { + /* + * Some additional minimal delay seems + * to be needed so that the first + * packet will be sent correctly + */ + mdelay(1); + } + } + } else { writel(readl(®s->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL, ®s->pcscntrl); + } } #endif -- cgit v1.3.1