From 5d867bcc2321041445ebb60d437b818bf706162f Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 9 Dec 2020 10:53:25 +0100 Subject: mtd: spi-nor: add unlock all config option Provide an explicit configuration option to disable default "unlock all" of any flash chip which supports locking. It doesn't make sense to automatically unprotect the entire flash on each u-boot startup if the block protection bits are actually used. Traditionally, the unlock was there to be able to write to flash devices which powered-up with the block protection bits set. Over time this feature creeped into all flash devices which support locking. For a more detailed description and discussion see: https://lore.kernel.org/linux-mtd/20201203162959.29589-8-michael@walle.cc/ Keep things simple in u-boot and just provide a configration option to disable this behavior which can be set per board. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- drivers/mtd/spi/Kconfig | 10 ++++++++++ drivers/mtd/spi/spi-nor-core.c | 9 +++++---- 2 files changed, 15 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index ea444436ad4..f8db8e5213a 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -95,6 +95,16 @@ config SPI_FLASH_BAR Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. +config SPI_FLASH_UNLOCK_ALL + bool "Unlock the entire SPI flash on u-boot startup" + default y + help + Some flashes tend to power up with the software write protection + bits set. If this option is set, the whole flash will be unlocked. + + For legacy reasons, this option default to y. But if you intend to + actually use the software protection bits you should say n here. + config SF_DUAL_FLASH bool "SPI DUAL flash memory support" help diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e16b0e1462d..ef426dac02b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2443,10 +2443,11 @@ static int spi_nor_init(struct spi_nor *nor) * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up * with the software protection bits set */ - if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || - JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || - JEDEC_MFR(nor->info) == SNOR_MFR_SST || - nor->info->flags & SPI_NOR_HAS_LOCK) { + if (IS_ENABLED(CONFIG_SPI_FLASH_UNLOCK_ALL) && + (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || + JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || + JEDEC_MFR(nor->info) == SNOR_MFR_SST || + nor->info->flags & SPI_NOR_HAS_LOCK)) { write_enable(nor); write_sr(nor, 0); spi_nor_wait_till_ready(nor); -- cgit v1.3.1 From 64a0fb4cc35ced6ac83e4177889501782b51891d Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 9 Dec 2020 13:31:58 +0200 Subject: net: memac_phy: add a timeout to MDIO operations We have encountered circumstances when a board design does not include pull-up resistors on the external MDIO buses which are not used. This leads to the MDIO data line not being pulled-up, thus the MDIO controller will always see the line as busy. Without a timeout in the MDIO bus driver, the execution is stuck in an infinite loop when any access is initiated on that external bus. Add a timeout in the driver so that we are protected in this circumstance. This is similar to what is being done in the Linux xgmac_mdio driver. Signed-off-by: Ioana Ciornei Reviewed-by: Madalin Bucur [Rebased] Signed-off-by: Priyanka Jain --- drivers/net/fm/memac_phy.c | 76 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 58 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 8bd32b0ab75..72b500a6d14 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -28,6 +28,8 @@ struct fm_mdio_priv { }; #endif +#define MAX_NUM_RETRIES 1000 + static u32 memac_in_32(u32 *reg) { #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN @@ -37,6 +39,42 @@ static u32 memac_in_32(u32 *reg) #endif } +/* + * Wait until the MDIO bus is free + */ +static int memac_wait_until_free(struct memac_mdio_controller *regs) +{ + unsigned int timeout = MAX_NUM_RETRIES; + + while ((memac_in_32(®s->mdio_stat) & MDIO_STAT_BSY) && timeout--) + ; + + if (!timeout) { + printf("timeout waiting for MDIO bus to be free\n"); + return -ETIMEDOUT; + } + + return 0; +} + +/* + * Wait till the MDIO read or write operation is complete + */ +static int memac_wait_until_done(struct memac_mdio_controller *regs) +{ + unsigned int timeout = MAX_NUM_RETRIES; + + while ((memac_in_32(®s->mdio_data) & MDIO_DATA_BSY) && timeout--) + ; + + if (!timeout) { + printf("timeout waiting for MDIO operation to complete\n"); + return -ETIMEDOUT; + } + + return 0; +} + /* * Write value to the PHY for this device to the register at regnum, waiting * until the write is done before it returns. All PHY configuration has to be @@ -48,6 +86,7 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, struct memac_mdio_controller *regs; u32 mdio_ctl; u32 c45 = 1; /* Default to 10G interface */ + int err; #ifndef CONFIG_DM_ETH regs = bus->priv; @@ -69,9 +108,9 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, } else memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Set the port and dev addr */ mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); @@ -81,16 +120,16 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, if (c45) memac_out_32(®s->mdio_addr, regnum & 0xffff); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Write the value to the register */ memac_out_32(®s->mdio_data, MDIO_DATA(value)); - /* Wait till the MDIO write is complete */ - while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY) - ; + err = memac_wait_until_done(regs); + if (err) + return err; return 0; } @@ -106,6 +145,7 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, struct memac_mdio_controller *regs; u32 mdio_ctl; u32 c45 = 1; + int err; #ifndef CONFIG_DM_ETH regs = bus->priv; @@ -129,9 +169,9 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, } else memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Set the Port and Device Addrs */ mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); @@ -141,17 +181,17 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, if (c45) memac_out_32(®s->mdio_addr, regnum & 0xffff); - /* Wait till the bus is free */ - while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY) - ; + err = memac_wait_until_free(regs); + if (err) + return err; /* Initiate the read */ mdio_ctl |= MDIO_CTL_READ; memac_out_32(®s->mdio_ctl, mdio_ctl); - /* Wait till the MDIO write is complete */ - while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY) - ; + err = memac_wait_until_done(regs); + if (err) + return err; /* Return all Fs if nothing was there */ if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER) -- cgit v1.3.1 From 440b28a8c6045865d7cc6c77ddf21058182e79a6 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 28 Dec 2020 20:15:10 +0800 Subject: net: eqos: Reduce the MDIO wait time Current MDIO wait time is too long, which introduce long delay when PHY negotiation register checking. Reduce it to 10us Signed-off-by: Ye Li Reviewed-by: Fugang Duan Signed-off-by: Peng Fan Reviewed-by: Priyanka Jain --- drivers/net/dwc_eth_qos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 944412958d6..e8242ca4e1b 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -2127,7 +2127,7 @@ static struct eqos_ops eqos_imx_ops = { struct eqos_config __maybe_unused eqos_imx_config = { .reg_access_always_ok = false, - .mdio_wait = 10000, + .mdio_wait = 10, .swr_wait = 50, .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, -- cgit v1.3.1 From 6b4eb604eac8d0dd4f119dcf5523545fc779fafa Mon Sep 17 00:00:00 2001 From: Mathew McBride Date: Mon, 25 Jan 2021 03:55:21 +0000 Subject: spi: fsl_qspi: Ensure width is respected in spi-mem operations Adapted from kernel commit b0177aca7aea From: Michael Walle Make use of a core helper to ensure the desired width is respected when calling spi-mem operators. Otherwise only the SPI controller will be matched with the flash chip, which might lead to wrong widths. Also consider the width specified by the user in the device tree. Fixes: 91afd36f38 ("spi: Add a driver for the Freescale/NXP QuadSPI controller") Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc Signed-off-by: Mark Brown Signed-off-by: Mathew McBride [adapt for U-Boot] Reviewed-by: Priyanka Jain --- drivers/spi/fsl_qspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 8bc7038a82a..2a1f3a0c44f 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -409,7 +409,7 @@ static bool fsl_qspi_supports_op(struct spi_slave *slave, op->data.nbytes > q->devtype_data->txfifo) return false; - return true; + return spi_mem_default_supports_op(slave, op); } static void fsl_qspi_prepare_lut(struct fsl_qspi *q, -- cgit v1.3.1 From fd20097336aa1cbadca9db3cfe7a7681312271bd Mon Sep 17 00:00:00 2001 From: Mathew McBride Date: Mon, 25 Jan 2021 03:55:22 +0000 Subject: spi: fsl_qspi: apply the same settings for LS1088 as LS208x The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL workaround as the LS208x and also has a 64 byte TX buffer. With the previous settings SPI-NAND reads over AHB were corrupted. Fixes: 91afd36f3802 ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API") Signed-off-by: Mathew McBride Reviewed-by: Priyanka Jain --- drivers/spi/fsl_qspi.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 2a1f3a0c44f..f965301d6ac 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -259,14 +259,6 @@ static const struct fsl_qspi_devtype_data ls1021a_data = { .little_endian = false, }; -static const struct fsl_qspi_devtype_data ls1088a_data = { - .rxfifo = SZ_128, - .txfifo = SZ_128, - .ahb_buf_size = SZ_1K, - .quirks = QUADSPI_QUIRK_TKT253890, - .little_endian = true, -}; - static const struct fsl_qspi_devtype_data ls2080a_data = { .rxfifo = SZ_128, .txfifo = SZ_64, @@ -877,7 +869,7 @@ static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, }, { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, }, { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, }, - { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, }, + { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls2080a_data, }, { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, }, { } }; -- cgit v1.3.1 From 584107337b6fd8701586acbca862ef43f7639d19 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 29 Jan 2021 12:47:05 +0800 Subject: pci: layerscape: Remove the shadow SVR definitions This patch moves the SVR definitions to a new svr.h for Layerscape armv7 and armv8 platforms respectively, so that the PCIe driver can reuse them. Signed-off-by: Hou Zhiqiang Reviewed-by: Wasim Khan Reviewed-by: Priyanka Jain --- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 33 +------------------- arch/arm/include/asm/arch-fsl-layerscape/svr.h | 42 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/svr.h | 13 ++++++++ drivers/pci/pcie_layerscape.h | 12 ++------ 4 files changed, 58 insertions(+), 42 deletions(-) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/svr.h create mode 100644 arch/arm/include/asm/arch-ls102xa/svr.h (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 887954eaa52..bd41df1be44 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -16,6 +16,7 @@ #include #endif #endif +#include #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE #define gur_in32(a) in_le32(a) @@ -77,38 +78,6 @@ enum boot_src get_boot_src(void); #endif #endif #define SVR_WO_E 0xFFFFFE -#define SVR_LS1012A 0x870400 -#define SVR_LS1043A 0x879200 -#define SVR_LS1023A 0x879208 -/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ -#define SVR_LS1043A_P23 0x879202 -#define SVR_LS1023A_P23 0x87920A -#define SVR_LS1017A 0x870B24 -#define SVR_LS1018A 0x870B20 -#define SVR_LS1027A 0x870B04 -#define SVR_LS1028A 0x870B00 -#define SVR_LS1046A 0x870700 -#define SVR_LS1026A 0x870708 -#define SVR_LS1048A 0x870320 -#define SVR_LS1084A 0x870302 -#define SVR_LS1088A 0x870300 -#define SVR_LS1044A 0x870322 -#define SVR_LS2045A 0x870120 -#define SVR_LS2080A 0x870110 -#define SVR_LS2085A 0x870100 -#define SVR_LS2040A 0x870130 -#define SVR_LS2088A 0x870900 -#define SVR_LS2084A 0x870910 -#define SVR_LS2048A 0x870920 -#define SVR_LS2044A 0x870930 -#define SVR_LS2081A 0x870918 -#define SVR_LS2041A 0x870914 -#define SVR_LX2160A 0x873600 -#define SVR_LX2120A 0x873620 -#define SVR_LX2080A 0x873602 -#define SVR_LX2162A 0x873608 -#define SVR_LX2122A 0x873628 -#define SVR_LX2082A 0x87360A #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/svr.h b/arch/arm/include/asm/arch-fsl-layerscape/svr.h new file mode 100644 index 00000000000..e37c4a88b54 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/svr.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ + +#define SVR_LS1012A 0x870400 +#define SVR_LS1043A 0x879200 +#define SVR_LS1023A 0x879208 +/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ +#define SVR_LS1043A_P23 0x879202 +#define SVR_LS1023A_P23 0x87920A +#define SVR_LS1017A 0x870B24 +#define SVR_LS1018A 0x870B20 +#define SVR_LS1027A 0x870B04 +#define SVR_LS1028A 0x870B00 +#define SVR_LS1046A 0x870700 +#define SVR_LS1026A 0x870708 +#define SVR_LS1048A 0x870320 +#define SVR_LS1084A 0x870302 +#define SVR_LS1088A 0x870300 +#define SVR_LS1044A 0x870322 +#define SVR_LS2045A 0x870120 +#define SVR_LS2080A 0x870110 +#define SVR_LS2085A 0x870100 +#define SVR_LS2040A 0x870130 +#define SVR_LS2088A 0x870900 +#define SVR_LS2084A 0x870910 +#define SVR_LS2048A 0x870920 +#define SVR_LS2044A 0x870930 +#define SVR_LS2081A 0x870918 +#define SVR_LS2041A 0x870914 +#define SVR_LX2160A 0x873600 +#define SVR_LX2120A 0x873620 +#define SVR_LX2080A 0x873602 +#define SVR_LX2162A 0x873608 +#define SVR_LX2122A 0x873628 +#define SVR_LX2082A 0x87360A + +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/svr.h b/arch/arm/include/asm/arch-ls102xa/svr.h new file mode 100644 index 00000000000..52b27e2d67e --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/svr.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef _ASM_LS102X_SVR_H_ +#define _ASM_LS102X_SVR_H_ + +#define SVR_LS102XA 0 +#define SVR_VAR_PER_SHIFT 8 +#define SVR_LS102XA_MASK 0x700 + +#endif /* _ASM_LS102X_SVR_H_ */ diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 0124e8e0518..8cdf516d9fa 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -10,6 +10,8 @@ #include #include +#include +#include #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE @@ -121,16 +123,6 @@ /* CS2 */ #define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */ -#define SVR_LS102XA 0 -#define SVR_VAR_PER_SHIFT 8 -#define SVR_LS102XA_MASK 0x700 -#define SVR_LS2088A 0x870900 -#define SVR_LS2084A 0x870910 -#define SVR_LS2048A 0x870920 -#define SVR_LS2044A 0x870930 -#define SVR_LS2081A 0x870918 -#define SVR_LS2041A 0x870914 - /* LS1021a PCIE space */ #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL #define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL -- cgit v1.3.1 From d167667d1b9053534445a1c0748a0739fe3aa944 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 29 Jan 2021 13:22:02 +0800 Subject: pci: kconfig: layerscape: Change LX2162A PCIe node compatible string LX2162A is not like LX2160A which has different PCIe controller in rev1 and rev2 silicon. It supports only one configuration of PCIe controller, which is same as LS2088A. So update PCIe compatible string same as LS2088A. Signed-off-by: Hou Zhiqiang Reviewed-by: Wasim Khan Tested-by: Wasim Khan Reviewed-by: Priyanka Jain --- drivers/pci/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index b1de38f7662..ba41787f64d 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -219,7 +219,8 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A - default "fsl,lx2160a-pcie" if ARCH_LX2160A || ARCH_LX2162A + default "fsl,lx2160a-pcie" if ARCH_LX2160A + default "fsl,ls2088a-pcie" if ARCH_LX2162A default "fsl,ls1021a-pcie" if ARCH_LS1021A help This compatible is used to find pci controller node in Kernel DT @@ -228,7 +229,7 @@ config FSL_PCIE_COMPAT config FSL_PCIE_EP_COMPAT string "PCIe EP compatible of Kernel DT" depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4 - default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A || ARCH_LX2162A + default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A default "fsl,ls-pcie-ep" help This compatible is used to find pci controller ep node in Kernel DT -- cgit v1.3.1 From 781188097d392563bce09afeb5bdacd0092b9408 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 5 Feb 2021 19:01:47 +0800 Subject: gpio: mpc8xxx_gpio: Fix for litte endian Update gpio driver to use same logic for big-endian and little-endian Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 10 +++++ arch/arm/include/asm/arch-ls102xa/gpio.h | 16 ++++++++ arch/powerpc/include/asm/immap_83xx.h | 13 ++++++ drivers/gpio/mpc8xxx_gpio.c | 47 ++++------------------ 4 files changed, 47 insertions(+), 39 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index b61666ed4b7..b64d7fbc1b3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -589,5 +589,15 @@ struct ccsr_serdes { u8 res5[0x19fc - 0xa00]; }; +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + #endif /*__ASSEMBLY__ */ #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h index dad181e7abd..517652b5d0f 100644 --- a/arch/arm/include/asm/arch-ls102xa/gpio.h +++ b/arch/arm/include/asm/arch-ls102xa/gpio.h @@ -13,4 +13,20 @@ #ifndef __ASM_ARCH_LS102XA_GPIO_H_ #define __ASM_ARCH_LS102XA_GPIO_H_ +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + +struct mpc8xxx_gpio_plat { + ulong addr; + ulong size; + uint ngpios; +}; + #endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 609869c7154..a03f938d9f4 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -966,6 +966,19 @@ typedef struct immap { } immap_t; #endif +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + union { + u32 gpibe; + u8 res0[0xE8]; + }; +}; + #define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000) #define CONFIG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index a964347fa32..c7336032894 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -6,7 +6,7 @@ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is * * Copyright 2010 eXMeritus, A Boeing Company - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ #include @@ -16,16 +16,6 @@ #include #include -struct ccsr_gpio { - u32 gpdir; - u32 gpodr; - u32 gpdat; - u32 gpier; - u32 gpimr; - u32 gpicr; - u32 gpibe; -}; - struct mpc8xxx_gpio_data { /* The bank's register base in memory */ struct ccsr_gpio __iomem *base; @@ -187,32 +177,11 @@ static int mpc8xxx_gpio_of_to_plat(struct udevice *dev) { struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev); struct mpc8xxx_gpio_data *data = dev_get_priv(dev); - fdt_addr_t addr; - u32 i; - u32 reg[4]; - if (ofnode_read_bool(dev_ofnode(dev), "little-endian")) + if (dev_read_bool(dev, "little-endian")) data->little_endian = true; - if (data->little_endian) - dev_read_u32_array(dev, "reg", reg, 4); - else - dev_read_u32_array(dev, "reg", reg, 2); - - if (data->little_endian) { - for (i = 0; i < 2; i++) - reg[i] = be32_to_cpu(reg[i]); - } - - addr = dev_translate_address(dev, reg); - - plat->addr = addr; - - if (data->little_endian) - plat->size = reg[3]; - else - plat->size = reg[1]; - + plat->addr = (ulong)dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size); plat->ngpios = dev_read_u32_default(dev, "ngpios", 32); return 0; @@ -257,11 +226,11 @@ static int mpc8xxx_gpio_probe(struct udevice *dev) if (!str) return -ENOMEM; - if (ofnode_device_is_compatible(dev_ofnode(dev), "fsl,qoriq-gpio")) { - unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio) - - sizeof(u32); - - out_be32((unsigned int *)gpibe, 0xffffffff); + if (device_is_compatible(dev, "fsl,qoriq-gpio")) { + if (data->little_endian) + out_le32(&data->base->gpibe, 0xffffffff); + else + out_be32(&data->base->gpibe, 0xffffffff); } uc_priv->bank_name = str; -- cgit v1.3.1