From 36c2ee4ce5192f0dd49b9616ba246bdad90e2546 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 21 Jul 2017 23:18:03 +0200 Subject: clk: rmobile: Add RCar Gen3 clock driver Add clock driver for the RCar Gen3 R8A7795 and R8A7796 SoCs . This driver allows reading out the clock configuration set by previous boot stages and enabling and disabling clock using the MSTP registers. Setting clock is not supported thus far. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/renesas/Kconfig | 13 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-rcar-gen3.c | 951 ++++++++++++++++++++++++++++++++++++ 5 files changed, 967 insertions(+) create mode 100644 drivers/clk/renesas/Kconfig create mode 100644 drivers/clk/renesas/Makefile create mode 100644 drivers/clk/renesas/clk-rcar-gen3.c (limited to 'drivers') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 44da716b267..60bd706fa2b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -55,5 +55,6 @@ source "drivers/clk/tegra/Kconfig" source "drivers/clk/uniphier/Kconfig" source "drivers/clk/exynos/Kconfig" source "drivers/clk/at91/Kconfig" +source "drivers/clk/renesas/Kconfig" endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 2746a8016ab..159f285f9a2 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o +obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig new file mode 100644 index 00000000000..07640d1ccf9 --- /dev/null +++ b/drivers/clk/renesas/Kconfig @@ -0,0 +1,13 @@ +config CLK_RENESAS + bool "Renesas clock drivers" + depends on CLK && ARCH_RMOBILE + help + Enable support for clock present on Renesas RCar SoCs. + +config CLK_RCAR_GEN3 + bool "Renesas RCar Gen3 R8A7795/R8A7796 clock driver" + def_bool y if RCAR_GEN3 + depends on CLK_RENESAS + help + Enable this to support the clocks on Renesas RCar Gen3 + R8A7795 and R8A7796 SoC. diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile new file mode 100644 index 00000000000..bd635052bef --- /dev/null +++ b/drivers/clk/renesas/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c new file mode 100644 index 00000000000..5ea7d9a1f5a --- /dev/null +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -0,0 +1,951 @@ +/* + * Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver + * + * Copyright (C) 2017 Marek Vasut + * + * Based on the following driver from Linux kernel: + * r8a7796 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2016 Glider bvba + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define CPG_RST_MODEMR 0x0060 + +#define CPG_PLL0CR 0x00d8 +#define CPG_PLL2CR 0x002c +#define CPG_PLL4CR 0x01f4 + +/* + * Module Standby and Software Reset register offets. + * + * If the registers exist, these are valid for SH-Mobile, R-Mobile, + * R-Car Gen2, R-Car Gen3, and RZ/G1. + * These are NOT valid for R-Car Gen1 and RZ/A1! + */ + +/* + * Module Stop Status Register offsets + */ + +static const u16 mstpsr[] = { + 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, + 0x9A0, 0x9A4, 0x9A8, 0x9AC, +}; + +#define MSTPSR(i) mstpsr[i] + + +/* + * System Module Stop Control Register offsets + */ + +static const u16 smstpcr[] = { + 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, + 0x990, 0x994, 0x998, 0x99C, +}; + +#define SMSTPCR(i) smstpcr[i] + + +/* Realtime Module Stop Control Register offsets */ +#define RMSTPCR(i) (smstpcr[i] - 0x20) + +/* Modem Module Stop Control Register offsets (r8a73a4) */ +#define MMSTPCR(i) (smstpcr[i] + 0x20) + +/* Software Reset Clearing Register offsets */ +#define SRSTCLR(i) (0x940 + (i) * 4) + +struct gen3_clk_priv { + void __iomem *base; + struct clk clk_extal; + struct clk clk_extalr; + const struct rcar_gen3_cpg_pll_config *cpg_pll_config; + const struct mssr_mod_clk *mod_clk; + u32 mod_clk_size; +}; + +/* + * Definitions of CPG Core Clocks + * + * These include: + * - Clock outputs exported to DT + * - External input clocks + * - Internal CPG clocks + */ +struct cpg_core_clk { + /* Common */ + const char *name; + unsigned int id; + unsigned int type; + /* Depending on type */ + unsigned int parent; /* Core Clocks only */ + unsigned int div; + unsigned int mult; + unsigned int offset; +}; + +enum clk_types { + /* Generic */ + CLK_TYPE_IN, /* External Clock Input */ + CLK_TYPE_FF, /* Fixed Factor Clock */ + + /* Custom definitions start here */ + CLK_TYPE_CUSTOM, +}; + +#define DEF_TYPE(_name, _id, _type...) \ + { .name = _name, .id = _id, .type = _type } +#define DEF_BASE(_name, _id, _type, _parent...) \ + DEF_TYPE(_name, _id, _type, .parent = _parent) + +#define DEF_INPUT(_name, _id) \ + DEF_TYPE(_name, _id, CLK_TYPE_IN) +#define DEF_FIXED(_name, _id, _parent, _div, _mult) \ + DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) +#define DEF_GEN3_SD(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) + +/* + * Definitions of Module Clocks + */ +struct mssr_mod_clk { + const char *name; + unsigned int id; + unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */ +}; + +/* Convert from sparse base-100 to packed index space */ +#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32)) + +#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x)) + +#define DEF_MOD(_name, _mod, _parent...) \ + { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent } + +enum rcar_gen3_clk_types { + CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, + CLK_TYPE_GEN3_PLL0, + CLK_TYPE_GEN3_PLL1, + CLK_TYPE_GEN3_PLL2, + CLK_TYPE_GEN3_PLL3, + CLK_TYPE_GEN3_PLL4, + CLK_TYPE_GEN3_SD, + CLK_TYPE_GEN3_R, +}; + +struct rcar_gen3_cpg_pll_config { + unsigned int extal_div; + unsigned int pll1_mult; + unsigned int pll3_mult; +}; + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A7796_CLK_OSC, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL4, + CLK_PLL1_DIV2, + CLK_PLL1_DIV4, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + CLK_SSPSRC, + CLK_RINT, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk gen3_core_clks[] = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), + DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), + DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + + /* Core Clock Outputs */ + DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), + DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1), + DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1), + DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1), + DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1), + DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1), + DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1), + DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1), + DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1), + DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1), + DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1), + DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1), + DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1), + DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1), + DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1), + DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1), + + DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074), + DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078), + DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268), + DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c), + + DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), + + /* NOTE: HDMI, CSI, CAN etc. clock are missing */ + + DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), +}; + +static const struct mssr_mod_clk r8a7795_mod_clks[] = { + DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */ + DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), + DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), + DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), + DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), + DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), + DEF_MOD("scif1", 206, R8A7795_CLK_S3D4), + DEF_MOD("scif0", 207, R8A7795_CLK_S3D4), + DEF_MOD("msiof3", 208, R8A7795_CLK_MSO), + DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), + DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), + DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), + DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3), + DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3), + DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3), + DEF_MOD("cmt3", 300, R8A7795_CLK_R), + DEF_MOD("cmt2", 301, R8A7795_CLK_R), + DEF_MOD("cmt1", 302, R8A7795_CLK_R), + DEF_MOD("cmt0", 303, R8A7795_CLK_R), + DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), + DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), + DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), + DEF_MOD("sdif1", 313, R8A7795_CLK_SD1), + DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), + DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), + DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), + DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1), + DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */ + DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), + DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1), + DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), + DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), + DEF_MOD("rwdt", 402, R8A7795_CLK_R), + DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), + DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), + DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3), + DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3), + DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), + DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), + DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), + DEF_MOD("drif4", 511, R8A7795_CLK_S3D2), + DEF_MOD("drif3", 512, R8A7795_CLK_S3D2), + DEF_MOD("drif2", 513, R8A7795_CLK_S3D2), + DEF_MOD("drif1", 514, R8A7795_CLK_S3D2), + DEF_MOD("drif0", 515, R8A7795_CLK_S3D2), + DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), + DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), + DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), + DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), + DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), + DEF_MOD("thermal", 522, R8A7795_CLK_CP), + DEF_MOD("pwm", 523, R8A7795_CLK_S0D12), + DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */ + DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2), + DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2), + DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2), + DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1), + DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1), + DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */ + DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1), + DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1), + DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */ + DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1), + DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1), + DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */ + DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */ + DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1), + DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */ + DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2), + DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2), + DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2), + DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1), + DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1), + DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ + DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), + DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), + DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4), + DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), + DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), + DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), + DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), + DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4), + DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ + DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), + DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), + DEF_MOD("csi40", 716, R8A7795_CLK_CSI0), + DEF_MOD("du3", 721, R8A7795_CLK_S2D1), + DEF_MOD("du2", 722, R8A7795_CLK_S2D1), + DEF_MOD("du1", 723, R8A7795_CLK_S2D1), + DEF_MOD("du0", 724, R8A7795_CLK_S2D1), + DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), + DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), + DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), + DEF_MOD("vin7", 804, R8A7795_CLK_S0D2), + DEF_MOD("vin6", 805, R8A7795_CLK_S0D2), + DEF_MOD("vin5", 806, R8A7795_CLK_S0D2), + DEF_MOD("vin4", 807, R8A7795_CLK_S0D2), + DEF_MOD("vin3", 808, R8A7795_CLK_S0D2), + DEF_MOD("vin2", 809, R8A7795_CLK_S0D2), + DEF_MOD("vin1", 810, R8A7795_CLK_S0D2), + DEF_MOD("vin0", 811, R8A7795_CLK_S0D2), + DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6), + DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), + DEF_MOD("imr3", 820, R8A7795_CLK_S0D2), + DEF_MOD("imr2", 821, R8A7795_CLK_S0D2), + DEF_MOD("imr1", 822, R8A7795_CLK_S0D2), + DEF_MOD("imr0", 823, R8A7795_CLK_S0D2), + DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4), + DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4), + DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4), + DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4), + DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4), + DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4), + DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4), + DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4), + DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), + DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), + DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), + DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6), + DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6), + DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP), + DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6), + DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6), + DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2), + DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2), + DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2), + DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4), + DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), + DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), + DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), + DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), + DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), + DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), + DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), + DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), + DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), + DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), + DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4), + DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), + DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), + DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), + DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), + DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), + DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), + DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), + DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), + DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), + DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), + DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), + DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), +}; + +static const struct mssr_mod_clk r8a7796_mod_clks[] = { + DEF_MOD("scif5", 202, R8A7796_CLK_S3D4), + DEF_MOD("scif4", 203, R8A7796_CLK_S3D4), + DEF_MOD("scif3", 204, R8A7796_CLK_S3D4), + DEF_MOD("scif1", 206, R8A7796_CLK_S3D4), + DEF_MOD("scif0", 207, R8A7796_CLK_S3D4), + DEF_MOD("msiof3", 208, R8A7796_CLK_MSO), + DEF_MOD("msiof2", 209, R8A7796_CLK_MSO), + DEF_MOD("msiof1", 210, R8A7796_CLK_MSO), + DEF_MOD("msiof0", 211, R8A7796_CLK_MSO), + DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3), + DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3), + DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3), + DEF_MOD("cmt3", 300, R8A7796_CLK_R), + DEF_MOD("cmt2", 301, R8A7796_CLK_R), + DEF_MOD("cmt1", 302, R8A7796_CLK_R), + DEF_MOD("cmt0", 303, R8A7796_CLK_R), + DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), + DEF_MOD("sdif3", 311, R8A7796_CLK_SD3), + DEF_MOD("sdif2", 312, R8A7796_CLK_SD2), + DEF_MOD("sdif1", 313, R8A7796_CLK_SD1), + DEF_MOD("sdif0", 314, R8A7796_CLK_SD0), + DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1), + DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1), + DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1), + DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1), + DEF_MOD("rwdt", 402, R8A7796_CLK_R), + DEF_MOD("intc-ex", 407, R8A7796_CLK_CP), + DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), + DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3), + DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3), + DEF_MOD("drif7", 508, R8A7796_CLK_S3D2), + DEF_MOD("drif6", 509, R8A7796_CLK_S3D2), + DEF_MOD("drif5", 510, R8A7796_CLK_S3D2), + DEF_MOD("drif4", 511, R8A7796_CLK_S3D2), + DEF_MOD("drif3", 512, R8A7796_CLK_S3D2), + DEF_MOD("drif2", 513, R8A7796_CLK_S3D2), + DEF_MOD("drif1", 514, R8A7796_CLK_S3D2), + DEF_MOD("drif0", 515, R8A7796_CLK_S3D2), + DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1), + DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1), + DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1), + DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1), + DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1), + DEF_MOD("thermal", 522, R8A7796_CLK_CP), + DEF_MOD("pwm", 523, R8A7796_CLK_S0D12), + DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2), + DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2), + DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2), + DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1), + DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1), + DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1), + DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2), + DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2), + DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2), + DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2), + DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2), + DEF_MOD("vspb", 626, R8A7796_CLK_S0D1), + DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1), + DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4), + DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4), + DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4), + DEF_MOD("csi20", 714, R8A7796_CLK_CSI0), + DEF_MOD("csi40", 716, R8A7796_CLK_CSI0), + DEF_MOD("du2", 722, R8A7796_CLK_S2D1), + DEF_MOD("du1", 723, R8A7796_CLK_S2D1), + DEF_MOD("du0", 724, R8A7796_CLK_S2D1), + DEF_MOD("lvds", 727, R8A7796_CLK_S2D1), + DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI), + DEF_MOD("vin7", 804, R8A7796_CLK_S0D2), + DEF_MOD("vin6", 805, R8A7796_CLK_S0D2), + DEF_MOD("vin5", 806, R8A7796_CLK_S0D2), + DEF_MOD("vin4", 807, R8A7796_CLK_S0D2), + DEF_MOD("vin3", 808, R8A7796_CLK_S0D2), + DEF_MOD("vin2", 809, R8A7796_CLK_S0D2), + DEF_MOD("vin1", 810, R8A7796_CLK_S0D2), + DEF_MOD("vin0", 811, R8A7796_CLK_S0D2), + DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6), + DEF_MOD("imr1", 822, R8A7796_CLK_S0D2), + DEF_MOD("imr0", 823, R8A7796_CLK_S0D2), + DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4), + DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4), + DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4), + DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4), + DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4), + DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4), + DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4), + DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4), + DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2), + DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4), + DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4), + DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), + DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6), + DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP), + DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6), + DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6), + DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2), + DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2), + DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2), + DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4), + DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), + DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), + DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), + DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), + DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), + DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), + DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), + DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), + DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), + DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), + DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4), + DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), + DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), + DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), + DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), + DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), + DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), + DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), + DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), + DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), + DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), + DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), + DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), +}; + +/* + * CPG Clock Data + */ + +/* + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 + * 14 13 19 17 (MHz) + *------------------------------------------------------------------- + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 + * 0 0 1 0 Prohibited setting + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 + * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 + * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 + * 0 1 1 0 Prohibited setting + * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 + * 1 0 1 0 Prohibited setting + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 + * 1 1 1 0 Prohibited setting + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ + (((md) & BIT(13)) >> 11) | \ + (((md) & BIT(19)) >> 18) | \ + (((md) & BIT(17)) >> 17)) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { + /* EXTAL div PLL1 mult PLL3 mult */ + { 1, 192, 192, }, + { 1, 192, 128, }, + { 0, /* Prohibited setting */ }, + { 1, 192, 192, }, + { 1, 160, 160, }, + { 1, 160, 106, }, + { 0, /* Prohibited setting */ }, + { 1, 160, 160, }, + { 1, 128, 128, }, + { 1, 128, 84, }, + { 0, /* Prohibited setting */ }, + { 1, 128, 128, }, + { 2, 192, 192, }, + { 2, 192, 128, }, + { 0, /* Prohibited setting */ }, + { 2, 192, 192, }, +}; + +/* + * SDn Clock + */ +#define CPG_SD_STP_HCK BIT(9) +#define CPG_SD_STP_CK BIT(8) + +#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK) +#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0) + +#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \ +{ \ + .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \ + ((stp_ck) ? CPG_SD_STP_CK : 0) | \ + ((sd_srcfc) << 2) | \ + ((sd_fc) << 0), \ + .div = (sd_div), \ +} + +struct sd_div_table { + u32 val; + unsigned int div; +}; + +/* SDn divider + * sd_srcfc sd_fc div + * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc + *------------------------------------------------------------------- + * 0 0 0 (1) 1 (4) 4 + * 0 0 1 (2) 1 (4) 8 + * 1 0 2 (4) 1 (4) 16 + * 1 0 3 (8) 1 (4) 32 + * 1 0 4 (16) 1 (4) 64 + * 0 0 0 (1) 0 (2) 2 + * 0 0 1 (2) 0 (2) 4 + * 1 0 2 (4) 0 (2) 8 + * 1 0 3 (8) 0 (2) 16 + * 1 0 4 (16) 0 (2) 32 + */ +static const struct sd_div_table cpg_sd_div_table[] = { +/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */ + CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4), + CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8), + CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16), + CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32), + CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64), + CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2), + CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4), + CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8), + CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16), + CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32), +}; + +static bool gen3_clk_is_mod(struct clk *clk) +{ + return (clk->id >> 16) == CPG_MOD; +} + +static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr) +{ + struct gen3_clk_priv *priv = dev_get_priv(clk->dev); + const unsigned long clkid = clk->id & 0xffff; + int i; + + if (!gen3_clk_is_mod(clk)) + return -EINVAL; + + for (i = 0; i < priv->mod_clk_size; i++) { + if (priv->mod_clk[i].id != MOD_CLK_ID(clkid)) + continue; + + *mssr = &priv->mod_clk[i]; + return 0; + } + + return -ENODEV; +} + +static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core) +{ + const unsigned long clkid = clk->id & 0xffff; + int i; + + if (gen3_clk_is_mod(clk)) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(gen3_core_clks); i++) { + if (gen3_core_clks[i].id != clkid) + continue; + + *core = &gen3_core_clks[i]; + return 0; + } + + return -ENODEV; +} + +static int gen3_clk_get_parent(struct clk *clk, struct clk *parent) +{ + const struct cpg_core_clk *core; + const struct mssr_mod_clk *mssr; + int ret; + + if (gen3_clk_is_mod(clk)) { + ret = gen3_clk_get_mod(clk, &mssr); + if (ret) + return ret; + + parent->id = mssr->parent; + } else { + ret = gen3_clk_get_core(clk, &core); + if (ret) + return ret; + + if (core->type == CLK_TYPE_IN) + parent->id = ~0; /* Top-level clock */ + else + parent->id = core->parent; + } + + parent->dev = clk->dev; + + return 0; +} + +static int gen3_clk_endisable(struct clk *clk, bool enable) +{ + struct gen3_clk_priv *priv = dev_get_priv(clk->dev); + const unsigned long clkid = clk->id & 0xffff; + const unsigned int reg = clkid / 100; + const unsigned int bit = clkid % 100; + const u32 bitmask = BIT(bit); + + if (!gen3_clk_is_mod(clk)) + return -EINVAL; + + debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__, + clkid, reg, bit, enable ? "ON" : "OFF"); + + if (enable) { + clrbits_le32(priv->base + SMSTPCR(reg), bitmask); + return wait_for_bit("MSTP", priv->base + MSTPSR(reg), + bitmask, 0, 100, 0); + } else { + setbits_le32(priv->base + SMSTPCR(reg), bitmask); + return 0; + } +} + +static int gen3_clk_enable(struct clk *clk) +{ + return gen3_clk_endisable(clk, true); +} + +static int gen3_clk_disable(struct clk *clk) +{ + return gen3_clk_endisable(clk, false); +} + +static ulong gen3_clk_get_rate(struct clk *clk) +{ + struct gen3_clk_priv *priv = dev_get_priv(clk->dev); + struct clk parent; + const struct cpg_core_clk *core; + const struct rcar_gen3_cpg_pll_config *pll_config = + priv->cpg_pll_config; + u32 value, mult, rate = 0; + int i, ret; + + debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id); + + ret = gen3_clk_get_parent(clk, &parent); + if (ret) { + printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); + return ret; + } + + if (gen3_clk_is_mod(clk)) { + rate = gen3_clk_get_rate(&parent); + debug("%s[%i] MOD clk: parent=%lu => rate=%u\n", + __func__, __LINE__, parent.id, rate); + return rate; + } + + ret = gen3_clk_get_core(clk, &core); + if (ret) + return ret; + + switch (core->type) { + case CLK_TYPE_IN: + if (core->id == CLK_EXTAL) { + rate = clk_get_rate(&priv->clk_extal); + debug("%s[%i] EXTAL clk: rate=%u\n", + __func__, __LINE__, rate); + return rate; + } + + if (core->id == CLK_EXTALR) { + rate = clk_get_rate(&priv->clk_extalr); + debug("%s[%i] EXTALR clk: rate=%u\n", + __func__, __LINE__, rate); + return rate; + } + + return -EINVAL; + + case CLK_TYPE_GEN3_MAIN: + rate = gen3_clk_get_rate(&parent) / pll_config->extal_div; + debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n", + __func__, __LINE__, + core->parent, pll_config->extal_div, rate); + return rate; + + case CLK_TYPE_GEN3_PLL0: + value = readl(priv->base + CPG_PLL0CR); + mult = (((value >> 24) & 0x7f) + 1) * 2; + rate = gen3_clk_get_rate(&parent) * mult; + debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n", + __func__, __LINE__, core->parent, mult, rate); + return rate; + + case CLK_TYPE_GEN3_PLL1: + rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult; + debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n", + __func__, __LINE__, + core->parent, pll_config->pll1_mult, rate); + return rate; + + case CLK_TYPE_GEN3_PLL2: + value = readl(priv->base + CPG_PLL2CR); + mult = (((value >> 24) & 0x7f) + 1) * 2; + rate = gen3_clk_get_rate(&parent) * mult; + debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n", + __func__, __LINE__, core->parent, mult, rate); + return rate; + + case CLK_TYPE_GEN3_PLL3: + rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult; + debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n", + __func__, __LINE__, + core->parent, pll_config->pll3_mult, rate); + return rate; + + case CLK_TYPE_GEN3_PLL4: + value = readl(priv->base + CPG_PLL4CR); + mult = (((value >> 24) & 0x7f) + 1) * 2; + rate = gen3_clk_get_rate(&parent) * mult; + debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n", + __func__, __LINE__, core->parent, mult, rate); + return rate; + + case CLK_TYPE_FF: + rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div; + debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n", + __func__, __LINE__, + core->parent, core->mult, core->div, rate); + return rate; + + case CLK_TYPE_GEN3_SD: /* FIXME */ + value = readl(priv->base + core->offset); + value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK; + + for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) { + if (cpg_sd_div_table[i].val != value) + continue; + + rate = gen3_clk_get_rate(&parent) / + cpg_sd_div_table[i].div; + debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n", + __func__, __LINE__, + core->parent, cpg_sd_div_table[i].div, rate); + + return rate; + } + + return -EINVAL; + } + + printf("%s[%i] unknown fail\n", __func__, __LINE__); + + return -ENOENT; +} + +static ulong gen3_clk_set_rate(struct clk *clk, ulong rate) +{ + return gen3_clk_get_rate(clk); +} + +static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) +{ + if (args->args_count != 2) { + debug("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + clk->id = (args->args[0] << 16) | args->args[1]; + + return 0; +} + +static const struct clk_ops gen3_clk_ops = { + .enable = gen3_clk_enable, + .disable = gen3_clk_disable, + .get_rate = gen3_clk_get_rate, + .set_rate = gen3_clk_set_rate, + .of_xlate = gen3_clk_of_xlate, +}; + +enum gen3_clk_model { + CLK_R8A7795, + CLK_R8A7796, +}; + +static int gen3_clk_probe(struct udevice *dev) +{ + struct gen3_clk_priv *priv = dev_get_priv(dev); + enum gen3_clk_model model = dev_get_driver_data(dev); + fdt_addr_t rst_base; + u32 cpg_mode; + int ret; + + priv->base = (struct gen3_base *)devfdt_get_addr(dev); + if (!priv->base) + return -EINVAL; + + switch (model) { + case CLK_R8A7795: + priv->mod_clk = r8a7795_mod_clks; + priv->mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks); + ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, + "renesas,r8a7795-rst"); + if (ret < 0) + return ret; + break; + case CLK_R8A7796: + priv->mod_clk = r8a7796_mod_clks; + priv->mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks); + ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, + "renesas,r8a7796-rst"); + if (ret < 0) + return ret; + break; + default: + return -EINVAL; + } + + rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg"); + if (rst_base == FDT_ADDR_T_NONE) + return -EINVAL; + + cpg_mode = readl(rst_base + CPG_RST_MODEMR); + + priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (!priv->cpg_pll_config->extal_div) + return -EINVAL; + + ret = clk_get_by_name(dev, "extal", &priv->clk_extal); + if (ret < 0) + return ret; + + ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr); + if (ret < 0) + return ret; + + return 0; +} + +static const struct udevice_id gen3_clk_ids[] = { + { .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 }, + { .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 }, + { } +}; + +U_BOOT_DRIVER(clk_gen3) = { + .name = "clk_gen3", + .id = UCLASS_CLK, + .of_match = gen3_clk_ids, + .priv_auto_alloc_size = sizeof(struct gen3_clk_priv), + .ops = &gen3_clk_ops, + .probe = gen3_clk_probe, +}; -- cgit v1.3.1 From 03a38a397248529b01908eaed24f9262545ca9b5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 21 Jul 2017 23:18:46 +0200 Subject: serial: sh: Convert to Kconfig Convert the SH Serial to Kconfig using tools/moveconfig.py tool and a bit of manual adjustment to cater for failed conversions. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- configs/MigoR_defconfig | 1 + configs/alt_defconfig | 1 + configs/ap325rxa_defconfig | 1 + configs/ap_sh4a_4a_defconfig | 1 + configs/armadillo-800eva_defconfig | 1 + configs/blanche_defconfig | 1 + configs/ecovec_defconfig | 1 + configs/espt_defconfig | 1 + configs/gose_defconfig | 1 + configs/koelsch_defconfig | 1 + configs/kzm9g_defconfig | 1 + configs/lager_defconfig | 1 + configs/mpr2_defconfig | 1 + configs/ms7720se_defconfig | 1 + configs/ms7722se_defconfig | 1 + configs/ms7750se_defconfig | 1 + configs/porter_defconfig | 1 + configs/r0p7734_defconfig | 1 + configs/r2dplus_defconfig | 1 + configs/r7780mp_defconfig | 1 + configs/r8a7795_salvator-x_defconfig | 1 + configs/r8a7795_ulcb_defconfig | 1 + configs/r8a7796_salvator-x_defconfig | 1 + configs/r8a7796_ulcb_defconfig | 1 + configs/rsk7203_defconfig | 1 + configs/rsk7264_defconfig | 1 + configs/rsk7269_defconfig | 1 + configs/sh7752evb_defconfig | 1 + configs/sh7753evb_defconfig | 1 + configs/sh7757lcr_defconfig | 1 + configs/sh7763rdp_defconfig | 1 + configs/sh7785lcr_32bit_defconfig | 1 + configs/sh7785lcr_defconfig | 1 + configs/shmin_defconfig | 1 + configs/silk_defconfig | 1 + configs/stout_defconfig | 1 + drivers/serial/Kconfig | 8 ++++++++ include/configs/MigoR.h | 1 - include/configs/alt.h | 1 - include/configs/ap325rxa.h | 1 - include/configs/ap_sh4a_4a.h | 1 - include/configs/armadillo-800eva.h | 1 - include/configs/blanche.h | 1 - include/configs/ecovec.h | 1 - include/configs/espt.h | 1 - include/configs/gose.h | 1 - include/configs/koelsch.h | 1 - include/configs/kzm9g.h | 1 - include/configs/lager.h | 1 - include/configs/mpr2.h | 1 - include/configs/ms7720se.h | 1 - include/configs/ms7722se.h | 1 - include/configs/ms7750se.h | 1 - include/configs/porter.h | 1 - include/configs/r0p7734.h | 1 - include/configs/r2dplus.h | 1 - include/configs/r7780mp.h | 1 - include/configs/rsk7203.h | 1 - include/configs/rsk7264.h | 1 - include/configs/rsk7269.h | 1 - include/configs/salvator-x.h | 1 - include/configs/sh7752evb.h | 1 - include/configs/sh7753evb.h | 1 - include/configs/sh7757lcr.h | 1 - include/configs/sh7763rdp.h | 1 - include/configs/sh7785lcr.h | 1 - include/configs/shmin.h | 1 - include/configs/silk.h | 1 - include/configs/stout.h | 1 - include/configs/ulcb.h | 1 - scripts/config_whitelist.txt | 1 - 71 files changed, 44 insertions(+), 34 deletions(-) (limited to 'drivers') diff --git a/configs/MigoR_defconfig b/configs/MigoR_defconfig index 091045f6a34..b8e2da2678e 100644 --- a/configs/MigoR_defconfig +++ b/configs/MigoR_defconfig @@ -20,4 +20,5 @@ CONFIG_VERSION_VARIABLE=y CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 84f6f12b3e9..109b1abfe7b 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -25,6 +25,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/ap325rxa_defconfig b/configs/ap325rxa_defconfig index ebefe3cdb32..8c1aaf2c3c3 100644 --- a/configs/ap325rxa_defconfig +++ b/configs/ap325rxa_defconfig @@ -24,4 +24,5 @@ CONFIG_CMD_EXT2=y CONFIG_DOS_PARTITION=y CONFIG_MTD_NOR_FLASH=y CONFIG_BAUDRATE=38400 +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/ap_sh4a_4a_defconfig b/configs/ap_sh4a_4a_defconfig index c08ae4f3eb7..400cfd10a75 100644 --- a/configs/ap_sh4a_4a_defconfig +++ b/configs/ap_sh4a_4a_defconfig @@ -23,4 +23,5 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig index c5a652457ff..8b2448b1fcf 100644 --- a/configs/armadillo-800eva_defconfig +++ b/configs/armadillo-800eva_defconfig @@ -27,4 +27,5 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set # CONFIG_MMC is not set +CONFIG_SCIF_CONSOLE=y CONFIG_OF_LIBFDT=y diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index ccd0d8f0da6..c2a4c8092f1 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -21,3 +21,4 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 +CONFIG_SCIF_CONSOLE=y diff --git a/configs/ecovec_defconfig b/configs/ecovec_defconfig index 7fb14ab9de5..532b22d3be2 100644 --- a/configs/ecovec_defconfig +++ b/configs/ecovec_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/espt_defconfig b/configs/espt_defconfig index a7f50efc459..a41704ec967 100644 --- a/configs/espt_defconfig +++ b/configs/espt_defconfig @@ -23,4 +23,5 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index b579826fe45..12b768ca392 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -25,6 +25,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index a28326b456f..e6eef3f7314 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -25,6 +25,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig index 0ee7f4bb80a..ac21f979b9e 100644 --- a/configs/kzm9g_defconfig +++ b/configs/kzm9g_defconfig @@ -14,5 +14,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y # CONFIG_FAT_WRITE is not set CONFIG_OF_LIBFDT=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index f4c4389075c..ca4f73d04f6 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -25,6 +25,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/mpr2_defconfig b/configs/mpr2_defconfig index ea332370037..efa0f7fe1c0 100644 --- a/configs/mpr2_defconfig +++ b/configs/mpr2_defconfig @@ -23,4 +23,5 @@ CONFIG_VERSION_VARIABLE=y CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/ms7720se_defconfig b/configs/ms7720se_defconfig index 30e52692d0e..7f137fa911a 100644 --- a/configs/ms7720se_defconfig +++ b/configs/ms7720se_defconfig @@ -27,3 +27,4 @@ CONFIG_CMD_EXT2=y CONFIG_DOS_PARTITION=y CONFIG_MTD_NOR_FLASH=y CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SCIF_CONSOLE=y diff --git a/configs/ms7722se_defconfig b/configs/ms7722se_defconfig index 633a087616d..37cf8776c22 100644 --- a/configs/ms7722se_defconfig +++ b/configs/ms7722se_defconfig @@ -23,4 +23,5 @@ CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_CMD_JFFS2=y CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/ms7750se_defconfig b/configs/ms7750se_defconfig index 9fabcd90598..402be860606 100644 --- a/configs/ms7750se_defconfig +++ b/configs/ms7750se_defconfig @@ -24,4 +24,5 @@ CONFIG_BOOTDELAY=-1 # CONFIG_CMD_MISC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_BAUDRATE=38400 +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index d74a954615e..e90fbf11374 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -25,6 +25,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/r0p7734_defconfig b/configs/r0p7734_defconfig index a6f6a9324d7..91b36058bc7 100644 --- a/configs/r0p7734_defconfig +++ b/configs/r0p7734_defconfig @@ -23,4 +23,5 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig index 32a12720c97..31b9cc4f5b6 100644 --- a/configs/r2dplus_defconfig +++ b/configs/r2dplus_defconfig @@ -12,4 +12,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y CONFIG_RTL8139=y CONFIG_PCI=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/r7780mp_defconfig b/configs/r7780mp_defconfig index c5fa3f3b36e..a46954d3c31 100644 --- a/configs/r7780mp_defconfig +++ b/configs/r7780mp_defconfig @@ -25,4 +25,5 @@ CONFIG_CMD_EXT2=y CONFIG_DOS_PARTITION=y CONFIG_MTD_NOR_FLASH=y CONFIG_PCI=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index bd64ae76c44..3d67ff41d21 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -20,6 +20,7 @@ CONFIG_CLK_RENESAS=y CONFIG_SH_SDHI=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index ebe5cffab87..dfd5be1b352 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -18,6 +18,7 @@ CONFIG_CLK_RENESAS=y CONFIG_SH_SDHI=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index b408cb0e5cd..1fd4505ad2d 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -21,6 +21,7 @@ CONFIG_CLK_RENESAS=y CONFIG_SH_SDHI=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index d7c4cf3535a..b5443c0035a 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -19,6 +19,7 @@ CONFIG_CLK_RENESAS=y CONFIG_SH_SDHI=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/rsk7203_defconfig b/configs/rsk7203_defconfig index 1aeb78aad14..f7b99f48420 100644 --- a/configs/rsk7203_defconfig +++ b/configs/rsk7203_defconfig @@ -22,4 +22,5 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/rsk7264_defconfig b/configs/rsk7264_defconfig index b07e48c68be..f1999b53e51 100644 --- a/configs/rsk7264_defconfig +++ b/configs/rsk7264_defconfig @@ -3,4 +3,5 @@ CONFIG_TARGET_RSK7264=y CONFIG_BOOTDELAY=3 # CONFIG_CMD_SETEXPR is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/rsk7269_defconfig b/configs/rsk7269_defconfig index ed4fe21f949..4a07af61801 100644 --- a/configs/rsk7269_defconfig +++ b/configs/rsk7269_defconfig @@ -3,4 +3,5 @@ CONFIG_TARGET_RSK7269=y CONFIG_BOOTDELAY=3 # CONFIG_CMD_SETEXPR is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig index 1271ea03564..124757353bf 100644 --- a/configs/sh7752evb_defconfig +++ b/configs/sh7752evb_defconfig @@ -32,4 +32,5 @@ CONFIG_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig index 06a95bcde9c..68e0c5cdfb5 100644 --- a/configs/sh7753evb_defconfig +++ b/configs/sh7753evb_defconfig @@ -31,4 +31,5 @@ CONFIG_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig index 09ed1b3affd..d43c0184e46 100644 --- a/configs/sh7757lcr_defconfig +++ b/configs/sh7757lcr_defconfig @@ -31,4 +31,5 @@ CONFIG_DOS_PARTITION=y CONFIG_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sh7763rdp_defconfig b/configs/sh7763rdp_defconfig index 9334f6bdec4..32cc565b5e8 100644 --- a/configs/sh7763rdp_defconfig +++ b/configs/sh7763rdp_defconfig @@ -24,4 +24,5 @@ CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_CMD_JFFS2=y CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sh7785lcr_32bit_defconfig b/configs/sh7785lcr_32bit_defconfig index 59e6067209f..675c4eb6784 100644 --- a/configs/sh7785lcr_32bit_defconfig +++ b/configs/sh7785lcr_32bit_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_FAT=y CONFIG_MAC_PARTITION=y CONFIG_MTD_NOR_FLASH=y CONFIG_PCI=y +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sh7785lcr_defconfig b/configs/sh7785lcr_defconfig index cf9c305bc35..d118fd4f5d5 100644 --- a/configs/sh7785lcr_defconfig +++ b/configs/sh7785lcr_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_FAT=y CONFIG_MAC_PARTITION=y CONFIG_MTD_NOR_FLASH=y CONFIG_PCI=y +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/shmin_defconfig b/configs/shmin_defconfig index dffff1187bd..249582f4958 100644 --- a/configs/shmin_defconfig +++ b/configs/shmin_defconfig @@ -21,4 +21,5 @@ CONFIG_VERSION_VARIABLE=y CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_SCIF_CONSOLE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index cf20114d3b3..d2d20b9b96f 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -25,6 +25,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index 063b33ca72f..bee7401d799 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -25,6 +25,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 +CONFIG_SCIF_CONSOLE=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 2582c954f2a..a8e997834ad 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -464,6 +464,14 @@ config SANDBOX_SERIAL -t raw Raw mode, Ctrl-C is processed by U-Boot -t cooked Cooked mode, Ctrl-C terminates +config SCIF_CONSOLE + bool "Renesas SCIF UART support" + depends on SH || ARCH_RMOBILE + help + Select this to enable Renesas SCIF UART. To operate serial ports + on systems with RCar or SH SoCs, say Y to this option. If unsure, + say N. + config UNIPHIER_SERIAL bool "Support for UniPhier on-chip UART" depends on ARCH_UNIPHIER diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index 5ee83b90346..73b0e6e05a8 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -37,7 +37,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 #define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE) diff --git a/include/configs/alt.h b/include/configs/alt.h index 16525087f18..a61814ef009 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -37,7 +37,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ -#define CONFIG_SCIF_CONSOLE /* FLASH */ #define CONFIG_SPI diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h index 285041dbf83..448c9279a9d 100644 --- a/include/configs/ap325rxa.h +++ b/include/configs/ap325rxa.h @@ -47,7 +47,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 38400 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */ #define CONFIG_CONS_SCIF5 1 diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h index 078c77bf68c..adc7d1feba9 100644 --- a/include/configs/ap_sh4a_4a.h +++ b/include/configs/ap_sh4a_4a.h @@ -49,7 +49,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_SCIF 1 #define CONFIG_CONS_SCIF4 1 diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 492062abb35..643b26b4880 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -46,7 +46,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF1 #define SCIF0_BASE 0xe6c40000 #define SCIF1_BASE 0xe6c50000 diff --git a/include/configs/blanche.h b/include/configs/blanche.h index 9a18046d9ce..cdff96685b4 100755 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -28,7 +28,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ -#define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF0 #define CONFIG_SYS_MEMTEST_START (RCAR_GEN2_SDRAM_BASE) diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h index cabbe160a37..2471277c68b 100644 --- a/include/configs/ecovec.h +++ b/include/configs/ecovec.h @@ -81,7 +81,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_SCIF 1 #define CONFIG_CONS_SCIF0 1 diff --git a/include/configs/espt.h b/include/configs/espt.h index 1b3295346d8..07f327532ba 100644 --- a/include/configs/espt.h +++ b/include/configs/espt.h @@ -26,7 +26,6 @@ #undef CONFIG_SHOW_BOOT_PROGRESS /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 diff --git a/include/configs/gose.h b/include/configs/gose.h index 8a1d6d3407f..067e86d41cf 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -38,7 +38,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000 /* SCIF */ -#define CONFIG_SCIF_CONSOLE /* FLASH */ #define CONFIG_SPI diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 2166e2c8f23..988b747cbc9 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -38,7 +38,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ -#define CONFIG_SCIF_CONSOLE /* FLASH */ #define CONFIG_SPI diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index f4349913143..6f60c7c2c30 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -49,7 +49,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF4 #define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE) diff --git a/include/configs/lager.h b/include/configs/lager.h index bf1352d941e..73ea9ac828d 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -38,7 +38,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ -#define CONFIG_SCIF_CONSOLE /* SPI */ #define CONFIG_SPI diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h index 5b37277ccea..30395d5b7e6 100644 --- a/include/configs/mpr2.h +++ b/include/configs/mpr2.h @@ -64,7 +64,6 @@ #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ /* UART */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 #endif /* __MPR2_H */ diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h index 850a8cc2226..86b93a39bb1 100644 --- a/include/configs/ms7720se.h +++ b/include/configs/ms7720se.h @@ -38,7 +38,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 #define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index f456bf62931..49eadd10e99 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -37,7 +37,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 #define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE) diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index 8ea431efdc1..497b8c785fc 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -20,7 +20,6 @@ /* * Command line configuration. */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF1 1 #define CONFIG_BOOTARGS "console=ttySC0,38400" diff --git a/include/configs/porter.h b/include/configs/porter.h index ac21411178e..fa1fff98296 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -38,7 +38,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) /* SCIF */ -#define CONFIG_SCIF_CONSOLE /* FLASH */ #define CONFIG_SPI diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h index 5f74b2a0e08..d79aa21c9e6 100644 --- a/include/configs/r0p7734.h +++ b/include/configs/r0p7734.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_SCIF 1 #define CONFIG_CONS_SCIF3 1 diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 64fd4b97a06..7f1f115ff6e 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -15,7 +15,6 @@ #define CONFIG_CMD_SH_ZIMAGEBOOT /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF1 1 #define CONFIG_BOOTARGS "console=ttySC0,115200" diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index c5f577a3bfb..14390e81fbc 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -23,7 +23,6 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_PCI -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 #define CONFIG_BOOTARGS "console=ttySC0,115200" diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h index 8f30aefc41f..58aadbef015 100644 --- a/include/configs/rsk7203.h +++ b/include/configs/rsk7203.h @@ -37,7 +37,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 #define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h index 14e55c579d4..f2e82f7daaf 100644 --- a/include/configs/rsk7264.h +++ b/include/configs/rsk7264.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ /* Serial */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF3 1 /* Memory */ diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h index 60844ab738d..5dc87a63d7f 100644 --- a/include/configs/rsk7269.h +++ b/include/configs/rsk7269.h @@ -24,7 +24,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Serial */ -#define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF7 /* Memory */ diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 7f81063d13b..f8bfe96781e 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -17,7 +17,6 @@ #include "rcar-gen3-common.h" /* SCIF */ -#define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF2 #define CONFIG_CONS_INDEX 2 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index 46d0f2aede9..39e8244b252 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -35,7 +35,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF2 1 #define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE) diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index aa8d05c2210..24ec0768afa 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -35,7 +35,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF2 1 #define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE) diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index 1759a6f5d9e..e5084adfccb 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -36,7 +36,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF2 1 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index 50a0e3e7d1f..74bd9fc29ab 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -26,7 +26,6 @@ #undef CONFIG_SHOW_BOOT_PROGRESS /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF2 1 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h index 59fcad03098..48a77197fd9 100644 --- a/include/configs/sh7785lcr.h +++ b/include/configs/sh7785lcr.h @@ -53,7 +53,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF1 1 #define CONFIG_SCIF_EXT_CLOCK 1 diff --git a/include/configs/shmin.h b/include/configs/shmin.h index c9718f9b36e..d31dc558b1f 100644 --- a/include/configs/shmin.h +++ b/include/configs/shmin.h @@ -41,7 +41,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600,14400,19200,38400,57600,115200 } /* SCIF */ -#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 /* memory */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 84108fd5235..238783b4c44 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -38,7 +38,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ -#define CONFIG_SCIF_CONSOLE /* FLASH */ #define CONFIG_SPI diff --git a/include/configs/stout.h b/include/configs/stout.h index 16f3ce86474..3b8806d065f 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -40,7 +40,6 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ -#define CONFIG_SCIF_CONSOLE #define CONFIG_SCIF_A /* SPI */ diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index 857fc9f8cf3..921b9e5ec66 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -25,7 +25,6 @@ #endif /* SCIF */ -#define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF2 #define CONFIG_CONS_INDEX 2 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e630314926a..3b5c17a9825 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2023,7 +2023,6 @@ CONFIG_SBC8641D CONFIG_SCF0403_LCD CONFIG_SCIF CONFIG_SCIF_A -CONFIG_SCIF_CONSOLE CONFIG_SCIF_EXT_CLOCK CONFIG_SCIF_USE_EXT_CLK CONFIG_SCSI_AHCI -- cgit v1.3.1 From 8171499df99884e770430346698d7045c777a46b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 21 Jul 2017 23:19:18 +0200 Subject: serial: sh: Use the clock framework to obtain clock config Since we now have clock driver on the RCar Gen3 , obtain the clock configuration using the clock framework functions. In case this fails, fall back to the original code for pulling the clock config directly out of OF. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- drivers/serial/serial_sh.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 51f7fbcfb79..087785f9a24 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -214,15 +215,23 @@ static const struct udevice_id sh_serial_id[] ={ static int sh_serial_ofdata_to_platdata(struct udevice *dev) { struct sh_serial_platdata *plat = dev_get_platdata(dev); + struct clk sh_serial_clk; fdt_addr_t addr; + int ret; addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg"); if (addr == FDT_ADDR_T_NONE) return -EINVAL; plat->base = addr; - plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock", - 1); + + ret = clk_get_by_name(dev, "fck", &sh_serial_clk); + if (!ret) + plat->clk = clk_get_rate(&sh_serial_clk); + else + plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "clock", 1); + plat->type = dev_get_driver_data(dev); return 0; } -- cgit v1.3.1 From 5ee8b4d7f5e52e2ace15ca6bfbb35593d908af0f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 21 Jul 2017 23:20:33 +0200 Subject: net: ravb: Add OF probing support Add support for probing the RAVB Ethernet block from device tree. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Nobuhiro Iwamatsu Acked-by: Joe Hershberger Signed-off-by: Nobuhiro Iwamatsu --- drivers/net/ravb.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'drivers') diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index ab45a31d6a6..7f0e2568b76 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -589,9 +589,46 @@ static const struct eth_ops ravb_ops = { .write_hwaddr = ravb_write_hwaddr, }; +int ravb_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + const char *phy_mode; + const fdt32_t *cell; + int ret = 0; + + pdata->iobase = devfdt_get_addr(dev); + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", + NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + pdata->max_speed = 1000; + cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); + if (cell) + pdata->max_speed = fdt32_to_cpu(*cell); + + sprintf(bb_miiphy_buses[0].name, dev->name); + + return ret; +} + +static const struct udevice_id ravb_ids[] = { + { .compatible = "renesas,etheravb-r8a7795" }, + { .compatible = "renesas,etheravb-r8a7796" }, + { .compatible = "renesas,etheravb-rcar-gen3" }, + { } +}; + U_BOOT_DRIVER(eth_ravb) = { .name = "ravb", .id = UCLASS_ETH, + .of_match = ravb_ids, + .ofdata_to_platdata = ravb_ofdata_to_platdata, .probe = ravb_probe, .remove = ravb_remove, .ops = &ravb_ops, -- cgit v1.3.1 From e821a7bdb13435eace82e907363dc59be56f139a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 21 Jul 2017 23:20:34 +0200 Subject: net: ravb: Detect PHY correctly The order of parameters passed to the phy_connect() was wrong. Moreover, only PHY address 0 was used. Replace this with code capable of detecting the PHY address. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Nobuhiro Iwamatsu Acked-by: Joe Hershberger Signed-off-by: Nobuhiro Iwamatsu --- drivers/net/ravb.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 7f0e2568b76..ce0eacceb60 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -298,13 +298,14 @@ static int ravb_phy_config(struct udevice *dev) struct ravb_priv *eth = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_platdata(dev); struct phy_device *phydev; - int reg; + int mask = 0xffffffff, reg; - phydev = phy_connect(eth->bus, pdata->phy_interface, - dev, PHY_INTERFACE_MODE_RGMII_ID); + phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface); if (!phydev) return -ENODEV; + phy_connect_dev(phydev, dev); + eth->phydev = phydev; /* 10BASE is not supported for Ethernet AVB MAC */ -- cgit v1.3.1 From 1fea9e25faca9d72a52b7da1587b90153fde6239 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 21 Jul 2017 23:20:35 +0200 Subject: net: ravb: Add clock handling support Add support for enabling and disabling the clock using the clock framework based on the content of OF instead of doing it manually in the board file. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Nobuhiro Iwamatsu Acked-by: Joe Hershberger Signed-off-by: Nobuhiro Iwamatsu --- drivers/net/ravb.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index ce0eacceb60..8db127ba06f 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -120,6 +121,7 @@ struct ravb_priv { struct phy_device *phydev; struct mii_dev *bus; void __iomem *iobase; + struct clk clk; }; static inline void ravb_flush_dcache(u32 addr, u32 len) @@ -432,27 +434,38 @@ int ravb_start(struct udevice *dev) struct ravb_priv *eth = dev_get_priv(dev); int ret; - ret = ravb_reset(dev); + ret = clk_enable(ð->clk); if (ret) return ret; + ret = ravb_reset(dev); + if (ret) + goto err; + ravb_base_desc_init(eth); ravb_tx_desc_init(eth); ravb_rx_desc_init(eth); ret = ravb_config(dev); if (ret) - return ret; + goto err; /* Setting the control will start the AVB-DMAC process. */ writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC); return 0; + +err: + clk_disable(ð->clk); + return ret; } static void ravb_stop(struct udevice *dev) { + struct ravb_priv *eth = dev_get_priv(dev); + ravb_reset(dev); + clk_disable(ð->clk); } static int ravb_probe(struct udevice *dev) @@ -466,6 +479,10 @@ static int ravb_probe(struct udevice *dev) iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE); eth->iobase = iobase; + ret = clk_get_by_index(dev, 0, ð->clk); + if (ret < 0) + goto err_mdio_alloc; + mdiodev = mdio_alloc(); if (!mdiodev) { ret = -ENOMEM; -- cgit v1.3.1