From e5bc97578c189a99c291f7fe7ce89092474e43e9 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 29 Dec 2014 19:32:22 -0700
Subject: bios_emulator: Fix an #ifdef typo in the header file

This stops the debug mode from working properly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 drivers/bios_emulator/include/x86emu/debug.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/drivers/bios_emulator/include/x86emu/debug.h b/drivers/bios_emulator/include/x86emu/debug.h
index 304b2bf0070..4962a2acaf1 100644
--- a/drivers/bios_emulator/include/x86emu/debug.h
+++ b/drivers/bios_emulator/include/x86emu/debug.h
@@ -102,7 +102,7 @@
 # define ERR_PRINTF(x)		printf(x)
 # define ERR_PRINTF2(x, y)	printf(x, y)
 
-#ifdef CONFIG_X86EMU_DEBUG103
+#ifdef CONFIG_X86EMU_DEBUG
 
 
 # define DECODE_PRINTF(x)	if (DEBUG_DECODE()) \
-- 
cgit v1.3.1


From 40305240c66ab5e3725c131e321402c7dfe687a2 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 29 Dec 2014 19:32:23 -0700
Subject: x86: Correct endianness isues in pci_rom

This code is too x86-dependent at present. Correct it so that it can run on
big-endian machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 drivers/pci/pci_rom.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

(limited to 'drivers')

diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 7d25cc9f2f3..86f0e95cd5a 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -66,6 +66,7 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
 	struct pci_rom_header *rom_header;
 	struct pci_rom_data *rom_data;
 	u16 vendor, device;
+	u16 rom_vendor, rom_device;
 	u32 vendev;
 	u32 mapped_vendev;
 	u32 rom_address;
@@ -95,25 +96,27 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
 	rom_header = (struct pci_rom_header *)rom_address;
 
 	debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n",
-	      le32_to_cpu(rom_header->signature),
-	      rom_header->size * 512, le32_to_cpu(rom_header->data));
+	      le16_to_cpu(rom_header->signature),
+	      rom_header->size * 512, le16_to_cpu(rom_header->data));
 
-	if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
+	if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
 		printf("Incorrect expansion ROM header signature %04x\n",
-		       le32_to_cpu(rom_header->signature));
+		       le16_to_cpu(rom_header->signature));
 		return -EINVAL;
 	}
 
-	rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data));
+	rom_data = (((void *)rom_header) + le16_to_cpu(rom_header->data));
+	rom_vendor = le16_to_cpu(rom_data->vendor);
+	rom_device = le16_to_cpu(rom_data->device);
 
 	debug("PCI ROM image, vendor ID %04x, device ID %04x,\n",
-	      rom_data->vendor, rom_data->device);
+	      rom_vendor, rom_device);
 
 	/* If the device id is mapped, a mismatch is expected */
-	if ((vendor != rom_data->vendor || device != rom_data->device) &&
+	if ((vendor != rom_vendor || device != rom_device) &&
 	    (vendev == mapped_vendev)) {
 		printf("ID mismatch: vendor ID %04x, device ID %04x\n",
-		       rom_data->vendor, rom_data->device);
+		       rom_vendor, rom_device);
 		return -EPERM;
 	}
 
@@ -144,10 +147,10 @@ int pci_rom_load(uint16_t class, struct pci_rom_header *rom_header,
 							    image_size);
 
 		rom_data = (struct pci_rom_data *)((void *)rom_header +
-				le32_to_cpu(rom_header->data));
+				le16_to_cpu(rom_header->data));
 
-		image_size = le32_to_cpu(rom_data->ilen) * 512;
-	} while ((rom_data->type != 0) && (rom_data->indicator != 0));
+		image_size = le16_to_cpu(rom_data->ilen) * 512;
+	} while ((rom_data->type != 0) && (rom_data->indicator == 0));
 
 	if (rom_data->type != 0)
 		return -EACCES;
-- 
cgit v1.3.1


From bdc88d4eb31e2bc84afb427c216c79e87a4233ef Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 29 Dec 2014 19:32:24 -0700
Subject: x86: Support ROMs on other archs

We shouldn't assume that the VGA ROM can always be loaded at c0000. This
is only true on x86 machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 arch/x86/include/asm/u-boot-x86.h | 2 ++
 drivers/pci/pci_rom.c             | 6 ++++++
 include/pci_rom.h                 | 1 -
 3 files changed, 8 insertions(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 36145cb0a81..b98afa801d3 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -70,4 +70,6 @@ uint64_t timer_get_tsc(void);
 
 void quick_ram_check(void);
 
+#define PCI_VGA_RAM_IMAGE_START		0xc0000
+
 #endif	/* _U_BOOT_I386_H_ */
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 86f0e95cd5a..124b730271d 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -157,7 +157,13 @@ int pci_rom_load(uint16_t class, struct pci_rom_header *rom_header,
 
 	rom_size = rom_header->size * 512;
 
+#ifdef PCI_VGA_RAM_IMAGE_START
 	target = (void *)PCI_VGA_RAM_IMAGE_START;
+#else
+	target = (void *)malloc(rom_size);
+	if (!target)
+		return -ENOMEM;
+#endif
 	if (target != rom_header) {
 		ulong start = get_timer(0);
 
diff --git a/include/pci_rom.h b/include/pci_rom.h
index 8b2674cf879..4ba36eb1b7b 100644
--- a/include/pci_rom.h
+++ b/include/pci_rom.h
@@ -8,7 +8,6 @@
 #define _PCI_ROM_H
 
 #define PCI_ROM_HDR			0xaa55
-#define PCI_VGA_RAM_IMAGE_START		0xc0000
 
 struct pci_rom_header {
 	uint16_t signature;
-- 
cgit v1.3.1


From e78dd86998298df6d6108b1bc070d934bd805873 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 29 Dec 2014 19:32:25 -0700
Subject: bios_emulator: Don't display error when emulator terminates

As it turns out this is a normal condition, so suppress the error.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 drivers/bios_emulator/x86emu/ops.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c
index 2bb5e2d9d50..5752fee1cda 100644
--- a/drivers/bios_emulator/x86emu/ops.c
+++ b/drivers/bios_emulator/x86emu/ops.c
@@ -179,7 +179,7 @@ void x86emuOp_illegal_op(
 {
     START_OF_INSTR();
     if (M.x86.R_SP != 0) {
-	ERR_PRINTF("ILLEGAL X86 OPCODE\n");
+	DB(printf("ILLEGAL X86 OPCODE\n"));
 	TRACE_REGS();
 	DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n",
 	    M.x86.R_CS, M.x86.R_IP-1,op1));
-- 
cgit v1.3.1


From 222f25f85503f19acb9cb7ff138d3fe5215c3ad9 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 29 Dec 2014 19:32:26 -0700
Subject: bios_emulator: Add some VESA interface debugging

Allow the supported modes to be listed when in debug mode.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 drivers/bios_emulator/atibios.c | 161 +++++++++++++++++++++++++++++++++++-----
 include/vbe.h                   |   9 ++-
 2 files changed, 148 insertions(+), 22 deletions(-)

(limited to 'drivers')

diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c
index 93b815ccb49..7ea5fa62247 100644
--- a/drivers/bios_emulator/atibios.c
+++ b/drivers/bios_emulator/atibios.c
@@ -62,40 +62,158 @@ static u32 saveBaseAddress14;
 static u32 saveBaseAddress18;
 static u32 saveBaseAddress20;
 
-static void atibios_set_vesa_mode(RMREGS *regs, int vesa_mode,
-				  struct vbe_mode_info *mode_info)
+/* Addres im memory of VBE region */
+const int vbe_offset = 0x2000;
+
+static const void *bios_ptr(const void *buf, BE_VGAInfo *vga_info,
+			    u32 x86_dword_ptr)
+{
+	u32 seg_ofs, flat;
+
+	seg_ofs = le32_to_cpu(x86_dword_ptr);
+	flat = ((seg_ofs & 0xffff0000) >> 12) | (seg_ofs & 0xffff);
+	if (flat >= 0xc0000)
+		return vga_info->BIOSImage + flat - 0xc0000;
+	else
+		return buf + (flat - vbe_offset);
+}
+
+static int atibios_debug_mode(BE_VGAInfo *vga_info, RMREGS *regs,
+			      int vesa_mode, struct vbe_mode_info *mode_info)
+{
+	void *buffer = (void *)(M.mem_base + vbe_offset);
+	u16 buffer_seg = (((unsigned long)vbe_offset) >> 4) & 0xff00;
+	u16 buffer_adr = ((unsigned long)vbe_offset) & 0xffff;
+	struct vesa_mode_info *vm;
+	struct vbe_info *info;
+	const u16 *modes_bios, *ptr;
+	u16 *modes;
+	int size;
+
+	debug("VBE: Getting information\n");
+	regs->e.eax = VESA_GET_INFO;
+	regs->e.esi = buffer_seg;
+	regs->e.edi = buffer_adr;
+	info = buffer;
+	memset(info, '\0', sizeof(*info));
+	strcpy(info->signature, "VBE2");
+	BE_int86(0x10, regs, regs);
+	if (regs->e.eax != 0x4f) {
+		debug("VESA_GET_INFO: error %x\n", regs->e.eax);
+		return -ENOSYS;
+	}
+	debug("version %x\n", le16_to_cpu(info->version));
+	debug("oem '%s'\n", (char *)bios_ptr(buffer, vga_info,
+					     info->oem_string_ptr));
+	debug("vendor '%s'\n", (char *)bios_ptr(buffer, vga_info,
+						info->vendor_name_ptr));
+	debug("product '%s'\n", (char *)bios_ptr(buffer, vga_info,
+						 info->product_name_ptr));
+	debug("rev '%s'\n", (char *)bios_ptr(buffer, vga_info,
+					     info->product_rev_ptr));
+	modes_bios = bios_ptr(buffer, vga_info, info->modes_ptr);
+	debug("Modes: ");
+	for (ptr = modes_bios; *ptr != 0xffff; ptr++)
+		debug("%x ", le16_to_cpu(*ptr));
+	debug("\nmemory %dMB\n", le16_to_cpu(info->total_memory) >> 4);
+	size = (ptr - modes_bios) * sizeof(u16) + 2;
+	modes = malloc(size);
+	if (!modes)
+		return -ENOMEM;
+	memcpy(modes, modes_bios, size);
+
+	regs->e.eax = VESA_GET_CUR_MODE;
+	BE_int86(0x10, regs, regs);
+	if (regs->e.eax != 0x4f) {
+		debug("VESA_GET_CUR_MODE: error %x\n", regs->e.eax);
+		return -ENOSYS;
+	}
+	debug("Current mode %x\n", regs->e.ebx);
+
+	for (ptr = modes; *ptr != 0xffff; ptr++) {
+		int mode = le16_to_cpu(*ptr);
+		bool linear_ok;
+		int attr;
+
+		break;
+		debug("Mode %x: ", mode);
+		memset(buffer, '\0', sizeof(struct vbe_mode_info));
+		regs->e.eax = VESA_GET_MODE_INFO;
+		regs->e.ebx = 0;
+		regs->e.ecx = mode;
+		regs->e.edx = 0;
+		regs->e.esi = buffer_seg;
+		regs->e.edi = buffer_adr;
+		BE_int86(0x10, regs, regs);
+		if (regs->e.eax != 0x4f) {
+			debug("VESA_GET_MODE_INFO: error %x\n", regs->e.eax);
+			continue;
+		}
+		memcpy(mode_info->mode_info_block, buffer,
+		       sizeof(struct vesa_mode_info));
+		mode_info->valid = true;
+		vm = &mode_info->vesa;
+		attr = le16_to_cpu(vm->mode_attributes);
+		linear_ok = attr & 0x80;
+		debug("res %d x %d, %d bpp, mm %d, (Linear %s, attr %02x)\n",
+		      le16_to_cpu(vm->x_resolution),
+		      le16_to_cpu(vm->y_resolution),
+		      vm->bits_per_pixel, vm->memory_model,
+		      linear_ok ? "OK" : "not available",
+		      attr);
+		debug("\tRGB pos=%d,%d,%d, size=%d,%d,%d\n",
+		      vm->red_mask_pos, vm->green_mask_pos, vm->blue_mask_pos,
+		      vm->red_mask_size, vm->green_mask_size,
+		      vm->blue_mask_size);
+	}
+
+	return 0;
+}
+
+static int atibios_set_vesa_mode(RMREGS *regs, int vesa_mode,
+				 struct vbe_mode_info *mode_info)
 {
+	void *buffer = (void *)(M.mem_base + vbe_offset);
+	u16 buffer_seg = (((unsigned long)vbe_offset) >> 4) & 0xff00;
+	u16 buffer_adr = ((unsigned long)vbe_offset) & 0xffff;
+	struct vesa_mode_info *vm;
+
 	debug("VBE: Setting VESA mode %#04x\n", vesa_mode);
-	/* request linear framebuffer mode */
-	vesa_mode |= (1 << 14);
-	/* request clearing of framebuffer */
-	vesa_mode &= ~(1 << 15);
 	regs->e.eax = VESA_SET_MODE;
 	regs->e.ebx = vesa_mode;
+	/* request linear framebuffer mode and don't clear display */
+	regs->e.ebx |= (1 << 14) | (1 << 15);
 	BE_int86(0x10, regs, regs);
+	if (regs->e.eax != 0x4f) {
+		debug("VESA_SET_MODE: error %x\n", regs->e.eax);
+		return -ENOSYS;
+	}
 
-	int offset = 0x2000;
-	void *buffer = (void *)(M.mem_base + offset);
-
-	u16 buffer_seg = (((unsigned long)offset) >> 4) & 0xff00;
-	u16 buffer_adr = ((unsigned long)offset) & 0xffff;
+	memset(buffer, '\0', sizeof(struct vbe_mode_info));
+	debug("VBE: Geting info for VESA mode %#04x\n", vesa_mode);
 	regs->e.eax = VESA_GET_MODE_INFO;
-	regs->e.ebx = 0;
 	regs->e.ecx = vesa_mode;
-	regs->e.edx = 0;
 	regs->e.esi = buffer_seg;
 	regs->e.edi = buffer_adr;
 	BE_int86(0x10, regs, regs);
+	if (regs->e.eax != 0x4f) {
+		debug("VESA_GET_MODE_INFO: error %x\n", regs->e.eax);
+		return -ENOSYS;
+	}
+
 	memcpy(mode_info->mode_info_block, buffer,
-	       sizeof(struct vbe_mode_info));
+		sizeof(struct vesa_mode_info));
 	mode_info->valid = true;
+	mode_info->video_mode = vesa_mode;
+	vm = &mode_info->vesa;
+	vm->x_resolution = le16_to_cpu(vm->x_resolution);
+	vm->y_resolution = le16_to_cpu(vm->y_resolution);
+	vm->bytes_per_scanline = le16_to_cpu(vm->bytes_per_scanline);
+	vm->phys_base_ptr = le32_to_cpu(vm->phys_base_ptr);
+	vm->mode_attributes = le16_to_cpu(vm->mode_attributes);
+	debug("VBE: Init complete\n");
 
-	vesa_mode |= (1 << 14);
-	/* request clearing of framebuffer */
-	vesa_mode &= ~(1 << 15);
-	regs->e.eax = VESA_SET_MODE;
-	regs->e.ebx = vesa_mode;
-	BE_int86(0x10, regs, regs);
+	return 0;
 }
 
 /****************************************************************************
@@ -132,6 +250,9 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
 	/*Cleanup and exit*/
 	BE_getVGA(vga_info);
 
+	/* Useful for debugging */
+	if (0)
+		atibios_debug_mode(vga_info, &regs, vesa_mode, mode_info);
 	if (vesa_mode != -1)
 		atibios_set_vesa_mode(&regs, vesa_mode, mode_info);
 }
diff --git a/include/vbe.h b/include/vbe.h
index d4056914c4e..c5deee9eca9 100644
--- a/include/vbe.h
+++ b/include/vbe.h
@@ -35,10 +35,14 @@ struct __packed screen_info_input {
 struct __packed vbe_info {
 	char signature[4];
 	u16 version;
-	u8 *oem_string_ptr;
+	u32 oem_string_ptr;
 	u32 capabilities;
-	u16 video_mode_list[256];
+	u32 modes_ptr;
 	u16 total_memory;
+	u16 oem_version;
+	u32 vendor_name_ptr;
+	u32 product_name_ptr;
+	u32 product_rev_ptr;
 };
 
 struct __packed vesa_mode_info {
@@ -96,6 +100,7 @@ struct vbe_ddc_info {
 #define VESA_GET_INFO		0x4f00
 #define VESA_GET_MODE_INFO	0x4f01
 #define VESA_SET_MODE		0x4f02
+#define VESA_GET_CUR_MODE	0x4f03
 
 struct graphic_device;
 int vbe_get_video_info(struct graphic_device *gdev);
-- 
cgit v1.3.1


From c5caba03665b0491832ca4c38209d71ff28bf593 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 29 Dec 2014 19:32:27 -0700
Subject: x86: pci: Don't stop when we get a vendor/device mismatch

These are quite common and we may as well press on and not be so picky.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 drivers/pci/pci_rom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 124b730271d..a16e99f1dad 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -117,7 +117,7 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
 	    (vendev == mapped_vendev)) {
 		printf("ID mismatch: vendor ID %04x, device ID %04x\n",
 		       rom_vendor, rom_device);
-		return -EPERM;
+		/* Continue anyway */
 	}
 
 	debug("PCI ROM image, Class Code %04x%02x, Code Type %02x\n",
-- 
cgit v1.3.1


From 6b1ba984507039a893b14c2dec3c7b1edbc8413d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 29 Dec 2014 19:32:28 -0700
Subject: x86: Add a VESA video driver

Add a driver intended to cope with any VESA-compatible x86 graphics
adapter. It will not support ROMs which use OpenFirmware (Forth) since
there is no support for that in U-Boot. This means that MAC OS cards
will not work.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 drivers/video/Kconfig   | 10 ++++++++
 drivers/video/Makefile  |  1 +
 drivers/video/vesa_fb.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 75 insertions(+)
 create mode 100644 drivers/video/vesa_fb.c

(limited to 'drivers')

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index ccbd7e295dd..697171e413c 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1,3 +1,13 @@
+config VIDEO_VESA
+	bool "Enable VESA video driver support"
+	depends on X86
+	default n
+	help
+	  Turn on this option to enable a very simple driver which uses vesa
+	  to discover the video mode and then provides a frame buffer for use
+	  by U-Boot. This can in principle be used with any platform that
+	  supports PCI and video cards that support VESA BIOS Extension (VBE).
+
 config VIDEO_X86
 	bool "Enable x86 video driver support"
 	depends on X86
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index c3fcf455d26..9f3c8bba17c 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
 obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o
 obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
 obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
+obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o
 obj-$(CONFIG_VIDEO_X86) += x86_fb.o
 obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
new file mode 100644
index 00000000000..3dacafd6bf5
--- /dev/null
+++ b/drivers/video/vesa_fb.c
@@ -0,0 +1,64 @@
+/*
+ *
+ * Vesa frame buffer driver for x86
+ *
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci_rom.h>
+#include <video_fb.h>
+#include <vbe.h>
+
+/*
+ * The Graphic Device
+ */
+GraphicDevice ctfb;
+
+/* Devices to allow - only the last one works fully */
+struct pci_device_id vesa_video_ids[] = {
+	{ .vendor = 0x102b, .device = 0x0525 },
+	{ .vendor = 0x1002, .device = 0x5159 },
+	{ .vendor = 0x1002, .device = 0x4752 },
+	{ .vendor = 0x1002, .device = 0x5452 },
+	{},
+};
+
+void *video_hw_init(void)
+{
+	GraphicDevice *gdev = &ctfb;
+	int bits_per_pixel;
+	pci_dev_t dev;
+	int ret;
+
+	printf("Video: ");
+	if (vbe_get_video_info(gdev)) {
+		/* TODO: Should we look these up by class? */
+		dev = pci_find_devices(vesa_video_ids, 0);
+		if (dev == -1) {
+			printf("no card detected\n");
+			return NULL;
+		}
+		printf("bdf %x\n", dev);
+		ret = pci_run_vga_bios(dev, NULL, true);
+		if (ret) {
+			printf("failed to run video BIOS: %d\n", ret);
+			return NULL;
+		}
+	}
+
+	if (vbe_get_video_info(gdev)) {
+		printf("No video mode configured\n");
+		return NULL;
+	}
+
+	bits_per_pixel = gdev->gdfBytesPP * 8;
+	sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
+		bits_per_pixel);
+	printf("%s\n", gdev->modeIdent);
+	debug("Framex buffer at %x\n", gdev->pciBase);
+
+	return (void *)gdev;
+}
-- 
cgit v1.3.1


From edb8b7a66b75045cc9e16a2762cd8344cdcd9bf5 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 29 Dec 2014 19:32:29 -0700
Subject: x86: Drop the x86_fb driver

Now that we have a full VESA driver we may as well use that. We need to
support the VESA layer being set up by early start-up code or by
running a VGA ROM.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 configs/chromebook_link_defconfig |  2 +-
 drivers/video/Kconfig             |  9 ---------
 drivers/video/Makefile            |  1 -
 drivers/video/x86_fb.c            | 38 --------------------------------------
 4 files changed, 1 insertion(+), 49 deletions(-)
 delete mode 100644 drivers/video/x86_fb.c

(limited to 'drivers')

diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index e956835dc6d..2f0c714e59f 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -6,6 +6,6 @@ CONFIG_OF_SEPARATE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
 CONFIG_HAVE_MRC=y
 CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_VIDEO_X86=y
+CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 697171e413c..51728b366f0 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -8,15 +8,6 @@ config VIDEO_VESA
 	  by U-Boot. This can in principle be used with any platform that
 	  supports PCI and video cards that support VESA BIOS Extension (VBE).
 
-config VIDEO_X86
-	bool "Enable x86 video driver support"
-	depends on X86
-	default n
-	help
-	  Turn on this option to enable a very simple driver which uses vesa
-	  to discover the video mode and then provides a frame buffer for use
-	  by U-Boot.
-
 config VIDEO_LCD_SSD2828
 	bool "SSD2828 bridge chip"
 	default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 9f3c8bba17c..af2d47bd75f 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -45,7 +45,6 @@ obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o
 obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
 obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
 obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o
-obj-$(CONFIG_VIDEO_X86) += x86_fb.o
 obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_PARADE) += parade.o
diff --git a/drivers/video/x86_fb.c b/drivers/video/x86_fb.c
deleted file mode 100644
index 6641033a5df..00000000000
--- a/drivers/video/x86_fb.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *
- * Vesa frame buffer driver for x86
- *
- * Copyright (C) 2014 Google, Inc
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <video_fb.h>
-#include <vbe.h>
-#include "videomodes.h"
-
-/*
- * The Graphic Device
- */
-GraphicDevice ctfb;
-
-void *video_hw_init(void)
-{
-	GraphicDevice *gdev = &ctfb;
-	int bits_per_pixel;
-
-	printf("Video: ");
-	if (vbe_get_video_info(gdev)) {
-		printf("No video mode configured\n");
-		return NULL;
-	}
-
-	bits_per_pixel = gdev->gdfBytesPP * 8;
-	sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
-		bits_per_pixel);
-	printf("%s\n", gdev->modeIdent);
-	debug("Frame buffer at %x\n", gdev->frameAdrs);
-
-	return (void *)gdev;
-}
-- 
cgit v1.3.1


From 4df2b48fbee148cd2c4137ee920220338f0dcaf0 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 31 Dec 2014 17:18:39 +0800
Subject: x86: ahci: Make sure interface is not busy after enabling the port

Each time U-Boot boots on Intel Crown Bay board, the displayed hard
drive information is wrong. It could be either wrong capacity or just
a 'Capacity: not available' message. After enabling the debug switch,
we can see the scsi inquiry command did not execute successfully.
However, doing a 'scsi scan' in the U-Boot shell does not expose
this issue.

SCSI:  Target spinup took 0 ms.
SATA link 1 timeout.
AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
flags: ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
ahci_device_data_io: 0 byte transferred.   <--- scsi inquiry fails
ahci_device_data_io: 512 byte transferred.
ahci_device_data_io: 512 byte transferred.
ahci_device_data_io: 512 byte transferred.
  Device 0: (0:0) Vendor: ATA Prod.:  Rev: ?8
              Type: Hard Disk
	                  Capacity: 912968.3 MB = 891.5 GB (1869759264 x 512)
			  Found 1 device(s).

So uninitialized contents on the stack were passed to dev_print() to
display those wrong information.

The symptom were observed on two hard drives (one is Seagate, the
other one is Western Digital). The fix is to make sure the AHCI
interface is not busy by checking the error and status information
from task file register after enabling the port in ahci_port_start()
before proceeding other operations like scsi_scan().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 drivers/block/ahci.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 37d2d2a28ee..c908fab4506 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -513,6 +513,20 @@ static void ahci_set_feature(u8 port)
 }
 #endif
 
+static int wait_spinup(volatile u8 *port_mmio)
+{
+	ulong start;
+	u32 tf_data;
+
+	start = get_timer(0);
+	do {
+		tf_data = readl(port_mmio + PORT_TFDATA);
+		if (!(tf_data & ATA_BUSY))
+			return 0;
+	} while (get_timer(start) < WAIT_MS_SPINUP);
+
+	return -ETIMEDOUT;
+}
 
 static int ahci_port_start(u8 port)
 {
@@ -579,7 +593,11 @@ static int ahci_port_start(u8 port)
 
 	debug("Exit start port %d\n", port);
 
-	return 0;
+	/*
+	 * Make sure interface is not busy based on error and status
+	 * information from task file data register before proceeding
+	 */
+	return wait_spinup(port_mmio);
 }
 
 
-- 
cgit v1.3.1


From 4a2708a097eacd7aa3d10ccf26a70a467fa69217 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 14 Jan 2015 21:37:04 -0700
Subject: x86: Access the VGA ROM when needed

Add code to the generic pci_rom file to access the VGA ROM in PCI space
when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 drivers/pci/pci_auto.c | 28 +++++++++++++++++++++++++++-
 drivers/pci/pci_rom.c  |  7 ++++++-
 include/pci.h          |  9 +++++++++
 3 files changed, 42 insertions(+), 2 deletions(-)

(limited to 'drivers')

diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 44470fa812b..ed928574061 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -11,7 +11,7 @@
  */
 
 #include <common.h>
-
+#include <errno.h>
 #include <pci.h>
 
 #undef DEBUG
@@ -191,6 +191,32 @@ void pciauto_setup_device(struct pci_controller *hose,
 	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 }
 
+int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev)
+{
+	pci_addr_t bar_value;
+	pci_size_t bar_size;
+	u32 bar_response;
+	u16 cmdstat = 0;
+
+	pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 0xfffffffe);
+	pci_hose_read_config_dword(hose, dev, PCI_ROM_ADDRESS, &bar_response);
+	if (!bar_response)
+		return -ENOENT;
+
+	bar_size = -(bar_response & ~1);
+	DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size);
+	if (pciauto_region_allocate(hose->pci_mem, bar_size, &bar_value) == 0) {
+		pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS,
+					    bar_value);
+	}
+	DEBUGF("\n");
+	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
+	cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
+
+	return 0;
+}
+
 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 					 pci_dev_t dev, int sub_bus)
 {
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index a16e99f1dad..eb7659177b4 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -81,7 +81,12 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
 #ifdef CONFIG_X86_OPTION_ROM_ADDR
 	rom_address = CONFIG_X86_OPTION_ROM_ADDR;
 #else
-	pci_write_config_dword(dev, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
+
+	if (pciauto_setup_rom(pci_bus_to_hose(PCI_BUS(dev)), dev)) {
+		debug("Cannot find option ROM\n");
+		return -ENOENT;
+	}
+
 	pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address);
 	if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
 		debug("%s: rom_address=%x\n", __func__, rom_address);
diff --git a/include/pci.h b/include/pci.h
index 7f67ca65426..4fbb8f6729f 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -697,5 +697,14 @@ void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
  * */
 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
 
+/**
+ * pciauto_setup_rom() - Set up access to a device ROM
+ *
+ * @hose:	PCI hose to use
+ * @dev:	PCI device to adjust
+ * @return 0 if done, -ve on error
+ */
+int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev);
+
 #endif /* __ASSEMBLY__ */
 #endif /* _PCI_H */
-- 
cgit v1.3.1


From 3c0b668f6672334a68be83cde9aaabf0e87a31e9 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 1 Jan 2015 16:17:57 -0700
Subject: x86: video: Add support for CONFIG_CONSOLE_SCROLL_LINES

Some machines are very slow to scroll their displays. To cope with this,
support the CONFIG_CONSOLE_SCROLL_LINES option. Setting this to 5 allows
the display to operate at an acceptable speed by scrolling 5 lines at
a time.

This same option is available for LCDs so when these systems are unified
this code can be unified also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
---
 drivers/video/cfb_console.c | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

(limited to 'drivers')

diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index d4226e3eb6f..a81affa3333 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -299,7 +299,11 @@ void console_cursor(int state);
 #define CONSOLE_ROW_SECOND	(video_console_address + CONSOLE_ROW_SIZE)
 #define CONSOLE_ROW_LAST	(video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE)
 #define CONSOLE_SIZE		(CONSOLE_ROW_SIZE * CONSOLE_ROWS)
-#define CONSOLE_SCROLL_SIZE	(CONSOLE_SIZE - CONSOLE_ROW_SIZE)
+
+/* By default we scroll by a single line */
+#ifndef CONFIG_CONSOLE_SCROLL_LINES
+#define CONFIG_CONSOLE_SCROLL_LINES 1
+#endif
 
 /* Macros */
 #ifdef	VIDEO_FB_LITTLE_ENDIAN
@@ -740,26 +744,33 @@ static void console_clear_line(int line, int begin, int end)
 
 static void console_scrollup(void)
 {
+	const int rows = CONFIG_CONSOLE_SCROLL_LINES;
+	int i;
+
 	/* copy up rows ignoring the first one */
 
 #ifdef VIDEO_HW_BITBLT
 	video_hw_bitblt(VIDEO_PIXEL_SIZE,	/* bytes per pixel */
 			0,			/* source pos x */
 			video_logo_height +
-				VIDEO_FONT_HEIGHT, /* source pos y */
+				VIDEO_FONT_HEIGHT * rows, /* source pos y */
 			0,			/* dest pos x */
 			video_logo_height,	/* dest pos y */
 			VIDEO_VISIBLE_COLS,	/* frame width */
 			VIDEO_VISIBLE_ROWS
 			- video_logo_height
-			- VIDEO_FONT_HEIGHT	/* frame height */
+			- VIDEO_FONT_HEIGHT * rows	/* frame height */
 		);
 #else
-	memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND,
-		CONSOLE_SCROLL_SIZE >> 2);
+	memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_FIRST + rows * CONSOLE_ROW_SIZE,
+		(CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows) >> 2);
 #endif
 	/* clear the last one */
-	console_clear_line(CONSOLE_ROWS - 1, 0, CONSOLE_COLS - 1);
+	for (i = 1; i <= rows; i++)
+		console_clear_line(CONSOLE_ROWS - i, 0, CONSOLE_COLS - 1);
+
+	/* Decrement row number */
+	console_row -= rows;
 }
 
 static void console_back(void)
@@ -871,9 +882,6 @@ static void console_newline(int n)
 	if (console_row >= CONSOLE_ROWS) {
 		/* Scroll everything up */
 		console_scrollup();
-
-		/* Decrement row number */
-		console_row = CONSOLE_ROWS - 1;
 	}
 }
 
-- 
cgit v1.3.1


From 053b86e6d8e50359412e626c33bae3f7bafd74dd Mon Sep 17 00:00:00 2001
From: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Date: Tue, 20 Jan 2015 18:06:53 +0100
Subject: pci: tegra: Fix port information parsing

commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the
new fdtdec pci helpers. To get the device index of the root port, the
"reg" property should be parsed from the dtb (as was previously the
case).

With this patch i can successfully network boot my jetson tk1

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
 drivers/pci/pci_tegra.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

(limited to 'drivers')

diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c
index f9e05add191..67b5fdf07c5 100644
--- a/drivers/pci/pci_tegra.c
+++ b/drivers/pci/pci_tegra.c
@@ -459,7 +459,6 @@ static int tegra_pcie_parse_port_info(const void *fdt, int node,
 				      unsigned int *lanes)
 {
 	struct fdt_pci_addr addr;
-	pci_dev_t bdf;
 	int err;
 
 	err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0);
@@ -470,13 +469,13 @@ static int tegra_pcie_parse_port_info(const void *fdt, int node,
 
 	*lanes = err;
 
-	err = fdtdec_get_pci_bdf(fdt, node, &addr, &bdf);
+	err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr);
 	if (err < 0) {
 		error("failed to parse \"reg\" property");
 		return err;
 	}
 
-	*index = PCI_DEV(bdf) - 1;
+	*index = PCI_DEV(addr.phys_hi) - 1;
 
 	return 0;
 }
-- 
cgit v1.3.1


From fc4860c089a6b6603e1ae4f9c1f8bd1b3aadfc8b Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 19 Jan 2015 22:16:10 -0700
Subject: x86: rtc: mc146818: Add helpers to read/write CMOS RAM

On x86 we use CMOS RAM to read and write some settings. Add basic support
for this, including access to registers 128-255.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 drivers/rtc/mc146818.c | 121 +++++++++++++++++++++++++++++--------------------
 include/rtc.h          |  32 +++++++++++++
 2 files changed, 105 insertions(+), 48 deletions(-)

(limited to 'drivers')

diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index 39e6041be36..c9d318c0a7e 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -27,9 +27,6 @@
 /* Set this to 1 to clear the CMOS RAM */
 #define CLEAR_CMOS 0
 
-static uchar rtc_read  (uchar reg);
-static void  rtc_write (uchar reg, uchar val);
-
 #define RTC_PORT_MC146818	CONFIG_SYS_ISA_IO_BASE_ADDRESS +  0x70
 #define RTC_SECONDS		0x00
 #define RTC_SECONDS_ALARM	0x01
@@ -60,24 +57,24 @@ int rtc_get (struct rtc_time *tmp)
 {
 	uchar sec, min, hour, mday, wday, mon, year;
   /* here check if rtc can be accessed */
-	while((rtc_read(RTC_CONFIG_A)&0x80)==0x80);
-	sec	= rtc_read (RTC_SECONDS);
-	min	= rtc_read (RTC_MINUTES);
-	hour	= rtc_read (RTC_HOURS);
-	mday	= rtc_read (RTC_DATE_OF_MONTH);
-	wday	= rtc_read (RTC_DAY_OF_WEEK);
-	mon	= rtc_read (RTC_MONTH);
-	year	= rtc_read (RTC_YEAR);
+	while ((rtc_read8(RTC_CONFIG_A) & 0x80) == 0x80);
+	sec	= rtc_read8(RTC_SECONDS);
+	min	= rtc_read8(RTC_MINUTES);
+	hour	= rtc_read8(RTC_HOURS);
+	mday	= rtc_read8(RTC_DATE_OF_MONTH);
+	wday	= rtc_read8(RTC_DAY_OF_WEEK);
+	mon	= rtc_read8(RTC_MONTH);
+	year	= rtc_read8(RTC_YEAR);
 #ifdef RTC_DEBUG
 	printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
 		"hr: %02x min: %02x sec: %02x\n",
 		year, mon, mday, wday,
 		hour, min, sec );
 	printf ( "Alarms: month: %02x hour: %02x min: %02x sec: %02x\n",
-		rtc_read (RTC_CONFIG_D) & 0x3F,
-		rtc_read (RTC_HOURS_ALARM),
-		rtc_read (RTC_MINUTES_ALARM),
-		rtc_read (RTC_SECONDS_ALARM) );
+		rtc_read8(RTC_CONFIG_D) & 0x3F,
+		rtc_read8(RTC_HOURS_ALARM),
+		rtc_read8(RTC_MINUTES_ALARM),
+		rtc_read8(RTC_SECONDS_ALARM));
 #endif
 	tmp->tm_sec  = bcd2bin (sec  & 0x7F);
 	tmp->tm_min  = bcd2bin (min  & 0x7F);
@@ -108,80 +105,108 @@ int rtc_set (struct rtc_time *tmp)
 		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
 		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
 #endif
-	rtc_write(RTC_CONFIG_B,0x82); /* disables the RTC to update the regs */
+	rtc_write8(RTC_CONFIG_B, 0x82); /* disable the RTC to update the regs */
 
-	rtc_write (RTC_YEAR, bin2bcd(tmp->tm_year % 100));
-	rtc_write (RTC_MONTH, bin2bcd(tmp->tm_mon));
-	rtc_write (RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday));
-	rtc_write (RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday));
-	rtc_write (RTC_HOURS, bin2bcd(tmp->tm_hour));
-	rtc_write (RTC_MINUTES, bin2bcd(tmp->tm_min ));
-	rtc_write (RTC_SECONDS, bin2bcd(tmp->tm_sec ));
-	rtc_write(RTC_CONFIG_B,0x02); /* enables the RTC to update the regs */
+	rtc_write8(RTC_YEAR, bin2bcd(tmp->tm_year % 100));
+	rtc_write8(RTC_MONTH, bin2bcd(tmp->tm_mon));
+	rtc_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday));
+	rtc_write8(RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday));
+	rtc_write8(RTC_HOURS, bin2bcd(tmp->tm_hour));
+	rtc_write8(RTC_MINUTES, bin2bcd(tmp->tm_min));
+	rtc_write8(RTC_SECONDS, bin2bcd(tmp->tm_sec));
+	rtc_write8(RTC_CONFIG_B, 0x02); /* enable the RTC to update the regs */
 
 	return 0;
 }
 
 void rtc_reset (void)
 {
-	rtc_write(RTC_CONFIG_B,0x82); /* disables the RTC to update the regs */
-	rtc_write(RTC_CONFIG_A,0x20); /* Normal OP */
-	rtc_write(RTC_CONFIG_B,0x00);
-	rtc_write(RTC_CONFIG_B,0x00);
-	rtc_write(RTC_CONFIG_B,0x02); /* enables the RTC to update the regs */
+	rtc_write8(RTC_CONFIG_B, 0x82); /* disable the RTC to update the regs */
+	rtc_write8(RTC_CONFIG_A, 0x20); /* Normal OP */
+	rtc_write8(RTC_CONFIG_B, 0x00);
+	rtc_write8(RTC_CONFIG_B, 0x00);
+	rtc_write8(RTC_CONFIG_B, 0x02); /* enable the RTC to update the regs */
 }
 
 /* ------------------------------------------------------------------------- */
 
-#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
 /*
  * use direct memory access
  */
-static uchar rtc_read (uchar reg)
+int rtc_read8(int reg)
 {
+#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
 	return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg);
+#else
+	int ofs = 0;
+
+	if (reg >= 128) {
+		ofs = 2;
+		reg -= 128;
+	}
+	out8(RTC_PORT_MC146818 + ofs, reg);
+
+	return in8(RTC_PORT_MC146818 + ofs + 1);
+#endif
 }
 
-static void rtc_write (uchar reg, uchar val)
+void rtc_write8(int reg, uchar val)
 {
+#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
 	out8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg, val);
-}
 #else
-static uchar rtc_read (uchar reg)
+	int ofs = 0;
+
+	if (reg >= 128) {
+		ofs = 2;
+		reg -= 128;
+	}
+	out8(RTC_PORT_MC146818 + ofs, reg);
+	out8(RTC_PORT_MC146818 + ofs + 1, val);
+#endif
+}
+
+u32 rtc_read32(int reg)
 {
-	out8(RTC_PORT_MC146818,reg);
-	return in8(RTC_PORT_MC146818 + 1);
+	u32 value = 0;
+	int i;
+
+	for (i = 0; i < sizeof(value); i++)
+		value |= rtc_read8(reg + i) << (i << 3);
+
+	return value;
 }
 
-static void rtc_write (uchar reg, uchar val)
+void rtc_write32(int reg, u32 value)
 {
-	out8(RTC_PORT_MC146818,reg);
-	out8(RTC_PORT_MC146818+1, val);
+	int i;
+
+	for (i = 0; i < sizeof(value); i++)
+		rtc_write8(reg + i, (value >> (i << 3)) & 0xff);
 }
-#endif
 
 void rtc_init(void)
 {
 #if CLEAR_CMOS
 	int i;
 
-	rtc_write(RTC_SECONDS_ALARM, 0);
-	rtc_write(RTC_MINUTES_ALARM, 0);
-	rtc_write(RTC_HOURS_ALARM, 0);
+	rtc_write8(RTC_SECONDS_ALARM, 0);
+	rtc_write8(RTC_MINUTES_ALARM, 0);
+	rtc_write8(RTC_HOURS_ALARM, 0);
 	for (i = RTC_CONFIG_A; i < RTC_REG_SIZE; i++)
-		rtc_write(i, 0);
+		rtc_write8(i, 0);
 	printf("RTC: zeroing CMOS RAM\n");
 #endif
 
 	/* Setup the real time clock */
-	rtc_write(RTC_CONFIG_B, RTC_CONFIG_B_24H);
+	rtc_write8(RTC_CONFIG_B, RTC_CONFIG_B_24H);
 	/* Setup the frequency it operates at */
-	rtc_write(RTC_CONFIG_A, RTC_CONFIG_A_REF_CLCK_32KHZ |
+	rtc_write8(RTC_CONFIG_A, RTC_CONFIG_A_REF_CLCK_32KHZ |
 		  RTC_CONFIG_A_RATE_1024HZ);
 	/* Ensure all reserved bits are 0 in register D */
-	rtc_write(RTC_CONFIG_D, RTC_CONFIG_D_VALID_RAM_AND_TIME);
+	rtc_write8(RTC_CONFIG_D, RTC_CONFIG_D_VALID_RAM_AND_TIME);
 
 	/* Clear any pending interrupts */
-	rtc_read(RTC_CONFIG_C);
+	rtc_read8(RTC_CONFIG_C);
 }
 #endif
diff --git a/include/rtc.h b/include/rtc.h
index d11aa8baf91..54e361ea5e8 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -50,6 +50,38 @@ void to_tm (int, struct rtc_time *);
 unsigned long mktime (unsigned int, unsigned int, unsigned int,
 		      unsigned int, unsigned int, unsigned int);
 
+/**
+ * rtc_read8() - Read an 8-bit register
+ *
+ * @reg:	Register to read
+ * @return value read
+ */
+int rtc_read8(int reg);
+
+/**
+ * rtc_write8() - Write an 8-bit register
+ *
+ * @reg:	Register to write
+ * @value:	Value to write
+ */
+void rtc_write8(int reg, uchar val);
+
+/**
+ * rtc_read32() - Read a 32-bit value from the RTC
+ *
+ * @reg:	Offset to start reading from
+ * @return value read
+ */
+u32 rtc_read32(int reg);
+
+/**
+ * rtc_write32() - Write a 32-bit value to the RTC
+ *
+ * @reg:	Register to start writing to
+ * @value:	Value to write
+ */
+void rtc_write32(int reg, u32 value);
+
 /**
  * rtc_init() - Set up the real time clock ready for use
  */
-- 
cgit v1.3.1


From 8e899af0597a43d70752654b227f308dd0d0039c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 19 Jan 2015 22:16:11 -0700
Subject: x86: spi: Add device tree support

As a temporary measure before the ICH driver moves over to driver model,
add device tree support to the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 drivers/spi/ich.c            | 7 +++++++
 include/configs/x86-common.h | 1 +
 2 files changed, 8 insertions(+)

(limited to 'drivers')

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 0379444872e..fdff158637d 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -153,6 +153,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	return &ich->slave;
 }
 
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
+				      int spi_node)
+{
+	/* We only support a single SPI at present */
+	return spi_setup_slave(0, 0, 20000000, 0);
+}
+
 void spi_free_slave(struct spi_slave *slave)
 {
 	struct ich_spi_slave *ich = to_ich_spi(slave);
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 4f0a3c59289..ecedfc3ab16 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -211,6 +211,7 @@
 #define CONFIG_CMD_SF_TEST
 #define CONFIG_CMD_SPI
 #define CONFIG_SPI
+#define CONFIG_OF_SPI_FLASH
 
 /*-----------------------------------------------------------------------
  * Environment configuration
-- 
cgit v1.3.1