From 28dc20f34a5a946427d3d02aaf76b4d90f3c5468 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 27 Sep 2020 18:46:17 -0600
Subject: syscon: Drop the logging in syscon_get_by_driver_data()

This function can be called when it is not known whether it will find
anything. This results in confusing log messages if the device is not
found. It is better for the caller to log the failure, if necessary.

Drop the logging from this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 drivers/core/syscon-uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index 509b09845ad..567d0a4b50a 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -142,7 +142,7 @@ int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
 
 	ret = uclass_first_device_drvdata(UCLASS_SYSCON, driver_data, devp);
 	if (ret)
-		return log_msg_ret("find", ret);
+		return ret;
 
 	return 0;
 }
-- 
cgit v1.3.1


From acdd248bf27abc1f4621e90665d2cc281b832313 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 27 Sep 2020 18:46:23 -0600
Subject: i2c: designware: Use log_debug() for debugging

We don't want the debug output to be visible in a normal boot. Silence it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher<hs@denx.de>
---
 drivers/i2c/designware_i2c.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'drivers')

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 569a5d39b49..791f32e971c 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -807,8 +807,8 @@ int designware_i2c_probe(struct udevice *bus)
 		return -ENXIO;
 	}
 
-	log_info("I2C bus %s version %#x\n", bus->name,
-		 readl(&priv->regs->comp_version));
+	log_debug("I2C bus %s version %#x\n", bus->name,
+		  readl(&priv->regs->comp_version));
 
 	return __dw_i2c_init(priv->regs, 0, 0);
 }
-- 
cgit v1.3.1


From 39565cc2a9f9db1cfefed61804fc5812d0ed1624 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 27 Sep 2020 18:46:24 -0600
Subject: tpm: cr50: Correct logging statements

Fix up some logging statements in this file. Most of them should use
log_debug(), apart from one error.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 drivers/tpm/cr50_i2c.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'drivers')

diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c
index 64831a42232..a761e3d52f1 100644
--- a/drivers/tpm/cr50_i2c.c
+++ b/drivers/tpm/cr50_i2c.c
@@ -494,13 +494,13 @@ static int process_reset(struct udevice *dev)
 			continue;
 		}
 
-		log_warning("TPM ready after %ld ms\n", get_timer(start));
+		log_debug("TPM ready after %ld ms\n", get_timer(start));
 
 		return 0;
 	} while (get_timer(start) < TIMEOUT_INIT_MS);
 
-	log_warning("TPM failed to reset after %ld ms, status: %#x\n",
-		    get_timer(start), access);
+	log_err("TPM failed to reset after %ld ms, status: %#x\n",
+		get_timer(start), access);
 
 	return -EPERM;
 }
@@ -539,7 +539,7 @@ static int claim_locality(struct udevice *dev, int loc)
 		log_err("Failed to claim locality\n");
 		return -EPERM;
 	}
-	log_info("Claimed locality %d\n", loc);
+	log_debug("Claimed locality %d\n", loc);
 	priv->locality = loc;
 
 	return 0;
@@ -577,7 +577,7 @@ static int cr50_i2c_cleanup(struct udevice *dev)
 {
 	struct cr50_priv *priv = dev_get_priv(dev);
 
-	printf("%s: cleanup %d\n", __func__, priv->locality);
+	log_debug("cleanup %d\n", priv->locality);
 	if (priv->locality != -1)
 		release_locality(dev, 1);
 
-- 
cgit v1.3.1


From c670aeee3df9186902dba07b76bd2de0776df390 Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <xypron.glpk@gmx.de>
Date: Wed, 7 Oct 2020 18:11:48 +0200
Subject: common: rename getc() to getchar()

The sandbox is built with the SDL2 library with invokes the X11 library
which in turn calls getc(). But getc() in glibc is defined as

    int getc(FILE *)

This does not match our definition.

    int getc(void)

The sandbox crashes when called with parameter -l.

Rename our library symbol getc() to getchar().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 api/api.c                                   |  2 +-
 cmd/bootmenu.c                              |  4 +--
 cmd/load.c                                  | 44 ++++++++++++++---------------
 common/autoboot.c                           | 10 +++----
 common/cli_readline.c                       |  4 +--
 common/console.c                            | 12 ++++----
 common/spl/spl_ymodem.c                     |  2 +-
 common/xyzModem.c                           |  2 +-
 drivers/ddr/fsl/main.c                      |  2 +-
 drivers/ram/stm32mp1/stm32mp1_interactive.c |  2 +-
 drivers/serial/serial-uclass.c              |  2 +-
 drivers/serial/serial.c                     |  2 +-
 include/_exports.h                          |  2 +-
 include/stdio.h                             |  2 +-
 lib/charset.c                               |  2 +-
 lib/efi_loader/efi_console.c                | 20 ++++++-------
 test/dm/usb.c                               |  2 +-
 17 files changed, 58 insertions(+), 58 deletions(-)

(limited to 'drivers')

diff --git a/api/api.c b/api/api.c
index c7f5db776af..493b77f8094 100644
--- a/api/api.c
+++ b/api/api.c
@@ -57,7 +57,7 @@ static int API_getc(va_list ap)
 	if ((c = (int *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
-	*c = getc();
+	*c = getchar();
 	return 0;
 }
 
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index 18efe25751f..1ba7b622e50 100644
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -99,7 +99,7 @@ static void bootmenu_autoboot_loop(struct bootmenu_data *menu,
 			}
 
 			menu->delay = -1;
-			c = getc();
+			c = getchar();
 
 			switch (c) {
 			case '\e':
@@ -141,7 +141,7 @@ static void bootmenu_loop(struct bootmenu_data *menu,
 		mdelay(10);
 	}
 
-	c = getc();
+	c = getchar();
 
 	switch (*esc) {
 	case 0:
diff --git a/cmd/load.c b/cmd/load.c
index 63a94145430..9a3a16979c7 100644
--- a/cmd/load.c
+++ b/cmd/load.c
@@ -81,7 +81,7 @@ static int do_load_serial(struct cmd_tbl *cmdtp, int flag, int argc,
 		serial_setbrg();
 		udelay(50000);
 		for (;;) {
-			if (getc() == '\r')
+			if (getchar() == '\r')
 				break;
 		}
 	}
@@ -102,7 +102,7 @@ static int do_load_serial(struct cmd_tbl *cmdtp, int flag, int argc,
 	 */
 	for (i=0; i<100; ++i) {
 		if (tstc()) {
-			(void) getc();
+			getchar();
 		}
 		udelay(1000);
 	}
@@ -124,7 +124,7 @@ static int do_load_serial(struct cmd_tbl *cmdtp, int flag, int argc,
 		serial_setbrg();
 		udelay(50000);
 		for (;;) {
-			if (getc() == 0x1B) /* ESC */
+			if (getchar() == 0x1B) /* ESC */
 				break;
 		}
 	}
@@ -212,7 +212,7 @@ static int read_record(char *buf, ulong len)
 	--len;	/* always leave room for terminating '\0' byte */
 
 	for (p=buf; p < buf+len; ++p) {
-		c = getc();		/* read character		*/
+		c = getchar();		/* read character		*/
 		if (do_echo)
 			putc(c);	/* ... and echo it		*/
 
@@ -229,7 +229,7 @@ static int read_record(char *buf, ulong len)
 		}
 
 	    /* Check for the console hangup (if any different from serial) */
-	    if (gd->jt->getc != getc) {
+	    if (gd->jt->getc != getchar) {
 		if (ctrlc()) {
 		    return (-1);
 		}
@@ -276,7 +276,7 @@ int do_save_serial(struct cmd_tbl *cmdtp, int flag, int argc,
 		serial_setbrg();
 		udelay(50000);
 		for (;;) {
-			if (getc() == '\r')
+			if (getchar() == '\r')
 				break;
 		}
 	}
@@ -288,7 +288,7 @@ int do_save_serial(struct cmd_tbl *cmdtp, int flag, int argc,
 
 	printf("## Ready for S-Record upload, press ENTER to proceed ...\n");
 	for (;;) {
-		if (getc() == '\r')
+		if (getchar() == '\r')
 			break;
 	}
 	if (save_serial(offset, size)) {
@@ -305,7 +305,7 @@ int do_save_serial(struct cmd_tbl *cmdtp, int flag, int argc,
 		serial_setbrg();
 		udelay(50000);
 		for (;;) {
-			if (getc() == 0x1B) /* ESC */
+			if (getchar() == 0x1B) /* ESC */
 				break;
 		}
 	}
@@ -459,7 +459,7 @@ static int do_load_serial_bin(struct cmd_tbl *cmdtp, int flag, int argc,
 		serial_setbrg();
 		udelay(50000);
 		for (;;) {
-			if (getc() == '\r')
+			if (getchar() == '\r')
 				break;
 		}
 	}
@@ -505,7 +505,7 @@ static int do_load_serial_bin(struct cmd_tbl *cmdtp, int flag, int argc,
 		serial_setbrg();
 		udelay(50000);
 		for (;;) {
-			if (getc() == 0x1B) /* ESC */
+			if (getchar() == 0x1B) /* ESC */
 				break;
 		}
 	}
@@ -528,7 +528,7 @@ static ulong load_serial_bin(ulong offset)
 	 */
 	for (i=0; i<100; ++i) {
 		if (tstc()) {
-			(void) getc();
+			getchar();
 		}
 		udelay(1000);
 	}
@@ -831,7 +831,7 @@ static int k_recv(void)
 		/* get a packet */
 		/* wait for the starting character or ^C */
 		for (;;) {
-			switch (getc ()) {
+			switch (getchar()) {
 			case START_CHAR:	/* start packet */
 				goto START;
 			case ETX_CHAR:		/* ^C waiting for packet */
@@ -843,13 +843,13 @@ static int k_recv(void)
 START:
 		/* get length of packet */
 		sum = 0;
-		new_char = getc();
+		new_char = getchar();
 		if ((new_char & 0xE0) == 0)
 			goto packet_error;
 		sum += new_char & 0xff;
 		length = untochar(new_char);
 		/* get sequence number */
-		new_char = getc();
+		new_char = getchar();
 		if ((new_char & 0xE0) == 0)
 			goto packet_error;
 		sum += new_char & 0xff;
@@ -876,7 +876,7 @@ START:
 		/* END NEW CODE */
 
 		/* get packet type */
-		new_char = getc();
+		new_char = getchar();
 		if ((new_char & 0xE0) == 0)
 			goto packet_error;
 		sum += new_char & 0xff;
@@ -886,19 +886,19 @@ START:
 		if (length == -2) {
 			/* (length byte was 0, decremented twice) */
 			/* get the two length bytes */
-			new_char = getc();
+			new_char = getchar();
 			if ((new_char & 0xE0) == 0)
 				goto packet_error;
 			sum += new_char & 0xff;
 			len_hi = untochar(new_char);
-			new_char = getc();
+			new_char = getchar();
 			if ((new_char & 0xE0) == 0)
 				goto packet_error;
 			sum += new_char & 0xff;
 			len_lo = untochar(new_char);
 			length = len_hi * 95 + len_lo;
 			/* check header checksum */
-			new_char = getc();
+			new_char = getchar();
 			if ((new_char & 0xE0) == 0)
 				goto packet_error;
 			if (new_char != tochar((sum + ((sum >> 6) & 0x03)) & 0x3f))
@@ -908,7 +908,7 @@ START:
 		}
 		/* bring in rest of packet */
 		while (length > 1) {
-			new_char = getc();
+			new_char = getchar();
 			if ((new_char & 0xE0) == 0)
 				goto packet_error;
 			sum += new_char & 0xff;
@@ -925,13 +925,13 @@ START:
 			}
 		}
 		/* get and validate checksum character */
-		new_char = getc();
+		new_char = getchar();
 		if ((new_char & 0xE0) == 0)
 			goto packet_error;
 		if (new_char != tochar((sum + ((sum >> 6) & 0x03)) & 0x3f))
 			goto packet_error;
 		/* get END_CHAR */
-		new_char = getc();
+		new_char = getchar();
 		if (new_char != END_CHAR) {
 		  packet_error:
 			/* restore state machines */
@@ -955,7 +955,7 @@ START:
 
 static int getcxmodem(void) {
 	if (tstc())
-		return (getc());
+		return (getchar());
 	return -1;
 }
 static ulong load_serial_ymodem(ulong offset, int mode)
diff --git a/common/autoboot.c b/common/autoboot.c
index 74f97a05137..e628baffb89 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -117,7 +117,7 @@ static int passwd_abort_sha256(uint64_t etime)
 				return 0;
 			}
 
-			presskey[presskey_len++] = getc();
+			presskey[presskey_len++] = getchar();
 
 			/* Calculate sha256 upon each new char */
 			hash_block(algo_name, (const void *)presskey,
@@ -189,12 +189,12 @@ static int passwd_abort_key(uint64_t etime)
 	do {
 		if (tstc()) {
 			if (presskey_len < presskey_max) {
-				presskey[presskey_len++] = getc();
+				presskey[presskey_len++] = getchar();
 			} else {
 				for (i = 0; i < presskey_max - 1; i++)
 					presskey[i] = presskey[i + 1];
 
-				presskey[i] = getc();
+				presskey[i] = getchar();
 			}
 		}
 
@@ -257,7 +257,7 @@ static int abortboot_single_key(int bootdelay)
 	 * Check if key already pressed
 	 */
 	if (tstc()) {	/* we got a key press	*/
-		(void) getc();  /* consume input	*/
+		getchar();	/* consume input	*/
 		puts("\b\b\b 0");
 		abort = 1;	/* don't auto boot	*/
 	}
@@ -272,7 +272,7 @@ static int abortboot_single_key(int bootdelay)
 
 				abort  = 1;	/* don't auto boot	*/
 				bootdelay = 0;	/* no more delay	*/
-				key = getc(); /* consume input	*/
+				key = getchar();/* consume input	*/
 				if (IS_ENABLED(CONFIG_USE_AUTOBOOT_MENUKEY))
 					menukey = key;
 				break;
diff --git a/common/cli_readline.c b/common/cli_readline.c
index 1f1e28c6d85..47b876285cc 100644
--- a/common/cli_readline.c
+++ b/common/cli_readline.c
@@ -68,7 +68,7 @@ static char *delete_char (char *buffer, char *p, int *colp, int *np, int plen)
 #define CREAD_HIST_CHAR		('!')
 
 #define getcmd_putch(ch)	putc(ch)
-#define getcmd_getch()		getc()
+#define getcmd_getch()		getchar()
 #define getcmd_cbeep()		getcmd_putch('\a')
 
 #define HIST_MAX		20
@@ -571,7 +571,7 @@ int cli_readline_into_buffer(const char *const prompt, char *buffer,
 			return -2;	/* timed out */
 		WATCHDOG_RESET();	/* Trigger watchdog, if needed */
 
-		c = getc();
+		c = getchar();
 
 		/*
 		 * Special character handling
diff --git a/common/console.c b/common/console.c
index 8e50af1f9d2..3348436da6f 100644
--- a/common/console.c
+++ b/common/console.c
@@ -131,7 +131,7 @@ static int console_setfile(int file, struct stdio_dev * dev)
 		 */
 		switch (file) {
 		case stdin:
-			gd->jt->getc = getc;
+			gd->jt->getc = getchar;
 			gd->jt->tstc = tstc;
 			break;
 		case stdout:
@@ -179,7 +179,7 @@ struct stdio_dev **console_devices[MAX_FILES];
 int cd_count[MAX_FILES];
 
 /*
- * This depends on tstc() always being called before getc().
+ * This depends on tstc() always being called before getchar().
  * This is guaranteed to be true because this routine is called
  * only from fgetc() which assures it.
  * No attempt is made to demultiplex multiple input sources.
@@ -404,7 +404,7 @@ int fprintf(int file, const char *fmt, ...)
 
 /** U-Boot INITIAL CONSOLE-COMPATIBLE FUNCTION *****************************/
 
-int getc(void)
+int getchar(void)
 {
 #ifdef CONFIG_DISABLE_CONSOLE
 	if (gd->flags & GD_FLG_DISABLE_CONSOLE)
@@ -663,7 +663,7 @@ int ctrlc(void)
 {
 	if (!ctrlc_disabled && gd->have_console) {
 		if (tstc()) {
-			switch (getc()) {
+			switch (getchar()) {
 			case 0x03:		/* ^C - Control C */
 				ctrlc_was_pressed = 1;
 				return 1;
@@ -685,10 +685,10 @@ int confirm_yesno(void)
 
 	/* Flush input */
 	while (tstc())
-		getc();
+		getchar();
 	i = 0;
 	while (i < sizeof(str_input)) {
-		str_input[i] = getc();
+		str_input[i] = getchar();
 		putc(str_input[i]);
 		if (str_input[i] == '\r')
 			break;
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 284512478f1..e979f780ad0 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -32,7 +32,7 @@ struct ymodem_fit_info {
 
 static int getcymodem(void) {
 	if (tstc())
-		return (getc());
+		return (getchar());
 	return -1;
 }
 
diff --git a/common/xyzModem.c b/common/xyzModem.c
index 6bf2375671d..fc3459ebbaf 100644
--- a/common/xyzModem.c
+++ b/common/xyzModem.c
@@ -72,7 +72,7 @@ CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c)
     }
   if (tstc ())
     {
-      *c = getc ();
+      *c = getchar();
       return 1;
     }
   return 0;
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 84139b85c33..c02badd4a88 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -705,7 +705,7 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 
 	/* Compute it once normally. */
 #ifdef CONFIG_FSL_DDR_INTERACTIVE
-	if (tstc() && (getc() == 'd')) {	/* we got a key press of 'd' */
+	if (tstc() && (getchar() == 'd')) {	/* we got a key press of 'd' */
 		total_memory = fsl_ddr_interactive(pinfo, 0);
 	} else if (fsl_ddr_interactive_env_var_exists()) {
 		total_memory = fsl_ddr_interactive(pinfo, 1);
diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c
index 38390c0d552..5a5d0670461 100644
--- a/drivers/ram/stm32mp1/stm32mp1_interactive.c
+++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c
@@ -394,7 +394,7 @@ bool stm32mp1_ddr_interactive(void *priv,
 		unsigned long start = get_timer(0);
 
 		while (1) {
-			if (tstc() && (getc() == 'd')) {
+			if (tstc() && (getchar() == 'd')) {
 				next_step = STEP_DDR_RESET;
 				break;
 			}
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 0027625ebfd..f3c25d42167 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -413,7 +413,7 @@ static int on_baudrate(const char *name, const char *value, enum env_op op,
 
 		if ((flags & H_INTERACTIVE) != 0)
 			while (1) {
-				if (getc() == '\r')
+				if (getchar() == '\r')
 					break;
 			}
 
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 53358acb81f..355659ba056 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -90,7 +90,7 @@ static int on_baudrate(const char *name, const char *value, enum env_op op,
 
 		if ((flags & H_INTERACTIVE) != 0)
 			while (1) {
-				if (getc() == '\r')
+				if (getchar() == '\r')
 					break;
 			}
 
diff --git a/include/_exports.h b/include/_exports.h
index 1e9ba861088..aeb666c8470 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -8,7 +8,7 @@
 #define EXPORT_FUNC(a, b, c, ...)
 #endif
 	EXPORT_FUNC(get_version, unsigned long, get_version, void)
-	EXPORT_FUNC(getc, int, getc, void)
+	EXPORT_FUNC(getchar, int, getc, void)
 	EXPORT_FUNC(tstc, int, tstc, void)
 	EXPORT_FUNC(putc, void, putc, const char)
 	EXPORT_FUNC(puts, void, puts, const char *)
diff --git a/include/stdio.h b/include/stdio.h
index aedf3744525..039f7df6892 100644
--- a/include/stdio.h
+++ b/include/stdio.h
@@ -5,7 +5,7 @@
 #include <linux/compiler.h>
 
 /* stdin */
-int getc(void);
+int getchar(void);
 int tstc(void);
 
 /* stdout */
diff --git a/lib/charset.c b/lib/charset.c
index a28034ee1f1..5686d6fb59c 100644
--- a/lib/charset.c
+++ b/lib/charset.c
@@ -104,7 +104,7 @@ static u8 read_console(void *data)
 {
 	int ch;
 
-	ch = getc();
+	ch = getchar();
 	if (ch < 0)
 		ch = 0;
 	return ch;
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index 426de779517..011accab789 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -76,7 +76,7 @@ static int term_get_char(s32 *c)
 		if (timer_get_us() > timeout)
 			return 1;
 
-	*c = getc();
+	*c = getchar();
 	return 0;
 }
 
@@ -269,7 +269,7 @@ static int query_console_serial(int *rows, int *cols)
 
 	/* Empty input buffer */
 	while (tstc())
-		getc();
+		getchar();
 
 	/*
 	 * Not all terminals understand CSI [18t for querying the console size.
@@ -634,13 +634,13 @@ static int analyze_modifiers(struct efi_key_state *key_state)
 {
 	int c, mod = 0, ret = 0;
 
-	c = getc();
+	c = getchar();
 
 	if (c != ';') {
 		ret = c;
 		if (c == '~')
 			goto out;
-		c = getc();
+		c = getchar();
 	}
 	for (;;) {
 		switch (c) {
@@ -649,7 +649,7 @@ static int analyze_modifiers(struct efi_key_state *key_state)
 			mod += c - '0';
 		/* fall through */
 		case ';':
-			c = getc();
+			c = getchar();
 			break;
 		default:
 			goto out;
@@ -692,25 +692,25 @@ static efi_status_t efi_cin_read_key(struct efi_key_data *key)
 		 * Xterm Control Sequences
 		 * https://www.xfree86.org/4.8.0/ctlseqs.html
 		 */
-		ch = getc();
+		ch = getchar();
 		switch (ch) {
 		case cESC: /* ESC */
 			pressed_key.scan_code = 23;
 			break;
 		case 'O': /* F1 - F4, End */
-			ch = getc();
+			ch = getchar();
 			/* consider modifiers */
 			if (ch == 'F') { /* End */
 				pressed_key.scan_code = 6;
 				break;
 			} else if (ch < 'P') {
 				set_shift_mask(ch - '0', &key->key_state);
-				ch = getc();
+				ch = getchar();
 			}
 			pressed_key.scan_code = ch - 'P' + 11;
 			break;
 		case '[':
-			ch = getc();
+			ch = getchar();
 			switch (ch) {
 			case 'A'...'D': /* up, down right, left */
 				pressed_key.scan_code = ch - 'A' + 1;
@@ -868,7 +868,7 @@ static void efi_cin_check(void)
 static void efi_cin_empty_buffer(void)
 {
 	while (tstc())
-		getc();
+		getchar();
 	key_available = false;
 }
 
diff --git a/test/dm/usb.c b/test/dm/usb.c
index db4b8ba0f7a..5d6ceefce0b 100644
--- a/test/dm/usb.c
+++ b/test/dm/usb.c
@@ -427,7 +427,7 @@ static int dm_test_usb_keyb(struct unit_test_state *uts)
 
 		for (c = pos->result; *c; ++c) {
 			ut_asserteq(1, tstc());
-			ut_asserteq(*c, getc());
+			ut_asserteq(*c, getchar());
 		}
 		ut_asserteq(0, tstc());
 	}
-- 
cgit v1.3.1


From 8af7bb914f8b2238ea37faa8e59277ba4cb26d37 Mon Sep 17 00:00:00 2001
From: Sean Anderson <seanga2@gmail.com>
Date: Wed, 7 Oct 2020 14:37:44 -0400
Subject: timer: Return count from timer_ops.get_count

No timer drivers return an error from get_count. Instead of possibly
returning an error, just return the count directly.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 arch/riscv/lib/andes_plmt.c       |  6 ++----
 arch/riscv/lib/sifive_clint.c     |  6 ++----
 drivers/timer/ag101p_timer.c      |  5 ++---
 drivers/timer/altera_timer.c      |  6 ++----
 drivers/timer/arc_timer.c         |  6 ++----
 drivers/timer/ast_timer.c         |  6 ++----
 drivers/timer/atcpit100_timer.c   |  5 ++---
 drivers/timer/atmel_pit_timer.c   |  6 ++----
 drivers/timer/cadence-ttc.c       |  6 ++----
 drivers/timer/dw-apb-timer.c      |  6 ++----
 drivers/timer/mchp-pit64b-timer.c |  6 ++----
 drivers/timer/mpc83xx_timer.c     |  6 ++----
 drivers/timer/mtk_timer.c         |  6 ++----
 drivers/timer/nomadik-mtu-timer.c |  6 ++----
 drivers/timer/omap-timer.c        |  6 ++----
 drivers/timer/ostm_timer.c        |  6 ++----
 drivers/timer/riscv_timer.c       | 21 +++++++++------------
 drivers/timer/rockchip_timer.c    |  5 ++---
 drivers/timer/sandbox_timer.c     |  6 ++----
 drivers/timer/sti-timer.c         |  6 ++----
 drivers/timer/stm32_timer.c       |  6 ++----
 drivers/timer/timer-uclass.c      |  3 ++-
 drivers/timer/tsc_timer.c         |  6 ++----
 include/timer.h                   |  9 ++++++---
 24 files changed, 59 insertions(+), 97 deletions(-)

(limited to 'drivers')

diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
index a28c14c1ebf..cec86718c7f 100644
--- a/arch/riscv/lib/andes_plmt.c
+++ b/arch/riscv/lib/andes_plmt.c
@@ -17,11 +17,9 @@
 /* mtime register */
 #define MTIME_REG(base)			((ulong)(base))
 
-static int andes_plmt_get_count(struct udevice *dev, u64 *count)
+static u64 andes_plmt_get_count(struct udevice *dev)
 {
-	*count = readq((void __iomem *)MTIME_REG(dev->priv));
-
-	return 0;
+	return readq((void __iomem *)MTIME_REG(dev->priv));
 }
 
 static const struct timer_ops andes_plmt_ops = {
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index c9704c596fa..a5572cb8255 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -62,11 +62,9 @@ int riscv_get_ipi(int hart, int *pending)
 	return 0;
 }
 
-static int sifive_clint_get_count(struct udevice *dev, u64 *count)
+static u64 sifive_clint_get_count(struct udevice *dev)
 {
-	*count = readq((void __iomem *)MTIME_REG(dev->priv));
-
-	return 0;
+	return readq((void __iomem *)MTIME_REG(dev->priv));
 }
 
 static const struct timer_ops sifive_clint_ops = {
diff --git a/drivers/timer/ag101p_timer.c b/drivers/timer/ag101p_timer.c
index c011906b938..23ad5b2b67a 100644
--- a/drivers/timer/ag101p_timer.c
+++ b/drivers/timer/ag101p_timer.c
@@ -62,14 +62,13 @@ struct atftmr_timer_platdata {
 	struct atftmr_timer_regs *regs;
 };
 
-static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
+static u64 atftmr_timer_get_count(struct udevice *dev)
 {
 	struct atftmr_timer_platdata *plat = dev->platdata;
 	struct atftmr_timer_regs *const regs = plat->regs;
 	u32 val;
 	val = readl(&regs->t3_counter);
-	*count = timer_conv_64(val);
-	return 0;
+	return timer_conv_64(val);
 }
 
 static int atftmr_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c
index 6cb2923e0b6..ccc164ee176 100644
--- a/drivers/timer/altera_timer.c
+++ b/drivers/timer/altera_timer.c
@@ -32,7 +32,7 @@ struct altera_timer_platdata {
 	struct altera_timer_regs *regs;
 };
 
-static int altera_timer_get_count(struct udevice *dev, u64 *count)
+static u64 altera_timer_get_count(struct udevice *dev)
 {
 	struct altera_timer_platdata *plat = dev->platdata;
 	struct altera_timer_regs *const regs = plat->regs;
@@ -44,9 +44,7 @@ static int altera_timer_get_count(struct udevice *dev, u64 *count)
 	/* Read timer value */
 	val = readl(&regs->snapl) & 0xffff;
 	val |= (readl(&regs->snaph) & 0xffff) << 16;
-	*count = timer_conv_64(~val);
-
-	return 0;
+	return timer_conv_64(~val);
 }
 
 static int altera_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/arc_timer.c b/drivers/timer/arc_timer.c
index 8c574ec5af1..2dea9f40cba 100644
--- a/drivers/timer/arc_timer.c
+++ b/drivers/timer/arc_timer.c
@@ -26,7 +26,7 @@ struct arc_timer_priv {
 		uint timer_id;
 };
 
-static int arc_timer_get_count(struct udevice *dev, u64 *count)
+static u64 arc_timer_get_count(struct udevice *dev)
 {
 	u32 val = 0;
 	struct arc_timer_priv *priv = dev_get_priv(dev);
@@ -39,9 +39,7 @@ static int arc_timer_get_count(struct udevice *dev, u64 *count)
 		val = read_aux_reg(ARC_AUX_TIMER1_CNT);
 		break;
 	}
-	*count = timer_conv_64(val);
-
-	return 0;
+	return timer_conv_64(val);
 }
 
 static int arc_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/ast_timer.c b/drivers/timer/ast_timer.c
index e3132497404..35369a4087f 100644
--- a/drivers/timer/ast_timer.c
+++ b/drivers/timer/ast_timer.c
@@ -51,13 +51,11 @@ static int ast_timer_probe(struct udevice *dev)
 	return 0;
 }
 
-static int ast_timer_get_count(struct udevice *dev, u64 *count)
+static u64 ast_timer_get_count(struct udevice *dev)
 {
 	struct ast_timer_priv *priv = dev_get_priv(dev);
 
-	*count = AST_TMC_RELOAD_VAL - readl(&priv->tmc->status);
-
-	return 0;
+	return AST_TMC_RELOAD_VAL - readl(&priv->tmc->status);
 }
 
 static int ast_timer_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/timer/atcpit100_timer.c b/drivers/timer/atcpit100_timer.c
index 5d4ae685092..fcb8a453581 100644
--- a/drivers/timer/atcpit100_timer.c
+++ b/drivers/timer/atcpit100_timer.c
@@ -68,13 +68,12 @@ struct atcpit_timer_platdata {
 	u32 *regs;
 };
 
-static int atcpit_timer_get_count(struct udevice *dev, u64 *count)
+static u64 atcpit_timer_get_count(struct udevice *dev)
 {
 	struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
 	u32 val;
 	val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
-	*count = timer_conv_64(val);
-	return 0;
+	return timer_conv_64(val);
 }
 
 static int atcpit_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c
index 843d670b5e2..9f0ad1d703f 100644
--- a/drivers/timer/atmel_pit_timer.c
+++ b/drivers/timer/atmel_pit_timer.c
@@ -25,15 +25,13 @@ struct atmel_pit_platdata {
 	struct atmel_pit_regs *regs;
 };
 
-static int atmel_pit_get_count(struct udevice *dev, u64 *count)
+static u64 atmel_pit_get_count(struct udevice *dev)
 {
 	struct atmel_pit_platdata *plat = dev_get_platdata(dev);
 	struct atmel_pit_regs *const regs = plat->regs;
 	u32 val = readl(&regs->value_image);
 
-	*count = timer_conv_64(val);
-
-	return 0;
+	return timer_conv_64(val);
 }
 
 static int atmel_pit_probe(struct udevice *dev)
diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c
index e6b6dfe3765..bebb2c2e904 100644
--- a/drivers/timer/cadence-ttc.c
+++ b/drivers/timer/cadence-ttc.c
@@ -57,13 +57,11 @@ ulong timer_get_boot_us(void)
 }
 #endif
 
-static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
+static u64 cadence_ttc_get_count(struct udevice *dev)
 {
 	struct cadence_ttc_priv *priv = dev_get_priv(dev);
 
-	*count = readl(&priv->regs->counter_val1);
-
-	return 0;
+	return readl(&priv->regs->counter_val1);
 }
 
 static int cadence_ttc_probe(struct udevice *dev)
diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c
index 35271b20c89..68bc258131b 100644
--- a/drivers/timer/dw-apb-timer.c
+++ b/drivers/timer/dw-apb-timer.c
@@ -25,7 +25,7 @@ struct dw_apb_timer_priv {
 	struct reset_ctl_bulk resets;
 };
 
-static int dw_apb_timer_get_count(struct udevice *dev, u64 *count)
+static u64 dw_apb_timer_get_count(struct udevice *dev)
 {
 	struct dw_apb_timer_priv *priv = dev_get_priv(dev);
 
@@ -34,9 +34,7 @@ static int dw_apb_timer_get_count(struct udevice *dev, u64 *count)
 	 * requires the count to be incrementing. Invert the
 	 * result.
 	 */
-	*count = timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
-
-	return 0;
+	return timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
 }
 
 static int dw_apb_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/mchp-pit64b-timer.c b/drivers/timer/mchp-pit64b-timer.c
index ead8c9b84ad..ad962098b3d 100644
--- a/drivers/timer/mchp-pit64b-timer.c
+++ b/drivers/timer/mchp-pit64b-timer.c
@@ -27,16 +27,14 @@ struct mchp_pit64b_priv {
 	void __iomem *base;
 };
 
-static int mchp_pit64b_get_count(struct udevice *dev, u64 *count)
+static u64 mchp_pit64b_get_count(struct udevice *dev)
 {
 	struct mchp_pit64b_priv *priv = dev_get_priv(dev);
 
 	u32 lsb = readl(priv->base + MCHP_PIT64B_TLSBR);
 	u32 msb = readl(priv->base + MCHP_PIT64B_TMSBR);
 
-	*count = ((u64)msb << 32) | lsb;
-
-	return 0;
+	return ((u64)msb << 32) | lsb;
 }
 
 static int mchp_pit64b_probe(struct udevice *dev)
diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c
index ad8bb28e8b3..ba7704225a3 100644
--- a/drivers/timer/mpc83xx_timer.c
+++ b/drivers/timer/mpc83xx_timer.c
@@ -187,7 +187,7 @@ void wait_ticks(ulong ticks)
 		WATCHDOG_RESET();
 }
 
-static int mpc83xx_timer_get_count(struct udevice *dev, u64 *count)
+static u64 mpc83xx_timer_get_count(struct udevice *dev)
 {
 	u32 tbu, tbl;
 
@@ -201,9 +201,7 @@ static int mpc83xx_timer_get_count(struct udevice *dev, u64 *count)
 		tbl = mftb();
 	} while (tbu != mftbu());
 
-	*count = (tbu * 0x10000ULL) + tbl;
-
-	return 0;
+	return (tbu * 0x10000ULL) + tbl;
 }
 
 static int mpc83xx_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c
index 69ed521811d..74e9ea34ffa 100644
--- a/drivers/timer/mtk_timer.c
+++ b/drivers/timer/mtk_timer.c
@@ -27,14 +27,12 @@ struct mtk_timer_priv {
 	void __iomem *base;
 };
 
-static int mtk_timer_get_count(struct udevice *dev, u64 *count)
+static u64 mtk_timer_get_count(struct udevice *dev)
 {
 	struct mtk_timer_priv *priv = dev_get_priv(dev);
 	u32 val = readl(priv->base + MTK_GPT4_CNT);
 
-	*count = timer_conv_64(val);
-
-	return 0;
+	return timer_conv_64(val);
 }
 
 static int mtk_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/nomadik-mtu-timer.c b/drivers/timer/nomadik-mtu-timer.c
index 7ff921385a3..d7f7ca4effd 100644
--- a/drivers/timer/nomadik-mtu-timer.c
+++ b/drivers/timer/nomadik-mtu-timer.c
@@ -54,14 +54,12 @@ struct nomadik_mtu_priv {
 	struct nomadik_mtu_timer_regs *timer;
 };
 
-static int nomadik_mtu_get_count(struct udevice *dev, u64 *count)
+static u64 nomadik_mtu_get_count(struct udevice *dev)
 {
 	struct nomadik_mtu_priv *priv = dev_get_priv(dev);
 
 	/* Decrementing counter: invert the value */
-	*count = timer_conv_64(~readl(&priv->timer->cv));
-
-	return 0;
+	return timer_conv_64(~readl(&priv->timer->cv));
 }
 
 static int nomadik_mtu_probe(struct udevice *dev)
diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c
index cf3d27b96bc..4eecb3e64d2 100644
--- a/drivers/timer/omap-timer.c
+++ b/drivers/timer/omap-timer.c
@@ -48,13 +48,11 @@ struct omap_timer_priv {
 	struct omap_gptimer_regs *regs;
 };
 
-static int omap_timer_get_count(struct udevice *dev, u64 *count)
+static u64 omap_timer_get_count(struct udevice *dev)
 {
 	struct omap_timer_priv *priv = dev_get_priv(dev);
 
-	*count = timer_conv_64(readl(&priv->regs->tcrr));
-
-	return 0;
+	return timer_conv_64(readl(&priv->regs->tcrr));
 }
 
 static int omap_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/ostm_timer.c b/drivers/timer/ostm_timer.c
index bea97159ebe..bb0636a0719 100644
--- a/drivers/timer/ostm_timer.c
+++ b/drivers/timer/ostm_timer.c
@@ -27,13 +27,11 @@ struct ostm_priv {
 	fdt_addr_t	regs;
 };
 
-static int ostm_get_count(struct udevice *dev, u64 *count)
+static u64 ostm_get_count(struct udevice *dev)
 {
 	struct ostm_priv *priv = dev_get_priv(dev);
 
-	*count = timer_conv_64(readl(priv->regs + OSTM_CNT));
-
-	return 0;
+	return timer_conv_64(readl(priv->regs + OSTM_CNT));
 }
 
 static int ostm_probe(struct udevice *dev)
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 449fcfcfd59..21ae1840571 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -16,22 +16,19 @@
 #include <timer.h>
 #include <asm/csr.h>
 
-static int riscv_timer_get_count(struct udevice *dev, u64 *count)
+static u64 riscv_timer_get_count(struct udevice *dev)
 {
-	if (IS_ENABLED(CONFIG_64BIT)) {
-		*count = csr_read(CSR_TIME);
-	} else {
-		u32 hi, lo;
+	__maybe_unused u32 hi, lo;
 
-		do {
-			hi = csr_read(CSR_TIMEH);
-			lo = csr_read(CSR_TIME);
-		} while (hi != csr_read(CSR_TIMEH));
+	if (IS_ENABLED(CONFIG_64BIT))
+		return csr_read(CSR_TIME);
 
-		*count = ((u64)hi << 32) | lo;
-	}
+	do {
+		hi = csr_read(CSR_TIMEH);
+		lo = csr_read(CSR_TIME);
+	} while (hi != csr_read(CSR_TIMEH));
 
-	return 0;
+	return ((u64)hi << 32) | lo;
 }
 
 static int riscv_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c
index 7a5a4842527..53cdf09810d 100644
--- a/drivers/timer/rockchip_timer.c
+++ b/drivers/timer/rockchip_timer.c
@@ -88,14 +88,13 @@ ulong timer_get_boot_us(void)
 }
 #endif
 
-static int rockchip_timer_get_count(struct udevice *dev, u64 *count)
+static u64 rockchip_timer_get_count(struct udevice *dev)
 {
 	struct rockchip_timer_priv *priv = dev_get_priv(dev);
 	uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
 
 	/* timers are down-counting */
-	*count = ~0ull - cntr;
-	return 0;
+	return ~0ull - cntr;
 }
 
 static int rockchip_clk_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/timer/sandbox_timer.c b/drivers/timer/sandbox_timer.c
index 6a503c2f153..135c0f38a4d 100644
--- a/drivers/timer/sandbox_timer.c
+++ b/drivers/timer/sandbox_timer.c
@@ -29,11 +29,9 @@ unsigned long notrace timer_early_get_rate(void)
 	return SANDBOX_TIMER_RATE;
 }
 
-static notrace int sandbox_timer_get_count(struct udevice *dev, u64 *count)
+static notrace u64 sandbox_timer_get_count(struct udevice *dev)
 {
-	*count = timer_early_get_count();
-
-	return 0;
+	return timer_early_get_count();
 }
 
 static int sandbox_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/sti-timer.c b/drivers/timer/sti-timer.c
index ff42056abdd..e6843ebb337 100644
--- a/drivers/timer/sti-timer.c
+++ b/drivers/timer/sti-timer.c
@@ -17,7 +17,7 @@ struct sti_timer_priv {
 	struct globaltimer *global_timer;
 };
 
-static int sti_timer_get_count(struct udevice *dev, u64 *count)
+static u64 sti_timer_get_count(struct udevice *dev)
 {
 	struct sti_timer_priv *priv = dev_get_priv(dev);
 	struct globaltimer *global_timer = priv->global_timer;
@@ -34,9 +34,7 @@ static int sti_timer_get_count(struct udevice *dev, u64 *count)
 			old = high;
 	}
 	timer = high;
-	*count = (u64)((timer << 32) | low);
-
-	return 0;
+	return (u64)((timer << 32) | low);
 }
 
 static int sti_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c
index c57fa3f5570..f517d5e61f2 100644
--- a/drivers/timer/stm32_timer.c
+++ b/drivers/timer/stm32_timer.c
@@ -52,14 +52,12 @@ struct stm32_timer_priv {
 	struct stm32_timer_regs *base;
 };
 
-static int stm32_timer_get_count(struct udevice *dev, u64 *count)
+static u64 stm32_timer_get_count(struct udevice *dev)
 {
 	struct stm32_timer_priv *priv = dev_get_priv(dev);
 	struct stm32_timer_regs *regs = priv->base;
 
-	*count = readl(&regs->cnt);
-
-	return 0;
+	return readl(&regs->cnt);
 }
 
 static int stm32_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index f8a092b8cb1..62d0e860e80 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -34,7 +34,8 @@ int notrace timer_get_count(struct udevice *dev, u64 *count)
 	if (!ops->get_count)
 		return -ENOSYS;
 
-	return ops->get_count(dev, count);
+	*count = ops->get_count(dev);
+	return 0;
 }
 
 unsigned long notrace timer_get_rate(struct udevice *dev)
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 93c959ff444..abc0a1da05e 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -386,13 +386,11 @@ void __udelay(unsigned long usec)
 #endif
 }
 
-static int tsc_timer_get_count(struct udevice *dev, u64 *count)
+static u64 tsc_timer_get_count(struct udevice *dev)
 {
 	u64 now_tick = rdtsc();
 
-	*count = now_tick - gd->arch.tsc_base;
-
-	return 0;
+	return now_tick - gd->arch.tsc_base;
 }
 
 static void tsc_timer_ensure_setup(bool early)
diff --git a/include/timer.h b/include/timer.h
index aa9d870619d..a044cb034ed 100644
--- a/include/timer.h
+++ b/include/timer.h
@@ -67,11 +67,14 @@ struct timer_ops {
 	 *
 	 * @dev: The timer device
 	 *
-	 * @count: pointer that returns the current 64-bit timer count
+	 * This function may be called at any time after the driver is probed.
+	 * All necessary initialization must be completed by the time probe()
+	 * returns. The count returned by this functions should be monotonic.
+	 * This function must succeed.
 	 *
-	 * Return: 0 if OK, -ve on error
+	 * Return: The current 64-bit timer count
 	 */
-	int (*get_count)(struct udevice *dev, u64 *count);
+	u64 (*get_count)(struct udevice *dev);
 };
 
 /**
-- 
cgit v1.3.1


From 367ea426a51886f6815e520f8b75a010cfa1bdfb Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Thu, 8 Oct 2020 22:05:09 +0200
Subject: spi: Add Qualcomm QUP SPI controller driver

This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s.

Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW.
FIFO and Block modes are supported, no support for DMA mode is planned.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 MAINTAINERS                              |   1 +
 doc/device-tree-bindings/spi/spi-qup.txt |  33 ++
 drivers/spi/Kconfig                      |  10 +
 drivers/spi/Makefile                     |   1 +
 drivers/spi/spi-qup.c                    | 803 +++++++++++++++++++++++++++++++
 5 files changed, 848 insertions(+)
 create mode 100644 doc/device-tree-bindings/spi/spi-qup.txt
 create mode 100644 drivers/spi/spi-qup.c

(limited to 'drivers')

diff --git a/MAINTAINERS b/MAINTAINERS
index 196d635bddf..d5a418d0878 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -241,6 +241,7 @@ F:	include/dt-bindings/clock/qcom,ipq4019-gcc.h
 F:	include/dt-bindings/reset/qcom,ipq4019-reset.h
 F:	drivers/reset/reset-ipq4019.c
 F:	drivers/phy/phy-qcom-ipq4019-usb.c
+F:	drivers/spi/spi-qup.c
 
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
 M:	Stefan Roese <sr@denx.de>
diff --git a/doc/device-tree-bindings/spi/spi-qup.txt b/doc/device-tree-bindings/spi/spi-qup.txt
new file mode 100644
index 00000000000..3697df26310
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-qup.txt
@@ -0,0 +1,33 @@
+Qualcomm QUP SPI controller Device Tree Bindings
+-------------------------------------------
+
+Required properties:
+- compatible : Should be "qcom,spi-qup-v1.1.1", "qcom,spi-qup-v2.1.1"
+				or "qcom,spi-qup-v2.2.1"
+- reg : Physical base address and size of SPI registers map.
+- clock	: Clock phandle (see clock bindings for details).
+- #address-cells : Number of cells required to define a chip select
+                	address on the SPI bus. Should be set to 1.
+- #size-cells : Should be zero.
+- pinctrl-names : Must be "default"
+- pinctrl-n : At least one pinctrl phandle
+- cs-gpios : Should specify GPIOs used for chipselects.
+				The gpios will be referred to as reg = <index> in the
+				SPI child nodes.
+
+Optional properties:
+- num-cs : total number of chipselects
+
+Example:
+
+	blsp1_spi1: spi@78b5000 {
+		compatible = "qcom,spi-qup-v2.2.1";
+		reg = <0x78b5000 0x600>;
+		clock = <&gcc 23>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "spi";
+		pinctrl-0 = <&blsp_spi0>;
+		num-cs = <2>;
+		cs-gpios = <&soc_gpios 54 GPIO_ACTIVE_HIGH>, <&soc_gpios 4 GPIO_ACTIVE_HIGH>;
+	};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 5df97c80fa5..f7a98525655 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -271,6 +271,16 @@ config PL022_SPI
 	  controller. If you have an embedded system with an AMBA(R)
 	  bus and a PL022 controller, say Y or M here.
 
+config SPI_QUP
+	bool "Qualcomm SPI controller with QUP interface"
+	depends on ARCH_IPQ40XX
+	help
+	  Qualcomm Universal Peripheral (QUP) core is an AHB slave that
+	  provides a common data path (an output FIFO and an input FIFO)
+	  for serial peripheral interface (SPI) mini-core. SPI in master
+	  mode supports up to 50MHz, up to four chip selects, programmable
+	  data path from 4 bits to 32 bits and numerous protocol variants.
+
 config RENESAS_RPC_SPI
 	bool "Renesas RPC SPI driver"
 	depends on RCAR_GEN3 || RZA1
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index b5c9ff1af82..d9b5bd9b794 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o
 obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
 obj-$(CONFIG_PL022_SPI) += pl022_spi.o
+obj-$(CONFIG_SPI_QUP) += spi-qup.o
 obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
 obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
 obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
new file mode 100644
index 00000000000..6f8df55fa56
--- /dev/null
+++ b/drivers/spi/spi-qup.c
@@ -0,0 +1,803 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Qualcomm QUP SPI controller
+ * FIFO and Block modes supported, no DMA
+ * mode support
+ *
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
+ *
+ * Based on stock U-boot and Linux drivers
+ */
+
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/delay.h>
+#include <spi.h>
+
+#define QUP_CONFIG				0x0000
+#define QUP_STATE				0x0004
+#define QUP_IO_M_MODES			0x0008
+#define QUP_SW_RESET			0x000c
+#define QUP_OPERATIONAL			0x0018
+#define QUP_ERROR_FLAGS			0x001c
+#define QUP_ERROR_FLAGS_EN		0x0020
+#define QUP_OPERATIONAL_MASK	0x0028
+#define QUP_HW_VERSION			0x0030
+#define QUP_MX_OUTPUT_CNT		0x0100
+#define QUP_OUTPUT_FIFO			0x0110
+#define QUP_MX_WRITE_CNT		0x0150
+#define QUP_MX_INPUT_CNT		0x0200
+#define QUP_MX_READ_CNT			0x0208
+#define QUP_INPUT_FIFO			0x0218
+
+#define SPI_CONFIG				0x0300
+#define SPI_IO_CONTROL			0x0304
+#define SPI_ERROR_FLAGS			0x0308
+#define SPI_ERROR_FLAGS_EN		0x030c
+
+/* QUP_CONFIG fields */
+#define QUP_CONFIG_SPI_MODE			BIT(8)
+#define QUP_CONFIG_CLOCK_AUTO_GATE	BIT(13)
+#define QUP_CONFIG_NO_INPUT			BIT(7)
+#define QUP_CONFIG_NO_OUTPUT		BIT(6)
+#define QUP_CONFIG_N				0x001f
+
+/* QUP_STATE fields */
+#define QUP_STATE_VALID			BIT(2)
+#define QUP_STATE_RESET			0
+#define QUP_STATE_RUN			1
+#define QUP_STATE_PAUSE			3
+#define QUP_STATE_MASK			3
+#define QUP_STATE_CLEAR			2
+
+/* QUP_IO_M_MODES fields */
+#define QUP_IO_M_PACK_EN		BIT(15)
+#define QUP_IO_M_UNPACK_EN		BIT(14)
+#define QUP_IO_M_INPUT_MODE_MASK_SHIFT	12
+#define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT	10
+#define QUP_IO_M_INPUT_MODE_MASK	(3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
+#define QUP_IO_M_OUTPUT_MODE_MASK	(3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
+
+#define QUP_IO_M_OUTPUT_BLOCK_SIZE(x)	(((x) & (0x03 << 0)) >> 0)
+#define QUP_IO_M_OUTPUT_FIFO_SIZE(x)	(((x) & (0x07 << 2)) >> 2)
+#define QUP_IO_M_INPUT_BLOCK_SIZE(x)	(((x) & (0x03 << 5)) >> 5)
+#define QUP_IO_M_INPUT_FIFO_SIZE(x)	(((x) & (0x07 << 7)) >> 7)
+
+#define QUP_IO_M_MODE_FIFO		0
+#define QUP_IO_M_MODE_BLOCK		1
+#define QUP_IO_M_MODE_DMOV		2
+#define QUP_IO_M_MODE_BAM		3
+
+/* QUP_OPERATIONAL fields */
+#define QUP_OP_IN_BLOCK_READ_REQ	BIT(13)
+#define QUP_OP_OUT_BLOCK_WRITE_REQ	BIT(12)
+#define QUP_OP_MAX_INPUT_DONE_FLAG	BIT(11)
+#define QUP_OP_MAX_OUTPUT_DONE_FLAG	BIT(10)
+#define QUP_OP_IN_SERVICE_FLAG		BIT(9)
+#define QUP_OP_OUT_SERVICE_FLAG		BIT(8)
+#define QUP_OP_IN_FIFO_FULL		BIT(7)
+#define QUP_OP_OUT_FIFO_FULL		BIT(6)
+#define QUP_OP_IN_FIFO_NOT_EMPTY	BIT(5)
+#define QUP_OP_OUT_FIFO_NOT_EMPTY	BIT(4)
+
+/* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
+#define QUP_ERROR_OUTPUT_OVER_RUN	BIT(5)
+#define QUP_ERROR_INPUT_UNDER_RUN	BIT(4)
+#define QUP_ERROR_OUTPUT_UNDER_RUN	BIT(3)
+#define QUP_ERROR_INPUT_OVER_RUN	BIT(2)
+
+/* SPI_CONFIG fields */
+#define SPI_CONFIG_HS_MODE		BIT(10)
+#define SPI_CONFIG_INPUT_FIRST		BIT(9)
+#define SPI_CONFIG_LOOPBACK		BIT(8)
+
+/* SPI_IO_CONTROL fields */
+#define SPI_IO_C_FORCE_CS		BIT(11)
+#define SPI_IO_C_CLK_IDLE_HIGH		BIT(10)
+#define SPI_IO_C_MX_CS_MODE		BIT(8)
+#define SPI_IO_C_CS_N_POLARITY_0	BIT(4)
+#define SPI_IO_C_CS_SELECT(x)		(((x) & 3) << 2)
+#define SPI_IO_C_CS_SELECT_MASK		0x000c
+#define SPI_IO_C_TRISTATE_CS		BIT(1)
+#define SPI_IO_C_NO_TRI_STATE		BIT(0)
+
+/* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
+#define SPI_ERROR_CLK_OVER_RUN		BIT(1)
+#define SPI_ERROR_CLK_UNDER_RUN		BIT(0)
+
+#define SPI_NUM_CHIPSELECTS		4
+
+#define SPI_DELAY_THRESHOLD		1
+#define SPI_DELAY_RETRY			10
+
+#define SPI_RESET_STATE			0
+#define SPI_RUN_STATE			1
+#define SPI_CORE_RESET			0
+#define SPI_CORE_RUNNING		1
+
+#define DUMMY_DATA_VAL			0
+#define TIMEOUT_CNT				100
+
+#define QUP_STATE_VALID_BIT				2
+#define QUP_CONFIG_MINI_CORE_MSK		(0x0F << 8)
+#define QUP_CONFIG_MINI_CORE_SPI		BIT(8)
+#define QUP_CONF_INPUT_MSK				BIT(7)
+#define QUP_CONF_INPUT_ENA				(0 << 7)
+#define QUP_CONF_NO_INPUT				BIT(7)
+#define QUP_CONF_OUTPUT_MSK				BIT(6)
+#define QUP_CONF_OUTPUT_ENA				(0 << 6)
+#define QUP_CONF_NO_OUTPUT				BIT(6)
+#define QUP_STATE_RUN_STATE				0x1
+#define QUP_STATE_RESET_STATE			0x0
+#define QUP_STATE_PAUSE_STATE			0x3
+#define SPI_BIT_WORD_MSK				0x1F
+#define SPI_8_BIT_WORD					0x07
+#define LOOP_BACK_MSK					BIT(8)
+#define NO_LOOP_BACK					(0 << 8)
+#define SLAVE_OPERATION_MSK				BIT(5)
+#define SLAVE_OPERATION					(0 << 5)
+#define CLK_ALWAYS_ON					(0 << 9)
+#define MX_CS_MODE						BIT(8)
+#define CS_POLARITY_MASK				BIT(4)
+#define NO_TRI_STATE					BIT(0)
+#define FORCE_CS_MSK					BIT(11)
+#define FORCE_CS_EN						BIT(11)
+#define FORCE_CS_DIS					(0 << 11)
+#define OUTPUT_BIT_SHIFT_MSK			BIT(16)
+#define OUTPUT_BIT_SHIFT_EN				BIT(16)
+#define INPUT_BLOCK_MODE_MSK			(0x03 << 12)
+#define INPUT_BLOCK_MODE				(0x01 << 12)
+#define OUTPUT_BLOCK_MODE_MSK			(0x03 << 10)
+#define OUTPUT_BLOCK_MODE				(0x01 << 10)
+#define INPUT_BAM_MODE					(0x3 << 12)
+#define OUTPUT_BAM_MODE					(0x3 << 10)
+#define PACK_EN							(0x1 << 15)
+#define UNPACK_EN						(0x1 << 14)
+#define PACK_EN_MSK						(0x1 << 15)
+#define UNPACK_EN_MSK					(0x1 << 14)
+#define OUTPUT_SERVICE_MSK				(0x1 << 8)
+#define INPUT_SERVICE_MSK				(0x1 << 9)
+#define OUTPUT_SERVICE_DIS				(0x1 << 8)
+#define INPUT_SERVICE_DIS				(0x1 << 9)
+#define BLSP0_SPI_DEASSERT_WAIT_REG		0x0310
+#define QUP_DATA_AVAILABLE_FOR_READ		BIT(5)
+#define SPI_INPUT_BLOCK_SIZE			4
+#define SPI_OUTPUT_BLOCK_SIZE			4
+#define SPI_BITLEN_MSK					0x07
+#define MAX_COUNT_SIZE					0xffff
+
+struct qup_spi_priv {
+	phys_addr_t base;
+	struct clk clk;
+	u32 num_cs;
+	struct gpio_desc cs_gpios[SPI_NUM_CHIPSELECTS];
+	bool cs_high;
+	u32 core_state;
+};
+
+static int qup_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
+{
+	struct qup_spi_priv *priv = dev_get_priv(dev);
+
+	debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
+
+	if (cs >= SPI_NUM_CHIPSELECTS)
+		return -ENODEV;
+
+	if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
+		return -EINVAL;
+
+	if (priv->cs_high)
+		enable = !enable;
+
+	return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
+}
+
+/*
+ * Function to write data to OUTPUT FIFO
+ */
+static void qup_spi_write_byte(struct udevice *dev, unsigned char data)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	/* Wait for space in the FIFO */
+	while ((readl(priv->base + QUP_OPERATIONAL) & QUP_OP_OUT_FIFO_FULL))
+		udelay(1);
+
+	/* Write the byte of data */
+	writel(data, priv->base + QUP_OUTPUT_FIFO);
+}
+
+/*
+ * Function to read data from Input FIFO
+ */
+static unsigned char qup_spi_read_byte(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	/* Wait for Data in FIFO */
+	while (!(readl(priv->base + QUP_OPERATIONAL) & QUP_DATA_AVAILABLE_FOR_READ)) {
+		printf("Stuck at FIFO data wait\n");
+		udelay(1);
+	}
+
+	/* Read a byte of data */
+	return readl(priv->base + QUP_INPUT_FIFO) & 0xff;
+}
+
+/*
+ * Function to check wheather Input or Output FIFO
+ * has data to be serviced
+ */
+static int qup_spi_check_fifo_status(struct udevice *dev, u32 reg_addr)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	unsigned int count = TIMEOUT_CNT;
+	unsigned int status_flag;
+	unsigned int val;
+
+	do {
+		val = readl(priv->base + reg_addr);
+		count--;
+		if (count == 0)
+			return -ETIMEDOUT;
+
+		status_flag = ((val & QUP_OP_OUT_SERVICE_FLAG) | (val & QUP_OP_IN_SERVICE_FLAG));
+	} while (!status_flag);
+
+	return 0;
+}
+
+/*
+ * Function to configure Input and Output enable/disable
+ */
+static void qup_spi_enable_io_config(struct udevice *dev, u32 write_cnt, u32 read_cnt)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+
+	if (write_cnt) {
+		clrsetbits_le32(priv->base + QUP_CONFIG,
+				QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
+	} else {
+		clrsetbits_le32(priv->base + QUP_CONFIG,
+				QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
+	}
+
+	if (read_cnt) {
+		clrsetbits_le32(priv->base + QUP_CONFIG,
+				QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
+	} else {
+		clrsetbits_le32(priv->base + QUP_CONFIG,
+				QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
+	}
+}
+
+static int check_bit_state(struct udevice *dev, u32 reg_addr, int bit_num, int val,
+						   int us_delay)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	unsigned int count = TIMEOUT_CNT;
+	unsigned int bit_val = ((readl(priv->base + reg_addr) >> bit_num) & 0x01);
+
+	while (bit_val != val) {
+		count--;
+		if (count == 0)
+			return -ETIMEDOUT;
+		udelay(us_delay);
+		bit_val = ((readl(priv->base + reg_addr) >> bit_num) & 0x01);
+	}
+
+	return 0;
+}
+
+/*
+ * Check whether QUPn State is valid
+ */
+static int check_qup_state_valid(struct udevice *dev)
+{
+	return check_bit_state(dev, QUP_STATE, QUP_STATE_VALID, 1, 1);
+}
+
+/*
+ * Configure QUPn Core state
+ */
+static int qup_spi_config_spi_state(struct udevice *dev, unsigned int state)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	u32 val;
+	int ret;
+
+	ret = check_qup_state_valid(dev);
+	if (ret != 0)
+		return ret;
+
+	switch (state) {
+	case SPI_RUN_STATE:
+		/* Set the state to RUN */
+		val = ((readl(priv->base + QUP_STATE) & ~QUP_STATE_MASK)
+					| QUP_STATE_RUN);
+		writel(val, priv->base + QUP_STATE);
+		ret = check_qup_state_valid(dev);
+		if (ret != 0)
+			return ret;
+		priv->core_state = SPI_CORE_RUNNING;
+		break;
+	case SPI_RESET_STATE:
+		/* Set the state to RESET */
+		val = ((readl(priv->base + QUP_STATE) & ~QUP_STATE_MASK)
+					| QUP_STATE_RESET);
+		writel(val, priv->base + QUP_STATE);
+		ret = check_qup_state_valid(dev);
+		if (ret != 0)
+			return ret;
+		priv->core_state = SPI_CORE_RESET;
+		break;
+	default:
+		printf("Unsupported QUP SPI state: %d\n", state);
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+/*
+ * Function to read bytes number of data from the Input FIFO
+ */
+static int __qup_spi_blsp_spi_read(struct udevice *dev, u8 *data_buffer, unsigned int bytes)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	u32 val;
+	unsigned int i;
+	unsigned int read_bytes = bytes;
+	unsigned int fifo_count;
+	int ret = 0;
+	int state_config;
+
+	/* Configure no of bytes to read */
+	state_config = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
+	if (state_config)
+		return state_config;
+
+	/* Configure input and output enable */
+	qup_spi_enable_io_config(dev, 0, read_bytes);
+
+	writel(bytes, priv->base + QUP_MX_INPUT_CNT);
+
+	state_config = qup_spi_config_spi_state(dev, SPI_RUN_STATE);
+	if (state_config)
+		return state_config;
+
+	while (read_bytes) {
+		ret = qup_spi_check_fifo_status(dev, QUP_OPERATIONAL);
+		if (ret != 0)
+			goto out;
+
+		val = readl(priv->base + QUP_OPERATIONAL);
+		if (val & QUP_OP_IN_SERVICE_FLAG) {
+			/*
+			 * acknowledge to hw that software will
+			 * read input data
+			 */
+			val &= QUP_OP_IN_SERVICE_FLAG;
+			writel(val, priv->base + QUP_OPERATIONAL);
+
+			fifo_count = ((read_bytes > SPI_INPUT_BLOCK_SIZE) ?
+					SPI_INPUT_BLOCK_SIZE : read_bytes);
+
+			for (i = 0; i < fifo_count; i++) {
+				*data_buffer = qup_spi_read_byte(dev);
+				data_buffer++;
+				read_bytes--;
+			}
+		}
+	}
+
+out:
+	/*
+	 * Put the SPI Core back in the Reset State
+	 * to end the transfer
+	 */
+	(void)qup_spi_config_spi_state(dev, SPI_RESET_STATE);
+
+	return ret;
+}
+
+static int qup_spi_blsp_spi_read(struct udevice *dev, u8 *data_buffer, unsigned int bytes)
+{
+	int length, ret;
+
+	while (bytes) {
+		length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
+
+		ret = __qup_spi_blsp_spi_read(dev, data_buffer, length);
+		if (ret != 0)
+			return ret;
+
+		data_buffer += length;
+		bytes -= length;
+	}
+
+	return 0;
+}
+
+/*
+ * Function to write data to the Output FIFO
+ */
+static int __qup_blsp_spi_write(struct udevice *dev, const u8 *cmd_buffer, unsigned int bytes)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	u32 val;
+	unsigned int i;
+	unsigned int write_len = bytes;
+	unsigned int read_len = bytes;
+	unsigned int fifo_count;
+	int ret = 0;
+	int state_config;
+
+	state_config = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
+	if (state_config)
+		return state_config;
+
+	writel(bytes, priv->base + QUP_MX_OUTPUT_CNT);
+	writel(bytes, priv->base + QUP_MX_INPUT_CNT);
+	state_config = qup_spi_config_spi_state(dev, SPI_RUN_STATE);
+	if (state_config)
+		return state_config;
+
+	/* Configure input and output enable */
+	qup_spi_enable_io_config(dev, write_len, read_len);
+
+	/*
+	 * read_len considered to ensure that we read the dummy data for the
+	 * write we performed. This is needed to ensure with WR-RD transaction
+	 * to get the actual data on the subsequent read cycle that happens
+	 */
+	while (write_len || read_len) {
+		ret = qup_spi_check_fifo_status(dev, QUP_OPERATIONAL);
+		if (ret != 0)
+			goto out;
+
+		val = readl(priv->base + QUP_OPERATIONAL);
+		if (val & QUP_OP_OUT_SERVICE_FLAG) {
+			/*
+			 * acknowledge to hw that software will write
+			 * expected output data
+			 */
+			val &= QUP_OP_OUT_SERVICE_FLAG;
+			writel(val, priv->base + QUP_OPERATIONAL);
+
+			if (write_len > SPI_OUTPUT_BLOCK_SIZE)
+				fifo_count = SPI_OUTPUT_BLOCK_SIZE;
+			else
+				fifo_count = write_len;
+
+			for (i = 0; i < fifo_count; i++) {
+				/* Write actual data to output FIFO */
+				qup_spi_write_byte(dev, *cmd_buffer);
+				cmd_buffer++;
+				write_len--;
+			}
+		}
+		if (val & QUP_OP_IN_SERVICE_FLAG) {
+			/*
+			 * acknowledge to hw that software
+			 * will read input data
+			 */
+			val &= QUP_OP_IN_SERVICE_FLAG;
+			writel(val, priv->base + QUP_OPERATIONAL);
+
+			if (read_len > SPI_INPUT_BLOCK_SIZE)
+				fifo_count = SPI_INPUT_BLOCK_SIZE;
+			else
+				fifo_count = read_len;
+
+			for (i = 0; i < fifo_count; i++) {
+				/* Read dummy data for the data written */
+				(void)qup_spi_read_byte(dev);
+
+				/* Decrement the write count after reading the
+				 * dummy data from the device. This is to make
+				 * sure we read dummy data before we write the
+				 * data to fifo
+				 */
+				read_len--;
+			}
+		}
+	}
+out:
+	/*
+	 * Put the SPI Core back in the Reset State
+	 * to end the transfer
+	 */
+	(void)qup_spi_config_spi_state(dev, SPI_RESET_STATE);
+
+	return ret;
+}
+
+static int qup_spi_blsp_spi_write(struct udevice *dev, const u8 *cmd_buffer, unsigned int bytes)
+{
+	int length, ret;
+
+	while (bytes) {
+		length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
+
+		ret = __qup_blsp_spi_write(dev, cmd_buffer, length);
+		if (ret != 0)
+			return ret;
+
+		cmd_buffer += length;
+		bytes -= length;
+	}
+
+	return 0;
+}
+
+static int qup_spi_set_speed(struct udevice *dev, uint speed)
+{
+	return 0;
+}
+
+static int qup_spi_set_mode(struct udevice *dev, uint mode)
+{
+	struct qup_spi_priv *priv = dev_get_priv(dev);
+	unsigned int clk_idle_state;
+	unsigned int input_first_mode;
+	u32 val;
+
+	switch (mode) {
+	case SPI_MODE_0:
+		clk_idle_state = 0;
+		input_first_mode = SPI_CONFIG_INPUT_FIRST;
+		break;
+	case SPI_MODE_1:
+		clk_idle_state = 0;
+		input_first_mode = 0;
+		break;
+	case SPI_MODE_2:
+		clk_idle_state = 1;
+		input_first_mode = SPI_CONFIG_INPUT_FIRST;
+		break;
+	case SPI_MODE_3:
+		clk_idle_state = 1;
+		input_first_mode = 0;
+		break;
+	default:
+		printf("Unsupported spi mode: %d\n", mode);
+		return -EINVAL;
+	}
+
+	if (mode & SPI_CS_HIGH)
+		priv->cs_high = true;
+	else
+		priv->cs_high = false;
+
+	val = readl(priv->base + SPI_CONFIG);
+	val |= input_first_mode;
+	writel(val, priv->base + SPI_CONFIG);
+
+	val = readl(priv->base + SPI_IO_CONTROL);
+	if (clk_idle_state)
+		val |= SPI_IO_C_CLK_IDLE_HIGH;
+	else
+		val &= ~SPI_IO_C_CLK_IDLE_HIGH;
+
+	writel(val, priv->base + SPI_IO_CONTROL);
+
+	return 0;
+}
+
+static void qup_spi_reset(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+
+	/* Driver may not be probed yet */
+	if (!priv)
+		return;
+
+	writel(0x1, priv->base + QUP_SW_RESET);
+	udelay(5);
+}
+
+static int qup_spi_hw_init(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	int ret;
+
+	/* QUPn module configuration */
+	qup_spi_reset(dev);
+
+	/* Set the QUPn state */
+	ret = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
+	if (ret)
+		return ret;
+
+	/*
+	 * Configure Mini core to SPI core with Input Output enabled,
+	 * SPI master, N = 8 bits
+	 */
+	clrsetbits_le32(priv->base + QUP_CONFIG, (QUP_CONFIG_MINI_CORE_MSK |
+						QUP_CONF_INPUT_MSK |
+						QUP_CONF_OUTPUT_MSK |
+						SPI_BIT_WORD_MSK),
+						(QUP_CONFIG_MINI_CORE_SPI |
+						QUP_CONF_INPUT_ENA |
+						QUP_CONF_OUTPUT_ENA |
+						SPI_8_BIT_WORD));
+
+	/*
+	 * Configure Input first SPI protocol,
+	 * SPI master mode and no loopback
+	 */
+	clrsetbits_le32(priv->base + SPI_CONFIG, (LOOP_BACK_MSK |
+						SLAVE_OPERATION_MSK),
+						(NO_LOOP_BACK |
+						SLAVE_OPERATION));
+
+	/*
+	 * Configure SPI IO Control Register
+	 * CLK_ALWAYS_ON = 0
+	 * MX_CS_MODE = 0
+	 * NO_TRI_STATE = 1
+	 */
+	writel((CLK_ALWAYS_ON | NO_TRI_STATE), priv->base + SPI_IO_CONTROL);
+
+	/*
+	 * Configure SPI IO Modes.
+	 * OUTPUT_BIT_SHIFT_EN = 1
+	 * INPUT_MODE = Block Mode
+	 * OUTPUT MODE = Block Mode
+	 */
+
+	clrsetbits_le32(priv->base + QUP_IO_M_MODES, (OUTPUT_BIT_SHIFT_MSK |
+				INPUT_BLOCK_MODE_MSK |
+				OUTPUT_BLOCK_MODE_MSK),
+				(OUTPUT_BIT_SHIFT_EN |
+				INPUT_BLOCK_MODE |
+				OUTPUT_BLOCK_MODE));
+
+	/* Disable Error mask */
+	writel(0, priv->base + SPI_ERROR_FLAGS_EN);
+	writel(0, priv->base + QUP_ERROR_FLAGS_EN);
+	writel(0, priv->base + BLSP0_SPI_DEASSERT_WAIT_REG);
+
+	return ret;
+}
+
+static int qup_spi_claim_bus(struct udevice *dev)
+{
+	int ret;
+
+	ret = qup_spi_hw_init(dev);
+	if (ret)
+		return -EIO;
+
+	return 0;
+}
+
+static int qup_spi_release_bus(struct udevice *dev)
+{
+	/* Reset the SPI hardware */
+	qup_spi_reset(dev);
+
+	return 0;
+}
+
+static int qup_spi_xfer(struct udevice *dev, unsigned int bitlen,
+						const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+	unsigned int len;
+	const u8 *txp = dout;
+	u8 *rxp = din;
+	int ret = 0;
+
+	if (bitlen & SPI_BITLEN_MSK) {
+		printf("Invalid bit length\n");
+		return -EINVAL;
+	}
+
+	len = bitlen >> 3;
+
+	if (flags & SPI_XFER_BEGIN) {
+		ret = qup_spi_hw_init(dev);
+		if (ret != 0)
+			return ret;
+
+		ret = qup_spi_set_cs(bus, slave_plat->cs, false);
+		if (ret != 0)
+			return ret;
+	}
+
+	if (dout != NULL) {
+		ret = qup_spi_blsp_spi_write(dev, txp, len);
+		if (ret != 0)
+			return ret;
+	}
+
+	if (din != NULL) {
+		ret = qup_spi_blsp_spi_read(dev, rxp, len);
+		if (ret != 0)
+			return ret;
+	}
+
+	if (flags & SPI_XFER_END) {
+		ret = qup_spi_set_cs(bus, slave_plat->cs, true);
+		if (ret != 0)
+			return ret;
+	}
+
+	return ret;
+}
+
+static int qup_spi_probe(struct udevice *dev)
+{
+	struct qup_spi_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret)
+		return ret;
+
+	ret = clk_enable(&priv->clk);
+	if (ret < 0)
+		return ret;
+
+	priv->num_cs = dev_read_u32_default(dev, "num-cs", 1);
+
+	ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
+					priv->num_cs, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret < 0) {
+		printf("Can't get %s cs gpios: %d\n", dev->name, ret);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct dm_spi_ops qup_spi_ops = {
+	.claim_bus	= qup_spi_claim_bus,
+	.release_bus	= qup_spi_release_bus,
+	.xfer		= qup_spi_xfer,
+	.set_speed	= qup_spi_set_speed,
+	.set_mode	= qup_spi_set_mode,
+	/*
+	 * cs_info is not needed, since we require all chip selects to be
+	 * in the device tree explicitly
+	 */
+};
+
+static const struct udevice_id qup_spi_ids[] = {
+	{ .compatible = "qcom,spi-qup-v1.1.1", },
+	{ .compatible = "qcom,spi-qup-v2.1.1", },
+	{ .compatible = "qcom,spi-qup-v2.2.1", },
+	{ }
+};
+
+U_BOOT_DRIVER(spi_qup) = {
+	.name	= "spi_qup",
+	.id	= UCLASS_SPI,
+	.of_match = qup_spi_ids,
+	.ops	= &qup_spi_ops,
+	.priv_auto_alloc_size	= sizeof(struct qup_spi_priv),
+	.probe	= qup_spi_probe,
+};
-- 
cgit v1.3.1


From 975151d056acef155643bdb57b29a1a28ba5590f Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Thu, 8 Oct 2020 22:05:11 +0200
Subject: net: Add IPQ40xx MDIO driver

This adds the driver for the IPQ40xx built-in MDIO.
This will be needed to support future PHY driver.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 MAINTAINERS                |   1 +
 drivers/net/Kconfig        |   7 +++
 drivers/net/Makefile       |   1 +
 drivers/net/mdio-ipq4019.c | 146 +++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 155 insertions(+)
 create mode 100644 drivers/net/mdio-ipq4019.c

(limited to 'drivers')

diff --git a/MAINTAINERS b/MAINTAINERS
index d5a418d0878..a80045fcd74 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -242,6 +242,7 @@ F:	include/dt-bindings/reset/qcom,ipq4019-reset.h
 F:	drivers/reset/reset-ipq4019.c
 F:	drivers/phy/phy-qcom-ipq4019-usb.c
 F:	drivers/spi/spi-qup.c
+F:	drivers/net/mdio-ipq4019.c
 
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
 M:	Stefan Roese <sr@denx.de>
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 2beec2da415..3a5e0368805 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -732,6 +732,13 @@ config MDIO_MUX_I2CREG
 	  an I2C chip.  The board it was developed for uses a mux controlled by
 	  on-board FPGA which in turn is accessed as a chip over I2C.
 
+config MDIO_IPQ4019
+	bool "Qualcomm IPQ4019 MDIO interface support"
+	depends on DM_MDIO
+	help
+	  This driver supports the MDIO interface found in Qualcomm
+	  IPQ40xx series Soc-s.
+
 config MVMDIO
 	bool "Marvell MDIO interface support"
 	depends on DM_MDIO
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 9f7a79ecb13..e3bdda359dc 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_LAN91C96) += lan91c96.o
 obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
 obj-$(CONFIG_MACB) += macb.o
 obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
+obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o
 obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o
 obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
 obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
diff --git a/drivers/net/mdio-ipq4019.c b/drivers/net/mdio-ipq4019.c
new file mode 100644
index 00000000000..bc68e1d5065
--- /dev/null
+++ b/drivers/net/mdio-ipq4019.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm IPQ4019 MDIO driver
+ *
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ * Based on Linux driver
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+#include <miiphy.h>
+#include <phy.h>
+
+#define MDIO_MODE_REG               0x40
+#define MDIO_ADDR_REG               0x44
+#define MDIO_DATA_WRITE_REG         0x48
+#define MDIO_DATA_READ_REG          0x4c
+#define MDIO_CMD_REG                0x50
+#define MDIO_CMD_ACCESS_BUSY        BIT(16)
+#define MDIO_CMD_ACCESS_START       BIT(8)
+#define MDIO_CMD_ACCESS_CODE_READ   0
+#define MDIO_CMD_ACCESS_CODE_WRITE  1
+
+/* 0 = Clause 22, 1 = Clause 45 */
+#define MDIO_MODE_BIT               BIT(8)
+
+#define IPQ4019_MDIO_TIMEOUT    10000
+#define IPQ4019_MDIO_SLEEP      10
+
+struct ipq4019_mdio_priv {
+	phys_addr_t mdio_base;
+};
+
+static int ipq4019_mdio_wait_busy(struct ipq4019_mdio_priv *priv)
+{
+	unsigned int busy;
+
+	return readl_poll_sleep_timeout(priv->mdio_base + MDIO_CMD_REG, busy,
+				  (busy & MDIO_CMD_ACCESS_BUSY) == 0, IPQ4019_MDIO_SLEEP,
+				  IPQ4019_MDIO_TIMEOUT);
+}
+
+int ipq4019_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+	struct ipq4019_mdio_priv *priv = dev_get_priv(dev);
+	unsigned int cmd;
+
+	if (ipq4019_mdio_wait_busy(priv))
+		return -ETIMEDOUT;
+
+	/* Issue the phy address and reg */
+	writel((addr << 8) | reg, priv->mdio_base + MDIO_ADDR_REG);
+
+	cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ;
+
+	/* Issue read command */
+	writel(cmd, priv->mdio_base + MDIO_CMD_REG);
+
+	/* Wait read complete */
+	if (ipq4019_mdio_wait_busy(priv))
+		return -ETIMEDOUT;
+
+	/* Read and return data */
+	return readl(priv->mdio_base + MDIO_DATA_READ_REG);
+}
+
+int ipq4019_mdio_write(struct udevice *dev, int addr, int devad,
+					  int reg, u16 val)
+{
+	struct ipq4019_mdio_priv *priv = dev_get_priv(dev);
+	unsigned int cmd;
+
+	if (ipq4019_mdio_wait_busy(priv))
+		return -ETIMEDOUT;
+
+	/* Issue the phy addreass and reg */
+	writel((addr << 8) | reg, priv->mdio_base + MDIO_ADDR_REG);
+
+	/* Issue write data */
+	writel(val, priv->mdio_base + MDIO_DATA_WRITE_REG);
+
+	cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE;
+
+	/* Issue write command */
+	writel(cmd, priv->mdio_base + MDIO_CMD_REG);
+
+	/* Wait for write complete */
+
+	if (ipq4019_mdio_wait_busy(priv))
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static const struct mdio_ops ipq4019_mdio_ops = {
+	.read = ipq4019_mdio_read,
+	.write = ipq4019_mdio_write,
+};
+
+static int ipq4019_mdio_bind(struct udevice *dev)
+{
+	if (ofnode_valid(dev->node))
+		device_set_name(dev, ofnode_get_name(dev->node));
+
+	return 0;
+}
+
+static int ipq4019_mdio_probe(struct udevice *dev)
+{
+	struct ipq4019_mdio_priv *priv = dev_get_priv(dev);
+	unsigned int data;
+
+	priv->mdio_base = dev_read_addr(dev);
+	if (priv->mdio_base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	/* Enter Clause 22 mode */
+	data = readl(priv->mdio_base + MDIO_MODE_REG);
+	data &= ~MDIO_MODE_BIT;
+	writel(data, priv->mdio_base + MDIO_MODE_REG);
+
+	return 0;
+}
+
+static const struct udevice_id ipq4019_mdio_ids[] = {
+	{ .compatible = "qcom,ipq4019-mdio", },
+	{ }
+};
+
+U_BOOT_DRIVER(ipq4019_mdio) = {
+	.name           = "ipq4019_mdio",
+	.id             = UCLASS_MDIO,
+	.of_match       = ipq4019_mdio_ids,
+	.bind           = ipq4019_mdio_bind,
+	.probe          = ipq4019_mdio_probe,
+	.ops            = &ipq4019_mdio_ops,
+	.priv_auto_alloc_size   = sizeof(struct ipq4019_mdio_priv),
+};
-- 
cgit v1.3.1


From 033ec636fcb67d6f58a045a50977f8f1449378a9 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Thu, 8 Oct 2020 22:05:13 +0200
Subject: rng: Add Qualcomm MSM PRNG driver

Add support for the hardware pseudo random number generator found in Qualcomm SoC-s.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 MAINTAINERS           |   1 +
 drivers/rng/Kconfig   |   7 +++
 drivers/rng/Makefile  |   1 +
 drivers/rng/msm_rng.c | 143 ++++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 152 insertions(+)
 create mode 100644 drivers/rng/msm_rng.c

(limited to 'drivers')

diff --git a/MAINTAINERS b/MAINTAINERS
index a80045fcd74..fc4fad46eee 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -243,6 +243,7 @@ F:	drivers/reset/reset-ipq4019.c
 F:	drivers/phy/phy-qcom-ipq4019-usb.c
 F:	drivers/spi/spi-qup.c
 F:	drivers/net/mdio-ipq4019.c
+F:	drivers/rng/msm_rng.c
 
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
 M:	Stefan Roese <sr@denx.de>
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index e4b22d79ebc..11001c8ae7c 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -24,6 +24,13 @@ config RNG_SANDBOX
 	  Enable random number generator for sandbox. This is an
 	  emulation of a rng device.
 
+config RNG_MSM
+	bool "Qualcomm SoCs Random Number Generator support"
+	depends on DM_RNG
+	help
+	  This driver provides support for the Random Number
+	  Generator hardware found on Qualcomm SoCs.
+
 config RNG_STM32MP1
 	bool "Enable random number generator for STM32MP1"
 	depends on ARCH_STM32MP
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 44a00039173..89534068820 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -6,5 +6,6 @@
 obj-$(CONFIG_DM_RNG) += rng-uclass.o
 obj-$(CONFIG_RNG_MESON) += meson-rng.o
 obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
+obj-$(CONFIG_RNG_MSM) += msm_rng.o
 obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
 obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
diff --git a/drivers/rng/msm_rng.c b/drivers/rng/msm_rng.c
new file mode 100644
index 00000000000..d51119303a6
--- /dev/null
+++ b/drivers/rng/msm_rng.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PRNG driver for Qualcomm IPQ40xx
+ *
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ * Based on Linux driver
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <rng.h>
+
+/* Device specific register offsets */
+#define PRNG_DATA_OUT		0x0000
+#define PRNG_STATUS			0x0004
+#define PRNG_LFSR_CFG		0x0100
+#define PRNG_CONFIG			0x0104
+
+/* Device specific register masks and config values */
+#define PRNG_LFSR_CFG_MASK		0x0000ffff
+#define PRNG_LFSR_CFG_CLOCKS	0x0000dddd
+#define PRNG_CONFIG_HW_ENABLE	BIT(1)
+#define PRNG_STATUS_DATA_AVAIL	BIT(0)
+
+#define MAX_HW_FIFO_DEPTH		16
+#define MAX_HW_FIFO_SIZE		(MAX_HW_FIFO_DEPTH * 4)
+#define WORD_SZ					4
+
+struct msm_rng_priv {
+	phys_addr_t base;
+	struct clk clk;
+};
+
+static int msm_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	struct msm_rng_priv *priv = dev_get_priv(dev);
+	size_t currsize = 0;
+	u32 *retdata = data;
+	size_t maxsize;
+	u32 val;
+
+	/* calculate max size bytes to transfer back to caller */
+	maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, len);
+
+	/* read random data from hardware */
+	do {
+		val = readl_relaxed(priv->base + PRNG_STATUS);
+		if (!(val & PRNG_STATUS_DATA_AVAIL))
+			break;
+
+		val = readl_relaxed(priv->base + PRNG_DATA_OUT);
+		if (!val)
+			break;
+
+		*retdata++ = val;
+		currsize += WORD_SZ;
+
+		/* make sure we stay on 32bit boundary */
+		if ((maxsize - currsize) < WORD_SZ)
+			break;
+	} while (currsize < maxsize);
+
+	return 0;
+}
+
+static int msm_rng_enable(struct msm_rng_priv *priv, int enable)
+{
+	u32 val;
+
+	if (enable) {
+		/* Enable PRNG only if it is not already enabled */
+		val = readl_relaxed(priv->base + PRNG_CONFIG);
+		if (val & PRNG_CONFIG_HW_ENABLE) {
+			val = readl_relaxed(priv->base + PRNG_LFSR_CFG);
+			val &= ~PRNG_LFSR_CFG_MASK;
+			val |= PRNG_LFSR_CFG_CLOCKS;
+			writel(val, priv->base + PRNG_LFSR_CFG);
+
+			val = readl_relaxed(priv->base + PRNG_CONFIG);
+			val |= PRNG_CONFIG_HW_ENABLE;
+			writel(val, priv->base + PRNG_CONFIG);
+		}
+	} else {
+		val = readl_relaxed(priv->base + PRNG_CONFIG);
+		val &= ~PRNG_CONFIG_HW_ENABLE;
+		writel(val, priv->base + PRNG_CONFIG);
+	}
+
+	return 0;
+}
+
+static int msm_rng_probe(struct udevice *dev)
+{
+	struct msm_rng_priv *priv = dev_get_priv(dev);
+
+	int ret;
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret)
+		return ret;
+
+	ret = clk_enable(&priv->clk);
+	if (ret < 0)
+		return ret;
+
+	return msm_rng_enable(priv, 1);
+}
+
+static int msm_rng_remove(struct udevice *dev)
+{
+	struct msm_rng_priv *priv = dev_get_priv(dev);
+
+	return msm_rng_enable(priv, 0);
+}
+
+static const struct dm_rng_ops msm_rng_ops = {
+	.read = msm_rng_read,
+};
+
+static const struct udevice_id msm_rng_match[] = {
+	{ .compatible = "qcom,prng", },
+	{},
+};
+
+U_BOOT_DRIVER(msm_rng) = {
+	.name = "msm-rng",
+	.id = UCLASS_RNG,
+	.of_match = msm_rng_match,
+	.ops = &msm_rng_ops,
+	.probe = msm_rng_probe,
+	.remove = msm_rng_remove,
+	.priv_auto_alloc_size = sizeof(struct msm_rng_priv),
+};
-- 
cgit v1.3.1


From 64dbd86b56846262cebfa4eea6c509783f80d365 Mon Sep 17 00:00:00 2001
From: Naoki Hayama <naoki.hayama@lineo.co.jp>
Date: Mon, 12 Oct 2020 18:35:22 +0900
Subject: mmc: Fix comment typo

%s/occured/occurred/

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
---
 drivers/mmc/mmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index c46fa4efc5a..a47700e313c 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2192,7 +2192,7 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
 				return 0;
 error:
 			mmc_set_signal_voltage(mmc, old_voltage);
-			/* if an error occured, revert to a safer bus mode */
+			/* if an error occurred, revert to a safer bus mode */
 			mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 				   EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
 			mmc_select_mode(mmc, MMC_LEGACY);
-- 
cgit v1.3.1


From ef38b42364515d138cb8bea82c23d36ceac8fd71 Mon Sep 17 00:00:00 2001
From: Naoki Hayama <naoki.hayama@lineo.co.jp>
Date: Mon, 12 Oct 2020 18:35:55 +0900
Subject: ARM: mvebu: a38x: Fix comment typo

%s/occured/occurred/

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Stefan Roese <sr@denx.de>
---
 drivers/ddr/marvell/a38x/ddr_ml_wrapper.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
index 5bf32399211..ac9250f74ed 100644
--- a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
+++ b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
@@ -107,7 +107,7 @@
 #define MV_NO_RESOURCE	(0x13)	/* Resource not available (memory ...)   */
 #define MV_FULL		(0x14)	/* Item is full (Queue or table etc...)  */
 #define MV_EMPTY	(0x15)	/* Item is empty (Queue or table etc...) */
-#define MV_INIT_ERROR	(0x16)	/* Error occured while INIT process      */
+#define MV_INIT_ERROR	(0x16)	/* Error occurred while INIT process     */
 #define MV_HW_ERROR	(0x17)	/* Hardware error                        */
 #define MV_TX_ERROR	(0x18)	/* Transmit operation not succeeded      */
 #define MV_RX_ERROR	(0x19)	/* Recieve operation not succeeded       */
-- 
cgit v1.3.1


From fa181d1a95a2851873f586139b7ca3c35c551498 Mon Sep 17 00:00:00 2001
From: Dario Binacchi <dariobin@libero.it>
Date: Wed, 14 Oct 2020 23:42:17 +0200
Subject: clk: ccf: replace the get_rate helper

The 12d152620d commit fixed the get_rate helper because the set_parent
one did not re-parent the clock device to the new parent. The 4d139f3838
commit allows you to remove this workaround by calling the
clk_get_parent_rate routine.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
---
 drivers/clk/clk-mux.c | 26 +-------------------------
 1 file changed, 1 insertion(+), 25 deletions(-)

(limited to 'drivers')

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 7a5ee7a45fc..f1becd20d8b 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -150,32 +150,8 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
 	return 0;
 }
 
-static ulong clk_mux_get_rate(struct clk *clk)
-{
-	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
-			dev_get_clk_ptr(clk->dev) : clk);
-	struct udevice *parent;
-	struct clk *pclk;
-	int err, index;
-
-	index = clk_mux_get_parent(clk);
-	if (index >= mux->num_parents)
-		return -EFAULT;
-
-	err = uclass_get_device_by_name(UCLASS_CLK, mux->parent_names[index],
-					&parent);
-	if (err)
-		return err;
-
-	pclk = dev_get_clk_ptr(parent);
-	if (!pclk)
-		return -ENODEV;
-
-	return clk_get_rate(pclk);
-}
-
 const struct clk_ops clk_mux_ops = {
-	.get_rate = clk_mux_get_rate,
+	.get_rate = clk_generic_get_rate,
 	.set_parent = clk_mux_set_parent,
 };
 
-- 
cgit v1.3.1


From 611a28ce271164941aac02feea19f1d87bd1cf32 Mon Sep 17 00:00:00 2001
From: "Chia-Wei, Wang" <chiawei_wang@aspeedtech.com>
Date: Thu, 15 Oct 2020 10:25:13 +0800
Subject: reset: ast2500: Use SCU for reset control

The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.

This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.

The Kconfig description is also updated accordingly.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 arch/arm/dts/ast2500-u-boot.dtsi          |  7 +--
 drivers/reset/Kconfig                     |  9 ++-
 drivers/reset/ast2500-reset.c             | 97 ++++++++++++++++---------------
 include/dt-bindings/reset/ast2500-reset.h | 73 ++++++++++++-----------
 4 files changed, 97 insertions(+), 89 deletions(-)

(limited to 'drivers')

diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 51a5244766c..ea60e4c8db9 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -16,7 +16,6 @@
 	rst: reset-controller {
 		u-boot,dm-pre-reloc;
 		compatible = "aspeed,ast2500-reset";
-		aspeed,wdt = <&wdt1>;
 		#reset-cells = <1>;
 	};
 
@@ -27,7 +26,7 @@
 			0x1e6e0200 0x1d4 >;
 		#reset-cells = <1>;
 		clocks = <&scu ASPEED_CLK_MPLL>;
-		resets = <&rst AST_RESET_SDRAM>;
+		resets = <&rst ASPEED_RESET_SDRAM>;
 	};
 
 	ahb {
@@ -41,7 +40,7 @@
 				reg = <0x1e740100>;
 				#reset-cells = <1>;
 				clocks = <&scu ASPEED_CLK_SDIO>;
-				resets = <&rst AST_RESET_SDIO>;
+				resets = <&rst ASPEED_RESET_SDIO>;
 			};
 
 			sdhci1: sdhci@1e740200 {
@@ -49,7 +48,7 @@
 				reg = <0x1e740200>;
 				#reset-cells = <1>;
 				clocks = <&scu ASPEED_CLK_SDIO>;
-				resets = <&rst AST_RESET_SDIO>;
+				resets = <&rst ASPEED_RESET_SDIO>;
 			};
 		};
 
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index b60e11f98b2..8b243fdcc66 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -74,13 +74,12 @@ config RESET_UNIPHIER
 
 config AST2500_RESET
 	bool "Reset controller driver for AST2500 SoCs"
-	depends on DM_RESET && WDT_ASPEED
+	depends on DM_RESET
 	default y if ASPEED_AST2500
 	help
-	  Support for reset controller on AST2500 SoC. This controller uses
-	  watchdog to reset different peripherals and thus only supports
-	  resets that are supported by watchdog. The main limitation though
-	  is that some reset signals, like I2C or MISC reset multiple devices.
+	  Support for reset controller on AST2500 SoC.
+	  Say Y if you want to control reset signals of different peripherals
+	  through System Control Unit (SCU).
 
 config RESET_ROCKCHIP
 	bool "Reset controller driver for Rockchip SoCs"
diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
index beb5cd8fa8c..e7b5c7decab 100644
--- a/drivers/reset/ast2500-reset.c
+++ b/drivers/reset/ast2500-reset.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2017 Google, Inc
+ * Copyright 2020 ASPEED Technology Inc.
  */
 
 #include <common.h>
@@ -9,28 +10,26 @@
 #include <misc.h>
 #include <reset.h>
 #include <reset-uclass.h>
-#include <wdt.h>
+#include <linux/err.h>
 #include <asm/io.h>
 #include <asm/arch/scu_ast2500.h>
-#include <asm/arch/wdt.h>
 
 struct ast2500_reset_priv {
-	/* WDT used to perform resets. */
-	struct udevice *wdt;
 	struct ast2500_scu *scu;
 };
 
-static int ast2500_ofdata_to_platdata(struct udevice *dev)
+static int ast2500_reset_request(struct reset_ctl *reset_ctl)
 {
-	struct ast2500_reset_priv *priv = dev_get_priv(dev);
-	int ret;
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
 
-	ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
-					   &priv->wdt);
-	if (ret) {
-		debug("%s: can't find WDT for reset controller", __func__);
-		return ret;
-	}
+	return 0;
+}
+
+static int ast2500_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
 
 	return 0;
 }
@@ -38,47 +37,52 @@ static int ast2500_ofdata_to_platdata(struct udevice *dev)
 static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
 {
 	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
-	u32 reset_mode, reset_mask;
-	bool reset_sdram;
-	int ret;
-
-	/*
-	 * To reset SDRAM, a specifal flag in SYSRESET register
-	 * needs to be enabled first
-	 */
-	reset_mode = ast_reset_mode_from_flags(reset_ctl->id);
-	reset_mask = ast_reset_mask_from_flags(reset_ctl->id);
-	reset_sdram = reset_mode == WDT_CTRL_RESET_SOC &&
-		(reset_mask & WDT_RESET_SDRAM);
-
-	if (reset_sdram) {
-		ast_scu_unlock(priv->scu);
-		setbits_le32(&priv->scu->sysreset_ctrl1,
-			     SCU_SYSRESET_SDRAM_WDT);
-		ret = wdt_expire_now(priv->wdt, reset_ctl->id);
-		clrbits_le32(&priv->scu->sysreset_ctrl1,
-			     SCU_SYSRESET_SDRAM_WDT);
-		ast_scu_lock(priv->scu);
-	} else {
-		ret = wdt_expire_now(priv->wdt, reset_ctl->id);
-	}
+	struct ast2500_scu *scu = priv->scu;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
 
-	return ret;
+	if (reset_ctl->id < 32)
+		setbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
+	else
+		setbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
+
+	return 0;
 }
 
-static int ast2500_reset_request(struct reset_ctl *reset_ctl)
+static int ast2500_reset_deassert(struct reset_ctl *reset_ctl)
 {
-	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
-	      reset_ctl->dev, reset_ctl->id);
+	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2500_scu *scu = priv->scu;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		clrbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
+	else
+		clrbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
 
 	return 0;
 }
 
 static int ast2500_reset_probe(struct udevice *dev)
 {
+	int rc;
 	struct ast2500_reset_priv *priv = dev_get_priv(dev);
+	struct udevice *scu_dev;
+
+	/* get SCU base from clock device */
+	rc = uclass_get_device_by_driver(UCLASS_CLK,
+					 DM_GET_DRIVER(aspeed_ast2500_scu), &scu_dev);
+	if (rc) {
+		debug("%s: clock device not found, rc=%d\n", __func__, rc);
+		return rc;
+	}
 
-	priv->scu = ast_get_scu();
+	priv->scu = devfdt_get_addr_ptr(scu_dev);
+	if (IS_ERR_OR_NULL(priv->scu)) {
+		debug("%s: invalid SCU base pointer\n", __func__);
+		return PTR_ERR(priv->scu);
+	}
 
 	return 0;
 }
@@ -89,16 +93,17 @@ static const struct udevice_id ast2500_reset_ids[] = {
 };
 
 struct reset_ops ast2500_reset_ops = {
-	.rst_assert = ast2500_reset_assert,
 	.request = ast2500_reset_request,
+	.rfree = ast2500_reset_free,
+	.rst_assert = ast2500_reset_assert,
+	.rst_deassert = ast2500_reset_deassert,
 };
 
 U_BOOT_DRIVER(ast2500_reset) = {
-	.name		= "ast2500_reset",
-	.id		= UCLASS_RESET,
+	.name = "ast2500_reset",
+	.id = UCLASS_RESET,
 	.of_match = ast2500_reset_ids,
 	.probe = ast2500_reset_probe,
 	.ops = &ast2500_reset_ops,
-	.ofdata_to_platdata = ast2500_ofdata_to_platdata,
 	.priv_auto_alloc_size = sizeof(struct ast2500_reset_priv),
 };
diff --git a/include/dt-bindings/reset/ast2500-reset.h b/include/dt-bindings/reset/ast2500-reset.h
index d1b6b23fc11..cc85a31edf9 100644
--- a/include/dt-bindings/reset/ast2500-reset.h
+++ b/include/dt-bindings/reset/ast2500-reset.h
@@ -1,44 +1,49 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2017 Google, Inc
+ * Copyright 2020 ASPEED Technology Inc.
  */
 
 #ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
 #define _ABI_MACH_ASPEED_AST2500_RESET_H_
 
-/*
- * The values are intentionally layed out as flags in
- * WDT reset parameter.
- */
-
-#define AST_RESET_SOC			0
-#define AST_RESET_CHIP			1
-#define AST_RESET_CPU			(1 << 1)
-#define AST_RESET_ARM			(1 << 2)
-#define AST_RESET_COPROC		(1 << 3)
-#define AST_RESET_SDRAM			(1 << 4)
-#define AST_RESET_AHB			(1 << 5)
-#define AST_RESET_I2C			(1 << 6)
-#define AST_RESET_MAC1			(1 << 7)
-#define AST_RESET_MAC2			(1 << 8)
-#define AST_RESET_GCRT			(1 << 9)
-#define AST_RESET_USB20			(1 << 10)
-#define AST_RESET_USB11_HOST		(1 << 11)
-#define AST_RESET_USB11_HID		(1 << 12)
-#define AST_RESET_VIDEO			(1 << 13)
-#define AST_RESET_HAC			(1 << 14)
-#define AST_RESET_LPC			(1 << 15)
-#define AST_RESET_SDIO			(1 << 16)
-#define AST_RESET_MIC			(1 << 17)
-#define AST_RESET_CRT2D			(1 << 18)
-#define AST_RESET_PWM			(1 << 19)
-#define AST_RESET_PECI			(1 << 20)
-#define AST_RESET_JTAG			(1 << 21)
-#define AST_RESET_ADC			(1 << 22)
-#define AST_RESET_GPIO			(1 << 23)
-#define AST_RESET_MCTP			(1 << 24)
-#define AST_RESET_XDMA			(1 << 25)
-#define AST_RESET_SPI			(1 << 26)
-#define AST_RESET_MISC			(1 << 27)
+#define ASPEED_RESET_CRT1		(37)
+#define ASPEED_RESET_RESERVED36		(36)
+#define ASPEED_RESET_RESERVED35		(35)
+#define ASPEED_RESET_RESERVED34		(34)
+#define ASPEED_RESET_RESERVED33		(33)
+#define ASPEED_RESET_RESERVED32		(32)
+#define ASPEED_RESET_RESERVED31		(31)
+#define ASPEED_RESET_RESERVED30		(30)
+#define ASPEED_RESET_RESERVED29		(29)
+#define ASPEED_RESET_RESERVED28		(28)
+#define ASPEED_RESET_RESERVED27		(27)
+#define ASPEED_RESET_RESERVED26		(26)
+#define ASPEED_RESET_XDMA		(25)
+#define ASPEED_RESET_MCTP		(24)
+#define ASPEED_RESET_ADC		(23)
+#define ASPEED_RESET_JTAG_MASTER	(22)
+#define ASPEED_RESET_RESERVED21		(21)
+#define ASPEED_RESET_RESERVED20		(20)
+#define ASPEED_RESET_RESERVED19		(19)
+#define ASPEED_RESET_MIC		(18)
+#define ASPEED_RESET_RESERVED17		(17)
+#define ASPEED_RESET_SDIO		(16)
+#define ASPEED_RESET_UHCI		(15)
+#define ASPEED_RESET_EHCI_P1		(14)
+#define ASPEED_RESET_CRT		(13)
+#define ASPEED_RESET_MAC2		(12)
+#define ASPEED_RESET_MAC1		(11)
+#define ASPEED_RESET_PECI		(10)
+#define ASPEED_RESET_PWM		(9)
+#define ASPEED_RESET_PCI_VGA		(8)
+#define ASPEED_RESET_2D			(7)
+#define ASPEED_RESET_VIDEO		(6)
+#define ASPEED_RESET_LPC_ESPI		(5)
+#define ASPEED_RESET_HACE		(4)
+#define ASPEED_RESET_EHCI_P2		(3)
+#define ASPEED_RESET_I2C		(2)
+#define ASPEED_RESET_AHB		(1)
+#define ASPEED_RESET_SDRAM		(0)
 
 #endif  /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */
-- 
cgit v1.3.1


From b2424cd2f4337cd36aa635d3bc52485f150d8ae6 Mon Sep 17 00:00:00 2001
From: "Chia-Wei, Wang" <chiawei_wang@aspeedtech.com>
Date: Thu, 15 Oct 2020 10:25:14 +0800
Subject: cosmetic: reset: ast2500: Rename driver and configs

1. Rename AST2500 reset driver from ast2500-reset.c
   to reset-ast2500.c
2. Rename AST2500 reset kconfig option from AST2500_RESET
   to RESET_AST2500

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 drivers/reset/Kconfig         |   2 +-
 drivers/reset/Makefile        |   2 +-
 drivers/reset/ast2500-reset.c | 109 ------------------------------------------
 drivers/reset/reset-ast2500.c | 109 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 111 insertions(+), 111 deletions(-)
 delete mode 100644 drivers/reset/ast2500-reset.c
 create mode 100644 drivers/reset/reset-ast2500.c

(limited to 'drivers')

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 8b243fdcc66..33c2736554e 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -72,7 +72,7 @@ config RESET_UNIPHIER
 	  Say Y if you want to control reset signals provided by System Control
 	  block, Media I/O block, Peripheral Block.
 
-config AST2500_RESET
+config RESET_AST2500
 	bool "Reset controller driver for AST2500 SoCs"
 	depends on DM_RESET
 	default y if ASPEED_AST2500
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 10a7973f823..fa52aa33291 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
-obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
+obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
 obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
deleted file mode 100644
index e7b5c7decab..00000000000
--- a/drivers/reset/ast2500-reset.c
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2017 Google, Inc
- * Copyright 2020 ASPEED Technology Inc.
- */
-
-#include <common.h>
-#include <dm.h>
-#include <log.h>
-#include <misc.h>
-#include <reset.h>
-#include <reset-uclass.h>
-#include <linux/err.h>
-#include <asm/io.h>
-#include <asm/arch/scu_ast2500.h>
-
-struct ast2500_reset_priv {
-	struct ast2500_scu *scu;
-};
-
-static int ast2500_reset_request(struct reset_ctl *reset_ctl)
-{
-	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
-	      reset_ctl->dev, reset_ctl->id);
-
-	return 0;
-}
-
-static int ast2500_reset_free(struct reset_ctl *reset_ctl)
-{
-	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
-	      reset_ctl->dev, reset_ctl->id);
-
-	return 0;
-}
-
-static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
-{
-	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
-	struct ast2500_scu *scu = priv->scu;
-
-	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
-
-	if (reset_ctl->id < 32)
-		setbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
-	else
-		setbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
-
-	return 0;
-}
-
-static int ast2500_reset_deassert(struct reset_ctl *reset_ctl)
-{
-	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
-	struct ast2500_scu *scu = priv->scu;
-
-	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
-
-	if (reset_ctl->id < 32)
-		clrbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
-	else
-		clrbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
-
-	return 0;
-}
-
-static int ast2500_reset_probe(struct udevice *dev)
-{
-	int rc;
-	struct ast2500_reset_priv *priv = dev_get_priv(dev);
-	struct udevice *scu_dev;
-
-	/* get SCU base from clock device */
-	rc = uclass_get_device_by_driver(UCLASS_CLK,
-					 DM_GET_DRIVER(aspeed_ast2500_scu), &scu_dev);
-	if (rc) {
-		debug("%s: clock device not found, rc=%d\n", __func__, rc);
-		return rc;
-	}
-
-	priv->scu = devfdt_get_addr_ptr(scu_dev);
-	if (IS_ERR_OR_NULL(priv->scu)) {
-		debug("%s: invalid SCU base pointer\n", __func__);
-		return PTR_ERR(priv->scu);
-	}
-
-	return 0;
-}
-
-static const struct udevice_id ast2500_reset_ids[] = {
-	{ .compatible = "aspeed,ast2500-reset" },
-	{ }
-};
-
-struct reset_ops ast2500_reset_ops = {
-	.request = ast2500_reset_request,
-	.rfree = ast2500_reset_free,
-	.rst_assert = ast2500_reset_assert,
-	.rst_deassert = ast2500_reset_deassert,
-};
-
-U_BOOT_DRIVER(ast2500_reset) = {
-	.name = "ast2500_reset",
-	.id = UCLASS_RESET,
-	.of_match = ast2500_reset_ids,
-	.probe = ast2500_reset_probe,
-	.ops = &ast2500_reset_ops,
-	.priv_auto_alloc_size = sizeof(struct ast2500_reset_priv),
-};
diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c
new file mode 100644
index 00000000000..e7b5c7decab
--- /dev/null
+++ b/drivers/reset/reset-ast2500.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017 Google, Inc
+ * Copyright 2020 ASPEED Technology Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <misc.h>
+#include <reset.h>
+#include <reset-uclass.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include <asm/arch/scu_ast2500.h>
+
+struct ast2500_reset_priv {
+	struct ast2500_scu *scu;
+};
+
+static int ast2500_reset_request(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int ast2500_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2500_scu *scu = priv->scu;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		setbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
+	else
+		setbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
+
+	return 0;
+}
+
+static int ast2500_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2500_scu *scu = priv->scu;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		clrbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
+	else
+		clrbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
+
+	return 0;
+}
+
+static int ast2500_reset_probe(struct udevice *dev)
+{
+	int rc;
+	struct ast2500_reset_priv *priv = dev_get_priv(dev);
+	struct udevice *scu_dev;
+
+	/* get SCU base from clock device */
+	rc = uclass_get_device_by_driver(UCLASS_CLK,
+					 DM_GET_DRIVER(aspeed_ast2500_scu), &scu_dev);
+	if (rc) {
+		debug("%s: clock device not found, rc=%d\n", __func__, rc);
+		return rc;
+	}
+
+	priv->scu = devfdt_get_addr_ptr(scu_dev);
+	if (IS_ERR_OR_NULL(priv->scu)) {
+		debug("%s: invalid SCU base pointer\n", __func__);
+		return PTR_ERR(priv->scu);
+	}
+
+	return 0;
+}
+
+static const struct udevice_id ast2500_reset_ids[] = {
+	{ .compatible = "aspeed,ast2500-reset" },
+	{ }
+};
+
+struct reset_ops ast2500_reset_ops = {
+	.request = ast2500_reset_request,
+	.rfree = ast2500_reset_free,
+	.rst_assert = ast2500_reset_assert,
+	.rst_deassert = ast2500_reset_deassert,
+};
+
+U_BOOT_DRIVER(ast2500_reset) = {
+	.name = "ast2500_reset",
+	.id = UCLASS_RESET,
+	.of_match = ast2500_reset_ids,
+	.probe = ast2500_reset_probe,
+	.ops = &ast2500_reset_ops,
+	.priv_auto_alloc_size = sizeof(struct ast2500_reset_priv),
+};
-- 
cgit v1.3.1


From 18426bf02217de2e9bb2b41eaa74d769892c55ef Mon Sep 17 00:00:00 2001
From: AKASHI Takahiro <takahiro.akashi@linaro.org>
Date: Thu, 15 Oct 2020 13:25:13 +0900
Subject: serial: serial_xen: print U-Boot banner and others

At present, DM_FLAG_PRE_RELOC is set only if !OF_CONTROL.
It doesn't make sense for this para-virtualized driver.

With this patch applied, you will be able to see early boot messages:

U-Boot 2020.10-00001-ge442e71a6c52-dirty (Oct 15 2020 - 11:02:25 +0900)
xenguest

Xen virtual CPU
Model: XENVM-4.15
DRAM:  128 MiB
PVBLOCK:
(XEN) gnttab_mark_dirty not implemented yet
pvblock: 0
In:    hypervisor
Out:   hypervisor
Err:   hypervisor
xenguest#

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/serial/serial_xen.c | 2 --
 1 file changed, 2 deletions(-)

(limited to 'drivers')

diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c
index ba6504b9479..ed191829f05 100644
--- a/drivers/serial/serial_xen.c
+++ b/drivers/serial/serial_xen.c
@@ -175,8 +175,6 @@ U_BOOT_DRIVER(serial_xen) = {
 	.priv_auto_alloc_size	= sizeof(struct xen_uart_priv),
 	.probe			= xen_serial_probe,
 	.ops			= &xen_serial_ops,
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
 	.flags			= DM_FLAG_PRE_RELOC,
-#endif
 };
 
-- 
cgit v1.3.1


From 82e21b391bd315f6fe0e0b79326af8a141e9cca7 Mon Sep 17 00:00:00 2001
From: AKASHI Takahiro <takahiro.akashi@linaro.org>
Date: Thu, 15 Oct 2020 13:25:16 +0900
Subject: serial: serial_xen: add DEBUG_UART support

By using a hypervisor call, we can implement DEBUG_UART on xen.
This will allow us to see messages even earlier than serial_init().

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
---
 drivers/serial/Kconfig      | 14 +++++++++++---
 drivers/serial/serial_xen.c | 20 ++++++++++++++++++++
 2 files changed, 31 insertions(+), 3 deletions(-)

(limited to 'drivers')

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index b4805a2e4ea..b6ba702bd35 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -401,11 +401,19 @@ config DEBUG_UART_MTK
 	  driver will be available until the real driver model serial is
 	  running.
 
+config DEBUG_UART_XEN
+	bool "XEN Hypervisor Console"
+	depends on XEN_SERIAL
+	help
+	  Select this to enable a debug UART using the serial_xen driver. You
+	  will not have to provide any parameters to make this work. The driver
+          will be available until the real driver-model serial is running.
+
 endchoice
 
 config DEBUG_UART_BASE
 	hex "Base address of UART"
-	depends on DEBUG_UART
+	depends on DEBUG_UART && !DEBUG_UART_XEN
 	default 0 if DEBUG_UART_SANDBOX
 	help
 	  This is the base address of your UART for memory-mapped UARTs.
@@ -415,7 +423,7 @@ config DEBUG_UART_BASE
 
 config DEBUG_UART_CLOCK
 	int "UART input clock"
-	depends on DEBUG_UART
+	depends on DEBUG_UART && !DEBUG_UART_XEN
 	default 0 if DEBUG_UART_SANDBOX
 	help
 	  The UART input clock determines the speed of the internal UART
@@ -427,7 +435,7 @@ config DEBUG_UART_CLOCK
 
 config DEBUG_UART_SHIFT
 	int "UART register shift"
-	depends on DEBUG_UART
+	depends on DEBUG_UART && !DEBUG_UART_XEN
 	default 0 if DEBUG_UART
 	help
 	  Some UARTs (notably ns16550) support different register layouts
diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c
index ed191829f05..34c90ece40f 100644
--- a/drivers/serial/serial_xen.c
+++ b/drivers/serial/serial_xen.c
@@ -5,6 +5,7 @@
  */
 #include <common.h>
 #include <cpu_func.h>
+#include <debug_uart.h>
 #include <dm.h>
 #include <serial.h>
 #include <watchdog.h>
@@ -15,11 +16,14 @@
 #include <xen/events.h>
 
 #include <xen/interface/sched.h>
+#include <xen/interface/xen.h>
 #include <xen/interface/hvm/hvm_op.h>
 #include <xen/interface/hvm/params.h>
 #include <xen/interface/io/console.h>
 #include <xen/interface/io/ring.h>
 
+#include <asm/xen/hypercall.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 u32 console_evtchn;
@@ -178,3 +182,19 @@ U_BOOT_DRIVER(serial_xen) = {
 	.flags			= DM_FLAG_PRE_RELOC,
 };
 
+#if defined(CONFIG_DEBUG_UART_XEN)
+static inline void _debug_uart_init(void) {}
+
+static inline void _debug_uart_putc(int c)
+{
+#if CONFIG_IS_ENABLED(ARM)
+	xen_debug_putc(c);
+#else
+	/* the type cast should work on LE only */
+	HYPERVISOR_console_io(CONSOLEIO_write, 1, (char *)&ch);
+#endif
+}
+
+DEBUG_UART_FUNCS
+
+#endif
-- 
cgit v1.3.1


From 0d67576713ef01739617a4e8a9bc6a032a0f7b80 Mon Sep 17 00:00:00 2001
From: Fabien Parent <fparent@baylibre.com>
Date: Thu, 15 Oct 2020 18:38:18 +0200
Subject: mmc: mtk-sd: change some dev_err into dev_dbg

dev_err has been used for debugging and a few dev_err message are
printed for normal code execution. Make them dev_dbg instead.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/mmc/mtk-sd.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'drivers')

diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index 30fe7a0aa20..4f9fa7d0ec3 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -1171,7 +1171,7 @@ skip_fall:
 			internal_delay |= (1 << i);
 	}
 
-	dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
+	dev_dbg(dev, "Final internal delay: 0x%x\n", internal_delay);
 
 	internal_delay_phase = get_best_delay(dev, host, internal_delay);
 	clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
@@ -1179,7 +1179,7 @@ skip_fall:
 			MSDC_PAD_TUNE_CMDRRDLY_S);
 
 skip_internal:
-	dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
+	dev_dbg(dev, "Final cmd pad delay: %x\n", final_delay);
 	return final_delay == 0xff ? -EIO : 0;
 }
 
@@ -1265,7 +1265,7 @@ skip_fall:
 				host->hs200_write_int_delay <<
 				MSDC_PAD_TUNE_DATWRDLY_S);
 
-	dev_err(dev, "Final data pad delay: %x\n", final_delay);
+	dev_dbg(dev, "Final data pad delay: %x\n", final_delay);
 
 	return final_delay == 0xff ? -EIO : 0;
 }
-- 
cgit v1.3.1


From dddfde5401ed5ad82c996b35b61dc4a45bb4e2b3 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Fri, 16 Oct 2020 10:41:46 +0200
Subject: rtc: move pcf8563 to Kconfig

add Kconfig option for pcf8563 driver and
run tools/moveconfig.py

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
---
 configs/ethernut5_defconfig                  | 1 +
 configs/ids8313_defconfig                    | 1 +
 configs/ls1012aqds_qspi_defconfig            | 1 +
 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 1 +
 configs/ls1012aqds_tfa_defconfig             | 1 +
 configs/ls2081ardb_defconfig                 | 1 +
 drivers/rtc/Kconfig                          | 6 ++++++
 include/configs/ethernut5.h                  | 1 -
 include/configs/ids8313.h                    | 1 -
 include/configs/ls1012aqds.h                 | 1 -
 include/configs/ls2080ardb.h                 | 1 -
 scripts/config_whitelist.txt                 | 1 -
 12 files changed, 12 insertions(+), 5 deletions(-)

(limited to 'drivers')

diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index 9a079402784..9f57f34eab9 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -66,6 +66,7 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_DATAFLASH=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
+CONFIG_RTC_PCF8563=y
 CONFIG_DM_SERIAL=y
 CONFIG_ATMEL_USART=y
 CONFIG_SPI=y
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 383c8cd0e33..3f5824d76fc 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -175,5 +175,6 @@ CONFIG_PHY_VITESSE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
 # CONFIG_PCI is not set
+CONFIG_RTC_PCF8563=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 3c431af81bc..1e8e3110f37 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -72,6 +72,7 @@ CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
+CONFIG_RTC_PCF8563=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index 2e79536e5c5..dc405c725a5 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -61,6 +61,7 @@ CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
+CONFIG_RTC_PCF8563=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index 10d9a67d86c..bf032162024 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -72,6 +72,7 @@ CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
+CONFIG_RTC_PCF8563=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
index f5cb3bc7dab..39e5d7d4216 100644
--- a/configs/ls2081ardb_defconfig
+++ b/configs/ls2081ardb_defconfig
@@ -51,6 +51,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_RTC_PCF8563=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
 CONFIG_CONS_INDEX=2
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 59e2fc44ba9..63662001c26 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -75,6 +75,12 @@ config RTC_ISL1208
 	  This driver supports reading and writing the RTC/calendar and detects
 	  total power failures.
 
+config RTC_PCF8563
+	tristate "Philips PCF8563"
+	help
+	  If you say yes here you get support for the Philips PCF8563 RTC
+	  and compatible chips.
+
 config RTC_RV3029
 	bool "Enable RV3029 driver"
 	depends on DM_RTC
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index d121b395dfe..b513b4bc68a 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -92,7 +92,6 @@
 
 /* RTC */
 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
-#define CONFIG_RTC_PCF8563
 #define CONFIG_SYS_I2C_RTC_ADDR		0x51
 #endif
 
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index bcd8aee7c32..362e2892d19 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -168,7 +168,6 @@
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
-#define CONFIG_RTC_PCF8563
 #define CONFIG_SYS_I2C_RTC_ADDR	0x51
 
 /*
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 9498a03f405..df2a613eaf3 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -50,7 +50,6 @@
 * RTC configuration
 */
 #define RTC
-#define CONFIG_RTC_PCF8563 1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 
 /* EEPROM */
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index b7a7dc0a64a..ab4214c2653 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -279,7 +279,6 @@ unsigned long get_board_sys_clk(void);
  */
 #define RTC
 #ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_RTC_PCF8563		1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 #else
 #define CONFIG_RTC_DS3231               1
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index dc4f0b050c9..dabe3293362 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1412,7 +1412,6 @@ CONFIG_RTC_MC13XXX
 CONFIG_RTC_MCFRRTC
 CONFIG_RTC_MCP79411
 CONFIG_RTC_MXS
-CONFIG_RTC_PCF8563
 CONFIG_RTC_PT7C4338
 CONFIG_RUN_FROM_DDR0
 CONFIG_RUN_FROM_DDR1
-- 
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