From 7ebb4479b07ff294eb4d76e420753a0349f7c93b Mon Sep 17 00:00:00 2001 From: Ulf Samuelsson Date: Thu, 24 May 2007 12:12:47 +0200 Subject: [PATCH][NAND] Define the Vendor Id for Micron NAND Flash Signed-off-by: Ulf Samuelsson Signed-off-by: Ladislav Michl Signed-off-by: Stefan Roese --- drivers/nand/nand_ids.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c index 8b58736bc10..70fdfd3f500 100644 --- a/drivers/nand/nand_ids.c +++ b/drivers/nand/nand_ids.c @@ -123,6 +123,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_NATIONAL, "National"}, {NAND_MFR_RENESAS, "Renesas"}, {NAND_MFR_STMICRO, "ST Micro"}, + {NAND_MFR_MICRON, "Micron"}, {0x0, "Unknown"} }; #endif -- cgit v1.3.1 From f539edc076cfe52bff919dd512ba8d7af0e22092 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Thu, 24 May 2007 15:52:25 -0700 Subject: cosmetic changes to bcm570x driver This is a cosmetic only changes submission. It affects files relevant to bcm570x driver. the commands used to generate this change was cd drivers Lindent -pcs -l80 bcm570x.c bcm570x_lm.h bcm570x_mm.h tigon3.c tigon3.h The BMW target (the only one using this chip so far) builds cleanly, the `before and after' generated object files for drivers/bcm570x.c and drivers/tigon3.o are identical as reported by objdump -d Signed-off-by: Vadim Bendebury Signed-off-by: Ben Warren --- drivers/bcm570x.c | 2324 ++++++------ drivers/bcm570x_lm.h | 207 +- drivers/bcm570x_mm.h | 58 +- drivers/tigon3.c | 9700 ++++++++++++++++++++++++-------------------------- drivers/tigon3.h | 3749 ++++++++++--------- 5 files changed, 7669 insertions(+), 8369 deletions(-) (limited to 'drivers') diff --git a/drivers/bcm570x.c b/drivers/bcm570x.c index 5f632a64692..7aeb5474b13 100644 --- a/drivers/bcm570x.c +++ b/drivers/bcm570x.c @@ -18,7 +18,6 @@ #include #include - /* * PCI Registers and definitions. */ @@ -31,7 +30,6 @@ #define BCM570X_MBAR 0x80100000 #define BCM570X_ILINE 1 - #define SECOND_USEC 1000000 #define MAX_PACKET_SIZE 1600 #define MAX_UNITS 4 @@ -39,62 +37,61 @@ /* Globals to this module */ int initialized = 0; unsigned int ioBase = 0; -volatile PLM_DEVICE_BLOCK pDevice = NULL; /* 570x softc */ -volatile PUM_DEVICE_BLOCK pUmDevice = NULL; +volatile PLM_DEVICE_BLOCK pDevice = NULL; /* 570x softc */ +volatile PUM_DEVICE_BLOCK pUmDevice = NULL; /* Used to pass the full-duplex flag, etc. */ -int line_speed[MAX_UNITS] = {0,0,0,0}; -static int full_duplex[MAX_UNITS] = {1,1,1,1}; -static int rx_flow_control[MAX_UNITS] = {0,0,0,0}; -static int tx_flow_control[MAX_UNITS] = {0,0,0,0}; -static int auto_flow_control[MAX_UNITS] = {0,0,0,0}; -static int tx_checksum[MAX_UNITS] = {1,1,1,1}; -static int rx_checksum[MAX_UNITS] = {1,1,1,1}; -static int auto_speed[MAX_UNITS] = {1,1,1,1}; +int line_speed[MAX_UNITS] = { 0, 0, 0, 0 }; +static int full_duplex[MAX_UNITS] = { 1, 1, 1, 1 }; +static int rx_flow_control[MAX_UNITS] = { 0, 0, 0, 0 }; +static int tx_flow_control[MAX_UNITS] = { 0, 0, 0, 0 }; +static int auto_flow_control[MAX_UNITS] = { 0, 0, 0, 0 }; +static int tx_checksum[MAX_UNITS] = { 1, 1, 1, 1 }; +static int rx_checksum[MAX_UNITS] = { 1, 1, 1, 1 }; +static int auto_speed[MAX_UNITS] = { 1, 1, 1, 1 }; #if JUMBO_FRAMES /* Jumbo MTU for interfaces. */ -static int mtu[MAX_UNITS] = {0,0,0,0}; +static int mtu[MAX_UNITS] = { 0, 0, 0, 0 }; #endif /* Turn on Wake-on lan for a device unit */ -static int enable_wol[MAX_UNITS] = {0,0,0,0}; +static int enable_wol[MAX_UNITS] = { 0, 0, 0, 0 }; #define TX_DESC_CNT DEFAULT_TX_PACKET_DESC_COUNT static unsigned int tx_pkt_desc_cnt[MAX_UNITS] = - {TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT, TX_DESC_CNT}; + { TX_DESC_CNT, TX_DESC_CNT, TX_DESC_CNT, TX_DESC_CNT }; #define RX_DESC_CNT DEFAULT_STD_RCV_DESC_COUNT static unsigned int rx_std_desc_cnt[MAX_UNITS] = - {RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT}; + { RX_DESC_CNT, RX_DESC_CNT, RX_DESC_CNT, RX_DESC_CNT }; -static unsigned int rx_adaptive_coalesce[MAX_UNITS] = {1,1,1,1}; +static unsigned int rx_adaptive_coalesce[MAX_UNITS] = { 1, 1, 1, 1 }; #if T3_JUMBO_RCV_RCB_ENTRY_COUNT #define JBO_DESC_CNT DEFAULT_JUMBO_RCV_DESC_COUNT static unsigned int rx_jumbo_desc_cnt[MAX_UNITS] = - {JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT}; + { JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT }; #endif #define RX_COAL_TK DEFAULT_RX_COALESCING_TICKS static unsigned int rx_coalesce_ticks[MAX_UNITS] = - {RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK}; + { RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK }; #define RX_COAL_FM DEFAULT_RX_MAX_COALESCED_FRAMES static unsigned int rx_max_coalesce_frames[MAX_UNITS] = - {RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM}; + { RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM }; #define TX_COAL_TK DEFAULT_TX_COALESCING_TICKS static unsigned int tx_coalesce_ticks[MAX_UNITS] = - {TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK}; + { TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK }; #define TX_COAL_FM DEFAULT_TX_MAX_COALESCED_FRAMES static unsigned int tx_max_coalesce_frames[MAX_UNITS] = - {TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM}; + { TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM }; #define ST_COAL_TK DEFAULT_STATS_COALESCING_TICKS static unsigned int stats_coalesce_ticks[MAX_UNITS] = - {ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK}; - + { ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK }; /* * Legitimate values for BCM570x device types @@ -134,707 +131,701 @@ typedef enum { /* Chip-Rev names for each device-type */ static struct { - char* name; + char *name; } chip_rev[] = { - {"BCM5700VIGIL"}, - {"BCM5700A6"}, - {"BCM5700T6"}, - {"BCM5700A9"}, - {"BCM5700T9"}, - {"BCM5700"}, - {"BCM5701A5"}, - {"BCM5701T1"}, - {"BCM5701T8"}, - {"BCM5701A7"}, - {"BCM5701A10"}, - {"BCM5701A12"}, - {"BCM5701"}, - {"BCM5702"}, - {"BCM5703"}, - {"BCM5703A31"}, - {"TC996T"}, - {"TC996ST"}, - {"TC996SSX"}, - {"TC996SX"}, - {"TC996BT"}, - {"TC997T"}, - {"TC997SX"}, - {"TC1000T"}, - {"TC940BR01"}, - {"TC942BR01"}, - {"NC6770"}, - {"NC7760"}, - {"NC7770"}, - {"NC7780"}, - {0} + { + "BCM5700VIGIL"}, { + "BCM5700A6"}, { + "BCM5700T6"}, { + "BCM5700A9"}, { + "BCM5700T9"}, { + "BCM5700"}, { + "BCM5701A5"}, { + "BCM5701T1"}, { + "BCM5701T8"}, { + "BCM5701A7"}, { + "BCM5701A10"}, { + "BCM5701A12"}, { + "BCM5701"}, { + "BCM5702"}, { + "BCM5703"}, { + "BCM5703A31"}, { + "TC996T"}, { + "TC996ST"}, { + "TC996SSX"}, { + "TC996SX"}, { + "TC996BT"}, { + "TC997T"}, { + "TC997SX"}, { + "TC1000T"}, { + "TC940BR01"}, { + "TC942BR01"}, { + "NC6770"}, { + "NC7760"}, { + "NC7770"}, { + "NC7780"}, { + 0} }; - /* indexed by board_t, above */ static struct { - char *name; + char *name; } board_info[] = { - { "Broadcom Vigil B5700 1000Base-T" }, - { "Broadcom BCM5700 1000Base-T" }, - { "Broadcom BCM5700 1000Base-SX" }, - { "Broadcom BCM5700 1000Base-SX" }, - { "Broadcom BCM5700 1000Base-T" }, - { "Broadcom BCM5700" }, - { "Broadcom BCM5701 1000Base-T" }, - { "Broadcom BCM5701 1000Base-T" }, - { "Broadcom BCM5701 1000Base-T" }, - { "Broadcom BCM5701 1000Base-SX" }, - { "Broadcom BCM5701 1000Base-T" }, - { "Broadcom BCM5701 1000Base-T" }, - { "Broadcom BCM5701" }, - { "Broadcom BCM5702 1000Base-T" }, - { "Broadcom BCM5703 1000Base-T" }, - { "Broadcom BCM5703 1000Base-SX" }, - { "3Com 3C996 10/100/1000 Server NIC" }, - { "3Com 3C996 10/100/1000 Server NIC" }, - { "3Com 3C996 Gigabit Fiber-SX Server NIC" }, - { "3Com 3C996 Gigabit Fiber-SX Server NIC" }, - { "3Com 3C996B Gigabit Server NIC" }, - { "3Com 3C997 Gigabit Server NIC" }, - { "3Com 3C997 Gigabit Fiber-SX Server NIC" }, - { "3Com 3C1000 Gigabit NIC" }, - { "3Com 3C940 Gigabit LOM (21X21)" }, - { "3Com 3C942 Gigabit LOM (31X31)" }, - { "Compaq NC6770 Gigabit Server Adapter" }, - { "Compaq NC7760 Gigabit Server Adapter" }, - { "Compaq NC7770 Gigabit Server Adapter" }, - { "Compaq NC7780 Gigabit Server Adapter" }, - { 0 }, -}; + { + "Broadcom Vigil B5700 1000Base-T"}, { + "Broadcom BCM5700 1000Base-T"}, { + "Broadcom BCM5700 1000Base-SX"}, { + "Broadcom BCM5700 1000Base-SX"}, { + "Broadcom BCM5700 1000Base-T"}, { + "Broadcom BCM5700"}, { + "Broadcom BCM5701 1000Base-T"}, { + "Broadcom BCM5701 1000Base-T"}, { + "Broadcom BCM5701 1000Base-T"}, { + "Broadcom BCM5701 1000Base-SX"}, { + "Broadcom BCM5701 1000Base-T"}, { + "Broadcom BCM5701 1000Base-T"}, { + "Broadcom BCM5701"}, { + "Broadcom BCM5702 1000Base-T"}, { + "Broadcom BCM5703 1000Base-T"}, { + "Broadcom BCM5703 1000Base-SX"}, { + "3Com 3C996 10/100/1000 Server NIC"}, { + "3Com 3C996 10/100/1000 Server NIC"}, { + "3Com 3C996 Gigabit Fiber-SX Server NIC"}, { + "3Com 3C996 Gigabit Fiber-SX Server NIC"}, { + "3Com 3C996B Gigabit Server NIC"}, { + "3Com 3C997 Gigabit Server NIC"}, { + "3Com 3C997 Gigabit Fiber-SX Server NIC"}, { + "3Com 3C1000 Gigabit NIC"}, { + "3Com 3C940 Gigabit LOM (21X21)"}, { + "3Com 3C942 Gigabit LOM (31X31)"}, { + "Compaq NC6770 Gigabit Server Adapter"}, { + "Compaq NC7760 Gigabit Server Adapter"}, { + "Compaq NC7770 Gigabit Server Adapter"}, { + "Compaq NC7780 Gigabit Server Adapter"}, { +0},}; /* PCI Devices which use the 570x chipset */ struct pci_device_table { - unsigned short vendor_id, device_id; /* Vendor/DeviceID */ - unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ - unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ - unsigned long board_id; /* Data private to the driver */ - int io_size, min_latency; + unsigned short vendor_id, device_id; /* Vendor/DeviceID */ + unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ + unsigned long board_id; /* Data private to the driver */ + int io_size, min_latency; } bcm570xDevices[] = { - {0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL ,128,32}, - {0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6 ,128,32}, - {0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6 ,128,32}, - {0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9 ,128,32}, - {0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9 ,128,32}, - {0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700 ,128,32}, - {0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700 ,128,32}, - {0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700 ,128,32}, - {0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700 ,128,32}, - {0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T ,128,32}, - {0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST ,128,32}, - {0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX ,128,32}, - {0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T ,128,32}, - {0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX ,128,32}, - {0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01 ,128,32}, - {0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700 ,128,32}, - {0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5 ,128,32}, - {0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1 ,128,32}, - {0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8 ,128,32}, - {0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7 ,128,32}, - {0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10 ,128,32}, - {0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12 ,128,32}, - {0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770 ,128,32}, - {0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770 ,128,32}, - {0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780 ,128,32}, - {0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701 ,128,32}, - {0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX ,128,32}, - {0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT ,128,32}, - {0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T ,128,32}, - {0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01 ,128,32}, - {0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701 ,128,32}, - {0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32}, - {0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32}, - {0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32}, - {0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32}, - {0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32}, - {0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32}, - {0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32}, - {0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32}, - {0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780 ,128,32}, - {0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32}, - {0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32}, - {0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32}, - {0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780 ,128,32}, - {0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32} + { + 0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL, 128, 32}, { + 0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6, 128, 32}, { + 0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6, 128, 32}, { + 0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9, 128, 32}, { + 0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9, 128, 32}, { + 0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700, 128, 32}, { + 0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700, 128, 32}, { + 0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700, 128, 32}, { + 0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700, 128, 32}, { + 0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T, 128, 32}, { + 0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST, 128, 32}, { + 0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX, 128, 32}, { + 0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T, 128, 32}, { + 0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX, 128, 32}, { + 0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01, 128, 32}, { + 0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700, 128, 32}, { + 0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5, 128, 32}, { + 0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1, 128, 32}, { + 0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8, 128, 32}, { + 0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7, 128, 32}, { + 0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10, 128, 32}, { + 0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12, 128, 32}, { + 0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770, 128, 32}, { + 0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770, 128, 32}, { + 0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780, 128, 32}, { + 0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701, 128, 32}, { + 0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX, 128, 32}, { + 0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT, 128, 32}, { + 0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T, 128, 32}, { + 0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01, 128, 32}, { + 0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701, 128, 32}, { + 0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702, 128, 32}, { + 0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760, 128, 32}, { + 0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702, 128, 32}, { + 0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702, 128, 32}, { + 0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760, 128, 32}, { + 0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702, 128, 32}, { + 0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31, 128, 32}, { + 0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770, 128, 32}, { + 0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780, 128, 32}, { + 0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31, 128, 32}, { + 0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703, 128, 32}, { + 0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770, 128, 32}, { + 0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780, 128, 32}, { + 0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703, 128, 32} }; #define n570xDevices (sizeof(bcm570xDevices)/sizeof(bcm570xDevices[0])) - /* * Allocate a packet buffer from the bcm570x packet pool. */ -void * -bcm570xPktAlloc(int u, int pksize) +void *bcm570xPktAlloc (int u, int pksize) { - return malloc(pksize); + return malloc (pksize); } /* * Free a packet previously allocated from the bcm570x packet * buffer pool. */ -void -bcm570xPktFree(int u, void *p) +void bcm570xPktFree (int u, void *p) { - free(p); + free (p); } -int -bcm570xReplenishRxBuffers(PUM_DEVICE_BLOCK pUmDevice) +int bcm570xReplenishRxBuffers (PUM_DEVICE_BLOCK pUmDevice) { - PLM_PACKET pPacket; - PUM_PACKET pUmPacket; - void *skb; - int queue_rx = 0; - int ret = 0; - - while ((pUmPacket = (PUM_PACKET) - QQ_PopHead(&pUmDevice->rx_out_of_buf_q.Container)) != 0) { - - pPacket = (PLM_PACKET) pUmPacket; - - /* reuse an old skb */ - if (pUmPacket->skbuff) { - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - queue_rx = 1; - continue; - } - if ( ( skb = bcm570xPktAlloc(pUmDevice->index, - pPacket->u.Rx.RxBufferSize + 2)) == 0) { - QQ_PushHead(&pUmDevice->rx_out_of_buf_q.Container,pPacket); - printf("NOTICE: Out of RX memory.\n"); - ret = 1; - break; - } + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + void *skb; + int queue_rx = 0; + int ret = 0; + + while ((pUmPacket = (PUM_PACKET) + QQ_PopHead (&pUmDevice->rx_out_of_buf_q.Container)) != 0) { + + pPacket = (PLM_PACKET) pUmPacket; + + /* reuse an old skb */ + if (pUmPacket->skbuff) { + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, + pPacket); + queue_rx = 1; + continue; + } + if ((skb = bcm570xPktAlloc (pUmDevice->index, + pPacket->u.Rx.RxBufferSize + 2)) == + 0) { + QQ_PushHead (&pUmDevice->rx_out_of_buf_q.Container, + pPacket); + printf ("NOTICE: Out of RX memory.\n"); + ret = 1; + break; + } - pUmPacket->skbuff = skb; - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - queue_rx = 1; - } + pUmPacket->skbuff = skb; + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); + queue_rx = 1; + } - if (queue_rx) { - LM_QueueRxPackets(pDevice); - } + if (queue_rx) { + LM_QueueRxPackets (pDevice); + } - return ret; + return ret; } /* * Probe, Map, and Init 570x device. */ -int eth_init(bd_t *bis) +int eth_init (bd_t * bis) { - int i, rv, devFound = FALSE; - pci_dev_t devbusfn; - unsigned short status; - - /* Find PCI device, if it exists, configure ... */ - for( i = 0; i < n570xDevices; i++){ - devbusfn = pci_find_device(bcm570xDevices[i].vendor_id, - bcm570xDevices[i].device_id, 0); - if(devbusfn == -1) { - continue; /* No device of that vendor/device ID */ + int i, rv, devFound = FALSE; + pci_dev_t devbusfn; + unsigned short status; + + /* Find PCI device, if it exists, configure ... */ + for (i = 0; i < n570xDevices; i++) { + devbusfn = pci_find_device (bcm570xDevices[i].vendor_id, + bcm570xDevices[i].device_id, 0); + if (devbusfn == -1) { + continue; /* No device of that vendor/device ID */ + } else { + + /* Set ILINE */ + pci_write_config_byte (devbusfn, + PCI_INTERRUPT_LINE, + BCM570X_ILINE); + + /* + * 0x10 - 0x14 define one 64-bit MBAR. + * 0x14 is the higher-order address bits of the BAR. + */ + pci_write_config_dword (devbusfn, + PCI_BASE_ADDRESS_1, 0); + + ioBase = BCM570X_MBAR; + + pci_write_config_dword (devbusfn, + PCI_BASE_ADDRESS_0, ioBase); + + /* + * Enable PCI memory, IO, and Master -- don't + * reset any status bits in doing so. + */ + pci_read_config_word (devbusfn, PCI_COMMAND, &status); + + status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + + pci_write_config_word (devbusfn, PCI_COMMAND, status); + + printf + ("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n", + board_info[bcm570xDevices[i].board_id].name, + PCI_BUS (devbusfn), PCI_DEV (devbusfn), + PCI_FUNC (devbusfn), ioBase); + + /* Allocate once, but always clear on init */ + if (!pDevice) { + pDevice = malloc (sizeof (UM_DEVICE_BLOCK)); + pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + memset (pDevice, 0x0, sizeof (UM_DEVICE_BLOCK)); + } + + /* Configure pci dev structure */ + pUmDevice->pdev = devbusfn; + pUmDevice->index = 0; + pUmDevice->tx_pkt = 0; + pUmDevice->rx_pkt = 0; + devFound = TRUE; + break; + } + } + + if (!devFound) { + printf + ("eth_init: FAILURE: no BCM570x Ethernet devices found.\n"); + return -1; + } + + /* Setup defaults for chip */ + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + + if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) { + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; } else { - /* Set ILINE */ - pci_write_config_byte(devbusfn, - PCI_INTERRUPT_LINE, BCM570X_ILINE); - - /* - * 0x10 - 0x14 define one 64-bit MBAR. - * 0x14 is the higher-order address bits of the BAR. - */ - pci_write_config_dword(devbusfn, - PCI_BASE_ADDRESS_1, 0); - - ioBase = BCM570X_MBAR; - - pci_write_config_dword(devbusfn, - PCI_BASE_ADDRESS_0, ioBase); - - /* - * Enable PCI memory, IO, and Master -- don't - * reset any status bits in doing so. - */ - pci_read_config_word(devbusfn, - PCI_COMMAND, &status); - - status |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER; - - pci_write_config_word(devbusfn, - PCI_COMMAND, status); - - printf("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n", - board_info[bcm570xDevices[i].board_id].name, - PCI_BUS(devbusfn), - PCI_DEV(devbusfn), - PCI_FUNC(devbusfn), - ioBase); - - /* Allocate once, but always clear on init */ - if (!pDevice) { - pDevice = malloc(sizeof(UM_DEVICE_BLOCK)); - pUmDevice = (PUM_DEVICE_BLOCK)pDevice; - memset(pDevice, 0x0, sizeof(UM_DEVICE_BLOCK)); - } - - /* Configure pci dev structure */ - pUmDevice->pdev = devbusfn; - pUmDevice->index = 0; - pUmDevice->tx_pkt = 0; - pUmDevice->rx_pkt = 0; - devFound = TRUE; - break; + if (rx_checksum[i]) { + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_RX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_RX_UDP_CHECKSUM; + } + + if (tx_checksum[i]) { + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM; + pDevice->NoTxPseudoHdrChksum = TRUE; + } + } + + /* Set Device PCI Memory base address */ + pDevice->pMappedMemBase = (PLM_UINT8) ioBase; + + /* Pull down adapter info */ + if ((rv = LM_GetAdapterInfo (pDevice)) != LM_STATUS_SUCCESS) { + printf ("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv); + return -2; } - } - if(!devFound){ - printf("eth_init: FAILURE: no BCM570x Ethernet devices found.\n"); - return -1; - } + /* Lock not needed */ + pUmDevice->do_global_lock = 0; - /* Setup defaults for chip */ - pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + if (T3_ASIC_REV (pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) { + /* The 5700 chip works best without interleaved register */ + /* accesses on certain machines. */ + pUmDevice->do_global_lock = 1; + } - if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) { - pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; - } else { + /* Setup timer delays */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + pDevice->UseTaggedStatus = TRUE; + pUmDevice->timer_interval = CFG_HZ; + } else { + pUmDevice->timer_interval = CFG_HZ / 50; + } - if (rx_checksum[i]) { - pDevice->TaskToOffload |= - LM_TASK_OFFLOAD_RX_TCP_CHECKSUM | - LM_TASK_OFFLOAD_RX_UDP_CHECKSUM; + /* Grab name .... */ + pUmDevice->name = + (char *)malloc (strlen (board_info[bcm570xDevices[i].board_id].name) + + 1); + strcpy (pUmDevice->name, board_info[bcm570xDevices[i].board_id].name); + + memcpy (pDevice->NodeAddress, bis->bi_enetaddr, 6); + LM_SetMacAddress (pDevice, bis->bi_enetaddr); + /* Init queues .. */ + QQ_InitQueue (&pUmDevice->rx_out_of_buf_q.Container, + MAX_RX_PACKET_DESC_COUNT); + pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0; + + /* delay for 4 seconds */ + pUmDevice->delayed_link_ind = (4 * CFG_HZ) / pUmDevice->timer_interval; + + pUmDevice->adaptive_expiry = CFG_HZ / pUmDevice->timer_interval; + + /* Sometimes we get spurious ints. after reset when link is down. */ + /* This field tells the isr to service the int. even if there is */ + /* no status block update. */ + pUmDevice->adapter_just_inited = + (3 * CFG_HZ) / pUmDevice->timer_interval; + + /* Initialize 570x */ + if (LM_InitializeAdapter (pDevice) != LM_STATUS_SUCCESS) { + printf ("ERROR: Adapter initialization failed.\n"); + return ERROR; } - if (tx_checksum[i]) { - pDevice->TaskToOffload |= - LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | - LM_TASK_OFFLOAD_TX_UDP_CHECKSUM; - pDevice->NoTxPseudoHdrChksum = TRUE; + /* Enable chip ISR */ + LM_EnableInterrupt (pDevice); + + /* Clear MC table */ + LM_MulticastClear (pDevice); + + /* Enable Multicast */ + LM_SetReceiveMask (pDevice, + pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST); + + pUmDevice->opened = 1; + pUmDevice->tx_full = 0; + pUmDevice->tx_pkt = 0; + pUmDevice->rx_pkt = 0; + printf ("eth%d: %s @0x%lx,", + pDevice->index, pUmDevice->name, (unsigned long)ioBase); + printf ("node addr "); + for (i = 0; i < 6; i++) { + printf ("%2.2x", pDevice->NodeAddress[i]); } - } - - /* Set Device PCI Memory base address */ - pDevice->pMappedMemBase = (PLM_UINT8) ioBase; - - /* Pull down adapter info */ - if ((rv = LM_GetAdapterInfo(pDevice)) != LM_STATUS_SUCCESS) { - printf("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv ); - return -2; - } - - /* Lock not needed */ - pUmDevice->do_global_lock = 0; - - if (T3_ASIC_REV(pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) { - /* The 5700 chip works best without interleaved register */ - /* accesses on certain machines. */ - pUmDevice->do_global_lock = 1; - } - - /* Setup timer delays */ - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) { - pDevice->UseTaggedStatus = TRUE; - pUmDevice->timer_interval = CFG_HZ; - } - else { - pUmDevice->timer_interval = CFG_HZ / 50; - } - - /* Grab name .... */ - pUmDevice->name = - (char*)malloc(strlen(board_info[bcm570xDevices[i].board_id].name)+1); - strcpy(pUmDevice->name,board_info[bcm570xDevices[i].board_id].name); - - memcpy(pDevice->NodeAddress, bis->bi_enetaddr, 6); - LM_SetMacAddress(pDevice, bis->bi_enetaddr); - /* Init queues .. */ - QQ_InitQueue(&pUmDevice->rx_out_of_buf_q.Container, - MAX_RX_PACKET_DESC_COUNT); - pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0; - - /* delay for 4 seconds */ - pUmDevice->delayed_link_ind = - (4 * CFG_HZ) / pUmDevice->timer_interval; - - pUmDevice->adaptive_expiry = - CFG_HZ / pUmDevice->timer_interval; - - /* Sometimes we get spurious ints. after reset when link is down. */ - /* This field tells the isr to service the int. even if there is */ - /* no status block update. */ - pUmDevice->adapter_just_inited = - (3 * CFG_HZ) / pUmDevice->timer_interval; - - /* Initialize 570x */ - if (LM_InitializeAdapter(pDevice) != LM_STATUS_SUCCESS) { - printf("ERROR: Adapter initialization failed.\n"); - return ERROR; - } - - /* Enable chip ISR */ - LM_EnableInterrupt(pDevice); - - /* Clear MC table */ - LM_MulticastClear(pDevice); - - /* Enable Multicast */ - LM_SetReceiveMask(pDevice, - pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST); - - pUmDevice->opened = 1; - pUmDevice->tx_full = 0; - pUmDevice->tx_pkt = 0; - pUmDevice->rx_pkt = 0; - printf("eth%d: %s @0x%lx,", - pDevice->index, pUmDevice->name, (unsigned long)ioBase); - printf( "node addr "); - for (i = 0; i < 6; i++) { - printf("%2.2x", pDevice->NodeAddress[i]); - } - printf("\n"); - - printf("eth%d: ", pDevice->index); - printf("%s with ", - chip_rev[bcm570xDevices[i].board_id].name); - - if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID) - printf("Broadcom BCM5400 Copper "); - else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) - printf("Broadcom BCM5401 Copper "); - else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID) - printf("Broadcom BCM5411 Copper "); - else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID) - printf("Broadcom BCM5701 Integrated Copper "); - else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID) - printf("Broadcom BCM5703 Integrated Copper "); - else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID) - printf("Broadcom BCM8002 SerDes "); - else if (pDevice->EnableTbi) - printf("Agilent HDMP-1636 SerDes "); - else - printf("Unknown "); - printf("transceiver found\n"); - - printf("eth%d: %s, MTU: %d,", - pDevice->index, pDevice->BusSpeedStr, 1500); - - if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) && - rx_checksum[i]) - printf("Rx Checksum ON\n"); - else - printf("Rx Checksum OFF\n"); - initialized++; - - return 0; + printf ("\n"); + + printf ("eth%d: ", pDevice->index); + printf ("%s with ", chip_rev[bcm570xDevices[i].board_id].name); + + if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID) + printf ("Broadcom BCM5400 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) + printf ("Broadcom BCM5401 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID) + printf ("Broadcom BCM5411 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID) + printf ("Broadcom BCM5701 Integrated Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID) + printf ("Broadcom BCM5703 Integrated Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID) + printf ("Broadcom BCM8002 SerDes "); + else if (pDevice->EnableTbi) + printf ("Agilent HDMP-1636 SerDes "); + else + printf ("Unknown "); + printf ("transceiver found\n"); + + printf ("eth%d: %s, MTU: %d,", + pDevice->index, pDevice->BusSpeedStr, 1500); + + if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) && rx_checksum[i]) + printf ("Rx Checksum ON\n"); + else + printf ("Rx Checksum OFF\n"); + initialized++; + + return 0; } /* Ethernet Interrupt service routine */ -void -eth_isr(void) +void eth_isr (void) { - LM_UINT32 oldtag, newtag; - int i; - - pUmDevice->interrupt = 1; - - if (pDevice->UseTaggedStatus) { - if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) || - pUmDevice->adapter_just_inited) { - MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); - oldtag = pDevice->pStatusBlkVirt->StatusTag; - - for (i = 0; ; i++) { - pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED; - LM_ServiceInterrupts(pDevice); - newtag = pDevice->pStatusBlkVirt->StatusTag; - if ((newtag == oldtag) || (i > 50)) { - MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, newtag << 24); - if (pDevice->UndiFix) { - REG_WR(pDevice, Grc.LocalCtrl, - pDevice->GrcLocalCtrl | 0x2); - } - break; - } - oldtag = newtag; - } + LM_UINT32 oldtag, newtag; + int i; + + pUmDevice->interrupt = 1; + + if (pDevice->UseTaggedStatus) { + if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) || + pUmDevice->adapter_just_inited) { + MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1); + oldtag = pDevice->pStatusBlkVirt->StatusTag; + + for (i = 0;; i++) { + pDevice->pStatusBlkVirt->Status &= + ~STATUS_BLOCK_UPDATED; + LM_ServiceInterrupts (pDevice); + newtag = pDevice->pStatusBlkVirt->StatusTag; + if ((newtag == oldtag) || (i > 50)) { + MB_REG_WR (pDevice, + Mailbox.Interrupt[0].Low, + newtag << 24); + if (pDevice->UndiFix) { + REG_WR (pDevice, Grc.LocalCtrl, + pDevice-> + GrcLocalCtrl | 0x2); + } + break; + } + oldtag = newtag; + } + } + } else { + while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) { + unsigned int dummy; + + pDevice->pMemView->Mailbox.Interrupt[0].Low = 1; + pDevice->pStatusBlkVirt->Status &= + ~STATUS_BLOCK_UPDATED; + LM_ServiceInterrupts (pDevice); + pDevice->pMemView->Mailbox.Interrupt[0].Low = 0; + dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low; + } + } + + /* Allocate new RX buffers */ + if (QQ_GetEntryCnt (&pUmDevice->rx_out_of_buf_q.Container)) { + bcm570xReplenishRxBuffers (pUmDevice); } - } - else { - while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) { - unsigned int dummy; - - pDevice->pMemView->Mailbox.Interrupt[0].Low = 1; - pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED; - LM_ServiceInterrupts(pDevice); - pDevice->pMemView->Mailbox.Interrupt[0].Low = 0; - dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low; + + /* Queue packets */ + if (QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container)) { + LM_QueueRxPackets (pDevice); + } + + if (pUmDevice->tx_queued) { + pUmDevice->tx_queued = 0; } - } - - /* Allocate new RX buffers */ - if (QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container)) { - bcm570xReplenishRxBuffers(pUmDevice); - } - - /* Queue packets */ - if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container)) { - LM_QueueRxPackets(pDevice); - } - - if (pUmDevice->tx_queued) { - pUmDevice->tx_queued = 0; - } - - if(pUmDevice->tx_full){ - if(pDevice->LinkStatus != LM_STATUS_LINK_DOWN){ - printf("NOTICE: tx was previously blocked, restarting MUX\n"); - pUmDevice->tx_full = 0; + + if (pUmDevice->tx_full) { + if (pDevice->LinkStatus != LM_STATUS_LINK_DOWN) { + printf + ("NOTICE: tx was previously blocked, restarting MUX\n"); + pUmDevice->tx_full = 0; + } } - } - pUmDevice->interrupt = 0; + pUmDevice->interrupt = 0; } -int -eth_send(volatile void *packet, int length) +int eth_send (volatile void *packet, int length) { - int status = 0; + int status = 0; #if ET_DEBUG - unsigned char* ptr = (unsigned char*)packet; + unsigned char *ptr = (unsigned char *)packet; #endif - PLM_PACKET pPacket; - PUM_PACKET pUmPacket; + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; - /* Link down, return */ - while(pDevice->LinkStatus == LM_STATUS_LINK_DOWN) { + /* Link down, return */ + while (pDevice->LinkStatus == LM_STATUS_LINK_DOWN) { #if 0 - printf("eth%d: link down - check cable or link partner.\n", - pUmDevice->index); + printf ("eth%d: link down - check cable or link partner.\n", + pUmDevice->index); #endif - eth_isr(); + eth_isr (); + + /* Wait to see link for one-half a second before sending ... */ + udelay (1500000); - /* Wait to see link for one-half a second before sending ... */ - udelay(1500000); + } - } + /* Clear sent flag */ + pUmDevice->tx_pkt = 0; - /* Clear sent flag */ - pUmDevice->tx_pkt = 0; + /* Previously blocked */ + if (pUmDevice->tx_full) { + printf ("eth%d: tx blocked.\n", pUmDevice->index); + return 0; + } - /* Previously blocked */ - if(pUmDevice->tx_full){ - printf("eth%d: tx blocked.\n", pUmDevice->index); - return 0; - } + pPacket = (PLM_PACKET) + QQ_PopHead (&pDevice->TxPacketFreeQ.Container); - pPacket = (PLM_PACKET) - QQ_PopHead(&pDevice->TxPacketFreeQ.Container); + if (pPacket == 0) { + pUmDevice->tx_full = 1; + printf ("bcm570xEndSend: TX full!\n"); + return 0; + } - if (pPacket == 0) { - pUmDevice->tx_full = 1; - printf("bcm570xEndSend: TX full!\n"); - return 0; - } + if (pDevice->SendBdLeft.counter == 0) { + pUmDevice->tx_full = 1; + printf ("bcm570xEndSend: no more TX descriptors!\n"); + QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket); + return 0; + } - if (pDevice->SendBdLeft.counter == 0) { - pUmDevice->tx_full = 1; - printf("bcm570xEndSend: no more TX descriptors!\n"); - QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); - return 0; - } - - if (length <= 0){ - printf("eth: bad packet size: %d\n", length); - goto out; - } - - /* Get packet buffers and fragment list */ - pUmPacket = (PUM_PACKET) pPacket; - /* Single DMA Descriptor transmit. - * Fragments may be provided, but one DMA descriptor max is - * used to send the packet. - */ - if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) { - if (pUmPacket->skbuff == NULL){ - /* Packet was discarded */ - printf("TX: failed (1)\n"); - status = 1; - } else{ - printf("TX: failed (2)\n"); - status = 2; + if (length <= 0) { + printf ("eth: bad packet size: %d\n", length); + goto out; } - QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket); - return status; - } - - /* Copy packet to DMA buffer */ - memset(pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE); - memcpy((void*)pUmPacket->skbuff, (void*)packet, length); - pPacket->PacketSize = length; - pPacket->Flags |= SND_BD_FLAG_END|SND_BD_FLAG_COAL_NOW; - pPacket->u.Tx.FragCount = 1; - /* We've already provided a frame ready for transmission */ - pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM; - - if ( LM_SendPacket(pDevice, pPacket) == LM_STATUS_FAILURE){ - /* - * A lower level send failure will push the packet descriptor back - * in the free queue, so just deal with the VxWorks clusters. + + /* Get packet buffers and fragment list */ + pUmPacket = (PUM_PACKET) pPacket; + /* Single DMA Descriptor transmit. + * Fragments may be provided, but one DMA descriptor max is + * used to send the packet. */ - if (pUmPacket->skbuff == NULL){ - printf("TX failed (1)!\n"); - /* Packet was discarded */ - status = 3; - } else { - /* A resource problem ... */ - printf("TX failed (2)!\n"); - status = 4; + if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) { + if (pUmPacket->skbuff == NULL) { + /* Packet was discarded */ + printf ("TX: failed (1)\n"); + status = 1; + } else { + printf ("TX: failed (2)\n"); + status = 2; + } + QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket); + return status; } - if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) == 0) { - printf("TX: emptyQ!\n"); - pUmDevice->tx_full = 1; + /* Copy packet to DMA buffer */ + memset (pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE); + memcpy ((void *)pUmPacket->skbuff, (void *)packet, length); + pPacket->PacketSize = length; + pPacket->Flags |= SND_BD_FLAG_END | SND_BD_FLAG_COAL_NOW; + pPacket->u.Tx.FragCount = 1; + /* We've already provided a frame ready for transmission */ + pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM; + + if (LM_SendPacket (pDevice, pPacket) == LM_STATUS_FAILURE) { + /* + * A lower level send failure will push the packet descriptor back + * in the free queue, so just deal with the VxWorks clusters. + */ + if (pUmPacket->skbuff == NULL) { + printf ("TX failed (1)!\n"); + /* Packet was discarded */ + status = 3; + } else { + /* A resource problem ... */ + printf ("TX failed (2)!\n"); + status = 4; + } + + if (QQ_GetEntryCnt (&pDevice->TxPacketFreeQ.Container) == 0) { + printf ("TX: emptyQ!\n"); + pUmDevice->tx_full = 1; + } } - } - while(pUmDevice->tx_pkt == 0){ - /* Service TX */ - eth_isr(); - } + while (pUmDevice->tx_pkt == 0) { + /* Service TX */ + eth_isr (); + } #if ET_DEBUG - printf("eth_send: 0x%x, %d bytes\n" - "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n", - (int)pPacket, length, - ptr[0],ptr[1],ptr[2],ptr[3],ptr[4],ptr[5], - ptr[6],ptr[7],ptr[8],ptr[9],ptr[10],ptr[11],ptr[12], - ptr[13],ptr[14],ptr[15]); + printf ("eth_send: 0x%x, %d bytes\n" + "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n", + (int)pPacket, length, + ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], + ptr[6], ptr[7], ptr[8], ptr[9], ptr[10], ptr[11], ptr[12], + ptr[13], ptr[14], ptr[15]); #endif - pUmDevice->tx_pkt = 0; - QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); + pUmDevice->tx_pkt = 0; + QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket); - /* Done with send */ - out: - return status; + /* Done with send */ + out: + return status; } - /* Ethernet receive */ -int -eth_rx(void) +int eth_rx (void) { - PLM_PACKET pPacket = NULL; - PUM_PACKET pUmPacket = NULL; - void *skb; - int size=0; + PLM_PACKET pPacket = NULL; + PUM_PACKET pUmPacket = NULL; + void *skb; + int size = 0; - while(TRUE) { + while (TRUE) { - bcm570x_service_isr: - /* Pull down packet if it is there */ - eth_isr(); + bcm570x_service_isr: + /* Pull down packet if it is there */ + eth_isr (); - /* Indicate RX packets called */ - if(pUmDevice->rx_pkt){ - /* printf("eth_rx: got a packet...\n"); */ - pUmDevice->rx_pkt = 0; - } else { - /* printf("eth_rx: waiting for packet...\n"); */ - goto bcm570x_service_isr; - } + /* Indicate RX packets called */ + if (pUmDevice->rx_pkt) { + /* printf("eth_rx: got a packet...\n"); */ + pUmDevice->rx_pkt = 0; + } else { + /* printf("eth_rx: waiting for packet...\n"); */ + goto bcm570x_service_isr; + } - pPacket = (PLM_PACKET) - QQ_PopHead(&pDevice->RxPacketReceivedQ.Container); + pPacket = (PLM_PACKET) + QQ_PopHead (&pDevice->RxPacketReceivedQ.Container); - if (pPacket == 0){ - printf("eth_rx: empty packet!\n"); - goto bcm570x_service_isr; - } + if (pPacket == 0) { + printf ("eth_rx: empty packet!\n"); + goto bcm570x_service_isr; + } - pUmPacket = (PUM_PACKET) pPacket; + pUmPacket = (PUM_PACKET) pPacket; #if ET_DEBUG - printf("eth_rx: packet @0x%x\n", - (int)pPacket); + printf ("eth_rx: packet @0x%x\n", (int)pPacket); #endif - /* If the packet generated an error, reuse buffer */ - if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) || - ((size = pPacket->PacketSize) > pDevice->RxMtu)) { - - /* reuse skb */ - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - printf("eth_rx: error in packet dma!\n"); - goto bcm570x_service_isr; - } + /* If the packet generated an error, reuse buffer */ + if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) || + ((size = pPacket->PacketSize) > pDevice->RxMtu)) { + + /* reuse skb */ + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, + pPacket); + printf ("eth_rx: error in packet dma!\n"); + goto bcm570x_service_isr; + } - /* Set size and address */ - skb = pUmPacket->skbuff; - size = pPacket->PacketSize; + /* Set size and address */ + skb = pUmPacket->skbuff; + size = pPacket->PacketSize; - /* Pass the packet up to the protocol - * layers. - */ - NetReceive(skb, size); + /* Pass the packet up to the protocol + * layers. + */ + NetReceive (skb, size); - /* Free packet buffer */ - bcm570xPktFree (pUmDevice->index, skb); - pUmPacket->skbuff = NULL; + /* Free packet buffer */ + bcm570xPktFree (pUmDevice->index, skb); + pUmPacket->skbuff = NULL; - /* Reuse SKB */ - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + /* Reuse SKB */ + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); - return 0; /* Got a packet, bail ... */ - } - return size; + return 0; /* Got a packet, bail ... */ + } + return size; } - /* Shut down device */ -void -eth_halt(void) +void eth_halt (void) { - int i; - if ( initialized) - if (pDevice && pUmDevice && pUmDevice->opened){ - printf("\neth%d:%s,", pUmDevice->index, pUmDevice->name); - printf("HALT,"); - /* stop device */ - LM_Halt(pDevice); - printf("POWER DOWN,"); - LM_SetPowerState(pDevice, LM_POWER_STATE_D3); - - /* Free the memory allocated by the device in tigon3 */ - for (i = 0; i < pUmDevice->mem_list_num; i++) { - if (pUmDevice->mem_list[i]) { - /* sanity check */ - if (pUmDevice->dma_list[i]) { /* cache-safe memory */ - free(pUmDevice->mem_list[i]); - } else { - free(pUmDevice->mem_list[i]); /* normal memory */ + int i; + if (initialized) + if (pDevice && pUmDevice && pUmDevice->opened) { + printf ("\neth%d:%s,", pUmDevice->index, + pUmDevice->name); + printf ("HALT,"); + /* stop device */ + LM_Halt (pDevice); + printf ("POWER DOWN,"); + LM_SetPowerState (pDevice, LM_POWER_STATE_D3); + + /* Free the memory allocated by the device in tigon3 */ + for (i = 0; i < pUmDevice->mem_list_num; i++) { + if (pUmDevice->mem_list[i]) { + /* sanity check */ + if (pUmDevice->dma_list[i]) { /* cache-safe memory */ + free (pUmDevice->mem_list[i]); + } else { + free (pUmDevice->mem_list[i]); /* normal memory */ + } + } + } + pUmDevice->opened = 0; + free (pDevice); + pDevice = NULL; + pUmDevice = NULL; + initialized = 0; + printf ("done - offline.\n"); } - } - } - pUmDevice->opened = 0; - free(pDevice); - pDevice = NULL; - pUmDevice = NULL; - initialized = 0; - printf("done - offline.\n"); - } } - /* * * Middle Module: Interface between the HW driver (tigon3 modules) and @@ -843,409 +834,380 @@ eth_halt(void) */ /* Middle module dependency - size of a packet descriptor */ -int MM_Packet_Desc_Size = sizeof(UM_PACKET); - +int MM_Packet_Desc_Size = sizeof (UM_PACKET); LM_STATUS -MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, - LM_UINT32 Offset, - LM_UINT32 *pValue32) +MM_ReadConfig32 (PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, LM_UINT32 * pValue32) { - UM_DEVICE_BLOCK *pUmDevice; - pUmDevice = (UM_DEVICE_BLOCK *) pDevice; - pci_read_config_dword(pUmDevice->pdev, - Offset, (u32 *) pValue32); - return LM_STATUS_SUCCESS; + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_read_config_dword (pUmDevice->pdev, Offset, (u32 *) pValue32); + return LM_STATUS_SUCCESS; } - LM_STATUS -MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, - LM_UINT32 Offset, - LM_UINT32 Value32) +MM_WriteConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 Value32) { - UM_DEVICE_BLOCK *pUmDevice; - pUmDevice = (UM_DEVICE_BLOCK *) pDevice; - pci_write_config_dword(pUmDevice->pdev, - Offset, Value32); - return LM_STATUS_SUCCESS; + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_write_config_dword (pUmDevice->pdev, Offset, Value32); + return LM_STATUS_SUCCESS; } - LM_STATUS -MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, - LM_UINT32 Offset, - LM_UINT16 *pValue16) +MM_ReadConfig16 (PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, LM_UINT16 * pValue16) { - UM_DEVICE_BLOCK *pUmDevice; - pUmDevice = (UM_DEVICE_BLOCK *) pDevice; - pci_read_config_word(pUmDevice->pdev, - Offset, (u16*) pValue16); - return LM_STATUS_SUCCESS; + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_read_config_word (pUmDevice->pdev, Offset, (u16 *) pValue16); + return LM_STATUS_SUCCESS; } LM_STATUS -MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, - LM_UINT32 Offset, - LM_UINT16 Value16) +MM_WriteConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT16 Value16) { - UM_DEVICE_BLOCK *pUmDevice; - pUmDevice = (UM_DEVICE_BLOCK *) pDevice; - pci_write_config_word(pUmDevice->pdev, - Offset, Value16); - return LM_STATUS_SUCCESS; + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_write_config_word (pUmDevice->pdev, Offset, Value16); + return LM_STATUS_SUCCESS; } - LM_STATUS -MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, - PLM_VOID *pMemoryBlockVirt, - PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, - LM_BOOL Cached) +MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID * pMemoryBlockVirt, + PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, LM_BOOL Cached) { - PLM_VOID pvirt; - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - dma_addr_t mapping; + PLM_VOID pvirt; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + dma_addr_t mapping; - pvirt = malloc(BlockSize); - mapping = (dma_addr_t)(pvirt); - if (!pvirt) - return LM_STATUS_FAILURE; + pvirt = malloc (BlockSize); + mapping = (dma_addr_t) (pvirt); + if (!pvirt) + return LM_STATUS_FAILURE; - pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; - pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping; - pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; - memset(pvirt, 0, BlockSize); + pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; + pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping; + pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; + memset (pvirt, 0, BlockSize); - *pMemoryBlockVirt = (PLM_VOID) pvirt; - MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping); + *pMemoryBlockVirt = (PLM_VOID) pvirt; + MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping); - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } - LM_STATUS -MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, - PLM_VOID *pMemoryBlockVirt) +MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID * pMemoryBlockVirt) { - PLM_VOID pvirt; - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PLM_VOID pvirt; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - pvirt = malloc(BlockSize); + pvirt = malloc (BlockSize); - if (!pvirt) - return LM_STATUS_FAILURE; + if (!pvirt) + return LM_STATUS_FAILURE; - pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; - pUmDevice->dma_list[pUmDevice->mem_list_num] = 0; - pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; - memset(pvirt, 0, BlockSize); - *pMemoryBlockVirt = pvirt; + pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; + pUmDevice->dma_list[pUmDevice->mem_list_num] = 0; + pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; + memset (pvirt, 0, BlockSize); + *pMemoryBlockVirt = pvirt; - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } -LM_STATUS -MM_MapMemBase(PLM_DEVICE_BLOCK pDevice) +LM_STATUS MM_MapMemBase (PLM_DEVICE_BLOCK pDevice) { - printf("BCM570x PCI Memory base address @0x%x\n", - (unsigned int)pDevice->pMappedMemBase); - return LM_STATUS_SUCCESS; + printf ("BCM570x PCI Memory base address @0x%x\n", + (unsigned int)pDevice->pMappedMemBase); + return LM_STATUS_SUCCESS; } -LM_STATUS -MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice) +LM_STATUS MM_InitializeUmPackets (PLM_DEVICE_BLOCK pDevice) { - int i; - void* skb; - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - PUM_PACKET pUmPacket = NULL; - PLM_PACKET pPacket = NULL; - - for (i = 0; i < pDevice->RxPacketDescCnt; i++) { - pPacket = QQ_PopHead(&pDevice->RxPacketFreeQ.Container); - pUmPacket = (PUM_PACKET) pPacket; + int i; + void *skb; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PUM_PACKET pUmPacket = NULL; + PLM_PACKET pPacket = NULL; + + for (i = 0; i < pDevice->RxPacketDescCnt; i++) { + pPacket = QQ_PopHead (&pDevice->RxPacketFreeQ.Container); + pUmPacket = (PUM_PACKET) pPacket; + + if (pPacket == 0) { + printf ("MM_InitializeUmPackets: Bad RxPacketFreeQ\n"); + } - if (pPacket == 0) { - printf("MM_InitializeUmPackets: Bad RxPacketFreeQ\n"); - } + skb = bcm570xPktAlloc (pUmDevice->index, + pPacket->u.Rx.RxBufferSize + 2); - skb = bcm570xPktAlloc(pUmDevice->index, - pPacket->u.Rx.RxBufferSize + 2); + if (skb == 0) { + pUmPacket->skbuff = 0; + QQ_PushTail (&pUmDevice->rx_out_of_buf_q.Container, + pPacket); + printf ("MM_InitializeUmPackets: out of buffer.\n"); + continue; + } - if (skb == 0) { - pUmPacket->skbuff = 0; - QQ_PushTail(&pUmDevice->rx_out_of_buf_q.Container, pPacket); - printf("MM_InitializeUmPackets: out of buffer.\n"); - continue; + pUmPacket->skbuff = skb; + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); } - pUmPacket->skbuff = skb; - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - } - - pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8; + pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8; - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } -LM_STATUS -MM_GetConfig(PLM_DEVICE_BLOCK pDevice) +LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice) { - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - int index = pDevice->index; - - if (auto_speed[index] == 0) - pDevice->DisableAutoNeg = TRUE; - else - pDevice->DisableAutoNeg = FALSE; - - if (line_speed[index] == 0) { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_AUTO; - pDevice->DisableAutoNeg = FALSE; - } - else { - if (line_speed[index] == 1000) { - if (pDevice->EnableTbi) { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX; - } - else if (full_duplex[index]) { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX; - } - else { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS; - } - if (!pDevice->EnableTbi) + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + int index = pDevice->index; + + if (auto_speed[index] == 0) + pDevice->DisableAutoNeg = TRUE; + else pDevice->DisableAutoNeg = FALSE; + + if (line_speed[index] == 0) { + pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO; + pDevice->DisableAutoNeg = FALSE; + } else { + if (line_speed[index] == 1000) { + if (pDevice->EnableTbi) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX; + } else if (full_duplex[index]) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX; + } else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS; + } + if (!pDevice->EnableTbi) + pDevice->DisableAutoNeg = FALSE; + } else if (line_speed[index] == 100) { + if (full_duplex[index]) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX; + } else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS; + } + } else if (line_speed[index] == 10) { + if (full_duplex[index]) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX; + } else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS; + } + } else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_AUTO; + pDevice->DisableAutoNeg = FALSE; + } + } - else if (line_speed[index] == 100) { - if (full_duplex[index]) { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX; - } - else { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS; - } - } - else if (line_speed[index] == 10) { - if (full_duplex[index]) { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX; - } - else { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS; - } + pDevice->FlowControlCap = 0; + if (rx_flow_control[index] != 0) { + pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE; } - else { - pDevice->RequestedMediaType = - LM_REQUESTED_MEDIA_TYPE_AUTO; - pDevice->DisableAutoNeg = FALSE; + if (tx_flow_control[index] != 0) { + pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; } - - } - pDevice->FlowControlCap = 0; - if (rx_flow_control[index] != 0) { - pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE; - } - if (tx_flow_control[index] != 0) { - pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; - } - if ((auto_flow_control[index] != 0) && - (pDevice->DisableAutoNeg == FALSE)) { - - pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE; - if ((tx_flow_control[index] == 0) && - (rx_flow_control[index] == 0)) { - pDevice->FlowControlCap |= - LM_FLOW_CONTROL_TRANSMIT_PAUSE | - LM_FLOW_CONTROL_RECEIVE_PAUSE; + if ((auto_flow_control[index] != 0) && + (pDevice->DisableAutoNeg == FALSE)) { + + pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE; + if ((tx_flow_control[index] == 0) && + (rx_flow_control[index] == 0)) { + pDevice->FlowControlCap |= + LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } } - } - /* Default MTU for now */ - pUmDevice->mtu = 1500; + /* Default MTU for now */ + pUmDevice->mtu = 1500; #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - if (pUmDevice->mtu > 1500) { - pDevice->RxMtu = pUmDevice->mtu; - pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; - } - else { - pDevice->RxJumboDescCnt = 0; - } - pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index]; + if (pUmDevice->mtu > 1500) { + pDevice->RxMtu = pUmDevice->mtu; + pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; + } else { + pDevice->RxJumboDescCnt = 0; + } + pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index]; #else - pDevice->RxMtu = pUmDevice->mtu; + pDevice->RxMtu = pUmDevice->mtu; #endif - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) { - pDevice->UseTaggedStatus = TRUE; - pUmDevice->timer_interval = CFG_HZ; - } - else { - pUmDevice->timer_interval = CFG_HZ/50; - } - - pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index]; - pDevice->RxStdDescCnt = rx_std_desc_cnt[index]; - /* Note: adaptive coalescence really isn't adaptive in this driver */ - pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index]; - if (!pUmDevice->rx_adaptive_coalesce) { - pDevice->RxCoalescingTicks = rx_coalesce_ticks[index]; - if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS) - pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS; - pUmDevice->rx_curr_coalesce_ticks =pDevice->RxCoalescingTicks; - - pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index]; - if (pDevice->RxMaxCoalescedFrames>MAX_RX_MAX_COALESCED_FRAMES) - pDevice->RxMaxCoalescedFrames = - MAX_RX_MAX_COALESCED_FRAMES; - pUmDevice->rx_curr_coalesce_frames = - pDevice->RxMaxCoalescedFrames; - pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index]; - if (pDevice->StatsCoalescingTicks>MAX_STATS_COALESCING_TICKS) - pDevice->StatsCoalescingTicks= - MAX_STATS_COALESCING_TICKS; - } - else { - pUmDevice->rx_curr_coalesce_frames = - DEFAULT_RX_MAX_COALESCED_FRAMES; - pUmDevice->rx_curr_coalesce_ticks = - DEFAULT_RX_COALESCING_TICKS; + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + pDevice->UseTaggedStatus = TRUE; + pUmDevice->timer_interval = CFG_HZ; + } else { + pUmDevice->timer_interval = CFG_HZ / 50; } - pDevice->TxCoalescingTicks = tx_coalesce_ticks[index]; - if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS) - pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS; - pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index]; - if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES) - pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES; - if (enable_wol[index]) { - pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET; - pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET; - } - pDevice->NicSendBd = TRUE; + pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index]; + pDevice->RxStdDescCnt = rx_std_desc_cnt[index]; + /* Note: adaptive coalescence really isn't adaptive in this driver */ + pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index]; + if (!pUmDevice->rx_adaptive_coalesce) { + pDevice->RxCoalescingTicks = rx_coalesce_ticks[index]; + if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS) + pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS; + pUmDevice->rx_curr_coalesce_ticks = pDevice->RxCoalescingTicks; + + pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index]; + if (pDevice->RxMaxCoalescedFrames > MAX_RX_MAX_COALESCED_FRAMES) + pDevice->RxMaxCoalescedFrames = + MAX_RX_MAX_COALESCED_FRAMES; + pUmDevice->rx_curr_coalesce_frames = + pDevice->RxMaxCoalescedFrames; + pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index]; + if (pDevice->StatsCoalescingTicks > MAX_STATS_COALESCING_TICKS) + pDevice->StatsCoalescingTicks = + MAX_STATS_COALESCING_TICKS; + } else { + pUmDevice->rx_curr_coalesce_frames = + DEFAULT_RX_MAX_COALESCED_FRAMES; + pUmDevice->rx_curr_coalesce_ticks = DEFAULT_RX_COALESCING_TICKS; + } + pDevice->TxCoalescingTicks = tx_coalesce_ticks[index]; + if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS) + pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS; + pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index]; + if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES) + pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES; + + if (enable_wol[index]) { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET; + pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET; + } + pDevice->NicSendBd = TRUE; - /* Don't update status blocks during interrupt */ - pDevice->RxCoalescingTicksDuringInt = 0; - pDevice->TxCoalescingTicksDuringInt = 0; + /* Don't update status blocks during interrupt */ + pDevice->RxCoalescingTicksDuringInt = 0; + pDevice->TxCoalescingTicksDuringInt = 0; - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } - -LM_STATUS -MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +LM_STATUS MM_StartTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) { - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - printf("Start TX DMA: dev=%d packet @0x%x\n", - (int)pUmDevice->index, (unsigned int)pPacket); + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + printf ("Start TX DMA: dev=%d packet @0x%x\n", + (int)pUmDevice->index, (unsigned int)pPacket); - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } -LM_STATUS -MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) { - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - printf("Complete TX DMA: dev=%d packet @0x%x\n", - (int)pUmDevice->index, (unsigned int)pPacket); - return LM_STATUS_SUCCESS; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + printf ("Complete TX DMA: dev=%d packet @0x%x\n", + (int)pUmDevice->index, (unsigned int)pPacket); + return LM_STATUS_SUCCESS; } - -LM_STATUS -MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status) +LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status) { - char buf[128]; - char lcd[4]; - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - LM_FLOW_CONTROL flow_control; - - pUmDevice->delayed_link_ind = 0; - memset(lcd, 0x0, 4); - - if (Status == LM_STATUS_LINK_DOWN) { - sprintf(buf,"eth%d: %s: NIC Link is down\n", - pUmDevice->index,pUmDevice->name); - lcd[0] = 'L';lcd[1]='N';lcd[2]='K';lcd[3] = '?'; - } else if (Status == LM_STATUS_LINK_ACTIVE) { - sprintf(buf,"eth%d:%s: ", pUmDevice->index, pUmDevice->name); - - if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS){ - strcat(buf,"1000 Mbps "); - lcd[0] = '1';lcd[1]='G';lcd[2]='B'; - } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS){ - strcat(buf,"100 Mbps "); - lcd[0] = '1';lcd[1]='0';lcd[2]='0'; - } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS){ - strcat(buf,"10 Mbps "); - lcd[0] = '1';lcd[1]='0';lcd[2]=' '; - } - if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL){ - strcat(buf, "full duplex"); - lcd[3] = 'F'; - } else { - strcat(buf, "half duplex"); - lcd[3] = 'H'; - } - strcat(buf, " link up"); - - flow_control = pDevice->FlowControl & - (LM_FLOW_CONTROL_RECEIVE_PAUSE | - LM_FLOW_CONTROL_TRANSMIT_PAUSE); - - if (flow_control) { - if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) { - strcat(buf,", receive "); - if (flow_control & LM_FLOW_CONTROL_TRANSMIT_PAUSE) - strcat(buf," & transmit "); - } - else { - strcat(buf,", transmit "); - } - strcat(buf,"flow control ON"); - } else { - strcat(buf, ", flow control OFF"); + char buf[128]; + char lcd[4]; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + LM_FLOW_CONTROL flow_control; + + pUmDevice->delayed_link_ind = 0; + memset (lcd, 0x0, 4); + + if (Status == LM_STATUS_LINK_DOWN) { + sprintf (buf, "eth%d: %s: NIC Link is down\n", + pUmDevice->index, pUmDevice->name); + lcd[0] = 'L'; + lcd[1] = 'N'; + lcd[2] = 'K'; + lcd[3] = '?'; + } else if (Status == LM_STATUS_LINK_ACTIVE) { + sprintf (buf, "eth%d:%s: ", pUmDevice->index, pUmDevice->name); + + if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) { + strcat (buf, "1000 Mbps "); + lcd[0] = '1'; + lcd[1] = 'G'; + lcd[2] = 'B'; + } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS) { + strcat (buf, "100 Mbps "); + lcd[0] = '1'; + lcd[1] = '0'; + lcd[2] = '0'; + } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) { + strcat (buf, "10 Mbps "); + lcd[0] = '1'; + lcd[1] = '0'; + lcd[2] = ' '; + } + if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) { + strcat (buf, "full duplex"); + lcd[3] = 'F'; + } else { + strcat (buf, "half duplex"); + lcd[3] = 'H'; + } + strcat (buf, " link up"); + + flow_control = pDevice->FlowControl & + (LM_FLOW_CONTROL_RECEIVE_PAUSE | + LM_FLOW_CONTROL_TRANSMIT_PAUSE); + + if (flow_control) { + if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) { + strcat (buf, ", receive "); + if (flow_control & + LM_FLOW_CONTROL_TRANSMIT_PAUSE) + strcat (buf, " & transmit "); + } else { + strcat (buf, ", transmit "); + } + strcat (buf, "flow control ON"); + } else { + strcat (buf, ", flow control OFF"); + } + strcat (buf, "\n"); + printf ("%s", buf); } - strcat(buf,"\n"); - printf("%s",buf); - } #if 0 - sysLedDsply(lcd[0],lcd[1],lcd[2],lcd[3]); + sysLedDsply (lcd[0], lcd[1], lcd[2], lcd[3]); #endif - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } -LM_STATUS -MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +LM_STATUS MM_FreeRxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) { - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - PUM_PACKET pUmPacket; - void *skb; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PUM_PACKET pUmPacket; + void *skb; - pUmPacket = (PUM_PACKET) pPacket; + pUmPacket = (PUM_PACKET) pPacket; - if ((skb = pUmPacket->skbuff)) - bcm570xPktFree(pUmDevice->index, skb); + if ((skb = pUmPacket->skbuff)) + bcm570xPktFree (pUmDevice->index, skb); - pUmPacket->skbuff = 0; + pUmPacket->skbuff = 0; - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } -unsigned long -MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo) +unsigned long MM_AnGetCurrentTime_us (PAN_STATE_INFO pAnInfo) { - return get_timer(0); + return get_timer (0); } /* @@ -1258,86 +1220,82 @@ MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo) * non-fatal. The incoming cluster chain is not freed, giving * the caller the choice of whether to try a retransmit later. */ -LM_STATUS -MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +LM_STATUS MM_CoalesceTxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) { - PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - void *skbnew; - int len = 0; - - if (len == 0) - return (LM_STATUS_SUCCESS); - - if (len > MAX_PACKET_SIZE){ - printf ("eth%d: xmit frame discarded, too big!, size = %d\n", - pUmDevice->index, len); - return (LM_STATUS_FAILURE); - } + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + void *skbnew; + int len = 0; + + if (len == 0) + return (LM_STATUS_SUCCESS); + + if (len > MAX_PACKET_SIZE) { + printf ("eth%d: xmit frame discarded, too big!, size = %d\n", + pUmDevice->index, len); + return (LM_STATUS_FAILURE); + } - skbnew = bcm570xPktAlloc(pUmDevice->index, MAX_PACKET_SIZE); + skbnew = bcm570xPktAlloc (pUmDevice->index, MAX_PACKET_SIZE); - if (skbnew == NULL) { - pUmDevice->tx_full = 1; - printf ("eth%d: out of transmit buffers", pUmDevice->index); - return (LM_STATUS_FAILURE); - } + if (skbnew == NULL) { + pUmDevice->tx_full = 1; + printf ("eth%d: out of transmit buffers", pUmDevice->index); + return (LM_STATUS_FAILURE); + } - /* New packet values */ - pUmPacket->skbuff = skbnew; - pUmPacket->lm_packet.u.Tx.FragCount = 1; + /* New packet values */ + pUmPacket->skbuff = skbnew; + pUmPacket->lm_packet.u.Tx.FragCount = 1; - return (LM_STATUS_SUCCESS); + return (LM_STATUS_SUCCESS); } - -LM_STATUS -MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice) +LM_STATUS MM_IndicateRxPackets (PLM_DEVICE_BLOCK pDevice) { - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - pUmDevice->rx_pkt = 1; - return LM_STATUS_SUCCESS; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + pUmDevice->rx_pkt = 1; + return LM_STATUS_SUCCESS; } -LM_STATUS -MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice) +LM_STATUS MM_IndicateTxPackets (PLM_DEVICE_BLOCK pDevice) { - PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; - PLM_PACKET pPacket; - PUM_PACKET pUmPacket; - void *skb; - while ( TRUE ) { - - pPacket = (PLM_PACKET) - QQ_PopHead(&pDevice->TxPacketXmittedQ.Container); - - if (pPacket == 0) - break; - - pUmPacket = (PUM_PACKET) pPacket; - skb = (void*)pUmPacket->skbuff; - - /* - * Free MBLK if we transmitted a fragmented packet or a - * non-fragmented packet straight from the VxWorks - * buffer pool. If packet was copied to a local transmit - * buffer, then there's no MBUF to free, just free - * the transmit buffer back to the cluster pool. - */ - - if (skb) - bcm570xPktFree (pUmDevice->index, skb); - - pUmPacket->skbuff = 0; - QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket); - pUmDevice->tx_pkt = 1; - } - if (pUmDevice->tx_full) { - if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) >= - (QQ_GetSize(&pDevice->TxPacketFreeQ.Container) >> 1)) - pUmDevice->tx_full = 0; - } - return LM_STATUS_SUCCESS; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + void *skb; + while (TRUE) { + + pPacket = (PLM_PACKET) + QQ_PopHead (&pDevice->TxPacketXmittedQ.Container); + + if (pPacket == 0) + break; + + pUmPacket = (PUM_PACKET) pPacket; + skb = (void *)pUmPacket->skbuff; + + /* + * Free MBLK if we transmitted a fragmented packet or a + * non-fragmented packet straight from the VxWorks + * buffer pool. If packet was copied to a local transmit + * buffer, then there's no MBUF to free, just free + * the transmit buffer back to the cluster pool. + */ + + if (skb) + bcm570xPktFree (pUmDevice->index, skb); + + pUmPacket->skbuff = 0; + QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket); + pUmDevice->tx_pkt = 1; + } + if (pUmDevice->tx_full) { + if (QQ_GetEntryCnt (&pDevice->TxPacketFreeQ.Container) >= + (QQ_GetSize (&pDevice->TxPacketFreeQ.Container) >> 1)) + pUmDevice->tx_full = 0; + } + return LM_STATUS_SUCCESS; } /* @@ -1345,16 +1303,12 @@ MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice) * Return its length and physical address. */ void MM_MapTxDma - ( - PLM_DEVICE_BLOCK pDevice, - struct _LM_PACKET *pPacket, - T3_64BIT_HOST_ADDR *paddr, - LM_UINT32 *len, - int frag) -{ - PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; - *len = pPacket->PacketSize; - MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff); + (PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, + T3_64BIT_HOST_ADDR * paddr, LM_UINT32 * len, int frag) { + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + *len = pPacket->PacketSize; + MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff); } /* @@ -1362,35 +1316,31 @@ void MM_MapTxDma * to a physical address as seen from a PCI device. Store the * result at paddr. */ -void MM_MapRxDma( - PLM_DEVICE_BLOCK pDevice, - struct _LM_PACKET *pPacket, - T3_64BIT_HOST_ADDR *paddr) +void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr) { - PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; - MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff); + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff); } -void -MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr) +void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr) { #if (BITS_PER_LONG == 64) - paddr->High = ((unsigned long) addr) >> 32; - paddr->Low = ((unsigned long) addr) & 0xffffffff; + paddr->High = ((unsigned long)addr) >> 32; + paddr->Low = ((unsigned long)addr) & 0xffffffff; #else paddr->High = 0; - paddr->Low = (unsigned long) addr; + paddr->Low = (unsigned long)addr; #endif } -void -MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr) +void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr) { - unsigned long baddr = (unsigned long) addr; + unsigned long baddr = (unsigned long)addr; #if (BITS_PER_LONG == 64) - set_64bit_addr(paddr, baddr & 0xffffffff, baddr >> 32); + set_64bit_addr (paddr, baddr & 0xffffffff, baddr >> 32); #else - set_64bit_addr(paddr, baddr, 0); + set_64bit_addr (paddr, baddr, 0); #endif } @@ -1403,42 +1353,38 @@ MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr) * If any uses of the function remain, they will refer to the single copy * in the library. */ -void -atomic_set(atomic_t* entry, int val) +void atomic_set (atomic_t * entry, int val) { - entry->counter = val; + entry->counter = val; } -int -atomic_read(atomic_t* entry) + +int atomic_read (atomic_t * entry) { - return entry->counter; + return entry->counter; } -void -atomic_inc(atomic_t* entry) + +void atomic_inc (atomic_t * entry) { - if(entry) - entry->counter++; + if (entry) + entry->counter++; } -void -atomic_dec(atomic_t* entry) +void atomic_dec (atomic_t * entry) { - if(entry) - entry->counter--; + if (entry) + entry->counter--; } -void -atomic_sub(int a, atomic_t* entry) +void atomic_sub (int a, atomic_t * entry) { - if(entry) - entry->counter -= a; + if (entry) + entry->counter -= a; } -void -atomic_add(int a, atomic_t* entry) +void atomic_add (int a, atomic_t * entry) { - if(entry) - entry->counter += a; + if (entry) + entry->counter += a; } /******************************************************************************/ @@ -1446,68 +1392,57 @@ atomic_add(int a, atomic_t* entry) /* */ /* Return: */ /******************************************************************************/ -void -QQ_InitQueue( -PQQ_CONTAINER pQueue, -unsigned int QueueSize) { - pQueue->Head = 0; - pQueue->Tail = 0; - pQueue->Size = QueueSize+1; - atomic_set(&pQueue->EntryCnt, 0); -} /* QQ_InitQueue */ - +void QQ_InitQueue (PQQ_CONTAINER pQueue, unsigned int QueueSize) +{ + pQueue->Head = 0; + pQueue->Tail = 0; + pQueue->Size = QueueSize + 1; + atomic_set (&pQueue->EntryCnt, 0); +} /* QQ_InitQueue */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -char -QQ_Full( -PQQ_CONTAINER pQueue) { - unsigned int NewHead; - - NewHead = (pQueue->Head + 1) % pQueue->Size; +char QQ_Full (PQQ_CONTAINER pQueue) +{ + unsigned int NewHead; - return(NewHead == pQueue->Tail); -} /* QQ_Full */ + NewHead = (pQueue->Head + 1) % pQueue->Size; + return (NewHead == pQueue->Tail); +} /* QQ_Full */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -char -QQ_Empty( -PQQ_CONTAINER pQueue) { - return(pQueue->Head == pQueue->Tail); -} /* QQ_Empty */ - +char QQ_Empty (PQQ_CONTAINER pQueue) +{ + return (pQueue->Head == pQueue->Tail); +} /* QQ_Empty */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -unsigned int -QQ_GetSize( -PQQ_CONTAINER pQueue) { - return pQueue->Size; -} /* QQ_GetSize */ - +unsigned int QQ_GetSize (PQQ_CONTAINER pQueue) +{ + return pQueue->Size; +} /* QQ_GetSize */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -unsigned int -QQ_GetEntryCnt( -PQQ_CONTAINER pQueue) { - return atomic_read(&pQueue->EntryCnt); -} /* QQ_GetEntryCnt */ - +unsigned int QQ_GetEntryCnt (PQQ_CONTAINER pQueue) +{ + return atomic_read (&pQueue->EntryCnt); +} /* QQ_GetEntryCnt */ /******************************************************************************/ /* Description: */ @@ -1516,28 +1451,25 @@ PQQ_CONTAINER pQueue) { /* TRUE entry was added successfully. */ /* FALSE queue is full. */ /******************************************************************************/ -char -QQ_PushHead( -PQQ_CONTAINER pQueue, -PQQ_ENTRY pEntry) { - unsigned int Head; +char QQ_PushHead (PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry) +{ + unsigned int Head; - Head = (pQueue->Head + 1) % pQueue->Size; + Head = (pQueue->Head + 1) % pQueue->Size; #if !defined(QQ_NO_OVERFLOW_CHECK) - if(Head == pQueue->Tail) { - return 0; - } /* if */ -#endif /* QQ_NO_OVERFLOW_CHECK */ + if (Head == pQueue->Tail) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ - pQueue->Array[pQueue->Head] = pEntry; - wmb(); - pQueue->Head = Head; - atomic_inc(&pQueue->EntryCnt); - - return -1; -} /* QQ_PushHead */ + pQueue->Array[pQueue->Head] = pEntry; + wmb (); + pQueue->Head = Head; + atomic_inc (&pQueue->EntryCnt); + return -1; +} /* QQ_PushHead */ /******************************************************************************/ /* Description: */ @@ -1546,146 +1478,126 @@ PQQ_ENTRY pEntry) { /* TRUE entry was added successfully. */ /* FALSE queue is full. */ /******************************************************************************/ -char -QQ_PushTail( -PQQ_CONTAINER pQueue, -PQQ_ENTRY pEntry) { - unsigned int Tail; - - Tail = pQueue->Tail; - if(Tail == 0) { - Tail = pQueue->Size; - } /* if */ - Tail--; +char QQ_PushTail (PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry) +{ + unsigned int Tail; -#if !defined(QQ_NO_OVERFLOW_CHECK) - if(Tail == pQueue->Head) { - return 0; - } /* if */ -#endif /* QQ_NO_OVERFLOW_CHECK */ + Tail = pQueue->Tail; + if (Tail == 0) { + Tail = pQueue->Size; + } /* if */ + Tail--; - pQueue->Array[Tail] = pEntry; - wmb(); - pQueue->Tail = Tail; - atomic_inc(&pQueue->EntryCnt); +#if !defined(QQ_NO_OVERFLOW_CHECK) + if (Tail == pQueue->Head) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ - return -1; -} /* QQ_PushTail */ + pQueue->Array[Tail] = pEntry; + wmb (); + pQueue->Tail = Tail; + atomic_inc (&pQueue->EntryCnt); + return -1; +} /* QQ_PushTail */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -PQQ_ENTRY -QQ_PopHead( -PQQ_CONTAINER pQueue) { - unsigned int Head; - PQQ_ENTRY Entry; +PQQ_ENTRY QQ_PopHead (PQQ_CONTAINER pQueue) +{ + unsigned int Head; + PQQ_ENTRY Entry; - Head = pQueue->Head; + Head = pQueue->Head; #if !defined(QQ_NO_UNDERFLOW_CHECK) - if(Head == pQueue->Tail) { - return (PQQ_ENTRY) 0; - } /* if */ -#endif /* QQ_NO_UNDERFLOW_CHECK */ - - if(Head == 0) { - Head = pQueue->Size; - } /* if */ - Head--; + if (Head == pQueue->Tail) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ - Entry = pQueue->Array[Head]; - membar(); + if (Head == 0) { + Head = pQueue->Size; + } /* if */ + Head--; - pQueue->Head = Head; - atomic_dec(&pQueue->EntryCnt); + Entry = pQueue->Array[Head]; + membar (); - return Entry; -} /* QQ_PopHead */ + pQueue->Head = Head; + atomic_dec (&pQueue->EntryCnt); + return Entry; +} /* QQ_PopHead */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -PQQ_ENTRY -QQ_PopTail( -PQQ_CONTAINER pQueue) { - unsigned int Tail; - PQQ_ENTRY Entry; +PQQ_ENTRY QQ_PopTail (PQQ_CONTAINER pQueue) +{ + unsigned int Tail; + PQQ_ENTRY Entry; - Tail = pQueue->Tail; + Tail = pQueue->Tail; #if !defined(QQ_NO_UNDERFLOW_CHECK) - if(Tail == pQueue->Head) { - return (PQQ_ENTRY) 0; - } /* if */ -#endif /* QQ_NO_UNDERFLOW_CHECK */ - - Entry = pQueue->Array[Tail]; - membar(); - pQueue->Tail = (Tail + 1) % pQueue->Size; - atomic_dec(&pQueue->EntryCnt); + if (Tail == pQueue->Head) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ - return Entry; -} /* QQ_PopTail */ + Entry = pQueue->Array[Tail]; + membar (); + pQueue->Tail = (Tail + 1) % pQueue->Size; + atomic_dec (&pQueue->EntryCnt); + return Entry; +} /* QQ_PopTail */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -PQQ_ENTRY -QQ_GetHead( - PQQ_CONTAINER pQueue, - unsigned int Idx) +PQQ_ENTRY QQ_GetHead (PQQ_CONTAINER pQueue, unsigned int Idx) { - if(Idx >= atomic_read(&pQueue->EntryCnt)) - { - return (PQQ_ENTRY) 0; - } - - if(pQueue->Head > Idx) - { - Idx = pQueue->Head - Idx; - } - else - { - Idx = pQueue->Size - (Idx - pQueue->Head); - } - Idx--; - - return pQueue->Array[Idx]; -} + if (Idx >= atomic_read (&pQueue->EntryCnt)) { + return (PQQ_ENTRY) 0; + } + + if (pQueue->Head > Idx) { + Idx = pQueue->Head - Idx; + } else { + Idx = pQueue->Size - (Idx - pQueue->Head); + } + Idx--; + return pQueue->Array[Idx]; +} /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -PQQ_ENTRY -QQ_GetTail( - PQQ_CONTAINER pQueue, - unsigned int Idx) +PQQ_ENTRY QQ_GetTail (PQQ_CONTAINER pQueue, unsigned int Idx) { - if(Idx >= atomic_read(&pQueue->EntryCnt)) - { - return (PQQ_ENTRY) 0; - } - - Idx += pQueue->Tail; - if(Idx >= pQueue->Size) - { - Idx = Idx - pQueue->Size; - } - - return pQueue->Array[Idx]; + if (Idx >= atomic_read (&pQueue->EntryCnt)) { + return (PQQ_ENTRY) 0; + } + + Idx += pQueue->Tail; + if (Idx >= pQueue->Size) { + Idx = Idx - pQueue->Size; + } + + return pQueue->Array[Idx]; } -#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_BCM570x */ +#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_BCM570x */ diff --git a/drivers/bcm570x_lm.h b/drivers/bcm570x_lm.h index 607f3fd067c..2ea6ca8fa9c 100644 --- a/drivers/bcm570x_lm.h +++ b/drivers/bcm570x_lm.h @@ -19,29 +19,28 @@ #include "bcm570x_queue.h" #include "bcm570x_bits.h" - /******************************************************************************/ /* Basic types. */ /******************************************************************************/ -typedef char LM_CHAR, *PLM_CHAR; -typedef unsigned int LM_UINT, *PLM_UINT; -typedef unsigned char LM_UINT8, *PLM_UINT8; -typedef unsigned short LM_UINT16, *PLM_UINT16; -typedef unsigned int LM_UINT32, *PLM_UINT32; -typedef unsigned int LM_COUNTER, *PLM_COUNTER; -typedef void LM_VOID, *PLM_VOID; -typedef char LM_BOOL, *PLM_BOOL; +typedef char LM_CHAR, *PLM_CHAR; +typedef unsigned int LM_UINT, *PLM_UINT; +typedef unsigned char LM_UINT8, *PLM_UINT8; +typedef unsigned short LM_UINT16, *PLM_UINT16; +typedef unsigned int LM_UINT32, *PLM_UINT32; +typedef unsigned int LM_COUNTER, *PLM_COUNTER; +typedef void LM_VOID, *PLM_VOID; +typedef char LM_BOOL, *PLM_BOOL; /* 64bit value. */ typedef struct { #ifdef BIG_ENDIAN_HOST - LM_UINT32 High; - LM_UINT32 Low; -#else /* BIG_ENDIAN_HOST */ - LM_UINT32 Low; - LM_UINT32 High; -#endif /* !BIG_ENDIAN_HOST */ + LM_UINT32 High; + LM_UINT32 Low; +#else /* BIG_ENDIAN_HOST */ + LM_UINT32 Low; + LM_UINT32 High; +#endif /* !BIG_ENDIAN_HOST */ } LM_UINT64, *PLM_UINT64; typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; @@ -58,15 +57,13 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; } \ } - #ifndef NULL #define NULL ((void *) 0) -#endif /* NULL */ +#endif /* NULL */ #ifndef OFFSETOF #define OFFSETOF(_s, _m) (MM_UINT_PTR(&(((_s *) 0)->_m))) -#endif /* OFFSETOF */ - +#endif /* OFFSETOF */ /******************************************************************************/ /* Simple macros. */ @@ -100,26 +97,24 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; ((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4]; \ ((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5]; - /******************************************************************************/ /* Constants. */ /******************************************************************************/ #define ETHERNET_ADDRESS_SIZE 6 #define ETHERNET_PACKET_HEADER_SIZE 14 -#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */ -#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */ +#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */ +#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */ #define MIN_ETHERNET_PACKET_SIZE_NO_CRC 60 #define MAX_ETHERNET_PACKET_SIZE_NO_CRC 1514 -#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */ +#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */ #ifndef LM_MAX_MC_TABLE_SIZE #define LM_MAX_MC_TABLE_SIZE 32 -#endif /* LM_MAX_MC_TABLE_SIZE */ +#endif /* LM_MAX_MC_TABLE_SIZE */ #define LM_MC_ENTRY_SIZE (ETHERNET_ADDRESS_SIZE+1) #define LM_MC_INSTANCE_COUNT_INDEX (LM_MC_ENTRY_SIZE-1) - /* Receive filter masks. */ #define LM_ACCEPT_UNICAST 0x0001 #define LM_ACCEPT_MULTICAST 0x0002 @@ -129,7 +124,6 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; #define LM_PROMISCUOUS_MODE 0x10000 - /******************************************************************************/ /* PCI registers. */ /******************************************************************************/ @@ -169,20 +163,20 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; /******************************************************************************/ typedef struct { - LM_UINT32 FragSize; - LM_PHYSICAL_ADDRESS FragBuf; + LM_UINT32 FragSize; + LM_PHYSICAL_ADDRESS FragBuf; } LM_FRAG, *PLM_FRAG; typedef struct { - /* FragCount is initialized for the caller to the maximum array size, on */ - /* return FragCount is the number of the actual fragments in the array. */ - LM_UINT32 FragCount; + /* FragCount is initialized for the caller to the maximum array size, on */ + /* return FragCount is the number of the actual fragments in the array. */ + LM_UINT32 FragCount; - /* Total buffer size. */ - LM_UINT32 TotalSize; + /* Total buffer size. */ + LM_UINT32 TotalSize; - /* Fragment array buffer. */ - LM_FRAG Fragments[1]; + /* Fragment array buffer. */ + LM_FRAG Fragments[1]; } LM_FRAG_LIST, *PLM_FRAG_LIST; #define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \ @@ -191,7 +185,6 @@ typedef struct { LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1]; \ } _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME - /******************************************************************************/ /* Status codes. */ /******************************************************************************/ @@ -217,7 +210,6 @@ typedef struct { typedef LM_UINT LM_STATUS, *PLM_STATUS; - /******************************************************************************/ /* Requested media type. */ /******************************************************************************/ @@ -240,7 +232,6 @@ typedef LM_UINT LM_STATUS, *PLM_STATUS; typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE; - /******************************************************************************/ /* Media type. */ /******************************************************************************/ @@ -254,7 +245,6 @@ typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE; typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE; - /******************************************************************************/ /* Line speed. */ /******************************************************************************/ @@ -266,7 +256,6 @@ typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE; typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED; - /******************************************************************************/ /* Duplex mode. */ /******************************************************************************/ @@ -277,7 +266,6 @@ typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED; typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE; - /******************************************************************************/ /* Power state. */ /******************************************************************************/ @@ -289,7 +277,6 @@ typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE; typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE; - /******************************************************************************/ /* Task offloading. */ /******************************************************************************/ @@ -305,7 +292,6 @@ typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE; typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD; - /******************************************************************************/ /* Flow control. */ /******************************************************************************/ @@ -324,7 +310,6 @@ typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD; typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL; - /******************************************************************************/ /* Wake up mode. */ /******************************************************************************/ @@ -336,7 +321,6 @@ typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL; typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE; - /******************************************************************************/ /* Counters. */ /******************************************************************************/ @@ -362,7 +346,6 @@ typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE; typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE; - /******************************************************************************/ /* Forward definition. */ /******************************************************************************/ @@ -370,82 +353,82 @@ typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE; typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK; typedef struct _LM_PACKET *PLM_PACKET; - /******************************************************************************/ /* Function prototypes. */ /******************************************************************************/ -LM_STATUS LM_GetAdapterInfo(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_InitializeAdapter(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_ResetAdapter(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_DisableInterrupt(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_EnableInterrupt(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); -LM_STATUS LM_ServiceInterrupts(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask); -LM_STATUS LM_Halt(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_MulticastAdd(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); -LM_STATUS LM_MulticastDel(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); -LM_STATUS LM_MulticastClear(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_SetMacAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress); -LM_STATUS LM_LoopbackAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress); - -LM_UINT32 LM_GetCrcCounter(PLM_DEVICE_BLOCK pDevice); - -LM_WAKE_UP_MODE LM_PMCapabilities(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_NwufAdd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, - LM_UINT8 *pByteMask, LM_UINT8 *pPattern); -LM_STATUS LM_NwufRemove(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, - LM_UINT8 *pByteMask, LM_UINT8 *pPattern); -LM_STATUS LM_SetPowerState(PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel); - -LM_VOID LM_ReadPhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, - PLM_UINT32 pData32); -LM_VOID LM_WritePhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, - LM_UINT32 Data32); - -LM_STATUS LM_ControlLoopBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control); -LM_STATUS LM_SetupPhy(PLM_DEVICE_BLOCK pDevice); -int LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration); - +LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask); +LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); +LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); +LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress); +LM_STATUS LM_LoopbackAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress); + +LM_UINT32 LM_GetCrcCounter (PLM_DEVICE_BLOCK pDevice); + +LM_WAKE_UP_MODE LM_PMCapabilities (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_NwufAdd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, + LM_UINT8 * pByteMask, LM_UINT8 * pPattern); +LM_STATUS LM_NwufRemove (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, + LM_UINT8 * pByteMask, LM_UINT8 * pPattern); +LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice, + LM_POWER_STATE PowerLevel); + +LM_VOID LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, + PLM_UINT32 pData32); +LM_VOID LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, + LM_UINT32 Data32); + +LM_STATUS LM_ControlLoopBack (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control); +LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice); +int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration); /******************************************************************************/ /* These are the OS specific functions called by LMAC. */ /******************************************************************************/ -LM_STATUS MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, - LM_UINT16 *pValue16); -LM_STATUS MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, - LM_UINT16 Value16); -LM_STATUS MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, - LM_UINT32 *pValue32); -LM_STATUS MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, - LM_UINT32 Value32); -LM_STATUS MM_MapMemBase(PLM_DEVICE_BLOCK pDevice); -LM_STATUS MM_MapIoBase(PLM_DEVICE_BLOCK pDevice); -LM_STATUS MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice); -LM_STATUS MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice); -LM_STATUS MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); -LM_STATUS MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); -LM_STATUS MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, - PLM_VOID *pMemoryBlockVirt); -LM_STATUS MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, - PLM_VOID *pMemoryBlockVirt, PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, - LM_BOOL Cached); -LM_STATUS MM_GetConfig(PLM_DEVICE_BLOCK pDevice); -LM_STATUS MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status); -LM_STATUS MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice); -LM_STATUS MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); -LM_STATUS MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); -LM_STATUS LM_MbufWorkAround(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_SetLinkSpeed(PLM_DEVICE_BLOCK pDevice, - LM_REQUESTED_MEDIA_TYPE RequestedMediaType); +LM_STATUS MM_ReadConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT16 * pValue16); +LM_STATUS MM_WriteConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT16 Value16); +LM_STATUS MM_ReadConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 * pValue32); +LM_STATUS MM_WriteConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 Value32); +LM_STATUS MM_MapMemBase (PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_MapIoBase (PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateRxPackets (PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateTxPackets (PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_StartTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID * pMemoryBlockVirt); +LM_STATUS MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice, + LM_UINT32 BlockSize, + PLM_VOID * pMemoryBlockVirt, + PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, + LM_BOOL Cached); +LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status); +LM_STATUS MM_InitializeUmPackets (PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_FreeRxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_CoalesceTxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS LM_MbufWorkAround (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetLinkSpeed (PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType); #if INCLUDE_5703_A0_FIX -LM_STATUS LM_Load5703DmaWFirmware(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_Load5703DmaWFirmware (PLM_DEVICE_BLOCK pDevice); #endif - -#endif /* LM_H */ +#endif /* LM_H */ diff --git a/drivers/bcm570x_mm.h b/drivers/bcm570x_mm.h index b7cbf8abd4b..ff5302f47c8 100644 --- a/drivers/bcm570x_mm.h +++ b/drivers/bcm570x_mm.h @@ -45,7 +45,7 @@ extern int MM_Packet_Desc_Size; #define MM_PACKET_DESC_SIZE MM_Packet_Desc_Size -DECLARE_QUEUE_TYPE(UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT+1); +DECLARE_QUEUE_TYPE (UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT + 1); #define MAX_MEM 16 @@ -65,51 +65,50 @@ typedef struct _UM_DEVICE_BLOCK { int mtu; int index; int opened; - int delayed_link_ind; /* Delay link status during initial load */ - int adapter_just_inited; /* the first few seconds after init. */ - int spurious_int; /* new -- unsupported */ + int delayed_link_ind; /* Delay link status during initial load */ + int adapter_just_inited; /* the first few seconds after init. */ + int spurious_int; /* new -- unsupported */ int timer_interval; int adaptive_expiry; - int crc_counter_expiry; /* new -- unsupported */ - int poll_tib_expiry; /* new -- unsupported */ + int crc_counter_expiry; /* new -- unsupported */ + int poll_tib_expiry; /* new -- unsupported */ int tx_full; int tx_queued; int line_speed; /* in Mbps, 0 if link is down */ UM_RX_PACKET_Q rx_out_of_buf_q; int rx_out_of_buf; - int rx_low_buf_thresh; /* changed to rx_buf_repl_thresh */ + int rx_low_buf_thresh; /* changed to rx_buf_repl_thresh */ int rx_buf_repl_panic_thresh; - int rx_buf_align; /* new -- unsupported */ + int rx_buf_align; /* new -- unsupported */ int do_global_lock; mutex_t global_lock; mutex_t undi_lock; long undi_flags; volatile int interrupt; int tasklet_pending; - int tasklet_busy; /* new -- unsupported */ + int tasklet_busy; /* new -- unsupported */ int rx_pkt; int tx_pkt; -#ifdef NICE_SUPPORT /* unsupported, this is a linux ioctl */ - void (*nice_rx)(void*, void* ); - void* nice_ctx; -#endif /* NICE_SUPPORT */ +#ifdef NICE_SUPPORT /* unsupported, this is a linux ioctl */ + void (*nice_rx) (void *, void *); + void *nice_ctx; +#endif /* NICE_SUPPORT */ int rx_adaptive_coalesce; unsigned int rx_last_cnt; unsigned int tx_last_cnt; unsigned int rx_curr_coalesce_frames; unsigned int rx_curr_coalesce_ticks; - unsigned int tx_curr_coalesce_frames; /* new -- unsupported */ -#if TIGON3_DEBUG /* new -- unsupported */ + unsigned int tx_curr_coalesce_frames; /* new -- unsupported */ +#if TIGON3_DEBUG /* new -- unsupported */ uint tx_zc_count; uint tx_chksum_count; uint tx_himem_count; uint rx_good_chksum_count; #endif - unsigned int rx_bad_chksum_count; /* new -- unsupported */ - unsigned int rx_misc_errors; /* new -- unsupported */ + unsigned int rx_bad_chksum_count; /* new -- unsupported */ + unsigned int rx_misc_errors; /* new -- unsupported */ } UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK; - /* Physical/PCI DMA address */ typedef union { dma_addr_t dma_map; @@ -117,9 +116,9 @@ typedef union { /* Packet */ typedef struct -_UM_PACKET { - LM_PACKET lm_packet; - void* skbuff; /* Address of packet buffer */ + _UM_PACKET { + LM_PACKET lm_packet; + void *skbuff; /* Address of packet buffer */ } UM_PACKET, *PUM_PACKET; #define MM_ACQUIRE_UNDI_LOCK(_pDevice) @@ -137,15 +136,14 @@ _UM_PACKET { #define MEM_TO_PCI_PHYS(addr) (addr) -extern void MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr); -extern void MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr); +extern void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr); +extern void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr); extern void MM_MapTxDma (PLM_DEVICE_BLOCK pDevice, - struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR *paddr, - LM_UINT32 *len, int frag); -extern void MM_MapRxDma ( PLM_DEVICE_BLOCK pDevice, - struct _LM_PACKET *pPacket, - T3_64BIT_HOST_ADDR *paddr); - + struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr, + LM_UINT32 * len, int frag); +extern void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, + T3_64BIT_HOST_ADDR * paddr); /* BSP needs to provide sysUsecDelay and sysSerialPrintString */ extern void sysSerialPrintString (char *s); @@ -157,4 +155,4 @@ extern void sysSerialPrintString (char *s); #if 0 #define cpu_to_le32(val) LONGSWAP(val) #endif -#endif /* MM_H */ +#endif /* MM_H */ diff --git a/drivers/tigon3.c b/drivers/tigon3.c index ec2cd2ac36f..91e22ebd21c 100644 --- a/drivers/tigon3.c +++ b/drivers/tigon3.c @@ -26,69 +26,70 @@ /* Local functions. */ /******************************************************************************/ -LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice); -LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice); - -static LM_STATUS LM_TranslateRequestedMediaType( - LM_REQUESTED_MEDIA_TYPE RequestedMediaType, - PLM_MEDIA_TYPE pMediaType, PLM_LINE_SPEED pLineSpeed, - PLM_DUPLEX_MODE pDuplexMode); - -static LM_STATUS LM_InitBcm540xPhy(PLM_DEVICE_BLOCK pDevice); - -__inline static LM_VOID LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice); -__inline static LM_VOID LM_ServiceTxInterrupt(PLM_DEVICE_BLOCK pDevice); - -static LM_STATUS LM_ForceAutoNegBcm540xPhy(PLM_DEVICE_BLOCK pDevice, - LM_REQUESTED_MEDIA_TYPE RequestedMediaType); -static LM_STATUS LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice, - LM_REQUESTED_MEDIA_TYPE RequestedMediaType); -static LM_UINT32 GetPhyAdFlowCntrlSettings(PLM_DEVICE_BLOCK pDevice); -STATIC LM_STATUS LM_SetFlowControl(PLM_DEVICE_BLOCK pDevice, - LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd); +LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice); + +static LM_STATUS LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE + RequestedMediaType, + PLM_MEDIA_TYPE pMediaType, + PLM_LINE_SPEED pLineSpeed, + PLM_DUPLEX_MODE pDuplexMode); + +static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice); + +__inline static LM_VOID LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice); +__inline static LM_VOID LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice); + +static LM_STATUS LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE + RequestedMediaType); +static LM_STATUS LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType); +static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice, + LM_UINT32 LocalPhyAd, + LM_UINT32 RemotePhyAd); #if INCLUDE_TBI_SUPPORT -STATIC LM_STATUS LM_SetupFiberPhy(PLM_DEVICE_BLOCK pDevice); -STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice); #endif -STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice); -STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid); -STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, - LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize); -STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number); -STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice); -STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, - PT3_SND_BD pSendBd); +STATIC LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice); +STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid, + LM_UINT16 Ssid); +STATIC LM_STATUS LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, + LM_PHYSICAL_ADDRESS BufferPhy, + LM_UINT32 BufferSize); +STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number); +STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice, + PLM_PACKET pPacket, PT3_SND_BD pSendBd); /******************************************************************************/ /* External functions. */ /******************************************************************************/ -LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice); - +LM_STATUS LM_LoadRlsFirmware (PLM_DEVICE_BLOCK pDevice); /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_UINT32 -LM_RegRdInd( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 Register) { - LM_UINT32 Value32; +LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register) +{ + LM_UINT32 Value32; #if PCIX_TARGET_WORKAROUND - MM_ACQUIRE_UNDI_LOCK(pDevice); + MM_ACQUIRE_UNDI_LOCK (pDevice); #endif - MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register); - MM_ReadConfig32(pDevice, T3_PCI_REG_DATA_REG, &Value32); + MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register); + MM_ReadConfig32 (pDevice, T3_PCI_REG_DATA_REG, &Value32); #if PCIX_TARGET_WORKAROUND - MM_RELEASE_UNDI_LOCK(pDevice); + MM_RELEASE_UNDI_LOCK (pDevice); #endif - return Value32; -} /* LM_RegRdInd */ - + return Value32; +} /* LM_RegRdInd */ /******************************************************************************/ /* Description: */ @@ -96,47 +97,41 @@ LM_UINT32 Register) { /* Return: */ /******************************************************************************/ LM_VOID -LM_RegWrInd( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 Register, -LM_UINT32 Value32) { +LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32) +{ #if PCIX_TARGET_WORKAROUND - MM_ACQUIRE_UNDI_LOCK(pDevice); + MM_ACQUIRE_UNDI_LOCK (pDevice); #endif - MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register); - MM_WriteConfig32(pDevice, T3_PCI_REG_DATA_REG, Value32); + MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register); + MM_WriteConfig32 (pDevice, T3_PCI_REG_DATA_REG, Value32); #if PCIX_TARGET_WORKAROUND - MM_RELEASE_UNDI_LOCK(pDevice); + MM_RELEASE_UNDI_LOCK (pDevice); #endif -} /* LM_RegWrInd */ - +} /* LM_RegWrInd */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_UINT32 -LM_MemRdInd( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 MemAddr) { - LM_UINT32 Value32; +LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr) +{ + LM_UINT32 Value32; - MM_ACQUIRE_UNDI_LOCK(pDevice); + MM_ACQUIRE_UNDI_LOCK (pDevice); #ifdef BIG_ENDIAN_HOST - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); - Value32 = REG_RD(pDevice, PciCfg.MemWindowData); - /* Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */ + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + Value32 = REG_RD (pDevice, PciCfg.MemWindowData); + /* Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */ #else - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); - MM_ReadConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32); + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + MM_ReadConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32); #endif - MM_RELEASE_UNDI_LOCK(pDevice); - - return Value32; -} /* LM_MemRdInd */ + MM_RELEASE_UNDI_LOCK (pDevice); + return Value32; +} /* LM_MemRdInd */ /******************************************************************************/ /* Description: */ @@ -144,168 +139,161 @@ LM_UINT32 MemAddr) { /* Return: */ /******************************************************************************/ LM_VOID -LM_MemWrInd( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 MemAddr, -LM_UINT32 Value32) { - MM_ACQUIRE_UNDI_LOCK(pDevice); +LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, LM_UINT32 Value32) +{ + MM_ACQUIRE_UNDI_LOCK (pDevice); #ifdef BIG_ENDIAN_HOST - REG_WR(pDevice,PciCfg.MemWindowBaseAddr,MemAddr); - REG_WR(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4],Value32); + REG_WR (pDevice, PciCfg.MemWindowBaseAddr, MemAddr); + REG_WR (pDevice, uIntMem.Mbuf[(MemAddr & 0x7fff) / 4], Value32); #else - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32); + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32); #endif - MM_RELEASE_UNDI_LOCK(pDevice); -} /* LM_MemWrInd */ - + MM_RELEASE_UNDI_LOCK (pDevice); +} /* LM_MemWrInd */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS -LM_QueueRxPackets( -PLM_DEVICE_BLOCK pDevice) { - LM_STATUS Lmstatus; - PLM_PACKET pPacket; - PT3_RCV_BD pRcvBd; - LM_UINT32 StdBdAdded = 0; +LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice) +{ + LM_STATUS Lmstatus; + PLM_PACKET pPacket; + PT3_RCV_BD pRcvBd; + LM_UINT32 StdBdAdded = 0; #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - LM_UINT32 JumboBdAdded = 0; -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + LM_UINT32 JumboBdAdded = 0; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - Lmstatus = LM_STATUS_SUCCESS; + Lmstatus = LM_STATUS_SUCCESS; - pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); - while(pPacket) { - switch(pPacket->u.Rx.RcvProdRing) { + pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container); + while (pPacket) { + switch (pPacket->u.Rx.RcvProdRing) { #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */ - /* Initialize the buffer descriptor. */ - pRcvBd = - &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx]; - pRcvBd->Flags = RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING; - pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize; - - /* Initialize the receive buffer pointer */ -#if 0 /* Jimmy, deleted in new */ - pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; - pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; + case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */ + /* Initialize the buffer descriptor. */ + pRcvBd = + &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx]; + pRcvBd->Flags = + RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING; + pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize; + + /* Initialize the receive buffer pointer */ +#if 0 /* Jimmy, deleted in new */ + pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; + pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; #endif - MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); + MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr); - /* The opaque field may point to an offset from a fix addr. */ - pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - - MM_UINT_PTR(pDevice->pPacketDescBase)); + /* The opaque field may point to an offset from a fix addr. */ + pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) - + MM_UINT_PTR (pDevice-> + pPacketDescBase)); - /* Update the producer index. */ - pDevice->RxJumboProdIdx = (pDevice->RxJumboProdIdx + 1) & - T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; + /* Update the producer index. */ + pDevice->RxJumboProdIdx = + (pDevice->RxJumboProdIdx + + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; - JumboBdAdded++; - break; -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - - case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */ - /* Initialize the buffer descriptor. */ - pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx]; - pRcvBd->Flags = RCV_BD_FLAG_END; - pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE; - - /* Initialize the receive buffer pointer */ -#if 0 /* Jimmy, deleted in new replaced with MM_MapRxDma */ - pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; - pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; + JumboBdAdded++; + break; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */ + /* Initialize the buffer descriptor. */ + pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx]; + pRcvBd->Flags = RCV_BD_FLAG_END; + pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE; + + /* Initialize the receive buffer pointer */ +#if 0 /* Jimmy, deleted in new replaced with MM_MapRxDma */ + pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; + pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; #endif - MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); + MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr); - /* The opaque field may point to an offset from a fix addr. */ - pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - - MM_UINT_PTR(pDevice->pPacketDescBase)); + /* The opaque field may point to an offset from a fix addr. */ + pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) - + MM_UINT_PTR (pDevice-> + pPacketDescBase)); - /* Update the producer index. */ - pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) & - T3_STD_RCV_RCB_ENTRY_COUNT_MASK; + /* Update the producer index. */ + pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) & + T3_STD_RCV_RCB_ENTRY_COUNT_MASK; - StdBdAdded++; - break; + StdBdAdded++; + break; - case T3_UNKNOWN_RCV_PROD_RING: - default: - Lmstatus = LM_STATUS_FAILURE; - break; - } /* switch */ + case T3_UNKNOWN_RCV_PROD_RING: + default: + Lmstatus = LM_STATUS_FAILURE; + break; + } /* switch */ - /* Bail out if there is any error. */ - if(Lmstatus != LM_STATUS_SUCCESS) - { - break; - } + /* Bail out if there is any error. */ + if (Lmstatus != LM_STATUS_SUCCESS) { + break; + } - pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); - } /* while */ + pPacket = + (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container); + } /* while */ - wmb(); - /* Update the procedure index. */ - if(StdBdAdded) - { - MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, pDevice->RxStdProdIdx); - } + wmb (); + /* Update the procedure index. */ + if (StdBdAdded) { + MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low, + pDevice->RxStdProdIdx); + } #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - if(JumboBdAdded) - { - MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, - pDevice->RxJumboProdIdx); - } -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - - return Lmstatus; -} /* LM_QueueRxPackets */ + if (JumboBdAdded) { + MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low, + pDevice->RxJumboProdIdx); + } +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + return Lmstatus; +} /* LM_QueueRxPackets */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -STATIC LM_VOID -LM_NvramInit( - PLM_DEVICE_BLOCK pDevice) +STATIC LM_VOID LM_NvramInit (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32; - LM_UINT32 j; - - /* Intialize clock period and state machine. */ - Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) | - SEEPROM_ADDR_FSM_RESET; - REG_WR(pDevice, Grc.EepromAddr, Value32); - - for(j = 0; j < 100; j++) - { - MM_Wait(10); - } - - /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */ - Value32 = REG_RD(pDevice, Grc.LocalCtrl); - REG_WR(pDevice, Grc.LocalCtrl, Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM); - - /* Set the 5701 compatibility mode if we are using EEPROM. */ - if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && - T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) - { - Value32 = REG_RD(pDevice, Nvram.Config1); - if((Value32 & FLASH_INTERFACE_ENABLE) == 0) - { - /* Use the new interface to read EEPROM. */ - Value32 &= ~FLASH_COMPAT_BYPASS; + LM_UINT32 Value32; + LM_UINT32 j; - REG_WR(pDevice, Nvram.Config1, Value32); + /* Intialize clock period and state machine. */ + Value32 = SEEPROM_ADDR_CLK_PERD (SEEPROM_CLOCK_PERIOD) | + SEEPROM_ADDR_FSM_RESET; + REG_WR (pDevice, Grc.EepromAddr, Value32); + + for (j = 0; j < 100; j++) { + MM_Wait (10); } - } -} /* LM_NvRamInit */ + /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */ + Value32 = REG_RD (pDevice, Grc.LocalCtrl); + REG_WR (pDevice, Grc.LocalCtrl, + Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM); + + /* Set the 5701 compatibility mode if we are using EEPROM. */ + if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) { + Value32 = REG_RD (pDevice, Nvram.Config1); + if ((Value32 & FLASH_INTERFACE_ENABLE) == 0) { + /* Use the new interface to read EEPROM. */ + Value32 &= ~FLASH_COMPAT_BYPASS; + + REG_WR (pDevice, Nvram.Config1, Value32); + } + } +} /* LM_NvRamInit */ /******************************************************************************/ /* Description: */ @@ -313,51 +301,44 @@ LM_NvramInit( /* Return: */ /******************************************************************************/ STATIC LM_STATUS -LM_EepromRead( - PLM_DEVICE_BLOCK pDevice, - LM_UINT32 Offset, - LM_UINT32 *pData) +LM_EepromRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData) { - LM_UINT32 Value32; - LM_UINT32 Addr; - LM_UINT32 Dev; - LM_UINT32 j; + LM_UINT32 Value32; + LM_UINT32 Addr; + LM_UINT32 Dev; + LM_UINT32 j; - if(Offset > SEEPROM_CHIP_SIZE) - { - return LM_STATUS_FAILURE; - } + if (Offset > SEEPROM_CHIP_SIZE) { + return LM_STATUS_FAILURE; + } - Dev = Offset / SEEPROM_CHIP_SIZE; - Addr = Offset % SEEPROM_CHIP_SIZE; + Dev = Offset / SEEPROM_CHIP_SIZE; + Addr = Offset % SEEPROM_CHIP_SIZE; - Value32 = REG_RD(pDevice, Grc.EepromAddr); - Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK | - SEEPROM_ADDR_RW_MASK); - REG_WR(pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID(Dev) | - SEEPROM_ADDR_ADDRESS(Addr) | SEEPROM_ADDR_START | SEEPROM_ADDR_READ); + Value32 = REG_RD (pDevice, Grc.EepromAddr); + Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK | + SEEPROM_ADDR_RW_MASK); + REG_WR (pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID (Dev) | + SEEPROM_ADDR_ADDRESS (Addr) | SEEPROM_ADDR_START | + SEEPROM_ADDR_READ); - for(j = 0; j < 1000; j++) - { - Value32 = REG_RD(pDevice, Grc.EepromAddr); - if(Value32 & SEEPROM_ADDR_COMPLETE) - { - break; + for (j = 0; j < 1000; j++) { + Value32 = REG_RD (pDevice, Grc.EepromAddr); + if (Value32 & SEEPROM_ADDR_COMPLETE) { + break; + } + MM_Wait (10); } - MM_Wait(10); - } - - if(Value32 & SEEPROM_ADDR_COMPLETE) - { - Value32 = REG_RD(pDevice, Grc.EepromData); - *pData = Value32; - return LM_STATUS_SUCCESS; - } + if (Value32 & SEEPROM_ADDR_COMPLETE) { + Value32 = REG_RD (pDevice, Grc.EepromData); + *pData = Value32; - return LM_STATUS_FAILURE; -} /* LM_EepromRead */ + return LM_STATUS_SUCCESS; + } + return LM_STATUS_FAILURE; +} /* LM_EepromRead */ /******************************************************************************/ /* Description: */ @@ -365,291 +346,248 @@ LM_EepromRead( /* Return: */ /******************************************************************************/ STATIC LM_STATUS -LM_NvramRead( - PLM_DEVICE_BLOCK pDevice, - LM_UINT32 Offset, - LM_UINT32 *pData) +LM_NvramRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData) { - LM_UINT32 Value32; - LM_STATUS Status; - LM_UINT32 j; - - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Status = LM_EepromRead(pDevice, Offset, pData); - } - else - { - /* Determine if we have flash or EEPROM. */ - Value32 = REG_RD(pDevice, Nvram.Config1); - if(Value32 & FLASH_INTERFACE_ENABLE) - { - if(Value32 & FLASH_SSRAM_BUFFERRED_MODE) - { - Offset = ((Offset/BUFFERED_FLASH_PAGE_SIZE) << - BUFFERED_FLASH_PAGE_POS) + - (Offset % BUFFERED_FLASH_PAGE_SIZE); - } - } + LM_UINT32 Value32; + LM_STATUS Status; + LM_UINT32 j; + + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Status = LM_EepromRead (pDevice, Offset, pData); + } else { + /* Determine if we have flash or EEPROM. */ + Value32 = REG_RD (pDevice, Nvram.Config1); + if (Value32 & FLASH_INTERFACE_ENABLE) { + if (Value32 & FLASH_SSRAM_BUFFERRED_MODE) { + Offset = ((Offset / BUFFERED_FLASH_PAGE_SIZE) << + BUFFERED_FLASH_PAGE_POS) + + (Offset % BUFFERED_FLASH_PAGE_SIZE); + } + } - REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); - for (j = 0; j < 1000; j++) - { - if (REG_RD(pDevice, Nvram.SwArb) & SW_ARB_GNT1) - { - break; - } - MM_Wait(20); - } - if (j == 1000) - { - return LM_STATUS_FAILURE; - } + REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); + for (j = 0; j < 1000; j++) { + if (REG_RD (pDevice, Nvram.SwArb) & SW_ARB_GNT1) { + break; + } + MM_Wait (20); + } + if (j == 1000) { + return LM_STATUS_FAILURE; + } - /* Read from flash or EEPROM with the new 5703/02 interface. */ - REG_WR(pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK); + /* Read from flash or EEPROM with the new 5703/02 interface. */ + REG_WR (pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK); - REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT | - NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); + REG_WR (pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT | + NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); - /* Wait for the done bit to clear. */ - for(j = 0; j < 500; j++) - { - MM_Wait(10); + /* Wait for the done bit to clear. */ + for (j = 0; j < 500; j++) { + MM_Wait (10); - Value32 = REG_RD(pDevice, Nvram.Cmd); - if(!(Value32 & NVRAM_CMD_DONE)) - { - break; - } - } + Value32 = REG_RD (pDevice, Nvram.Cmd); + if (!(Value32 & NVRAM_CMD_DONE)) { + break; + } + } - /* Wait for the done bit. */ - if(!(Value32 & NVRAM_CMD_DONE)) - { - for(j = 0; j < 500; j++) - { - MM_Wait(10); + /* Wait for the done bit. */ + if (!(Value32 & NVRAM_CMD_DONE)) { + for (j = 0; j < 500; j++) { + MM_Wait (10); - Value32 = REG_RD(pDevice, Nvram.Cmd); - if(Value32 & NVRAM_CMD_DONE) - { - MM_Wait(10); + Value32 = REG_RD (pDevice, Nvram.Cmd); + if (Value32 & NVRAM_CMD_DONE) { + MM_Wait (10); - *pData = REG_RD(pDevice, Nvram.ReadData); + *pData = + REG_RD (pDevice, Nvram.ReadData); - /* Change the endianess. */ - *pData = ((*pData & 0xff) << 24)| ((*pData & 0xff00) << 8)| - ((*pData & 0xff0000) >> 8) | ((*pData >> 24) & 0xff); + /* Change the endianess. */ + *pData = + ((*pData & 0xff) << 24) | + ((*pData & 0xff00) << 8) | + ((*pData & 0xff0000) >> 8) | + ((*pData >> 24) & 0xff); - break; + break; + } + } } - } - } - REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1); - if(Value32 & NVRAM_CMD_DONE) - { - Status = LM_STATUS_SUCCESS; - } - else - { - Status = LM_STATUS_FAILURE; + REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1); + if (Value32 & NVRAM_CMD_DONE) { + Status = LM_STATUS_SUCCESS; + } else { + Status = LM_STATUS_FAILURE; + } } - } - - return Status; -} /* LM_NvramRead */ + return Status; +} /* LM_NvramRead */ -STATIC void -LM_ReadVPD(PLM_DEVICE_BLOCK pDevice) +STATIC void LM_ReadVPD (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Vpd_arr[256/4]; - LM_UINT8 *Vpd = (LM_UINT8 *) &Vpd_arr[0]; - LM_UINT32 *Vpd_dptr = &Vpd_arr[0]; - LM_UINT32 Value32; - unsigned int j; - - /* Read PN from VPD */ - for (j = 0; j < 256; j += 4, Vpd_dptr++ ) - { - if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) { - printf("BCM570x: LM_ReadVPD: VPD read failed" - " (no EEPROM onboard)\n"); - return; - } - *Vpd_dptr = cpu_to_le32(Value32); - } - for (j = 0; j < 256; ) - { - unsigned int Vpd_r_len; - unsigned int Vpd_r_end; - - if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) - { - j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8); - } - else if (Vpd[j] == 0x90) - { - Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8); - j += 3; - Vpd_r_end = Vpd_r_len + j; - while (j < Vpd_r_end) - { - if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) - { - unsigned int len = Vpd[j + 2]; - - if (len <= 24) - { - memcpy(pDevice->PartNo, &Vpd[j + 3], len); - } - break; + LM_UINT32 Vpd_arr[256 / 4]; + LM_UINT8 *Vpd = (LM_UINT8 *) & Vpd_arr[0]; + LM_UINT32 *Vpd_dptr = &Vpd_arr[0]; + LM_UINT32 Value32; + unsigned int j; + + /* Read PN from VPD */ + for (j = 0; j < 256; j += 4, Vpd_dptr++) { + if (LM_NvramRead (pDevice, 0x100 + j, &Value32) != + LM_STATUS_SUCCESS) { + printf ("BCM570x: LM_ReadVPD: VPD read failed" + " (no EEPROM onboard)\n"); + return; } - else - { - if (Vpd[j + 2] == 0) - { + *Vpd_dptr = cpu_to_le32 (Value32); + } + for (j = 0; j < 256;) { + unsigned int Vpd_r_len; + unsigned int Vpd_r_end; + + if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) { + j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8); + } else if (Vpd[j] == 0x90) { + Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8); + j += 3; + Vpd_r_end = Vpd_r_len + j; + while (j < Vpd_r_end) { + if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) { + unsigned int len = Vpd[j + 2]; + + if (len <= 24) { + memcpy (pDevice->PartNo, + &Vpd[j + 3], len); + } + break; + } else { + if (Vpd[j + 2] == 0) { + break; + } + j = j + Vpd[j + 2]; + } + } + break; + } else { break; - } - j = j + Vpd[j + 2]; } - } - break; } - else { - break; - } - } } -STATIC void -LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice) +STATIC void LM_ReadBootCodeVersion (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32, offset, ver_offset; - int i; - - if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS) - return; - if (Value32 != 0xaa559966) - return; - if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS) - return; - - offset = ((offset & 0xff) << 24)| ((offset & 0xff00) << 8)| - ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff); - if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS) - return; - if ((Value32 == 0x0300000e) && - (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) && - (Value32 == 0)) { - - if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS) - return; - ver_offset = ((ver_offset & 0xff0000) >> 8) | - ((ver_offset >> 24) & 0xff); - for (i = 0; i < 16; i += 4) { - if (LM_NvramRead(pDevice, offset + ver_offset + i, &Value32) != - LM_STATUS_SUCCESS) - { + LM_UINT32 Value32, offset, ver_offset; + int i; + + if (LM_NvramRead (pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS) return; - } - *((LM_UINT32 *) &pDevice->BootCodeVer[i]) = cpu_to_le32(Value32); - } - } - else { - char c; + if (Value32 != 0xaa559966) + return; + if (LM_NvramRead (pDevice, 0xc, &offset) != LM_STATUS_SUCCESS) + return; + + offset = ((offset & 0xff) << 24) | ((offset & 0xff00) << 8) | + ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff); + if (LM_NvramRead (pDevice, offset, &Value32) != LM_STATUS_SUCCESS) + return; + if ((Value32 == 0x0300000e) && + (LM_NvramRead (pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) + && (Value32 == 0)) { + + if (LM_NvramRead (pDevice, offset + 8, &ver_offset) != + LM_STATUS_SUCCESS) + return; + ver_offset = ((ver_offset & 0xff0000) >> 8) | + ((ver_offset >> 24) & 0xff); + for (i = 0; i < 16; i += 4) { + if (LM_NvramRead + (pDevice, offset + ver_offset + i, + &Value32) != LM_STATUS_SUCCESS) { + return; + } + *((LM_UINT32 *) & pDevice->BootCodeVer[i]) = + cpu_to_le32 (Value32); + } + } else { + char c; - if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS) - return; + if (LM_NvramRead (pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS) + return; - i = 0; - c = ((Value32 & 0xff0000) >> 16); + i = 0; + c = ((Value32 & 0xff0000) >> 16); - if (c < 10) { - pDevice->BootCodeVer[i++] = c + '0'; - } - else { - pDevice->BootCodeVer[i++] = (c / 10) + '0'; - pDevice->BootCodeVer[i++] = (c % 10) + '0'; - } - pDevice->BootCodeVer[i++] = '.'; - c = (Value32 & 0xff000000) >> 24; - if (c < 10) { - pDevice->BootCodeVer[i++] = c + '0'; - } - else { - pDevice->BootCodeVer[i++] = (c / 10) + '0'; - pDevice->BootCodeVer[i++] = (c % 10) + '0'; + if (c < 10) { + pDevice->BootCodeVer[i++] = c + '0'; + } else { + pDevice->BootCodeVer[i++] = (c / 10) + '0'; + pDevice->BootCodeVer[i++] = (c % 10) + '0'; + } + pDevice->BootCodeVer[i++] = '.'; + c = (Value32 & 0xff000000) >> 24; + if (c < 10) { + pDevice->BootCodeVer[i++] = c + '0'; + } else { + pDevice->BootCodeVer[i++] = (c / 10) + '0'; + pDevice->BootCodeVer[i++] = (c % 10) + '0'; + } + pDevice->BootCodeVer[i] = 0; } - pDevice->BootCodeVer[i] = 0; - } } -STATIC void -LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice) +STATIC void LM_GetBusSpeed (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 PciState = pDevice->PciState; - LM_UINT32 ClockCtrl; - char *SpeedStr = ""; - - if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) - { - strcpy(pDevice->BusSpeedStr, "32-bit "); - } - else - { - strcpy(pDevice->BusSpeedStr, "64-bit "); - } - if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) - { - strcat(pDevice->BusSpeedStr, "PCI "); - if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) - { - SpeedStr = "66MHz"; - } - else - { - SpeedStr = "33MHz"; - } - } - else - { - strcat(pDevice->BusSpeedStr, "PCIX "); - if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) - { - SpeedStr = "133MHz"; - } - else - { - ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f; - switch (ClockCtrl) - { - case 0: - SpeedStr = "33MHz"; - break; - - case 2: - SpeedStr = "50MHz"; - break; - - case 4: - SpeedStr = "66MHz"; - break; - - case 6: - SpeedStr = "100MHz"; - break; - - case 7: - SpeedStr = "133MHz"; - break; - } + LM_UINT32 PciState = pDevice->PciState; + LM_UINT32 ClockCtrl; + char *SpeedStr = ""; + + if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) { + strcpy (pDevice->BusSpeedStr, "32-bit "); + } else { + strcpy (pDevice->BusSpeedStr, "64-bit "); + } + if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) { + strcat (pDevice->BusSpeedStr, "PCI "); + if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) { + SpeedStr = "66MHz"; + } else { + SpeedStr = "33MHz"; + } + } else { + strcat (pDevice->BusSpeedStr, "PCIX "); + if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) { + SpeedStr = "133MHz"; + } else { + ClockCtrl = REG_RD (pDevice, PciCfg.ClockCtrl) & 0x1f; + switch (ClockCtrl) { + case 0: + SpeedStr = "33MHz"; + break; + + case 2: + SpeedStr = "50MHz"; + break; + + case 4: + SpeedStr = "66MHz"; + break; + + case 6: + SpeedStr = "100MHz"; + break; + + case 7: + SpeedStr = "133MHz"; + break; + } + } } - } - strcat(pDevice->BusSpeedStr, SpeedStr); + strcat (pDevice->BusSpeedStr, SpeedStr); } /******************************************************************************/ @@ -660,977 +598,890 @@ LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice) /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_GetAdapterInfo( -PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice) { - PLM_ADAPTER_INFO pAdapterInfo; - LM_UINT32 Value32; - LM_STATUS Status; - LM_UINT32 j; - LM_UINT32 EeSigFound; - LM_UINT32 EePhyTypeSerdes = 0; - LM_UINT32 EePhyLedMode = 0; - LM_UINT32 EePhyId = 0; - - /* Get Device Id and Vendor Id */ - Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - pDevice->PciVendorId = (LM_UINT16) Value32; - pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16); - - /* If we are not getting the write adapter, exit. */ - if((Value32 != T3_PCI_ID_BCM5700) && - (Value32 != T3_PCI_ID_BCM5701) && - (Value32 != T3_PCI_ID_BCM5702) && - (Value32 != T3_PCI_ID_BCM5702x) && - (Value32 != T3_PCI_ID_BCM5702FE) && - (Value32 != T3_PCI_ID_BCM5703) && - (Value32 != T3_PCI_ID_BCM5703x) && - (Value32 != T3_PCI_ID_BCM5704)) - { - return LM_STATUS_FAILURE; - } + PLM_ADAPTER_INFO pAdapterInfo; + LM_UINT32 Value32; + LM_STATUS Status; + LM_UINT32 j; + LM_UINT32 EeSigFound; + LM_UINT32 EePhyTypeSerdes = 0; + LM_UINT32 EePhyLedMode = 0; + LM_UINT32 EePhyId = 0; + + /* Get Device Id and Vendor Id */ + Status = MM_ReadConfig32 (pDevice, PCI_VENDOR_ID_REG, &Value32); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + pDevice->PciVendorId = (LM_UINT16) Value32; + pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16); + + /* If we are not getting the write adapter, exit. */ + if ((Value32 != T3_PCI_ID_BCM5700) && + (Value32 != T3_PCI_ID_BCM5701) && + (Value32 != T3_PCI_ID_BCM5702) && + (Value32 != T3_PCI_ID_BCM5702x) && + (Value32 != T3_PCI_ID_BCM5702FE) && + (Value32 != T3_PCI_ID_BCM5703) && + (Value32 != T3_PCI_ID_BCM5703x) && (Value32 != T3_PCI_ID_BCM5704)) { + return LM_STATUS_FAILURE; + } - Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - pDevice->PciRevId = (LM_UINT8) Value32; + Status = MM_ReadConfig32 (pDevice, PCI_REV_ID_REG, &Value32); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + pDevice->PciRevId = (LM_UINT8) Value32; - /* Get IRQ. */ - Status = MM_ReadConfig32(pDevice, PCI_INT_LINE_REG, &Value32); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - pDevice->Irq = (LM_UINT8) Value32; + /* Get IRQ. */ + Status = MM_ReadConfig32 (pDevice, PCI_INT_LINE_REG, &Value32); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + pDevice->Irq = (LM_UINT8) Value32; - /* Get interrupt pin. */ - pDevice->IntPin = (LM_UINT8) (Value32 >> 8); + /* Get interrupt pin. */ + pDevice->IntPin = (LM_UINT8) (Value32 >> 8); - /* Get chip revision id. */ - Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32); - pDevice->ChipRevId = Value32 >> 16; + /* Get chip revision id. */ + Status = MM_ReadConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32); + pDevice->ChipRevId = Value32 >> 16; - /* Get subsystem vendor. */ - Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - pDevice->SubsystemVendorId = (LM_UINT16) Value32; + /* Get subsystem vendor. */ + Status = + MM_ReadConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + pDevice->SubsystemVendorId = (LM_UINT16) Value32; - /* Get PCI subsystem id. */ - pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16); + /* Get PCI subsystem id. */ + pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16); - /* Get the cache line size. */ - MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32); - pDevice->CacheLineSize = (LM_UINT8) Value32; - pDevice->SavedCacheLineReg = Value32; + /* Get the cache line size. */ + MM_ReadConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32); + pDevice->CacheLineSize = (LM_UINT8) Value32; + pDevice->SavedCacheLineReg = Value32; - if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 && - pDevice->ChipRevId != T3_CHIP_ID_5703_A2 && - pDevice->ChipRevId != T3_CHIP_ID_5704_A0) - { - pDevice->UndiFix = FALSE; - } + if (pDevice->ChipRevId != T3_CHIP_ID_5703_A1 && + pDevice->ChipRevId != T3_CHIP_ID_5703_A2 && + pDevice->ChipRevId != T3_CHIP_ID_5704_A0) { + pDevice->UndiFix = FALSE; + } #if !PCIX_TARGET_WORKAROUND - pDevice->UndiFix = FALSE; + pDevice->UndiFix = FALSE; #endif - /* Map the memory base to system address space. */ - if (!pDevice->UndiFix) - { - Status = MM_MapMemBase(pDevice); - if(Status != LM_STATUS_SUCCESS) - { - return Status; + /* Map the memory base to system address space. */ + if (!pDevice->UndiFix) { + Status = MM_MapMemBase (pDevice); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + /* Initialize the memory view pointer. */ + pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase; } - /* Initialize the memory view pointer. */ - pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase; - } - #if PCIX_TARGET_WORKAROUND - /* store whether we are in PCI are PCI-X mode */ - pDevice->EnablePciXFix = FALSE; - - MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32); - if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) - { - /* Enable PCI-X workaround only if we are running on 5700 BX. */ - if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) - { - pDevice->EnablePciXFix = TRUE; + /* store whether we are in PCI are PCI-X mode */ + pDevice->EnablePciXFix = FALSE; + + MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32); + if ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) { + /* Enable PCI-X workaround only if we are running on 5700 BX. */ + if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) { + pDevice->EnablePciXFix = TRUE; + } + } + if (pDevice->UndiFix) { + pDevice->EnablePciXFix = TRUE; } - } - if (pDevice->UndiFix) - { - pDevice->EnablePciXFix = TRUE; - } #endif - /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */ - /* management register may be clobbered which may cause the */ - /* BCM5700 to go into D3 state. While in this state, we will */ - /* not have memory mapped register access. As a workaround, we */ - /* need to restore the device to D0 state. */ - MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32); - Value32 |= T3_PM_PME_ASSERTED; - Value32 &= ~T3_PM_POWER_STATE_MASK; - Value32 |= T3_PM_POWER_STATE_D0; - MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32); - - /* read the current PCI command word */ - MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32); - - /* Make sure bus-mastering is enabled. */ - Value32 |= PCI_BUSMASTER_ENABLE; + /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */ + /* management register may be clobbered which may cause the */ + /* BCM5700 to go into D3 state. While in this state, we will */ + /* not have memory mapped register access. As a workaround, we */ + /* need to restore the device to D0 state. */ + MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32); + Value32 |= T3_PM_PME_ASSERTED; + Value32 &= ~T3_PM_POWER_STATE_MASK; + Value32 |= T3_PM_POWER_STATE_D0; + MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32); + + /* read the current PCI command word */ + MM_ReadConfig32 (pDevice, PCI_COMMAND_REG, &Value32); + + /* Make sure bus-mastering is enabled. */ + Value32 |= PCI_BUSMASTER_ENABLE; #if PCIX_TARGET_WORKAROUND - /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR# - are enabled */ - if (pDevice->EnablePciXFix == TRUE) { - Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE | - PCI_PARITY_ERROR_ENABLE); - } - if (pDevice->UndiFix) - { - Value32 &= ~PCI_MEM_SPACE_ENABLE; - } - + /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR# + are enabled */ + if (pDevice->EnablePciXFix == TRUE) { + Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE | + PCI_PARITY_ERROR_ENABLE); + } + if (pDevice->UndiFix) { + Value32 &= ~PCI_MEM_SPACE_ENABLE; + } #endif - if(pDevice->EnableMWI) - { - Value32 |= PCI_MEMORY_WRITE_INVALIDATE; - } - else { - Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE); - } - - /* Error out if mem-mapping is NOT enabled for PCI systems */ - if (!(Value32 | PCI_MEM_SPACE_ENABLE)) - { - return LM_STATUS_FAILURE; - } + if (pDevice->EnableMWI) { + Value32 |= PCI_MEMORY_WRITE_INVALIDATE; + } else { + Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE); + } + + /* Error out if mem-mapping is NOT enabled for PCI systems */ + if (!(Value32 | PCI_MEM_SPACE_ENABLE)) { + return LM_STATUS_FAILURE; + } - /* save the value we are going to write into the PCI command word */ - pDevice->PciCommandStatusWords = Value32; + /* save the value we are going to write into the PCI command word */ + pDevice->PciCommandStatusWords = Value32; - Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } + Status = MM_WriteConfig32 (pDevice, PCI_COMMAND_REG, Value32); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } - /* Set power state to D0. */ - LM_SetPowerState(pDevice, LM_POWER_STATE_D0); + /* Set power state to D0. */ + LM_SetPowerState (pDevice, LM_POWER_STATE_D0); #ifdef BIG_ENDIAN_PCI - pDevice->MiscHostCtrl = - MISC_HOST_CTRL_MASK_PCI_INT | - MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | - MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | - MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; -#else /* No CPU Swap modes for PCI IO */ - - /* Setup the mode registers. */ - pDevice->MiscHostCtrl = - MISC_HOST_CTRL_MASK_PCI_INT | - MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | + pDevice->MiscHostCtrl = + MISC_HOST_CTRL_MASK_PCI_INT | + MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | + MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | + MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; +#else /* No CPU Swap modes for PCI IO */ + + /* Setup the mode registers. */ + pDevice->MiscHostCtrl = + MISC_HOST_CTRL_MASK_PCI_INT | + MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | #ifdef BIG_ENDIAN_HOST - MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP | -#endif /* BIG_ENDIAN_HOST */ - MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | - MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; -#endif /* !BIG_ENDIAN_PCI */ + MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP | +#endif /* BIG_ENDIAN_HOST */ + MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | + MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; +#endif /* !BIG_ENDIAN_PCI */ - /* write to PCI misc host ctr first in order to enable indirect accesses */ - MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl); + /* write to PCI misc host ctr first in order to enable indirect accesses */ + MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, + pDevice->MiscHostCtrl); - REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl); + REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl); #ifdef BIG_ENDIAN_PCI - Value32 = GRC_MODE_WORD_SWAP_DATA| - GRC_MODE_WORD_SWAP_NON_FRAME_DATA; + Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA; #else /* No CPU Swap modes for PCI IO */ #ifdef BIG_ENDIAN_HOST - Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | - GRC_MODE_WORD_SWAP_NON_FRAME_DATA; + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA; #else - Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; #endif -#endif /* !BIG_ENDIAN_PCI */ - - REG_WR(pDevice, Grc.Mode, Value32); - - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1); - } - MM_Wait(40); - - /* Enable indirect memory access */ - REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); - - if (REG_RD(pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) - { - REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK | - T3_PCI_SELECT_ALTERNATE_CLOCK); - REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_SELECT_ALTERNATE_CLOCK); - MM_Wait(40); /* required delay is 27usec */ - } - REG_WR(pDevice, PciCfg.ClockCtrl, 0); - REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0); +#endif /* !BIG_ENDIAN_PCI */ + + REG_WR (pDevice, Grc.Mode, Value32); + + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + REG_WR (pDevice, Grc.LocalCtrl, + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1); + } + MM_Wait (40); + + /* Enable indirect memory access */ + REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); + + if (REG_RD (pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) { + REG_WR (pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK); + REG_WR (pDevice, PciCfg.ClockCtrl, + T3_PCI_SELECT_ALTERNATE_CLOCK); + MM_Wait (40); /* required delay is 27usec */ + } + REG_WR (pDevice, PciCfg.ClockCtrl, 0); + REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0); #if PCIX_TARGET_WORKAROUND - MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32); - if ((pDevice->EnablePciXFix == FALSE) && - ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) - { - if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B2 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B5) - { - __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x300])); - __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301])); - __raw_writel(0xffffffff, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301])); - if (__raw_readl(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]))) - { - pDevice->EnablePciXFix = TRUE; - } + MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32); + if ((pDevice->EnablePciXFix == FALSE) && + ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) { + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B2 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B5) { + __raw_writel (0, + &(pDevice->pMemView->uIntMem. + MemBlock32K[0x300])); + __raw_writel (0, + &(pDevice->pMemView->uIntMem. + MemBlock32K[0x301])); + __raw_writel (0xffffffff, + &(pDevice->pMemView->uIntMem. + MemBlock32K[0x301])); + if (__raw_readl + (&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]))) + { + pDevice->EnablePciXFix = TRUE; + } + } } - } #endif #if 1 - /* - * This code was at the beginning of else block below, but that's - * a bug if node address in shared memory. - */ - MM_Wait(50); - LM_NvramInit(pDevice); + /* + * This code was at the beginning of else block below, but that's + * a bug if node address in shared memory. + */ + MM_Wait (50); + LM_NvramInit (pDevice); #endif - /* Get the node address. First try to get in from the shared memory. */ - /* If the signature is not present, then get it from the NVRAM. */ - Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX); - if((Value32 >> 16) == 0x484b) - { - - pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8); - pDevice->NodeAddress[1] = (LM_UINT8) Value32; - - Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX); - - pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24); - pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16); - pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8); - pDevice->NodeAddress[5] = (LM_UINT8) Value32; - - Status = LM_STATUS_SUCCESS; - } - else - { - Status = LM_NvramRead(pDevice, 0x7c, &Value32); - if(Status == LM_STATUS_SUCCESS) - { - pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16); - pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24); - - Status = LM_NvramRead(pDevice, 0x80, &Value32); - - pDevice->NodeAddress[2] = (LM_UINT8) Value32; - pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8); - pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16); - pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24); + /* Get the node address. First try to get in from the shared memory. */ + /* If the signature is not present, then get it from the NVRAM. */ + Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_HIGH_MAILBOX); + if ((Value32 >> 16) == 0x484b) { + + pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[1] = (LM_UINT8) Value32; + + Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_LOW_MAILBOX); + + pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24); + pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[5] = (LM_UINT8) Value32; + + Status = LM_STATUS_SUCCESS; + } else { + Status = LM_NvramRead (pDevice, 0x7c, &Value32); + if (Status == LM_STATUS_SUCCESS) { + pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24); + + Status = LM_NvramRead (pDevice, 0x80, &Value32); + + pDevice->NodeAddress[2] = (LM_UINT8) Value32; + pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24); + } } - } - /* Assign a default address. */ - if(Status != LM_STATUS_SUCCESS) - { + /* Assign a default address. */ + if (Status != LM_STATUS_SUCCESS) { #ifndef EMBEDDED - printk(KERN_ERR "Cannot get MAC addr from NVRAM. Using default.\n"); -#endif - pDevice->NodeAddress[0] = 0x00; pDevice->NodeAddress[1] = 0x10; - pDevice->NodeAddress[2] = 0x18; pDevice->NodeAddress[3] = 0x68; - pDevice->NodeAddress[4] = 0x61; pDevice->NodeAddress[5] = 0x76; - } - - pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0]; - pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1]; - pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2]; - pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3]; - pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4]; - pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5]; - - /* Initialize the default values. */ - pDevice->NoTxPseudoHdrChksum = FALSE; - pDevice->NoRxPseudoHdrChksum = FALSE; - pDevice->NicSendBd = FALSE; - pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT; - pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT; - pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS; - pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS; - pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES; - pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES; - pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; - pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; - pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; - pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; - pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS; - pDevice->EnableMWI = FALSE; - pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; - pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; - pDevice->DisableAutoNeg = FALSE; - pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO; - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO; - pDevice->LedMode = LED_MODE_AUTO; - pDevice->ResetPhyOnInit = TRUE; - pDevice->DelayPciGrant = TRUE; - pDevice->UseTaggedStatus = FALSE; - pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE; - - pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO; - pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO; - pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO; - - pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO; - pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE; - pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE; - pDevice->EnableTbi = FALSE; -#if INCLUDE_TBI_SUPPORT - pDevice->PollTbiLink = BAD_DEFAULT_VALUE; + printk (KERN_ERR + "Cannot get MAC addr from NVRAM. Using default.\n"); #endif + pDevice->NodeAddress[0] = 0x00; + pDevice->NodeAddress[1] = 0x10; + pDevice->NodeAddress[2] = 0x18; + pDevice->NodeAddress[3] = 0x68; + pDevice->NodeAddress[4] = 0x61; + pDevice->NodeAddress[5] = 0x76; + } + + pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0]; + pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1]; + pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2]; + pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3]; + pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4]; + pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5]; + + /* Initialize the default values. */ + pDevice->NoTxPseudoHdrChksum = FALSE; + pDevice->NoRxPseudoHdrChksum = FALSE; + pDevice->NicSendBd = FALSE; + pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT; + pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT; + pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS; + pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS; + pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES; + pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES; + pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; + pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; + pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; + pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; + pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS; + pDevice->EnableMWI = FALSE; + pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + pDevice->DisableAutoNeg = FALSE; + pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO; + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO; + pDevice->LedMode = LED_MODE_AUTO; + pDevice->ResetPhyOnInit = TRUE; + pDevice->DelayPciGrant = TRUE; + pDevice->UseTaggedStatus = FALSE; + pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE; - switch (T3_ASIC_REV(pDevice->ChipRevId)) - { - case T3_ASIC_REV_5704: - pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; - pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64; - break; - default: - pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; - pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96; - break; - } - - pDevice->LinkStatus = LM_STATUS_LINK_DOWN; - pDevice->QueueRxPackets = TRUE; - - pDevice->EnableWireSpeed = TRUE; + pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO; + pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO; + pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO; -#if T3_JUMBO_RCV_RCB_ENTRY_COUNT - pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - - /* Make this is a known adapter. */ - pAdapterInfo = LM_GetAdapterInfoBySsid(pDevice->SubsystemVendorId, - pDevice->SubsystemId); - - pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK; - if (pDevice->BondId != GRC_MISC_BD_ID_5700 && - pDevice->BondId != GRC_MISC_BD_ID_5701 && - pDevice->BondId != GRC_MISC_BD_ID_5702FE && - pDevice->BondId != GRC_MISC_BD_ID_5703 && - pDevice->BondId != GRC_MISC_BD_ID_5703S && - pDevice->BondId != GRC_MISC_BD_ID_5704 && - pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) - { - return LM_STATUS_UNKNOWN_ADAPTER; - } - - pDevice->SplitModeEnable = SPLIT_MODE_DISABLE; - if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) && - (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) - { - pDevice->SplitModeEnable = SPLIT_MODE_ENABLE; - pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ; - } - - /* Get Eeprom info. */ - Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR); - if (Value32 == T3_NIC_DATA_SIG) - { - EeSigFound = TRUE; - Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR); - - /* Determine PHY type. */ - switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) - { - case T3_NIC_CFG_PHY_TYPE_COPPER: - EePhyTypeSerdes = FALSE; - break; + pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO; + pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE; + pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE; + pDevice->EnableTbi = FALSE; +#if INCLUDE_TBI_SUPPORT + pDevice->PollTbiLink = BAD_DEFAULT_VALUE; +#endif - case T3_NIC_CFG_PHY_TYPE_FIBER: - EePhyTypeSerdes = TRUE; + switch (T3_ASIC_REV (pDevice->ChipRevId)) { + case T3_ASIC_REV_5704: + pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; + pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64; break; - - default: - EePhyTypeSerdes = FALSE; + default: + pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; + pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96; break; } - /* Determine PHY led mode. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - switch(Value32 & T3_NIC_CFG_LED_MODE_MASK) - { - case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED: - EePhyLedMode = LED_MODE_THREE_LINK; - break; + pDevice->LinkStatus = LM_STATUS_LINK_DOWN; + pDevice->QueueRxPackets = TRUE; - case T3_NIC_CFG_LED_MODE_LINK_SPEED: - EePhyLedMode = LED_MODE_LINK10; - break; + pDevice->EnableWireSpeed = TRUE; - default: - EePhyLedMode = LED_MODE_AUTO; - break; - } - } - else - { - switch(Value32 & T3_NIC_CFG_LED_MODE_MASK) - { - case T3_NIC_CFG_LED_MODE_OPEN_DRAIN: - EePhyLedMode = LED_MODE_OPEN_DRAIN; - break; +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Make this is a known adapter. */ + pAdapterInfo = LM_GetAdapterInfoBySsid (pDevice->SubsystemVendorId, + pDevice->SubsystemId); + + pDevice->BondId = REG_RD (pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK; + if (pDevice->BondId != GRC_MISC_BD_ID_5700 && + pDevice->BondId != GRC_MISC_BD_ID_5701 && + pDevice->BondId != GRC_MISC_BD_ID_5702FE && + pDevice->BondId != GRC_MISC_BD_ID_5703 && + pDevice->BondId != GRC_MISC_BD_ID_5703S && + pDevice->BondId != GRC_MISC_BD_ID_5704 && + pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) { + return LM_STATUS_UNKNOWN_ADAPTER; + } + + pDevice->SplitModeEnable = SPLIT_MODE_DISABLE; + if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) && + (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) { + pDevice->SplitModeEnable = SPLIT_MODE_ENABLE; + pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ; + } + + /* Get Eeprom info. */ + Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_SIG_ADDR); + if (Value32 == T3_NIC_DATA_SIG) { + EeSigFound = TRUE; + Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_NIC_CFG_ADDR); + + /* Determine PHY type. */ + switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) { + case T3_NIC_CFG_PHY_TYPE_COPPER: + EePhyTypeSerdes = FALSE; + break; - case T3_NIC_CFG_LED_MODE_OUTPUT: - EePhyLedMode = LED_MODE_OUTPUT; - break; + case T3_NIC_CFG_PHY_TYPE_FIBER: + EePhyTypeSerdes = TRUE; + break; default: - EePhyLedMode = LED_MODE_AUTO; - break; - } - } - if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || - pDevice->ChipRevId == T3_CHIP_ID_5703_A2) - { - /* Enable EEPROM write protection. */ - if(Value32 & T3_NIC_EEPROM_WP) - { - pDevice->EepromWp = TRUE; - } - } + EePhyTypeSerdes = FALSE; + break; + } - /* Get the PHY Id. */ - Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR); - if (Value32) - { - EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) & - PHY_ID1_OUI_MASK) << 10; + /* Determine PHY led mode. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) { + case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED: + EePhyLedMode = LED_MODE_THREE_LINK; + break; + + case T3_NIC_CFG_LED_MODE_LINK_SPEED: + EePhyLedMode = LED_MODE_LINK10; + break; + + default: + EePhyLedMode = LED_MODE_AUTO; + break; + } + } else { + switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) { + case T3_NIC_CFG_LED_MODE_OPEN_DRAIN: + EePhyLedMode = LED_MODE_OPEN_DRAIN; + break; + + case T3_NIC_CFG_LED_MODE_OUTPUT: + EePhyLedMode = LED_MODE_OUTPUT; + break; + + default: + EePhyLedMode = LED_MODE_AUTO; + break; + } + } + if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || + pDevice->ChipRevId == T3_CHIP_ID_5703_A2) { + /* Enable EEPROM write protection. */ + if (Value32 & T3_NIC_EEPROM_WP) { + pDevice->EepromWp = TRUE; + } + } - Value32 = Value32 & T3_NIC_PHY_ID2_MASK; + /* Get the PHY Id. */ + Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_PHY_ID_ADDR); + if (Value32) { + EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) & + PHY_ID1_OUI_MASK) << 10; - EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | - (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); - } - else - { - EePhyId = 0; + Value32 = Value32 & T3_NIC_PHY_ID2_MASK; + + EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | + (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & + PHY_ID2_REV_MASK); + } else { + EePhyId = 0; + } + } else { + EeSigFound = FALSE; } - } - else - { - EeSigFound = FALSE; - } - /* Set the PHY address. */ - pDevice->PhyAddr = PHY_DEVICE_ID; + /* Set the PHY address. */ + pDevice->PhyAddr = PHY_DEVICE_ID; - /* Disable auto polling. */ - pDevice->MiMode = 0xc0000; - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - MM_Wait(40); + /* Disable auto polling. */ + pDevice->MiMode = 0xc0000; + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait (40); - /* Get the PHY id. */ - LM_ReadPhy(pDevice, PHY_ID1_REG, &Value32); - pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10; + /* Get the PHY id. */ + LM_ReadPhy (pDevice, PHY_ID1_REG, &Value32); + pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10; - LM_ReadPhy(pDevice, PHY_ID2_REG, &Value32); - pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | - (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); + LM_ReadPhy (pDevice, PHY_ID2_REG, &Value32); + pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | + (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); - /* Set the EnableTbi flag to false if we have a copper PHY. */ - switch(pDevice->PhyId & PHY_ID_MASK) - { + /* Set the EnableTbi flag to false if we have a copper PHY. */ + switch (pDevice->PhyId & PHY_ID_MASK) { case PHY_BCM5400_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + pDevice->EnableTbi = FALSE; + break; case PHY_BCM5401_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + pDevice->EnableTbi = FALSE; + break; case PHY_BCM5411_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + pDevice->EnableTbi = FALSE; + break; case PHY_BCM5701_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + pDevice->EnableTbi = FALSE; + break; case PHY_BCM5703_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + pDevice->EnableTbi = FALSE; + break; case PHY_BCM5704_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + pDevice->EnableTbi = FALSE; + break; case PHY_BCM8002_PHY_ID: - pDevice->EnableTbi = TRUE; - break; + pDevice->EnableTbi = TRUE; + break; default: - if (pAdapterInfo) - { - pDevice->PhyId = pAdapterInfo->PhyId; - pDevice->EnableTbi = pAdapterInfo->Serdes; - } - else if (EeSigFound) - { - pDevice->PhyId = EePhyId; - pDevice->EnableTbi = EePhyTypeSerdes; - } - break; - } - - /* Bail out if we don't know the copper PHY id. */ - if(UNKNOWN_PHY_ID(pDevice->PhyId) && !pDevice->EnableTbi) - { - return LM_STATUS_FAILURE; - } + if (pAdapterInfo) { + pDevice->PhyId = pAdapterInfo->PhyId; + pDevice->EnableTbi = pAdapterInfo->Serdes; + } else if (EeSigFound) { + pDevice->PhyId = EePhyId; + pDevice->EnableTbi = EePhyTypeSerdes; + } + break; + } - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) - { - if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) - { - pDevice->SavedCacheLineReg &= 0xffff00ff; - pDevice->SavedCacheLineReg |= 0x4000; - } - } - /* Change driver parameters. */ - Status = MM_GetConfig(pDevice); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } + /* Bail out if we don't know the copper PHY id. */ + if (UNKNOWN_PHY_ID (pDevice->PhyId) && !pDevice->EnableTbi) { + return LM_STATUS_FAILURE; + } + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) { + if ((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) { + pDevice->SavedCacheLineReg &= 0xffff00ff; + pDevice->SavedCacheLineReg |= 0x4000; + } + } + /* Change driver parameters. */ + Status = MM_GetConfig (pDevice); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } #if INCLUDE_5701_AX_FIX - if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0) - { - pDevice->ResetPhyOnInit = TRUE; - } + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) { + pDevice->ResetPhyOnInit = TRUE; + } #endif - /* Save the current phy link status. */ - if(!pDevice->EnableTbi) - { - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - - /* If we don't have link reset the PHY. */ - if(!(Value32 & PHY_STATUS_LINK_PASS) || pDevice->ResetPhyOnInit) - { + /* Save the current phy link status. */ + if (!pDevice->EnableTbi) { + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); + /* If we don't have link reset the PHY. */ + if (!(Value32 & PHY_STATUS_LINK_PASS) + || pDevice->ResetPhyOnInit) { - for(j = 0; j < 100; j++) - { - MM_Wait(10); + LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if(Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) - { - MM_Wait(40); - break; - } - } + for (j = 0; j < 100; j++) { + MM_Wait (10); + LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32); + if (Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) { + MM_Wait (40); + break; + } + } #if INCLUDE_5701_AX_FIX - /* 5701_AX_BX bug: only advertises 10mb speed. */ - if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0) - { - - Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | - PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | - PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; - - Value32 = BCM540X_AN_AD_1000BASET_HALF | - BCM540X_AN_AD_1000BASET_FULL | BCM540X_CONFIG_AS_MASTER | - BCM540X_ENABLE_CONFIG_AS_MASTER; - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); - pDevice->advertising1000 = Value32; - - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | - PHY_CTRL_RESTART_AUTO_NEG); - } + /* 5701_AX_BX bug: only advertises 10mb speed. */ + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) { + + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | + PHY_AN_AD_10BASET_HALF | + PHY_AN_AD_10BASET_FULL | + PHY_AN_AD_100BASETX_FULL | + PHY_AN_AD_100BASETX_HALF; + Value32 |= GetPhyAdFlowCntrlSettings (pDevice); + LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + + Value32 = BCM540X_AN_AD_1000BASET_HALF | + BCM540X_AN_AD_1000BASET_FULL | + BCM540X_CONFIG_AS_MASTER | + BCM540X_ENABLE_CONFIG_AS_MASTER; + LM_WritePhy (pDevice, + BCM540X_1000BASET_CTRL_REG, + Value32); + pDevice->advertising1000 = Value32; + + LM_WritePhy (pDevice, PHY_CTRL_REG, + PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); + } #endif - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) - { - LM_WritePhy(pDevice, 0x18, 0x0c00); - LM_WritePhy(pDevice, 0x17, 0x201f); - LM_WritePhy(pDevice, 0x15, 0x2aaa); - } - if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0) - { - LM_WritePhy(pDevice, 0x1c, 0x8d68); - LM_WritePhy(pDevice, 0x1c, 0x8d68); - } - /* Enable Ethernet@WireSpeed. */ - if(pDevice->EnableWireSpeed) - { - LM_WritePhy(pDevice, 0x18, 0x7007); - LM_ReadPhy(pDevice, 0x18, &Value32); - LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4); - } - } - } - - /* Turn off tap power management. */ - if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) - { - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); - - MM_Wait(40); - } + if (T3_ASIC_REV (pDevice->ChipRevId) == + T3_ASIC_REV_5703) { + LM_WritePhy (pDevice, 0x18, 0x0c00); + LM_WritePhy (pDevice, 0x17, 0x201f); + LM_WritePhy (pDevice, 0x15, 0x2aaa); + } + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { + LM_WritePhy (pDevice, 0x1c, 0x8d68); + LM_WritePhy (pDevice, 0x1c, 0x8d68); + } + /* Enable Ethernet@WireSpeed. */ + if (pDevice->EnableWireSpeed) { + LM_WritePhy (pDevice, 0x18, 0x7007); + LM_ReadPhy (pDevice, 0x18, &Value32); + LM_WritePhy (pDevice, 0x18, + Value32 | BIT_15 | BIT_4); + } + } + } -#if INCLUDE_TBI_SUPPORT - pDevice->IgnoreTbiLinkChange = FALSE; - - if(pDevice->EnableTbi) - { - pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE; - pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; - if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) || - pDevice->DisableAutoNeg) - { - pDevice->PollTbiLink = FALSE; - } - } - else - { - pDevice->PollTbiLink = FALSE; - } -#endif /* INCLUDE_TBI_SUPPORT */ - - /* UseTaggedStatus is only valid for 5701 and later. */ - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->UseTaggedStatus = FALSE; + /* Turn off tap power management. */ + if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) { + LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20); - pDevice->CoalesceMode = 0; - } - else - { - pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT | - HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT; - } - - /* Set the status block size. */ - if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX && - T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) - { - pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE; - } - - /* Check the DURING_INT coalescing ticks parameters. */ - if(pDevice->UseTaggedStatus) - { - if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->RxCoalescingTicksDuringInt = - DEFAULT_RX_COALESCING_TICKS_DURING_INT; + MM_Wait (40); } - - if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->TxCoalescingTicksDuringInt = - DEFAULT_TX_COALESCING_TICKS_DURING_INT; +#if INCLUDE_TBI_SUPPORT + pDevice->IgnoreTbiLinkChange = FALSE; + + if (pDevice->EnableTbi) { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE; + pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; + if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) || + pDevice->DisableAutoNeg) { + pDevice->PollTbiLink = FALSE; + } + } else { + pDevice->PollTbiLink = FALSE; } +#endif /* INCLUDE_TBI_SUPPORT */ - if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->RxMaxCoalescedFramesDuringInt = - DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT; - } + /* UseTaggedStatus is only valid for 5701 and later. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + pDevice->UseTaggedStatus = FALSE; - if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->TxMaxCoalescedFramesDuringInt = - DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT; - } - } - else - { - if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->RxCoalescingTicksDuringInt = 0; + pDevice->CoalesceMode = 0; + } else { + pDevice->CoalesceMode = + HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT | + HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT; } - if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->TxCoalescingTicksDuringInt = 0; + /* Set the status block size. */ + if (T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_AX && + T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) { + pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE; } - if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->RxMaxCoalescedFramesDuringInt = 0; - } + /* Check the DURING_INT coalescing ticks parameters. */ + if (pDevice->UseTaggedStatus) { + if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) { + pDevice->RxCoalescingTicksDuringInt = + DEFAULT_RX_COALESCING_TICKS_DURING_INT; + } - if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->TxMaxCoalescedFramesDuringInt = 0; - } - } + if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) { + pDevice->TxCoalescingTicksDuringInt = + DEFAULT_TX_COALESCING_TICKS_DURING_INT; + } -#if T3_JUMBO_RCV_RCB_ENTRY_COUNT - if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */)) - { - pDevice->RxJumboDescCnt = 0; - if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) - { - pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; - } - } - else - { - pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ + - COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK; + if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) { + pDevice->RxMaxCoalescedFramesDuringInt = + DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT; + } - if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) - { - pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE; - pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */; - } - pDevice->TxMtu = pDevice->RxMtu; + if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) { + pDevice->TxMaxCoalescedFramesDuringInt = + DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT; + } + } else { + if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) { + pDevice->RxCoalescingTicksDuringInt = 0; + } - } -#else - pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) { + pDevice->TxCoalescingTicksDuringInt = 0; + } + + if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) { + pDevice->RxMaxCoalescedFramesDuringInt = 0; + } + + if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) { + pDevice->TxMaxCoalescedFramesDuringInt = 0; + } + } - pDevice->RxPacketDescCnt = #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - pDevice->RxJumboDescCnt + -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - pDevice->RxStdDescCnt; + if (pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */ )) { + pDevice->RxJumboDescCnt = 0; + if (pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) { + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + } + } else { + pDevice->RxJumboBufferSize = + (pDevice->RxMtu + 8 /* CRC + VLAN */ + + COMMON_CACHE_LINE_SIZE - 1) & ~COMMON_CACHE_LINE_MASK; + + if (pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) { + pDevice->RxJumboBufferSize = + DEFAULT_JUMBO_RCV_BUFFER_SIZE; + pDevice->RxMtu = + pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */ ; + } + pDevice->TxMtu = pDevice->RxMtu; - if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) - { - pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; - } + } +#else + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) - { - pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE; - } + pDevice->RxPacketDescCnt = +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + pDevice->RxJumboDescCnt + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + pDevice->RxStdDescCnt; - /* Configure the proper ways to get link change interrupt. */ - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) - { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + if (pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) { + pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; } - else - { - pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; + + if (pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) { + pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE; } - } - else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) - { - /* Auto-polling does not work on 5700_AX and 5700_BX. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + + /* Configure the proper ways to get link change interrupt. */ + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) { + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + } else { + pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; + } + } else if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { + /* Auto-polling does not work on 5700_AX and 5700_BX. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + } } - } - /* Determine the method to get link change status. */ - if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) - { - /* The link status bit in the status block does not work on 5700_AX */ - /* and 5700_BX chips. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + /* Determine the method to get link change status. */ + if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) { + /* The link status bit in the status block does not work on 5700_AX */ + /* and 5700_BX chips. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + pDevice->LinkChngMode = + T3_LINK_CHNG_MODE_USE_STATUS_REG; + } else { + pDevice->LinkChngMode = + T3_LINK_CHNG_MODE_USE_STATUS_BLOCK; + } } - else - { - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK; + + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; } - } - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; - } + /* Configure PHY led mode. */ + if (pDevice->LedMode == LED_MODE_AUTO) { + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + if (pDevice->SubsystemVendorId == T3_SVID_DELL) { + pDevice->LedMode = LED_MODE_LINK10; + } else { + pDevice->LedMode = LED_MODE_THREE_LINK; - /* Configure PHY led mode. */ - if(pDevice->LedMode == LED_MODE_AUTO) - { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - if(pDevice->SubsystemVendorId == T3_SVID_DELL) - { - pDevice->LedMode = LED_MODE_LINK10; - } - else - { - pDevice->LedMode = LED_MODE_THREE_LINK; - - if(EeSigFound && EePhyLedMode != LED_MODE_AUTO) - { - pDevice->LedMode = EePhyLedMode; - } - } - - /* bug? 5701 in LINK10 mode does not seem to work when */ - /* PhyIntMode is LINK_READY. */ - if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && + if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) { + pDevice->LedMode = EePhyLedMode; + } + } + + /* bug? 5701 in LINK10 mode does not seem to work when */ + /* PhyIntMode is LINK_READY. */ + if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 + && #if INCLUDE_TBI_SUPPORT - pDevice->EnableTbi == FALSE && + pDevice->EnableTbi == FALSE && #endif - pDevice->LedMode == LED_MODE_LINK10) - { - pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; - } + pDevice->LedMode == LED_MODE_LINK10) { + pDevice->PhyIntMode = + T3_PHY_INT_MODE_MI_INTERRUPT; + pDevice->LinkChngMode = + T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + + if (pDevice->EnableTbi) { + pDevice->LedMode = LED_MODE_THREE_LINK; + } + } else { + if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) { + pDevice->LedMode = EePhyLedMode; + } else { + pDevice->LedMode = LED_MODE_OPEN_DRAIN; + } + } + } - if(pDevice->EnableTbi) - { - pDevice->LedMode = LED_MODE_THREE_LINK; - } + /* Enable OneDmaAtOnce. */ + if (pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) { + pDevice->OneDmaAtOnce = FALSE; } - else - { - if(EeSigFound && EePhyLedMode != LED_MODE_AUTO) - { - pDevice->LedMode = EePhyLedMode; - } - else - { - pDevice->LedMode = LED_MODE_OPEN_DRAIN; - } - } - } - - /* Enable OneDmaAtOnce. */ - if(pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) - { - pDevice->OneDmaAtOnce = FALSE; - } - - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B2) - { - pDevice->WolSpeed = WOL_SPEED_10MB; - } - else - { - pDevice->WolSpeed = WOL_SPEED_100MB; - } - - /* Offloadings. */ - pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; - - /* Turn off task offloading on Ax. */ - if(pDevice->ChipRevId == T3_CHIP_ID_5700_B0) - { - pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | - LM_TASK_OFFLOAD_TX_UDP_CHECKSUM); - } - pDevice->PciState = REG_RD(pDevice, PciCfg.PciState); - LM_ReadVPD(pDevice); - LM_ReadBootCodeVersion(pDevice); - LM_GetBusSpeed(pDevice); - - return LM_STATUS_SUCCESS; -} /* LM_GetAdapterInfo */ - -STATIC PLM_ADAPTER_INFO -LM_GetAdapterInfoBySsid( - LM_UINT16 Svid, - LM_UINT16 Ssid) + + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B2) { + pDevice->WolSpeed = WOL_SPEED_10MB; + } else { + pDevice->WolSpeed = WOL_SPEED_100MB; + } + + /* Offloadings. */ + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + + /* Turn off task offloading on Ax. */ + if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) { + pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM); + } + pDevice->PciState = REG_RD (pDevice, PciCfg.PciState); + LM_ReadVPD (pDevice); + LM_ReadBootCodeVersion (pDevice); + LM_GetBusSpeed (pDevice); + + return LM_STATUS_SUCCESS; +} /* LM_GetAdapterInfo */ + +STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid, LM_UINT16 Ssid) { - static LM_ADAPTER_INFO AdapterArr[] = - { - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 }, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5701_PHY_ID, 0}, - - { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 }, - { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 }, - { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 }, - - { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 }, - { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 }, - { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 }, - { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 }, - - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 }, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 }, - - }; - LM_UINT32 j; - - for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++) - { - if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) - { - return &AdapterArr[j]; + static LM_ADAPTER_INFO AdapterArr[] = { + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, + PHY_BCM5401_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, + PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, + PHY_BCM8002_PHY_ID, 1}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, + PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, + PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, + PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, + PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, + PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, + PHY_BCM5701_PHY_ID, 0}, + + {T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0}, + {T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1}, + {T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0}, + + {T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0}, + {T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0}, + {T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0}, + {T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0}, + + {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, + 0}, + {T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1}, + {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0}, + {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, + 0}, + + }; + LM_UINT32 j; + + for (j = 0; j < sizeof (AdapterArr) / sizeof (LM_ADAPTER_INFO); j++) { + if (AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) { + return &AdapterArr[j]; + } } - } - return NULL; + return NULL; } - /******************************************************************************/ /* Description: */ /* This routine sets up receive/transmit buffer descriptions queues. */ @@ -1638,237 +1489,226 @@ LM_GetAdapterInfoBySsid( /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_InitializeAdapter( -PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice) { - LM_PHYSICAL_ADDRESS MemPhy; - PLM_UINT8 pMemVirt; - PLM_PACKET pPacket; - LM_STATUS Status; - LM_UINT32 Size; - LM_UINT32 j; - - /* Set power state to D0. */ - LM_SetPowerState(pDevice, LM_POWER_STATE_D0); - - /* Intialize the queues. */ - QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container, - MAX_RX_PACKET_DESC_COUNT); - QQ_InitQueue(&pDevice->RxPacketFreeQ.Container, - MAX_RX_PACKET_DESC_COUNT); - - QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT); - QQ_InitQueue(&pDevice->TxPacketActiveQ.Container,MAX_TX_PACKET_DESC_COUNT); - QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT); - - /* Allocate shared memory for: status block, the buffers for receive */ - /* rings -- standard, mini, jumbo, and return rings. */ - Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) + - T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + + LM_PHYSICAL_ADDRESS MemPhy; + PLM_UINT8 pMemVirt; + PLM_PACKET pPacket; + LM_STATUS Status; + LM_UINT32 Size; + LM_UINT32 j; + + /* Set power state to D0. */ + LM_SetPowerState (pDevice, LM_POWER_STATE_D0); + + /* Intialize the queues. */ + QQ_InitQueue (&pDevice->RxPacketReceivedQ.Container, + MAX_RX_PACKET_DESC_COUNT); + QQ_InitQueue (&pDevice->RxPacketFreeQ.Container, + MAX_RX_PACKET_DESC_COUNT); + + QQ_InitQueue (&pDevice->TxPacketFreeQ.Container, + MAX_TX_PACKET_DESC_COUNT); + QQ_InitQueue (&pDevice->TxPacketActiveQ.Container, + MAX_TX_PACKET_DESC_COUNT); + QQ_InitQueue (&pDevice->TxPacketXmittedQ.Container, + MAX_TX_PACKET_DESC_COUNT); + + /* Allocate shared memory for: status block, the buffers for receive */ + /* rings -- standard, mini, jumbo, and return rings. */ + Size = T3_STATUS_BLOCK_SIZE + sizeof (T3_STATS_BLOCK) + + T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) + #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); - - /* Memory for host based Send BD. */ - if(pDevice->NicSendBd == FALSE) - { - Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; - } - - /* Allocate the memory block. */ - Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - - /* Program DMA Read/Write */ - if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) - { - pDevice->DmaReadWriteCtrl = 0x763f000f; - } - else - { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) - { - pDevice->DmaReadWriteCtrl = 0x761f0000; + T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD); + + /* Memory for host based Send BD. */ + if (pDevice->NicSendBd == FALSE) { + Size += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; + } + + /* Allocate the memory block. */ + Status = + MM_AllocateSharedMemory (pDevice, Size, (PLM_VOID) & pMemVirt, + &MemPhy, FALSE); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + + /* Program DMA Read/Write */ + if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) { + pDevice->DmaReadWriteCtrl = 0x763f000f; + } else { + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5704) { + pDevice->DmaReadWriteCtrl = 0x761f0000; + } else { + pDevice->DmaReadWriteCtrl = 0x761b000f; + } + if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || + pDevice->ChipRevId == T3_CHIP_ID_5703_A2) { + pDevice->OneDmaAtOnce = TRUE; + } } - else - { - pDevice->DmaReadWriteCtrl = 0x761b000f; + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) { + pDevice->DmaReadWriteCtrl &= 0xfffffff0; + } + + if (pDevice->OneDmaAtOnce) { + pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE; + } + REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); + + if (LM_DmaTest (pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) { + return LM_STATUS_FAILURE; } - if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || - pDevice->ChipRevId == T3_CHIP_ID_5703_A2) - { - pDevice->OneDmaAtOnce = TRUE; - } - } - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) - { - pDevice->DmaReadWriteCtrl &= 0xfffffff0; - } - - if(pDevice->OneDmaAtOnce) - { - pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE; - } - REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); - - if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) - { - return LM_STATUS_FAILURE; - } - /* Status block. */ - pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt; - pDevice->StatusBlkPhy = MemPhy; - pMemVirt += T3_STATUS_BLOCK_SIZE; - LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE); + /* Status block. */ + pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt; + pDevice->StatusBlkPhy = MemPhy; + pMemVirt += T3_STATUS_BLOCK_SIZE; + LM_INC_PHYSICAL_ADDRESS (&MemPhy, T3_STATUS_BLOCK_SIZE); - /* Statistics block. */ - pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt; - pDevice->StatsBlkPhy = MemPhy; - pMemVirt += sizeof(T3_STATS_BLOCK); - LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK)); + /* Statistics block. */ + pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt; + pDevice->StatsBlkPhy = MemPhy; + pMemVirt += sizeof (T3_STATS_BLOCK); + LM_INC_PHYSICAL_ADDRESS (&MemPhy, sizeof (T3_STATS_BLOCK)); - /* Receive standard BD buffer. */ - pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt; - pDevice->RxStdBdPhy = MemPhy; + /* Receive standard BD buffer. */ + pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RxStdBdPhy = MemPhy; - pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); - LM_INC_PHYSICAL_ADDRESS(&MemPhy, - T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); + pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS (&MemPhy, + T3_STD_RCV_RCB_ENTRY_COUNT * + sizeof (T3_RCV_BD)); #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - /* Receive jumbo BD buffer. */ - pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt; - pDevice->RxJumboBdPhy = MemPhy; - - pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); - LM_INC_PHYSICAL_ADDRESS(&MemPhy, - T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - - /* Receive return BD buffer. */ - pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt; - pDevice->RcvRetBdPhy = MemPhy; - - pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); - LM_INC_PHYSICAL_ADDRESS(&MemPhy, - T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); - - /* Set up Send BD. */ - if(pDevice->NicSendBd == FALSE) - { - pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt; - pDevice->SendBdPhy = MemPhy; - - pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; - LM_INC_PHYSICAL_ADDRESS(&MemPhy, - sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT); - } - else - { - pDevice->pSendBdVirt = (PT3_SND_BD) - pDevice->pMemView->uIntMem.First32k.BufferDesc; - pDevice->SendBdPhy.High = 0; - pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR; - } - - /* Allocate memory for packet descriptors. */ - Size = (pDevice->RxPacketDescCnt + - pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE; - Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - pDevice->pPacketDescBase = (PLM_VOID) pPacket; - - /* Create transmit packet descriptors from the memory block and add them */ - /* to the TxPacketFreeQ for each send ring. */ - for(j = 0; j < pDevice->TxPacketDescCnt; j++) - { - /* Ring index. */ - pPacket->Flags = 0; - - /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */ - QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket); - - /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ - /* is the total size of the packet descriptor including the */ - /* os-specific extensions in the UM_PACKET structure. */ - pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); - } /* for(j.. */ - - /* Create receive packet descriptors from the memory block and add them */ - /* to the RxPacketFreeQ. Create the Standard packet descriptors. */ - for(j = 0; j < pDevice->RxStdDescCnt; j++) - { - /* Receive producer ring. */ - pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING; - - /* Receive buffer size. */ - pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE; - - /* Add the descriptor to RxPacketFreeQ. */ - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - - /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ - /* is the total size of the packet descriptor including the */ - /* os-specific extensions in the UM_PACKET structure. */ - pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); - } /* for */ + /* Receive jumbo BD buffer. */ + pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RxJumboBdPhy = MemPhy; + + pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS (&MemPhy, + T3_JUMBO_RCV_RCB_ENTRY_COUNT * + sizeof (T3_RCV_BD)); +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Receive return BD buffer. */ + pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RcvRetBdPhy = MemPhy; + + pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS (&MemPhy, + T3_RCV_RETURN_RCB_ENTRY_COUNT * + sizeof (T3_RCV_BD)); + + /* Set up Send BD. */ + if (pDevice->NicSendBd == FALSE) { + pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt; + pDevice->SendBdPhy = MemPhy; + + pMemVirt += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; + LM_INC_PHYSICAL_ADDRESS (&MemPhy, + sizeof (T3_SND_BD) * + T3_SEND_RCB_ENTRY_COUNT); + } else { + pDevice->pSendBdVirt = (PT3_SND_BD) + pDevice->pMemView->uIntMem.First32k.BufferDesc; + pDevice->SendBdPhy.High = 0; + pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR; + } + + /* Allocate memory for packet descriptors. */ + Size = (pDevice->RxPacketDescCnt + + pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE; + Status = MM_AllocateMemory (pDevice, Size, (PLM_VOID *) & pPacket); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + pDevice->pPacketDescBase = (PLM_VOID) pPacket; + + /* Create transmit packet descriptors from the memory block and add them */ + /* to the TxPacketFreeQ for each send ring. */ + for (j = 0; j < pDevice->TxPacketDescCnt; j++) { + /* Ring index. */ + pPacket->Flags = 0; + + /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */ + QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket); + + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = + (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for(j.. */ + + /* Create receive packet descriptors from the memory block and add them */ + /* to the RxPacketFreeQ. Create the Standard packet descriptors. */ + for (j = 0; j < pDevice->RxStdDescCnt; j++) { + /* Receive producer ring. */ + pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING; + + /* Receive buffer size. */ + pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE; + + /* Add the descriptor to RxPacketFreeQ. */ + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); + + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = + (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for */ #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - /* Create the Jumbo packet descriptors. */ - for(j = 0; j < pDevice->RxJumboDescCnt; j++) - { - /* Receive producer ring. */ - pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING; - - /* Receive buffer size. */ - pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize; - - /* Add the descriptor to RxPacketFreeQ. */ - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - - /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ - /* is the total size of the packet descriptor including the */ - /* os-specific extensions in the UM_PACKET structure. */ - pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); - } /* for */ -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - - /* Initialize the rest of the packet descriptors. */ - Status = MM_InitializeUmPackets(pDevice); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } /* if */ + /* Create the Jumbo packet descriptors. */ + for (j = 0; j < pDevice->RxJumboDescCnt; j++) { + /* Receive producer ring. */ + pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING; - /* Default receive mask. */ - pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST | - LM_ACCEPT_UNICAST; + /* Receive buffer size. */ + pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize; - /* Make sure we are in the first 32k memory window or NicSendBd. */ - REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0); + /* Add the descriptor to RxPacketFreeQ. */ + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); - /* Initialize the hardware. */ - Status = LM_ResetAdapter(pDevice); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = + (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for */ +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Initialize the rest of the packet descriptors. */ + Status = MM_InitializeUmPackets (pDevice); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } - /* We are done with initialization. */ - pDevice->InitDone = TRUE; + /* if */ + /* Default receive mask. */ + pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST | + LM_ACCEPT_UNICAST; - return LM_STATUS_SUCCESS; -} /* LM_InitializeAdapter */ + /* Make sure we are in the first 32k memory window or NicSendBd. */ + REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0); + /* Initialize the hardware. */ + Status = LM_ResetAdapter (pDevice); + if (Status != LM_STATUS_SUCCESS) { + return Status; + } + + /* We are done with initialization. */ + pDevice->InitDone = TRUE; + + return LM_STATUS_SUCCESS; +} /* LM_InitializeAdapter */ /******************************************************************************/ /* Description: */ @@ -1878,414 +1718,408 @@ PLM_DEVICE_BLOCK pDevice) /* LM_STATUS_SUCCESS */ /******************************************************************************/ LM_STATUS -LM_CntrlBlock( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 mask,LM_UINT32 cntrl) +LM_CntrlBlock (PLM_DEVICE_BLOCK pDevice, LM_UINT32 mask, LM_UINT32 cntrl) { - LM_UINT32 j,i,data; - LM_UINT32 MaxWaitCnt; - - MaxWaitCnt = 2; - j = 0; - - for(i = 0 ; i < 32; i++) - { - if(!(mask & (1 << i))) - continue; - - switch (1 << i) - { - case T3_BLOCK_DMA_RD: - data = REG_RD(pDevice, DmaRead.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~DMA_READ_MODE_ENABLE; - REG_WR(pDevice, DmaRead.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, DmaRead.Mode, data | DMA_READ_MODE_ENABLE); - break; - - case T3_BLOCK_DMA_COMP: - data = REG_RD(pDevice,DmaComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~DMA_COMP_MODE_ENABLE; - REG_WR(pDevice, DmaComp.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, DmaComp.Mode, data | DMA_COMP_MODE_ENABLE); - break; + LM_UINT32 j, i, data; + LM_UINT32 MaxWaitCnt; + + MaxWaitCnt = 2; + j = 0; + + for (i = 0; i < 32; i++) { + if (!(mask & (1 << i))) + continue; + + switch (1 << i) { + case T3_BLOCK_DMA_RD: + data = REG_RD (pDevice, DmaRead.Mode); + if (cntrl == LM_DISABLE) { + data &= ~DMA_READ_MODE_ENABLE; + REG_WR (pDevice, DmaRead.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, DmaRead.Mode) & + DMA_READ_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, DmaRead.Mode, + data | DMA_READ_MODE_ENABLE); + break; - case T3_BLOCK_RX_BD_INITIATOR: - data = REG_RD(pDevice, RcvBdIn.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_BD_IN_MODE_ENABLE; - REG_WR(pDevice, RcvBdIn.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvBdIn.Mode,data | RCV_BD_IN_MODE_ENABLE); - break; + case T3_BLOCK_DMA_COMP: + data = REG_RD (pDevice, DmaComp.Mode); + if (cntrl == LM_DISABLE) { + data &= ~DMA_COMP_MODE_ENABLE; + REG_WR (pDevice, DmaComp.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, DmaComp.Mode) & + DMA_COMP_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, DmaComp.Mode, + data | DMA_COMP_MODE_ENABLE); + break; - case T3_BLOCK_RX_BD_COMP: - data = REG_RD(pDevice, RcvBdComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_BD_COMP_MODE_ENABLE; - REG_WR(pDevice, RcvBdComp.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvBdComp.Mode,data | RCV_BD_COMP_MODE_ENABLE); - break; + case T3_BLOCK_RX_BD_INITIATOR: + data = REG_RD (pDevice, RcvBdIn.Mode); + if (cntrl == LM_DISABLE) { + data &= ~RCV_BD_IN_MODE_ENABLE; + REG_WR (pDevice, RcvBdIn.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, RcvBdIn.Mode) & + RCV_BD_IN_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, RcvBdIn.Mode, + data | RCV_BD_IN_MODE_ENABLE); + break; - case T3_BLOCK_DMA_WR: - data = REG_RD(pDevice, DmaWrite.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~DMA_WRITE_MODE_ENABLE; - REG_WR(pDevice, DmaWrite.Mode,data); + case T3_BLOCK_RX_BD_COMP: + data = REG_RD (pDevice, RcvBdComp.Mode); + if (cntrl == LM_DISABLE) { + data &= ~RCV_BD_COMP_MODE_ENABLE; + REG_WR (pDevice, RcvBdComp.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, RcvBdComp.Mode) & + RCV_BD_COMP_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, RcvBdComp.Mode, + data | RCV_BD_COMP_MODE_ENABLE); + break; - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, DmaWrite.Mode,data | DMA_WRITE_MODE_ENABLE); - break; + case T3_BLOCK_DMA_WR: + data = REG_RD (pDevice, DmaWrite.Mode); + if (cntrl == LM_DISABLE) { + data &= ~DMA_WRITE_MODE_ENABLE; + REG_WR (pDevice, DmaWrite.Mode, data); + + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, DmaWrite.Mode) & + DMA_WRITE_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, DmaWrite.Mode, + data | DMA_WRITE_MODE_ENABLE); + break; - case T3_BLOCK_MSI_HANDLER: - data = REG_RD(pDevice, Msi.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~MSI_MODE_ENABLE; - REG_WR(pDevice, Msi.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, Msi.Mode) & MSI_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, Msi.Mode, data |MSI_MODE_ENABLE); - break; + case T3_BLOCK_MSI_HANDLER: + data = REG_RD (pDevice, Msi.Mode); + if (cntrl == LM_DISABLE) { + data &= ~MSI_MODE_ENABLE; + REG_WR (pDevice, Msi.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, Msi.Mode) & + MSI_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, Msi.Mode, + data | MSI_MODE_ENABLE); + break; - case T3_BLOCK_RX_LIST_PLMT: - data = REG_RD(pDevice, RcvListPlmt.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_LIST_PLMT_MODE_ENABLE; - REG_WR(pDevice, RcvListPlmt.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvListPlmt.Mode,data | RCV_LIST_PLMT_MODE_ENABLE); - break; + case T3_BLOCK_RX_LIST_PLMT: + data = REG_RD (pDevice, RcvListPlmt.Mode); + if (cntrl == LM_DISABLE) { + data &= ~RCV_LIST_PLMT_MODE_ENABLE; + REG_WR (pDevice, RcvListPlmt.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, RcvListPlmt.Mode) + & RCV_LIST_PLMT_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, RcvListPlmt.Mode, + data | RCV_LIST_PLMT_MODE_ENABLE); + break; - case T3_BLOCK_RX_LIST_SELECTOR: - data = REG_RD(pDevice, RcvListSel.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_LIST_SEL_MODE_ENABLE; - REG_WR(pDevice, RcvListSel.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvListSel.Mode,data |RCV_LIST_SEL_MODE_ENABLE); - break; + case T3_BLOCK_RX_LIST_SELECTOR: + data = REG_RD (pDevice, RcvListSel.Mode); + if (cntrl == LM_DISABLE) { + data &= ~RCV_LIST_SEL_MODE_ENABLE; + REG_WR (pDevice, RcvListSel.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, RcvListSel.Mode) & + RCV_LIST_SEL_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, RcvListSel.Mode, + data | RCV_LIST_SEL_MODE_ENABLE); + break; - case T3_BLOCK_RX_DATA_INITIATOR: - data = REG_RD(pDevice, RcvDataBdIn.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_DATA_BD_IN_MODE_ENABLE; - REG_WR(pDevice, RcvDataBdIn.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvDataBdIn.Mode, data | RCV_DATA_BD_IN_MODE_ENABLE); - break; + case T3_BLOCK_RX_DATA_INITIATOR: + data = REG_RD (pDevice, RcvDataBdIn.Mode); + if (cntrl == LM_DISABLE) { + data &= ~RCV_DATA_BD_IN_MODE_ENABLE; + REG_WR (pDevice, RcvDataBdIn.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, RcvDataBdIn.Mode) + & RCV_DATA_BD_IN_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, RcvDataBdIn.Mode, + data | RCV_DATA_BD_IN_MODE_ENABLE); + break; - case T3_BLOCK_RX_DATA_COMP: - data = REG_RD(pDevice, RcvDataComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_DATA_COMP_MODE_ENABLE; - REG_WR(pDevice, RcvDataComp.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvDataComp.Mode,data | RCV_DATA_COMP_MODE_ENABLE); - break; + case T3_BLOCK_RX_DATA_COMP: + data = REG_RD (pDevice, RcvDataComp.Mode); + if (cntrl == LM_DISABLE) { + data &= ~RCV_DATA_COMP_MODE_ENABLE; + REG_WR (pDevice, RcvDataComp.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, RcvDataBdIn.Mode) + & RCV_DATA_COMP_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, RcvDataComp.Mode, + data | RCV_DATA_COMP_MODE_ENABLE); + break; - case T3_BLOCK_HOST_COALESING: - data = REG_RD(pDevice, HostCoalesce.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~HOST_COALESCE_ENABLE; - REG_WR(pDevice, HostCoalesce.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, HostCoalesce.Mode, data | HOST_COALESCE_ENABLE); - break; + case T3_BLOCK_HOST_COALESING: + data = REG_RD (pDevice, HostCoalesce.Mode); + if (cntrl == LM_DISABLE) { + data &= ~HOST_COALESCE_ENABLE; + REG_WR (pDevice, HostCoalesce.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, SndBdIn.Mode) & + HOST_COALESCE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, HostCoalesce.Mode, + data | HOST_COALESCE_ENABLE); + break; - case T3_BLOCK_MAC_RX_ENGINE: - if(cntrl == LM_DISABLE) - { - pDevice->RxMode &= ~RX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE)) - { - break; + case T3_BLOCK_MAC_RX_ENGINE: + if (cntrl == LM_DISABLE) { + pDevice->RxMode &= ~RX_MODE_ENABLE; + REG_WR (pDevice, MacCtrl.RxMode, + pDevice->RxMode); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, MacCtrl.RxMode) & + RX_MODE_ENABLE)) { + break; + } + MM_Wait (10); + } + } else { + pDevice->RxMode |= RX_MODE_ENABLE; + REG_WR (pDevice, MacCtrl.RxMode, + pDevice->RxMode); } - MM_Wait(10); - } - } - else - { - pDevice->RxMode |= RX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); - } - break; + break; - case T3_BLOCK_MBUF_CLUSTER_FREE: - data = REG_RD(pDevice, MbufClusterFree.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE; - REG_WR(pDevice, MbufClusterFree.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, MbufClusterFree.Mode, data | MBUF_CLUSTER_FREE_MODE_ENABLE); - break; + case T3_BLOCK_MBUF_CLUSTER_FREE: + data = REG_RD (pDevice, MbufClusterFree.Mode); + if (cntrl == LM_DISABLE) { + data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE; + REG_WR (pDevice, MbufClusterFree.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD + (pDevice, + MbufClusterFree. + Mode) & + MBUF_CLUSTER_FREE_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, MbufClusterFree.Mode, + data | MBUF_CLUSTER_FREE_MODE_ENABLE); + break; - case T3_BLOCK_SEND_BD_INITIATOR: - data = REG_RD(pDevice, SndBdIn.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~SND_BD_IN_MODE_ENABLE; - REG_WR(pDevice, SndBdIn.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndBdIn.Mode, data | SND_BD_IN_MODE_ENABLE); - break; + case T3_BLOCK_SEND_BD_INITIATOR: + data = REG_RD (pDevice, SndBdIn.Mode); + if (cntrl == LM_DISABLE) { + data &= ~SND_BD_IN_MODE_ENABLE; + REG_WR (pDevice, SndBdIn.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, SndBdIn.Mode) & + SND_BD_IN_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, SndBdIn.Mode, + data | SND_BD_IN_MODE_ENABLE); + break; - case T3_BLOCK_SEND_BD_COMP: - data = REG_RD(pDevice, SndBdComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~SND_BD_COMP_MODE_ENABLE; - REG_WR(pDevice, SndBdComp.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndBdComp.Mode, data | SND_BD_COMP_MODE_ENABLE); - break; + case T3_BLOCK_SEND_BD_COMP: + data = REG_RD (pDevice, SndBdComp.Mode); + if (cntrl == LM_DISABLE) { + data &= ~SND_BD_COMP_MODE_ENABLE; + REG_WR (pDevice, SndBdComp.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, SndBdComp.Mode) & + SND_BD_COMP_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, SndBdComp.Mode, + data | SND_BD_COMP_MODE_ENABLE); + break; - case T3_BLOCK_SEND_BD_SELECTOR: - data = REG_RD(pDevice, SndBdSel.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~SND_BD_SEL_MODE_ENABLE; - REG_WR(pDevice, SndBdSel.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndBdSel.Mode, data | SND_BD_SEL_MODE_ENABLE); - break; + case T3_BLOCK_SEND_BD_SELECTOR: + data = REG_RD (pDevice, SndBdSel.Mode); + if (cntrl == LM_DISABLE) { + data &= ~SND_BD_SEL_MODE_ENABLE; + REG_WR (pDevice, SndBdSel.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, SndBdSel.Mode) & + SND_BD_SEL_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, SndBdSel.Mode, + data | SND_BD_SEL_MODE_ENABLE); + break; - case T3_BLOCK_SEND_DATA_INITIATOR: - data = REG_RD(pDevice, SndDataIn.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~T3_SND_DATA_IN_MODE_ENABLE; - REG_WR(pDevice, SndDataIn.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndDataIn.Mode,data | T3_SND_DATA_IN_MODE_ENABLE); - break; + case T3_BLOCK_SEND_DATA_INITIATOR: + data = REG_RD (pDevice, SndDataIn.Mode); + if (cntrl == LM_DISABLE) { + data &= ~T3_SND_DATA_IN_MODE_ENABLE; + REG_WR (pDevice, SndDataIn.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, SndDataIn.Mode) & + T3_SND_DATA_IN_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, SndDataIn.Mode, + data | T3_SND_DATA_IN_MODE_ENABLE); + break; - case T3_BLOCK_SEND_DATA_COMP: - data = REG_RD(pDevice, SndDataComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~SND_DATA_COMP_MODE_ENABLE; - REG_WR(pDevice, SndDataComp.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndDataComp.Mode,data | SND_DATA_COMP_MODE_ENABLE); - break; + case T3_BLOCK_SEND_DATA_COMP: + data = REG_RD (pDevice, SndDataComp.Mode); + if (cntrl == LM_DISABLE) { + data &= ~SND_DATA_COMP_MODE_ENABLE; + REG_WR (pDevice, SndDataComp.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, SndDataComp.Mode) + & SND_DATA_COMP_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, SndDataComp.Mode, + data | SND_DATA_COMP_MODE_ENABLE); + break; - case T3_BLOCK_MAC_TX_ENGINE: - if(cntrl == LM_DISABLE) - { - pDevice->TxMode &= ~TX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - { - pDevice->TxMode |= TX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); - } - break; + case T3_BLOCK_MAC_TX_ENGINE: + if (cntrl == LM_DISABLE) { + pDevice->TxMode &= ~TX_MODE_ENABLE; + REG_WR (pDevice, MacCtrl.TxMode, + pDevice->TxMode); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, MacCtrl.TxMode) & + TX_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else { + pDevice->TxMode |= TX_MODE_ENABLE; + REG_WR (pDevice, MacCtrl.TxMode, + pDevice->TxMode); + } + break; - case T3_BLOCK_MEM_ARBITOR: - data = REG_RD(pDevice, MemArbiter.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~T3_MEM_ARBITER_MODE_ENABLE; - REG_WR(pDevice, MemArbiter.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, MemArbiter.Mode,data|T3_MEM_ARBITER_MODE_ENABLE); - break; + case T3_BLOCK_MEM_ARBITOR: + data = REG_RD (pDevice, MemArbiter.Mode); + if (cntrl == LM_DISABLE) { + data &= ~T3_MEM_ARBITER_MODE_ENABLE; + REG_WR (pDevice, MemArbiter.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, MemArbiter.Mode) & + T3_MEM_ARBITER_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, MemArbiter.Mode, + data | T3_MEM_ARBITER_MODE_ENABLE); + break; - case T3_BLOCK_MBUF_MANAGER: - data = REG_RD(pDevice, BufMgr.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~BUFMGR_MODE_ENABLE; - REG_WR(pDevice, BufMgr.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, BufMgr.Mode,data | BUFMGR_MODE_ENABLE); - break; + case T3_BLOCK_MBUF_MANAGER: + data = REG_RD (pDevice, BufMgr.Mode); + if (cntrl == LM_DISABLE) { + data &= ~BUFMGR_MODE_ENABLE; + REG_WR (pDevice, BufMgr.Mode, data); + for (j = 0; j < MaxWaitCnt; j++) { + if (! + (REG_RD (pDevice, BufMgr.Mode) & + BUFMGR_MODE_ENABLE)) + break; + MM_Wait (10); + } + } else + REG_WR (pDevice, BufMgr.Mode, + data | BUFMGR_MODE_ENABLE); + break; - case T3_BLOCK_MAC_GLOBAL: - if(cntrl == LM_DISABLE) - { - pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE | - MAC_MODE_ENABLE_RDE | - MAC_MODE_ENABLE_FHDE); - } - else - { - pDevice->MacMode |= (MAC_MODE_ENABLE_TDE | - MAC_MODE_ENABLE_RDE | - MAC_MODE_ENABLE_FHDE); - } - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); - break; + case T3_BLOCK_MAC_GLOBAL: + if (cntrl == LM_DISABLE) { + pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | + MAC_MODE_ENABLE_FHDE); + } else { + pDevice->MacMode |= (MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | + MAC_MODE_ENABLE_FHDE); + } + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode); + break; - default: - return LM_STATUS_FAILURE; - } /* switch */ + default: + return LM_STATUS_FAILURE; + } /* switch */ - if(j >= MaxWaitCnt) - { - return LM_STATUS_FAILURE; + if (j >= MaxWaitCnt) { + return LM_STATUS_FAILURE; + } } - } - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } /******************************************************************************/ @@ -2295,682 +2129,631 @@ LM_UINT32 mask,LM_UINT32 cntrl) /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_ResetAdapter( -PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32; - LM_UINT16 Value16; - LM_UINT32 j, k; + LM_UINT32 Value32; + LM_UINT16 Value16; + LM_UINT32 j, k; - /* Disable interrupt. */ - LM_DisableInterrupt(pDevice); + /* Disable interrupt. */ + LM_DisableInterrupt (pDevice); - /* May get a spurious interrupt */ - pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED; + /* May get a spurious interrupt */ + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED; - /* Disable transmit and receive DMA engines. Abort all pending requests. */ - if(pDevice->InitDone) - { - LM_Abort(pDevice); - } + /* Disable transmit and receive DMA engines. Abort all pending requests. */ + if (pDevice->InitDone) { + LM_Abort (pDevice); + } - pDevice->ShuttingDown = FALSE; + pDevice->ShuttingDown = FALSE; - LM_ResetChip(pDevice); + LM_ResetChip (pDevice); - /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */ - /* in other chip revisions. */ - if(pDevice->DelayPciGrant) - { - Value32 = REG_RD(pDevice, PciCfg.ClockCtrl); - REG_WR(pDevice, PciCfg.ClockCtrl, Value32 | BIT_31); - } + /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */ + /* in other chip revisions. */ + if (pDevice->DelayPciGrant) { + Value32 = REG_RD (pDevice, PciCfg.ClockCtrl); + REG_WR (pDevice, PciCfg.ClockCtrl, Value32 | BIT_31); + } - if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0) - { - if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) - { - Value32 = REG_RD(pDevice, PciCfg.PciState); - Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; - REG_WR(pDevice, PciCfg.PciState, Value32); - } - } - - /* Enable TaggedStatus mode. */ - if(pDevice->UseTaggedStatus) - { - pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE; - } - - /* Restore PCI configuration registers. */ - MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, - pDevice->SavedCacheLineReg); - MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, - (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); - - /* Clear the statistics block. */ - for(j = 0x0300; j < 0x0b00; j++) - { - MEM_WR_OFFSET(pDevice, j, 0); - } - - /* Initialize the statistis Block */ - pDevice->pStatusBlkVirt->Status = 0; - pDevice->pStatusBlkVirt->RcvStdConIdx = 0; - pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; - pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; - - for(j = 0; j < 16; j++) - { - pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0; - pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0; - } - - for(k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT ;k++) - { - pDevice->pRxStdBdVirt[k].HostAddr.High = 0; - pDevice->pRxStdBdVirt[k].HostAddr.Low = 0; - } + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) { + Value32 = REG_RD (pDevice, PciCfg.PciState); + Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + REG_WR (pDevice, PciCfg.PciState, Value32); + } + } + + /* Enable TaggedStatus mode. */ + if (pDevice->UseTaggedStatus) { + pDevice->MiscHostCtrl |= + MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE; + } + + /* Restore PCI configuration registers. */ + MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG, + pDevice->SavedCacheLineReg); + MM_WriteConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, + (pDevice->SubsystemId << 16) | pDevice-> + SubsystemVendorId); + + /* Clear the statistics block. */ + for (j = 0x0300; j < 0x0b00; j++) { + MEM_WR_OFFSET (pDevice, j, 0); + } + + /* Initialize the statistis Block */ + pDevice->pStatusBlkVirt->Status = 0; + pDevice->pStatusBlkVirt->RcvStdConIdx = 0; + pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; + pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; + + for (j = 0; j < 16; j++) { + pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0; + pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0; + } + + for (k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT; k++) { + pDevice->pRxStdBdVirt[k].HostAddr.High = 0; + pDevice->pRxStdBdVirt[k].HostAddr.Low = 0; + } #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - /* Receive jumbo BD buffer. */ - for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) - { - pDevice->pRxJumboBdVirt[k].HostAddr.High = 0; - pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0; - } + /* Receive jumbo BD buffer. */ + for (k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) { + pDevice->pRxJumboBdVirt[k].HostAddr.High = 0; + pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0; + } #endif - REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); + REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); - /* GRC mode control register. */ -#ifdef BIG_ENDIAN_PCI /* Jimmy, this ifdef block deleted in new code! */ - Value32 = - GRC_MODE_WORD_SWAP_DATA | - GRC_MODE_WORD_SWAP_NON_FRAME_DATA | - GRC_MODE_INT_ON_MAC_ATTN | - GRC_MODE_HOST_STACK_UP; + /* GRC mode control register. */ +#ifdef BIG_ENDIAN_PCI /* Jimmy, this ifdef block deleted in new code! */ + Value32 = + GRC_MODE_WORD_SWAP_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP; #else - /* No CPU Swap modes for PCI IO */ - Value32 = + /* No CPU Swap modes for PCI IO */ + Value32 = #ifdef BIG_ENDIAN_HOST - GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | - GRC_MODE_WORD_SWAP_NON_FRAME_DATA | - GRC_MODE_BYTE_SWAP_DATA | - GRC_MODE_WORD_SWAP_DATA | + GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA | #else - GRC_MODE_WORD_SWAP_NON_FRAME_DATA | - GRC_MODE_BYTE_SWAP_DATA | - GRC_MODE_WORD_SWAP_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA | #endif - GRC_MODE_INT_ON_MAC_ATTN | - GRC_MODE_HOST_STACK_UP; -#endif /* !BIG_ENDIAN_PCI */ - - /* Configure send BD mode. */ - if(pDevice->NicSendBd == FALSE) - { - Value32 |= GRC_MODE_HOST_SEND_BDS; - } - else - { - Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS; - } - - /* Configure pseudo checksum mode. */ - if(pDevice->NoTxPseudoHdrChksum) - { - Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM; - } - - if(pDevice->NoRxPseudoHdrChksum) - { - Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM; - } - - REG_WR(pDevice, Grc.Mode, Value32); - - /* Setup the timer prescalar register. */ - REG_WR(pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */ - - /* Set up the MBUF pool base address and size. */ - REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase); - REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize); - - /* Set up the DMA descriptor pool base address and size. */ - REG_WR(pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR); - REG_WR(pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE); - - /* Configure MBUF and Threshold watermarks */ - /* Configure the DMA read MBUF low water mark. */ - if(pDevice->DmaMbufLowMark) - { - REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, - pDevice->DmaMbufLowMark); - } - else - { - if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) - { - REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, - T3_DEF_DMA_MBUF_LOW_WMARK); + GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP; +#endif /* !BIG_ENDIAN_PCI */ + + /* Configure send BD mode. */ + if (pDevice->NicSendBd == FALSE) { + Value32 |= GRC_MODE_HOST_SEND_BDS; + } else { + Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS; } - else - { - REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, - T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO); - } - } - - /* Configure the MAC Rx MBUF low water mark. */ - if(pDevice->RxMacMbufLowMark) - { - REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, - pDevice->RxMacMbufLowMark); - } - else - { - if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) - { - REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, - T3_DEF_RX_MAC_MBUF_LOW_WMARK); + + /* Configure pseudo checksum mode. */ + if (pDevice->NoTxPseudoHdrChksum) { + Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM; } - else - { - REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, - T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO); - } - } - - /* Configure the MBUF high water mark. */ - if(pDevice->MbufHighMark) - { - REG_WR(pDevice, BufMgr.MbufHighWaterMark, pDevice->MbufHighMark); - } - else - { - if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) - { - REG_WR(pDevice, BufMgr.MbufHighWaterMark, - T3_DEF_MBUF_HIGH_WMARK); + + if (pDevice->NoRxPseudoHdrChksum) { + Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM; } - else - { - REG_WR(pDevice, BufMgr.MbufHighWaterMark, - T3_DEF_MBUF_HIGH_WMARK_JUMBO); + + REG_WR (pDevice, Grc.Mode, Value32); + + /* Setup the timer prescalar register. */ + REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */ + + /* Set up the MBUF pool base address and size. */ + REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase); + REG_WR (pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize); + + /* Set up the DMA descriptor pool base address and size. */ + REG_WR (pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR); + REG_WR (pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE); + + /* Configure MBUF and Threshold watermarks */ + /* Configure the DMA read MBUF low water mark. */ + if (pDevice->DmaMbufLowMark) { + REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark, + pDevice->DmaMbufLowMark); + } else { + if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) { + REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK); + } else { + REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO); + } } - } - REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK); - REG_WR(pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK); + /* Configure the MAC Rx MBUF low water mark. */ + if (pDevice->RxMacMbufLowMark) { + REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark, + pDevice->RxMacMbufLowMark); + } else { + if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) { + REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK); + } else { + REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO); + } + } - /* Enable buffer manager. */ - REG_WR(pDevice, BufMgr.Mode, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); + /* Configure the MBUF high water mark. */ + if (pDevice->MbufHighMark) { + REG_WR (pDevice, BufMgr.MbufHighWaterMark, + pDevice->MbufHighMark); + } else { + if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) { + REG_WR (pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK); + } else { + REG_WR (pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK_JUMBO); + } + } - for(j = 0 ;j < 2000; j++) - { - if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE) - break; - MM_Wait(10); - } + REG_WR (pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK); + REG_WR (pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK); - if(j >= 2000) - { - return LM_STATUS_FAILURE; - } - - /* Enable the FTQs. */ - REG_WR(pDevice, Ftq.Reset, 0xffffffff); - REG_WR(pDevice, Ftq.Reset, 0); - - /* Wait until FTQ is ready */ - for(j = 0; j < 2000; j++) - { - if(REG_RD(pDevice, Ftq.Reset) == 0) - break; - MM_Wait(10); - } - - if(j >= 2000) - { - return LM_STATUS_FAILURE; - } - - /* Initialize the Standard Receive RCB. */ - REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High, - pDevice->RxStdBdPhy.High); - REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low, - pDevice->RxStdBdPhy.Low); - REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags, - MAX_STD_RCV_BUFFER_SIZE << 16); - - /* Initialize the Jumbo Receive RCB. */ - REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, - T3_RCB_FLAG_RING_DISABLED); -#if T3_JUMBO_RCV_RCB_ENTRY_COUNT - REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High, - pDevice->RxJumboBdPhy.High); - REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low, - pDevice->RxJumboBdPhy.Low); + /* Enable buffer manager. */ + REG_WR (pDevice, BufMgr.Mode, + BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); + + for (j = 0; j < 2000; j++) { + if (REG_RD (pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE) + break; + MM_Wait (10); + } + + if (j >= 2000) { + return LM_STATUS_FAILURE; + } - REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0); + /* Enable the FTQs. */ + REG_WR (pDevice, Ftq.Reset, 0xffffffff); + REG_WR (pDevice, Ftq.Reset, 0); -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + /* Wait until FTQ is ready */ + for (j = 0; j < 2000; j++) { + if (REG_RD (pDevice, Ftq.Reset) == 0) + break; + MM_Wait (10); + } - /* Initialize the Mini Receive RCB. */ - REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags, - T3_RCB_FLAG_RING_DISABLED); + if (j >= 2000) { + return LM_STATUS_FAILURE; + } - { - REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr, - (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR); - REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr, - (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR); - } + /* Initialize the Standard Receive RCB. */ + REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High, + pDevice->RxStdBdPhy.High); + REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low, + pDevice->RxStdBdPhy.Low); + REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags, + MAX_STD_RCV_BUFFER_SIZE << 16); - /* Receive BD Ring replenish threshold. */ - REG_WR(pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt/8); + /* Initialize the Jumbo Receive RCB. */ + REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - REG_WR(pDevice, RcvBdIn.JumboRcvThreshold, pDevice->RxJumboDescCnt/8); -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High, + pDevice->RxJumboBdPhy.High); + REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low, + pDevice->RxJumboBdPhy.Low); - /* Disable all the unused rings. */ - for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) { - MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); - } /* for */ + REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0); - /* Initialize the indices. */ - pDevice->SendProdIdx = 0; - pDevice->SendConIdx = 0; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, 0); - MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, 0); + /* Initialize the Mini Receive RCB. */ + REG_WR (pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); - /* Set up host or NIC based send RCB. */ - if(pDevice->NicSendBd == FALSE) - { - MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, - pDevice->SendBdPhy.High); - MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, - pDevice->SendBdPhy.Low); + { + REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr, + (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR); + REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr, + (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR); + } + + /* Receive BD Ring replenish threshold. */ + REG_WR (pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt / 8); +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + REG_WR (pDevice, RcvBdIn.JumboRcvThreshold, + pDevice->RxJumboDescCnt / 8); +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Disable all the unused rings. */ + for (j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) { + MEM_WR (pDevice, SendRcb[j].u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); + } /* for */ + + /* Initialize the indices. */ + pDevice->SendProdIdx = 0; + pDevice->SendConIdx = 0; + + MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, 0); + MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, 0); + + /* Set up host or NIC based send RCB. */ + if (pDevice->NicSendBd == FALSE) { + MEM_WR (pDevice, SendRcb[0].HostRingAddr.High, + pDevice->SendBdPhy.High); + MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low, + pDevice->SendBdPhy.Low); + + /* Set up the NIC ring address in the RCB. */ + MEM_WR (pDevice, SendRcb[0].NicRingAddr, + T3_NIC_SND_BUFFER_DESC_ADDR); + + /* Setup the RCB. */ + MEM_WR (pDevice, SendRcb[0].u.MaxLen_Flags, + T3_SEND_RCB_ENTRY_COUNT << 16); + + for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) { + pDevice->pSendBdVirt[k].HostAddr.High = 0; + pDevice->pSendBdVirt[k].HostAddr.Low = 0; + } + } else { + MEM_WR (pDevice, SendRcb[0].HostRingAddr.High, 0); + MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low, 0); + MEM_WR (pDevice, SendRcb[0].NicRingAddr, + pDevice->SendBdPhy.Low); + + for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) { + __raw_writel (0, + &(pDevice->pSendBdVirt[k].HostAddr.High)); + __raw_writel (0, + &(pDevice->pSendBdVirt[k].HostAddr.Low)); + __raw_writel (0, + &(pDevice->pSendBdVirt[k].u1.Len_Flags)); + pDevice->ShadowSendBd[k].HostAddr.High = 0; + pDevice->ShadowSendBd[k].u1.Len_Flags = 0; + } + } + atomic_set (&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT - 1); + + /* Configure the receive return rings. */ + for (j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) { + MEM_WR (pDevice, RcvRetRcb[j].u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); + } + + pDevice->RcvRetConIdx = 0; + + MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.High, + pDevice->RcvRetBdPhy.High); + MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.Low, + pDevice->RcvRetBdPhy.Low); /* Set up the NIC ring address in the RCB. */ - MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR); + /* Not very clear from the spec. I am guessing that for Receive */ + /* Return Ring, NicRingAddr is not used. */ + MEM_WR (pDevice, RcvRetRcb[0].NicRingAddr, 0); /* Setup the RCB. */ - MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags, - T3_SEND_RCB_ENTRY_COUNT << 16); + MEM_WR (pDevice, RcvRetRcb[0].u.MaxLen_Flags, + T3_RCV_RETURN_RCB_ENTRY_COUNT << 16); - for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) - { - pDevice->pSendBdVirt[k].HostAddr.High = 0; - pDevice->pSendBdVirt[k].HostAddr.Low = 0; - } - } - else - { - MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0); - MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0); - MEM_WR(pDevice, SendRcb[0].NicRingAddr, - pDevice->SendBdPhy.Low); - - for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) - { - __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.High)); - __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.Low)); - __raw_writel(0, &(pDevice->pSendBdVirt[k].u1.Len_Flags)); - pDevice->ShadowSendBd[k].HostAddr.High = 0; - pDevice->ShadowSendBd[k].u1.Len_Flags = 0; - } - } - atomic_set(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1); - - /* Configure the receive return rings. */ - for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) - { - MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); - } - - pDevice->RcvRetConIdx = 0; - - MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High, - pDevice->RcvRetBdPhy.High); - MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low, - pDevice->RcvRetBdPhy.Low); - - /* Set up the NIC ring address in the RCB. */ - /* Not very clear from the spec. I am guessing that for Receive */ - /* Return Ring, NicRingAddr is not used. */ - MEM_WR(pDevice, RcvRetRcb[0].NicRingAddr, 0); - - /* Setup the RCB. */ - MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags, - T3_RCV_RETURN_RCB_ENTRY_COUNT << 16); - - /* Reinitialize RX ring producer index */ - MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0); - MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, 0); - MB_REG_WR(pDevice, Mailbox.RcvMiniProdIdx.Low, 0); + /* Reinitialize RX ring producer index */ + MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low, 0); + MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low, 0); + MB_REG_WR (pDevice, Mailbox.RcvMiniProdIdx.Low, 0); #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - pDevice->RxJumboProdIdx = 0; - pDevice->RxJumboQueuedCnt = 0; + pDevice->RxJumboProdIdx = 0; + pDevice->RxJumboQueuedCnt = 0; #endif - /* Reinitialize our copy of the indices. */ - pDevice->RxStdProdIdx = 0; - pDevice->RxStdQueuedCnt = 0; + /* Reinitialize our copy of the indices. */ + pDevice->RxStdProdIdx = 0; + pDevice->RxStdQueuedCnt = 0; #if T3_JUMBO_RCV_ENTRY_COUNT - pDevice->RxJumboProdIdx = 0; -#endif /* T3_JUMBO_RCV_ENTRY_COUNT */ - - /* Configure the MAC address. */ - LM_SetMacAddress(pDevice, pDevice->NodeAddress); - - /* Initialize the transmit random backoff seed. */ - Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] + - pDevice->NodeAddress[2] + pDevice->NodeAddress[3] + - pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) & - MAC_TX_BACKOFF_SEED_MASK; - REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32); - - /* Receive MTU. Frames larger than the MTU is marked as oversized. */ - REG_WR(pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */ - - /* Configure Time slot/IPG per 802.3 */ - REG_WR(pDevice, MacCtrl.TxLengths, 0x2620); - - /* - * Configure Receive Rules so that packets don't match - * Programmble rule will be queued to Return Ring 1 - */ - REG_WR(pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS); - - /* - * Configure to have 16 Classes of Services (COS) and one - * queue per class. Bad frames are queued to RRR#1. - * And frames don't match rules are also queued to COS#1. - */ - REG_WR(pDevice, RcvListPlmt.Config, 0x181); - - /* Enable Receive Placement Statistics */ - REG_WR(pDevice, RcvListPlmt.StatsEnableMask,0xffffff); - REG_WR(pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE); - - /* Enable Send Data Initator Statistics */ - REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff); - REG_WR(pDevice, SndDataIn.StatsCtrl, - T3_SND_DATA_IN_STATS_CTRL_ENABLE | \ - T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE); - - /* Disable the host coalescing state machine before configuring it's */ - /* parameters. */ - REG_WR(pDevice, HostCoalesce.Mode, 0); - for(j = 0; j < 2000; j++) - { - Value32 = REG_RD(pDevice, HostCoalesce.Mode); - if(!(Value32 & HOST_COALESCE_ENABLE)) - { - break; - } - MM_Wait(10); - } - - /* Host coalescing configurations. */ - REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks); - REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks); - REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames, - pDevice->RxMaxCoalescedFrames); - REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames, - pDevice->TxMaxCoalescedFrames); - REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt, - pDevice->RxCoalescingTicksDuringInt); - REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt, - pDevice->TxCoalescingTicksDuringInt); - REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt, - pDevice->RxMaxCoalescedFramesDuringInt); - REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt, - pDevice->TxMaxCoalescedFramesDuringInt); - - /* Initialize the address of the status block. The NIC will DMA */ - /* the status block to this memory which resides on the host. */ - REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High, - pDevice->StatusBlkPhy.High); - REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low, - pDevice->StatusBlkPhy.Low); - - /* Initialize the address of the statistics block. The NIC will DMA */ - /* the statistics to this block of memory. */ - REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High, - pDevice->StatsBlkPhy.High); - REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low, - pDevice->StatsBlkPhy.Low); - - REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks, - pDevice->StatsCoalescingTicks); - - REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300); - REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00); - - /* Enable Host Coalesing state machine */ - REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE | - pDevice->CoalesceMode); - - /* Enable the Receive BD Completion state machine. */ - REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE | - RCV_BD_COMP_MODE_ATTN_ENABLE); - - /* Enable the Receive List Placement state machine. */ - REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE); - - /* Enable the Receive List Selector state machine. */ - REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE | - RCV_LIST_SEL_MODE_ATTN_ENABLE); - - /* Enable transmit DMA, clear statistics. */ - pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS | - MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE | - MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE; - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | - MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS); - - /* GRC miscellaneous local control register. */ - pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN | - GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM; - - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1; - } - - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); - MM_Wait(40); - - /* Reset RX counters. */ - for(j = 0; j < sizeof(LM_RX_COUNTERS); j++) - { - ((PLM_UINT8) &pDevice->RxCounters)[j] = 0; - } - - /* Reset TX counters. */ - for(j = 0; j < sizeof(LM_TX_COUNTERS); j++) - { - ((PLM_UINT8) &pDevice->TxCounters)[j] = 0; - } - - MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0); - - /* Enable the DMA Completion state machine. */ - REG_WR(pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE); - - /* Enable the DMA Write state machine. */ - Value32 = DMA_WRITE_MODE_ENABLE | - DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE | - DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE | - DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE | - DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE | - DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE | - DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE | - DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE | - DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE; - REG_WR(pDevice, DmaWrite.Mode, Value32); - - if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) - { - if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) - { - Value16 = REG_RD(pDevice, PciCfg.PciXCommand); - Value16 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK); - Value16 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) & - PCIX_CMD_MAX_BURST_MASK); - if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) - { - Value16 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL) - & PCIX_CMD_MAX_SPLIT_MASK; - } - REG_WR(pDevice, PciCfg.PciXCommand, Value16); - } - } - - /* Enable the Read DMA state machine. */ - Value32 = DMA_READ_MODE_ENABLE | - DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE | - DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE | - DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE | - DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE | - DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE | - DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE | - DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE | - DMA_READ_MODE_LONG_READ_ATTN_ENABLE; - - if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) - { - Value32 |= DMA_READ_MODE_SPLIT_ENABLE; - } - REG_WR(pDevice, DmaRead.Mode, Value32); - - /* Enable the Receive Data Completion state machine. */ - REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE | - RCV_DATA_COMP_MODE_ATTN_ENABLE); - - /* Enable the Mbuf Cluster Free state machine. */ - REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE); - - /* Enable the Send Data Completion state machine. */ - REG_WR(pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE); - - /* Enable the Send BD Completion state machine. */ - REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE | - SND_BD_COMP_MODE_ATTN_ENABLE); - - /* Enable the Receive BD Initiator state machine. */ - REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE | - RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE); - - /* Enable the Receive Data and Receive BD Initiator state machine. */ - REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE | - RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE); - - /* Enable the Send Data Initiator state machine. */ - REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE); - - /* Enable the Send BD Initiator state machine. */ - REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE | - SND_BD_IN_MODE_ATTN_ENABLE); - - /* Enable the Send BD Selector state machine. */ - REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE | - SND_BD_SEL_MODE_ATTN_ENABLE); + pDevice->RxJumboProdIdx = 0; +#endif /* T3_JUMBO_RCV_ENTRY_COUNT */ + + /* Configure the MAC address. */ + LM_SetMacAddress (pDevice, pDevice->NodeAddress); + + /* Initialize the transmit random backoff seed. */ + Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] + + pDevice->NodeAddress[2] + pDevice->NodeAddress[3] + + pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) & + MAC_TX_BACKOFF_SEED_MASK; + REG_WR (pDevice, MacCtrl.TxBackoffSeed, Value32); + + /* Receive MTU. Frames larger than the MTU is marked as oversized. */ + REG_WR (pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */ + + /* Configure Time slot/IPG per 802.3 */ + REG_WR (pDevice, MacCtrl.TxLengths, 0x2620); + + /* + * Configure Receive Rules so that packets don't match + * Programmble rule will be queued to Return Ring 1 + */ + REG_WR (pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS); + + /* + * Configure to have 16 Classes of Services (COS) and one + * queue per class. Bad frames are queued to RRR#1. + * And frames don't match rules are also queued to COS#1. + */ + REG_WR (pDevice, RcvListPlmt.Config, 0x181); + + /* Enable Receive Placement Statistics */ + REG_WR (pDevice, RcvListPlmt.StatsEnableMask, 0xffffff); + REG_WR (pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE); + + /* Enable Send Data Initator Statistics */ + REG_WR (pDevice, SndDataIn.StatsEnableMask, 0xffffff); + REG_WR (pDevice, SndDataIn.StatsCtrl, + T3_SND_DATA_IN_STATS_CTRL_ENABLE | + T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE); + + /* Disable the host coalescing state machine before configuring it's */ + /* parameters. */ + REG_WR (pDevice, HostCoalesce.Mode, 0); + for (j = 0; j < 2000; j++) { + Value32 = REG_RD (pDevice, HostCoalesce.Mode); + if (!(Value32 & HOST_COALESCE_ENABLE)) { + break; + } + MM_Wait (10); + } + + /* Host coalescing configurations. */ + REG_WR (pDevice, HostCoalesce.RxCoalescingTicks, + pDevice->RxCoalescingTicks); + REG_WR (pDevice, HostCoalesce.TxCoalescingTicks, + pDevice->TxCoalescingTicks); + REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFrames, + pDevice->RxMaxCoalescedFrames); + REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFrames, + pDevice->TxMaxCoalescedFrames); + REG_WR (pDevice, HostCoalesce.RxCoalescedTickDuringInt, + pDevice->RxCoalescingTicksDuringInt); + REG_WR (pDevice, HostCoalesce.TxCoalescedTickDuringInt, + pDevice->TxCoalescingTicksDuringInt); + REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt, + pDevice->RxMaxCoalescedFramesDuringInt); + REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt, + pDevice->TxMaxCoalescedFramesDuringInt); + + /* Initialize the address of the status block. The NIC will DMA */ + /* the status block to this memory which resides on the host. */ + REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.High, + pDevice->StatusBlkPhy.High); + REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.Low, + pDevice->StatusBlkPhy.Low); + + /* Initialize the address of the statistics block. The NIC will DMA */ + /* the statistics to this block of memory. */ + REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.High, + pDevice->StatsBlkPhy.High); + REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.Low, + pDevice->StatsBlkPhy.Low); + + REG_WR (pDevice, HostCoalesce.StatsCoalescingTicks, + pDevice->StatsCoalescingTicks); + + REG_WR (pDevice, HostCoalesce.StatsBlkNicAddr, 0x300); + REG_WR (pDevice, HostCoalesce.StatusBlkNicAddr, 0xb00); + + /* Enable Host Coalesing state machine */ + REG_WR (pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE | + pDevice->CoalesceMode); + + /* Enable the Receive BD Completion state machine. */ + REG_WR (pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE | + RCV_BD_COMP_MODE_ATTN_ENABLE); + + /* Enable the Receive List Placement state machine. */ + REG_WR (pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE); + + /* Enable the Receive List Selector state machine. */ + REG_WR (pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE | + RCV_LIST_SEL_MODE_ATTN_ENABLE); + + /* Enable transmit DMA, clear statistics. */ + pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS | + MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE; + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS); + + /* GRC miscellaneous local control register. */ + pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN | + GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM; + + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1; + } + + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); + MM_Wait (40); + + /* Reset RX counters. */ + for (j = 0; j < sizeof (LM_RX_COUNTERS); j++) { + ((PLM_UINT8) & pDevice->RxCounters)[j] = 0; + } + + /* Reset TX counters. */ + for (j = 0; j < sizeof (LM_TX_COUNTERS); j++) { + ((PLM_UINT8) & pDevice->TxCounters)[j] = 0; + } + + MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0); + + /* Enable the DMA Completion state machine. */ + REG_WR (pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE); + + /* Enable the DMA Write state machine. */ + Value32 = DMA_WRITE_MODE_ENABLE | + DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE | + DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE | + DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE | + DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE | + DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE; + REG_WR (pDevice, DmaWrite.Mode, Value32); + + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) { + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { + Value16 = REG_RD (pDevice, PciCfg.PciXCommand); + Value16 &= + ~(PCIX_CMD_MAX_SPLIT_MASK | + PCIX_CMD_MAX_BURST_MASK); + Value16 |= + ((PCIX_CMD_MAX_BURST_CPIOB << + PCIX_CMD_MAX_BURST_SHL) & + PCIX_CMD_MAX_BURST_MASK); + if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) { + Value16 |= + (pDevice-> + SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL) + & PCIX_CMD_MAX_SPLIT_MASK; + } + REG_WR (pDevice, PciCfg.PciXCommand, Value16); + } + } + + /* Enable the Read DMA state machine. */ + Value32 = DMA_READ_MODE_ENABLE | + DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE | + DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE | + DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE | + DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE | + DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE | + DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE | + DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE | + DMA_READ_MODE_LONG_READ_ATTN_ENABLE; + + if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) { + Value32 |= DMA_READ_MODE_SPLIT_ENABLE; + } + REG_WR (pDevice, DmaRead.Mode, Value32); + + /* Enable the Receive Data Completion state machine. */ + REG_WR (pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE | + RCV_DATA_COMP_MODE_ATTN_ENABLE); + + /* Enable the Mbuf Cluster Free state machine. */ + REG_WR (pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE); + + /* Enable the Send Data Completion state machine. */ + REG_WR (pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE); + + /* Enable the Send BD Completion state machine. */ + REG_WR (pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE | + SND_BD_COMP_MODE_ATTN_ENABLE); + + /* Enable the Receive BD Initiator state machine. */ + REG_WR (pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE | + RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE); + + /* Enable the Receive Data and Receive BD Initiator state machine. */ + REG_WR (pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE | + RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE); + + /* Enable the Send Data Initiator state machine. */ + REG_WR (pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE); + + /* Enable the Send BD Initiator state machine. */ + REG_WR (pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE | + SND_BD_IN_MODE_ATTN_ENABLE); + + /* Enable the Send BD Selector state machine. */ + REG_WR (pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE | + SND_BD_SEL_MODE_ATTN_ENABLE); #if INCLUDE_5701_AX_FIX - /* Load the firmware for the 5701_A0 workaround. */ - if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0) - { - LM_LoadRlsFirmware(pDevice); - } + /* Load the firmware for the 5701_A0 workaround. */ + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0) { + LM_LoadRlsFirmware (pDevice); + } #endif - /* Enable the transmitter. */ - pDevice->TxMode = TX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); - - /* Enable the receiver. */ - pDevice->RxMode = RX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); - - if (pDevice->RestoreOnWakeUp) - { - pDevice->RestoreOnWakeUp = FALSE; - pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg; - pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType; - } - - /* Disable auto polling. */ - pDevice->MiMode = 0xc0000; - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = LED_CTRL_PHY_MODE_1; - } - else - { - if(pDevice->LedMode == LED_MODE_OUTPUT) - { - Value32 = LED_CTRL_PHY_MODE_2; - } - else - { - Value32 = LED_CTRL_PHY_MODE_1; + /* Enable the transmitter. */ + pDevice->TxMode = TX_MODE_ENABLE; + REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode); + + /* Enable the receiver. */ + pDevice->RxMode = RX_MODE_ENABLE; + REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode); + + if (pDevice->RestoreOnWakeUp) { + pDevice->RestoreOnWakeUp = FALSE; + pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg; + pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType; } - } - REG_WR(pDevice, MacCtrl.LedCtrl, Value32); - /* Activate Link to enable MAC state machine */ - REG_WR(pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN); + /* Disable auto polling. */ + pDevice->MiMode = 0xc0000; + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode); - if (pDevice->EnableTbi) - { - REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET); - MM_Wait(10); - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); - if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) - { - REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000); + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = LED_CTRL_PHY_MODE_1; + } else { + if (pDevice->LedMode == LED_MODE_OUTPUT) { + Value32 = LED_CTRL_PHY_MODE_2; + } else { + Value32 = LED_CTRL_PHY_MODE_1; + } } - } - /* Setup the phy chip. */ - LM_SetupPhy(pDevice); + REG_WR (pDevice, MacCtrl.LedCtrl, Value32); + + /* Activate Link to enable MAC state machine */ + REG_WR (pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN); - if (!pDevice->EnableTbi) { - /* Clear CRC stats */ - LM_ReadPhy(pDevice, 0x1e, &Value32); - LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000); - LM_ReadPhy(pDevice, 0x14, &Value32); - } + if (pDevice->EnableTbi) { + REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_RESET); + MM_Wait (10); + REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode); + if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) { + REG_WR (pDevice, MacCtrl.SerdesCfg, 0x616000); + } + } + /* Setup the phy chip. */ + LM_SetupPhy (pDevice); - /* Set up the receive mask. */ - LM_SetReceiveMask(pDevice, pDevice->ReceiveMask); + if (!pDevice->EnableTbi) { + /* Clear CRC stats */ + LM_ReadPhy (pDevice, 0x1e, &Value32); + LM_WritePhy (pDevice, 0x1e, Value32 | 0x8000); + LM_ReadPhy (pDevice, 0x14, &Value32); + } - /* Queue Rx packet buffers. */ - if(pDevice->QueueRxPackets) - { - LM_QueueRxPackets(pDevice); - } + /* Set up the receive mask. */ + LM_SetReceiveMask (pDevice, pDevice->ReceiveMask); - /* Enable interrupt to the host. */ - if(pDevice->InitDone) - { - LM_EnableInterrupt(pDevice); - } + /* Queue Rx packet buffers. */ + if (pDevice->QueueRxPackets) { + LM_QueueRxPackets (pDevice); + } - return LM_STATUS_SUCCESS; -} /* LM_ResetAdapter */ + /* Enable interrupt to the host. */ + if (pDevice->InitDone) { + LM_EnableInterrupt (pDevice); + } + return LM_STATUS_SUCCESS; +} /* LM_ResetAdapter */ /******************************************************************************/ /* Description: */ @@ -2979,18 +2762,15 @@ PLM_DEVICE_BLOCK pDevice) /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_DisableInterrupt( - PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice) { - REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl | - MISC_HOST_CTRL_MASK_PCI_INT); - MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); + REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl | + MISC_HOST_CTRL_MASK_PCI_INT); + MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1); - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } - /******************************************************************************/ /* Description: */ /* This routine enables the adapter to generate interrupts. */ @@ -2998,24 +2778,20 @@ LM_DisableInterrupt( /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_EnableInterrupt( - PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice) { - REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl & - ~MISC_HOST_CTRL_MASK_PCI_INT); - MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0); + REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl & + ~MISC_HOST_CTRL_MASK_PCI_INT); + MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0); - if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) - { - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_SET_INT); - } + if (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) { + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_SET_INT); + } - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } - /******************************************************************************/ /* Description: */ /* This routine puts a packet on the wire if there is a transmit DMA */ @@ -3027,306 +2803,279 @@ LM_EnableInterrupt( /* LM_STATUS_SUCCESS */ /******************************************************************************/ #if 0 -LM_STATUS -LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) { - LM_UINT32 FragCount; - PT3_SND_BD pSendBd; - PT3_SND_BD pShadowSendBd; - LM_UINT32 Value32, Len; - LM_UINT32 Idx; + LM_UINT32 FragCount; + PT3_SND_BD pSendBd; + PT3_SND_BD pShadowSendBd; + LM_UINT32 Value32, Len; + LM_UINT32 Idx; - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) { - return LM_5700SendPacket(pDevice, pPacket); - } + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + return LM_5700SendPacket (pDevice, pPacket); + } - /* Update the SendBdLeft count. */ - atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + /* Update the SendBdLeft count. */ + atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); - /* Initalize the send buffer descriptors. */ - Idx = pDevice->SendProdIdx; + /* Initalize the send buffer descriptors. */ + Idx = pDevice->SendProdIdx; - pSendBd = &pDevice->pSendBdVirt[Idx]; + pSendBd = &pDevice->pSendBdVirt[Idx]; - /* Next producer index. */ - if (pDevice->NicSendBd == TRUE) - { - T3_64BIT_HOST_ADDR paddr; + /* Next producer index. */ + if (pDevice->NicSendBd == TRUE) { + T3_64BIT_HOST_ADDR paddr; + + pShadowSendBd = &pDevice->ShadowSendBd[Idx]; + for (FragCount = 0;;) { + MM_MapTxDma (pDevice, pPacket, &paddr, &Len, FragCount); + /* Initialize the pointer to the send buffer fragment. */ + if (paddr.High != pShadowSendBd->HostAddr.High) { + __raw_writel (paddr.High, + &(pSendBd->HostAddr.High)); + pShadowSendBd->HostAddr.High = paddr.High; + } + __raw_writel (paddr.Low, &(pSendBd->HostAddr.Low)); + + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; + + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) { + Value32 |= SND_BD_FLAG_END; + if (Value32 != pShadowSendBd->u1.Len_Flags) { + __raw_writel (Value32, + &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { + __raw_writel (pPacket->VlanTag, + &(pSendBd->u2.VlanTag)); + } + break; + } else { + if (Value32 != pShadowSendBd->u1.Len_Flags) { + __raw_writel (Value32, + &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { + __raw_writel (pPacket->VlanTag, + &(pSendBd->u2.VlanTag)); + } + } - pShadowSendBd = &pDevice->ShadowSendBd[Idx]; - for(FragCount = 0; ; ) - { - MM_MapTxDma(pDevice, pPacket, &paddr, &Len, FragCount); - /* Initialize the pointer to the send buffer fragment. */ - if (paddr.High != pShadowSendBd->HostAddr.High) - { - __raw_writel(paddr.High, &(pSendBd->HostAddr.High)); - pShadowSendBd->HostAddr.High = paddr.High; - } - __raw_writel(paddr.Low, &(pSendBd->HostAddr.Low)); - - /* Setup the control flags and send buffer size. */ - Value32 = (Len << 16) | pPacket->Flags; - - Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - - FragCount++; - if (FragCount >= pPacket->u.Tx.FragCount) - { - Value32 |= SND_BD_FLAG_END; - if (Value32 != pShadowSendBd->u1.Len_Flags) - { - __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); - pShadowSendBd->u1.Len_Flags = Value32; - } - if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { - __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag)); - } - break; - } - else - { - if (Value32 != pShadowSendBd->u1.Len_Flags) - { - __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); - pShadowSendBd->u1.Len_Flags = Value32; - } - if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { - __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag)); - } - } - - pSendBd++; - pShadowSendBd++; - if (Idx == 0) - { - pSendBd = &pDevice->pSendBdVirt[0]; - pShadowSendBd = &pDevice->ShadowSendBd[0]; - } - } /* for */ + pSendBd++; + pShadowSendBd++; + if (Idx == 0) { + pSendBd = &pDevice->pSendBdVirt[0]; + pShadowSendBd = &pDevice->ShadowSendBd[0]; + } + } /* for */ - /* Put the packet descriptor in the ActiveQ. */ - QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket); - wmb(); - MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + wmb (); + MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); - } - else - { - for(FragCount = 0; ; ) - { - /* Initialize the pointer to the send buffer fragment. */ - MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); + } else { + for (FragCount = 0;;) { + /* Initialize the pointer to the send buffer fragment. */ + MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len, + FragCount); - pSendBd->u2.VlanTag = pPacket->VlanTag; + pSendBd->u2.VlanTag = pPacket->VlanTag; - /* Setup the control flags and send buffer size. */ - Value32 = (Len << 16) | pPacket->Flags; + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; - Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - FragCount++; - if (FragCount >= pPacket->u.Tx.FragCount) - { - pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; - break; - } - else - { - pSendBd->u1.Len_Flags = Value32; - } - pSendBd++; - if (Idx == 0) - { - pSendBd = &pDevice->pSendBdVirt[0]; - } - } /* for */ + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) { + pSendBd->u1.Len_Flags = + Value32 | SND_BD_FLAG_END; + break; + } else { + pSendBd->u1.Len_Flags = Value32; + } + pSendBd++; + if (Idx == 0) { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } /* for */ - /* Put the packet descriptor in the ActiveQ. */ - QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket); - wmb(); - MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + wmb (); + MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); - } + } - /* Update the producer index. */ - pDevice->SendProdIdx = Idx; + /* Update the producer index. */ + pDevice->SendProdIdx = Idx; - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } #endif -LM_STATUS -LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) { - LM_UINT32 FragCount; - PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd; - T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT]; - LM_UINT32 StartIdx, Idx; + LM_UINT32 FragCount; + PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd; + T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT]; + LM_UINT32 StartIdx, Idx; + + while (1) { + /* Initalize the send buffer descriptors. */ + StartIdx = Idx = pDevice->SendProdIdx; + + if (pDevice->NicSendBd) { + pTmpSendBd = pSendBd = &NicSendBdArr[0]; + } else { + pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx]; + } - while (1) - { - /* Initalize the send buffer descriptors. */ - StartIdx = Idx = pDevice->SendProdIdx; + /* Next producer index. */ + for (FragCount = 0;;) { + LM_UINT32 Value32, Len; - if (pDevice->NicSendBd) - { - pTmpSendBd = pSendBd = &NicSendBdArr[0]; - } - else - { - pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx]; + /* Initialize the pointer to the send buffer fragment. */ + MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len, + FragCount); + + pSendBd->u2.VlanTag = pPacket->VlanTag; + + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; + + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) { + pSendBd->u1.Len_Flags = + Value32 | SND_BD_FLAG_END; + break; + } else { + pSendBd->u1.Len_Flags = Value32; + } + pSendBd++; + if ((Idx == 0) && !pDevice->NicSendBd) { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } /* for */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + if (LM_Test4GBoundary (pDevice, pPacket, pTmpSendBd) == + LM_STATUS_SUCCESS) { + if (MM_CoalesceTxBuffer (pDevice, pPacket) != + LM_STATUS_SUCCESS) { + QQ_PushHead (&pDevice->TxPacketFreeQ. + Container, pPacket); + return LM_STATUS_FAILURE; + } + continue; + } + } + break; } + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket); - /* Next producer index. */ - for(FragCount = 0; ; ) - { - LM_UINT32 Value32, Len; + if (pDevice->NicSendBd) { + pSendBd = &pDevice->pSendBdVirt[StartIdx]; + pShadowSendBd = &pDevice->ShadowSendBd[StartIdx]; - /* Initialize the pointer to the send buffer fragment. */ - MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); + while (StartIdx != Idx) { + LM_UINT32 Value32; - pSendBd->u2.VlanTag = pPacket->VlanTag; + if ((Value32 = pTmpSendBd->HostAddr.High) != + pShadowSendBd->HostAddr.High) { + __raw_writel (Value32, + &(pSendBd->HostAddr.High)); + pShadowSendBd->HostAddr.High = Value32; + } - /* Setup the control flags and send buffer size. */ - Value32 = (Len << 16) | pPacket->Flags; + __raw_writel (pTmpSendBd->HostAddr.Low, + &(pSendBd->HostAddr.Low)); - Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if ((Value32 = pTmpSendBd->u1.Len_Flags) != + pShadowSendBd->u1.Len_Flags) { + __raw_writel (Value32, + &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } - FragCount++; - if (FragCount >= pPacket->u.Tx.FragCount) - { - pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; - break; - } - else - { - pSendBd->u1.Len_Flags = Value32; - } - pSendBd++; - if ((Idx == 0) && !pDevice->NicSendBd) - { - pSendBd = &pDevice->pSendBdVirt[0]; - } - } /* for */ - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) == - LM_STATUS_SUCCESS) - { - if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS) - { - QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); - return LM_STATUS_FAILURE; - } - continue; - } - } - break; - } - /* Put the packet descriptor in the ActiveQ. */ - QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); - - if (pDevice->NicSendBd) - { - pSendBd = &pDevice->pSendBdVirt[StartIdx]; - pShadowSendBd = &pDevice->ShadowSendBd[StartIdx]; - - while (StartIdx != Idx) - { - LM_UINT32 Value32; - - if ((Value32 = pTmpSendBd->HostAddr.High) != - pShadowSendBd->HostAddr.High) - { - __raw_writel(Value32, &(pSendBd->HostAddr.High)); - pShadowSendBd->HostAddr.High = Value32; - } - - __raw_writel(pTmpSendBd->HostAddr.Low, &(pSendBd->HostAddr.Low)); - - if ((Value32 = pTmpSendBd->u1.Len_Flags) != - pShadowSendBd->u1.Len_Flags) - { - __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); - pShadowSendBd->u1.Len_Flags = Value32; - } - - if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) - { - __raw_writel(pTmpSendBd->u2.VlanTag, &(pSendBd->u2.VlanTag)); - } - - StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - if (StartIdx == 0) - pSendBd = &pDevice->pSendBdVirt[0]; - else - pSendBd++; - pTmpSendBd++; - } - wmb(); - MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { + __raw_writel (pTmpSendBd->u2.VlanTag, + &(pSendBd->u2.VlanTag)); + } - if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) - { - MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); - } - } - else - { - wmb(); - MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + StartIdx = + (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if (StartIdx == 0) + pSendBd = &pDevice->pSendBdVirt[0]; + else + pSendBd++; + pTmpSendBd++; + } + wmb (); + MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); - if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) - { - MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) { + MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + } + } else { + wmb (); + MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + + if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) { + MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, + Idx); + } } - } - /* Update the SendBdLeft count. */ - atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + /* Update the SendBdLeft count. */ + atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); - /* Update the producer index. */ - pDevice->SendProdIdx = Idx; + /* Update the producer index. */ + pDevice->SendProdIdx = Idx; - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } STATIC LM_STATUS -LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, - PT3_SND_BD pSendBd) +LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, + PT3_SND_BD pSendBd) { - int FragCount; - LM_UINT32 Idx, Base, Len; - - Idx = pDevice->SendProdIdx; - for(FragCount = 0; ; ) - { - Len = pSendBd->u1.Len_Flags >> 16; - if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) && - (pSendBd->HostAddr.High == 0) && - ((Base + 8 + Len) < Base)) - { - return LM_STATUS_SUCCESS; - } - FragCount++; - if (FragCount >= pPacket->u.Tx.FragCount) - { - break; + int FragCount; + LM_UINT32 Idx, Base, Len; + + Idx = pDevice->SendProdIdx; + for (FragCount = 0;;) { + Len = pSendBd->u1.Len_Flags >> 16; + if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) && + (pSendBd->HostAddr.High == 0) && + ((Base + 8 + Len) < Base)) { + return LM_STATUS_SUCCESS; + } + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) { + break; + } + pSendBd++; + if (!pDevice->NicSendBd) { + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if (Idx == 0) { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } } - pSendBd++; - if (!pDevice->NicSendBd) - { - Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - if (Idx == 0) - { - pSendBd = &pDevice->pSendBdVirt[0]; - } - } - } - return LM_STATUS_FAILURE; + return LM_STATUS_FAILURE; } /******************************************************************************/ @@ -3335,35 +3084,30 @@ LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, /* Return: */ /******************************************************************************/ __inline static unsigned long -ComputeCrc32( -unsigned char *pBuffer, -unsigned long BufferSize) { - unsigned long Reg; - unsigned long Tmp; - unsigned long j, k; +ComputeCrc32 (unsigned char *pBuffer, unsigned long BufferSize) +{ + unsigned long Reg; + unsigned long Tmp; + unsigned long j, k; - Reg = 0xffffffff; + Reg = 0xffffffff; - for(j = 0; j < BufferSize; j++) - { - Reg ^= pBuffer[j]; + for (j = 0; j < BufferSize; j++) { + Reg ^= pBuffer[j]; - for(k = 0; k < 8; k++) - { - Tmp = Reg & 0x01; + for (k = 0; k < 8; k++) { + Tmp = Reg & 0x01; - Reg >>= 1; + Reg >>= 1; - if(Tmp) - { - Reg ^= 0xedb88320; - } + if (Tmp) { + Reg ^= 0xedb88320; + } + } } - } - - return ~Reg; -} /* ComputeCrc32 */ + return ~Reg; +} /* ComputeCrc32 */ /******************************************************************************/ /* Description: */ @@ -3372,149 +3116,139 @@ unsigned long BufferSize) { /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_SetReceiveMask( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 Mask) { - LM_UINT32 ReceiveMask; - LM_UINT32 RxMode; - LM_UINT32 j, k; - - ReceiveMask = Mask; - - RxMode = pDevice->RxMode; - - if(Mask & LM_ACCEPT_UNICAST) - { - Mask &= ~LM_ACCEPT_UNICAST; - } - - if(Mask & LM_ACCEPT_MULTICAST) - { - Mask &= ~LM_ACCEPT_MULTICAST; - } - - if(Mask & LM_ACCEPT_ALL_MULTICAST) - { - Mask &= ~LM_ACCEPT_ALL_MULTICAST; - } - - if(Mask & LM_ACCEPT_BROADCAST) - { - Mask &= ~LM_ACCEPT_BROADCAST; - } - - RxMode &= ~RX_MODE_PROMISCUOUS_MODE; - if(Mask & LM_PROMISCUOUS_MODE) - { - RxMode |= RX_MODE_PROMISCUOUS_MODE; - Mask &= ~LM_PROMISCUOUS_MODE; - } - - RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED); - if(Mask & LM_ACCEPT_ERROR_PACKET) - { - RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED; - Mask &= ~LM_ACCEPT_ERROR_PACKET; - } - - /* Make sure all the bits are valid before committing changes. */ - if(Mask) - { - return LM_STATUS_FAILURE; - } +LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask) +{ + LM_UINT32 ReceiveMask; + LM_UINT32 RxMode; + LM_UINT32 j, k; - /* Commit the new filter. */ - pDevice->RxMode = RxMode; - REG_WR(pDevice, MacCtrl.RxMode, RxMode); + ReceiveMask = Mask; - pDevice->ReceiveMask = ReceiveMask; + RxMode = pDevice->RxMode; - /* Set up the MC hash table. */ - if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST) - { - for(k = 0; k < 4; k++) - { - REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff); + if (Mask & LM_ACCEPT_UNICAST) { + Mask &= ~LM_ACCEPT_UNICAST; } - } - else if(ReceiveMask & LM_ACCEPT_MULTICAST) - { - LM_UINT32 HashReg[4]; - HashReg[0] = 0; HashReg[1] = 0; HashReg[2] = 0; HashReg[3] = 0; - for(j = 0; j < pDevice->McEntryCount; j++) - { - LM_UINT32 RegIndex; - LM_UINT32 Bitpos; - LM_UINT32 Crc32; + if (Mask & LM_ACCEPT_MULTICAST) { + Mask &= ~LM_ACCEPT_MULTICAST; + } + + if (Mask & LM_ACCEPT_ALL_MULTICAST) { + Mask &= ~LM_ACCEPT_ALL_MULTICAST; + } + + if (Mask & LM_ACCEPT_BROADCAST) { + Mask &= ~LM_ACCEPT_BROADCAST; + } - Crc32 = ComputeCrc32(pDevice->McTable[j], ETHERNET_ADDRESS_SIZE); + RxMode &= ~RX_MODE_PROMISCUOUS_MODE; + if (Mask & LM_PROMISCUOUS_MODE) { + RxMode |= RX_MODE_PROMISCUOUS_MODE; + Mask &= ~LM_PROMISCUOUS_MODE; + } + + RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED); + if (Mask & LM_ACCEPT_ERROR_PACKET) { + RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED; + Mask &= ~LM_ACCEPT_ERROR_PACKET; + } + + /* Make sure all the bits are valid before committing changes. */ + if (Mask) { + return LM_STATUS_FAILURE; + } - /* The most significant 7 bits of the CRC32 (no inversion), */ - /* are used to index into one of the possible 128 bit positions. */ - Bitpos = ~Crc32 & 0x7f; + /* Commit the new filter. */ + pDevice->RxMode = RxMode; + REG_WR (pDevice, MacCtrl.RxMode, RxMode); - /* Hash register index. */ - RegIndex = (Bitpos & 0x60) >> 5; + pDevice->ReceiveMask = ReceiveMask; - /* Bit to turn on within a hash register. */ - Bitpos &= 0x1f; + /* Set up the MC hash table. */ + if (ReceiveMask & LM_ACCEPT_ALL_MULTICAST) { + for (k = 0; k < 4; k++) { + REG_WR (pDevice, MacCtrl.HashReg[k], 0xffffffff); + } + } else if (ReceiveMask & LM_ACCEPT_MULTICAST) { + LM_UINT32 HashReg[4]; + + HashReg[0] = 0; + HashReg[1] = 0; + HashReg[2] = 0; + HashReg[3] = 0; + for (j = 0; j < pDevice->McEntryCount; j++) { + LM_UINT32 RegIndex; + LM_UINT32 Bitpos; + LM_UINT32 Crc32; + + Crc32 = + ComputeCrc32 (pDevice->McTable[j], + ETHERNET_ADDRESS_SIZE); + + /* The most significant 7 bits of the CRC32 (no inversion), */ + /* are used to index into one of the possible 128 bit positions. */ + Bitpos = ~Crc32 & 0x7f; + + /* Hash register index. */ + RegIndex = (Bitpos & 0x60) >> 5; + + /* Bit to turn on within a hash register. */ + Bitpos &= 0x1f; + + /* Enable the multicast bit. */ + HashReg[RegIndex] |= (1 << Bitpos); + } - /* Enable the multicast bit. */ - HashReg[RegIndex] |= (1 << Bitpos); + /* REV_AX has problem with multicast filtering where it uses both */ + /* DA and SA to perform hashing. */ + for (k = 0; k < 4; k++) { + REG_WR (pDevice, MacCtrl.HashReg[k], HashReg[k]); + } + } else { + /* Reject all multicast frames. */ + for (j = 0; j < 4; j++) { + REG_WR (pDevice, MacCtrl.HashReg[j], 0); + } } - /* REV_AX has problem with multicast filtering where it uses both */ - /* DA and SA to perform hashing. */ - for(k = 0; k < 4; k++) - { - REG_WR(pDevice, MacCtrl.HashReg[k], HashReg[k]); + /* By default, Tigon3 will accept broadcast frames. We need to setup */ + if (ReceiveMask & LM_ACCEPT_BROADCAST) { + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); + } else { + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE); + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE); + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE2_RULE); + REG_WR (pDevice, + MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE2_VALUE); + } + + /* disable the rest of the rules. */ + for (j = RCV_LAST_RULE_IDX; j < 16; j++) { + REG_WR (pDevice, MacCtrl.RcvRules[j].Rule, 0); + REG_WR (pDevice, MacCtrl.RcvRules[j].Value, 0); } - } - else - { - /* Reject all multicast frames. */ - for(j = 0; j < 4; j++) - { - REG_WR(pDevice, MacCtrl.HashReg[j], 0); - } - } - - /* By default, Tigon3 will accept broadcast frames. We need to setup */ - if(ReceiveMask & LM_ACCEPT_BROADCAST) - { - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, - REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, - REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, - REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, - REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); - } - else - { - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, - REJECT_BROADCAST_RULE1_RULE); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, - REJECT_BROADCAST_RULE1_VALUE); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, - REJECT_BROADCAST_RULE2_RULE); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, - REJECT_BROADCAST_RULE2_VALUE); - } - - /* disable the rest of the rules. */ - for(j = RCV_LAST_RULE_IDX; j < 16; j++) - { - REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0); - REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0); - } - - return LM_STATUS_SUCCESS; -} /* LM_SetReceiveMask */ + return LM_STATUS_SUCCESS; +} /* LM_SetReceiveMask */ /******************************************************************************/ /* Description: */ @@ -3525,138 +3259,135 @@ LM_UINT32 Mask) { /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_Abort( -PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice) { - PLM_PACKET pPacket; - LM_UINT Idx; - - LM_DisableInterrupt(pDevice); - - /* Disable all the state machines. */ - LM_CntrlBlock(pDevice,T3_BLOCK_MAC_RX_ENGINE,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_INITIATOR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_PLMT,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_SELECTOR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_INITIATOR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_COMP,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_COMP,LM_DISABLE); - - LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_SELECTOR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_INITIATOR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_INITIATOR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_DMA_RD,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_COMP,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_DMA_COMP,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_COMP,LM_DISABLE); - - /* Clear TDE bit */ - pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE; - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); - - LM_CntrlBlock(pDevice,T3_BLOCK_MAC_TX_ENGINE,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_HOST_COALESING,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_DMA_WR,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_CLUSTER_FREE,LM_DISABLE); - - /* Reset all FTQs */ - REG_WR(pDevice, Ftq.Reset, 0xffffffff); - REG_WR(pDevice, Ftq.Reset, 0x0); - - LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_MANAGER,LM_DISABLE); - LM_CntrlBlock(pDevice,T3_BLOCK_MEM_ARBITOR,LM_DISABLE); - - MM_ACQUIRE_INT_LOCK(pDevice); - - /* Abort packets that have already queued to go out. */ - pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->TxPacketActiveQ.Container); - while(pPacket) - { - - pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED; - pDevice->TxCounters.TxPacketAbortedCnt++; - - atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); - - QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); - - pPacket = (PLM_PACKET) - QQ_PopHead(&pDevice->TxPacketActiveQ.Container); - } - - /* Cleanup the receive return rings. */ - LM_ServiceRxInterrupt(pDevice); - - /* Don't want to indicate rx packets in Ndis miniport shutdown context. */ - /* Doing so may cause system crash. */ - if(!pDevice->ShuttingDown) - { - /* Indicate packets to the protocol. */ - MM_IndicateTxPackets(pDevice); - - /* Indicate received packets to the protocols. */ - MM_IndicateRxPackets(pDevice); - } - else - { - /* Move the receive packet descriptors in the ReceivedQ to the */ - /* free queue. */ - for(; ;) - { - pPacket = (PLM_PACKET) QQ_PopHead( - &pDevice->RxPacketReceivedQ.Container); - if(pPacket == NULL) - { - break; - } - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + PLM_PACKET pPacket; + LM_UINT Idx; + + LM_DisableInterrupt (pDevice); + + /* Disable all the state machines. */ + LM_CntrlBlock (pDevice, T3_BLOCK_MAC_RX_ENGINE, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_INITIATOR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_PLMT, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_SELECTOR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_INITIATOR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_COMP, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_COMP, LM_DISABLE); + + LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_SELECTOR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_INITIATOR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_INITIATOR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_DMA_RD, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_COMP, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_DMA_COMP, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_COMP, LM_DISABLE); + + /* Clear TDE bit */ + pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE; + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode); + + LM_CntrlBlock (pDevice, T3_BLOCK_MAC_TX_ENGINE, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_HOST_COALESING, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_DMA_WR, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_CLUSTER_FREE, LM_DISABLE); + + /* Reset all FTQs */ + REG_WR (pDevice, Ftq.Reset, 0xffffffff); + REG_WR (pDevice, Ftq.Reset, 0x0); + + LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_MANAGER, LM_DISABLE); + LM_CntrlBlock (pDevice, T3_BLOCK_MEM_ARBITOR, LM_DISABLE); + + MM_ACQUIRE_INT_LOCK (pDevice); + + /* Abort packets that have already queued to go out. */ + pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ.Container); + while (pPacket) { + + pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED; + pDevice->TxCounters.TxPacketAbortedCnt++; + + atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + + QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket); + + pPacket = (PLM_PACKET) + QQ_PopHead (&pDevice->TxPacketActiveQ.Container); + } + + /* Cleanup the receive return rings. */ + LM_ServiceRxInterrupt (pDevice); + + /* Don't want to indicate rx packets in Ndis miniport shutdown context. */ + /* Doing so may cause system crash. */ + if (!pDevice->ShuttingDown) { + /* Indicate packets to the protocol. */ + MM_IndicateTxPackets (pDevice); + + /* Indicate received packets to the protocols. */ + MM_IndicateRxPackets (pDevice); + } else { + /* Move the receive packet descriptors in the ReceivedQ to the */ + /* free queue. */ + for (;;) { + pPacket = + (PLM_PACKET) QQ_PopHead (&pDevice-> + RxPacketReceivedQ. + Container); + if (pPacket == NULL) { + break; + } + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, + pPacket); + } } - } - /* Clean up the Std Receive Producer ring. */ - Idx = pDevice->pStatusBlkVirt->RcvStdConIdx; + /* Clean up the Std Receive Producer ring. */ + Idx = pDevice->pStatusBlkVirt->RcvStdConIdx; - while(Idx != pDevice->RxStdProdIdx) { - pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + - MM_UINT_PTR(pDevice->pRxStdBdVirt[Idx].Opaque)); + while (Idx != pDevice->RxStdProdIdx) { + pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) + + MM_UINT_PTR (pDevice->pRxStdBdVirt[Idx]. + Opaque)); - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); - Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK; - } /* while */ + Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK; + } /* while */ - /* Reinitialize our copy of the indices. */ - pDevice->RxStdProdIdx = 0; + /* Reinitialize our copy of the indices. */ + pDevice->RxStdProdIdx = 0; #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - /* Clean up the Jumbo Receive Producer ring. */ - Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx; - - while(Idx != pDevice->RxJumboProdIdx) { - pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + - MM_UINT_PTR(pDevice->pRxJumboBdVirt[Idx].Opaque)); + /* Clean up the Jumbo Receive Producer ring. */ + Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx; - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + while (Idx != pDevice->RxJumboProdIdx) { + pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) + + MM_UINT_PTR (pDevice-> + pRxJumboBdVirt[Idx]. + Opaque)); - Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; - } /* while */ + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); - /* Reinitialize our copy of the indices. */ - pDevice->RxJumboProdIdx = 0; -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; + } /* while */ - MM_RELEASE_INT_LOCK(pDevice); + /* Reinitialize our copy of the indices. */ + pDevice->RxJumboProdIdx = 0; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - /* Initialize the statistis Block */ - pDevice->pStatusBlkVirt->Status = 0; - pDevice->pStatusBlkVirt->RcvStdConIdx = 0; - pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; - pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; + MM_RELEASE_INT_LOCK (pDevice); - return LM_STATUS_SUCCESS; -} /* LM_Abort */ + /* Initialize the statistis Block */ + pDevice->pStatusBlkVirt->Status = 0; + pDevice->pStatusBlkVirt->RcvStdConIdx = 0; + pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; + pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; + return LM_STATUS_SUCCESS; +} /* LM_Abort */ /******************************************************************************/ /* Description: */ @@ -3667,140 +3398,130 @@ PLM_DEVICE_BLOCK pDevice) /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_Halt( -PLM_DEVICE_BLOCK pDevice) { - PLM_PACKET pPacket; - LM_UINT32 EntryCnt; - - LM_Abort(pDevice); +LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice) +{ + PLM_PACKET pPacket; + LM_UINT32 EntryCnt; - /* Get the number of entries in the queue. */ - EntryCnt = QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container); + LM_Abort (pDevice); - /* Make sure all the packets have been accounted for. */ - for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) - { - pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); - if (pPacket == 0) - break; + /* Get the number of entries in the queue. */ + EntryCnt = QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container); - MM_FreeRxBuffer(pDevice, pPacket); + /* Make sure all the packets have been accounted for. */ + for (EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) { + pPacket = + (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container); + if (pPacket == 0) + break; - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - } + MM_FreeRxBuffer (pDevice, pPacket); - LM_ResetChip(pDevice); + QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket); + } - /* Restore PCI configuration registers. */ - MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, - pDevice->SavedCacheLineReg); - LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, - (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); + LM_ResetChip (pDevice); - /* Reprogram the MAC address. */ - LM_SetMacAddress(pDevice, pDevice->NodeAddress); + /* Restore PCI configuration registers. */ + MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG, + pDevice->SavedCacheLineReg); + LM_RegWrInd (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, + (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); - return LM_STATUS_SUCCESS; -} /* LM_Halt */ + /* Reprogram the MAC address. */ + LM_SetMacAddress (pDevice, pDevice->NodeAddress); + return LM_STATUS_SUCCESS; +} /* LM_Halt */ -STATIC LM_STATUS -LM_ResetChip(PLM_DEVICE_BLOCK pDevice) +STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32; - LM_UINT32 j; - - /* Wait for access to the nvram interface before resetting. This is */ - /* a workaround to prevent EEPROM corruption. */ - if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && - T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) - { - /* Request access to the flash interface. */ - REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); - - for(j = 0; j < 100000; j++) - { - Value32 = REG_RD(pDevice, Nvram.SwArb); - if(Value32 & SW_ARB_GNT1) - { - break; - } - MM_Wait(10); + LM_UINT32 Value32; + LM_UINT32 j; + + /* Wait for access to the nvram interface before resetting. This is */ + /* a workaround to prevent EEPROM corruption. */ + if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) { + /* Request access to the flash interface. */ + REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); + + for (j = 0; j < 100000; j++) { + Value32 = REG_RD (pDevice, Nvram.SwArb); + if (Value32 & SW_ARB_GNT1) { + break; + } + MM_Wait (10); + } } - } - /* Global reset. */ - REG_WR(pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET); - MM_Wait(40); MM_Wait(40); MM_Wait(40); + /* Global reset. */ + REG_WR (pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET); + MM_Wait (40); + MM_Wait (40); + MM_Wait (40); - /* make sure we re-enable indirect accesses */ - MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, - pDevice->MiscHostCtrl); + /* make sure we re-enable indirect accesses */ + MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, + pDevice->MiscHostCtrl); - /* Set MAX PCI retry to zero. */ - Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE; - if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) - { - if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) - { - Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + /* Set MAX PCI retry to zero. */ + Value32 = + T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE; + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) { + Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + } } - } - MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32); + MM_WriteConfig32 (pDevice, T3_PCI_STATE_REG, Value32); - /* Restore PCI command register. */ - MM_WriteConfig32(pDevice, PCI_COMMAND_REG, - pDevice->PciCommandStatusWords); + /* Restore PCI command register. */ + MM_WriteConfig32 (pDevice, PCI_COMMAND_REG, + pDevice->PciCommandStatusWords); - /* Disable PCI-X relaxed ordering bit. */ - MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32); - Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING; - MM_WriteConfig32(pDevice, PCIX_CAP_REG, Value32); + /* Disable PCI-X relaxed ordering bit. */ + MM_ReadConfig32 (pDevice, PCIX_CAP_REG, &Value32); + Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING; + MM_WriteConfig32 (pDevice, PCIX_CAP_REG, Value32); - /* Enable memory arbiter. */ - REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); + /* Enable memory arbiter. */ + REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); -#ifdef BIG_ENDIAN_PCI /* This from jfd */ - Value32 = GRC_MODE_WORD_SWAP_DATA| - GRC_MODE_WORD_SWAP_NON_FRAME_DATA; +#ifdef BIG_ENDIAN_PCI /* This from jfd */ + Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA; #else #ifdef BIG_ENDIAN_HOST - /* Reconfigure the mode register. */ - Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | - GRC_MODE_WORD_SWAP_NON_FRAME_DATA | - GRC_MODE_BYTE_SWAP_DATA | - GRC_MODE_WORD_SWAP_DATA; + /* Reconfigure the mode register. */ + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA; #else - /* Reconfigure the mode register. */ - Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; + /* Reconfigure the mode register. */ + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; #endif #endif - REG_WR(pDevice, Grc.Mode, Value32); - - /* Prevent PXE from restarting. */ - MEM_WR_OFFSET(pDevice, 0x0b50, T3_MAGIC_NUM); - - if(pDevice->EnableTbi) { - pDevice->MacMode = MAC_MODE_PORT_MODE_TBI; - REG_WR(pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI); - } - else { - REG_WR(pDevice, MacCtrl.Mode, 0); - } - - /* Wait for the firmware to finish initialization. */ - for(j = 0; j < 100000; j++) - { - MM_Wait(10); - - Value32 = MEM_RD_OFFSET(pDevice, 0x0b50); - if(Value32 == ~T3_MAGIC_NUM) - { - break; + REG_WR (pDevice, Grc.Mode, Value32); + + /* Prevent PXE from restarting. */ + MEM_WR_OFFSET (pDevice, 0x0b50, T3_MAGIC_NUM); + + if (pDevice->EnableTbi) { + pDevice->MacMode = MAC_MODE_PORT_MODE_TBI; + REG_WR (pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI); + } else { + REG_WR (pDevice, MacCtrl.Mode, 0); + } + + /* Wait for the firmware to finish initialization. */ + for (j = 0; j < 100000; j++) { + MM_Wait (10); + + Value32 = MEM_RD_OFFSET (pDevice, 0x0b50); + if (Value32 == ~T3_MAGIC_NUM) { + break; + } } - } - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } /******************************************************************************/ @@ -3808,161 +3529,143 @@ LM_ResetChip(PLM_DEVICE_BLOCK pDevice) /* */ /* Return: */ /******************************************************************************/ -__inline static void -LM_ServiceTxInterrupt( -PLM_DEVICE_BLOCK pDevice) { - PLM_PACKET pPacket; - LM_UINT32 HwConIdx; - LM_UINT32 SwConIdx; - - HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; - - /* Get our copy of the consumer index. The buffer descriptors */ - /* that are in between the consumer indices are freed. */ - SwConIdx = pDevice->SendConIdx; - - /* Move the packets from the TxPacketActiveQ that are sent out to */ - /* the TxPacketXmittedQ. Packets that are sent use the */ - /* descriptors that are between SwConIdx and HwConIdx. */ - while(SwConIdx != HwConIdx) - { - /* Get the packet that was sent from the TxPacketActiveQ. */ - pPacket = (PLM_PACKET) QQ_PopHead( - &pDevice->TxPacketActiveQ.Container); - - /* Set the return status. */ - pPacket->PacketStatus = LM_STATUS_SUCCESS; - - /* Put the packet in the TxPacketXmittedQ for indication later. */ - QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); - - /* Move to the next packet's BD. */ - SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) & - T3_SEND_RCB_ENTRY_COUNT_MASK; - - /* Update the number of unused BDs. */ - atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); - - /* Get the new updated HwConIdx. */ +__inline static void LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice) +{ + PLM_PACKET pPacket; + LM_UINT32 HwConIdx; + LM_UINT32 SwConIdx; + HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; - } /* while */ - /* Save the new SwConIdx. */ - pDevice->SendConIdx = SwConIdx; + /* Get our copy of the consumer index. The buffer descriptors */ + /* that are in between the consumer indices are freed. */ + SwConIdx = pDevice->SendConIdx; + + /* Move the packets from the TxPacketActiveQ that are sent out to */ + /* the TxPacketXmittedQ. Packets that are sent use the */ + /* descriptors that are between SwConIdx and HwConIdx. */ + while (SwConIdx != HwConIdx) { + /* Get the packet that was sent from the TxPacketActiveQ. */ + pPacket = + (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ. + Container); + + /* Set the return status. */ + pPacket->PacketStatus = LM_STATUS_SUCCESS; + + /* Put the packet in the TxPacketXmittedQ for indication later. */ + QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket); + + /* Move to the next packet's BD. */ + SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) & + T3_SEND_RCB_ENTRY_COUNT_MASK; + + /* Update the number of unused BDs. */ + atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + + /* Get the new updated HwConIdx. */ + HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; + } /* while */ -} /* LM_ServiceTxInterrupt */ + /* Save the new SwConIdx. */ + pDevice->SendConIdx = SwConIdx; +} /* LM_ServiceTxInterrupt */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -__inline static void -LM_ServiceRxInterrupt( -PLM_DEVICE_BLOCK pDevice) { - PLM_PACKET pPacket; - PT3_RCV_BD pRcvBd; - LM_UINT32 HwRcvRetProdIdx; - LM_UINT32 SwRcvRetConIdx; - - /* Loop thru the receive return rings for received packets. */ - HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; - - SwRcvRetConIdx = pDevice->RcvRetConIdx; - while(SwRcvRetConIdx != HwRcvRetProdIdx) - { - pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx]; - - /* Get the received packet descriptor. */ - pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + - MM_UINT_PTR(pRcvBd->Opaque)); - - /* Check the error flag. */ - if(pRcvBd->ErrorFlag && - pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) - { - pPacket->PacketStatus = LM_STATUS_FAILURE; - - pDevice->RxCounters.RxPacketErrCnt++; - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) - { - pDevice->RxCounters.RxErrCrcCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) - { - pDevice->RxCounters.RxErrCollCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) - { - pDevice->RxCounters.RxErrLinkLostCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) - { - pDevice->RxCounters.RxErrPhyDecodeCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) - { - pDevice->RxCounters.RxErrOddNibbleCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) - { - pDevice->RxCounters.RxErrMacAbortCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) - { - pDevice->RxCounters.RxErrShortPacketCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) - { - pDevice->RxCounters.RxErrNoResourceCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) - { - pDevice->RxCounters.RxErrLargePacketCnt++; - } - } - else - { - pPacket->PacketStatus = LM_STATUS_SUCCESS; - pPacket->PacketSize = pRcvBd->Len - 4; +__inline static void LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice) +{ + PLM_PACKET pPacket; + PT3_RCV_BD pRcvBd; + LM_UINT32 HwRcvRetProdIdx; + LM_UINT32 SwRcvRetConIdx; - pPacket->Flags = pRcvBd->Flags; - if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) - { - pPacket->VlanTag = pRcvBd->VlanTag; - } + /* Loop thru the receive return rings for received packets. */ + HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; - pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum; - } + SwRcvRetConIdx = pDevice->RcvRetConIdx; + while (SwRcvRetConIdx != HwRcvRetProdIdx) { + pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx]; - /* Put the packet descriptor containing the received packet */ - /* buffer in the RxPacketReceivedQ for indication later. */ - QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket); + /* Get the received packet descriptor. */ + pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) + + MM_UINT_PTR (pRcvBd->Opaque)); - /* Go to the next buffer descriptor. */ - SwRcvRetConIdx = (SwRcvRetConIdx + 1) & - T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK; + /* Check the error flag. */ + if (pRcvBd->ErrorFlag && + pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) { + pPacket->PacketStatus = LM_STATUS_FAILURE; - /* Get the updated HwRcvRetProdIdx. */ - HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; - } /* while */ + pDevice->RxCounters.RxPacketErrCnt++; + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) { + pDevice->RxCounters.RxErrCrcCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) { + pDevice->RxCounters.RxErrCollCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) { + pDevice->RxCounters.RxErrLinkLostCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) { + pDevice->RxCounters.RxErrPhyDecodeCnt++; + } - pDevice->RcvRetConIdx = SwRcvRetConIdx; + if (pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) { + pDevice->RxCounters.RxErrOddNibbleCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) { + pDevice->RxCounters.RxErrMacAbortCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) { + pDevice->RxCounters.RxErrShortPacketCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) { + pDevice->RxCounters.RxErrNoResourceCnt++; + } + + if (pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) { + pDevice->RxCounters.RxErrLargePacketCnt++; + } + } else { + pPacket->PacketStatus = LM_STATUS_SUCCESS; + pPacket->PacketSize = pRcvBd->Len - 4; + + pPacket->Flags = pRcvBd->Flags; + if (pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) { + pPacket->VlanTag = pRcvBd->VlanTag; + } + + pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum; + } + + /* Put the packet descriptor containing the received packet */ + /* buffer in the RxPacketReceivedQ for indication later. */ + QQ_PushTail (&pDevice->RxPacketReceivedQ.Container, pPacket); + + /* Go to the next buffer descriptor. */ + SwRcvRetConIdx = (SwRcvRetConIdx + 1) & + T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK; + + /* Get the updated HwRcvRetProdIdx. */ + HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; + } /* while */ - /* Update the receive return ring consumer index. */ - MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx); -} /* LM_ServiceRxInterrupt */ + pDevice->RcvRetConIdx = SwRcvRetConIdx; + /* Update the receive return ring consumer index. */ + MB_REG_WR (pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx); +} /* LM_ServiceRxInterrupt */ /******************************************************************************/ /* Description: */ @@ -3972,206 +3675,179 @@ PLM_DEVICE_BLOCK pDevice) { /* Return: */ /* LM_STATUS_SUCCESS */ /******************************************************************************/ -LM_STATUS -LM_ServiceInterrupts( - PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32; - int ServicePhyInt = FALSE; - - /* Setup the phy chip whenever the link status changes. */ - if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) - { - Value32 = REG_RD(pDevice, MacCtrl.Status); - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) - { - if (Value32 & MAC_STATUS_MI_INTERRUPT) - { - ServicePhyInt = TRUE; - } - } - else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED) - { - ServicePhyInt = TRUE; - } - } - else - { - if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS) - { - pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | - (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); - ServicePhyInt = TRUE; + LM_UINT32 Value32; + int ServicePhyInt = FALSE; + + /* Setup the phy chip whenever the link status changes. */ + if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) { + Value32 = REG_RD (pDevice, MacCtrl.Status); + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) { + if (Value32 & MAC_STATUS_MI_INTERRUPT) { + ServicePhyInt = TRUE; + } + } else if (Value32 & MAC_STATUS_LINK_STATE_CHANGED) { + ServicePhyInt = TRUE; + } + } else { + if (pDevice->pStatusBlkVirt-> + Status & STATUS_BLOCK_LINK_CHANGED_STATUS) { + pDevice->pStatusBlkVirt->Status = + STATUS_BLOCK_UPDATED | (pDevice->pStatusBlkVirt-> + Status & + ~STATUS_BLOCK_LINK_CHANGED_STATUS); + ServicePhyInt = TRUE; + } } - } #if INCLUDE_TBI_SUPPORT - if (pDevice->IgnoreTbiLinkChange == TRUE) - { - ServicePhyInt = FALSE; - } + if (pDevice->IgnoreTbiLinkChange == TRUE) { + ServicePhyInt = FALSE; + } #endif - if (ServicePhyInt == TRUE) - { - LM_SetupPhy(pDevice); - } - - /* Service receive and transmit interrupts. */ - LM_ServiceRxInterrupt(pDevice); - LM_ServiceTxInterrupt(pDevice); + if (ServicePhyInt == TRUE) { + LM_SetupPhy (pDevice); + } - /* No spinlock for this queue since this routine is serialized. */ - if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container)) - { - /* Indicate receive packets. */ - MM_IndicateRxPackets(pDevice); - /* LM_QueueRxPackets(pDevice); */ - } + /* Service receive and transmit interrupts. */ + LM_ServiceRxInterrupt (pDevice); + LM_ServiceTxInterrupt (pDevice); - /* No spinlock for this queue since this routine is serialized. */ - if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container)) - { - MM_IndicateTxPackets(pDevice); - } + /* No spinlock for this queue since this routine is serialized. */ + if (!QQ_Empty (&pDevice->RxPacketReceivedQ.Container)) { + /* Indicate receive packets. */ + MM_IndicateRxPackets (pDevice); + /* LM_QueueRxPackets(pDevice); */ + } - return LM_STATUS_SUCCESS; -} /* LM_ServiceInterrupts */ + /* No spinlock for this queue since this routine is serialized. */ + if (!QQ_Empty (&pDevice->TxPacketXmittedQ.Container)) { + MM_IndicateTxPackets (pDevice); + } + return LM_STATUS_SUCCESS; +} /* LM_ServiceInterrupts */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS -LM_MulticastAdd( -PLM_DEVICE_BLOCK pDevice, -PLM_UINT8 pMcAddress) { - PLM_UINT8 pEntry; - LM_UINT32 j; - - pEntry = pDevice->McTable[0]; - for(j = 0; j < pDevice->McEntryCount; j++) - { - if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress)) - { - /* Found a match, increment the instance count. */ - pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1; +LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress) +{ + PLM_UINT8 pEntry; + LM_UINT32 j; - return LM_STATUS_SUCCESS; - } + pEntry = pDevice->McTable[0]; + for (j = 0; j < pDevice->McEntryCount; j++) { + if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) { + /* Found a match, increment the instance count. */ + pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1; - pEntry += LM_MC_ENTRY_SIZE; - } + return LM_STATUS_SUCCESS; + } - if(pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE) - { - return LM_STATUS_FAILURE; - } + pEntry += LM_MC_ENTRY_SIZE; + } - pEntry = pDevice->McTable[pDevice->McEntryCount]; + if (pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE) { + return LM_STATUS_FAILURE; + } - COPY_ETH_ADDRESS(pMcAddress, pEntry); - pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1; + pEntry = pDevice->McTable[pDevice->McEntryCount]; - pDevice->McEntryCount++; + COPY_ETH_ADDRESS (pMcAddress, pEntry); + pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1; - LM_SetReceiveMask(pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST); + pDevice->McEntryCount++; - return LM_STATUS_SUCCESS; -} /* LM_MulticastAdd */ + LM_SetReceiveMask (pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST); + return LM_STATUS_SUCCESS; +} /* LM_MulticastAdd */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS -LM_MulticastDel( -PLM_DEVICE_BLOCK pDevice, -PLM_UINT8 pMcAddress) { - PLM_UINT8 pEntry; - LM_UINT32 j; - - pEntry = pDevice->McTable[0]; - for(j = 0; j < pDevice->McEntryCount; j++) - { - if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress)) - { - /* Found a match, decrement the instance count. */ - pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1; - - /* No more instance left, remove the address from the table. */ - /* Move the last entry in the table to the delete slot. */ - if(pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 && - pDevice->McEntryCount > 1) - { - - COPY_ETH_ADDRESS( - pDevice->McTable[pDevice->McEntryCount-1], pEntry); - pEntry[LM_MC_INSTANCE_COUNT_INDEX] = - pDevice->McTable[pDevice->McEntryCount-1] - [LM_MC_INSTANCE_COUNT_INDEX]; - } - pDevice->McEntryCount--; +LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress) +{ + PLM_UINT8 pEntry; + LM_UINT32 j; + + pEntry = pDevice->McTable[0]; + for (j = 0; j < pDevice->McEntryCount; j++) { + if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) { + /* Found a match, decrement the instance count. */ + pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1; + + /* No more instance left, remove the address from the table. */ + /* Move the last entry in the table to the delete slot. */ + if (pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 && + pDevice->McEntryCount > 1) { + + COPY_ETH_ADDRESS (pDevice-> + McTable[pDevice-> + McEntryCount - 1], + pEntry); + pEntry[LM_MC_INSTANCE_COUNT_INDEX] = + pDevice->McTable[pDevice->McEntryCount - 1] + [LM_MC_INSTANCE_COUNT_INDEX]; + } + pDevice->McEntryCount--; + + /* Update the receive mask if the table is empty. */ + if (pDevice->McEntryCount == 0) { + LM_SetReceiveMask (pDevice, + pDevice-> + ReceiveMask & + ~LM_ACCEPT_MULTICAST); + } - /* Update the receive mask if the table is empty. */ - if(pDevice->McEntryCount == 0) - { - LM_SetReceiveMask(pDevice, - pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); - } + return LM_STATUS_SUCCESS; + } - return LM_STATUS_SUCCESS; + pEntry += LM_MC_ENTRY_SIZE; } - pEntry += LM_MC_ENTRY_SIZE; - } - - return LM_STATUS_FAILURE; -} /* LM_MulticastDel */ - + return LM_STATUS_FAILURE; +} /* LM_MulticastDel */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS -LM_MulticastClear( -PLM_DEVICE_BLOCK pDevice) { - pDevice->McEntryCount = 0; - - LM_SetReceiveMask(pDevice, pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); +LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice) +{ + pDevice->McEntryCount = 0; - return LM_STATUS_SUCCESS; -} /* LM_MulticastClear */ + LM_SetReceiveMask (pDevice, + pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); + return LM_STATUS_SUCCESS; +} /* LM_MulticastClear */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS -LM_SetMacAddress( - PLM_DEVICE_BLOCK pDevice, - PLM_UINT8 pMacAddress) +LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress) { - LM_UINT32 j; - - for(j = 0; j < 4; j++) - { - REG_WR(pDevice, MacCtrl.MacAddr[j].High, - (pMacAddress[0] << 8) | pMacAddress[1]); - REG_WR(pDevice, MacCtrl.MacAddr[j].Low, - (pMacAddress[2] << 24) | (pMacAddress[3] << 16) | - (pMacAddress[4] << 8) | pMacAddress[5]); - } - - return LM_STATUS_SUCCESS; -} + LM_UINT32 j; + + for (j = 0; j < 4; j++) { + REG_WR (pDevice, MacCtrl.MacAddr[j].High, + (pMacAddress[0] << 8) | pMacAddress[1]); + REG_WR (pDevice, MacCtrl.MacAddr[j].Low, + (pMacAddress[2] << 24) | (pMacAddress[3] << 16) | + (pMacAddress[4] << 8) | pMacAddress[5]); + } + return LM_STATUS_SUCCESS; +} /******************************************************************************/ /* Description: */ @@ -4182,93 +3858,93 @@ LM_SetMacAddress( /* None. */ /******************************************************************************/ static LM_STATUS -LM_TranslateRequestedMediaType( -LM_REQUESTED_MEDIA_TYPE RequestedMediaType, -PLM_MEDIA_TYPE pMediaType, -PLM_LINE_SPEED pLineSpeed, -PLM_DUPLEX_MODE pDuplexMode) { - *pMediaType = LM_MEDIA_TYPE_AUTO; - *pLineSpeed = LM_LINE_SPEED_UNKNOWN; - *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN; - - /* determine media type */ - switch(RequestedMediaType) { +LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE RequestedMediaType, + PLM_MEDIA_TYPE pMediaType, + PLM_LINE_SPEED pLineSpeed, + PLM_DUPLEX_MODE pDuplexMode) +{ + *pMediaType = LM_MEDIA_TYPE_AUTO; + *pLineSpeed = LM_LINE_SPEED_UNKNOWN; + *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN; + + /* determine media type */ + switch (RequestedMediaType) { case LM_REQUESTED_MEDIA_TYPE_BNC: - *pMediaType = LM_MEDIA_TYPE_BNC; - *pLineSpeed = LM_LINE_SPEED_10MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; + *pMediaType = LM_MEDIA_TYPE_BNC; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_AUTO: - *pMediaType = LM_MEDIA_TYPE_UTP; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_10MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_10MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_100MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_100MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_1000MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_1000MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS: - *pMediaType = LM_MEDIA_TYPE_FIBER; - *pLineSpeed = LM_LINE_SPEED_100MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_FIBER; - *pLineSpeed = LM_LINE_SPEED_100MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS: - *pMediaType = LM_MEDIA_TYPE_FIBER; - *pLineSpeed = LM_LINE_SPEED_1000MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_FIBER; - *pLineSpeed = LM_LINE_SPEED_1000MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; default: - break; - } /* switch */ + break; + } /* switch */ - return LM_STATUS_SUCCESS; -} /* LM_TranslateRequestedMediaType */ + return LM_STATUS_SUCCESS; +} /* LM_TranslateRequestedMediaType */ /******************************************************************************/ /* Description: */ @@ -4277,285 +3953,284 @@ PLM_DUPLEX_MODE pDuplexMode) { /* LM_STATUS_LINK_ACTIVE */ /* LM_STATUS_LINK_DOWN */ /******************************************************************************/ -static LM_STATUS -LM_InitBcm540xPhy( -PLM_DEVICE_BLOCK pDevice) +static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice) { - LM_LINE_SPEED CurrentLineSpeed; - LM_DUPLEX_MODE CurrentDuplexMode; - LM_STATUS CurrentLinkStatus; - LM_UINT32 Value32; - LM_UINT32 j; - -#if 1 /* jmb: bugfix -- moved here, out of code that sets initial pwr state */ - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x2); + LM_LINE_SPEED CurrentLineSpeed; + LM_DUPLEX_MODE CurrentDuplexMode; + LM_STATUS CurrentLinkStatus; + LM_UINT32 Value32; + LM_UINT32 j; + +#if 1 /* jmb: bugfix -- moved here, out of code that sets initial pwr state */ + LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x2); #endif - if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) - { - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - - if(!pDevice->InitDone) - { - Value32 = 0; - } - - if(!(Value32 & PHY_STATUS_LINK_PASS)) - { - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); + if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) { + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); + if (!pDevice->InitDone) { + Value32 = 0; + } - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); + if (!(Value32 & PHY_STATUS_LINK_PASS)) { + LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - for(j = 0; j < 1000; j++) - { - MM_Wait(10); + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - if(Value32 & PHY_STATUS_LINK_PASS) - { - MM_Wait(40); - break; - } - } + LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20); - if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV) - { - if(!(Value32 & PHY_STATUS_LINK_PASS) && - (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS)) - { - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); - for(j = 0; j < 100; j++) - { - MM_Wait(10); + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + for (j = 0; j < 1000; j++) { + MM_Wait (10); - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if(!(Value32 & PHY_CTRL_PHY_RESET)) - { - MM_Wait(40); - break; + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + if (Value32 & PHY_STATUS_LINK_PASS) { + MM_Wait (40); + break; + } } - } - - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); - - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); - - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); - - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); - - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + if ((pDevice->PhyId & PHY_ID_REV_MASK) == + PHY_BCM5401_B0_REV) { + if (!(Value32 & PHY_STATUS_LINK_PASS) + && (pDevice->OldLineSpeed == + LM_LINE_SPEED_1000MBPS)) { + LM_WritePhy (pDevice, PHY_CTRL_REG, + PHY_CTRL_PHY_RESET); + for (j = 0; j < 100; j++) { + MM_Wait (10); + + LM_ReadPhy (pDevice, + PHY_CTRL_REG, + &Value32); + if (! + (Value32 & + PHY_CTRL_PHY_RESET)) { + MM_Wait (40); + break; + } + } + + LM_WritePhy (pDevice, BCM5401_AUX_CTRL, + 0x0c20); + + LM_WritePhy (pDevice, + BCM540X_DSP_ADDRESS_REG, + 0x0012); + LM_WritePhy (pDevice, + BCM540X_DSP_RW_PORT, + 0x1804); + + LM_WritePhy (pDevice, + BCM540X_DSP_ADDRESS_REG, + 0x0013); + LM_WritePhy (pDevice, + BCM540X_DSP_RW_PORT, + 0x1204); + + LM_WritePhy (pDevice, + BCM540X_DSP_ADDRESS_REG, + 0x8006); + LM_WritePhy (pDevice, + BCM540X_DSP_RW_PORT, + 0x0132); + + LM_WritePhy (pDevice, + BCM540X_DSP_ADDRESS_REG, + 0x8006); + LM_WritePhy (pDevice, + BCM540X_DSP_RW_PORT, + 0x0232); + + LM_WritePhy (pDevice, + BCM540X_DSP_ADDRESS_REG, + 0x201f); + LM_WritePhy (pDevice, + BCM540X_DSP_RW_PORT, + 0x0a20); + } + } + } + } else if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) { + /* Bug: 5701 A0, B0 TX CRC workaround. */ + LM_WritePhy (pDevice, 0x15, 0x0a75); + LM_WritePhy (pDevice, 0x1c, 0x8c68); + LM_WritePhy (pDevice, 0x1c, 0x8d68); + LM_WritePhy (pDevice, 0x1c, 0x8c68); + } + + /* Acknowledge interrupts. */ + LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32); + LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32); + + /* Configure the interrupt mask. */ + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) { + LM_WritePhy (pDevice, BCM540X_INT_MASK_REG, + ~BCM540X_INT_LINK_CHANGE); + } + + /* Configure PHY led mode. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701 || + (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700)) { + if (pDevice->LedMode == LED_MODE_THREE_LINK) { + LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG, + BCM540X_EXT_CTRL_LINK3_LED_MODE); + } else { + LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG, 0); } - } - } - } - else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0) - { - /* Bug: 5701 A0, B0 TX CRC workaround. */ - LM_WritePhy(pDevice, 0x15, 0x0a75); - LM_WritePhy(pDevice, 0x1c, 0x8c68); - LM_WritePhy(pDevice, 0x1c, 0x8d68); - LM_WritePhy(pDevice, 0x1c, 0x8c68); - } - - /* Acknowledge interrupts. */ - LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32); - - /* Configure the interrupt mask. */ - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) - { - LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE); - } - - /* Configure PHY led mode. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 || - (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)) - { - if(pDevice->LedMode == LED_MODE_THREE_LINK) - { - LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, - BCM540X_EXT_CTRL_LINK3_LED_MODE); - } - else - { - LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0); } - } - CurrentLinkStatus = LM_STATUS_LINK_DOWN; + CurrentLinkStatus = LM_STATUS_LINK_DOWN; - /* Get current link and duplex mode. */ - for(j = 0; j < 100; j++) - { - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + /* Get current link and duplex mode. */ + for (j = 0; j < 100; j++) { + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); - if(Value32 & PHY_STATUS_LINK_PASS) - { - break; + if (Value32 & PHY_STATUS_LINK_PASS) { + break; + } + MM_Wait (40); } - MM_Wait(40); - } - - if(Value32 & PHY_STATUS_LINK_PASS) - { - - /* Determine the current line and duplex settings. */ - LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); - for(j = 0; j < 2000; j++) - { - MM_Wait(10); - LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); - if(Value32) - { - break; - } - } + if (Value32 & PHY_STATUS_LINK_PASS) { - switch(Value32 & BCM540X_AUX_SPEED_MASK) - { - case BCM540X_AUX_10BASET_HD: - CurrentLineSpeed = LM_LINE_SPEED_10MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_HALF; - break; + /* Determine the current line and duplex settings. */ + LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32); + for (j = 0; j < 2000; j++) { + MM_Wait (10); - case BCM540X_AUX_10BASET_FD: - CurrentLineSpeed = LM_LINE_SPEED_10MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_FULL; - break; + LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32); + if (Value32) { + break; + } + } - case BCM540X_AUX_100BASETX_HD: - CurrentLineSpeed = LM_LINE_SPEED_100MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_HALF; - break; + switch (Value32 & BCM540X_AUX_SPEED_MASK) { + case BCM540X_AUX_10BASET_HD: + CurrentLineSpeed = LM_LINE_SPEED_10MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; - case BCM540X_AUX_100BASETX_FD: - CurrentLineSpeed = LM_LINE_SPEED_100MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_FULL; - break; + case BCM540X_AUX_10BASET_FD: + CurrentLineSpeed = LM_LINE_SPEED_10MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; - case BCM540X_AUX_100BASET_HD: - CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_HALF; - break; + case BCM540X_AUX_100BASETX_HD: + CurrentLineSpeed = LM_LINE_SPEED_100MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; - case BCM540X_AUX_100BASET_FD: - CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_FULL; - break; + case BCM540X_AUX_100BASETX_FD: + CurrentLineSpeed = LM_LINE_SPEED_100MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; - default: + case BCM540X_AUX_100BASET_HD: + CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; - CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN; - CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN; - break; - } + case BCM540X_AUX_100BASET_FD: + CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; - /* Make sure we are in auto-neg mode. */ - for (j = 0; j < 200; j++) - { - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if(Value32 && Value32 != 0x7fff) - { - break; - } + default: - if(Value32 == 0 && pDevice->RequestedMediaType == - LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) - { - break; - } + CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN; + CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN; + break; + } - MM_Wait(10); - } + /* Make sure we are in auto-neg mode. */ + for (j = 0; j < 200; j++) { + LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32); + if (Value32 && Value32 != 0x7fff) { + break; + } - /* Use the current line settings for "auto" mode. */ - if(pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) - { - if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE) - { - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + if (Value32 == 0 && pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) { + break; + } - /* We may be exiting low power mode and the link is in */ - /* 10mb. In this case, we need to restart autoneg. */ - LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &Value32); - pDevice->advertising1000 = Value32; - /* 5702FE supports 10/100Mb only. */ - if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703 || - pDevice->BondId != GRC_MISC_BD_ID_5702FE) - { - if(!(Value32 & (BCM540X_AN_AD_1000BASET_HALF | - BCM540X_AN_AD_1000BASET_FULL))) - { - CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; - } - } - } - else - { - CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; - } - } - else - { - /* Force line settings. */ - /* Use the current setting if it matches the user's requested */ - /* setting. */ - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if((pDevice->LineSpeed == CurrentLineSpeed) && - (pDevice->DuplexMode == CurrentDuplexMode)) - { - if ((pDevice->DisableAutoNeg && - !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) || - (!pDevice->DisableAutoNeg && - (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) - { - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + MM_Wait (10); } - else - { - CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + + /* Use the current line settings for "auto" mode. */ + if (pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO + || pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) { + if (Value32 & PHY_CTRL_AUTO_NEG_ENABLE) { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + + /* We may be exiting low power mode and the link is in */ + /* 10mb. In this case, we need to restart autoneg. */ + LM_ReadPhy (pDevice, BCM540X_1000BASET_CTRL_REG, + &Value32); + pDevice->advertising1000 = Value32; + /* 5702FE supports 10/100Mb only. */ + if (T3_ASIC_REV (pDevice->ChipRevId) != + T3_ASIC_REV_5703 + || pDevice->BondId != + GRC_MISC_BD_ID_5702FE) { + if (! + (Value32 & + (BCM540X_AN_AD_1000BASET_HALF | + BCM540X_AN_AD_1000BASET_FULL))) { + CurrentLinkStatus = + LM_STATUS_LINK_SETTING_MISMATCH; + } + } + } else { + CurrentLinkStatus = + LM_STATUS_LINK_SETTING_MISMATCH; + } + } else { + /* Force line settings. */ + /* Use the current setting if it matches the user's requested */ + /* setting. */ + LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32); + if ((pDevice->LineSpeed == CurrentLineSpeed) && + (pDevice->DuplexMode == CurrentDuplexMode)) { + if ((pDevice->DisableAutoNeg && + !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) || + (!pDevice->DisableAutoNeg && + (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) { + CurrentLinkStatus = + LM_STATUS_LINK_ACTIVE; + } else { + CurrentLinkStatus = + LM_STATUS_LINK_SETTING_MISMATCH; + } + } else { + CurrentLinkStatus = + LM_STATUS_LINK_SETTING_MISMATCH; + } } - } - else - { - CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; - } - } - /* Save line settings. */ - pDevice->LineSpeed = CurrentLineSpeed; - pDevice->DuplexMode = CurrentDuplexMode; - pDevice->MediaType = LM_MEDIA_TYPE_UTP; - } + /* Save line settings. */ + pDevice->LineSpeed = CurrentLineSpeed; + pDevice->DuplexMode = CurrentDuplexMode; + pDevice->MediaType = LM_MEDIA_TYPE_UTP; + } - return CurrentLinkStatus; -} /* LM_InitBcm540xPhy */ + return CurrentLinkStatus; +} /* LM_InitBcm540xPhy */ /******************************************************************************/ /* Description: */ @@ -4563,83 +4238,69 @@ PLM_DEVICE_BLOCK pDevice) /* Return: */ /******************************************************************************/ LM_STATUS -LM_SetFlowControl( - PLM_DEVICE_BLOCK pDevice, - LM_UINT32 LocalPhyAd, - LM_UINT32 RemotePhyAd) +LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice, + LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd) { - LM_FLOW_CONTROL FlowCap; + LM_FLOW_CONTROL FlowCap; - /* Resolve flow control. */ - FlowCap = LM_FLOW_CONTROL_NONE; + /* Resolve flow control. */ + FlowCap = LM_FLOW_CONTROL_NONE; - /* See Table 28B-3 of 802.3ab-1999 spec. */ - if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) - { - if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) - { - if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) - { - if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) - { - FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | - LM_FLOW_CONTROL_RECEIVE_PAUSE; - } - else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE) - { - FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE; - } - } - else - { - if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) - { - FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | - LM_FLOW_CONTROL_RECEIVE_PAUSE; - } - } - } - else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) - { - if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) && - (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) - { - FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE; - } - } - } - else - { - FlowCap = pDevice->FlowControlCap; - } - - /* Enable/disable rx PAUSE. */ - pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL; - if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE && - (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || - pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) - { - pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE; - pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL; - - } - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); - - /* Enable/disable tx PAUSE. */ - pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL; - if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE && - (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || - pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) - { - pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; - pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL; - - } - REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); - - return LM_STATUS_SUCCESS; -} + /* See Table 28B-3 of 802.3ab-1999 spec. */ + if (pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) { + if (LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) { + if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) { + if (RemotePhyAd & + PHY_LINK_PARTNER_PAUSE_CAPABLE) { + FlowCap = + LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } else if (RemotePhyAd & + PHY_LINK_PARTNER_ASYM_PAUSE) { + FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } else { + if (RemotePhyAd & + PHY_LINK_PARTNER_PAUSE_CAPABLE) { + FlowCap = + LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + } else if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) { + if ((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) && + (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE; + } + } + } else { + FlowCap = pDevice->FlowControlCap; + } + + /* Enable/disable rx PAUSE. */ + pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL; + if (FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE && + (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || + pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) { + pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE; + pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL; + + } + REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode); + + /* Enable/disable tx PAUSE. */ + pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL; + if (FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE && + (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || + pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) { + pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; + pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL; + } + REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode); + + return LM_STATUS_SUCCESS; +} #if INCLUDE_TBI_SUPPORT /******************************************************************************/ @@ -4647,583 +4308,520 @@ LM_SetFlowControl( /* */ /* Return: */ /******************************************************************************/ -STATIC LM_STATUS -LM_InitBcm800xPhy( - PLM_DEVICE_BLOCK pDevice) +STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32; - LM_UINT32 j; + LM_UINT32 Value32; + LM_UINT32 j; - Value32 = REG_RD(pDevice, MacCtrl.Status); + Value32 = REG_RD (pDevice, MacCtrl.Status); - /* Reset the SERDES during init and when we have link. */ - if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) - { - /* Set PLL lock range. */ - LM_WritePhy(pDevice, 0x16, 0x8007); + /* Reset the SERDES during init and when we have link. */ + if (!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) { + /* Set PLL lock range. */ + LM_WritePhy (pDevice, 0x16, 0x8007); - /* Software reset. */ - LM_WritePhy(pDevice, 0x00, 0x8000); + /* Software reset. */ + LM_WritePhy (pDevice, 0x00, 0x8000); - /* Wait for reset to complete. */ - for(j = 0; j < 500; j++) - { - MM_Wait(10); - } + /* Wait for reset to complete. */ + for (j = 0; j < 500; j++) { + MM_Wait (10); + } - /* Config mode; seletct PMA/Ch 1 regs. */ - LM_WritePhy(pDevice, 0x10, 0x8411); + /* Config mode; seletct PMA/Ch 1 regs. */ + LM_WritePhy (pDevice, 0x10, 0x8411); - /* Enable auto-lock and comdet, select txclk for tx. */ - LM_WritePhy(pDevice, 0x11, 0x0a10); + /* Enable auto-lock and comdet, select txclk for tx. */ + LM_WritePhy (pDevice, 0x11, 0x0a10); - LM_WritePhy(pDevice, 0x18, 0x00a0); - LM_WritePhy(pDevice, 0x16, 0x41ff); + LM_WritePhy (pDevice, 0x18, 0x00a0); + LM_WritePhy (pDevice, 0x16, 0x41ff); - /* Assert and deassert POR. */ - LM_WritePhy(pDevice, 0x13, 0x0400); - MM_Wait(40); - LM_WritePhy(pDevice, 0x13, 0x0000); + /* Assert and deassert POR. */ + LM_WritePhy (pDevice, 0x13, 0x0400); + MM_Wait (40); + LM_WritePhy (pDevice, 0x13, 0x0000); - LM_WritePhy(pDevice, 0x11, 0x0a50); - MM_Wait(40); - LM_WritePhy(pDevice, 0x11, 0x0a10); + LM_WritePhy (pDevice, 0x11, 0x0a50); + MM_Wait (40); + LM_WritePhy (pDevice, 0x11, 0x0a10); - /* Delay for signal to stabilize. */ - for(j = 0; j < 15000; j++) - { - MM_Wait(10); - } + /* Delay for signal to stabilize. */ + for (j = 0; j < 15000; j++) { + MM_Wait (10); + } - /* Deselect the channel register so we can read the PHY id later. */ - LM_WritePhy(pDevice, 0x10, 0x8011); - } + /* Deselect the channel register so we can read the PHY id later. */ + LM_WritePhy (pDevice, 0x10, 0x8011); + } - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } - /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -STATIC LM_STATUS -LM_SetupFiberPhy( - PLM_DEVICE_BLOCK pDevice) +STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice) { - LM_STATUS CurrentLinkStatus; - AUTONEG_STATUS AnStatus = 0; - LM_UINT32 Value32; - LM_UINT32 Cnt; - LM_UINT32 j, k; + LM_STATUS CurrentLinkStatus; + AUTONEG_STATUS AnStatus = 0; + LM_UINT32 Value32; + LM_UINT32 Cnt; + LM_UINT32 j, k; - pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK); + pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK); - /* Initialize the send_config register. */ - REG_WR(pDevice, MacCtrl.TxAutoNeg, 0); + /* Initialize the send_config register. */ + REG_WR (pDevice, MacCtrl.TxAutoNeg, 0); - /* Enable TBI and full duplex mode. */ - pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI; - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + /* Enable TBI and full duplex mode. */ + pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI; + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode); - /* Initialize the BCM8002 SERDES PHY. */ - switch(pDevice->PhyId & PHY_ID_MASK) - { + /* Initialize the BCM8002 SERDES PHY. */ + switch (pDevice->PhyId & PHY_ID_MASK) { case PHY_BCM8002_PHY_ID: - LM_InitBcm800xPhy(pDevice); - break; + LM_InitBcm800xPhy (pDevice); + break; default: - break; - } - - /* Enable link change interrupt. */ - REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); - - /* Default to link down. */ - CurrentLinkStatus = LM_STATUS_LINK_DOWN; + break; + } - /* Get the link status. */ - Value32 = REG_RD(pDevice, MacCtrl.Status); - if(Value32 & MAC_STATUS_PCS_SYNCED) - { - if((pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO) || - (pDevice->DisableAutoNeg == FALSE)) - { - /* auto-negotiation mode. */ - /* Initialize the autoneg default capaiblities. */ - AutonegInit(&pDevice->AnInfo); - - /* Set the context pointer to point to the main device structure. */ - pDevice->AnInfo.pContext = pDevice; - - /* Setup flow control advertisement register. */ - Value32 = GetPhyAdFlowCntrlSettings(pDevice); - if(Value32 & PHY_AN_AD_PAUSE_CAPABLE) - { - pDevice->AnInfo.mr_adv_sym_pause = 1; - } - else - { - pDevice->AnInfo.mr_adv_sym_pause = 0; - } - - if(Value32 & PHY_AN_AD_ASYM_PAUSE) - { - pDevice->AnInfo.mr_adv_asym_pause = 1; - } - else - { - pDevice->AnInfo.mr_adv_asym_pause = 0; - } - - /* Try to autoneg up to six times. */ - if (pDevice->IgnoreTbiLinkChange) - { - Cnt = 1; - } - else - { - Cnt = 6; - } - for (j = 0; j < Cnt; j++) - { - REG_WR(pDevice, MacCtrl.TxAutoNeg, 0); - - Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK; - REG_WR(pDevice, MacCtrl.Mode, Value32); - MM_Wait(20); - - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | - MAC_MODE_SEND_CONFIGS); - - MM_Wait(20); - - pDevice->AnInfo.State = AN_STATE_UNKNOWN; - pDevice->AnInfo.CurrentTime_us = 0; - - REG_WR(pDevice, Grc.Timer, 0); - for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) && - (k < 75000); k++) - { - AnStatus = Autoneg8023z(&pDevice->AnInfo); - - if((AnStatus == AUTONEG_STATUS_DONE) || - (AnStatus == AUTONEG_STATUS_FAILED)) - { - break; - } + /* Enable link change interrupt. */ + REG_WR (pDevice, MacCtrl.MacEvent, + MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); - pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer); + /* Default to link down. */ + CurrentLinkStatus = LM_STATUS_LINK_DOWN; - } - if((AnStatus == AUTONEG_STATUS_DONE) || - (AnStatus == AUTONEG_STATUS_FAILED)) - { - break; - } - if (j >= 1) - { - if (!(REG_RD(pDevice, MacCtrl.Status) & - MAC_STATUS_PCS_SYNCED)) { - break; - } - } - } + /* Get the link status. */ + Value32 = REG_RD (pDevice, MacCtrl.Status); + if (Value32 & MAC_STATUS_PCS_SYNCED) { + if ((pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_AUTO) + || (pDevice->DisableAutoNeg == FALSE)) { + /* auto-negotiation mode. */ + /* Initialize the autoneg default capaiblities. */ + AutonegInit (&pDevice->AnInfo); + + /* Set the context pointer to point to the main device structure. */ + pDevice->AnInfo.pContext = pDevice; + + /* Setup flow control advertisement register. */ + Value32 = GetPhyAdFlowCntrlSettings (pDevice); + if (Value32 & PHY_AN_AD_PAUSE_CAPABLE) { + pDevice->AnInfo.mr_adv_sym_pause = 1; + } else { + pDevice->AnInfo.mr_adv_sym_pause = 0; + } - /* Stop sending configs. */ - MM_AnTxIdle(&pDevice->AnInfo); + if (Value32 & PHY_AN_AD_ASYM_PAUSE) { + pDevice->AnInfo.mr_adv_asym_pause = 1; + } else { + pDevice->AnInfo.mr_adv_asym_pause = 0; + } - /* Resolve flow control settings. */ - if((AnStatus == AUTONEG_STATUS_DONE) && - pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok && - pDevice->AnInfo.mr_lp_adv_full_duplex) - { - LM_UINT32 RemotePhyAd; - LM_UINT32 LocalPhyAd; + /* Try to autoneg up to six times. */ + if (pDevice->IgnoreTbiLinkChange) { + Cnt = 1; + } else { + Cnt = 6; + } + for (j = 0; j < Cnt; j++) { + REG_WR (pDevice, MacCtrl.TxAutoNeg, 0); + + Value32 = + pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK; + REG_WR (pDevice, MacCtrl.Mode, Value32); + MM_Wait (20); + + REG_WR (pDevice, MacCtrl.Mode, + pDevice-> + MacMode | MAC_MODE_SEND_CONFIGS); + + MM_Wait (20); + + pDevice->AnInfo.State = AN_STATE_UNKNOWN; + pDevice->AnInfo.CurrentTime_us = 0; + + REG_WR (pDevice, Grc.Timer, 0); + for (k = 0; + (pDevice->AnInfo.CurrentTime_us < 75000) + && (k < 75000); k++) { + AnStatus = + Autoneg8023z (&pDevice->AnInfo); + + if ((AnStatus == AUTONEG_STATUS_DONE) || + (AnStatus == AUTONEG_STATUS_FAILED)) + { + break; + } + + pDevice->AnInfo.CurrentTime_us = + REG_RD (pDevice, Grc.Timer); + + } + if ((AnStatus == AUTONEG_STATUS_DONE) || + (AnStatus == AUTONEG_STATUS_FAILED)) { + break; + } + if (j >= 1) { + if (!(REG_RD (pDevice, MacCtrl.Status) & + MAC_STATUS_PCS_SYNCED)) { + break; + } + } + } - LocalPhyAd = 0; - if(pDevice->AnInfo.mr_adv_sym_pause) - { - LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE; + /* Stop sending configs. */ + MM_AnTxIdle (&pDevice->AnInfo); + + /* Resolve flow control settings. */ + if ((AnStatus == AUTONEG_STATUS_DONE) && + pDevice->AnInfo.mr_an_complete + && pDevice->AnInfo.mr_link_ok + && pDevice->AnInfo.mr_lp_adv_full_duplex) { + LM_UINT32 RemotePhyAd; + LM_UINT32 LocalPhyAd; + + LocalPhyAd = 0; + if (pDevice->AnInfo.mr_adv_sym_pause) { + LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE; + } + + if (pDevice->AnInfo.mr_adv_asym_pause) { + LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE; + } + + RemotePhyAd = 0; + if (pDevice->AnInfo.mr_lp_adv_sym_pause) { + RemotePhyAd |= + PHY_LINK_PARTNER_PAUSE_CAPABLE; + } + + if (pDevice->AnInfo.mr_lp_adv_asym_pause) { + RemotePhyAd |= + PHY_LINK_PARTNER_ASYM_PAUSE; + } + + LM_SetFlowControl (pDevice, LocalPhyAd, + RemotePhyAd); + + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + for (j = 0; j < 30; j++) { + MM_Wait (20); + REG_WR (pDevice, MacCtrl.Status, + MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MM_Wait (20); + if ((REG_RD (pDevice, MacCtrl.Status) & + (MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED)) == 0) + break; + } + if (pDevice->PollTbiLink) { + Value32 = REG_RD (pDevice, MacCtrl.Status); + if (Value32 & MAC_STATUS_RECEIVING_CFG) { + pDevice->IgnoreTbiLinkChange = TRUE; + } else { + pDevice->IgnoreTbiLinkChange = FALSE; + } + } + Value32 = REG_RD (pDevice, MacCtrl.Status); + if (CurrentLinkStatus == LM_STATUS_LINK_DOWN && + (Value32 & MAC_STATUS_PCS_SYNCED) && + ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + } else { + /* We are forcing line speed. */ + pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; + LM_SetFlowControl (pDevice, 0, 0); + + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); } + } + /* Set the link polarity bit. */ + pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode); - if(pDevice->AnInfo.mr_adv_asym_pause) - { - LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE; - } + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | + (pDevice->pStatusBlkVirt-> + Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); - RemotePhyAd = 0; - if(pDevice->AnInfo.mr_lp_adv_sym_pause) - { - RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE; - } + for (j = 0; j < 100; j++) { + REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MM_Wait (5); + if ((REG_RD (pDevice, MacCtrl.Status) & + (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) + break; + } - if(pDevice->AnInfo.mr_lp_adv_asym_pause) - { - RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE; + Value32 = REG_RD (pDevice, MacCtrl.Status); + if ((Value32 & MAC_STATUS_PCS_SYNCED) == 0) { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + if (pDevice->DisableAutoNeg == FALSE) { + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + MM_Wait (1); + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode); } + } - LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); + /* Initialize the current link status. */ + if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) { + pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS; + pDevice->DuplexMode = LM_DUPLEX_MODE_FULL; + REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_1000MBPS_LED_ON); + } else { + pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN; + pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN; + REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_OVERRIDE_TRAFFIC_LED); + } - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - } - for (j = 0; j < 30; j++) - { - MM_Wait(20); - REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | - MAC_STATUS_CFG_CHANGED); - MM_Wait(20); - if ((REG_RD(pDevice, MacCtrl.Status) & - (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) - break; - } - if (pDevice->PollTbiLink) - { - Value32 = REG_RD(pDevice, MacCtrl.Status); - if (Value32 & MAC_STATUS_RECEIVING_CFG) - { - pDevice->IgnoreTbiLinkChange = TRUE; - } - else - { - pDevice->IgnoreTbiLinkChange = FALSE; - } - } - Value32 = REG_RD(pDevice, MacCtrl.Status); - if (CurrentLinkStatus == LM_STATUS_LINK_DOWN && - (Value32 & MAC_STATUS_PCS_SYNCED) && - ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) - { - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - } + /* Indicate link status. */ + if (pDevice->LinkStatus != CurrentLinkStatus) { + pDevice->LinkStatus = CurrentLinkStatus; + MM_IndicateStatus (pDevice, CurrentLinkStatus); } - else - { - /* We are forcing line speed. */ - pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; - LM_SetFlowControl(pDevice, 0, 0); - - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | - MAC_MODE_SEND_CONFIGS); - } - } - /* Set the link polarity bit. */ - pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); - - pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | - (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); - - for (j = 0; j < 100; j++) - { - REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | - MAC_STATUS_CFG_CHANGED); - MM_Wait(5); - if ((REG_RD(pDevice, MacCtrl.Status) & - (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) - break; - } - - Value32 = REG_RD(pDevice, MacCtrl.Status); - if((Value32 & MAC_STATUS_PCS_SYNCED) == 0) - { - CurrentLinkStatus = LM_STATUS_LINK_DOWN; - if (pDevice->DisableAutoNeg == FALSE) - { - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | - MAC_MODE_SEND_CONFIGS); - MM_Wait(1); - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); - } - } - - /* Initialize the current link status. */ - if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) - { - pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS; - pDevice->DuplexMode = LM_DUPLEX_MODE_FULL; - REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | - LED_CTRL_1000MBPS_LED_ON); - } - else - { - pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN; - pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN; - REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | - LED_CTRL_OVERRIDE_TRAFFIC_LED); - } - - /* Indicate link status. */ - if (pDevice->LinkStatus != CurrentLinkStatus) { - pDevice->LinkStatus = CurrentLinkStatus; - MM_IndicateStatus(pDevice, CurrentLinkStatus); - } - - return LM_STATUS_SUCCESS; -} -#endif /* INCLUDE_TBI_SUPPORT */ + return LM_STATUS_SUCCESS; +} +#endif /* INCLUDE_TBI_SUPPORT */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS -LM_SetupCopperPhy( - PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice) { - LM_STATUS CurrentLinkStatus; - LM_UINT32 Value32; + LM_STATUS CurrentLinkStatus; + LM_UINT32 Value32; - /* Assume there is not link first. */ - CurrentLinkStatus = LM_STATUS_LINK_DOWN; + /* Assume there is not link first. */ + CurrentLinkStatus = LM_STATUS_LINK_DOWN; - /* Disable phy link change attention. */ - REG_WR(pDevice, MacCtrl.MacEvent, 0); + /* Disable phy link change attention. */ + REG_WR (pDevice, MacCtrl.MacEvent, 0); - /* Clear link change attention. */ - REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | - MAC_STATUS_CFG_CHANGED); + /* Clear link change attention. */ + REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); - /* Disable auto-polling for the moment. */ - pDevice->MiMode = 0xc0000; - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - MM_Wait(40); + /* Disable auto-polling for the moment. */ + pDevice->MiMode = 0xc0000; + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait (40); - /* Determine the requested line speed and duplex. */ - pDevice->OldLineSpeed = pDevice->LineSpeed; - LM_TranslateRequestedMediaType(pDevice->RequestedMediaType, - &pDevice->MediaType, &pDevice->LineSpeed, &pDevice->DuplexMode); + /* Determine the requested line speed and duplex. */ + pDevice->OldLineSpeed = pDevice->LineSpeed; + LM_TranslateRequestedMediaType (pDevice->RequestedMediaType, + &pDevice->MediaType, + &pDevice->LineSpeed, + &pDevice->DuplexMode); - /* Initialize the phy chip. */ - switch(pDevice->PhyId & PHY_ID_MASK) - { + /* Initialize the phy chip. */ + switch (pDevice->PhyId & PHY_ID_MASK) { case PHY_BCM5400_PHY_ID: case PHY_BCM5401_PHY_ID: case PHY_BCM5411_PHY_ID: case PHY_BCM5701_PHY_ID: case PHY_BCM5703_PHY_ID: case PHY_BCM5704_PHY_ID: - CurrentLinkStatus = LM_InitBcm540xPhy(pDevice); - break; + CurrentLinkStatus = LM_InitBcm540xPhy (pDevice); + break; default: - break; - } - - if(CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH) - { - CurrentLinkStatus = LM_STATUS_LINK_DOWN; - } + break; + } - /* Setup flow control. */ - pDevice->FlowControl = LM_FLOW_CONTROL_NONE; - if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) - { - LM_FLOW_CONTROL FlowCap; /* Flow control capability. */ + if (CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH) { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + } + + /* Setup flow control. */ + pDevice->FlowControl = LM_FLOW_CONTROL_NONE; + if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) { + LM_FLOW_CONTROL FlowCap; /* Flow control capability. */ + + FlowCap = LM_FLOW_CONTROL_NONE; + + if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) { + if (pDevice->DisableAutoNeg == FALSE || + pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_AUTO + || pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) { + LM_UINT32 ExpectedPhyAd; + LM_UINT32 LocalPhyAd; + LM_UINT32 RemotePhyAd; + + LM_ReadPhy (pDevice, PHY_AN_AD_REG, + &LocalPhyAd); + pDevice->advertising = LocalPhyAd; + LocalPhyAd &= + (PHY_AN_AD_ASYM_PAUSE | + PHY_AN_AD_PAUSE_CAPABLE); + + ExpectedPhyAd = + GetPhyAdFlowCntrlSettings (pDevice); + + if (LocalPhyAd != ExpectedPhyAd) { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + } else { + LM_ReadPhy (pDevice, + PHY_LINK_PARTNER_ABILITY_REG, + &RemotePhyAd); + + LM_SetFlowControl (pDevice, LocalPhyAd, + RemotePhyAd); + } + } else { + pDevice->FlowControlCap &= + ~LM_FLOW_CONTROL_AUTO_PAUSE; + LM_SetFlowControl (pDevice, 0, 0); + } + } + } - FlowCap = LM_FLOW_CONTROL_NONE; + if (CurrentLinkStatus == LM_STATUS_LINK_DOWN) { + LM_ForceAutoNeg (pDevice, pDevice->RequestedMediaType); - if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) - { - if(pDevice->DisableAutoNeg == FALSE || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) - { - LM_UINT32 ExpectedPhyAd; - LM_UINT32 LocalPhyAd; - LM_UINT32 RemotePhyAd; + /* If we force line speed, we make get link right away. */ + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + if (Value32 & PHY_STATUS_LINK_PASS) { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + } - LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd); - pDevice->advertising = LocalPhyAd; - LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE); + /* GMII interface. */ + pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK; + if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) { + if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS || + pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) { + pDevice->MacMode |= MAC_MODE_PORT_MODE_MII; + } else { + pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; + } + } else { + pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; + } - ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice); + /* Set the MAC to operate in the appropriate duplex mode. */ + pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX; + if (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF) { + pDevice->MacMode |= MAC_MODE_HALF_DUPLEX; + } - if(LocalPhyAd != ExpectedPhyAd) - { - CurrentLinkStatus = LM_STATUS_LINK_DOWN; + /* Set the link polarity bit. */ + pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + if ((pDevice->LedMode == LED_MODE_LINK10) || + (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE && + pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) { + pDevice->MacMode |= MAC_MODE_LINK_POLARITY; + } + } else { + if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) { + pDevice->MacMode |= MAC_MODE_LINK_POLARITY; } - else - { - LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG, - &RemotePhyAd); - LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); + /* Set LED mode. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = LED_CTRL_PHY_MODE_1; + } else { + if (pDevice->LedMode == LED_MODE_OUTPUT) { + Value32 = LED_CTRL_PHY_MODE_2; + } else { + Value32 = LED_CTRL_PHY_MODE_1; + } } - } - else - { - pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; - LM_SetFlowControl(pDevice, 0, 0); - } + REG_WR (pDevice, MacCtrl.LedCtrl, Value32); } - } - if(CurrentLinkStatus == LM_STATUS_LINK_DOWN) - { - LM_ForceAutoNeg(pDevice, pDevice->RequestedMediaType); + REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode); - /* If we force line speed, we make get link right away. */ - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - if(Value32 & PHY_STATUS_LINK_PASS) - { - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + /* Enable auto polling. */ + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { + pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE; + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode); } - } - /* GMII interface. */ - pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK; - if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) - { - if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS || - pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) - { - pDevice->MacMode |= MAC_MODE_PORT_MODE_MII; - } - else - { - pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; - } - } - else { - pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; - } - - /* Set the MAC to operate in the appropriate duplex mode. */ - pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX; - if(pDevice->DuplexMode == LM_DUPLEX_MODE_HALF) - { - pDevice->MacMode |= MAC_MODE_HALF_DUPLEX; - } - - /* Set the link polarity bit. */ - pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - if((pDevice->LedMode == LED_MODE_LINK10) || - (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE && - pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) - { - pDevice->MacMode |= MAC_MODE_LINK_POLARITY; + /* Enable phy link change attention. */ + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) { + REG_WR (pDevice, MacCtrl.MacEvent, + MAC_EVENT_ENABLE_MI_INTERRUPT); + } else { + REG_WR (pDevice, MacCtrl.MacEvent, + MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); } - } - else - { - if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) - { - pDevice->MacMode |= MAC_MODE_LINK_POLARITY; + if ((T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) && + (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) && + (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && + (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) && + (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) || + !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) { + MM_Wait (120); + REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MEM_WR_OFFSET (pDevice, T3_FIRMWARE_MAILBOX, + T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE); } - /* Set LED mode. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = LED_CTRL_PHY_MODE_1; + /* Indicate link status. */ + if (pDevice->LinkStatus != CurrentLinkStatus) { + pDevice->LinkStatus = CurrentLinkStatus; + MM_IndicateStatus (pDevice, CurrentLinkStatus); } - else - { - if(pDevice->LedMode == LED_MODE_OUTPUT) - { - Value32 = LED_CTRL_PHY_MODE_2; - } - else - { - Value32 = LED_CTRL_PHY_MODE_1; - } - } - REG_WR(pDevice, MacCtrl.LedCtrl, Value32); - } - - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); - - /* Enable auto polling. */ - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) - { - pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE; - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - } - - /* Enable phy link change attention. */ - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) - { - REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT); - } - else - { - REG_WR(pDevice, MacCtrl.MacEvent, - MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); - } - if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) && - (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) && - (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && - (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) && - (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) || - !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) - { - MM_Wait(120); - REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | - MAC_STATUS_CFG_CHANGED); - MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX, - T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE); - } - - /* Indicate link status. */ - if (pDevice->LinkStatus != CurrentLinkStatus) { - pDevice->LinkStatus = CurrentLinkStatus; - MM_IndicateStatus(pDevice, CurrentLinkStatus); - } - - return LM_STATUS_SUCCESS; -} /* LM_SetupCopperPhy */ + + return LM_STATUS_SUCCESS; +} /* LM_SetupCopperPhy */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS -LM_SetupPhy( - PLM_DEVICE_BLOCK pDevice) +LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice) { - LM_STATUS LmStatus; - LM_UINT32 Value32; + LM_STATUS LmStatus; + LM_UINT32 Value32; #if INCLUDE_TBI_SUPPORT - if(pDevice->EnableTbi) - { - LmStatus = LM_SetupFiberPhy(pDevice); - } - else -#endif /* INCLUDE_TBI_SUPPORT */ - { - LmStatus = LM_SetupCopperPhy(pDevice); - } - if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) - { - if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) - { - Value32 = REG_RD(pDevice, PciCfg.PciState); - REG_WR(pDevice, PciCfg.PciState, - Value32 | T3_PCI_STATE_RETRY_SAME_DMA); - } - } - if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && - (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) - { - REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff); - } - else - { - REG_WR(pDevice, MacCtrl.TxLengths, 0x2620); - } - - return LmStatus; + if (pDevice->EnableTbi) { + LmStatus = LM_SetupFiberPhy (pDevice); + } else +#endif /* INCLUDE_TBI_SUPPORT */ + { + LmStatus = LM_SetupCopperPhy (pDevice); + } + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) { + Value32 = REG_RD (pDevice, PciCfg.PciState); + REG_WR (pDevice, PciCfg.PciState, + Value32 | T3_PCI_STATE_RETRY_SAME_DMA); + } + } + if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && + (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) { + REG_WR (pDevice, MacCtrl.TxLengths, 0x26ff); + } else { + REG_WR (pDevice, MacCtrl.TxLengths, 0x2620); + } + + return LmStatus; } /******************************************************************************/ @@ -5232,55 +4830,47 @@ LM_SetupPhy( /* Return: */ /******************************************************************************/ LM_VOID -LM_ReadPhy( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 PhyReg, -PLM_UINT32 pData32) { - LM_UINT32 Value32; - LM_UINT32 j; +LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, PLM_UINT32 pData32) +{ + LM_UINT32 Value32; + LM_UINT32 j; - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) - { - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode & - ~MI_MODE_AUTO_POLLING_ENABLE); - MM_Wait(40); - } + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode & + ~MI_MODE_AUTO_POLLING_ENABLE); + MM_Wait (40); + } - Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | - ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) | - MI_COM_CMD_READ | MI_COM_START; + Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | + ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << + MI_COM_FIRST_PHY_REG_ADDR_BIT) | MI_COM_CMD_READ | MI_COM_START; - REG_WR(pDevice, MacCtrl.MiCom, Value32); + REG_WR (pDevice, MacCtrl.MiCom, Value32); - for(j = 0; j < 20; j++) - { - MM_Wait(25); + for (j = 0; j < 20; j++) { + MM_Wait (25); - Value32 = REG_RD(pDevice, MacCtrl.MiCom); + Value32 = REG_RD (pDevice, MacCtrl.MiCom); - if(!(Value32 & MI_COM_BUSY)) - { - MM_Wait(5); - Value32 = REG_RD(pDevice, MacCtrl.MiCom); - Value32 &= MI_COM_PHY_DATA_MASK; - break; + if (!(Value32 & MI_COM_BUSY)) { + MM_Wait (5); + Value32 = REG_RD (pDevice, MacCtrl.MiCom); + Value32 &= MI_COM_PHY_DATA_MASK; + break; + } } - } - if(Value32 & MI_COM_BUSY) - { - Value32 = 0; - } - - *pData32 = Value32; + if (Value32 & MI_COM_BUSY) { + Value32 = 0; + } - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) - { - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - MM_Wait(40); - } -} /* LM_ReadPhy */ + *pData32 = Value32; + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait (40); + } +} /* LM_ReadPhy */ /******************************************************************************/ /* Description: */ @@ -5288,341 +4878,296 @@ PLM_UINT32 pData32) { /* Return: */ /******************************************************************************/ LM_VOID -LM_WritePhy( -PLM_DEVICE_BLOCK pDevice, -LM_UINT32 PhyReg, -LM_UINT32 Data32) { - LM_UINT32 Value32; - LM_UINT32 j; +LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, LM_UINT32 Data32) +{ + LM_UINT32 Value32; + LM_UINT32 j; - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) - { - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode & - ~MI_MODE_AUTO_POLLING_ENABLE); - MM_Wait(40); - } + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode & + ~MI_MODE_AUTO_POLLING_ENABLE); + MM_Wait (40); + } - Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | - ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) | - (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START; + Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | + ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << + MI_COM_FIRST_PHY_REG_ADDR_BIT) | (Data32 & MI_COM_PHY_DATA_MASK) | + MI_COM_CMD_WRITE | MI_COM_START; - REG_WR(pDevice, MacCtrl.MiCom, Value32); + REG_WR (pDevice, MacCtrl.MiCom, Value32); - for(j = 0; j < 20; j++) - { - MM_Wait(25); + for (j = 0; j < 20; j++) { + MM_Wait (25); - Value32 = REG_RD(pDevice, MacCtrl.MiCom); + Value32 = REG_RD (pDevice, MacCtrl.MiCom); - if(!(Value32 & MI_COM_BUSY)) - { - MM_Wait(5); - break; + if (!(Value32 & MI_COM_BUSY)) { + MM_Wait (5); + break; + } } - } - - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) - { - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - MM_Wait(40); - } -} /* LM_WritePhy */ + if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { + REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait (40); + } +} /* LM_WritePhy */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS -LM_SetPowerState( -PLM_DEVICE_BLOCK pDevice, -LM_POWER_STATE PowerLevel) { - LM_UINT32 PmeSupport; - LM_UINT32 Value32; - LM_UINT32 PmCtrl; +LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel) +{ + LM_UINT32 PmeSupport; + LM_UINT32 Value32; + LM_UINT32 PmCtrl; - /* make sureindirect accesses are enabled*/ - MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl); + /* make sureindirect accesses are enabled */ + MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, + pDevice->MiscHostCtrl); - /* Clear the PME_ASSERT bit and the power state bits. Also enable */ - /* the PME bit. */ - MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl); + /* Clear the PME_ASSERT bit and the power state bits. Also enable */ + /* the PME bit. */ + MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl); - PmCtrl |= T3_PM_PME_ASSERTED; - PmCtrl &= ~T3_PM_POWER_STATE_MASK; + PmCtrl |= T3_PM_PME_ASSERTED; + PmCtrl &= ~T3_PM_POWER_STATE_MASK; - /* Set the appropriate power state. */ - if(PowerLevel == LM_POWER_STATE_D0) - { + /* Set the appropriate power state. */ + if (PowerLevel == LM_POWER_STATE_D0) { - /* Bring the card out of low power mode. */ - PmCtrl |= T3_PM_POWER_STATE_D0; - MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); + /* Bring the card out of low power mode. */ + PmCtrl |= T3_PM_POWER_STATE_D0; + MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); - MM_Wait (40); -#if 0 /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */ - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02); + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); + MM_Wait (40); +#if 0 /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */ + LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x02); #endif - return LM_STATUS_SUCCESS; - } - else if(PowerLevel == LM_POWER_STATE_D1) - { - PmCtrl |= T3_PM_POWER_STATE_D1; - } - else if(PowerLevel == LM_POWER_STATE_D2) - { - PmCtrl |= T3_PM_POWER_STATE_D2; - } - else if(PowerLevel == LM_POWER_STATE_D3) - { - PmCtrl |= T3_PM_POWER_STATE_D3; - } - else - { - return LM_STATUS_FAILURE; - } - PmCtrl |= T3_PM_PME_ENABLE; - - /* Mask out all interrupts so LM_SetupPhy won't be called while we are */ - /* setting new line speed. */ - Value32 = REG_RD(pDevice, PciCfg.MiscHostCtrl); - REG_WR(pDevice, PciCfg.MiscHostCtrl, Value32 | MISC_HOST_CTRL_MASK_PCI_INT); - - if(!pDevice->RestoreOnWakeUp) - { - pDevice->RestoreOnWakeUp = TRUE; - pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg; - pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType; - } - - /* Force auto-negotiation to 10 line speed. */ - pDevice->DisableAutoNeg = FALSE; - pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS; - LM_SetupPhy(pDevice); - - /* Put the driver in the initial state, and go through the power down */ - /* sequence. */ - LM_Halt(pDevice); - - MM_ReadConfig32(pDevice, T3_PCI_PM_CAP_REG, &PmeSupport); - - if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) - { - - /* Enable WOL. */ - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a); - MM_Wait(40); - - /* Set LED mode. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = LED_CTRL_PHY_MODE_1; - } - else - { - if(pDevice->LedMode == LED_MODE_OUTPUT) - { - Value32 = LED_CTRL_PHY_MODE_2; - } - else - { - Value32 = LED_CTRL_PHY_MODE_1; - } + return LM_STATUS_SUCCESS; + } else if (PowerLevel == LM_POWER_STATE_D1) { + PmCtrl |= T3_PM_POWER_STATE_D1; + } else if (PowerLevel == LM_POWER_STATE_D2) { + PmCtrl |= T3_PM_POWER_STATE_D2; + } else if (PowerLevel == LM_POWER_STATE_D3) { + PmCtrl |= T3_PM_POWER_STATE_D3; + } else { + return LM_STATUS_FAILURE; } + PmCtrl |= T3_PM_PME_ENABLE; - Value32 = MAC_MODE_PORT_MODE_MII; - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - if(pDevice->LedMode == LED_MODE_LINK10 || - pDevice->WolSpeed == WOL_SPEED_10MB) - { - Value32 |= MAC_MODE_LINK_POLARITY; - } - } - else - { - Value32 |= MAC_MODE_LINK_POLARITY; - } - REG_WR(pDevice, MacCtrl.Mode, Value32); - MM_Wait(40); MM_Wait(40); MM_Wait(40); + /* Mask out all interrupts so LM_SetupPhy won't be called while we are */ + /* setting new line speed. */ + Value32 = REG_RD (pDevice, PciCfg.MiscHostCtrl); + REG_WR (pDevice, PciCfg.MiscHostCtrl, + Value32 | MISC_HOST_CTRL_MASK_PCI_INT); - /* Always enable magic packet wake-up if we have vaux. */ - if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) && - (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) - { - Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE; + if (!pDevice->RestoreOnWakeUp) { + pDevice->RestoreOnWakeUp = TRUE; + pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg; + pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType; } - REG_WR(pDevice, MacCtrl.Mode, Value32); + /* Force auto-negotiation to 10 line speed. */ + pDevice->DisableAutoNeg = FALSE; + pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS; + LM_SetupPhy (pDevice); - /* Enable the receiver. */ - REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE); - } - - /* Disable tx/rx clocks, and seletect an alternate clock. */ - if(pDevice->WolSpeed == WOL_SPEED_100MB) - { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | - T3_PCI_SELECT_ALTERNATE_CLOCK; - } - else - { - Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK; - } - REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + /* Put the driver in the initial state, and go through the power down */ + /* sequence. */ + LM_Halt (pDevice); - MM_Wait(40); + MM_ReadConfig32 (pDevice, T3_PCI_PM_CAP_REG, &PmeSupport); - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | - T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK; - } - else - { - Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | - T3_PCI_44MHZ_CORE_CLOCK; - } + if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) { - REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + /* Enable WOL. */ + LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x5a); + MM_Wait (40); - MM_Wait(40); + /* Set LED mode. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = LED_CTRL_PHY_MODE_1; + } else { + if (pDevice->LedMode == LED_MODE_OUTPUT) { + Value32 = LED_CTRL_PHY_MODE_2; + } else { + Value32 = LED_CTRL_PHY_MODE_1; + } + } - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | - T3_PCI_44MHZ_CORE_CLOCK; - } - else - { - Value32 = T3_PCI_44MHZ_CORE_CLOCK; - } + Value32 = MAC_MODE_PORT_MODE_MII; + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) { + if (pDevice->LedMode == LED_MODE_LINK10 || + pDevice->WolSpeed == WOL_SPEED_10MB) { + Value32 |= MAC_MODE_LINK_POLARITY; + } + } else { + Value32 |= MAC_MODE_LINK_POLARITY; + } + REG_WR (pDevice, MacCtrl.Mode, Value32); + MM_Wait (40); + MM_Wait (40); + MM_Wait (40); + + /* Always enable magic packet wake-up if we have vaux. */ + if ((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) && + (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) { + Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE; + } - REG_WR(pDevice, PciCfg.ClockCtrl, Value32); - } - else - { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | - T3_PCI_SELECT_ALTERNATE_CLOCK | - T3_PCI_POWER_DOWN_PCI_PLL133; - } - else - { - Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | - T3_PCI_POWER_DOWN_PCI_PLL133; + REG_WR (pDevice, MacCtrl.Mode, Value32); + + /* Enable the receiver. */ + REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_ENABLE); } - REG_WR(pDevice, PciCfg.ClockCtrl, Value32); - } + /* Disable tx/rx clocks, and seletect an alternate clock. */ + if (pDevice->WolSpeed == WOL_SPEED_100MB) { + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = + T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK; + } else { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK; + } + REG_WR (pDevice, PciCfg.ClockCtrl, Value32); + + MM_Wait (40); + + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = + T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_44MHZ_CORE_CLOCK; + } else { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_44MHZ_CORE_CLOCK; + } + + REG_WR (pDevice, PciCfg.ClockCtrl, Value32); - MM_Wait(40); + MM_Wait (40); - if(!pDevice->EepromWp && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)) - { - /* Switch adapter to auxilliary power. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_GPIO_OE0 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE2 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); - MM_Wait(40); + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = + T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_44MHZ_CORE_CLOCK; + } else { + Value32 = T3_PCI_44MHZ_CORE_CLOCK; + } + + REG_WR (pDevice, PciCfg.ClockCtrl, Value32); + } else { + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + Value32 = + T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_POWER_DOWN_PCI_PLL133; + } else { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_POWER_DOWN_PCI_PLL133; + } + + REG_WR (pDevice, PciCfg.ClockCtrl, Value32); } - else - { - /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */ - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_GPIO_OE0 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE2 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); - MM_Wait(40); - - /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */ - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_GPIO_OE0 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE2 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); - MM_Wait(40); - - /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_GPIO_OE0 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE2 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); - MM_Wait(40); - } - } - - /* Set the phy to low power mode. */ - /* Put the the hardware in low power mode. */ - MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); - - return LM_STATUS_SUCCESS; -} /* LM_SetPowerState */ + MM_Wait (40); + + if (!pDevice->EepromWp + && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)) { + /* Switch adapter to auxilliary power. */ + if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); + MM_Wait (40); + } else { + /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */ + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); + MM_Wait (40); + + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */ + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); + MM_Wait (40); + + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ + REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); + MM_Wait (40); + } + } + + /* Set the phy to low power mode. */ + /* Put the the hardware in low power mode. */ + MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); + + return LM_STATUS_SUCCESS; +} /* LM_SetPowerState */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -static LM_UINT32 -GetPhyAdFlowCntrlSettings( - PLM_DEVICE_BLOCK pDevice) +static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice) { - LM_UINT32 Value32; - - Value32 = 0; - - /* Auto negotiation flow control only when autonegotiation is enabled. */ - if(pDevice->DisableAutoNeg == FALSE || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) - { - /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */ - if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) || - ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) && - (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) - { - Value32 |= PHY_AN_AD_PAUSE_CAPABLE; - } - else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) - { - Value32 |= PHY_AN_AD_ASYM_PAUSE; - } - else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) - { - Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE; + LM_UINT32 Value32; + + Value32 = 0; + + /* Auto negotiation flow control only when autonegotiation is enabled. */ + if (pDevice->DisableAutoNeg == FALSE || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) { + /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */ + if ((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) || + ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) + && (pDevice-> + FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) { + Value32 |= PHY_AN_AD_PAUSE_CAPABLE; + } else if (pDevice-> + FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) { + Value32 |= PHY_AN_AD_ASYM_PAUSE; + } else if (pDevice-> + FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) { + Value32 |= + PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE; + } } - } - return Value32; + return Value32; } - /******************************************************************************/ /* Description: */ /* */ @@ -5632,195 +5177,169 @@ GetPhyAdFlowCntrlSettings( /* */ /******************************************************************************/ static LM_STATUS -LM_ForceAutoNegBcm540xPhy( -PLM_DEVICE_BLOCK pDevice, -LM_REQUESTED_MEDIA_TYPE RequestedMediaType) +LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType) { - LM_MEDIA_TYPE MediaType; - LM_LINE_SPEED LineSpeed; - LM_DUPLEX_MODE DuplexMode; - LM_UINT32 NewPhyCtrl; - LM_UINT32 Value32; - LM_UINT32 Cnt; - - /* Get the interface type, line speed, and duplex mode. */ - LM_TranslateRequestedMediaType(RequestedMediaType, &MediaType, &LineSpeed, - &DuplexMode); - - if (pDevice->RestoreOnWakeUp) - { - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); - pDevice->advertising1000 = 0; - Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF; - if (pDevice->WolSpeed == WOL_SPEED_100MB) - { - Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; - } - Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; - } - /* Setup the auto-negotiation advertisement register. */ - else if(LineSpeed == LM_LINE_SPEED_UNKNOWN) - { - /* Setup the 10/100 Mbps auto-negotiation advertisement register. */ - Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | - PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | - PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); - - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; - - /* Advertise 1000Mbps */ - Value32 = BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL; + LM_MEDIA_TYPE MediaType; + LM_LINE_SPEED LineSpeed; + LM_DUPLEX_MODE DuplexMode; + LM_UINT32 NewPhyCtrl; + LM_UINT32 Value32; + LM_UINT32 Cnt; + + /* Get the interface type, line speed, and duplex mode. */ + LM_TranslateRequestedMediaType (RequestedMediaType, &MediaType, + &LineSpeed, &DuplexMode); + + if (pDevice->RestoreOnWakeUp) { + LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; + Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF; + if (pDevice->WolSpeed == WOL_SPEED_100MB) { + Value32 |= + PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + } + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings (pDevice); + LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + } + /* Setup the auto-negotiation advertisement register. */ + else if (LineSpeed == LM_LINE_SPEED_UNKNOWN) { + /* Setup the 10/100 Mbps auto-negotiation advertisement register. */ + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | + PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | + PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + Value32 |= GetPhyAdFlowCntrlSettings (pDevice); + + LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + + /* Advertise 1000Mbps */ + Value32 = + BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL; #if INCLUDE_5701_AX_FIX - /* Bug: workaround for CRC error in gigabit mode when we are in */ - /* slave mode. This will force the PHY to operate in */ - /* master mode. */ - if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0) - { - Value32 |= BCM540X_CONFIG_AS_MASTER | - BCM540X_ENABLE_CONFIG_AS_MASTER; - } + /* Bug: workaround for CRC error in gigabit mode when we are in */ + /* slave mode. This will force the PHY to operate in */ + /* master mode. */ + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) { + Value32 |= BCM540X_CONFIG_AS_MASTER | + BCM540X_ENABLE_CONFIG_AS_MASTER; + } #endif - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); - pDevice->advertising1000 = Value32; - } - else - { - if(LineSpeed == LM_LINE_SPEED_1000MBPS) - { - Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, Value32); + pDevice->advertising1000 = Value32; + } else { + if (LineSpeed == LM_LINE_SPEED_1000MBPS) { + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings (pDevice); + + LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + + if (DuplexMode != LM_DUPLEX_MODE_FULL) { + Value32 = BCM540X_AN_AD_1000BASET_HALF; + } else { + Value32 = BCM540X_AN_AD_1000BASET_FULL; + } - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; + LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, + Value32); + pDevice->advertising1000 = Value32; + } else if (LineSpeed == LM_LINE_SPEED_100MBPS) { + LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; + + if (DuplexMode != LM_DUPLEX_MODE_FULL) { + Value32 = PHY_AN_AD_100BASETX_HALF; + } else { + Value32 = PHY_AN_AD_100BASETX_FULL; + } - if(DuplexMode != LM_DUPLEX_MODE_FULL) - { - Value32 = BCM540X_AN_AD_1000BASET_HALF; - } - else - { - Value32 = BCM540X_AN_AD_1000BASET_FULL; - } + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings (pDevice); - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); - pDevice->advertising1000 = Value32; - } - else if(LineSpeed == LM_LINE_SPEED_100MBPS) - { - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); - pDevice->advertising1000 = 0; + LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + } else if (LineSpeed == LM_LINE_SPEED_10MBPS) { + LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; - if(DuplexMode != LM_DUPLEX_MODE_FULL) - { - Value32 = PHY_AN_AD_100BASETX_HALF; - } - else - { - Value32 = PHY_AN_AD_100BASETX_FULL; - } + if (DuplexMode != LM_DUPLEX_MODE_FULL) { + Value32 = PHY_AN_AD_10BASET_HALF; + } else { + Value32 = PHY_AN_AD_10BASET_FULL; + } - Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings (pDevice); - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; - } - else if(LineSpeed == LM_LINE_SPEED_10MBPS) - { - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); - pDevice->advertising1000 = 0; - - if(DuplexMode != LM_DUPLEX_MODE_FULL) - { - Value32 = PHY_AN_AD_10BASET_HALF; - } - else - { - Value32 = PHY_AN_AD_10BASET_FULL; - } - - Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); - - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; - } - } - - /* Force line speed if auto-negotiation is disabled. */ - if(pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN) - { - /* This code path is executed only when there is link. */ - pDevice->MediaType = MediaType; - pDevice->LineSpeed = LineSpeed; - pDevice->DuplexMode = DuplexMode; - - /* Force line seepd. */ - NewPhyCtrl = 0; - switch(LineSpeed) - { - case LM_LINE_SPEED_10MBPS: - NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS; - break; - case LM_LINE_SPEED_100MBPS: - NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS; - break; - case LM_LINE_SPEED_1000MBPS: - NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; - break; - default: - NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; - break; + LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + } } - if(DuplexMode == LM_DUPLEX_MODE_FULL) - { - NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE; - } + /* Force line speed if auto-negotiation is disabled. */ + if (pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN) { + /* This code path is executed only when there is link. */ + pDevice->MediaType = MediaType; + pDevice->LineSpeed = LineSpeed; + pDevice->DuplexMode = DuplexMode; - /* Don't do anything if the PHY_CTRL is already what we wanted. */ - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if(Value32 != NewPhyCtrl) - { - /* Temporary bring the link down before forcing line speed. */ - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE); + /* Force line seepd. */ + NewPhyCtrl = 0; + switch (LineSpeed) { + case LM_LINE_SPEED_10MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS; + break; + case LM_LINE_SPEED_100MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS; + break; + case LM_LINE_SPEED_1000MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; + break; + default: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; + break; + } - /* Wait for link to go down. */ - for(Cnt = 0; Cnt < 15000; Cnt++) - { - MM_Wait(10); + if (DuplexMode == LM_DUPLEX_MODE_FULL) { + NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE; + } - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + /* Don't do anything if the PHY_CTRL is already what we wanted. */ + LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32); + if (Value32 != NewPhyCtrl) { + /* Temporary bring the link down before forcing line speed. */ + LM_WritePhy (pDevice, PHY_CTRL_REG, + PHY_CTRL_LOOPBACK_MODE); - if(!(Value32 & PHY_STATUS_LINK_PASS)) - { - MM_Wait(40); - break; - } - } + /* Wait for link to go down. */ + for (Cnt = 0; Cnt < 15000; Cnt++) { + MM_Wait (10); - LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl); - MM_Wait(40); - } - } - else - { - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | - PHY_CTRL_RESTART_AUTO_NEG); - } + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32); + + if (!(Value32 & PHY_STATUS_LINK_PASS)) { + MM_Wait (40); + break; + } + } - return LM_STATUS_SUCCESS; -} /* LM_ForceAutoNegBcm540xPhy */ + LM_WritePhy (pDevice, PHY_CTRL_REG, NewPhyCtrl); + MM_Wait (40); + } + } else { + LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); + } + return LM_STATUS_SUCCESS; +} /* LM_ForceAutoNegBcm540xPhy */ /******************************************************************************/ /* Description: */ @@ -5828,218 +5347,199 @@ LM_REQUESTED_MEDIA_TYPE RequestedMediaType) /* Return: */ /******************************************************************************/ static LM_STATUS -LM_ForceAutoNeg( -PLM_DEVICE_BLOCK pDevice, -LM_REQUESTED_MEDIA_TYPE RequestedMediaType) +LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType) { - LM_STATUS LmStatus; + LM_STATUS LmStatus; - /* Initialize the phy chip. */ - switch(pDevice->PhyId & PHY_ID_MASK) - { + /* Initialize the phy chip. */ + switch (pDevice->PhyId & PHY_ID_MASK) { case PHY_BCM5400_PHY_ID: case PHY_BCM5401_PHY_ID: case PHY_BCM5411_PHY_ID: case PHY_BCM5701_PHY_ID: case PHY_BCM5703_PHY_ID: case PHY_BCM5704_PHY_ID: - LmStatus = LM_ForceAutoNegBcm540xPhy(pDevice, RequestedMediaType); - break; + LmStatus = + LM_ForceAutoNegBcm540xPhy (pDevice, RequestedMediaType); + break; default: - LmStatus = LM_STATUS_FAILURE; - break; - } + LmStatus = LM_STATUS_FAILURE; + break; + } - return LmStatus; -} /* LM_ForceAutoNeg */ + return LmStatus; +} /* LM_ForceAutoNeg */ /******************************************************************************/ /* Description: */ /* */ /* Return: */ /******************************************************************************/ -LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice, - PT3_FWIMG_INFO pFwImg, - LM_UINT32 LoadCpu, - LM_UINT32 StartCpu) +LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice, + PT3_FWIMG_INFO pFwImg, + LM_UINT32 LoadCpu, LM_UINT32 StartCpu) { - LM_UINT32 i; - LM_UINT32 address; + LM_UINT32 i; + LM_UINT32 address; - if (LoadCpu & T3_RX_CPU_ID) - { - if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS) - { - return LM_STATUS_FAILURE; - } + if (LoadCpu & T3_RX_CPU_ID) { + if (LM_HaltCpu (pDevice, T3_RX_CPU_ID) != LM_STATUS_SUCCESS) { + return LM_STATUS_FAILURE; + } - /* First of all clear scrach pad memory */ - for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i+=4) - { - LM_RegWrInd(pDevice,T3_RX_CPU_SPAD_ADDR+i,0); - } + /* First of all clear scrach pad memory */ + for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i += 4) { + LM_RegWrInd (pDevice, T3_RX_CPU_SPAD_ADDR + i, 0); + } - /* Copy code first */ - address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); - for (i = 0; i <= pFwImg->Text.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]); - } + /* Copy code first */ + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); + for (i = 0; i <= pFwImg->Text.Length; i += 4) { + LM_RegWrInd (pDevice, address + i, + ((LM_UINT32 *) pFwImg->Text.Buffer)[i / + 4]); + } - address = T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); - for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]); - } + address = + T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); + for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) { + LM_RegWrInd (pDevice, address + i, + ((LM_UINT32 *) pFwImg->ROnlyData. + Buffer)[i / 4]); + } - address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); - for (i= 0; i <= pFwImg->Data.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]); + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); + for (i = 0; i <= pFwImg->Data.Length; i += 4) { + LM_RegWrInd (pDevice, address + i, + ((LM_UINT32 *) pFwImg->Data.Buffer)[i / + 4]); + } } - } - if (LoadCpu & T3_TX_CPU_ID) - { - if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS) - { - return LM_STATUS_FAILURE; - } + if (LoadCpu & T3_TX_CPU_ID) { + if (LM_HaltCpu (pDevice, T3_TX_CPU_ID) != LM_STATUS_SUCCESS) { + return LM_STATUS_FAILURE; + } - /* First of all clear scrach pad memory */ - for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4) - { - LM_RegWrInd(pDevice,T3_TX_CPU_SPAD_ADDR+i,0); - } + /* First of all clear scrach pad memory */ + for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i += 4) { + LM_RegWrInd (pDevice, T3_TX_CPU_SPAD_ADDR + i, 0); + } - /* Copy code first */ - address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); - for (i= 0; i <= pFwImg->Text.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]); - } + /* Copy code first */ + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); + for (i = 0; i <= pFwImg->Text.Length; i += 4) { + LM_RegWrInd (pDevice, address + i, + ((LM_UINT32 *) pFwImg->Text.Buffer)[i / + 4]); + } - address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); - for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]); - } + address = + T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); + for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) { + LM_RegWrInd (pDevice, address + i, + ((LM_UINT32 *) pFwImg->ROnlyData. + Buffer)[i / 4]); + } - address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); - for (i= 0; i <= pFwImg->Data.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]); + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); + for (i = 0; i <= pFwImg->Data.Length; i += 4) { + LM_RegWrInd (pDevice, address + i, + ((LM_UINT32 *) pFwImg->Data.Buffer)[i / + 4]); + } } - } - if (StartCpu & T3_RX_CPU_ID) - { - /* Start Rx CPU */ - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress); - for (i = 0 ; i < 5; i++) - { - if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC)) - break; + if (StartCpu & T3_RX_CPU_ID) { + /* Start Rx CPU */ + REG_WR (pDevice, rxCpu.reg.state, 0xffffffff); + REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress); + for (i = 0; i < 5; i++) { + if (pFwImg->StartAddress == + REG_RD (pDevice, rxCpu.reg.PC)) + break; + + REG_WR (pDevice, rxCpu.reg.state, 0xffffffff); + REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT); + REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress); + MM_Wait (1000); + } - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); - REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress); - MM_Wait(1000); + REG_WR (pDevice, rxCpu.reg.state, 0xffffffff); + REG_WR (pDevice, rxCpu.reg.mode, 0); } - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.mode, 0); - } + if (StartCpu & T3_TX_CPU_ID) { + /* Start Tx CPU */ + REG_WR (pDevice, txCpu.reg.state, 0xffffffff); + REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress); + for (i = 0; i < 5; i++) { + if (pFwImg->StartAddress == + REG_RD (pDevice, txCpu.reg.PC)) + break; - if (StartCpu & T3_TX_CPU_ID) - { - /* Start Tx CPU */ - REG_WR(pDevice,txCpu.reg.state, 0xffffffff); - REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress); - for (i = 0 ; i < 5; i++) - { - if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC)) - break; + REG_WR (pDevice, txCpu.reg.state, 0xffffffff); + REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT); + REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress); + MM_Wait (1000); + } - REG_WR(pDevice,txCpu.reg.state, 0xffffffff); - REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT); - REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress); - MM_Wait(1000); + REG_WR (pDevice, txCpu.reg.state, 0xffffffff); + REG_WR (pDevice, txCpu.reg.mode, 0); } - REG_WR(pDevice,txCpu.reg.state, 0xffffffff); - REG_WR(pDevice,txCpu.reg.mode, 0); - } - - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } -STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number) +STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number) { - LM_UINT32 i; + LM_UINT32 i; - if (cpu_number == T3_RX_CPU_ID) - { - for (i = 0 ; i < 10000; i++) - { - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); + if (cpu_number == T3_RX_CPU_ID) { + for (i = 0; i < 10000; i++) { + REG_WR (pDevice, rxCpu.reg.state, 0xffffffff); + REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT); - if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT) - break; - } + if (REG_RD (pDevice, rxCpu.reg.mode) & CPU_MODE_HALT) + break; + } - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); - MM_Wait(10); - } - else - { - for (i = 0 ; i < 10000; i++) - { - REG_WR(pDevice,txCpu.reg.state, 0xffffffff); - REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT); + REG_WR (pDevice, rxCpu.reg.state, 0xffffffff); + REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT); + MM_Wait (10); + } else { + for (i = 0; i < 10000; i++) { + REG_WR (pDevice, txCpu.reg.state, 0xffffffff); + REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT); - if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT) - break; + if (REG_RD (pDevice, txCpu.reg.mode) & CPU_MODE_HALT) + break; + } } - } - return (( i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS); + return ((i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS); } - -int -LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec) +int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec) { LM_UINT32 Oldcfg; int j; int ret = 0; - if(BlinkDurationSec == 0) - { + if (BlinkDurationSec == 0) { return 0; } - if(BlinkDurationSec > 120) - { + if (BlinkDurationSec > 120) { BlinkDurationSec = 120; } - Oldcfg = REG_RD(pDevice, MacCtrl.LedCtrl); - for(j = 0; j < BlinkDurationSec * 2; j++) - { - if(j % 2) - { + Oldcfg = REG_RD (pDevice, MacCtrl.LedCtrl); + for (j = 0; j < BlinkDurationSec * 2; j++) { + if (j % 2) { /* Turn on the LEDs. */ - REG_WR(pDevice, MacCtrl.LedCtrl, + REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | LED_CTRL_1000MBPS_LED_ON | LED_CTRL_100MBPS_LED_ON | @@ -6047,154 +5547,152 @@ LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec) LED_CTRL_OVERRIDE_TRAFFIC_LED | LED_CTRL_BLINK_TRAFFIC_LED | LED_CTRL_TRAFFIC_LED); - } - else - { + } else { /* Turn off the LEDs. */ - REG_WR(pDevice, MacCtrl.LedCtrl, + REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | LED_CTRL_OVERRIDE_TRAFFIC_LED); } #ifndef EMBEDDED current->state = TASK_INTERRUPTIBLE; - if (schedule_timeout(HZ/2) != 0) { + if (schedule_timeout (HZ / 2) != 0) { ret = -EINTR; break; } #else - udelay(100000); /* 1s sleep */ + udelay (100000); /* 1s sleep */ #endif } - REG_WR(pDevice, MacCtrl.LedCtrl, Oldcfg); + REG_WR (pDevice, MacCtrl.LedCtrl, Oldcfg); return ret; } -int t3_do_dma(PLM_DEVICE_BLOCK pDevice, - LM_PHYSICAL_ADDRESS host_addr_phy, int length, - int dma_read) +int t3_do_dma (PLM_DEVICE_BLOCK pDevice, + LM_PHYSICAL_ADDRESS host_addr_phy, int length, int dma_read) { - T3_DMA_DESC dma_desc; - int i; - LM_UINT32 dma_desc_addr; - LM_UINT32 value32; - - REG_WR(pDevice, BufMgr.Mode, 0); - REG_WR(pDevice, Ftq.Reset, 0); - - dma_desc.host_addr.High = host_addr_phy.High; - dma_desc.host_addr.Low = host_addr_phy.Low; - dma_desc.nic_mbuf = 0x2100; - dma_desc.len = length; - dma_desc.flags = 0x00000004; /* Generate Rx-CPU event */ - - if (dma_read) - { - dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) | - T3_QID_DMA_HIGH_PRI_READ; - REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE); - } - else - { - dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) | - T3_QID_DMA_HIGH_PRI_WRITE; - REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE); - } - - dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR; - - /* Writing this DMA descriptor to DMA memory */ - for (i = 0; i < sizeof(T3_DMA_DESC); i += 4) - { - value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i)); - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i); - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, cpu_to_le32(value32)); - } - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0); - - if (dma_read) - REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr); - else - REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr); - - for (i = 0; i < 40; i++) - { + T3_DMA_DESC dma_desc; + int i; + LM_UINT32 dma_desc_addr; + LM_UINT32 value32; + + REG_WR (pDevice, BufMgr.Mode, 0); + REG_WR (pDevice, Ftq.Reset, 0); + + dma_desc.host_addr.High = host_addr_phy.High; + dma_desc.host_addr.Low = host_addr_phy.Low; + dma_desc.nic_mbuf = 0x2100; + dma_desc.len = length; + dma_desc.flags = 0x00000004; /* Generate Rx-CPU event */ + + if (dma_read) { + dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) | + T3_QID_DMA_HIGH_PRI_READ; + REG_WR (pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE); + } else { + dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) | + T3_QID_DMA_HIGH_PRI_WRITE; + REG_WR (pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE); + } + + dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR; + + /* Writing this DMA descriptor to DMA memory */ + for (i = 0; i < sizeof (T3_DMA_DESC); i += 4) { + value32 = *((PLM_UINT32) (((PLM_UINT8) & dma_desc) + i)); + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, + dma_desc_addr + i); + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, + cpu_to_le32 (value32)); + } + MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0); + if (dma_read) - value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue); + REG_WR (pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, + dma_desc_addr); else - value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue); + REG_WR (pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, + dma_desc_addr); + + for (i = 0; i < 40; i++) { + if (dma_read) + value32 = + REG_RD (pDevice, + Ftq.RcvBdCompFtqFifoEnqueueDequeue); + else + value32 = + REG_RD (pDevice, + Ftq.RcvDataCompFtqFifoEnqueueDequeue); - if ((value32 & 0xffff) == dma_desc_addr) - break; + if ((value32 & 0xffff) == dma_desc_addr) + break; - MM_Wait(10); - } + MM_Wait (10); + } - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } STATIC LM_STATUS -LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, - LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize) +LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, + LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize) { - int j; - LM_UINT32 *ptr; - int dma_success = 0; + int j; + LM_UINT32 *ptr; + int dma_success = 0; + + if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) { + return LM_STATUS_SUCCESS; + } + while (!dma_success) { + /* Fill data with incremental patterns */ + ptr = (LM_UINT32 *) pBufferVirt; + for (j = 0; j < BufferSize / 4; j++) + *ptr++ = j; + + if (t3_do_dma (pDevice, BufferPhy, BufferSize, 1) == + LM_STATUS_FAILURE) { + return LM_STATUS_FAILURE; + } - if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && - T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) - { - return LM_STATUS_SUCCESS; - } - while (!dma_success) - { - /* Fill data with incremental patterns */ - ptr = (LM_UINT32 *)pBufferVirt; - for (j = 0; j < BufferSize/4; j++) - *ptr++ = j; - - if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE) - { - return LM_STATUS_FAILURE; - } + MM_Wait (40); + ptr = (LM_UINT32 *) pBufferVirt; + /* Fill data with zero */ + for (j = 0; j < BufferSize / 4; j++) + *ptr++ = 0; - MM_Wait(40); - ptr = (LM_UINT32 *)pBufferVirt; - /* Fill data with zero */ - for (j = 0; j < BufferSize/4; j++) - *ptr++ = 0; + if (t3_do_dma (pDevice, BufferPhy, BufferSize, 0) == + LM_STATUS_FAILURE) { + return LM_STATUS_FAILURE; + } - if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE) - { - return LM_STATUS_FAILURE; + MM_Wait (40); + /* Check for data */ + ptr = (LM_UINT32 *) pBufferVirt; + for (j = 0; j < BufferSize / 4; j++) { + if (*ptr++ != j) { + if ((pDevice-> + DmaReadWriteCtrl & + DMA_CTRL_WRITE_BOUNDARY_MASK) + == DMA_CTRL_WRITE_BOUNDARY_DISABLE) { + pDevice->DmaReadWriteCtrl = + (pDevice-> + DmaReadWriteCtrl & + ~DMA_CTRL_WRITE_BOUNDARY_MASK) | + DMA_CTRL_WRITE_BOUNDARY_16; + REG_WR (pDevice, + PciCfg.DmaReadWriteCtrl, + pDevice->DmaReadWriteCtrl); + break; + } else { + return LM_STATUS_FAILURE; + } + } + } + if (j == (BufferSize / 4)) + dma_success = 1; } - - MM_Wait(40); - /* Check for data */ - ptr = (LM_UINT32 *)pBufferVirt; - for (j = 0; j < BufferSize/4; j++) - { - if (*ptr++ != j) - { - if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK) - == DMA_CTRL_WRITE_BOUNDARY_DISABLE) - { - pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl & - ~DMA_CTRL_WRITE_BOUNDARY_MASK) | - DMA_CTRL_WRITE_BOUNDARY_16; - REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, - pDevice->DmaReadWriteCtrl); - break; - } - else - { - return LM_STATUS_FAILURE; - } - } - } - if (j == (BufferSize/4)) - dma_success = 1; - } - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } -#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_TIGON3 */ +#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_TIGON3 */ diff --git a/drivers/tigon3.h b/drivers/tigon3.h index ea4367d61d2..c03347fdc9b 100644 --- a/drivers/tigon3.h +++ b/drivers/tigon3.h @@ -21,7 +21,6 @@ #include "bcm570x_autoneg.h" #endif - /* io defines */ #if !defined(BIG_ENDIAN_HOST) #define readl(addr) \ @@ -29,7 +28,7 @@ #define writel(b,addr) \ ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b))) #else -#if 0 /* !defined(PPC603) */ +#if 0 /* !defined(PPC603) */ #define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr))) #define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b)) #else @@ -37,25 +36,28 @@ #define readl(addr) (*(volatile unsigned int*)(addr)) #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) #else -extern int sprintf(char* buf, const char* f, ...); -static __inline unsigned int readl(void* addr){ - char buf[128]; - unsigned int tmp = (*(volatile unsigned int*)(addr)); - sprintf(buf,"%s:%s: read 0x%x from 0x%x\n",__FILE__,__LINE__,tmp,addr,0,0); - sysSerialPrintString(buf); - return tmp; +extern int sprintf (char *buf, const char *f, ...); +static __inline unsigned int readl (void *addr) +{ + char buf[128]; + unsigned int tmp = (*(volatile unsigned int *)(addr)); + sprintf (buf, "%s:%s: read 0x%x from 0x%x\n", __FILE__, __LINE__, tmp, + addr, 0, 0); + sysSerialPrintString (buf); + return tmp; } -static __inline void writel(unsigned int b, unsigned int addr){ - char buf[128]; - ((*(volatile unsigned int *) (addr)) = (b)); - sprintf(buf,"%s:%s: write 0x%x to 0x%x\n",__FILE__,__LINE__,b,addr,0,0); - sysSerialPrintString(buf); +static __inline void writel (unsigned int b, unsigned int addr) +{ + char buf[128]; + ((*(volatile unsigned int *)(addr)) = (b)); + sprintf (buf, "%s:%s: write 0x%x to 0x%x\n", __FILE__, __LINE__, b, + addr, 0, 0); + sysSerialPrintString (buf); } #endif -#endif /* PPC603 */ +#endif /* PPC603 */ #endif - /******************************************************************************/ /* Constants. */ /******************************************************************************/ @@ -90,7 +92,7 @@ static __inline void writel(unsigned int b, unsigned int addr){ /* B0 bug. */ #define BCM5700_BX_MIN_FRAG_SIZE 10 -#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */ +#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */ #define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1) #define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \ MAX_FRAGMENT_COUNT) @@ -161,32 +163,32 @@ static __inline void writel(unsigned int b, unsigned int addr){ /* Number of entries in the Standard Receive RCB. Must be 512 entries. */ #define T3_STD_RCV_RCB_ENTRY_COUNT 512 #define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1) -#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */ +#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */ #define MAX_STD_RCV_BUFFER_SIZE 0x600 /* Number of entries in the Mini Receive RCB. This value can either be */ /* 0, 1024. Currently Mini Receive RCB is disabled. */ #ifndef T3_MINI_RCV_RCB_ENTRY_COUNT #define T3_MINI_RCV_RCB_ENTRY_COUNT 0 -#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */ +#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */ #define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1) #define MAX_MINI_RCV_BUFFER_SIZE 512 #define DEFAULT_MINI_RCV_BUFFER_SIZE 64 -#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */ +#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */ /* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */ /* Currently, Jumbo Receive RCB is disabled. */ #ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT #define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0 -#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ #define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1) -#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */ -#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */ -#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */ +#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */ +#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */ +#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */ -#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */ -#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */ +#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */ +#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */ /* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */ #define T3_MAX_RCV_RETURN_RCB_COUNT 16 @@ -195,10 +197,9 @@ static __inline void writel(unsigned int b, unsigned int addr){ /* or 2048. */ #ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT #define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024 -#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */ +#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */ #define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1) - /* Default coalescing parameters. */ #define DEFAULT_RX_COALESCING_TICKS 100 #define MAX_RX_COALESCING_TICKS 500 @@ -227,7 +228,6 @@ static __inline void writel(unsigned int b, unsigned int addr){ #define DEFAULT_STATS_COALESCING_TICKS 1000000 #define MAX_STATS_COALESCING_TICKS 3600000000U - /* Receive BD Replenish thresholds. */ #define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4 #define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4 @@ -240,12 +240,10 @@ static __inline void writel(unsigned int b, unsigned int addr){ /* Maximum physical fragment size. */ #define MAX_FRAGMENT_SIZE (64 * 1024) - /* Standard view. */ #define T3_STD_VIEW_SIZE (64 * 1024) #define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024) - /* Buffer descriptor base address on the NIC's memory. */ #define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000 @@ -265,19 +263,17 @@ static __inline void writel(unsigned int b, unsigned int addr){ #define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \ sizeof(T3_EXT_RCV_BD) / 4) - /* MBUF pool. */ #define T3_NIC_MBUF_POOL_ADDR 0x8000 /* #define T3_NIC_MBUF_POOL_SIZE 0x18000 */ #define T3_NIC_MBUF_POOL_SIZE96 0x18000 #define T3_NIC_MBUF_POOL_SIZE64 0x10000 - #define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000 /* DMA descriptor pool */ #define T3_NIC_DMA_DESC_POOL_ADDR 0x2000 -#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */ +#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */ #define T3_DEF_DMA_MBUF_LOW_WMARK 0x40 #define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20 @@ -301,24 +297,21 @@ static __inline void writel(unsigned int b, unsigned int addr){ #define T3_TX_CPU_SPAD_ADDR 0x34000 #define T3_TX_CPU_SPAD_SIZE 0x4000 -typedef struct T3_DIR_ENTRY -{ - PLM_UINT8 Buffer; - LM_UINT32 Offset; - LM_UINT32 Length; -} T3_DIR_ENTRY,*PT3_DIR_ENTRY; - -typedef struct T3_FWIMG_INFO -{ - LM_UINT32 StartAddress; - T3_DIR_ENTRY Text; - T3_DIR_ENTRY ROnlyData; - T3_DIR_ENTRY Data; - T3_DIR_ENTRY Sbss; - T3_DIR_ENTRY Bss; +typedef struct T3_DIR_ENTRY { + PLM_UINT8 Buffer; + LM_UINT32 Offset; + LM_UINT32 Length; +} T3_DIR_ENTRY, *PT3_DIR_ENTRY; + +typedef struct T3_FWIMG_INFO { + LM_UINT32 StartAddress; + T3_DIR_ENTRY Text; + T3_DIR_ENTRY ROnlyData; + T3_DIR_ENTRY Data; + T3_DIR_ENTRY Sbss; + T3_DIR_ENTRY Bss; } T3_FWIMG_INFO, *PT3_FWIMG_INFO; - /******************************************************************************/ /* Tigon3 PCI Registers. */ /******************************************************************************/ @@ -362,7 +355,6 @@ typedef struct T3_FWIMG_INFO #define T3_ASIC_REV_5703 0x01 #define T3_ASIC_REV_5704 0x02 - /* Chip id and revision. */ #define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8) #define T3_CHIP_REV_5700_AX 0x70 @@ -386,7 +378,6 @@ typedef struct T3_FWIMG_INFO #define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15 #define T3_PCI_44MHZ_CORE_CLOCK BIT_18 - #define T3_PCI_REG_ADDR_REG 0x78 #define T3_PCI_REG_DATA_REG 0x80 @@ -409,7 +400,6 @@ typedef struct T3_FWIMG_INFO #define T3_PM_PME_ENABLE BIT_8 #define T3_PM_PME_ASSERTED BIT_15 - /* PCI state register. */ #define T3_PCI_STATE_REG 0x70 @@ -419,17 +409,16 @@ typedef struct T3_FWIMG_INFO #define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3 #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 - /* Broadcom subsystem/subvendor IDs. */ #define T3_SVID_BROADCOM 0x14e4 #define T3_SSID_BROADCOM_BCM95700A6 0x1644 #define T3_SSID_BROADCOM_BCM95701A5 0x0001 -#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */ -#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */ +#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */ +#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */ #define T3_SSID_BROADCOM_BCM95701T1 0x0005 #define T3_SSID_BROADCOM_BCM95701T8 0x0006 -#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */ +#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */ #define T3_SSID_BROADCOM_BCM95701A10 0x0008 #define T3_SSID_BROADCOM_BCM95701A12 0x8008 #define T3_SSID_BROADCOM_BCM95703Ax1 0x0009 @@ -449,7 +438,6 @@ typedef struct T3_FWIMG_INFO #define T3_SSID_3COM_3C996SX 0x1004 #define T3_SSID_3COM_3C997SX 0x1005 - /* Dell subsystem/subvendor IDs. */ #define T3_SVID_DELL 0x1028 @@ -469,7 +457,6 @@ typedef struct T3_FWIMG_INFO #define T3_SSID_COMPAQ_NC7780 0x0085 #define T3_SSID_COMPAQ_NC7780_2 0x0099 - /******************************************************************************/ /* MII registers. */ /******************************************************************************/ @@ -490,14 +477,12 @@ typedef struct T3_FWIMG_INFO #define PHY_CTRL_LOOPBACK_MODE BIT_14 #define PHY_CTRL_PHY_RESET BIT_15 - /* Status register. */ #define PHY_STATUS_REG 0x01 #define PHY_STATUS_LINK_PASS BIT_2 #define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5 - /* Phy Id registers. */ #define PHY_ID1_REG 0x02 #define PHY_ID1_OUI_MASK 0xffff @@ -507,7 +492,6 @@ typedef struct T3_FWIMG_INFO #define PHY_ID2_MODEL_MASK 0x03f0 #define PHY_ID2_OUI_MASK 0xfc00 - /* Auto-negotiation advertisement register. */ #define PHY_AN_AD_REG 0x04 @@ -519,18 +503,15 @@ typedef struct T3_FWIMG_INFO #define PHY_AN_AD_100BASETX_FULL BIT_8 #define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01 - /* Auto-negotiation Link Partner Ability register. */ #define PHY_LINK_PARTNER_ABILITY_REG 0x05 #define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11 #define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10 - /* Auto-negotiation expansion register. */ #define PHY_AN_EXPANSION_REG 0x06 - /******************************************************************************/ /* BCM5400 and BCM5401 phy info. */ /******************************************************************************/ @@ -557,7 +538,6 @@ typedef struct T3_FWIMG_INFO #define PHY_ID_MASK (PHY_ID_OUI_MASK | \ PHY_ID_MODEL_MASK) - #define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \ (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \ (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \ @@ -566,7 +546,6 @@ typedef struct T3_FWIMG_INFO (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \ (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID)) - /* 1000Base-T control register. */ #define BCM540X_1000BASET_CTRL_REG 0x09 @@ -575,7 +554,6 @@ typedef struct T3_FWIMG_INFO #define BCM540X_CONFIG_AS_MASTER BIT_11 #define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12 - /* Extended control register. */ #define BCM540X_EXT_CTRL_REG 0x10 @@ -587,11 +565,9 @@ typedef struct T3_FWIMG_INFO #define BCM540X_EXT_STATUS_LINK_PASS BIT_8 - /* DSP Coefficient Read/Write Port. */ #define BCM540X_DSP_RW_PORT 0x15 - /* DSP Coeficient Address Register. */ #define BCM540X_DSP_ADDRESS_REG 0x17 @@ -631,7 +607,6 @@ typedef struct T3_FWIMG_INFO #define BCM540X_CONTROL_ALL_CHANNELS BIT_15 - /* Auxilliary Control Register (Shadow Register) */ #define BCM5401_AUX_CTRL 0x18 @@ -644,7 +619,6 @@ typedef struct T3_FWIMG_INFO #define BCM5401_SHADOW_SEL_MISC_TEST2 0x05 #define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06 - /* Shadow register selector == '000' */ #define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3 #define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4 @@ -664,7 +638,6 @@ typedef struct T3_FWIMG_INFO #define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14 #define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15 - /* Auxilliary status summary. */ #define BCM540X_AUX_STATUS_REG 0x19 @@ -678,7 +651,6 @@ typedef struct T3_FWIMG_INFO #define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10) #define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10) - /* Interrupt status. */ #define BCM540X_INT_STATUS_REG 0x1a @@ -687,11 +659,9 @@ typedef struct T3_FWIMG_INFO #define BCM540X_INT_DUPLEX_CHANGE BIT_3 #define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10 - /* Interrupt mask register. */ #define BCM540X_INT_MASK_REG 0x1b - /******************************************************************************/ /* Register definitions. */ /******************************************************************************/ @@ -701,9 +671,9 @@ typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER; typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER; typedef struct { - /* Big endian format. */ - T3_32BIT_REGISTER High; - T3_32BIT_REGISTER Low; + /* Big endian format. */ + T3_32BIT_REGISTER High; + T3_32BIT_REGISTER Low; } T3_64BIT_REGISTER, *PT3_64BIT_REGISTER; typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR; @@ -711,47 +681,44 @@ typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR; #define T3_NUM_OF_DMA_DESC 256 #define T3_NUM_OF_MBUF 768 -typedef struct -{ - T3_64BIT_REGISTER host_addr; - T3_32BIT_REGISTER nic_mbuf; - T3_16BIT_REGISTER len; - T3_16BIT_REGISTER cqid_sqid; - T3_32BIT_REGISTER flags; - T3_32BIT_REGISTER opaque1; - T3_32BIT_REGISTER opaque2; - T3_32BIT_REGISTER opaque3; -}T3_DMA_DESC, *PT3_DMA_DESC; - +typedef struct { + T3_64BIT_REGISTER host_addr; + T3_32BIT_REGISTER nic_mbuf; + T3_16BIT_REGISTER len; + T3_16BIT_REGISTER cqid_sqid; + T3_32BIT_REGISTER flags; + T3_32BIT_REGISTER opaque1; + T3_32BIT_REGISTER opaque2; + T3_32BIT_REGISTER opaque3; +} T3_DMA_DESC, *PT3_DMA_DESC; /******************************************************************************/ /* Ring control block. */ /******************************************************************************/ typedef struct { - T3_64BIT_REGISTER HostRingAddr; + T3_64BIT_REGISTER HostRingAddr; - union { - struct { + union { + struct { #ifdef BIG_ENDIAN_HOST - T3_16BIT_REGISTER MaxLen; - T3_16BIT_REGISTER Flags; -#else /* BIG_ENDIAN_HOST */ - T3_16BIT_REGISTER Flags; - T3_16BIT_REGISTER MaxLen; + T3_16BIT_REGISTER MaxLen; + T3_16BIT_REGISTER Flags; +#else /* BIG_ENDIAN_HOST */ + T3_16BIT_REGISTER Flags; + T3_16BIT_REGISTER MaxLen; #endif - } s; + } s; - T3_32BIT_REGISTER MaxLen_Flags; - } u; + T3_32BIT_REGISTER MaxLen_Flags; + } u; - T3_32BIT_REGISTER NicRingAddr; + T3_32BIT_REGISTER NicRingAddr; } T3_RCB, *PT3_RCB; #define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0 #define T3_RCB_FLAG_RING_DISABLED BIT_1 - /******************************************************************************/ /* Status block. */ /******************************************************************************/ @@ -763,98 +730,95 @@ typedef struct { #define T3_STATUS_BLOCK_SIZE 0x80 typedef struct { - volatile LM_UINT32 Status; - #define STATUS_BLOCK_UPDATED BIT_0 - #define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1 - #define STATUS_BLOCK_ERROR BIT_2 + volatile LM_UINT32 Status; +#define STATUS_BLOCK_UPDATED BIT_0 +#define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1 +#define STATUS_BLOCK_ERROR BIT_2 - volatile LM_UINT32 StatusTag; + volatile LM_UINT32 StatusTag; #ifdef BIG_ENDIAN_HOST - volatile LM_UINT16 RcvStdConIdx; - volatile LM_UINT16 RcvJumboConIdx; - - volatile LM_UINT16 Reserved2; - volatile LM_UINT16 RcvMiniConIdx; - - struct { - volatile LM_UINT16 SendConIdx; /* Send consumer index. */ - volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ - } Idx[16]; -#else /* BIG_ENDIAN_HOST */ - volatile LM_UINT16 RcvJumboConIdx; - volatile LM_UINT16 RcvStdConIdx; - - volatile LM_UINT16 RcvMiniConIdx; - volatile LM_UINT16 Reserved2; - - struct { - volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ - volatile LM_UINT16 SendConIdx; /* Send consumer index. */ - } Idx[16]; + volatile LM_UINT16 RcvStdConIdx; + volatile LM_UINT16 RcvJumboConIdx; + + volatile LM_UINT16 Reserved2; + volatile LM_UINT16 RcvMiniConIdx; + + struct { + volatile LM_UINT16 SendConIdx; /* Send consumer index. */ + volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ + } Idx[16]; +#else /* BIG_ENDIAN_HOST */ + volatile LM_UINT16 RcvJumboConIdx; + volatile LM_UINT16 RcvStdConIdx; + + volatile LM_UINT16 RcvMiniConIdx; + volatile LM_UINT16 Reserved2; + + struct { + volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ + volatile LM_UINT16 SendConIdx; /* Send consumer index. */ + } Idx[16]; #endif } T3_STATUS_BLOCK, *PT3_STATUS_BLOCK; - /******************************************************************************/ /* Receive buffer descriptors. */ /******************************************************************************/ typedef struct { - T3_64BIT_HOST_ADDR HostAddr; + T3_64BIT_HOST_ADDR HostAddr; #ifdef BIG_ENDIAN_HOST - volatile LM_UINT16 Index; - volatile LM_UINT16 Len; + volatile LM_UINT16 Index; + volatile LM_UINT16 Len; - volatile LM_UINT16 Type; - volatile LM_UINT16 Flags; + volatile LM_UINT16 Type; + volatile LM_UINT16 Flags; - volatile LM_UINT16 IpCksum; - volatile LM_UINT16 TcpUdpCksum; + volatile LM_UINT16 IpCksum; + volatile LM_UINT16 TcpUdpCksum; - volatile LM_UINT16 ErrorFlag; - volatile LM_UINT16 VlanTag; -#else /* BIG_ENDIAN_HOST */ - volatile LM_UINT16 Len; - volatile LM_UINT16 Index; + volatile LM_UINT16 ErrorFlag; + volatile LM_UINT16 VlanTag; +#else /* BIG_ENDIAN_HOST */ + volatile LM_UINT16 Len; + volatile LM_UINT16 Index; - volatile LM_UINT16 Flags; - volatile LM_UINT16 Type; + volatile LM_UINT16 Flags; + volatile LM_UINT16 Type; - volatile LM_UINT16 TcpUdpCksum; - volatile LM_UINT16 IpCksum; + volatile LM_UINT16 TcpUdpCksum; + volatile LM_UINT16 IpCksum; - volatile LM_UINT16 VlanTag; - volatile LM_UINT16 ErrorFlag; + volatile LM_UINT16 VlanTag; + volatile LM_UINT16 ErrorFlag; #endif - volatile LM_UINT32 Reserved; - volatile LM_UINT32 Opaque; + volatile LM_UINT32 Reserved; + volatile LM_UINT32 Opaque; } T3_RCV_BD, *PT3_RCV_BD; - typedef struct { - T3_64BIT_HOST_ADDR HostAddr[3]; + T3_64BIT_HOST_ADDR HostAddr[3]; #ifdef BIG_ENDIAN_HOST - LM_UINT16 Len1; - LM_UINT16 Len2; + LM_UINT16 Len1; + LM_UINT16 Len2; - LM_UINT16 Len3; - LM_UINT16 Reserved1; -#else /* BIG_ENDIAN_HOST */ - LM_UINT16 Len2; - LM_UINT16 Len1; + LM_UINT16 Len3; + LM_UINT16 Reserved1; +#else /* BIG_ENDIAN_HOST */ + LM_UINT16 Len2; + LM_UINT16 Len1; - LM_UINT16 Reserved1; - LM_UINT16 Len3; + LM_UINT16 Reserved1; + LM_UINT16 Len3; #endif - T3_RCV_BD StdRcvBd; + T3_RCV_BD StdRcvBd; } T3_EXT_RCV_BD, *PT3_EXT_RCV_BD; - /* Error flags. */ #define RCV_BD_ERR_BAD_CRC 0x0001 #define RCV_BD_ERR_COLL_DETECT 0x0002 @@ -866,7 +830,6 @@ typedef struct { #define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080 #define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100 - /* Buffer descriptor flags. */ #define RCV_BD_FLAG_END 0x0004 #define RCV_BD_FLAG_JUMBO_RING 0x0020 @@ -877,44 +840,42 @@ typedef struct { #define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000 #define RCV_BD_FLAG_TCP_PACKET 0x4000 - /******************************************************************************/ /* Send buffer descriptor. */ /******************************************************************************/ typedef struct { - T3_64BIT_HOST_ADDR HostAddr; + T3_64BIT_HOST_ADDR HostAddr; - union { - struct { + union { + struct { #ifdef BIG_ENDIAN_HOST - LM_UINT16 Len; - LM_UINT16 Flags; -#else /* BIG_ENDIAN_HOST */ - LM_UINT16 Flags; - LM_UINT16 Len; + LM_UINT16 Len; + LM_UINT16 Flags; +#else /* BIG_ENDIAN_HOST */ + LM_UINT16 Flags; + LM_UINT16 Len; #endif - } s1; + } s1; - LM_UINT32 Len_Flags; - } u1; + LM_UINT32 Len_Flags; + } u1; - union { - struct { + union { + struct { #ifdef BIG_ENDIAN_HOST - LM_UINT16 Reserved; - LM_UINT16 VlanTag; -#else /* BIG_ENDIAN_HOST */ - LM_UINT16 VlanTag; - LM_UINT16 Reserved; + LM_UINT16 Reserved; + LM_UINT16 VlanTag; +#else /* BIG_ENDIAN_HOST */ + LM_UINT16 VlanTag; + LM_UINT16 Reserved; #endif - } s2; + } s2; - LM_UINT32 VlanTag; - } u2; + LM_UINT32 VlanTag; + } u2; } T3_SND_BD, *PT3_SND_BD; - /* Send buffer descriptor flags. */ #define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001 #define SND_BD_FLAG_IP_CKSUM 0x0002 @@ -932,435 +893,426 @@ typedef struct { /* MBUFs */ typedef struct T3_MBUF_FRAME_DESC { #ifdef BIG_ENDIAN_HOST - LM_UINT32 status_control; - union { - struct { - LM_UINT8 cqid; - LM_UINT8 reserved1; - LM_UINT16 length; - }s1; - LM_UINT32 word; - }u1; - union { - struct - { - LM_UINT16 ip_hdr_start; - LM_UINT16 tcp_udp_hdr_start; - }s2; - - LM_UINT32 word; - }u2; - - union { - struct { - LM_UINT16 data_start; - LM_UINT16 vlan_id; - }s3; - - LM_UINT32 word; - }u3; - - union { - struct { - LM_UINT16 ip_checksum; - LM_UINT16 tcp_udp_checksum; - }s4; - - LM_UINT32 word; - }u4; - - union { - struct { - LM_UINT16 pseudo_checksum; - LM_UINT16 checksum_status; - }s5; - - LM_UINT32 word; - }u5; - - union { - struct { - LM_UINT16 rule_match; - LM_UINT8 class; - LM_UINT8 rupt; - }s6; - - LM_UINT32 word; - }u6; - - union { - struct { - LM_UINT16 reserved2; - LM_UINT16 mbuf_num; - }s7; - - LM_UINT32 word; - }u7; - - LM_UINT32 reserved3; - LM_UINT32 reserved4; + LM_UINT32 status_control; + union { + struct { + LM_UINT8 cqid; + LM_UINT8 reserved1; + LM_UINT16 length; + } s1; + LM_UINT32 word; + } u1; + union { + struct { + LM_UINT16 ip_hdr_start; + LM_UINT16 tcp_udp_hdr_start; + } s2; + + LM_UINT32 word; + } u2; + + union { + struct { + LM_UINT16 data_start; + LM_UINT16 vlan_id; + } s3; + + LM_UINT32 word; + } u3; + + union { + struct { + LM_UINT16 ip_checksum; + LM_UINT16 tcp_udp_checksum; + } s4; + + LM_UINT32 word; + } u4; + + union { + struct { + LM_UINT16 pseudo_checksum; + LM_UINT16 checksum_status; + } s5; + + LM_UINT32 word; + } u5; + + union { + struct { + LM_UINT16 rule_match; + LM_UINT8 class; + LM_UINT8 rupt; + } s6; + + LM_UINT32 word; + } u6; + + union { + struct { + LM_UINT16 reserved2; + LM_UINT16 mbuf_num; + } s7; + + LM_UINT32 word; + } u7; + + LM_UINT32 reserved3; + LM_UINT32 reserved4; #else - LM_UINT32 status_control; - union { - struct { - LM_UINT16 length; - LM_UINT8 reserved1; - LM_UINT8 cqid; - }s1; - LM_UINT32 word; - }u1; - union { - struct - { - LM_UINT16 tcp_udp_hdr_start; - LM_UINT16 ip_hdr_start; - }s2; - - LM_UINT32 word; - }u2; - - union { - struct { - LM_UINT16 vlan_id; - LM_UINT16 data_start; - }s3; - - LM_UINT32 word; - }u3; - - union { - struct { - LM_UINT16 tcp_udp_checksum; - LM_UINT16 ip_checksum; - }s4; - - LM_UINT32 word; - }u4; - - union { - struct { - LM_UINT16 checksum_status; - LM_UINT16 pseudo_checksum; - }s5; - - LM_UINT32 word; - }u5; - - union { - struct { - LM_UINT8 rupt; - LM_UINT8 class; - LM_UINT16 rule_match; - }s6; - - LM_UINT32 word; - }u6; - - union { - struct { - LM_UINT16 mbuf_num; - LM_UINT16 reserved2; - }s7; - - LM_UINT32 word; - }u7; - - LM_UINT32 reserved3; - LM_UINT32 reserved4; + LM_UINT32 status_control; + union { + struct { + LM_UINT16 length; + LM_UINT8 reserved1; + LM_UINT8 cqid; + } s1; + LM_UINT32 word; + } u1; + union { + struct { + LM_UINT16 tcp_udp_hdr_start; + LM_UINT16 ip_hdr_start; + } s2; + + LM_UINT32 word; + } u2; + + union { + struct { + LM_UINT16 vlan_id; + LM_UINT16 data_start; + } s3; + + LM_UINT32 word; + } u3; + + union { + struct { + LM_UINT16 tcp_udp_checksum; + LM_UINT16 ip_checksum; + } s4; + + LM_UINT32 word; + } u4; + + union { + struct { + LM_UINT16 checksum_status; + LM_UINT16 pseudo_checksum; + } s5; + + LM_UINT32 word; + } u5; + + union { + struct { + LM_UINT8 rupt; + LM_UINT8 class; + LM_UINT16 rule_match; + } s6; + + LM_UINT32 word; + } u6; + + union { + struct { + LM_UINT16 mbuf_num; + LM_UINT16 reserved2; + } s7; + + LM_UINT32 word; + } u7; + + LM_UINT32 reserved3; + LM_UINT32 reserved4; #endif -}T3_MBUF_FRAME_DESC,*PT3_MBUF_FRAME_DESC; +} T3_MBUF_FRAME_DESC, *PT3_MBUF_FRAME_DESC; typedef struct T3_MBUF_HDR { - union { - struct { - unsigned int C:1; - unsigned int F:1; - unsigned int reserved1:7; - unsigned int next_mbuf:16; - unsigned int length:7; - }s1; - - LM_UINT32 word; - }u1; - - LM_UINT32 next_frame_ptr; -}T3_MBUF_HDR, *PT3_MBUF_HDR; - -typedef struct T3_MBUF -{ - T3_MBUF_HDR hdr; - union - { - struct { - T3_MBUF_FRAME_DESC frame_hdr; - LM_UINT32 data[20]; - }s1; - - struct { - LM_UINT32 data[30]; - }s2; - }body; -}T3_MBUF, *PT3_MBUF; + union { + struct { + unsigned int C:1; + unsigned int F:1; + unsigned int reserved1:7; + unsigned int next_mbuf:16; + unsigned int length:7; + } s1; + + LM_UINT32 word; + } u1; + + LM_UINT32 next_frame_ptr; +} T3_MBUF_HDR, *PT3_MBUF_HDR; + +typedef struct T3_MBUF { + T3_MBUF_HDR hdr; + union { + struct { + T3_MBUF_FRAME_DESC frame_hdr; + LM_UINT32 data[20]; + } s1; + + struct { + LM_UINT32 data[30]; + } s2; + } body; +} T3_MBUF, *PT3_MBUF; #define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7) #define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7) - /******************************************************************************/ /* Statistics block. */ /******************************************************************************/ typedef struct { - LM_UINT8 Reserved0[0x400-0x300]; - - /* Statistics maintained by Receive MAC. */ - T3_64BIT_REGISTER ifHCInOctets; - T3_64BIT_REGISTER Reserved1; - T3_64BIT_REGISTER etherStatsFragments; - T3_64BIT_REGISTER ifHCInUcastPkts; - T3_64BIT_REGISTER ifHCInMulticastPkts; - T3_64BIT_REGISTER ifHCInBroadcastPkts; - T3_64BIT_REGISTER dot3StatsFCSErrors; - T3_64BIT_REGISTER dot3StatsAlignmentErrors; - T3_64BIT_REGISTER xonPauseFramesReceived; - T3_64BIT_REGISTER xoffPauseFramesReceived; - T3_64BIT_REGISTER macControlFramesReceived; - T3_64BIT_REGISTER xoffStateEntered; - T3_64BIT_REGISTER dot3StatsFramesTooLong; - T3_64BIT_REGISTER etherStatsJabbers; - T3_64BIT_REGISTER etherStatsUndersizePkts; - T3_64BIT_REGISTER inRangeLengthError; - T3_64BIT_REGISTER outRangeLengthError; - T3_64BIT_REGISTER etherStatsPkts64Octets; - T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets; - T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets; - T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets; - T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets; - T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets; - T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets; - T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets; - T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets; - T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets; - - T3_64BIT_REGISTER Unused1[37]; - - /* Statistics maintained by Transmit MAC. */ - T3_64BIT_REGISTER ifHCOutOctets; - T3_64BIT_REGISTER Reserved2; - T3_64BIT_REGISTER etherStatsCollisions; - T3_64BIT_REGISTER outXonSent; - T3_64BIT_REGISTER outXoffSent; - T3_64BIT_REGISTER flowControlDone; - T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors; - T3_64BIT_REGISTER dot3StatsSingleCollisionFrames; - T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames; - T3_64BIT_REGISTER dot3StatsDeferredTransmissions; - T3_64BIT_REGISTER Reserved3; - T3_64BIT_REGISTER dot3StatsExcessiveCollisions; - T3_64BIT_REGISTER dot3StatsLateCollisions; - T3_64BIT_REGISTER dot3Collided2Times; - T3_64BIT_REGISTER dot3Collided3Times; - T3_64BIT_REGISTER dot3Collided4Times; - T3_64BIT_REGISTER dot3Collided5Times; - T3_64BIT_REGISTER dot3Collided6Times; - T3_64BIT_REGISTER dot3Collided7Times; - T3_64BIT_REGISTER dot3Collided8Times; - T3_64BIT_REGISTER dot3Collided9Times; - T3_64BIT_REGISTER dot3Collided10Times; - T3_64BIT_REGISTER dot3Collided11Times; - T3_64BIT_REGISTER dot3Collided12Times; - T3_64BIT_REGISTER dot3Collided13Times; - T3_64BIT_REGISTER dot3Collided14Times; - T3_64BIT_REGISTER dot3Collided15Times; - T3_64BIT_REGISTER ifHCOutUcastPkts; - T3_64BIT_REGISTER ifHCOutMulticastPkts; - T3_64BIT_REGISTER ifHCOutBroadcastPkts; - T3_64BIT_REGISTER dot3StatsCarrierSenseErrors; - T3_64BIT_REGISTER ifOutDiscards; - T3_64BIT_REGISTER ifOutErrors; - - T3_64BIT_REGISTER Unused2[31]; - - /* Statistics maintained by Receive List Placement. */ - T3_64BIT_REGISTER COSIfHCInPkts[16]; - T3_64BIT_REGISTER COSFramesDroppedDueToFilters; - T3_64BIT_REGISTER nicDmaWriteQueueFull; - T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull; - T3_64BIT_REGISTER nicNoMoreRxBDs; - T3_64BIT_REGISTER ifInDiscards; - T3_64BIT_REGISTER ifInErrors; - T3_64BIT_REGISTER nicRecvThresholdHit; - - T3_64BIT_REGISTER Unused3[9]; - - /* Statistics maintained by Send Data Initiator. */ - T3_64BIT_REGISTER COSIfHCOutPkts[16]; - T3_64BIT_REGISTER nicDmaReadQueueFull; - T3_64BIT_REGISTER nicDmaReadHighPriQueueFull; - T3_64BIT_REGISTER nicSendDataCompQueueFull; - - /* Statistics maintained by Host Coalescing. */ - T3_64BIT_REGISTER nicRingSetSendProdIndex; - T3_64BIT_REGISTER nicRingStatusUpdate; - T3_64BIT_REGISTER nicInterrupts; - T3_64BIT_REGISTER nicAvoidedInterrupts; - T3_64BIT_REGISTER nicSendThresholdHit; - - LM_UINT8 Reserved4[0xb00-0x9c0]; + LM_UINT8 Reserved0[0x400 - 0x300]; + + /* Statistics maintained by Receive MAC. */ + T3_64BIT_REGISTER ifHCInOctets; + T3_64BIT_REGISTER Reserved1; + T3_64BIT_REGISTER etherStatsFragments; + T3_64BIT_REGISTER ifHCInUcastPkts; + T3_64BIT_REGISTER ifHCInMulticastPkts; + T3_64BIT_REGISTER ifHCInBroadcastPkts; + T3_64BIT_REGISTER dot3StatsFCSErrors; + T3_64BIT_REGISTER dot3StatsAlignmentErrors; + T3_64BIT_REGISTER xonPauseFramesReceived; + T3_64BIT_REGISTER xoffPauseFramesReceived; + T3_64BIT_REGISTER macControlFramesReceived; + T3_64BIT_REGISTER xoffStateEntered; + T3_64BIT_REGISTER dot3StatsFramesTooLong; + T3_64BIT_REGISTER etherStatsJabbers; + T3_64BIT_REGISTER etherStatsUndersizePkts; + T3_64BIT_REGISTER inRangeLengthError; + T3_64BIT_REGISTER outRangeLengthError; + T3_64BIT_REGISTER etherStatsPkts64Octets; + T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets; + T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets; + T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets; + T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets; + T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets; + T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets; + T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets; + T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets; + T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets; + + T3_64BIT_REGISTER Unused1[37]; + + /* Statistics maintained by Transmit MAC. */ + T3_64BIT_REGISTER ifHCOutOctets; + T3_64BIT_REGISTER Reserved2; + T3_64BIT_REGISTER etherStatsCollisions; + T3_64BIT_REGISTER outXonSent; + T3_64BIT_REGISTER outXoffSent; + T3_64BIT_REGISTER flowControlDone; + T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors; + T3_64BIT_REGISTER dot3StatsSingleCollisionFrames; + T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames; + T3_64BIT_REGISTER dot3StatsDeferredTransmissions; + T3_64BIT_REGISTER Reserved3; + T3_64BIT_REGISTER dot3StatsExcessiveCollisions; + T3_64BIT_REGISTER dot3StatsLateCollisions; + T3_64BIT_REGISTER dot3Collided2Times; + T3_64BIT_REGISTER dot3Collided3Times; + T3_64BIT_REGISTER dot3Collided4Times; + T3_64BIT_REGISTER dot3Collided5Times; + T3_64BIT_REGISTER dot3Collided6Times; + T3_64BIT_REGISTER dot3Collided7Times; + T3_64BIT_REGISTER dot3Collided8Times; + T3_64BIT_REGISTER dot3Collided9Times; + T3_64BIT_REGISTER dot3Collided10Times; + T3_64BIT_REGISTER dot3Collided11Times; + T3_64BIT_REGISTER dot3Collided12Times; + T3_64BIT_REGISTER dot3Collided13Times; + T3_64BIT_REGISTER dot3Collided14Times; + T3_64BIT_REGISTER dot3Collided15Times; + T3_64BIT_REGISTER ifHCOutUcastPkts; + T3_64BIT_REGISTER ifHCOutMulticastPkts; + T3_64BIT_REGISTER ifHCOutBroadcastPkts; + T3_64BIT_REGISTER dot3StatsCarrierSenseErrors; + T3_64BIT_REGISTER ifOutDiscards; + T3_64BIT_REGISTER ifOutErrors; + + T3_64BIT_REGISTER Unused2[31]; + + /* Statistics maintained by Receive List Placement. */ + T3_64BIT_REGISTER COSIfHCInPkts[16]; + T3_64BIT_REGISTER COSFramesDroppedDueToFilters; + T3_64BIT_REGISTER nicDmaWriteQueueFull; + T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull; + T3_64BIT_REGISTER nicNoMoreRxBDs; + T3_64BIT_REGISTER ifInDiscards; + T3_64BIT_REGISTER ifInErrors; + T3_64BIT_REGISTER nicRecvThresholdHit; + + T3_64BIT_REGISTER Unused3[9]; + + /* Statistics maintained by Send Data Initiator. */ + T3_64BIT_REGISTER COSIfHCOutPkts[16]; + T3_64BIT_REGISTER nicDmaReadQueueFull; + T3_64BIT_REGISTER nicDmaReadHighPriQueueFull; + T3_64BIT_REGISTER nicSendDataCompQueueFull; + + /* Statistics maintained by Host Coalescing. */ + T3_64BIT_REGISTER nicRingSetSendProdIndex; + T3_64BIT_REGISTER nicRingStatusUpdate; + T3_64BIT_REGISTER nicInterrupts; + T3_64BIT_REGISTER nicAvoidedInterrupts; + T3_64BIT_REGISTER nicSendThresholdHit; + + LM_UINT8 Reserved4[0xb00 - 0x9c0]; } T3_STATS_BLOCK, *PT3_STATS_BLOCK; - /******************************************************************************/ /* PCI configuration registers. */ /******************************************************************************/ typedef struct { - T3_16BIT_REGISTER VendorId; - T3_16BIT_REGISTER DeviceId; - - T3_16BIT_REGISTER Command; - T3_16BIT_REGISTER Status; - - T3_32BIT_REGISTER ClassCodeRevId; - - T3_8BIT_REGISTER CacheLineSize; - T3_8BIT_REGISTER LatencyTimer; - T3_8BIT_REGISTER HeaderType; - T3_8BIT_REGISTER Bist; - - T3_32BIT_REGISTER MemBaseAddrLow; - T3_32BIT_REGISTER MemBaseAddrHigh; - - LM_UINT8 Unused1[20]; - - T3_16BIT_REGISTER SubsystemVendorId; - T3_16BIT_REGISTER SubsystemId; - - T3_32BIT_REGISTER RomBaseAddr; - - T3_8BIT_REGISTER PciXCapiblityPtr; - LM_UINT8 Unused2[7]; - - T3_8BIT_REGISTER IntLine; - T3_8BIT_REGISTER IntPin; - T3_8BIT_REGISTER MinGnt; - T3_8BIT_REGISTER MaxLat; - - T3_8BIT_REGISTER PciXCapabilities; - T3_8BIT_REGISTER PmCapabilityPtr; - T3_16BIT_REGISTER PciXCommand; - - T3_32BIT_REGISTER PciXStatus; - - T3_8BIT_REGISTER PmCapabilityId; - T3_8BIT_REGISTER VpdCapabilityPtr; - T3_16BIT_REGISTER PmCapabilities; - - T3_16BIT_REGISTER PmCtrlStatus; - #define PM_CTRL_PME_STATUS BIT_15 - #define PM_CTRL_PME_ENABLE BIT_8 - #define PM_CTRL_PME_POWER_STATE_D0 0 - #define PM_CTRL_PME_POWER_STATE_D1 1 - #define PM_CTRL_PME_POWER_STATE_D2 2 - #define PM_CTRL_PME_POWER_STATE_D3H 3 - - T3_8BIT_REGISTER BridgeSupportExt; - T3_8BIT_REGISTER PmData; - - T3_8BIT_REGISTER VpdCapabilityId; - T3_8BIT_REGISTER MsiCapabilityPtr; - T3_16BIT_REGISTER VpdAddrFlag; - #define VPD_FLAG_WRITE (1 << 15) - #define VPD_FLAG_RW_MASK (1 << 15) - #define VPD_FLAG_READ 0 - - - T3_32BIT_REGISTER VpdData; - - T3_8BIT_REGISTER MsiCapabilityId; - T3_8BIT_REGISTER NextCapabilityPtr; - T3_16BIT_REGISTER MsiCtrl; - #define MSI_CTRL_64BIT_CAP (1 << 7) - #define MSI_CTRL_MSG_ENABLE(x) (x << 4) - #define MSI_CTRL_MSG_CAP(x) (x << 1) - #define MSI_CTRL_ENABLE (1 << 0) - - - T3_32BIT_REGISTER MsiAddrLow; - T3_32BIT_REGISTER MsiAddrHigh; - - T3_16BIT_REGISTER MsiData; - T3_16BIT_REGISTER Unused3; - - T3_32BIT_REGISTER MiscHostCtrl; - #define MISC_HOST_CTRL_CLEAR_INT BIT_0 - #define MISC_HOST_CTRL_MASK_PCI_INT BIT_1 - #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2 - #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3 - #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4 - #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5 - #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6 - #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7 - #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8 - #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9 - - T3_32BIT_REGISTER DmaReadWriteCtrl; - #define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13) - #define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0 - #define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11 - #define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12 - #define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11) - #define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13 - #define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11) - #define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12) - #define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11) - #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14 - - - T3_32BIT_REGISTER PciState; - #define T3_PCI_STATE_FORCE_PCI_RESET BIT_0 - #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1 - #define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2 - #define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3 - #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 - #define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5 - #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6 - #define T3_PCI_STATE_FLAT_VIEW BIT_8 - #define T3_PCI_STATE_RETRY_SAME_DMA BIT_13 - - T3_32BIT_REGISTER ClockCtrl; - #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11 - #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10 - #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9 - - T3_32BIT_REGISTER RegBaseAddr; - - T3_32BIT_REGISTER MemWindowBaseAddr; + T3_16BIT_REGISTER VendorId; + T3_16BIT_REGISTER DeviceId; + + T3_16BIT_REGISTER Command; + T3_16BIT_REGISTER Status; + + T3_32BIT_REGISTER ClassCodeRevId; + + T3_8BIT_REGISTER CacheLineSize; + T3_8BIT_REGISTER LatencyTimer; + T3_8BIT_REGISTER HeaderType; + T3_8BIT_REGISTER Bist; + + T3_32BIT_REGISTER MemBaseAddrLow; + T3_32BIT_REGISTER MemBaseAddrHigh; + + LM_UINT8 Unused1[20]; + + T3_16BIT_REGISTER SubsystemVendorId; + T3_16BIT_REGISTER SubsystemId; + + T3_32BIT_REGISTER RomBaseAddr; + + T3_8BIT_REGISTER PciXCapiblityPtr; + LM_UINT8 Unused2[7]; + + T3_8BIT_REGISTER IntLine; + T3_8BIT_REGISTER IntPin; + T3_8BIT_REGISTER MinGnt; + T3_8BIT_REGISTER MaxLat; + + T3_8BIT_REGISTER PciXCapabilities; + T3_8BIT_REGISTER PmCapabilityPtr; + T3_16BIT_REGISTER PciXCommand; + + T3_32BIT_REGISTER PciXStatus; + + T3_8BIT_REGISTER PmCapabilityId; + T3_8BIT_REGISTER VpdCapabilityPtr; + T3_16BIT_REGISTER PmCapabilities; + + T3_16BIT_REGISTER PmCtrlStatus; +#define PM_CTRL_PME_STATUS BIT_15 +#define PM_CTRL_PME_ENABLE BIT_8 +#define PM_CTRL_PME_POWER_STATE_D0 0 +#define PM_CTRL_PME_POWER_STATE_D1 1 +#define PM_CTRL_PME_POWER_STATE_D2 2 +#define PM_CTRL_PME_POWER_STATE_D3H 3 + + T3_8BIT_REGISTER BridgeSupportExt; + T3_8BIT_REGISTER PmData; + + T3_8BIT_REGISTER VpdCapabilityId; + T3_8BIT_REGISTER MsiCapabilityPtr; + T3_16BIT_REGISTER VpdAddrFlag; +#define VPD_FLAG_WRITE (1 << 15) +#define VPD_FLAG_RW_MASK (1 << 15) +#define VPD_FLAG_READ 0 + + T3_32BIT_REGISTER VpdData; + + T3_8BIT_REGISTER MsiCapabilityId; + T3_8BIT_REGISTER NextCapabilityPtr; + T3_16BIT_REGISTER MsiCtrl; +#define MSI_CTRL_64BIT_CAP (1 << 7) +#define MSI_CTRL_MSG_ENABLE(x) (x << 4) +#define MSI_CTRL_MSG_CAP(x) (x << 1) +#define MSI_CTRL_ENABLE (1 << 0) + + T3_32BIT_REGISTER MsiAddrLow; + T3_32BIT_REGISTER MsiAddrHigh; + + T3_16BIT_REGISTER MsiData; + T3_16BIT_REGISTER Unused3; + + T3_32BIT_REGISTER MiscHostCtrl; +#define MISC_HOST_CTRL_CLEAR_INT BIT_0 +#define MISC_HOST_CTRL_MASK_PCI_INT BIT_1 +#define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2 +#define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3 +#define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4 +#define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5 +#define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6 +#define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7 +#define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8 +#define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9 + + T3_32BIT_REGISTER DmaReadWriteCtrl; +#define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13) +#define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0 +#define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11 +#define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12 +#define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11) +#define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13 +#define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11) +#define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12) +#define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11) +#define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14 + + T3_32BIT_REGISTER PciState; +#define T3_PCI_STATE_FORCE_PCI_RESET BIT_0 +#define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1 +#define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2 +#define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3 +#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 +#define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5 +#define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6 +#define T3_PCI_STATE_FLAT_VIEW BIT_8 +#define T3_PCI_STATE_RETRY_SAME_DMA BIT_13 + + T3_32BIT_REGISTER ClockCtrl; +#define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11 +#define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10 +#define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9 + + T3_32BIT_REGISTER RegBaseAddr; + + T3_32BIT_REGISTER MemWindowBaseAddr; #ifdef NIC_CPU_VIEW - /* These registers are ONLY visible to NIC CPU */ - T3_32BIT_REGISTER PowerConsumed; - T3_32BIT_REGISTER PowerDissipated; -#else /* NIC_CPU_VIEW */ - T3_32BIT_REGISTER RegData; - T3_32BIT_REGISTER MemWindowData; -#endif /* !NIC_CPU_VIEW */ + /* These registers are ONLY visible to NIC CPU */ + T3_32BIT_REGISTER PowerConsumed; + T3_32BIT_REGISTER PowerDissipated; +#else /* NIC_CPU_VIEW */ + T3_32BIT_REGISTER RegData; + T3_32BIT_REGISTER MemWindowData; +#endif /* !NIC_CPU_VIEW */ - T3_32BIT_REGISTER ModeCtrl; + T3_32BIT_REGISTER ModeCtrl; - T3_32BIT_REGISTER MiscCfg; + T3_32BIT_REGISTER MiscCfg; - T3_32BIT_REGISTER MiscLocalCtrl; + T3_32BIT_REGISTER MiscLocalCtrl; - T3_32BIT_REGISTER Unused4; + T3_32BIT_REGISTER Unused4; - /* NOTE: Big/Little-endian clarification needed. Are these register */ - /* in big or little endian formate. */ - T3_64BIT_REGISTER StdRingProdIdx; - T3_64BIT_REGISTER RcvRetRingConIdx; - T3_64BIT_REGISTER SndProdIdx; + /* NOTE: Big/Little-endian clarification needed. Are these register */ + /* in big or little endian formate. */ + T3_64BIT_REGISTER StdRingProdIdx; + T3_64BIT_REGISTER RcvRetRingConIdx; + T3_64BIT_REGISTER SndProdIdx; - LM_UINT8 Unused5[80]; + LM_UINT8 Unused5[80]; } T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION; #define PCIX_CMD_MAX_SPLIT_MASK 0x0070 @@ -1374,1382 +1326,1347 @@ typedef struct { /******************************************************************************/ typedef struct { - /* MAC mode control. */ - T3_32BIT_REGISTER Mode; - #define MAC_MODE_GLOBAL_RESET BIT_0 - #define MAC_MODE_HALF_DUPLEX BIT_1 - #define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3) - #define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3) - #define MAC_MODE_PORT_MODE_GMII BIT_3 - #define MAC_MODE_PORT_MODE_MII BIT_2 - #define MAC_MODE_PORT_MODE_NONE BIT_NONE - #define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4 - #define MAC_MODE_TAGGED_MAC_CONTROL BIT_7 - #define MAC_MODE_TX_BURSTING BIT_8 - #define MAC_MODE_MAX_DEFER BIT_9 - #define MAC_MODE_LINK_POLARITY BIT_10 - #define MAC_MODE_ENABLE_RX_STATISTICS BIT_11 - #define MAC_MODE_CLEAR_RX_STATISTICS BIT_12 - #define MAC_MODE_FLUSH_RX_STATISTICS BIT_13 - #define MAC_MODE_ENABLE_TX_STATISTICS BIT_14 - #define MAC_MODE_CLEAR_TX_STATISTICS BIT_15 - #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16 - #define MAC_MODE_SEND_CONFIGS BIT_17 - #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18 - #define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19 - #define MAC_MODE_ENABLE_MIP BIT_20 - #define MAC_MODE_ENABLE_TDE BIT_21 - #define MAC_MODE_ENABLE_RDE BIT_22 - #define MAC_MODE_ENABLE_FHDE BIT_23 - - /* MAC status */ - T3_32BIT_REGISTER Status; - #define MAC_STATUS_PCS_SYNCED BIT_0 - #define MAC_STATUS_SIGNAL_DETECTED BIT_1 - #define MAC_STATUS_RECEIVING_CFG BIT_2 - #define MAC_STATUS_CFG_CHANGED BIT_3 - #define MAC_STATUS_SYNC_CHANGED BIT_4 - #define MAC_STATUS_PORT_DECODE_ERROR BIT_10 - #define MAC_STATUS_LINK_STATE_CHANGED BIT_12 - #define MAC_STATUS_MI_COMPLETION BIT_22 - #define MAC_STATUS_MI_INTERRUPT BIT_23 - #define MAC_STATUS_AP_ERROR BIT_24 - #define MAC_STATUS_ODI_ERROR BIT_25 - #define MAC_STATUS_RX_STATS_OVERRUN BIT_26 - #define MAC_STATUS_TX_STATS_OVERRUN BIT_27 - - /* Event Enable */ - T3_32BIT_REGISTER MacEvent; - #define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10 - #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12 - #define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22 - #define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23 - #define MAC_EVENT_ENABLE_AP_ERROR BIT_24 - #define MAC_EVENT_ENABLE_ODI_ERROR BIT_25 - #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26 - #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27 - - /* Led control. */ - T3_32BIT_REGISTER LedCtrl; - #define LED_CTRL_OVERRIDE_LINK_LED BIT_0 - #define LED_CTRL_1000MBPS_LED_ON BIT_1 - #define LED_CTRL_100MBPS_LED_ON BIT_2 - #define LED_CTRL_10MBPS_LED_ON BIT_3 - #define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4 - #define LED_CTRL_BLINK_TRAFFIC_LED BIT_5 - #define LED_CTRL_TRAFFIC_LED BIT_6 - #define LED_CTRL_1000MBPS_LED_STATUS BIT_7 - #define LED_CTRL_100MBPS_LED_STATUS BIT_8 - #define LED_CTRL_10MBPS_LED_STATUS BIT_9 - #define LED_CTRL_TRAFFIC_LED_STATUS BIT_10 - #define LED_CTRL_MAC_MODE BIT_NONE - #define LED_CTRL_PHY_MODE_1 BIT_11 - #define LED_CTRL_PHY_MODE_2 BIT_12 - #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 - #define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19 - #define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31 - - /* MAC addresses. */ - struct { - T3_32BIT_REGISTER High; /* Upper 2 bytes. */ - T3_32BIT_REGISTER Low; /* Lower 4 bytes. */ - } MacAddr[4]; - - /* ACPI Mbuf pointer. */ - T3_32BIT_REGISTER AcpiMbufPtr; - - /* ACPI Length and Offset. */ - T3_32BIT_REGISTER AcpiLengthOffset; - #define ACPI_LENGTH_MASK 0xffff - #define ACPI_OFFSET_MASK 0x0fff0000 - #define ACPI_LENGTH(x) x - #define ACPI_OFFSET(x) ((x) << 16) - - /* Transmit random backoff. */ - T3_32BIT_REGISTER TxBackoffSeed; - #define MAC_TX_BACKOFF_SEED_MASK 0x3ff - - /* Receive MTU */ - T3_32BIT_REGISTER MtuSize; - #define MAC_RX_MTU_MASK 0xffff - - /* Gigabit PCS Test. */ - T3_32BIT_REGISTER PcsTest; - #define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff - #define MAC_PCS_TEST_ENABLE BIT_20 - - /* Transmit Gigabit Auto-Negotiation. */ - T3_32BIT_REGISTER TxAutoNeg; - #define MAC_AN_TX_AN_DATA_MASK 0xffff - - /* Receive Gigabit Auto-Negotiation. */ - T3_32BIT_REGISTER RxAutoNeg; - #define MAC_AN_RX_AN_DATA_MASK 0xffff - - /* MI Communication. */ - T3_32BIT_REGISTER MiCom; - #define MI_COM_CMD_MASK (BIT_26 | BIT_27) - #define MI_COM_CMD_WRITE BIT_26 - #define MI_COM_CMD_READ BIT_27 - #define MI_COM_READ_FAILED BIT_28 - #define MI_COM_START BIT_29 - #define MI_COM_BUSY BIT_29 - - #define MI_COM_PHY_ADDR_MASK 0x1f - #define MI_COM_FIRST_PHY_ADDR_BIT 21 - - #define MI_COM_PHY_REG_ADDR_MASK 0x1f - #define MI_COM_FIRST_PHY_REG_ADDR_BIT 16 - - #define MI_COM_PHY_DATA_MASK 0xffff - - /* MI Status. */ - T3_32BIT_REGISTER MiStatus; - #define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0 - - /* MI Mode. */ - T3_32BIT_REGISTER MiMode; - #define MI_MODE_CLOCK_SPEED_10MHZ BIT_0 - #define MI_MODE_USE_SHORT_PREAMBLE BIT_1 - #define MI_MODE_AUTO_POLLING_ENABLE BIT_4 - #define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15 - - /* Auto-polling status. */ - T3_32BIT_REGISTER AutoPollStatus; - #define AUTO_POLL_ERROR BIT_0 - - /* Transmit MAC mode. */ - T3_32BIT_REGISTER TxMode; - #define TX_MODE_RESET BIT_0 - #define TX_MODE_ENABLE BIT_1 - #define TX_MODE_ENABLE_FLOW_CONTROL BIT_4 - #define TX_MODE_ENABLE_BIG_BACKOFF BIT_5 - #define TX_MODE_ENABLE_LONG_PAUSE BIT_6 - - /* Transmit MAC status. */ - T3_32BIT_REGISTER TxStatus; - #define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0 - #define TX_STATUS_SENT_XOFF BIT_1 - #define TX_STATUS_SENT_XON BIT_2 - #define TX_STATUS_LINK_UP BIT_3 - #define TX_STATUS_ODI_UNDERRUN BIT_4 - #define TX_STATUS_ODI_OVERRUN BIT_5 - - /* Transmit MAC length. */ - T3_32BIT_REGISTER TxLengths; - #define TX_LEN_SLOT_TIME_MASK 0xff - #define TX_LEN_IPG_MASK 0x0f00 - #define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13) - - /* Receive MAC mode. */ - T3_32BIT_REGISTER RxMode; - #define RX_MODE_RESET BIT_0 - #define RX_MODE_ENABLE BIT_1 - #define RX_MODE_ENABLE_FLOW_CONTROL BIT_2 - #define RX_MODE_KEEP_MAC_CONTROL BIT_3 - #define RX_MODE_KEEP_PAUSE BIT_4 - #define RX_MODE_ACCEPT_OVERSIZED BIT_5 - #define RX_MODE_ACCEPT_RUNTS BIT_6 - #define RX_MODE_LENGTH_CHECK BIT_7 - #define RX_MODE_PROMISCUOUS_MODE BIT_8 - #define RX_MODE_NO_CRC_CHECK BIT_9 - #define RX_MODE_KEEP_VLAN_TAG BIT_10 - - /* Receive MAC status. */ - T3_32BIT_REGISTER RxStatus; - #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0 - #define RX_STATUS_XOFF_RECEIVED BIT_1 - #define RX_STATUS_XON_RECEIVED BIT_2 - - /* Hash registers. */ - T3_32BIT_REGISTER HashReg[4]; - - /* Receive placement rules registers. */ - struct { - T3_32BIT_REGISTER Rule; - T3_32BIT_REGISTER Value; - } RcvRules[16]; - - #define RCV_DISABLE_RULE_MASK 0x7fffffff - - #define RCV_RULE1_REJECT_BROADCAST_IDX 0x00 - #define REJECT_BROADCAST_RULE1_RULE 0xc2000000 - #define REJECT_BROADCAST_RULE1_VALUE 0xffffffff - - #define RCV_RULE2_REJECT_BROADCAST_IDX 0x01 - #define REJECT_BROADCAST_RULE2_RULE 0x86000004 - #define REJECT_BROADCAST_RULE2_VALUE 0xffffffff + /* MAC mode control. */ + T3_32BIT_REGISTER Mode; +#define MAC_MODE_GLOBAL_RESET BIT_0 +#define MAC_MODE_HALF_DUPLEX BIT_1 +#define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3) +#define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3) +#define MAC_MODE_PORT_MODE_GMII BIT_3 +#define MAC_MODE_PORT_MODE_MII BIT_2 +#define MAC_MODE_PORT_MODE_NONE BIT_NONE +#define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4 +#define MAC_MODE_TAGGED_MAC_CONTROL BIT_7 +#define MAC_MODE_TX_BURSTING BIT_8 +#define MAC_MODE_MAX_DEFER BIT_9 +#define MAC_MODE_LINK_POLARITY BIT_10 +#define MAC_MODE_ENABLE_RX_STATISTICS BIT_11 +#define MAC_MODE_CLEAR_RX_STATISTICS BIT_12 +#define MAC_MODE_FLUSH_RX_STATISTICS BIT_13 +#define MAC_MODE_ENABLE_TX_STATISTICS BIT_14 +#define MAC_MODE_CLEAR_TX_STATISTICS BIT_15 +#define MAC_MODE_FLUSH_TX_STATISTICS BIT_16 +#define MAC_MODE_SEND_CONFIGS BIT_17 +#define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18 +#define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19 +#define MAC_MODE_ENABLE_MIP BIT_20 +#define MAC_MODE_ENABLE_TDE BIT_21 +#define MAC_MODE_ENABLE_RDE BIT_22 +#define MAC_MODE_ENABLE_FHDE BIT_23 + + /* MAC status */ + T3_32BIT_REGISTER Status; +#define MAC_STATUS_PCS_SYNCED BIT_0 +#define MAC_STATUS_SIGNAL_DETECTED BIT_1 +#define MAC_STATUS_RECEIVING_CFG BIT_2 +#define MAC_STATUS_CFG_CHANGED BIT_3 +#define MAC_STATUS_SYNC_CHANGED BIT_4 +#define MAC_STATUS_PORT_DECODE_ERROR BIT_10 +#define MAC_STATUS_LINK_STATE_CHANGED BIT_12 +#define MAC_STATUS_MI_COMPLETION BIT_22 +#define MAC_STATUS_MI_INTERRUPT BIT_23 +#define MAC_STATUS_AP_ERROR BIT_24 +#define MAC_STATUS_ODI_ERROR BIT_25 +#define MAC_STATUS_RX_STATS_OVERRUN BIT_26 +#define MAC_STATUS_TX_STATS_OVERRUN BIT_27 + + /* Event Enable */ + T3_32BIT_REGISTER MacEvent; +#define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10 +#define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12 +#define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22 +#define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23 +#define MAC_EVENT_ENABLE_AP_ERROR BIT_24 +#define MAC_EVENT_ENABLE_ODI_ERROR BIT_25 +#define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26 +#define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27 + + /* Led control. */ + T3_32BIT_REGISTER LedCtrl; +#define LED_CTRL_OVERRIDE_LINK_LED BIT_0 +#define LED_CTRL_1000MBPS_LED_ON BIT_1 +#define LED_CTRL_100MBPS_LED_ON BIT_2 +#define LED_CTRL_10MBPS_LED_ON BIT_3 +#define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4 +#define LED_CTRL_BLINK_TRAFFIC_LED BIT_5 +#define LED_CTRL_TRAFFIC_LED BIT_6 +#define LED_CTRL_1000MBPS_LED_STATUS BIT_7 +#define LED_CTRL_100MBPS_LED_STATUS BIT_8 +#define LED_CTRL_10MBPS_LED_STATUS BIT_9 +#define LED_CTRL_TRAFFIC_LED_STATUS BIT_10 +#define LED_CTRL_MAC_MODE BIT_NONE +#define LED_CTRL_PHY_MODE_1 BIT_11 +#define LED_CTRL_PHY_MODE_2 BIT_12 +#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 +#define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19 +#define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31 + + /* MAC addresses. */ + struct { + T3_32BIT_REGISTER High; /* Upper 2 bytes. */ + T3_32BIT_REGISTER Low; /* Lower 4 bytes. */ + } MacAddr[4]; + + /* ACPI Mbuf pointer. */ + T3_32BIT_REGISTER AcpiMbufPtr; + + /* ACPI Length and Offset. */ + T3_32BIT_REGISTER AcpiLengthOffset; +#define ACPI_LENGTH_MASK 0xffff +#define ACPI_OFFSET_MASK 0x0fff0000 +#define ACPI_LENGTH(x) x +#define ACPI_OFFSET(x) ((x) << 16) + + /* Transmit random backoff. */ + T3_32BIT_REGISTER TxBackoffSeed; +#define MAC_TX_BACKOFF_SEED_MASK 0x3ff + + /* Receive MTU */ + T3_32BIT_REGISTER MtuSize; +#define MAC_RX_MTU_MASK 0xffff + + /* Gigabit PCS Test. */ + T3_32BIT_REGISTER PcsTest; +#define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff +#define MAC_PCS_TEST_ENABLE BIT_20 + + /* Transmit Gigabit Auto-Negotiation. */ + T3_32BIT_REGISTER TxAutoNeg; +#define MAC_AN_TX_AN_DATA_MASK 0xffff + + /* Receive Gigabit Auto-Negotiation. */ + T3_32BIT_REGISTER RxAutoNeg; +#define MAC_AN_RX_AN_DATA_MASK 0xffff + + /* MI Communication. */ + T3_32BIT_REGISTER MiCom; +#define MI_COM_CMD_MASK (BIT_26 | BIT_27) +#define MI_COM_CMD_WRITE BIT_26 +#define MI_COM_CMD_READ BIT_27 +#define MI_COM_READ_FAILED BIT_28 +#define MI_COM_START BIT_29 +#define MI_COM_BUSY BIT_29 + +#define MI_COM_PHY_ADDR_MASK 0x1f +#define MI_COM_FIRST_PHY_ADDR_BIT 21 + +#define MI_COM_PHY_REG_ADDR_MASK 0x1f +#define MI_COM_FIRST_PHY_REG_ADDR_BIT 16 + +#define MI_COM_PHY_DATA_MASK 0xffff + + /* MI Status. */ + T3_32BIT_REGISTER MiStatus; +#define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0 + + /* MI Mode. */ + T3_32BIT_REGISTER MiMode; +#define MI_MODE_CLOCK_SPEED_10MHZ BIT_0 +#define MI_MODE_USE_SHORT_PREAMBLE BIT_1 +#define MI_MODE_AUTO_POLLING_ENABLE BIT_4 +#define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15 + + /* Auto-polling status. */ + T3_32BIT_REGISTER AutoPollStatus; +#define AUTO_POLL_ERROR BIT_0 + + /* Transmit MAC mode. */ + T3_32BIT_REGISTER TxMode; +#define TX_MODE_RESET BIT_0 +#define TX_MODE_ENABLE BIT_1 +#define TX_MODE_ENABLE_FLOW_CONTROL BIT_4 +#define TX_MODE_ENABLE_BIG_BACKOFF BIT_5 +#define TX_MODE_ENABLE_LONG_PAUSE BIT_6 + + /* Transmit MAC status. */ + T3_32BIT_REGISTER TxStatus; +#define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0 +#define TX_STATUS_SENT_XOFF BIT_1 +#define TX_STATUS_SENT_XON BIT_2 +#define TX_STATUS_LINK_UP BIT_3 +#define TX_STATUS_ODI_UNDERRUN BIT_4 +#define TX_STATUS_ODI_OVERRUN BIT_5 + + /* Transmit MAC length. */ + T3_32BIT_REGISTER TxLengths; +#define TX_LEN_SLOT_TIME_MASK 0xff +#define TX_LEN_IPG_MASK 0x0f00 +#define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13) + + /* Receive MAC mode. */ + T3_32BIT_REGISTER RxMode; +#define RX_MODE_RESET BIT_0 +#define RX_MODE_ENABLE BIT_1 +#define RX_MODE_ENABLE_FLOW_CONTROL BIT_2 +#define RX_MODE_KEEP_MAC_CONTROL BIT_3 +#define RX_MODE_KEEP_PAUSE BIT_4 +#define RX_MODE_ACCEPT_OVERSIZED BIT_5 +#define RX_MODE_ACCEPT_RUNTS BIT_6 +#define RX_MODE_LENGTH_CHECK BIT_7 +#define RX_MODE_PROMISCUOUS_MODE BIT_8 +#define RX_MODE_NO_CRC_CHECK BIT_9 +#define RX_MODE_KEEP_VLAN_TAG BIT_10 + + /* Receive MAC status. */ + T3_32BIT_REGISTER RxStatus; +#define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0 +#define RX_STATUS_XOFF_RECEIVED BIT_1 +#define RX_STATUS_XON_RECEIVED BIT_2 + + /* Hash registers. */ + T3_32BIT_REGISTER HashReg[4]; + + /* Receive placement rules registers. */ + struct { + T3_32BIT_REGISTER Rule; + T3_32BIT_REGISTER Value; + } RcvRules[16]; + +#define RCV_DISABLE_RULE_MASK 0x7fffffff + +#define RCV_RULE1_REJECT_BROADCAST_IDX 0x00 +#define REJECT_BROADCAST_RULE1_RULE 0xc2000000 +#define REJECT_BROADCAST_RULE1_VALUE 0xffffffff + +#define RCV_RULE2_REJECT_BROADCAST_IDX 0x01 +#define REJECT_BROADCAST_RULE2_RULE 0x86000004 +#define REJECT_BROADCAST_RULE2_VALUE 0xffffffff #if INCLUDE_5701_AX_FIX - #define RCV_LAST_RULE_IDX 0x04 +#define RCV_LAST_RULE_IDX 0x04 #else - #define RCV_LAST_RULE_IDX 0x02 +#define RCV_LAST_RULE_IDX 0x02 #endif - T3_32BIT_REGISTER RcvRuleCfg; - #define RX_RULE_DEFAULT_CLASS (1 << 3) + T3_32BIT_REGISTER RcvRuleCfg; +#define RX_RULE_DEFAULT_CLASS (1 << 3) - LM_UINT8 Reserved1[140]; + LM_UINT8 Reserved1[140]; - T3_32BIT_REGISTER SerdesCfg; - T3_32BIT_REGISTER SerdesStatus; + T3_32BIT_REGISTER SerdesCfg; + T3_32BIT_REGISTER SerdesStatus; - LM_UINT8 Reserved2[104]; + LM_UINT8 Reserved2[104]; - volatile LM_UINT8 TxMacState[16]; - volatile LM_UINT8 RxMacState[20]; + volatile LM_UINT8 TxMacState[16]; + volatile LM_UINT8 RxMacState[20]; - LM_UINT8 Reserved3[476]; + LM_UINT8 Reserved3[476]; - T3_32BIT_REGISTER RxStats[26]; + T3_32BIT_REGISTER RxStats[26]; - LM_UINT8 Reserved4[24]; + LM_UINT8 Reserved4[24]; - T3_32BIT_REGISTER TxStats[28]; + T3_32BIT_REGISTER TxStats[28]; - LM_UINT8 Reserved5[784]; + LM_UINT8 Reserved5[784]; } T3_MAC_CONTROL, *PT3_MAC_CONTROL; - /******************************************************************************/ /* Send data initiator control registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define T3_SND_DATA_IN_MODE_RESET BIT_0 - #define T3_SND_DATA_IN_MODE_ENABLE BIT_1 - #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2 - - T3_32BIT_REGISTER Status; - #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2 - - T3_32BIT_REGISTER StatsCtrl; - #define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0 - #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1 - #define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2 - #define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3 - #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4 - - T3_32BIT_REGISTER StatsEnableMask; - T3_32BIT_REGISTER StatsIncMask; - - LM_UINT8 Reserved[108]; - - T3_32BIT_REGISTER ClassOfServCnt[16]; - T3_32BIT_REGISTER DmaReadQFullCnt; - T3_32BIT_REGISTER DmaPriorityReadQFullCnt; - T3_32BIT_REGISTER SdcQFullCnt; - - T3_32BIT_REGISTER NicRingSetSendProdIdxCnt; - T3_32BIT_REGISTER StatusUpdatedCnt; - T3_32BIT_REGISTER InterruptsCnt; - T3_32BIT_REGISTER AvoidInterruptsCnt; - T3_32BIT_REGISTER SendThresholdHitCnt; - - /* Unused space. */ - LM_UINT8 Unused[800]; -} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR; + T3_32BIT_REGISTER Mode; +#define T3_SND_DATA_IN_MODE_RESET BIT_0 +#define T3_SND_DATA_IN_MODE_ENABLE BIT_1 +#define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; +#define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2 + + T3_32BIT_REGISTER StatsCtrl; +#define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0 +#define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1 +#define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2 +#define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3 +#define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4 + + T3_32BIT_REGISTER StatsEnableMask; + T3_32BIT_REGISTER StatsIncMask; + + LM_UINT8 Reserved[108]; + T3_32BIT_REGISTER ClassOfServCnt[16]; + T3_32BIT_REGISTER DmaReadQFullCnt; + T3_32BIT_REGISTER DmaPriorityReadQFullCnt; + T3_32BIT_REGISTER SdcQFullCnt; + + T3_32BIT_REGISTER NicRingSetSendProdIdxCnt; + T3_32BIT_REGISTER StatusUpdatedCnt; + T3_32BIT_REGISTER InterruptsCnt; + T3_32BIT_REGISTER AvoidInterruptsCnt; + T3_32BIT_REGISTER SendThresholdHitCnt; + + /* Unused space. */ + LM_UINT8 Unused[800]; +} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR; /******************************************************************************/ /* Send data completion control registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define SND_DATA_COMP_MODE_RESET BIT_0 - #define SND_DATA_COMP_MODE_ENABLE BIT_1 + T3_32BIT_REGISTER Mode; +#define SND_DATA_COMP_MODE_RESET BIT_0 +#define SND_DATA_COMP_MODE_ENABLE BIT_1 - /* Unused space. */ - LM_UINT8 Unused[1020]; + /* Unused space. */ + LM_UINT8 Unused[1020]; } T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION; - /******************************************************************************/ /* Send BD Ring Selector Control Registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define SND_BD_SEL_MODE_RESET BIT_0 - #define SND_BD_SEL_MODE_ENABLE BIT_1 - #define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define SND_BD_SEL_MODE_RESET BIT_0 +#define SND_BD_SEL_MODE_ENABLE BIT_1 +#define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2 - T3_32BIT_REGISTER Status; - #define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2 + T3_32BIT_REGISTER Status; +#define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2 - T3_32BIT_REGISTER HwDiag; + T3_32BIT_REGISTER HwDiag; - /* Unused space. */ - LM_UINT8 Unused1[52]; + /* Unused space. */ + LM_UINT8 Unused1[52]; - /* Send BD Ring Selector Local NIC Send BD Consumer Index. */ - T3_32BIT_REGISTER NicSendBdSelConIdx[16]; + /* Send BD Ring Selector Local NIC Send BD Consumer Index. */ + T3_32BIT_REGISTER NicSendBdSelConIdx[16]; - /* Unused space. */ - LM_UINT8 Unused2[896]; + /* Unused space. */ + LM_UINT8 Unused2[896]; } T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR; - /******************************************************************************/ /* Send BD initiator control registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define SND_BD_IN_MODE_RESET BIT_0 - #define SND_BD_IN_MODE_ENABLE BIT_1 - #define SND_BD_IN_MODE_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define SND_BD_IN_MODE_RESET BIT_0 +#define SND_BD_IN_MODE_ENABLE BIT_1 +#define SND_BD_IN_MODE_ATTN_ENABLE BIT_2 - T3_32BIT_REGISTER Status; - #define SND_BD_IN_STATUS_ERROR_ATTN BIT_2 + T3_32BIT_REGISTER Status; +#define SND_BD_IN_STATUS_ERROR_ATTN BIT_2 - /* Send BD initiator local NIC send BD producer index. */ - T3_32BIT_REGISTER NicSendBdInProdIdx[16]; + /* Send BD initiator local NIC send BD producer index. */ + T3_32BIT_REGISTER NicSendBdInProdIdx[16]; - /* Unused space. */ - LM_UINT8 Unused2[952]; + /* Unused space. */ + LM_UINT8 Unused2[952]; } T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR; - /******************************************************************************/ /* Send BD Completion Control. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define SND_BD_COMP_MODE_RESET BIT_0 - #define SND_BD_COMP_MODE_ENABLE BIT_1 - #define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define SND_BD_COMP_MODE_RESET BIT_0 +#define SND_BD_COMP_MODE_ENABLE BIT_1 +#define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2 - /* Unused space. */ - LM_UINT8 Unused2[1020]; + /* Unused space. */ + LM_UINT8 Unused2[1020]; } T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION; - /******************************************************************************/ /* Receive list placement control registers. */ /******************************************************************************/ typedef struct { - /* Mode. */ - T3_32BIT_REGISTER Mode; - #define RCV_LIST_PLMT_MODE_RESET BIT_0 - #define RCV_LIST_PLMT_MODE_ENABLE BIT_1 - #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2 - #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3 - #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4 - - /* Status. */ - T3_32BIT_REGISTER Status; - #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2 - #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3 - #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4 - - /* Receive selector list lock register. */ - T3_32BIT_REGISTER Lock; - #define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff - #define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000 - - /* Selector non-empty bits. */ - T3_32BIT_REGISTER NonEmptyBits; - #define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff - - /* Receive list placement configuration register. */ - T3_32BIT_REGISTER Config; - - /* Receive List Placement statistics Control. */ - T3_32BIT_REGISTER StatsCtrl; + /* Mode. */ + T3_32BIT_REGISTER Mode; +#define RCV_LIST_PLMT_MODE_RESET BIT_0 +#define RCV_LIST_PLMT_MODE_ENABLE BIT_1 +#define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2 +#define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3 +#define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4 + + /* Status. */ + T3_32BIT_REGISTER Status; +#define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2 +#define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3 +#define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4 + + /* Receive selector list lock register. */ + T3_32BIT_REGISTER Lock; +#define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff +#define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000 + + /* Selector non-empty bits. */ + T3_32BIT_REGISTER NonEmptyBits; +#define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff + + /* Receive list placement configuration register. */ + T3_32BIT_REGISTER Config; + + /* Receive List Placement statistics Control. */ + T3_32BIT_REGISTER StatsCtrl; #define RCV_LIST_STATS_ENABLE BIT_0 #define RCV_LIST_STATS_FAST_UPDATE BIT_1 - /* Receive List Placement statistics Enable Mask. */ - T3_32BIT_REGISTER StatsEnableMask; - - /* Receive List Placement statistics Increment Mask. */ - T3_32BIT_REGISTER StatsIncMask; - - /* Unused space. */ - LM_UINT8 Unused1[224]; + /* Receive List Placement statistics Enable Mask. */ + T3_32BIT_REGISTER StatsEnableMask; - struct { - T3_32BIT_REGISTER Head; - T3_32BIT_REGISTER Tail; - T3_32BIT_REGISTER Count; + /* Receive List Placement statistics Increment Mask. */ + T3_32BIT_REGISTER StatsIncMask; /* Unused space. */ - LM_UINT8 Unused[4]; - } RcvSelectorList[16]; - - /* Local statistics counter. */ - T3_32BIT_REGISTER ClassOfServCnt[16]; - - T3_32BIT_REGISTER DropDueToFilterCnt; - T3_32BIT_REGISTER DmaWriteQFullCnt; - T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt; - T3_32BIT_REGISTER NoMoreReceiveBdCnt; - T3_32BIT_REGISTER IfInDiscardsCnt; - T3_32BIT_REGISTER IfInErrorsCnt; - T3_32BIT_REGISTER RcvThresholdHitCnt; - - /* Another unused space. */ - LM_UINT8 Unused2[420]; -} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT; + LM_UINT8 Unused1[224]; + struct { + T3_32BIT_REGISTER Head; + T3_32BIT_REGISTER Tail; + T3_32BIT_REGISTER Count; + + /* Unused space. */ + LM_UINT8 Unused[4]; + } RcvSelectorList[16]; + + /* Local statistics counter. */ + T3_32BIT_REGISTER ClassOfServCnt[16]; + + T3_32BIT_REGISTER DropDueToFilterCnt; + T3_32BIT_REGISTER DmaWriteQFullCnt; + T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt; + T3_32BIT_REGISTER NoMoreReceiveBdCnt; + T3_32BIT_REGISTER IfInDiscardsCnt; + T3_32BIT_REGISTER IfInErrorsCnt; + T3_32BIT_REGISTER RcvThresholdHitCnt; + + /* Another unused space. */ + LM_UINT8 Unused2[420]; +} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT; /******************************************************************************/ /* Receive Data and Receive BD Initiator Control. */ /******************************************************************************/ typedef struct { - /* Mode. */ - T3_32BIT_REGISTER Mode; - #define RCV_DATA_BD_IN_MODE_RESET BIT_0 - #define RCV_DATA_BD_IN_MODE_ENABLE BIT_1 - #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2 - #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3 - #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4 - - /* Status. */ - T3_32BIT_REGISTER Status; - #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2 - #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3 - #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4 - - /* Split frame minium size. */ - T3_32BIT_REGISTER SplitFrameMinSize; - - /* Unused space. */ - LM_UINT8 Unused1[0x2440-0x240c]; - - /* Receive RCBs. */ - T3_RCB JumboRcvRcb; - T3_RCB StdRcvRcb; - T3_RCB MiniRcvRcb; - - /* Receive Data and Receive BD Ring Initiator Local NIC Receive */ - /* BD Consumber Index. */ - T3_32BIT_REGISTER NicJumboConIdx; - T3_32BIT_REGISTER NicStdConIdx; - T3_32BIT_REGISTER NicMiniConIdx; - - /* Unused space. */ - LM_UINT8 Unused2[4]; - - /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */ - T3_32BIT_REGISTER RcvDataBdProdIdx[16]; - - /* Receive Data and Receive BD Initiator Hardware Diagnostic. */ - T3_32BIT_REGISTER HwDiag; - - /* Unused space. */ - LM_UINT8 Unused3[828]; -} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR; + /* Mode. */ + T3_32BIT_REGISTER Mode; +#define RCV_DATA_BD_IN_MODE_RESET BIT_0 +#define RCV_DATA_BD_IN_MODE_ENABLE BIT_1 +#define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2 +#define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3 +#define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4 + + /* Status. */ + T3_32BIT_REGISTER Status; +#define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2 +#define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3 +#define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4 + + /* Split frame minium size. */ + T3_32BIT_REGISTER SplitFrameMinSize; + + /* Unused space. */ + LM_UINT8 Unused1[0x2440 - 0x240c]; + + /* Receive RCBs. */ + T3_RCB JumboRcvRcb; + T3_RCB StdRcvRcb; + T3_RCB MiniRcvRcb; + + /* Receive Data and Receive BD Ring Initiator Local NIC Receive */ + /* BD Consumber Index. */ + T3_32BIT_REGISTER NicJumboConIdx; + T3_32BIT_REGISTER NicStdConIdx; + T3_32BIT_REGISTER NicMiniConIdx; + + /* Unused space. */ + LM_UINT8 Unused2[4]; + + /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */ + T3_32BIT_REGISTER RcvDataBdProdIdx[16]; + /* Receive Data and Receive BD Initiator Hardware Diagnostic. */ + T3_32BIT_REGISTER HwDiag; + + /* Unused space. */ + LM_UINT8 Unused3[828]; +} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR; /******************************************************************************/ /* Receive Data Completion Control Registes. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define RCV_DATA_COMP_MODE_RESET BIT_0 - #define RCV_DATA_COMP_MODE_ENABLE BIT_1 - #define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define RCV_DATA_COMP_MODE_RESET BIT_0 +#define RCV_DATA_COMP_MODE_ENABLE BIT_1 +#define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2 - /* Unused spaced. */ - LM_UINT8 Unused[1020]; + /* Unused spaced. */ + LM_UINT8 Unused[1020]; } T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION; - /******************************************************************************/ /* Receive BD Initiator Control. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define RCV_BD_IN_MODE_RESET BIT_0 - #define RCV_BD_IN_MODE_ENABLE BIT_1 - #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define RCV_BD_IN_MODE_RESET BIT_0 +#define RCV_BD_IN_MODE_ENABLE BIT_1 +#define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2 - T3_32BIT_REGISTER Status; - #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2 + T3_32BIT_REGISTER Status; +#define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2 - T3_32BIT_REGISTER NicJumboRcvProdIdx; - T3_32BIT_REGISTER NicStdRcvProdIdx; - T3_32BIT_REGISTER NicMiniRcvProdIdx; + T3_32BIT_REGISTER NicJumboRcvProdIdx; + T3_32BIT_REGISTER NicStdRcvProdIdx; + T3_32BIT_REGISTER NicMiniRcvProdIdx; - T3_32BIT_REGISTER MiniRcvThreshold; - T3_32BIT_REGISTER StdRcvThreshold; - T3_32BIT_REGISTER JumboRcvThreshold; + T3_32BIT_REGISTER MiniRcvThreshold; + T3_32BIT_REGISTER StdRcvThreshold; + T3_32BIT_REGISTER JumboRcvThreshold; - /* Unused space. */ - LM_UINT8 Unused[992]; + /* Unused space. */ + LM_UINT8 Unused[992]; } T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR; - /******************************************************************************/ /* Receive BD Completion Control Registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define RCV_BD_COMP_MODE_RESET BIT_0 - #define RCV_BD_COMP_MODE_ENABLE BIT_1 - #define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define RCV_BD_COMP_MODE_RESET BIT_0 +#define RCV_BD_COMP_MODE_ENABLE BIT_1 +#define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2 - T3_32BIT_REGISTER Status; - #define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2 + T3_32BIT_REGISTER Status; +#define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2 - T3_32BIT_REGISTER NicJumboRcvBdProdIdx; - T3_32BIT_REGISTER NicStdRcvBdProdIdx; - T3_32BIT_REGISTER NicMiniRcvBdProdIdx; + T3_32BIT_REGISTER NicJumboRcvBdProdIdx; + T3_32BIT_REGISTER NicStdRcvBdProdIdx; + T3_32BIT_REGISTER NicMiniRcvBdProdIdx; - /* Unused space. */ - LM_UINT8 Unused[1004]; + /* Unused space. */ + LM_UINT8 Unused[1004]; } T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION; - /******************************************************************************/ /* Receive list selector control register. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define RCV_LIST_SEL_MODE_RESET BIT_0 - #define RCV_LIST_SEL_MODE_ENABLE BIT_1 - #define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2 + T3_32BIT_REGISTER Mode; +#define RCV_LIST_SEL_MODE_RESET BIT_0 +#define RCV_LIST_SEL_MODE_ENABLE BIT_1 +#define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2 - T3_32BIT_REGISTER Status; - #define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2 + T3_32BIT_REGISTER Status; +#define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2 - /* Unused space. */ - LM_UINT8 Unused[1016]; + /* Unused space. */ + LM_UINT8 Unused[1016]; } T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR; - /******************************************************************************/ /* Mbuf cluster free registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; + T3_32BIT_REGISTER Mode; #define MBUF_CLUSTER_FREE_MODE_RESET BIT_0 #define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1 - T3_32BIT_REGISTER Status; + T3_32BIT_REGISTER Status; - /* Unused space. */ - LM_UINT8 Unused[1016]; + /* Unused space. */ + LM_UINT8 Unused[1016]; } T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE; - /******************************************************************************/ /* Host coalescing control registers. */ /******************************************************************************/ typedef struct { - /* Mode. */ - T3_32BIT_REGISTER Mode; - #define HOST_COALESCE_RESET BIT_0 - #define HOST_COALESCE_ENABLE BIT_1 - #define HOST_COALESCE_ATTN BIT_2 - #define HOST_COALESCE_NOW BIT_3 - #define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE - #define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7 - #define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8 - #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9 - #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10 - #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11 - #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12 + /* Mode. */ + T3_32BIT_REGISTER Mode; +#define HOST_COALESCE_RESET BIT_0 +#define HOST_COALESCE_ENABLE BIT_1 +#define HOST_COALESCE_ATTN BIT_2 +#define HOST_COALESCE_NOW BIT_3 +#define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE +#define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7 +#define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8 +#define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9 +#define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10 +#define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11 +#define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12 - /* Status. */ - T3_32BIT_REGISTER Status; - #define HOST_COALESCE_ERROR_ATTN BIT_2 + /* Status. */ + T3_32BIT_REGISTER Status; +#define HOST_COALESCE_ERROR_ATTN BIT_2 - /* Receive coalescing ticks. */ - T3_32BIT_REGISTER RxCoalescingTicks; + /* Receive coalescing ticks. */ + T3_32BIT_REGISTER RxCoalescingTicks; - /* Send coalescing ticks. */ - T3_32BIT_REGISTER TxCoalescingTicks; + /* Send coalescing ticks. */ + T3_32BIT_REGISTER TxCoalescingTicks; - /* Receive max coalesced frames. */ - T3_32BIT_REGISTER RxMaxCoalescedFrames; + /* Receive max coalesced frames. */ + T3_32BIT_REGISTER RxMaxCoalescedFrames; - /* Send max coalesced frames. */ - T3_32BIT_REGISTER TxMaxCoalescedFrames; + /* Send max coalesced frames. */ + T3_32BIT_REGISTER TxMaxCoalescedFrames; - /* Receive coalescing ticks during interrupt. */ - T3_32BIT_REGISTER RxCoalescedTickDuringInt; + /* Receive coalescing ticks during interrupt. */ + T3_32BIT_REGISTER RxCoalescedTickDuringInt; - /* Send coalescing ticks during interrupt. */ - T3_32BIT_REGISTER TxCoalescedTickDuringInt; + /* Send coalescing ticks during interrupt. */ + T3_32BIT_REGISTER TxCoalescedTickDuringInt; - /* Receive max coalesced frames during interrupt. */ - T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt; + /* Receive max coalesced frames during interrupt. */ + T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt; - /* Send max coalesced frames during interrupt. */ - T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt; + /* Send max coalesced frames during interrupt. */ + T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt; - /* Statistics tick. */ - T3_32BIT_REGISTER StatsCoalescingTicks; + /* Statistics tick. */ + T3_32BIT_REGISTER StatsCoalescingTicks; - /* Unused space. */ - LM_UINT8 Unused2[4]; + /* Unused space. */ + LM_UINT8 Unused2[4]; - /* Statistics host address. */ - T3_64BIT_REGISTER StatsBlkHostAddr; + /* Statistics host address. */ + T3_64BIT_REGISTER StatsBlkHostAddr; - /* Status block host address.*/ - T3_64BIT_REGISTER StatusBlkHostAddr; + /* Status block host address. */ + T3_64BIT_REGISTER StatusBlkHostAddr; - /* Statistics NIC address. */ - T3_32BIT_REGISTER StatsBlkNicAddr; + /* Statistics NIC address. */ + T3_32BIT_REGISTER StatsBlkNicAddr; - /* Statust block NIC address. */ - T3_32BIT_REGISTER StatusBlkNicAddr; + /* Statust block NIC address. */ + T3_32BIT_REGISTER StatusBlkNicAddr; - /* Flow attention registers. */ - T3_32BIT_REGISTER FlowAttn; + /* Flow attention registers. */ + T3_32BIT_REGISTER FlowAttn; - /* Unused space. */ - LM_UINT8 Unused3[4]; + /* Unused space. */ + LM_UINT8 Unused3[4]; - T3_32BIT_REGISTER NicJumboRcvBdConIdx; - T3_32BIT_REGISTER NicStdRcvBdConIdx; - T3_32BIT_REGISTER NicMiniRcvBdConIdx; + T3_32BIT_REGISTER NicJumboRcvBdConIdx; + T3_32BIT_REGISTER NicStdRcvBdConIdx; + T3_32BIT_REGISTER NicMiniRcvBdConIdx; - /* Unused space. */ - LM_UINT8 Unused4[36]; + /* Unused space. */ + LM_UINT8 Unused4[36]; - T3_32BIT_REGISTER NicRetProdIdx[16]; - T3_32BIT_REGISTER NicSndBdConIdx[16]; + T3_32BIT_REGISTER NicRetProdIdx[16]; + T3_32BIT_REGISTER NicSndBdConIdx[16]; - /* Unused space. */ - LM_UINT8 Unused5[768]; + /* Unused space. */ + LM_UINT8 Unused5[768]; } T3_HOST_COALESCING, *PT3_HOST_COALESCING; - /******************************************************************************/ /* Memory arbiter registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; + T3_32BIT_REGISTER Mode; #define T3_MEM_ARBITER_MODE_RESET BIT_0 #define T3_MEM_ARBITER_MODE_ENABLE BIT_1 - T3_32BIT_REGISTER Status; + T3_32BIT_REGISTER Status; - T3_32BIT_REGISTER ArbTrapAddrLow; - T3_32BIT_REGISTER ArbTrapAddrHigh; + T3_32BIT_REGISTER ArbTrapAddrLow; + T3_32BIT_REGISTER ArbTrapAddrHigh; - /* Unused space. */ - LM_UINT8 Unused[1008]; + /* Unused space. */ + LM_UINT8 Unused[1008]; } T3_MEM_ARBITER, *PT3_MEM_ARBITER; - /******************************************************************************/ /* Buffer manager control register. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define BUFMGR_MODE_RESET BIT_0 - #define BUFMGR_MODE_ENABLE BIT_1 - #define BUFMGR_MODE_ATTN_ENABLE BIT_2 - #define BUFMGR_MODE_BM_TEST BIT_3 - #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4 - - T3_32BIT_REGISTER Status; - #define BUFMGR_STATUS_ERROR BIT_2 - #define BUFMGR_STATUS_MBUF_LOW BIT_4 - - T3_32BIT_REGISTER MbufPoolAddr; - T3_32BIT_REGISTER MbufPoolSize; - T3_32BIT_REGISTER MbufReadDmaLowWaterMark; - T3_32BIT_REGISTER MbufMacRxLowWaterMark; - T3_32BIT_REGISTER MbufHighWaterMark; - - T3_32BIT_REGISTER RxCpuMbufAllocReq; - #define BUFMGR_MBUF_ALLOC_BIT BIT_31 - T3_32BIT_REGISTER RxCpuMbufAllocResp; - T3_32BIT_REGISTER TxCpuMbufAllocReq; - T3_32BIT_REGISTER TxCpuMbufAllocResp; - - T3_32BIT_REGISTER DmaDescPoolAddr; - T3_32BIT_REGISTER DmaDescPoolSize; - T3_32BIT_REGISTER DmaLowWaterMark; - T3_32BIT_REGISTER DmaHighWaterMark; - - T3_32BIT_REGISTER RxCpuDmaAllocReq; - T3_32BIT_REGISTER RxCpuDmaAllocResp; - T3_32BIT_REGISTER TxCpuDmaAllocReq; - T3_32BIT_REGISTER TxCpuDmaAllocResp; - - T3_32BIT_REGISTER Hwdiag[3]; - - /* Unused space. */ - LM_UINT8 Unused[936]; -} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER; + T3_32BIT_REGISTER Mode; +#define BUFMGR_MODE_RESET BIT_0 +#define BUFMGR_MODE_ENABLE BIT_1 +#define BUFMGR_MODE_ATTN_ENABLE BIT_2 +#define BUFMGR_MODE_BM_TEST BIT_3 +#define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4 + + T3_32BIT_REGISTER Status; +#define BUFMGR_STATUS_ERROR BIT_2 +#define BUFMGR_STATUS_MBUF_LOW BIT_4 + + T3_32BIT_REGISTER MbufPoolAddr; + T3_32BIT_REGISTER MbufPoolSize; + T3_32BIT_REGISTER MbufReadDmaLowWaterMark; + T3_32BIT_REGISTER MbufMacRxLowWaterMark; + T3_32BIT_REGISTER MbufHighWaterMark; + + T3_32BIT_REGISTER RxCpuMbufAllocReq; +#define BUFMGR_MBUF_ALLOC_BIT BIT_31 + T3_32BIT_REGISTER RxCpuMbufAllocResp; + T3_32BIT_REGISTER TxCpuMbufAllocReq; + T3_32BIT_REGISTER TxCpuMbufAllocResp; + + T3_32BIT_REGISTER DmaDescPoolAddr; + T3_32BIT_REGISTER DmaDescPoolSize; + T3_32BIT_REGISTER DmaLowWaterMark; + T3_32BIT_REGISTER DmaHighWaterMark; + + T3_32BIT_REGISTER RxCpuDmaAllocReq; + T3_32BIT_REGISTER RxCpuDmaAllocResp; + T3_32BIT_REGISTER TxCpuDmaAllocReq; + T3_32BIT_REGISTER TxCpuDmaAllocResp; + + T3_32BIT_REGISTER Hwdiag[3]; + /* Unused space. */ + LM_UINT8 Unused[936]; +} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER; /******************************************************************************/ /* Read DMA control registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define DMA_READ_MODE_RESET BIT_0 - #define DMA_READ_MODE_ENABLE BIT_1 - #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 - #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 - #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 - #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 - #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 - #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 - #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 - #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9 - #define DMA_READ_MODE_SPLIT_ENABLE BIT_11 - #define DMA_READ_MODE_SPLIT_RESET BIT_12 - - T3_32BIT_REGISTER Status; - #define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2 - #define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3 - #define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4 - #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5 - #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6 - #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7 - #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8 - #define DMA_READ_STATUS_LONG_READ_ATTN BIT_9 - - /* Unused space. */ - LM_UINT8 Unused[1016]; + T3_32BIT_REGISTER Mode; +#define DMA_READ_MODE_RESET BIT_0 +#define DMA_READ_MODE_ENABLE BIT_1 +#define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 +#define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 +#define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 +#define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 +#define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 +#define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 +#define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 +#define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9 +#define DMA_READ_MODE_SPLIT_ENABLE BIT_11 +#define DMA_READ_MODE_SPLIT_RESET BIT_12 + + T3_32BIT_REGISTER Status; +#define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2 +#define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3 +#define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4 +#define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5 +#define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6 +#define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7 +#define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8 +#define DMA_READ_STATUS_LONG_READ_ATTN BIT_9 + + /* Unused space. */ + LM_UINT8 Unused[1016]; } T3_DMA_READ, *PT3_DMA_READ; -typedef union T3_CPU -{ - struct - { - T3_32BIT_REGISTER mode; - #define CPU_MODE_HALT BIT_10 - #define CPU_MODE_RESET BIT_0 - T3_32BIT_REGISTER state; - T3_32BIT_REGISTER EventMask; - T3_32BIT_REGISTER reserved1[4]; - T3_32BIT_REGISTER PC; - T3_32BIT_REGISTER Instruction; - T3_32BIT_REGISTER SpadUnderflow; - T3_32BIT_REGISTER WatchdogClear; - T3_32BIT_REGISTER WatchdogVector; - T3_32BIT_REGISTER WatchdogSavedPC; - T3_32BIT_REGISTER HardwareBp; - T3_32BIT_REGISTER reserved2[3]; - T3_32BIT_REGISTER WatchdogSavedState; - T3_32BIT_REGISTER LastBrchAddr; - T3_32BIT_REGISTER SpadUnderflowSet; - T3_32BIT_REGISTER reserved3[(0x200-0x50)/4]; - T3_32BIT_REGISTER Regs[32]; - T3_32BIT_REGISTER reserved4[(0x400-0x280)/4]; - }reg; -}T3_CPU, *PT3_CPU; +typedef union T3_CPU { + struct { + T3_32BIT_REGISTER mode; +#define CPU_MODE_HALT BIT_10 +#define CPU_MODE_RESET BIT_0 + T3_32BIT_REGISTER state; + T3_32BIT_REGISTER EventMask; + T3_32BIT_REGISTER reserved1[4]; + T3_32BIT_REGISTER PC; + T3_32BIT_REGISTER Instruction; + T3_32BIT_REGISTER SpadUnderflow; + T3_32BIT_REGISTER WatchdogClear; + T3_32BIT_REGISTER WatchdogVector; + T3_32BIT_REGISTER WatchdogSavedPC; + T3_32BIT_REGISTER HardwareBp; + T3_32BIT_REGISTER reserved2[3]; + T3_32BIT_REGISTER WatchdogSavedState; + T3_32BIT_REGISTER LastBrchAddr; + T3_32BIT_REGISTER SpadUnderflowSet; + T3_32BIT_REGISTER reserved3[(0x200 - 0x50) / 4]; + T3_32BIT_REGISTER Regs[32]; + T3_32BIT_REGISTER reserved4[(0x400 - 0x280) / 4]; + } reg; +} T3_CPU, *PT3_CPU; /******************************************************************************/ /* Write DMA control registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define DMA_WRITE_MODE_RESET BIT_0 - #define DMA_WRITE_MODE_ENABLE BIT_1 - #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 - #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 - #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 - #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 - #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 - #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 - #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 - #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9 - - T3_32BIT_REGISTER Status; - #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2 - #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3 - #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4 - #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5 - #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6 - #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7 - #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8 - #define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9 - - /* Unused space. */ - LM_UINT8 Unused[1016]; -} T3_DMA_WRITE, *PT3_DMA_WRITE; + T3_32BIT_REGISTER Mode; +#define DMA_WRITE_MODE_RESET BIT_0 +#define DMA_WRITE_MODE_ENABLE BIT_1 +#define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 +#define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 +#define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 +#define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 +#define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 +#define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 +#define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 +#define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9 + + T3_32BIT_REGISTER Status; +#define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2 +#define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3 +#define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4 +#define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5 +#define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6 +#define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7 +#define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8 +#define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9 + /* Unused space. */ + LM_UINT8 Unused[1016]; +} T3_DMA_WRITE, *PT3_DMA_WRITE; /******************************************************************************/ /* Mailbox registers. */ /******************************************************************************/ typedef struct { - /* Interrupt mailbox registers. */ - T3_64BIT_REGISTER Interrupt[4]; + /* Interrupt mailbox registers. */ + T3_64BIT_REGISTER Interrupt[4]; - /* General mailbox registers. */ - T3_64BIT_REGISTER General[8]; + /* General mailbox registers. */ + T3_64BIT_REGISTER General[8]; - /* Reload statistics mailbox. */ - T3_64BIT_REGISTER ReloadStat; + /* Reload statistics mailbox. */ + T3_64BIT_REGISTER ReloadStat; - /* Receive BD ring producer index registers. */ - T3_64BIT_REGISTER RcvStdProdIdx; - T3_64BIT_REGISTER RcvJumboProdIdx; - T3_64BIT_REGISTER RcvMiniProdIdx; + /* Receive BD ring producer index registers. */ + T3_64BIT_REGISTER RcvStdProdIdx; + T3_64BIT_REGISTER RcvJumboProdIdx; + T3_64BIT_REGISTER RcvMiniProdIdx; - /* Receive return ring consumer index registers. */ - T3_64BIT_REGISTER RcvRetConIdx[16]; + /* Receive return ring consumer index registers. */ + T3_64BIT_REGISTER RcvRetConIdx[16]; - /* Send BD ring host producer index registers. */ - T3_64BIT_REGISTER SendHostProdIdx[16]; + /* Send BD ring host producer index registers. */ + T3_64BIT_REGISTER SendHostProdIdx[16]; - /* Send BD ring nic producer index registers. */ - T3_64BIT_REGISTER SendNicProdIdx[16]; -}T3_MAILBOX, *PT3_MAILBOX; + /* Send BD ring nic producer index registers. */ + T3_64BIT_REGISTER SendNicProdIdx[16]; +} T3_MAILBOX, *PT3_MAILBOX; typedef struct { - T3_MAILBOX Mailbox; + T3_MAILBOX Mailbox; - /* Priority mailbox registers. */ - T3_32BIT_REGISTER HighPriorityEventVector; - T3_32BIT_REGISTER HighPriorityEventMask; - T3_32BIT_REGISTER LowPriorityEventVector; - T3_32BIT_REGISTER LowPriorityEventMask; + /* Priority mailbox registers. */ + T3_32BIT_REGISTER HighPriorityEventVector; + T3_32BIT_REGISTER HighPriorityEventMask; + T3_32BIT_REGISTER LowPriorityEventVector; + T3_32BIT_REGISTER LowPriorityEventMask; - /* Unused space. */ - LM_UINT8 Unused[496]; + /* Unused space. */ + LM_UINT8 Unused[496]; } T3_GRC_MAILBOX, *PT3_GRC_MAILBOX; - /******************************************************************************/ /* Flow through queues. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Reset; - - LM_UINT8 Unused[12]; - - T3_32BIT_REGISTER DmaNormalReadFtqCtrl; - T3_32BIT_REGISTER DmaNormalReadFtqFullCnt; - T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek; - - T3_32BIT_REGISTER DmaHighReadFtqCtrl; - T3_32BIT_REGISTER DmaHighReadFtqFullCnt; - T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek; - - T3_32BIT_REGISTER DmaCompDiscardFtqCtrl; - T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt; - T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek; - - T3_32BIT_REGISTER SendBdCompFtqCtrl; - T3_32BIT_REGISTER SendBdCompFtqFullCnt; - T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek; - - T3_32BIT_REGISTER SendDataInitiatorFtqCtrl; - T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt; - T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek; - - T3_32BIT_REGISTER DmaNormalWriteFtqCtrl; - T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt; - T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek; - - T3_32BIT_REGISTER DmaHighWriteFtqCtrl; - T3_32BIT_REGISTER DmaHighWriteFtqFullCnt; - T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek; - - T3_32BIT_REGISTER SwType1FtqCtrl; - T3_32BIT_REGISTER SwType1FtqFullCnt; - T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue; - T3_32BIT_REGISTER SwType1FtqFifoWritePeek; - - T3_32BIT_REGISTER SendDataCompFtqCtrl; - T3_32BIT_REGISTER SendDataCompFtqFullCnt; - T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek; - - T3_32BIT_REGISTER HostCoalesceFtqCtrl; - T3_32BIT_REGISTER HostCoalesceFtqFullCnt; - T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek; - - T3_32BIT_REGISTER MacTxFtqCtrl; - T3_32BIT_REGISTER MacTxFtqFullCnt; - T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER MacTxFtqFifoWritePeek; - - T3_32BIT_REGISTER MbufClustFreeFtqCtrl; - T3_32BIT_REGISTER MbufClustFreeFtqFullCnt; - T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek; - - T3_32BIT_REGISTER RcvBdCompFtqCtrl; - T3_32BIT_REGISTER RcvBdCompFtqFullCnt; - T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek; - - T3_32BIT_REGISTER RcvListPlmtFtqCtrl; - T3_32BIT_REGISTER RcvListPlmtFtqFullCnt; - T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek; - - T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl; - T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt; - T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek; - - T3_32BIT_REGISTER RcvDataCompFtqCtrl; - T3_32BIT_REGISTER RcvDataCompFtqFullCnt; - T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue; - T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek; - - T3_32BIT_REGISTER SwType2FtqCtrl; - T3_32BIT_REGISTER SwType2FtqFullCnt; - T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue; - T3_32BIT_REGISTER SwType2FtqFifoWritePeek; - - /* Unused space. */ - LM_UINT8 Unused2[736]; -} T3_FTQ, *PT3_FTQ; + T3_32BIT_REGISTER Reset; + + LM_UINT8 Unused[12]; + + T3_32BIT_REGISTER DmaNormalReadFtqCtrl; + T3_32BIT_REGISTER DmaNormalReadFtqFullCnt; + T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek; + + T3_32BIT_REGISTER DmaHighReadFtqCtrl; + T3_32BIT_REGISTER DmaHighReadFtqFullCnt; + T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek; + + T3_32BIT_REGISTER DmaCompDiscardFtqCtrl; + T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt; + T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek; + + T3_32BIT_REGISTER SendBdCompFtqCtrl; + T3_32BIT_REGISTER SendBdCompFtqFullCnt; + T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek; + + T3_32BIT_REGISTER SendDataInitiatorFtqCtrl; + T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt; + T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek; + + T3_32BIT_REGISTER DmaNormalWriteFtqCtrl; + T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt; + T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek; + + T3_32BIT_REGISTER DmaHighWriteFtqCtrl; + T3_32BIT_REGISTER DmaHighWriteFtqFullCnt; + T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek; + + T3_32BIT_REGISTER SwType1FtqCtrl; + T3_32BIT_REGISTER SwType1FtqFullCnt; + T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SwType1FtqFifoWritePeek; + + T3_32BIT_REGISTER SendDataCompFtqCtrl; + T3_32BIT_REGISTER SendDataCompFtqFullCnt; + T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek; + + T3_32BIT_REGISTER HostCoalesceFtqCtrl; + T3_32BIT_REGISTER HostCoalesceFtqFullCnt; + T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek; + + T3_32BIT_REGISTER MacTxFtqCtrl; + T3_32BIT_REGISTER MacTxFtqFullCnt; + T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER MacTxFtqFifoWritePeek; + + T3_32BIT_REGISTER MbufClustFreeFtqCtrl; + T3_32BIT_REGISTER MbufClustFreeFtqFullCnt; + T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek; + + T3_32BIT_REGISTER RcvBdCompFtqCtrl; + T3_32BIT_REGISTER RcvBdCompFtqFullCnt; + T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek; + + T3_32BIT_REGISTER RcvListPlmtFtqCtrl; + T3_32BIT_REGISTER RcvListPlmtFtqFullCnt; + T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek; + + T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek; + + T3_32BIT_REGISTER RcvDataCompFtqCtrl; + T3_32BIT_REGISTER RcvDataCompFtqFullCnt; + T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek; + + T3_32BIT_REGISTER SwType2FtqCtrl; + T3_32BIT_REGISTER SwType2FtqFullCnt; + T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SwType2FtqFifoWritePeek; + /* Unused space. */ + LM_UINT8 Unused2[736]; +} T3_FTQ, *PT3_FTQ; /******************************************************************************/ /* Message signaled interrupt registers. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; + T3_32BIT_REGISTER Mode; #define MSI_MODE_RESET BIT_0 #define MSI_MODE_ENABLE BIT_1 - T3_32BIT_REGISTER Status; + T3_32BIT_REGISTER Status; - T3_32BIT_REGISTER MsiFifoAccess; + T3_32BIT_REGISTER MsiFifoAccess; - /* Unused space. */ - LM_UINT8 Unused[1012]; + /* Unused space. */ + LM_UINT8 Unused[1012]; } T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT; - /******************************************************************************/ /* DMA Completion registes. */ /******************************************************************************/ typedef struct { - T3_32BIT_REGISTER Mode; - #define DMA_COMP_MODE_RESET BIT_0 - #define DMA_COMP_MODE_ENABLE BIT_1 + T3_32BIT_REGISTER Mode; +#define DMA_COMP_MODE_RESET BIT_0 +#define DMA_COMP_MODE_ENABLE BIT_1 - /* Unused space. */ - LM_UINT8 Unused[1020]; + /* Unused space. */ + LM_UINT8 Unused[1020]; } T3_DMA_COMPLETION, *PT3_DMA_COMPLETION; - /******************************************************************************/ /* GRC registers. */ /******************************************************************************/ typedef struct { - /* Mode control register. */ - T3_32BIT_REGISTER Mode; - #define GRC_MODE_UPDATE_ON_COALESCING BIT_0 - #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1 - #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2 - #define GRC_MODE_BYTE_SWAP_DATA BIT_4 - #define GRC_MODE_WORD_SWAP_DATA BIT_5 - #define GRC_MODE_SPLIT_HEADER_MODE BIT_8 - #define GRC_MODE_NO_FRAME_CRACKING BIT_9 - #define GRC_MODE_INCLUDE_CRC BIT_10 - #define GRC_MODE_ALLOW_BAD_FRAMES BIT_11 - #define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13 - #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14 - #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15 - #define GRC_MODE_HOST_STACK_UP BIT_16 - #define GRC_MODE_HOST_SEND_BDS BIT_17 - #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20 - #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23 - #define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24 - #define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25 - #define GRC_MODE_INT_ON_MAC_ATTN BIT_26 - #define GRC_MODE_INT_ON_DMA_ATTN BIT_27 - #define GRC_MODE_INT_ON_FLOW_ATTN BIT_28 - #define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29 - #define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30 - - /* Misc configuration register. */ - T3_32BIT_REGISTER MiscCfg; - #define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0 - #define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe - #define GRC_MISC_BD_ID_MASK 0x0001e000 - #define GRC_MISC_BD_ID_5700 0x0001e000 - #define GRC_MISC_BD_ID_5701 0x00000000 - #define GRC_MISC_BD_ID_5703 0x00000000 - #define GRC_MISC_BD_ID_5703S 0x00002000 - #define GRC_MISC_BD_ID_5702FE 0x00004000 - #define GRC_MISC_BD_ID_5704 0x00000000 - #define GRC_MISC_BD_ID_5704CIOBE 0x00004000 - - /* Miscellaneous local control register. */ - T3_32BIT_REGISTER LocalCtrl; - #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0 - #define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1 - #define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2 - #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3 - #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8 - #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9 - #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10 - #define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11 - #define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12 - #define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13 - #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14 - #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15 - #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16 - #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17 - #define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21 - #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22 - - #define GRC_MISC_MEMSIZE_256K 0 - #define GRC_MISC_MEMSIZE_512K (1 << 18) - #define GRC_MISC_MEMSIZE_1024K (2 << 18) - #define GRC_MISC_MEMSIZE_2048K (3 << 18) - #define GRC_MISC_MEMSIZE_4096K (4 << 18) - #define GRC_MISC_MEMSIZE_8192K (5 << 18) - #define GRC_MISC_MEMSIZE_16M (6 << 18) - #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24 - - - T3_32BIT_REGISTER Timer; - - T3_32BIT_REGISTER RxCpuEvent; - T3_32BIT_REGISTER RxTimerRef; - T3_32BIT_REGISTER RxCpuSemaphore; - T3_32BIT_REGISTER RemoteRxCpuAttn; - - T3_32BIT_REGISTER TxCpuEvent; - T3_32BIT_REGISTER TxTimerRef; - T3_32BIT_REGISTER TxCpuSemaphore; - T3_32BIT_REGISTER RemoteTxCpuAttn; - - T3_64BIT_REGISTER MemoryPowerUp; - - T3_32BIT_REGISTER EepromAddr; - #define SEEPROM_ADDR_WRITE 0 - #define SEEPROM_ADDR_READ (1 << 31) - #define SEEPROM_ADDR_RW_MASK 0x80000000 - #define SEEPROM_ADDR_COMPLETE (1 << 30) - #define SEEPROM_ADDR_FSM_RESET (1 << 29) - #define SEEPROM_ADDR_DEV_ID(x) (x << 26) - #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000 - #define SEEPROM_ADDR_START (1 << 25) - #define SEEPROM_ADDR_CLK_PERD(x) (x << 16) - #define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc) - #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff - - #define SEEPROM_CLOCK_PERIOD 60 - #define SEEPROM_CHIP_SIZE (64 * 1024) - - T3_32BIT_REGISTER EepromData; - T3_32BIT_REGISTER EepromCtrl; - - T3_32BIT_REGISTER MdiCtrl; - T3_32BIT_REGISTER SepromDelay; - - /* Unused space. */ - LM_UINT8 Unused[948]; -} T3_GRC, *PT3_GRC; + /* Mode control register. */ + T3_32BIT_REGISTER Mode; +#define GRC_MODE_UPDATE_ON_COALESCING BIT_0 +#define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1 +#define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2 +#define GRC_MODE_BYTE_SWAP_DATA BIT_4 +#define GRC_MODE_WORD_SWAP_DATA BIT_5 +#define GRC_MODE_SPLIT_HEADER_MODE BIT_8 +#define GRC_MODE_NO_FRAME_CRACKING BIT_9 +#define GRC_MODE_INCLUDE_CRC BIT_10 +#define GRC_MODE_ALLOW_BAD_FRAMES BIT_11 +#define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13 +#define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14 +#define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15 +#define GRC_MODE_HOST_STACK_UP BIT_16 +#define GRC_MODE_HOST_SEND_BDS BIT_17 +#define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20 +#define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23 +#define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24 +#define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25 +#define GRC_MODE_INT_ON_MAC_ATTN BIT_26 +#define GRC_MODE_INT_ON_DMA_ATTN BIT_27 +#define GRC_MODE_INT_ON_FLOW_ATTN BIT_28 +#define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29 +#define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30 + + /* Misc configuration register. */ + T3_32BIT_REGISTER MiscCfg; +#define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0 +#define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe +#define GRC_MISC_BD_ID_MASK 0x0001e000 +#define GRC_MISC_BD_ID_5700 0x0001e000 +#define GRC_MISC_BD_ID_5701 0x00000000 +#define GRC_MISC_BD_ID_5703 0x00000000 +#define GRC_MISC_BD_ID_5703S 0x00002000 +#define GRC_MISC_BD_ID_5702FE 0x00004000 +#define GRC_MISC_BD_ID_5704 0x00000000 +#define GRC_MISC_BD_ID_5704CIOBE 0x00004000 + + /* Miscellaneous local control register. */ + T3_32BIT_REGISTER LocalCtrl; +#define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0 +#define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1 +#define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2 +#define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3 +#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8 +#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9 +#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10 +#define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11 +#define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12 +#define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13 +#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14 +#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15 +#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16 +#define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17 +#define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21 +#define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22 + +#define GRC_MISC_MEMSIZE_256K 0 +#define GRC_MISC_MEMSIZE_512K (1 << 18) +#define GRC_MISC_MEMSIZE_1024K (2 << 18) +#define GRC_MISC_MEMSIZE_2048K (3 << 18) +#define GRC_MISC_MEMSIZE_4096K (4 << 18) +#define GRC_MISC_MEMSIZE_8192K (5 << 18) +#define GRC_MISC_MEMSIZE_16M (6 << 18) +#define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24 + + T3_32BIT_REGISTER Timer; + + T3_32BIT_REGISTER RxCpuEvent; + T3_32BIT_REGISTER RxTimerRef; + T3_32BIT_REGISTER RxCpuSemaphore; + T3_32BIT_REGISTER RemoteRxCpuAttn; + + T3_32BIT_REGISTER TxCpuEvent; + T3_32BIT_REGISTER TxTimerRef; + T3_32BIT_REGISTER TxCpuSemaphore; + T3_32BIT_REGISTER RemoteTxCpuAttn; + + T3_64BIT_REGISTER MemoryPowerUp; + + T3_32BIT_REGISTER EepromAddr; +#define SEEPROM_ADDR_WRITE 0 +#define SEEPROM_ADDR_READ (1 << 31) +#define SEEPROM_ADDR_RW_MASK 0x80000000 +#define SEEPROM_ADDR_COMPLETE (1 << 30) +#define SEEPROM_ADDR_FSM_RESET (1 << 29) +#define SEEPROM_ADDR_DEV_ID(x) (x << 26) +#define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000 +#define SEEPROM_ADDR_START (1 << 25) +#define SEEPROM_ADDR_CLK_PERD(x) (x << 16) +#define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc) +#define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff + +#define SEEPROM_CLOCK_PERIOD 60 +#define SEEPROM_CHIP_SIZE (64 * 1024) + + T3_32BIT_REGISTER EepromData; + T3_32BIT_REGISTER EepromCtrl; + + T3_32BIT_REGISTER MdiCtrl; + T3_32BIT_REGISTER SepromDelay; + /* Unused space. */ + LM_UINT8 Unused[948]; +} T3_GRC, *PT3_GRC; /******************************************************************************/ /* NVRAM control registers. */ /******************************************************************************/ -typedef struct -{ - T3_32BIT_REGISTER Cmd; - #define NVRAM_CMD_RESET BIT_0 - #define NVRAM_CMD_DONE BIT_3 - #define NVRAM_CMD_DO_IT BIT_4 - #define NVRAM_CMD_WR BIT_5 - #define NVRAM_CMD_RD BIT_NONE - #define NVRAM_CMD_ERASE BIT_6 - #define NVRAM_CMD_FIRST BIT_7 - #define NVRAM_CMD_LAST BIT_8 - - T3_32BIT_REGISTER Status; - T3_32BIT_REGISTER WriteData; - - T3_32BIT_REGISTER Addr; - #define NVRAM_ADDRESS_MASK 0xffffff - - T3_32BIT_REGISTER ReadData; - - /* Flash config 1 register. */ - T3_32BIT_REGISTER Config1; - #define FLASH_INTERFACE_ENABLE BIT_0 - #define FLASH_SSRAM_BUFFERRED_MODE BIT_1 - #define FLASH_PASS_THRU_MODE BIT_2 - #define FLASH_BIT_BANG_MODE BIT_3 - #define FLASH_COMPAT_BYPASS BIT_31 - - /* Buffered flash (Atmel: AT45DB011B) specific information */ - #define BUFFERED_FLASH_PAGE_POS 9 - #define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<pMemView + Offset)) - /* There could be problem access the memory window directly. For now, */ /* we have to go through the PCI configuration register. */ #define MEM_RD(pDevice, AddrName) \ @@ -3368,9 +3277,9 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, #define MEM_WR_OFFSET(pDevice, Offset, Value32) \ LM_MemWrInd(pDevice, Offset, Value32) -#endif /* PCIX_TARGET_WORKAROUND */ +#endif /* PCIX_TARGET_WORKAROUND */ -#endif /* Jimmy, merging */ +#endif /* Jimmy, merging */ /* Jimmy...rest of file is new stuff! */ /******************************************************************************/ @@ -3378,14 +3287,14 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, /******************************************************************************/ /* MAC register access. */ -LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); -LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, - LM_UINT32 Value32); +LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); +LM_VOID LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, + LM_UINT32 Value32); /* MAC memory access. */ -LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr); -LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, - LM_UINT32 Value32); +LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr); +LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, + LM_UINT32 Value32); #define MB_REG_WR(pDevice, OffsetName, Value32) \ ((pDevice)->UndiFix) ? \ @@ -3427,4 +3336,4 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, #define MEM_WR_OFFSET(pDevice, Offset, Value32) \ LM_MemWrInd(pDevice, Offset, Value32) -#endif /* TIGON3_H */ +#endif /* TIGON3_H */ -- cgit v1.3.1 From 8e585f02f82c17cc66cd229dbf0fd3066bbbf658 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Mon, 18 Jun 2007 13:50:13 -0500 Subject: Added M5329AFEE and M5329BFEE Platforms Added board/freescale/m5329evb, cpu/mcf532x, drivers/net, drivers/serial, immap_5329.h, m5329.h, mcfrtc.h, include/configs/M5329EVB.h, lib_m68k/interrupts.c, and rtc/mcfrtc.c Modified CREDITS, MAKEFILE, Makefile, README, common/cmd_bdinfo.c, common/cmd_mii.c, include/asm-m68k/byteorder.h, include/asm-m68k/fec.h, include/asm-m68k/io.h, include/asm-m68k/mcftimer.h, include/asm-m68k/mcfuart.h, include/asm-m68k/ptrace.h, include/asm-m68k/u-boot.h, lib_m68k/Makefile, lib_m68k/board.c, lib_m68k/time.c, net/eth.c and rtc/Makefile Signed-off-by: TsiChung Liew --- CREDITS | 6 + MAKEALL | 2 +- Makefile | 14 + README | 5 + board/freescale/m5329evb/Makefile | 44 + board/freescale/m5329evb/config.mk | 25 + board/freescale/m5329evb/flash.c | 643 +++++++++++ board/freescale/m5329evb/m5329evb.c | 376 +++++++ board/freescale/m5329evb/u-boot.lds | 144 +++ common/cmd_bdinfo.c | 53 + common/cmd_mii.c | 2 +- cpu/mcf532x/Makefile | 48 + cpu/mcf532x/config.mk | 27 + cpu/mcf532x/cpu.c | 134 +++ cpu/mcf532x/cpu_init.c | 126 +++ cpu/mcf532x/speed.c | 222 ++++ cpu/mcf532x/start.S | 338 ++++++ drivers/net/Makefile | 45 + drivers/net/mcffec.c | 594 ++++++++++ drivers/serial/Makefile | 45 + drivers/serial/mcfserial.c | 126 +++ include/asm-m68k/byteorder.h | 102 +- include/asm-m68k/fec.h | 241 ++++- include/asm-m68k/immap_5329.h | 793 ++++++++++++++ include/asm-m68k/io.h | 214 +++- include/asm-m68k/m5329.h | 2023 +++++++++++++++++++++++++++++++++++ include/asm-m68k/mcfrtc.h | 108 ++ include/asm-m68k/mcftimer.h | 144 ++- include/asm-m68k/mcfuart.h | 328 ++++-- include/asm-m68k/ptrace.h | 44 +- include/asm-m68k/u-boot.h | 48 +- include/configs/M5329EVB.h | 275 +++++ lib_m68k/Makefile | 2 +- lib_m68k/board.c | 67 +- lib_m68k/interrupts.c | 118 ++ lib_m68k/time.c | 167 ++- net/eth.c | 1 + rtc/Makefile | 3 +- rtc/mcfrtc.c | 120 +++ 39 files changed, 7629 insertions(+), 188 deletions(-) mode change 100755 => 100644 MAKEALL mode change 100644 => 100755 Makefile create mode 100644 board/freescale/m5329evb/Makefile create mode 100644 board/freescale/m5329evb/config.mk create mode 100644 board/freescale/m5329evb/flash.c create mode 100644 board/freescale/m5329evb/m5329evb.c create mode 100644 board/freescale/m5329evb/u-boot.lds create mode 100644 cpu/mcf532x/Makefile create mode 100644 cpu/mcf532x/config.mk create mode 100644 cpu/mcf532x/cpu.c create mode 100644 cpu/mcf532x/cpu_init.c create mode 100644 cpu/mcf532x/speed.c create mode 100644 cpu/mcf532x/start.S create mode 100644 drivers/net/Makefile create mode 100644 drivers/net/mcffec.c create mode 100644 drivers/serial/Makefile create mode 100644 drivers/serial/mcfserial.c create mode 100644 include/asm-m68k/immap_5329.h create mode 100644 include/asm-m68k/m5329.h create mode 100644 include/asm-m68k/mcfrtc.h create mode 100644 include/configs/M5329EVB.h create mode 100644 lib_m68k/interrupts.c create mode 100644 rtc/mcfrtc.c (limited to 'drivers') diff --git a/CREDITS b/CREDITS index 7af1b806ab0..8558a401292 100644 --- a/CREDITS +++ b/CREDITS @@ -479,3 +479,9 @@ N: Michal Simek E: monstr@monstr.eu D: Support for Microblaze, ML401, XUPV2P board W: www.monstr.eu + +N: TsiChung Liew +E: Tsi-Chung.Liew@freescale.com +D: Support for ColdFire MCF532x +W: www.freescale.com + diff --git a/MAKEALL b/MAKEALL old mode 100755 new mode 100644 index 0e4e7440937..22c6c6da293 --- a/MAKEALL +++ b/MAKEALL @@ -306,7 +306,7 @@ LIST_microblaze=" \ LIST_coldfire=" \ cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \ idmr M5271EVB M5272C3 M5282EVB \ - TASREG r5200 M5271EVB \ + TASREG r5200 M5271EVB M5329EVB \ " ######################################################################### diff --git a/Makefile b/Makefile old mode 100644 new mode 100755 index d5e220aadde..8a728a4328b --- a/Makefile +++ b/Makefile @@ -207,9 +207,11 @@ LIBS += dtt/libdtt.a LIBS += drivers/libdrivers.a LIBS += drivers/nand/libnand.a LIBS += drivers/nand_legacy/libnand_legacy.a +LIBS += drivers/net/libnet.a ifeq ($(CPU),mpc83xx) LIBS += drivers/qe/qe.a endif +LIBS += drivers/serial/libserial.a LIBS += drivers/sk98lin/libsk98lin.a LIBS += post/libpost.a post/drivers/libpostdrivers.a LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \ @@ -1637,6 +1639,18 @@ TASREG_config : unconfig r5200_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200 +M5329AFEE_config \ +M5329BFEE_config : unconfig + @case "$@" in \ + M5329AFEE_config) NAND=0;; \ + M5329BFEE_config) NAND=16;; \ + esac; \ + >include/config.h ; \ + if [ "$${NAND}" != "0" ] ; then \ + echo "#define NANDFLASH_SIZE $${NAND}" >> include/config.h ; \ + fi + @$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale + ######################################################################### ## MPC83xx Systems ######################################################################### diff --git a/README b/README index bb5b46e3379..dd12cd7ee5a 100644 --- a/README +++ b/README @@ -136,6 +136,7 @@ Directory Hierarchy: - i386 Files specific to i386 CPUs - ixp Files specific to Intel XScale IXP CPUs - mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs + - mcf532x Files specific to Freescale ColdFire MCF5329 CPUs - mips Files specific to MIPS CPUs - mpc5xx Files specific to Freescale MPC5xx CPUs - mpc5xxx Files specific to Freescale MPC5xxx CPUs @@ -251,6 +252,10 @@ The following options need to be configured: CONFIG_PXA250 CONFIG_CPU_MONAHANS + ColdFire based CPUs: + -------------------- + CONFIG_M5329 + MicroBlaze based CPUs: ---------------------- CONFIG_MICROBLAZE diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile new file mode 100644 index 00000000000..f94ee9d1391 --- /dev/null +++ b/board/freescale/m5329evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5329evb/config.mk b/board/freescale/m5329evb/config.mk new file mode 100644 index 00000000000..ce014edca8f --- /dev/null +++ b/board/freescale/m5329evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0 diff --git a/board/freescale/m5329evb/flash.c b/board/freescale/m5329evb/flash.c new file mode 100644 index 00000000000..7d3b0e84d22 --- /dev/null +++ b/board/freescale/m5329evb/flash.c @@ -0,0 +1,643 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifndef CFG_FLASH_CFI + +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; + +#define PHYS_FLASH_1 CFG_FLASH_BASE +#define FLASH_BANK_SIZE 0x200000 + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x00100010 +#define INTEL_ERASE 0x00200020 +#define INTEL_WRSETUP 0x00400040 +#define INTEL_CLEAR 0x00500050 +#define INTEL_LOCKBIT 0x00600060 +#define INTEL_PROTECT 0x00010001 +#define INTEL_STATUS 0x00700070 +#define INTEL_READID 0x00900090 +#define INTEL_CFIQRY 0x00980098 +#define INTEL_SUSERASE 0x00B000B0 +#define INTEL_PROTPROG 0x00C000C0 +#define INTEL_CONFIRM 0x00D000D0 +#define INTEL_RESET 0x00FF00FF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x00800080 +#define INTEL_OK 0x00800080 +#define INTEL_ERASESUS 0x00600060 +#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS) + +/* 28F160C3B CFI Data offset - This could vary */ +#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */ +#define INTEL_CFI_PART 0x01 /* Product ID */ +#define INTEL_CFI_LOCK 0x02 /* */ +#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */ +#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */ +#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */ +#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */ +#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */ +#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */ +#define INTEL_CFI_BANK 0x2C /* Number of Bank */ +#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */ +#define INTEL_CFI_SZ1B 0x30 +#define INTEL_CFI_SZ2A 0x33 +#define INTEL_CFI_SZ2B 0x34 +#define INTEL_CFI_BLK1 0x2D /* Number of Blocks */ +#define INTEL_CFI_BLK2 0x31 + +#define WR_BLOCK 0x20 + +#define SYNC __asm__("nop") + +/*----------------------------------------------------------------------- + * Functions + */ + +ulong flash_get_size(FPWV * addr, flash_info_t * info); +int flash_get_offsets(ulong base, flash_info_t * info); +int flash_cmd_rd(FPWV * addr, int index); +int write_data(flash_info_t * info, ulong dest, FPW data); +void flash_sync_real_protect(flash_info_t * info); +uchar intel_sector_protected(flash_info_t * info, ushort sector); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +ulong flash_init(void) +{ + FPWV *flash_addr[CFG_MAX_FLASH_BANKS]; + ulong size; + int i; + + flash_addr[0] = (FPW *) CFG_FLASH0_BASE; +#ifdef CFG_FLASH1_BASE + flash_addr[1] = (FPW *) CFG_FLASH1_BASE; +#endif + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + memset(&flash_info[i], 0, sizeof(flash_info_t)); + + size = flash_get_size(flash_addr[i], &flash_info[i]); + flash_protect(FLAG_PROTECT_CLEAR, + flash_info[i].start[0], + flash_info[i].start[0] + size - 1, + &flash_info[0]); + /* get the h/w and s/w protection status in sync */ + flash_sync_real_protect(&flash_info[i]); + } + + /* Protect monitor and environment sectors */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + + return size; +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf("INTEL "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + printf("28F160C3B\n"); + break; + case FLASH_28F160C3T: + printf("28F160C3T\n"); + break; + case FLASH_28F320C3B: + printf("28F320C3B\n"); + break; + case FLASH_28F320C3T: + printf("28F320C3T\n"); + break; + case FLASH_28F640C3B: + printf("28F640C3B\n"); + break; + case FLASH_28F640C3T: + printf("28F640C3T\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + } + + if (info->size > 0x100000) { + int remainder; + + printf(" Size: %ld", info->size >> 20); + + remainder = (info->size % 0x100000); + if (remainder) { + remainder >>= 10; + remainder = (int)((float) + (((float)remainder / (float)1024) * + 10000)); + printf(".%d ", remainder); + } + + printf("MB in %d Sectors\n", info->sector_count); + } else + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size(FPWV * addr, flash_info_t * info) +{ + int intel = 0; + u16 value; + static int bank = 0; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + *addr = (FPW) INTEL_RESET; /* restore read mode */ + *addr = (FPW) INTEL_READID; + + switch (addr[INTEL_CFI_MFG] & 0xff) { + case (ushort) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + value = addr[INTEL_CFI_PART]; + intel = 1; + break; + default: + printf("Unknown Flash\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + *addr = (FPW) INTEL_RESET; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + switch (value) { + case (u16) INTEL_ID_28F160C3B: + info->flash_id += FLASH_28F160C3B; + break; + case (u16) INTEL_ID_28F160C3T: + info->flash_id += FLASH_28F160C3T; + break; + case (u16) INTEL_ID_28F320C3B: + info->flash_id += FLASH_28F320C3B; + break; + case (u16) INTEL_ID_28F320C3T: + info->flash_id += FLASH_28F320C3T; + break; + case (u16) INTEL_ID_28F640C3B: + info->flash_id += FLASH_28F640C3B; + break; + case (u16) INTEL_ID_28F640C3T: + info->flash_id += FLASH_28F640C3T; + break; + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (intel) { + /* Intel spec. under CFI section */ + u32 sz, size, offset; + int sec, sectors, bs; + int part, i, j, cnt; + + part = flash_cmd_rd(addr, INTEL_CFI_BANK); + + /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. + * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count + * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count + */ + offset = (u32) addr; + sectors = sec = 0; + size = sz = cnt = 0; + for (i = 0; i < part; i++) { + bs = (((addr[INTEL_CFI_SZ1B + i * 4] << 8) | + addr[INTEL_CFI_SZ1A + i * 4]) * 0x100); + sec = addr[INTEL_CFI_BLK1 + i * 4] + 1; + sz = bs * sec; + + for (j = 0; j < sec; j++) { + info->start[cnt++] = offset; + offset += bs; + } + + sectors += sec; + size += sz; + } + info->sector_count = sectors; + info->size = size; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + *addr = (FPW) INTEL_RESET; /* restore read mode */ + + return (info->size); +} + +int flash_cmd_rd(FPWV * addr, int index) +{ + return (int)addr[index]; +} + +/* + * This function gets the u-boot flash sector protection status + * (flash_info_t.protect[]) in sync with the sector protection + * status stored in hardware. + */ +void flash_sync_real_protect(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + for (i = 0; i < info->sector_count; ++i) { + info->protect[i] = intel_sector_protected(info, i); + } + break; + default: + /* no h/w protect support */ + break; + } +} + +/* + * checks if "sector" in bank "info" is protected. Should work on intel + * strata flash chips 28FxxxJ3x in 8-bit mode. + * Returns 1 if sector is protected (or timed-out while trying to read + * protection status), 0 if it is not. + */ +uchar intel_sector_protected(flash_info_t * info, ushort sector) +{ + FPWV *addr; + FPWV *lock_conf_addr; + ulong start; + unsigned char ret; + + /* + * first, wait for the WSM to be finished. The rationale for + * waiting for the WSM to become idle for at most + * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * because of: (1) erase, (2) program or (3) lock bit + * configuration. So we just wait for the longest timeout of + * the (1)-(3), i.e. the erase timeout. + */ + + /* wait at least 35ns (W12) before issuing Read Status Register */ + /*udelay(1); */ + addr = (FPWV *) info->start[sector]; + *addr = (FPW) INTEL_STATUS; + + start = get_timer(0); + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + printf("WSM busy too long, can't get prot status\n"); + return 1; + } + } + + /* issue the Read Identifier Codes command */ + *addr = (FPW) INTEL_READID; + + /* Intel example code uses offset of 4 for 8-bit flash */ + lock_conf_addr = (FPWV *) info->start[sector]; + ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0; + + /* put flash back in read mode */ + *addr = (FPW) INTEL_RESET; + + return ret; +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + type = (info->flash_id & FLASH_VENDMASK); + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf("\n"); + + start = get_timer(0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + + FPWV *addr = (FPWV *) (info->start[sect]); + int min = 0; + + printf("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + *addr = (FPW) INTEL_READID; + min = addr[INTEL_CFI_TERB]; + min = 1 << min; /* ms */ + min = (min / info->sector_count) * 1000; + + /* start erase block */ + *addr = (FPW) INTEL_CLEAR; /* clear status register */ + *addr = (FPW) INTEL_ERASE; /* erase setup */ + *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ + + while ((*addr & (FPW) INTEL_FINISHED) != + (FPW) INTEL_FINISHED) { + + if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = (FPW) INTEL_SUSERASE; /* suspend erase */ + *addr = (FPW) INTEL_RESET; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *addr = (FPW) INTEL_RESET; /* resest to read mode */ + + printf(" done\n"); + } + } + + return rcode; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + if (info->flash_id == FLASH_UNKNOWN) + return 4; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + { + ulong cp, wp; + FPW data; + int i, l, rc, port_width; + + /* get lower word aligned address */ + wp = addr; + port_width = 1; + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < port_width; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + if ((rc = write_data(info, wp, data)) != 0) + return (rc); + + wp += port_width; + } + + /* handle word aligned part */ + while (cnt >= 2) { + data = *((FPW *) src); + + if ((rc = + write_data(info, (ulong) ((FPWV *) wp), + (FPW) data)) != 0) { + return (rc); + } + + src += sizeof(FPW); + wp += sizeof(FPW); + cnt -= sizeof(FPW); + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data |= (*(uchar *) cp); + } + + return write_data(info, (ulong) ((FPWV *) wp), + (FPW) data); + + } /* case FLASH_MAN_INTEL */ + + } /* switch */ + + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_data(flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf("not erased at %08lx (%lx)\n", (ulong) addr, + (ulong) * addr); + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = (int)disable_interrupts(); + + *addr = (FPW) INTEL_CLEAR; + *addr = (FPW) INTEL_RESET; + + *addr = (FPW) INTEL_WRSETUP; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) INTEL_SUSERASE; /* suspend mode */ + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* reset */ + return (1); + } + } + + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* restore read mode */ + + return (0); +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t * info, long sector, int prot) +{ + int rcode = 0; /* assume success */ + FPWV *addr; /* address of sector */ + FPW value; + + addr = (FPWV *) (info->start[sector]); + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + *addr = (FPW) INTEL_RESET; /* make sure in read mode */ + *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */ + + if (prot) + *addr = (FPW) INTEL_PROTECT; /* lock sector */ + else + *addr = (FPW) INTEL_CONFIRM; /* unlock sector */ + + /* now see if it really is locked/unlocked as requested */ + *addr = (FPW) INTEL_READID; + + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but return failure. Mixed protected and + * unprotected devices within a sector should never happen. + */ + value = addr[2] & (FPW) INTEL_PROTECT; + if (value == 0) + info->protect[sector] = 0; + else if (value == (FPW) INTEL_PROTECT) + info->protect[sector] = 1; + else { + /* error, mixed protected and unprotected */ + rcode = 1; + info->protect[sector] = 1; + } + if (info->protect[sector] != prot) + rcode = 1; /* failed to protect/unprotect as requested */ + + /* reload all protection bits from hardware for now */ + flash_sync_real_protect(info); + break; + + default: + /* no hardware protect that we support */ + info->protect[sector] = prot; + break; + } + + return rcode; +} +#endif /* CFG_FLASH_PROTECTION */ +#endif /* CFG_FLASH_CFI */ diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c new file mode 100644 index 00000000000..4ccea30d61d --- /dev/null +++ b/board/freescale/m5329evb/m5329evb.c @@ -0,0 +1,376 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale FireEngine 5329 EVB\n"); + return 0; +}; + +long int initdram(int board_type) +{ + volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + u32 dramsize, i; + + dramsize = CFG_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + sdram->cs0 = (CFG_SDRAM_BASE | i); + sdram->cfg1 = CFG_SDRAM_CFG1; + sdram->cfg2 = CFG_SDRAM_CFG2; + + /* Issue PALL */ + sdram->ctrl = CFG_SDRAM_CTRL | 2; + + /* Issue LEMR */ + sdram->mode = CFG_SDRAM_EMOD; + sdram->mode = (CFG_SDRAM_MODE | 0x04000000); + + udelay(500); + + /* Issue PALL */ + sdram->ctrl = (CFG_SDRAM_CTRL | 2); + + /* Perform two refresh cycles */ + sdram->ctrl = CFG_SDRAM_CTRL | 4; + sdram->ctrl = CFG_SDRAM_CTRL | 4; + + sdram->mode = CFG_SDRAM_MODE; + + sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + + udelay(100); + + return dramsize; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#ifdef CFG_FLASH_CFI +void sync(void) +{ + /* This sync function is PowerPC intruction, + coldfire does not have this instruction. Dummy function */ +} +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; + } else { + gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18) | \ + (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + strcpy(info->phy_name, + STR_ID_DP83848VV); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + printf(STR_ID_DP83848VV); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +void mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds new file mode 100644 index 00000000000..9b994a09db8 --- /dev/null +++ b/board/freescale/m5329evb/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf532x/start.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index d97c09e88ee..9651b309740 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -207,6 +207,59 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } +#elif defined(CONFIG_M68K) /* M68K */ + +int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + bd_t *bd = gd->bd; + print_num ("memstart", (ulong)bd->bi_memstart); + print_num ("memsize", (ulong)bd->bi_memsize); + print_num ("flashstart", (ulong)bd->bi_flashstart); + print_num ("flashsize", (ulong)bd->bi_flashsize); + print_num ("flashoffset", (ulong)bd->bi_flashoffset); +#if defined(CFG_INIT_RAM_ADDR) + print_num ("sramstart", (ulong)bd->bi_sramstart); + print_num ("sramsize", (ulong)bd->bi_sramsize); +#endif +#if defined(CFG_MBAR) + print_num ("mbar", bd->bi_mbar_base ); +#endif +#if defined(CFG_CMD_NET) + puts ("ethaddr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); + } + +#if defined(CONFIG_HAS_ETH1) + puts ("\neth1addr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]); + } +#endif + +#if defined(CONFIG_HAS_ETH2) + puts ("\neth2addr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]); + } +#endif + +#if defined(CONFIG_HAS_ETH3) + puts ("\neth3addr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]); + } +#endif + + puts ("\nip_addr = "); + print_IPaddr (bd->bi_ip_addr); +#endif /* CFG_CMD_NET */ + printf ("\nbaudrate = %d bps\n", bd->bi_baudrate); + + return 0; +} + #else /* ! PPC, which leaves MIPS */ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) diff --git a/common/cmd_mii.c b/common/cmd_mii.c index e6595360cbe..c3f43d7f463 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -438,7 +438,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int rcode = 0; char *devname; -#ifdef CONFIG_8xx +#if defined(CONFIG_8xx) || defined(CONFIG_MCF532x) mii_init (); #endif diff --git a/cpu/mcf532x/Makefile b/cpu/mcf532x/Makefile new file mode 100644 index 00000000000..452848d32ad --- /dev/null +++ b/cpu/mcf532x/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = +COBJS = cpu.o speed.o cpu_init.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mcf532x/config.mk b/cpu/mcf532x/config.mk new file mode 100644 index 00000000000..ba324a894a5 --- /dev/null +++ b/cpu/mcf532x/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 Josef Baumgartner +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data +PLATFORM_CPPFLAGS += -m5307 -fPIC diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c new file mode 100644 index 00000000000..071c5030477 --- /dev/null +++ b/cpu/mcf532x/cpu.c @@ -0,0 +1,134 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + wdp->cr = 0; + udelay(1000); + + /* enable watchdog, set timeout to 0 and wait */ + wdp->cr = WTM_WCR_EN; + while (1) ; + + /* we don't return! */ + return 0; +}; + +int checkcpu(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + u16 msk; + u16 id = 0; + u8 ver; + + puts("CPU: "); + msk = (ccm->cir >> 6); + ver = (ccm->cir & 0x003f); + switch (msk) { + case 0x54: + id = 5329; + break; + case 0x59: + id = 5328; + break; + case 0x61: + id = 5327; + break; + } + + if (id) { + printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, + ver); + printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n", + (int)(gd->cpu_clk / 1000000), + (int)(gd->bus_clk / 1000000)); + } + + return 0; +}; + +#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + wdp->sr = 0x5555; /* Count register */ +} + +int watchdog_disable(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + + /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ + wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */ + + puts("WATCHDOG:disabled\n"); + return (0); +} + +int watchdog_init(void) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + u32 wdog_module = 0; + + /* set timeout and enable watchdog */ + wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module |= (wdog_module / 8192); + wdp->mr = wdog_module; + + wdp->cr = WTM_WCR_EN; + puts("WATCHDOG:enabled\n"); + + return (0); +} +#endif /* #ifdef CONFIG_WATCHDOG */ + +#ifdef CONFIG_MCFINTC +int interrupt_init(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrh0 |= 0xFFFFFFFF; + intp->imrl0 |= 0xFFFFFFFF; + + enable_interrupts(); + return 0; +} +#endif /* CONFIG_MCFINTC */ diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c new file mode 100644 index 00000000000..6319658c06b --- /dev/null +++ b/cpu/mcf532x/cpu_init.c @@ -0,0 +1,126 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; + + /* watchdog is enabled by default - disable the watchdog */ +#ifndef CONFIG_WATCHDOG + wdog->cr = 0; +#endif + + scm1->mpr0 = 0x77777777; + scm2->pacra = 0; + scm2->pacrb = 0; + scm2->pacrc = 0; + scm2->pacrd = 0; + scm2->pacre = 0; + scm2->pacrf = 0; + scm2->pacrg = 0; + scm1->pacrh = 0; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + break; + case 1: + gpio->par_uart = + (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + break; + case 2: + gpio->par_uart = (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); + break; + } + + /* Port configuration */ + gpio->par_cs = 0x3E; + +#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) + fbcs->csar0 = CFG_CS0_BASE; + fbcs->cscr0 = CFG_CS0_CTRL; + fbcs->csmr0 = CFG_CS0_MASK; +#endif + +#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) + /* Latch chipselect */ + fbcs->csar1 = CFG_CS1_BASE; + fbcs->cscr1 = CFG_CS1_CTRL; + fbcs->csmr1 = CFG_CS1_MASK; +#endif + +#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) + fbcs->csar2 = CFG_CS2_BASE; + fbcs->cscr2 = CFG_CS2_CTRL; + fbcs->csmr2 = CFG_CS2_MASK; +#endif + +#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) + fbcs->csar3 = CFG_CS3_BASE; + fbcs->cscr3 = CFG_CS3_CTRL; + fbcs->csmr3 = CFG_CS3_MASK; +#endif + +#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) + fbcs->csar4 = CFG_CS4_BASE; + fbcs->cscr4 = CFG_CS4_CTRL; + fbcs->csmr4 = CFG_CS4_MASK; +#endif + +#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) + fbcs->csar5 = CFG_CS5_BASE; + fbcs->cscr5 = CFG_CS5_CTRL; + fbcs->csmr5 = CFG_CS5_MASK; +#endif +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + /*icache_enable(); */ + return (0); +} diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c new file mode 100644 index 00000000000..c4ba7ec6692 --- /dev/null +++ b/cpu/mcf532x/speed.c @@ -0,0 +1,222 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +/* PLL min/max specifications */ +#define MAX_FVCO 500000 /* KHz */ +#define MAX_FSYS 80000 /* KHz */ +#define MIN_FSYS 58333 /* KHz */ +#define FREF 16000 /* KHz */ +#define MAX_MFD 135 /* Multiplier */ +#define MIN_MFD 88 /* Multiplier */ +#define BUSDIV 6 /* Divider */ +/* + * Low Power Divider specifications + */ +#define MIN_LPD (1 << 0) /* Divider (not encoded) */ +#define MAX_LPD (1 << 15) /* Divider (not encoded) */ +#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ + +/* + * Get the value of the current system clock + * + * Parameters: + * none + * + * Return Value: + * The current output system frequency + */ +int get_sys_clock(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + int divider; + + /* Test to see if device is in LIMP mode */ + if (ccm->misccr & CCM_MISCCR_LIMP) { + divider = ccm->cdr & CCM_CDR_LPDIV(0xF); + return (FREF / (2 << divider)); + } else { + return ((FREF * pll->pfdr) / (BUSDIV * 4)); + } +} + +/* + * Initialize the Low Power Divider circuit + * + * Parameters: + * div Desired system frequency divider + * + * Return Value: + * The resulting output system frequency + */ +int clock_limp(int div) +{ + volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + u32 temp; + + /* Check bounds of divider */ + if (div < MIN_LPD) + div = MIN_LPD; + if (div > MAX_LPD) + div = MAX_LPD; + + /* Save of the current value of the SSIDIV so we don't overwrite the value */ + temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF)); + + /* Apply the divider to the system clock */ + ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); + + ccm->misccr |= CCM_MISCCR_LIMP; + + return (FREF / (3 * (1 << div))); +} + +/* + * Exit low power LIMP mode + * + * Parameters: + * div Desired system frequency divider + * + * Return Value: + * The resulting output system frequency + */ +int clock_exit_limp(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + int fout; + + /* Exit LIMP mode */ + ccm->misccr &= (~CCM_MISCCR_LIMP); + + /* Wait for PLL to lock */ + while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ; + + fout = get_sys_clock(); + + return fout; +} + +/* Initialize the PLL + * + * Parameters: + * fref PLL reference clock frequency in KHz + * fsys Desired PLL output frequency in KHz + * flags Operating parameters + * + * Return Value: + * The resulting output system frequency + */ +int clock_pll(int fsys, int flags) +{ + volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80); + volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + int fref, temp, fout, mfd; + u32 i; + + fref = FREF; + + if (fsys == 0) { + /* Return current PLL output */ + mfd = pll->pfdr; + + return (fref * mfd / (BUSDIV * 4)); + } + + /* Check bounds of requested system clock */ + if (fsys > MAX_FSYS) + fsys = MAX_FSYS; + + if (fsys < MIN_FSYS) + fsys = MIN_FSYS; + + /* Multiplying by 100 when calculating the temp value, + and then dividing by 100 to calculate the mfd allows + for exact values without needing to include floating + point libraries. */ + temp = (100 * fsys) / fref; + mfd = (4 * BUSDIV * temp) / 100; + + /* Determine the output frequency for selected values */ + fout = ((fref * mfd) / (BUSDIV * 4)); + + /* + * Check to see if the SDRAM has already been initialized. + * If it has then the SDRAM needs to be put into self refresh + * mode before reprogramming the PLL. + */ + /* Put SDRAM into self refresh mode */ +/* if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) + MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;*/ + + /* + * Initialize the PLL to generate the new system clock frequency. + * The device must be put into LIMP mode to reprogram the PLL. + */ + + /* Enter LIMP mode */ + clock_limp(DEFAULT_LPD); + + /* Reprogram PLL for desired fsys */ + pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV)); + + pll->pfdr = mfd; + + /* Exit LIMP mode */ + clock_exit_limp(); + + /* + * Return the SDRAM to normal operation if it is in use. + */ + /* Exit self refresh mode */ +/* if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) + MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;*/ + + /* software workaround for SDRAM opeartion after exiting LIMP mode errata */ + *sdram_workaround = CFG_SDRAM_BASE; + /* wait for DQS logic to relock */ + for (i = 0; i < 0x200; i++) ; + + return fout; +} + +/* + * get_clocks() fills in gd->cpu_clock and gd->bus_clk + */ +int get_clocks(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000; + gd->cpu_clk = (gd->bus_clk * 3); + return (0); +} diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S new file mode 100644 index 00000000000..d36d076cf32 --- /dev/null +++ b/cpu/mcf532x/start.S @@ -0,0 +1,338 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "version.h" + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR0 + + /* invalidate and disable cache */ + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2 + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CFG_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CFG_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CFG_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CFG_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CFG_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CFG_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ +/* cache functions */ + .globl icache_enable +icache_enable: + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + move.l #(CFG_CS0_BASE + 0xc000), %d0 /* Setup cache mask */ + movec %d0, %ACR1 /* Enable cache */ + + /*move.l #0x81000100, %d0*/ /* Setup cache mask */ + move.l #0x81000100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl icache_disable +icache_disable: + move.l #0x00000100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + clr.l %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + movec %d0, %ACR1 /* Enable cache */ + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl icache_status +icache_status: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l (%a1), %d0 + rts + + .globl icache_invalid +icache_invalid: + move.l #0x00000100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + rts + + .globl dcache_enable +dcache_enable: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + /* No dcache, just a dummy function */ + .globl dcache_disable +dcache_disable: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_status +dcache_status: + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + move.l (%a1), %d0 + rts + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/drivers/net/Makefile b/drivers/net/Makefile new file mode 100644 index 00000000000..37d69b9949b --- /dev/null +++ b/drivers/net/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libnet.a + +COBJS := mcffec.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c new file mode 100644 index 00000000000..d1c84caee0d --- /dev/null +++ b/drivers/net/mcffec.c @@ -0,0 +1,594 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_MCFFEC +#undef ET_DEBUG +#undef MII_DEBUG + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 + +#define TX_BUF_CNT 2 + +/* + NOTE: PKT_MAXBUF_SIZE must be larger or equal to PKT_MAXBLR_SIZE, + see M54455 User Manual for MAX_FL of Receive Control Register for more + description. If PKT_MAXBUF_SIZE set to 1518, the FEC bandwidth will + reduce to about 20~40% of normal bandwidth. Changing PKT_MAXBLR_SIZE + will not make any improvement on speed +*/ +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1520 +#define LAST_PKTBUFSRX PKTBUFSRX - 1 +#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) +#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) + +DECLARE_GLOBAL_DATA_PTR; + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) + +struct fec_info_s fec_info[] = { +#ifdef CFG_FEC0_IOBASE + { + 0, /* index */ + CFG_FEC0_IOBASE, /* io base */ + CFG_FEC0_PINMUX, /* gpio pin muxing */ + CFG_FEC0_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phyname init */ + 0, /* RX BD */ + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + }, +#endif +#ifdef CFG_FEC1_IOBASE + { + 1, /* index */ + CFG_FEC1_IOBASE, /* io base */ + CFG_FEC1_PINMUX, /* gpio pin muxing */ + CFG_FEC1_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phy name init */ + 0, /* RX BD */ + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + } +#endif +}; + +/* + * FEC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ + +int fec_send(struct eth_device *dev, volatile void *packet, int length); +int fec_recv(struct eth_device *dev); +int fec_init(struct eth_device *dev, bd_t * bd); +void fec_halt(struct eth_device *dev); +void fec_reset(struct eth_device *dev); + +extern int fecpin_setclear(struct eth_device *dev, int setclear); + +#ifdef CFG_DISCOVER_PHY +extern void mii_init(void); +extern uint mii_send(uint mii_cmd); +extern int mii_discover_phy(struct eth_device *dev); +extern int mcffec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +extern int mcffec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +#endif + +void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) +{ + if ((dup_spd >> 16) == FULL) { + /* Set maximum frame length */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | + FEC_RCR_PROM | 0x100; + fecp->tcr = FEC_TCR_FDEN; + } else { + /* Half duplex mode */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | + FEC_RCR_MII_MODE | FEC_RCR_DRT; + fecp->tcr &= ~FEC_TCR_FDEN; + } + + if ((dup_spd & 0xFFFF) == _100BASET) { +#ifdef MII_DEBUG + printf("100Mbps\n"); +#endif + bd->bi_ethspeed = 100; + } else { +#ifdef MII_DEBUG + printf("10Mbps\n"); +#endif + bd->bi_ethspeed = 10; + } +} + +int fec_send(struct eth_device *dev, volatile void *packet, int length) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int j, rc; + u16 phyStatus; + + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); + + /* section 16.9.23.3 + * Wait for ready + */ + j = 0; + while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && + (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("TX not ready\n"); + } + + info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; + info->txbd[info->txIdx].cbd_datlen = length; + info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; + + /* Activate transmit Buffer Descriptor polling */ + fecp->tdar = 0x01000000; /* Descriptor polling active */ + + j = 0; + while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && + (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("TX timeout\n"); + } +#ifdef ET_DEBUG + printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", + __FILE__, __LINE__, __FUNCTION__, j, + info->txbd[info->txIdx].cbd_sc, + (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); +#endif + + /* return only status bits */ ; + rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); + info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; + + return rc; +} + +int fec_recv(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int length; + + for (;;) { + /* section 16.9.23.2 */ + if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + length = info->rxbd[info->rxIdx].cbd_datlen; + + if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) { + printf("%s[%d] err: %x\n", + __FUNCTION__, __LINE__, + info->rxbd[info->rxIdx].cbd_sc); +#ifdef ET_DEBUG + printf("%s[%d] err: %x\n", + __FUNCTION__, __LINE__, + info->rxbd[info->rxIdx].cbd_sc); +#endif + } else { + + length -= 4; + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[info->rxIdx], length); + + fecp->eir |= FEC_EIR_RXF; + } + + /* Give the buffer back to the FEC. */ + info->rxbd[info->rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if (info->rxIdx == LAST_PKTBUFSRX) { + info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; + info->rxIdx = 0; + } else { + info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + info->rxIdx++; + } + + /* Try to fill Buffer Descriptors */ + fecp->rdar = 0x01000000; /* Descriptor polling active */ + } + + return length; +} + +/************************************************************** + * + * FEC Ethernet Initialization Routine + * + *************************************************************/ + +#ifdef ET_DEBUG +void dbgFecRegs(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + + printf("=====\n"); + printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); + printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); + printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar); + printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar); + printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); + printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); + printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); + printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); + printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); + printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); + printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); + printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); + printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); + printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); + printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); + printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); + printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); + printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); + printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr); + printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr); + printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr); + printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr); + printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr); + + printf("\n"); + printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop, + fecp->rmon_t_drop); + printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets, + fecp->rmon_t_packets); + printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt, + fecp->rmon_t_bc_pkt); + printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt, + fecp->rmon_t_mc_pkt); + printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align, + fecp->rmon_t_crc_align); + printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize, + fecp->rmon_t_undersize); + printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize, + fecp->rmon_t_oversize); + printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag, + fecp->rmon_t_frag); + printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab, + fecp->rmon_t_jab); + printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col, + fecp->rmon_t_col); + printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64, + fecp->rmon_t_p64); + printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127, + fecp->rmon_t_p65to127); + printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255, + fecp->rmon_t_p128to255); + printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511, + fecp->rmon_t_p256to511); + printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023, + fecp->rmon_t_p512to1023); + printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047, + fecp->rmon_t_p1024to2047); + printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048, + fecp->rmon_t_p_gte2048); + printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets, + fecp->rmon_t_octets); + + printf("\n"); + printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop, + fecp->ieee_t_drop); + printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok, + fecp->ieee_t_frame_ok); + printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col, + fecp->ieee_t_1col); + printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol, + fecp->ieee_t_mcol); + printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def, + fecp->ieee_t_def); + printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol, + fecp->ieee_t_lcol); + printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol, + fecp->ieee_t_excol); + printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr, + fecp->ieee_t_macerr); + printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr, + fecp->ieee_t_cserr); + printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe, + fecp->ieee_t_sqe); + printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc, + fecp->ieee_t_fdxfc); + printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok, + fecp->ieee_t_octets_ok); + + printf("\n"); + printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop, + fecp->rmon_r_drop); + printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets, + fecp->rmon_r_packets); + printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt, + fecp->rmon_r_bc_pkt); + printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt, + fecp->rmon_r_mc_pkt); + printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align, + fecp->rmon_r_crc_align); + printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize, + fecp->rmon_r_undersize); + printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize, + fecp->rmon_r_oversize); + printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag, + fecp->rmon_r_frag); + printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab, + fecp->rmon_r_jab); + printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64, + fecp->rmon_r_p64); + printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127, + fecp->rmon_r_p65to127); + printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255, + fecp->rmon_r_p128to255); + printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511, + fecp->rmon_r_p256to511); + printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023, + fecp->rmon_r_p512to1023); + printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047, + fecp->rmon_r_p1024to2047); + printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048, + fecp->rmon_r_p_gte2048); + printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets, + fecp->rmon_r_octets); + + printf("\n"); + printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop, + fecp->ieee_r_drop); + printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok, + fecp->ieee_r_frame_ok); + printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc, + fecp->ieee_r_crc); + printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align, + fecp->ieee_r_align); + printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr, + fecp->ieee_r_macerr); + printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc, + fecp->ieee_r_fdxfc); + printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok, + fecp->ieee_r_octets_ok); + + printf("\n\n\n"); +} +#endif + +int fec_init(struct eth_device *dev, bd_t * bd) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int i; + u8 *ea; + + fecpin_setclear(dev, 1); + + fec_reset(dev); + +#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined (CONFIG_MII) || \ + defined (CFG_DISCOVER_PHY) + + mii_init(); + + setFecDuplexSpeed(fecp, bd, info->dup_spd); +#else +#ifndef CFG_DISCOVER_PHY + setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); +#endif /* ifndef CFG_DISCOVER_PHY */ +#endif /* CFG_CMD_MII || CONFIG_MII */ + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set station address */ + if ((u32) fecp == CFG_FEC0_IOBASE) { + ea = &bd->bi_enetaddr[0]; + } else { +#ifdef CFG_FEC1_IOBASE + ea = &bd->bi_enet1addr[0]; +#endif + } + + fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->paur = (ea[4] << 24) | (ea[5] << 16); +#ifdef ET_DEBUG + printf("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n", + ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); +#endif + + /* Clear unicast address hash table */ + fecp->iaur = 0; + fecp->ialr = 0; + + /* Clear multicast address hash table */ + fecp->gaur = 0; + fecp->galr = 0; + + /* Set maximum receive buffer size. */ + fecp->emrbr = PKT_MAXBLR_SIZE; + + /* + * Setup Buffers and Buffer Desriptors + */ + info->rxIdx = 0; + info->txIdx = 0; + + /* + * Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: + * Empty, Wrap + */ + for (i = 0; i < PKTBUFSRX; i++) { + info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + info->rxbd[i].cbd_datlen = 0; /* Reset */ + info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + } + info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* + * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: + * Last, Tx CRC + */ + for (i = 0; i < TX_BUF_CNT; i++) { + info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; + info->txbd[i].cbd_datlen = 0; /* Reset */ + info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); + } + info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* Set receive and transmit descriptor base */ + fecp->erdsr = (unsigned int)(&info->rxbd[0]); + fecp->etdsr = (unsigned int)(&info->txbd[0]); + + /* Now enable the transmit and receive processing */ + fecp->ecr |= FEC_ECR_ETHER_EN; + + /* And last, try to fill Rx Buffer Descriptors */ + fecp->rdar = 0x01000000; /* Descriptor polling active */ + + return 1; +} + +void fec_reset(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + volatile fec_t *fecp = (fec_t *) (info->iobase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +void fec_halt(struct eth_device *dev) +{ + struct fec_info_s *info = dev->priv; + + fec_reset(dev); + + fecpin_setclear(dev, 0); + + info->rxIdx = info->txIdx = 0; + memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t)); + memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t)); + memset(info->txbuf, 0, DBUF_LENGTH); +} + +int mcffec_initialize(bd_t * bis) +{ + struct eth_device *dev; + int i; + + for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { + + dev = (struct eth_device *)malloc(sizeof *dev); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "FEC%d", fec_info[i].index); + + dev->priv = &fec_info[i]; + dev->init = fec_init; + dev->halt = fec_halt; + dev->send = fec_send; + dev->recv = fec_recv; + + /* setup Receive and Transmit buffer descriptor */ + fec_info[i].rxbd = + (cbd_t *) memalign(32, (PKTBUFSRX * sizeof(cbd_t) + 31)); + fec_info[i].txbd = + (cbd_t *) memalign(32, (TX_BUF_CNT * sizeof(cbd_t) + 31)); + fec_info[i].txbuf = (char *)memalign(32, DBUF_LENGTH + 31); +#ifdef ET_DEBUG + printf("rxbd %x txbd %x\n", + (int)fec_info[i].rxbd, (int)fec_info[i].txbd); +#endif + + fec_info[i].phy_name = (char *)malloc(32); + + eth_register(dev); + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register(dev->name, + mcffec_miiphy_read, mcffec_miiphy_write); +#endif + } + + /* default speed */ + bis->bi_ethspeed = 10; + + return 1; +} + +#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ +#endif /* CONFIG_MCFFEC */ diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile new file mode 100644 index 00000000000..2208a08a71c --- /dev/null +++ b/drivers/serial/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libserial.a + +COBJS := mcfserial.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/serial/mcfserial.c b/drivers/serial/mcfserial.c new file mode 100644 index 00000000000..a8ca78ad8ca --- /dev/null +++ b/drivers/serial/mcfserial.c @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2004, Freescale, Inc + * TsiChung Liew, Tsi-Chung.Liew@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Minimal serial functions needed to use one of the uart ports + * as serial console interface. + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_MCFSERIAL +int serial_init(void) +{ + volatile uart_t *uart; + u32 counter; + + uart = (volatile uart_t *)(CFG_UART_BASE); + + /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ + uart->ucr = UART_UCR_RESET_RX; + uart->ucr = UART_UCR_RESET_TX; + uart->ucr = UART_UCR_RESET_ERROR; + uart->ucr = UART_UCR_RESET_MR; + __asm__("nop"); + + uart->uimr = 0; + + /* write to CSR: RX/TX baud rate from timers */ + uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK); + + uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE); + uart->umr = UART_UMR_SB_STOP_BITS_1; + + /* Setting up BaudRate */ + counter = (u32) (gd->bus_clk / (gd->baudrate)); + counter >>= 5; + + /* write to CTUR: divide counter upper byte */ + uart->ubg1 = (u8) ((counter & 0xff00) >> 8); + /* write to CTLR: divide counter lower byte */ + uart->ubg2 = (u8) (counter & 0x00ff); + + uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED); + + return (0); +} + +void serial_putc(const char c) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + + if (c == '\n') + serial_putc('\r'); + + /* Wait for last character to go. */ + while (!(uart->usr & UART_USR_TXRDY)) ; + + uart->utb = c; +} + +void serial_puts(const char *s) +{ + while (*s) { + serial_putc(*s++); + } +} + +int serial_getc(void) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + + /* Wait for a character to arrive. */ + while (!(uart->usr & UART_USR_RXRDY)) ; + return uart->urb; +} + +int serial_tstc(void) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + + return (uart->usr & UART_USR_RXRDY); +} + +void serial_setbrg(void) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + u32 counter; + + counter = ((gd->bus_clk / gd->baudrate)) >> 5; + counter++; + + /* write to CTUR: divide counter upper byte */ + uart->ubg1 = ((counter & 0xff00) >> 8); + /* write to CTLR: divide counter lower byte */ + uart->ubg2 = (counter & 0x00ff); + + uart->ucr = UART_UCR_RESET_RX; + uart->ucr = UART_UCR_RESET_TX; + + uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED; +} +#endif /* CONFIG_MCFSERIAL */ diff --git a/include/asm-m68k/byteorder.h b/include/asm-m68k/byteorder.h index ce613ac384a..0e2a0ed8cbd 100644 --- a/include/asm-m68k/byteorder.h +++ b/include/asm-m68k/byteorder.h @@ -1,7 +1,107 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #ifndef _M68K_BYTEORDER_H #define _M68K_BYTEORDER_H #include + +#ifdef __GNUC__ +#define __sw16(x) \ + ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8) )) +#define __sw32(x) \ + ((__u32)( \ + (((__u32)(x)) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x)) >> 24) )) + +extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) +{ + unsigned result = *addr; + return __sw16(result); +} + +extern __inline__ void st_le16(volatile unsigned short *addr, + const unsigned val) +{ + *addr = __sw16(val); +} + +extern __inline__ unsigned ld_le32(const volatile unsigned *addr) +{ + unsigned result = *addr; + return __sw32(result); +} + +extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) +{ + *addr = __sw32(val); +} + +#if 0 +/* alas, egcs sounds like it has a bug in this code that doesn't use the + inline asm correctly, and can cause file corruption. Until I hear that + it's fixed, I can live without the extra speed. I hope. */ +#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90) +#if 0 +# define __arch_swab16(x) ld_le16(&x) +# define __arch_swab32(x) ld_le32(&x) +#else +static __inline__ __attribute__ ((const)) +__u16 ___arch__swab16(__u16 value) +{ + return __sw16(value); +} + +static __inline__ __attribute__ ((const)) +__u32 ___arch__swab32(__u32 value) +{ + return __sw32(value); +} + +#define __arch__swab32(x) ___arch__swab32(x) +#define __arch__swab16(x) ___arch__swab16(x) +#endif /* 0 */ + +#endif + +/* The same, but returns converted value from the location pointer by addr. */ +#define __arch__swab16p(addr) ld_le16(addr) +#define __arch__swab32p(addr) ld_le32(addr) + +/* The same, but do the conversion in situ, ie. put the value back to addr. */ +#define __arch__swab16s(addr) st_le16(addr,*addr) +#define __arch__swab32s(addr) st_le32(addr,*addr) +#endif + +#endif /* __GNUC__ */ + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +#define __BYTEORDER_HAS_U64__ +#endif #include -#endif /* _M68K_BYTEORDER_H */ +#endif /* _M68K_BYTEORDER_H */ diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h index 5bbbfb245d8..9a5e7d5ab9b 100644 --- a/include/asm-m68k/fec.h +++ b/include/asm-m68k/fec.h @@ -5,6 +5,10 @@ * MPC8xx Communication Processor Module. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) * + * Add FEC Structure and definitions + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -30,9 +34,9 @@ /* Buffer descriptors used FEC. */ typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ } cbd_t; #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ @@ -53,28 +57,36 @@ typedef struct cpm_buf_desc { /* Buffer descriptor control/status used by Ethernet receive. */ #define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_RO1 ((ushort)0x4000) #define BD_ENET_RX_WRAP ((ushort)0x2000) #define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_RO2 BD_ENET_RX_INTR #define BD_ENET_RX_LAST ((ushort)0x0800) #define BD_ENET_RX_FIRST ((ushort)0x0400) #define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_BC ((ushort)0x0080) +#define BD_ENET_RX_MC ((ushort)0x0040) #define BD_ENET_RX_LG ((ushort)0x0020) #define BD_ENET_RX_NO ((ushort)0x0010) #define BD_ENET_RX_SH ((ushort)0x0008) #define BD_ENET_RX_CR ((ushort)0x0004) #define BD_ENET_RX_OV ((ushort)0x0002) #define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_TR BD_ENET_RX_CL #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ /* Buffer descriptor control/status used by Ethernet transmit. */ #define BD_ENET_TX_READY ((ushort)0x8000) #define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_TO1 BD_ENET_TX_PAD #define BD_ENET_TX_WRAP ((ushort)0x2000) #define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_ #define BD_ENET_TX_LAST ((ushort)0x0800) #define BD_ENET_TX_TC ((ushort)0x0400) #define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_ABC BD_ENET_TX_DEF #define BD_ENET_TX_HB ((ushort)0x0100) #define BD_ENET_TX_LC ((ushort)0x0080) #define BD_ENET_TX_RL ((ushort)0x0040) @@ -83,4 +95,225 @@ typedef struct cpm_buf_desc { #define BD_ENET_TX_CSL ((ushort)0x0001) #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ -#endif /* fec_h */ +#ifdef CONFIG_MCFFEC +/********************************************************************* +* +* Fast Ethernet Controller (FEC) +* +*********************************************************************/ +/* FEC private information */ +struct fec_info_s { + int index; + u32 iobase; + u32 pinmux; + u32 miibase; + int phy_addr; + int dup_spd; + char *phy_name; + int phyname_init; + cbd_t *rxbd; /* Rx BD */ + cbd_t *txbd; /* Tx BD */ + uint rxIdx; + uint txIdx; + char *txbuf; + int initialized; +}; + +/* Register read/write struct */ +typedef struct fec { + u8 resv0[0x4]; + u32 eir; + u32 eimr; + u8 resv1[0x4]; + u32 rdar; + u32 tdar; + u8 resv2[0xC]; + u32 ecr; + u8 resv3[0x18]; + u32 mmfr; + u32 mscr; + u8 resv4[0x1C]; + u32 mibc; + u8 resv5[0x1C]; + u32 rcr; + u8 resv6[0x3C]; + u32 tcr; + u8 resv7[0x1C]; + u32 palr; + u32 paur; + u32 opd; + u8 resv8[0x28]; + u32 iaur; + u32 ialr; + u32 gaur; + u32 galr; + u8 resv9[0x1C]; + u32 tfwr; + u8 resv10[0x4]; + u32 frbr; + u32 frsr; + u8 resv11[0x2C]; + u32 erdsr; + u32 etdsr; + u32 emrbr; + u8 resv12[0x74]; + + u32 rmon_t_drop; + u32 rmon_t_packets; + u32 rmon_t_bc_pkt; + u32 rmon_t_mc_pkt; + u32 rmon_t_crc_align; + u32 rmon_t_undersize; + u32 rmon_t_oversize; + u32 rmon_t_frag; + u32 rmon_t_jab; + u32 rmon_t_col; + u32 rmon_t_p64; + u32 rmon_t_p65to127; + u32 rmon_t_p128to255; + u32 rmon_t_p256to511; + u32 rmon_t_p512to1023; + u32 rmon_t_p1024to2047; + u32 rmon_t_p_gte2048; + u32 rmon_t_octets; + + u32 ieee_t_drop; + u32 ieee_t_frame_ok; + u32 ieee_t_1col; + u32 ieee_t_mcol; + u32 ieee_t_def; + u32 ieee_t_lcol; + u32 ieee_t_excol; + u32 ieee_t_macerr; + u32 ieee_t_cserr; + u32 ieee_t_sqe; + u32 ieee_t_fdxfc; + u32 ieee_t_octets_ok; + u8 resv13[0x8]; + + u32 rmon_r_drop; + u32 rmon_r_packets; + u32 rmon_r_bc_pkt; + u32 rmon_r_mc_pkt; + u32 rmon_r_crc_align; + u32 rmon_r_undersize; + u32 rmon_r_oversize; + u32 rmon_r_frag; + u32 rmon_r_jab; + u32 rmon_r_resvd_0; + u32 rmon_r_p64; + u32 rmon_r_p65to127; + u32 rmon_r_p128to255; + u32 rmon_r_p256to511; + u32 rmon_r_p512to1023; + u32 rmon_r_p1024to2047; + u32 rmon_r_p_gte2048; + u32 rmon_r_octets; + + u32 ieee_r_drop; + u32 ieee_r_frame_ok; + u32 ieee_r_crc; + u32 ieee_r_align; + u32 ieee_r_macerr; + u32 ieee_r_fdxfc; + u32 ieee_r_octets_ok; +} fec_t; + +/********************************************************************* +* Fast Ethernet Controller (FEC) +*********************************************************************/ +/* Bit definitions and macros for FEC_EIR */ +#define FEC_EIR_CLEAR_ALL (0xFFF80000) +#define FEC_EIR_HBERR (0x80000000) +#define FEC_EIR_BABR (0x40000000) +#define FEC_EIR_BABT (0x20000000) +#define FEC_EIR_GRA (0x10000000) +#define FEC_EIR_TXF (0x08000000) +#define FEC_EIR_TXB (0x04000000) +#define FEC_EIR_RXF (0x02000000) +#define FEC_EIR_RXB (0x01000000) +#define FEC_EIR_MII (0x00800000) +#define FEC_EIR_EBERR (0x00400000) +#define FEC_EIR_LC (0x00200000) +#define FEC_EIR_RL (0x00100000) +#define FEC_EIR_UN (0x00080000) + +/* Bit definitions and macros for FEC_RDAR */ +#define FEC_RDAR_R_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for FEC_TDAR */ +#define FEC_TDAR_X_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for FEC_ECR */ +#define FEC_ECR_ETHER_EN (0x00000002) +#define FEC_ECR_RESET (0x00000001) + +/* Bit definitions and macros for FEC_MMFR */ +#define FEC_MMFR_DATA(x) (((x)&0xFFFF)) +#define FEC_MMFR_ST(x) (((x)&0x03)<<30) +#define FEC_MMFR_ST_01 (0x40000000) +#define FEC_MMFR_OP_RD (0x20000000) +#define FEC_MMFR_OP_WR (0x10000000) +#define FEC_MMFR_PA(x) (((x)&0x1F)<<23) +#define FEC_MMFR_RA(x) (((x)&0x1F)<<18) +#define FEC_MMFR_TA(x) (((x)&0x03)<<16) +#define FEC_MMFR_TA_10 (0x00020000) + +/* Bit definitions and macros for FEC_MSCR */ +#define FEC_MSCR_DIS_PREAMBLE (0x00000080) +#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1) + +/* Bit definitions and macros for FEC_MIBC */ +#define FEC_MIBC_MIB_DISABLE (0x80000000) +#define FEC_MIBC_MIB_IDLE (0x40000000) + +/* Bit definitions and macros for FEC_RCR */ +#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16) +#define FEC_RCR_FCE (0x00000020) +#define FEC_RCR_BC_REJ (0x00000010) +#define FEC_RCR_PROM (0x00000008) +#define FEC_RCR_MII_MODE (0x00000004) +#define FEC_RCR_DRT (0x00000002) +#define FEC_RCR_LOOP (0x00000001) + +/* Bit definitions and macros for FEC_TCR */ +#define FEC_TCR_RFC_PAUSE (0x00000010) +#define FEC_TCR_TFC_PAUSE (0x00000008) +#define FEC_TCR_FDEN (0x00000004) +#define FEC_TCR_HBC (0x00000002) +#define FEC_TCR_GTS (0x00000001) + +/* Bit definitions and macros for FEC_PAUR */ +#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16) +#define FEC_PAUR_TYPE(x) ((x)&0xFFFF) + +/* Bit definitions and macros for FEC_OPD */ +#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) +#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for FEC_TFWR */ +#define FEC_TFWR_X_WMRK(x) ((x)&0x03) +#define FEC_TFWR_X_WMRK_64 (0x01) +#define FEC_TFWR_X_WMRK_128 (0x02) +#define FEC_TFWR_X_WMRK_192 (0x03) + +/* Bit definitions and macros for FEC_FRBR */ +#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2) + +/* Bit definitions and macros for FEC_FRSR */ +#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2) + +/* Bit definitions and macros for FEC_ERDSR */ +#define FEC_ERDSR_R_DES_START(x)(((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for FEC_ETDSR */ +#define FEC_ETDSR_X_DES_START(x)(((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for FEC_EMRBR */ +#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4) + +#define FEC_RESET_DELAY 100 +#define FEC_RX_TOUT 100 + +#endif /* CONFIG_MCFFEC */ +#endif /* fec_h */ diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h new file mode 100644 index 00000000000..5ef1265f815 --- /dev/null +++ b/include/asm-m68k/immap_5329.h @@ -0,0 +1,793 @@ +/* + * MCF5329 Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5329__ +#define __IMMAP_5329__ + +#define MMAP_SCM1 0xEC000000 +#define MMAP_MDHA 0xEC080000 +#define MMAP_SKHA 0xEC084000 +#define MMAP_RNG 0xEC088000 +#define MMAP_SCM2 0xFC000000 +#define MMAP_XBS 0xFC004000 +#define MMAP_FBCS 0xFC008000 +#define MMAP_CAN 0xFC020000 +#define MMAP_FEC 0xFC030000 +#define MMAP_SCM3 0xFC040000 +#define MMAP_EDMA 0xFC044000 +#define MMAP_TCD 0xFC045000 +#define MMAP_INTC0 0xFC048000 +#define MMAP_INTC1 0xFC04C000 +#define MMAP_INTCACK 0xFC054000 +#define MMAP_I2C 0xFC058000 +#define MMAP_QSPI 0xFC05C000 +#define MMAP_UART0 0xFC060000 +#define MMAP_UART1 0xFC064000 +#define MMAP_UART2 0xFC068000 +#define MMAP_DTMR0 0xFC070000 +#define MMAP_DTMR1 0xFC074000 +#define MMAP_DTMR2 0xFC078000 +#define MMAP_DTMR3 0xFC07C000 +#define MMAP_PIT0 0xFC080000 +#define MMAP_PIT1 0xFC084000 +#define MMAP_PIT2 0xFC088000 +#define MMAP_PIT3 0xFC08C000 +#define MMAP_PWM 0xFC090000 +#define MMAP_EPORT 0xFC094000 +#define MMAP_WDOG 0xFC098000 +#define MMAP_CCM 0xFC0A0000 +#define MMAP_GPIO 0xFC0A4000 +#define MMAP_RTC 0xFC0A8000 +#define MMAP_LCDC 0xFC0AC000 +#define MMAP_USBOTG 0xFC0B0000 +#define MMAP_USBH 0xFC0B4000 +#define MMAP_SDRAM 0xFC0B8000 +#define MMAP_SSI 0xFC0BC000 +#define MMAP_PLL 0xFC0C0000 + +/* System control module registers */ +typedef struct scm1_ctrl { + u32 mpr0; /* 0x00 Master Privilege Register 0 */ + u32 res1[15]; /* 0x04 - 0x3F */ + u32 pacrh; /* 0x40 Peripheral Access Control Register H */ + u32 res2[3]; /* 0x44 - 0x53 */ + u32 bmt0; /*0x54 Bus Monitor Timeout 0 */ +} scm1_t; + +/* Message Digest Hardware Accelerator */ +typedef struct mdha_ctrl { + u32 mdmr; /* 0x00 MDHA Mode Register */ + u32 mdcr; /* 0x04 Control register */ + u32 mdcmr; /* 0x08 Command Register */ + u32 mdsr; /* 0x0C Status Register */ + u32 mdisr; /* 0x10 Interrupt Status Register */ + u32 mdimr; /* 0x14 Interrupt Mask Register */ + u32 mddsr; /* 0x1C Data Size Register */ + u32 mdin; /* 0x20 Input FIFO */ + u32 res1[3]; /* 0x24 - 0x2F */ + u32 mdao; /* 0x30 Message Digest AO Register */ + u32 mdbo; /* 0x34 Message Digest BO Register */ + u32 mdco; /* 0x38 Message Digest CO Register */ + u32 mddo; /* 0x3C Message Digest DO Register */ + u32 mdeo; /* 0x40 Message Digest EO Register */ + u32 mdmds; /* 0x44 Message Data Size Register */ + u32 res[10]; /* 0x48 - 0x6F */ + u32 mda1; /* 0x70 Message Digest A1 Register */ + u32 mdb1; /* 0x74 Message Digest B1 Register */ + u32 mdc1; /* 0x78 Message Digest C1 Register */ + u32 mdd1; /* 0x7C Message Digest D1 Register */ + u32 mde1; /* 0x80 Message Digest E1 Register */ +} mdha_t; + +/* Symmetric Key Hardware Accelerator */ +typedef struct skha_ctrl { + u32 mr; /* 0x00 Mode Register */ + u32 cr; /* 0x04 Control Register */ + u32 cmr; /* 0x08 Command Register */ + u32 sr; /* 0x0C Status Register */ + u32 esr; /* 0x10 Error Status Register */ + u32 emr; /* 0x14 Error Status Mask Register) */ + u32 ksr; /* 0x18 Key Size Register */ + u32 dsr; /* 0x1C Data Size Register */ + u32 in; /* 0x20 Input FIFO */ + u32 out; /* 0x24 Output FIFO */ + u32 res1[2]; /* 0x28 - 0x2F */ + u32 kdr1; /* 0x30 Key Data Register 1 */ + u32 kdr2; /* 0x34 Key Data Register 2 */ + u32 kdr3; /* 0x38 Key Data Register 3 */ + u32 kdr4; /* 0x3C Key Data Register 4 */ + u32 kdr5; /* 0x40 Key Data Register 5 */ + u32 kdr6; /* 0x44 Key Data Register 6 */ + u32 res2[10]; /* 0x48 - 0x6F */ + u32 c1; /* 0x70 Context 1 */ + u32 c2; /* 0x74 Context 2 */ + u32 c3; /* 0x78 Context 3 */ + u32 c4; /* 0x7C Context 4 */ + u32 c5; /* 0x80 Context 5 */ + u32 c6; /* 0x84 Context 6 */ + u32 c7; /* 0x88 Context 7 */ + u32 c8; /* 0x8C Context 8 */ + u32 c9; /* 0x90 Context 9 */ + u32 c10; /* 0x94 Context 10 */ + u32 c11; /* 0x98 Context 11 */ +} skha_t; + +/* Random Number Generator */ +typedef struct rng_ctrl { + u32 rngcr; /* 0x00 RNG Control Register */ + u32 rngsr; /* 0x04 RNG Status Register */ + u32 rnger; /* 0x08 RNG Entropy Register */ + u32 rngout; /* 0x0C RNG Output FIFO */ +} rng_t; + +/* System control module registers 2 */ +typedef struct scm2_ctrl { + u32 mpr1; /* 0x00 Master Privilege Register */ + u32 res1[7]; /* 0x04 - 0x1F */ + u32 pacra; /* 0x20 Peripheral Access Control Register A */ + u32 pacrb; /* 0x24 Peripheral Access Control Register B */ + u32 pacrc; /* 0x28 Peripheral Access Control Register C */ + u32 pacrd; /* 0x2C Peripheral Access Control Register D */ + u32 res2[4]; /* 0x30 - 0x3F */ + u32 pacre; /* 0x40 Peripheral Access Control Register E */ + u32 pacrf; /* 0x44 Peripheral Access Control Register F */ + u32 pacrg; /* 0x48 Peripheral Access Control Register G */ + u32 res3[2]; /* 0x4C - 0x53 */ + u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */ +} scm2_t; + +/* Cross-Bar Switch Module */ +typedef struct xbs_ctrl { + u32 prs1; /* 0x100 Priority Register Slave 1 */ + u32 res1[3]; /* 0x104 - 0F */ + u32 crs1; /* 0x110 Control Register Slave 1 */ + u32 res2[187]; /* 0x114 - 0x3FF */ + + u32 prs4; /* 0x400 Priority Register Slave 4 */ + u32 res3[3]; /* 0x404 - 0F */ + u32 crs4; /* 0x410 Control Register Slave 4 */ + u32 res4[123]; /* 0x414 - 0x5FF */ + + u32 prs6; /* 0x600 Priority Register Slave 6 */ + u32 res5[3]; /* 0x604 - 0F */ + u32 crs6; /* 0x610 Control Register Slave 6 */ + u32 res6[59]; /* 0x614 - 0x6FF */ + + u32 prs7; /* 0x700 Priority Register Slave 7 */ + u32 res7[3]; /* 0x704 - 0F */ + u32 crs7; /* 0x710 Control Register Slave 7 */ +} xbs_t; + +/* Flexbus module Chip select registers */ +typedef struct fbcs_ctrl { + u16 csar0; /* 0x00 Chip-Select Address Register 0 */ + u16 res0; + u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */ + u32 cscr0; /* 0x08 Chip-Select Control Register 0 */ + + u16 csar1; /* 0x0C Chip-Select Address Register 1 */ + u16 res1; + u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */ + u32 cscr1; /* 0x14 Chip-Select Control Register 1 */ + + u16 csar2; /* 0x18 Chip-Select Address Register 2 */ + u16 res2; + u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */ + u32 cscr2; /* 0x20 Chip-Select Control Register 2 */ + + u16 csar3; /* 0x24 Chip-Select Address Register 3 */ + u16 res3; + u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */ + u32 cscr3; /* 0x2C Chip-Select Control Register 3 */ + + u16 csar4; /* 0x30 Chip-Select Address Register 4 */ + u16 res4; + u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */ + u32 cscr4; /* 0x38 Chip-Select Control Register 4 */ + + u16 csar5; /* 0x3C Chip-Select Address Register 5 */ + u16 res5; + u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */ + u32 cscr5; /* 0x44 Chip-Select Control Register 5 */ +} fbcs_t; + +/* FlexCan module registers */ +typedef struct can_ctrl { + u32 mcr; /* 0x00 Module Configuration register */ + u32 ctrl; /* 0x04 Control register */ + u32 timer; /* 0x08 Free Running Timer */ + u32 res1; /* 0x0C */ + u32 rxgmask; /* 0x10 Rx Global Mask */ + u32 rx14mask; /* 0x14 RxBuffer 14 Mask */ + u32 rx15mask; /* 0x18 RxBuffer 15 Mask */ + u32 errcnt; /* 0x1C Error Counter Register */ + u32 errstat; /* 0x20 Error and status Register */ + u32 res2; /* 0x24 */ + u32 imask; /* 0x28 Interrupt Mask Register */ + u32 res3; /* 0x2C */ + u32 iflag; /* 0x30 Interrupt Flag Register */ + u32 res4[19]; /* 0x34 - 0x7F */ + u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */ +} can_t; + +/* System Control Module register 3 */ +typedef struct scm3_ctrl { + u8 res1[19]; /* 0x00 - 0x12 */ + u8 wcr; /* 0x13 wakeup control register */ + u16 res2; /* 0x14 - 0x15 */ + u16 cwcr; /* 0x16 Core Watchdog Control Register */ + u8 res3[3]; /* 0x18 - 0x1A */ + u8 cwsr; /* 0x1B Core Watchdog Service Register */ + u8 res4[2]; /* 0x1C - 0x1D */ + u8 scmisr; /* 0x1F Interrupt Status Register */ + u32 res5; /* 0x20 */ + u32 bcr; /* 0x24 Burst Configuration Register */ + u32 res6[18]; /* 0x28 - 0x6F */ + u32 cfadr; /* 0x70 Core Fault Address Register */ + u8 res7[4]; /* 0x71 - 0x74 */ + u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */ + u8 cfloc; /* 0x76 Core Fault Location Register */ + u8 cfatr; /* 0x77 Core Fault Attributes Register */ + u32 res8; /* 0x78 */ + u32 cfdtr; /* 0x7C Core Fault Data Register */ +} scm3_t; + +/* eDMA module registers */ +typedef struct edma_ctrl { + u32 cr; /* 0x00 Control Register */ + u32 es; /* 0x04 Error Status Register */ + u16 res1[3]; /* 0x08 - 0x0D */ + u16 erq; /* 0x0E Enable Request Register */ + u16 res2[3]; /* 0x10 - 0x15 */ + u16 eei; /* 0x16 Enable Error Interrupt Request */ + u8 serq; /* 0x18 Set Enable Request */ + u8 cerq; /* 0x19 Clear Enable Request */ + u8 seei; /* 0x1A Set Enable Error Interrupt Request */ + u8 ceei; /* 0x1B Clear Enable Error Interrupt Request */ + u8 cint; /* 0x1C Clear Interrupt Enable Register */ + u8 cerr; /* 0x1D Clear Error Register */ + u8 ssrt; /* 0x1E Set START Bit Register */ + u8 cdne; /* 0x1F Clear DONE Status Bit Register */ + u16 res3[3]; /* 0x20 - 0x25 */ + u16 intr; /* 0x26 Interrupt Request Register */ + u16 res4[3]; /* 0x28 - 0x2D */ + u16 err; /* 0x2E Error Register */ + u32 res5[52]; /* 0x30 - 0xFF */ + u8 dchpri0; /* 0x100 Channel 0 Priority Register */ + u8 dchpri1; /* 0x101 Channel 1 Priority Register */ + u8 dchpri2; /* 0x102 Channel 2 Priority Register */ + u8 dchpri3; /* 0x103 Channel 3 Priority Register */ + u8 dchpri4; /* 0x104 Channel 4 Priority Register */ + u8 dchpri5; /* 0x105 Channel 5 Priority Register */ + u8 dchpri6; /* 0x106 Channel 6 Priority Register */ + u8 dchpri7; /* 0x107 Channel 7 Priority Register */ + u8 dchpri8; /* 0x108 Channel 8 Priority Register */ + u8 dchpri9; /* 0x109 Channel 9 Priority Register */ + u8 dchpri10; /* 0x110 Channel 10 Priority Register */ + u8 dchpri11; /* 0x111 Channel 11 Priority Register */ + u8 dchpri12; /* 0x112 Channel 12 Priority Register */ + u8 dchpri13; /* 0x113 Channel 13 Priority Register */ + u8 dchpri14; /* 0x114 Channel 14 Priority Register */ + u8 dchpri15; /* 0x115 Channel 15 Priority Register */ +} edma_t; + +/* TCD - eDMA*/ +typedef struct tcd_ctrl { + u32 saddr; /* 0x00 Source Address */ + u16 attr; /* 0x04 Transfer Attributes */ + u16 soff; /* 0x06 Signed Source Address Offset */ + u32 nbytes; /* 0x08 Minor Byte Count */ + u32 slast; /* 0x0C Last Source Address Adjustment */ + u32 daddr; /* 0x10 Destination address */ + u16 citer; /* 0x14 Current Minor Loop Link, Major Loop Count */ + u16 doff; /* 0x16 Signed Destination Address Offset */ + u32 dlast_sga; /* 0x18 Last Destination Address Adjustment/Scatter Gather Address */ + u16 biter; /* 0x1C Beginning Minor Loop Link, Major Loop Count */ + u16 csr; /* 0x1E Control and Status */ +} tcd_st; + +typedef struct tcd_multiple { + tcd_st tcd[16]; +} tcd_t; + +/* Interrupt module registers */ +typedef struct int0_ctrl { + /* Interrupt Controller 0 */ + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 - 0x19 */ + u16 icfg0; /* 0x1A Configuration Register */ + u8 simr0; /* 0x1C Set Interrupt Mask */ + u8 cimr0; /* 0x1D Clear Interrupt Mask */ + u8 clmask0; /* 0x1E Current Level Mask */ + u8 slmask; /* 0x1F Saved Level Mask */ + u32 res2[8]; /* 0x20 - 0x3F */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; + +typedef struct int1_ctrl { + /* Interrupt Controller 1 */ + u32 iprh1; /* 0x00 Pending Register High */ + u32 iprl1; /* 0x04 Pending Register Low */ + u32 imrh1; /* 0x08 Mask Register High */ + u32 imrl1; /* 0x0C Mask Register Low */ + u32 frch1; /* 0x10 Force Register High */ + u32 frcl1; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 */ + u16 icfg1; /* 0x1A Configuration Register */ + u8 simr1; /* 0x1C Set Interrupt Mask */ + u8 cimr1; /* 0x1D Clear Interrupt Mask */ + u16 res2; /* 0x1E - 0x1F */ + u32 res3[8]; /* 0x20 - 0x3F */ + u8 icr1[64]; /* 0x40 - 0x7F */ + u32 res4[24]; /* 0x80 - 0xDF */ + u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */ + u8 res5[3]; /* 0xE1 - 0xE3 */ + u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE5 - 0xE7 */ + u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xE9 - 0xEB */ + u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xED - 0xEF */ + u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF1 - 0xF3 */ + u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF5 - 0xF7 */ + u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xF9 - 0xFB */ + u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resc[3]; /* 0xFD - 0xFF */ +} int1_t; + +typedef struct intgack_ctrl1 { + /* Global IACK Registers */ + u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */ + u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */ +} intgack_t; + +/*I2C module registers */ +typedef struct i2c_ctrl { + u8 adr; /* 0x00 address register */ + u8 res1[3]; /* 0x01 - 0x03 */ + u8 fdr; /* 0x04 frequency divider register */ + u8 res2[3]; /* 0x05 - 0x07 */ + u8 cr; /* 0x08 control register */ + u8 res3[3]; /* 0x09 - 0x0B */ + u8 sr; /* 0x0C status register */ + u8 res4[3]; /* 0x0D - 0x0F */ + u8 dr; /* 0x10 data register */ + u8 res5[3]; /* 0x11 - 0x13 */ +} i2c_t; + +/* QSPI module registers */ +typedef struct qspi_ctrl { + u16 qmr; /* Mode register */ + u16 res1; + u16 qdlyr; /* Delay register */ + u16 res2; + u16 qwr; /* Wrap register */ + u16 res3; + u16 qir; /* Interrupt register */ + u16 res4; + u16 qar; /* Address register */ + u16 res5; + u16 qdr; /* Data register */ + u16 res6; +} qspi_t; + +/* PWM module registers */ +typedef struct pwm_ctrl { + u8 en; /* 0x00 PWM Enable Register */ + u8 pol; /* 0x01 Polarity Register */ + u8 clk; /* 0x02 Clock Select Register */ + u8 prclk; /* 0x03 Prescale Clock Select Register */ + u8 cae; /* 0x04 Center Align Enable Register */ + u8 ctl; /* 0x05 Control Register */ + u8 res1[2]; /* 0x06 - 0x07 */ + u8 scla; /* 0x08 Scale A register */ + u8 sclb; /* 0x09 Scale B register */ + u8 res2[2]; /* 0x0A - 0x0B */ + u8 cnt0; /* 0x0C Channel 0 Counter register */ + u8 cnt1; /* 0x0D Channel 1 Counter register */ + u8 cnt2; /* 0x0E Channel 2 Counter register */ + u8 cnt3; /* 0x0F Channel 3 Counter register */ + u8 cnt4; /* 0x10 Channel 4 Counter register */ + u8 cnt5; /* 0x11 Channel 5 Counter register */ + u8 cnt6; /* 0x12 Channel 6 Counter register */ + u8 cnt7; /* 0x13 Channel 7 Counter register */ + u8 per0; /* 0x14 Channel 0 Period register */ + u8 per1; /* 0x15 Channel 1 Period register */ + u8 per2; /* 0x16 Channel 2 Period register */ + u8 per3; /* 0x17 Channel 3 Period register */ + u8 per4; /* 0x18 Channel 4 Period register */ + u8 per5; /* 0x19 Channel 5 Period register */ + u8 per6; /* 0x1A Channel 6 Period register */ + u8 per7; /* 0x1B Channel 7 Period register */ + u8 dty0; /* 0x1C Channel 0 Duty register */ + u8 dty1; /* 0x1D Channel 1 Duty register */ + u8 dty2; /* 0x1E Channel 2 Duty register */ + u8 dty3; /* 0x1F Channel 3 Duty register */ + u8 dty4; /* 0x20 Channel 4 Duty register */ + u8 dty5; /* 0x21 Channel 5 Duty register */ + u8 dty6; /* 0x22 Channel 6 Duty register */ + u8 dty7; /* 0x23 Channel 7 Duty register */ + u8 sdn; /* 0x24 Shutdown register */ + u8 res3[3]; /* 0x25 - 0x27 */ +} pwm_t; + +/* Edge Port module registers */ +typedef struct eport_ctrl { + u16 par; /* 0x00 Pin Assignment Register */ + u8 ddar; /* 0x02 Data Direction Register */ + u8 ier; /* 0x03 Interrupt Enable Register */ + u8 dr; /* 0x04 Data Register */ + u8 pdr; /* 0x05 Pin Data Register */ + u8 fr; /* 0x06 Flag_Register */ + u8 res1; +} eport_t; + +/* Watchdog registers */ +typedef struct wdog_ctrl { + u16 cr; /* 0x00 Control register */ + u16 mr; /* 0x02 Modulus register */ + u16 cntr; /* 0x04 Count register */ + u16 sr; /* 0x06 Service register */ +} wdog_t; + +/*Chip configuration module registers */ +typedef struct ccm_ctrl { + u8 rstctrl; /* 0x00 Reset Controller register */ + u8 rststat; /* 0x01 Reset Status register */ + u16 res1; /* 0x02 - 0x03 */ + u16 ccr; /* 0x04 Chip configuration register */ + u16 res2; /* 0x06 */ + u16 rcon; /* 0x08 Rreset configuration register */ + u16 cir; /* 0x0A Chip identification register */ + u32 res3; /* 0x0C */ + u16 misccr; /* 0x10 Miscellaneous control register */ + u16 cdr; /* 0x12 Clock divider register */ + u16 uhcsr; /* 0x14 USB Host controller status register */ + u16 uocsr; /* 0x16 USB On-the-Go Controller Status Register */ +} ccm_t; + +/* GPIO port registers */ +typedef struct gpio_ctrl { + /* Port Output Data Registers */ + u8 podr_fech; /* 0x00 */ + u8 podr_fecl; /* 0x01 */ + u8 podr_ssi; /* 0x02 */ + u8 podr_busctl; /* 0x03 */ + u8 podr_be; /* 0x04 */ + u8 podr_cs; /* 0x05 */ + u8 podr_pwm; /* 0x06 */ + u8 podr_feci2c; /* 0x07 */ + u8 res1; /* 0x08 */ + u8 podr_uart; /* 0x09 */ + u8 podr_qspi; /* 0x0A */ + u8 podr_timer; /* 0x0B */ + u8 res2; /* 0x0C */ + u8 podr_lcddatah; /* 0x0D */ + u8 podr_lcddatam; /* 0x0E */ + u8 podr_lcddatal; /* 0x0F */ + u8 podr_lcdctlh; /* 0x10 */ + u8 podr_lcdctll; /* 0x11 */ + + /* Port Data Direction Registers */ + u16 res3; /* 0x12 - 0x13 */ + u8 pddr_fech; /* 0x14 */ + u8 pddr_fecl; /* 0x15 */ + u8 pddr_ssi; /* 0x16 */ + u8 pddr_busctl; /* 0x17 */ + u8 pddr_be; /* 0x18 */ + u8 pddr_cs; /* 0x19 */ + u8 pddr_pwm; /* 0x1A */ + u8 pddr_feci2c; /* 0x1B */ + u8 res4; /* 0x1C */ + u8 pddr_uart; /* 0x1D */ + u8 pddr_qspi; /* 0x1E */ + u8 pddr_timer; /* 0x1F */ + u8 res5; /* 0x20 */ + u8 pddr_lcddatah; /* 0x21 */ + u8 pddr_lcddatam; /* 0x22 */ + u8 pddr_lcddatal; /* 0x23 */ + u8 pddr_lcdctlh; /* 0x24 */ + u8 pddr_lcdctll; /* 0x25 */ + u16 res6; /* 0x26 - 0x27 */ + + /* Port Data Direction Registers */ + u8 ppd_fech; /* 0x28 */ + u8 ppd_fecl; /* 0x29 */ + u8 ppd_ssi; /* 0x2A */ + u8 ppd_busctl; /* 0x2B */ + u8 ppd_be; /* 0x2C */ + u8 ppd_cs; /* 0x2D */ + u8 ppd_pwm; /* 0x2E */ + u8 ppd_feci2c; /* 0x2F */ + u8 res7; /* 0x30 */ + u8 ppd_uart; /* 0x31 */ + u8 ppd_qspi; /* 0x32 */ + u8 ppd_timer; /* 0x33 */ + u8 res8; /* 0x34 */ + u8 ppd_lcddatah; /* 0x35 */ + u8 ppd_lcddatam; /* 0x36 */ + u8 ppd_lcddatal; /* 0x37 */ + u8 ppd_lcdctlh; /* 0x38 */ + u8 ppd_lcdctll; /* 0x39 */ + u16 res9; /* 0x3A - 0x3B */ + + /* Port Clear Output Data Registers */ + u8 pclrr_fech; /* 0x3C */ + u8 pclrr_fecl; /* 0x3D */ + u8 pclrr_ssi; /* 0x3E */ + u8 pclrr_busctl; /* 0x3F */ + u8 pclrr_be; /* 0x40 */ + u8 pclrr_cs; /* 0x41 */ + u8 pclrr_pwm; /* 0x42 */ + u8 pclrr_feci2c; /* 0x43 */ + u8 res10; /* 0x44 */ + u8 pclrr_uart; /* 0x45 */ + u8 pclrr_qspi; /* 0x46 */ + u8 pclrr_timer; /* 0x47 */ + u8 res11; /* 0x48 */ + u8 pclrr_lcddatah; /* 0x49 */ + u8 pclrr_lcddatam; /* 0x4A */ + u8 pclrr_lcddatal; /* 0x4B */ + u8 pclrr_lcdctlh; /* 0x4C */ + u8 pclrr_lcdctll; /* 0x4D */ + u16 res12; /* 0x4E - 0x4F */ + + /* Pin Assignment Registers */ + u8 par_fec; /* 0x50 */ + u8 par_pwm; /* 0x51 */ + u8 par_busctl; /* 0x52 */ + u8 par_feci2c; /* 0x53 */ + u8 par_be; /* 0x54 */ + u8 par_cs; /* 0x55 */ + u16 par_ssi; /* 0x56 */ + u16 par_uart; /* 0x58 */ + u16 par_qspi; /* 0x5A */ + u8 par_timer; /* 0x5C */ + u8 par_lcddata; /* 0x5D */ + u16 par_lcdctl; /* 0x5E */ + u16 par_irq; /* 0x60 */ + u16 res16; /* 0x62 - 0x63 */ + + /* Mode Select Control Registers */ + u8 mscr_flexbus; /* 0x64 */ + u8 mscr_sdram; /* 0x65 */ + u16 res17; /* 0x66 - 0x67 */ + + /* Drive Strength Control Registers */ + u8 dscr_i2c; /* 0x68 */ + u8 dscr_pwm; /* 0x69 */ + u8 dscr_fec; /* 0x6A */ + u8 dscr_uart; /* 0x6B */ + u8 dscr_qspi; /* 0x6C */ + u8 dscr_timer; /* 0x6D */ + u8 dscr_ssi; /* 0x6E */ + u8 dscr_lcd; /* 0x6F */ + u8 dscr_debug; /* 0x70 */ + u8 dscr_clkrst; /* 0x71 */ + u8 dscr_irq; /* 0x72 */ +} gpio_t; + +/* LCD module registers */ +typedef struct lcd_ctrl { + u32 ssar; /* 0x00 Screen Start Address Register */ + u32 sr; /* 0x04 LCD Size Register */ + u32 vpw; /* 0x08 Virtual Page Width Register */ + u32 cpr; /* 0x0C Cursor Position Register */ + u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */ + u32 ccmr; /* 0x14 Color Cursor Mapping Register */ + u32 pcr; /* 0x18 Panel Configuration Register */ + u32 hcr; /* 0x1C Horizontal Configuration Register */ + u32 vcr; /* 0x20 Vertical Configuration Register */ + u32 por; /* 0x24 Panning Offset Register */ + u32 scr; /* 0x28 Sharp Configuration Register */ + u32 pccr; /* 0x2C PWM Contrast Control Register */ + u32 dcr; /* 0x30 DMA Control Register */ + u32 rmcr; /* 0x34 Refresh Mode Control Register */ + u32 icr; /* 0x38 Refresh Mode Control Register */ + u32 ier; /* 0x3C Interrupt Enable Register */ + u32 isr; /* 0x40 Interrupt Status Register */ + u32 res[4]; + u32 gwsar; /* 0x50 Graphic Window Start Address Register */ + u32 gwsr; /* 0x54 Graphic Window Size Register */ + u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */ + u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */ + u32 gwpr; /* 0x60 Graphic Window Position Register */ + u32 gwcr; /* 0x64 Graphic Window Control Register */ + u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */ +} lcd_t; + +typedef struct lcdbg_ctrl { + u32 bglut[255]; +} lcdbg_t; + +typedef struct lcdgw_ctrl { + u32 gwlut[255]; +} lcdgw_t; + +/* USB OTG module registers */ +typedef struct usb_otg { + u32 id; /* 0x000 Identification Register */ + u32 hwgeneral; /* 0x004 General HW Parameters */ + u32 hwhost; /* 0x008 Host HW Parameters */ + u32 hwdev; /* 0x00C Device HW parameters */ + u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */ + u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */ + u32 res1[58]; /* 0x18 - 0xFF */ + u8 caplength; /* 0x100 Capability Register Length */ + u8 res2; /* 0x101 */ + u16 hciver; /* 0x102 Host Interface Version Number */ + u32 hcsparams; /* 0x104 Host Structural Parameters */ + u32 hccparams; /* 0x108 Host Capability Parameters */ + u32 res3[5]; /* 0x10C - 0x11F */ + u16 dciver; /* 0x120 Device Interface Version Number */ + u16 res4; /* 0x122 */ + u32 dccparams; /* 0x124 Device Capability Parameters */ + u32 res5[6]; /* 0x128 - 0x13F */ + u32 cmd; /* 0x140 USB Command */ + u32 sts; /* 0x144 USB Status */ + u32 intr; /* 0x148 USB Interrupt Enable */ + u32 frindex; /* 0x14C USB Frame Index */ + u32 res6; /* 0x150 */ + u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */ + u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */ + u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */ + u32 burstsize; /* 0x160 Master Interface Data Burst Size */ + u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */ + u32 res7[6]; /* 0x168 - 0x17F */ + u32 cfgflag; /* 0x180 Configure Flag Register */ + u32 portsc1; /* 0x184 Port Status/Control */ + u32 res8[7]; /* 0x188 - 0x1A3 */ + u32 otgsc; /* 0x1A4 On The Go Status and Control */ + u32 mode; /* 0x1A8 USB mode register */ + u32 eptsetstat; /* 0x1AC Endpoint Setup status */ + u32 eptprime; /* 0x1B0 Endpoint initialization */ + u32 eptflush; /* 0x1B4 Endpoint de-initialize */ + u32 eptstat; /* 0x1B8 Endpoint status */ + u32 eptcomplete; /* 0x1BC Endpoint Complete */ + u32 eptctrl0; /* 0x1C0 Endpoint control 0 */ + u32 eptctrl1; /* 0x1C4 Endpoint control 1 */ + u32 eptctrl2; /* 0x1C8 Endpoint control 2 */ + u32 eptctrl3; /* 0x1CC Endpoint control 3 */ +} usbotg_t; + +/* USB Host module registers */ +typedef struct usb_host { + u32 id; /* 0x000 Identification Register */ + u32 hwgeneral; /* 0x004 General HW Parameters */ + u32 hwhost; /* 0x008 Host HW Parameters */ + u32 res1; /* 0x0C */ + u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */ + u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */ + u32 res2[58]; /* 0x18 - 0xFF */ + + /* Host Controller Capability Register */ + u8 caplength; /* 0x100 Capability Register Length */ + u8 res3; /* 0x101 */ + u16 hciver; /* 0x102 Host Interface Version Number */ + u32 hcsparams; /* 0x104 Host Structural Parameters */ + u32 hccparams; /* 0x108 Host Capability Parameters */ + u32 res4[13]; /* 0x10C - 0x13F */ + + /* Host Controller Operational Register */ + u32 cmd; /* 0x140 USB Command */ + u32 sts; /* 0x144 USB Status */ + u32 intr; /* 0x148 USB Interrupt Enable */ + u32 frindex; /* 0x14C USB Frame Index */ + u32 res5; /* 0x150 (ctrl segment register in EHCI spec) */ + u32 prdlst; /* 0x154 Periodic Frame List Base Address */ + u32 aynclst; /* 0x158 Current Asynchronous List Address */ + u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */ + u32 burstsize; /* 0x160 Master Interface Data Burst Size (non-ehci) */ + u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control (non-ehci) */ + u32 res6[6]; /* 0x168 - 0x17F */ + u32 cfgflag; /* 0x180 Configure Flag Register */ + u32 portsc1; /* 0x184 Port Status/Control */ + u32 res7[8]; /* 0x188 - 0x1A7 */ + + /* non-ehci registers */ + u32 mode; /* 0x1A8 USB mode register */ + u32 eptsetstat; /* 0x1AC Endpoint Setup status */ + u32 eptprime; /* 0x1B0 Endpoint initialization */ + u32 eptflush; /* 0x1B4 Endpoint de-initialize */ + u32 eptstat; /* 0x1B8 Endpoint status */ + u32 eptcomplete; /* 0x1BC Endpoint Complete */ + u32 eptctrl0; /* 0x1C0 Endpoint control 0 */ + u32 eptctrl1; /* 0x1C4 Endpoint control 1 */ + u32 eptctrl2; /* 0x1C8 Endpoint control 2 */ + u32 eptctrl3; /* 0x1CC Endpoint control 3 */ +} usbhost_t; + +/* SDRAM controller registers */ +typedef struct sdram_ctrl { + u32 mode; /* 0x00 Mode/Extended Mode register */ + u32 ctrl; /* 0x04 Control register */ + u32 cfg1; /* 0x08 Configuration register 1 */ + u32 cfg2; /* 0x0C Configuration register 2 */ + u32 res1[64]; /* 0x10 - 0x10F */ + u32 cs0; /* 0x110 Chip Select 0 Configuration */ + u32 cs1; /* 0x114 Chip Select 1 Configuration */ +} sdram_t; + +/* Synchronous serial interface */ +typedef struct ssi_ctrl { + u32 tx0; /* 0x00 Transmit Data Register 0 */ + u32 tx1; /* 0x04 Transmit Data Register 1 */ + u32 rx0; /* 0x08 Receive Data Register 0 */ + u32 rx1; /* 0x0C Receive Data Register 1 */ + u32 cr; /* 0x10 Control Register */ + u32 isr; /* 0x14 Interrupt Status Register */ + u32 ier; /* 0x18 Interrupt Enable Register */ + u32 tcr; /* 0x1C Transmit Configuration Register */ + u32 rcr; /* 0x20 Receive Configuration Register */ + u32 ccr; /* 0x24 Clock Control Register */ + u32 res1; /* 0x28 */ + u32 fcsr; /* 0x2C FIFO Control/Status Register */ + u32 res2[2]; /* 0x30 - 0x37 */ + u32 acr; /* 0x38 AC97 Control Register */ + u32 acadd; /* 0x3C AC97 Command Address Register */ + u32 acdat; /* 0x40 AC97 Command Data Register */ + u32 atag; /* 0x44 AC97 Tag Register */ + u32 tmask; /* 0x48 Transmit Time Slot Mask Register */ + u32 rmask; /* 0x4C Receive Time Slot Mask Register */ +} ssi_t; + +/* Clock Module registers */ +typedef struct pll_ctrl { + u8 podr; /* 0x00 Output Divider Register */ + u8 res1[3]; + u8 pcr; /* 0x04 Control Register */ + u8 res2[3]; + u8 pmdr; /* 0x08 Modulation Divider Register */ + u8 res3[3]; + u8 pfdr; /* 0x0C Feedback Divider Register */ + u8 res4[3]; +} pll_t; + +#endif /* __IMMAP_5329__ */ diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 7bbdefba760..cec25d0bf7d 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -1,8 +1,214 @@ -#ifndef __ASM_M68K_IO_H_ -#define __ASM_M68K_IO_H_ +/* + * IO header file + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ -static inline void sync(void) + #ifndef __ASM_M68K_IO_H__ +#define __ASM_M68K_IO_H__ + +#include + +#define readb(addr) in_8((volatile u8 *)(addr)) +#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) +#if !defined(__BIG_ENDIAN) +#define readw(addr) (*(volatile u16 *) (addr)) +#define readl(addr) (*(volatile u32 *) (addr)) +#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) +#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) +#else +#define readw(addr) in_le16((volatile u16 *)(addr)) +#define readl(addr) in_le32((volatile u32 *)(addr)) +#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) +#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) +#endif + +/* + * The insw/outsw/insl/outsl macros don't do byte-swapping. + * They are only used in practice for transferring buffers which + * are arrays of bytes, and byte-swapping is not appropriate in + * that case. - paulus + */ +#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + +#define inb(port) in_8((u8 *)((port)+_IO_BASE)) +#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) +#if !defined(__BIG_ENDIAN) +#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) +#else +#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) +#endif + +extern inline void _insb(volatile u8 * port, void *buf, int ns) +{ + u8 *data = (u8 *) buf; + while (ns--) + *data++ = *port; +} + +extern inline void _outsb(volatile u8 * port, const void *buf, int ns) +{ + u8 *data = (u8 *) buf; + while (ns--) + *port = *data++; +} + +extern inline void _insw(volatile u16 * port, void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) + *data++ = __sw16(*port); +} + +extern inline void _outsw(volatile u16 * port, const void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) { + *port = __sw16(*data); + data++; + } +} + +extern inline void _insl(volatile u32 * port, void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) + *data++ = __sw32(*port); +} + +extern inline void _outsl(volatile u32 * port, const void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) { + *port = __sw32(*data); + data++; + } +} + +extern inline void _insw_ns(volatile u16 * port, void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) + *data++ = *port; +} + +extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) +{ + u16 *data = (u16 *) buf; + while (ns--) { + *port = *data++; + } +} + +extern inline void _insl_ns(volatile u32 * port, void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) + *data++ = *port; +} + +extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) +{ + u32 *data = (u32 *) buf; + while (nl--) { + *port = *data; + data++; + } +} + +/* + * The *_ns versions below don't do byte-swapping. + * Neither do the standard versions now, these are just here + * for older code. + */ +#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + +#define IO_SPACE_LIMIT ~0 + +/* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + */ +extern inline int in_8(volatile u8 * addr) +{ + return (int)*addr; +} + +extern inline void out_8(volatile u8 * addr, int val) +{ + *addr = (u8) val; +} + +extern inline int in_le16(volatile u16 * addr) +{ + return __sw16(*addr); +} + +extern inline int in_be16(volatile u16 * addr) +{ + return (*addr & 0xFFFF); +} + +extern inline void out_le16(volatile u16 * addr, int val) +{ + *addr = __sw16(val); +} + +extern inline void out_be16(volatile u16 * addr, int val) +{ + *addr = (u16) val; +} + +extern inline unsigned in_le32(volatile u32 * addr) +{ + return __sw32(*addr); +} + +extern inline unsigned in_be32(volatile u32 * addr) +{ + return (*addr); +} + +extern inline void out_le32(volatile unsigned *addr, int val) +{ + *addr = __sw32(val); +} + +extern inline void out_be32(volatile unsigned *addr, int val) { + *addr = val; } -#endif /* __ASM_M68K_IO_H_ */ +#endif /* __ASM_M68K_IO_H__ */ diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h new file mode 100644 index 00000000000..15bb121ed17 --- /dev/null +++ b/include/asm-m68k/m5329.h @@ -0,0 +1,2023 @@ +/* + * mcf5329.h -- Definitions for Freescale Coldfire 5329 + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef mcf5329_h +#define mcf5329_h +/****************************************************************************/ + +/********************************************************************* +* System Control Module (SCM) +*********************************************************************/ +/* Bit definitions and macros for SCM_MPR */ +#define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) +#define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) +#define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) +#define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) +#define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) +#define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) +#define MPROT_MTR 4 +#define MPROT_MTW 2 +#define MPROT_MPL 1 + +/* Bit definitions and macros for SCM_BMT */ +#define BMT_BME (0x08) +#define BMT_8 (0x07) +#define BMT_16 (0x06) +#define BMT_32 (0x05) +#define BMT_64 (0x04) +#define BMT_128 (0x03) +#define BMT_256 (0x02) +#define BMT_512 (0x01) +#define BMT_1024 (0x00) + +/* Bit definitions and macros for SCM_PACRA */ +#define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28) +#define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24) +#define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20) +#define PACR_SP 4 +#define PACR_WP 2 +#define PACR_TP 1 + +/* Bit definitions and macros for SCM_PACRB */ +#define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28) +#define SCM_PACRB_PACR12(x) (((x)&0x0F)<<12) + +/* Bit definitions and macros for SCM_PACRC */ +#define SCM_PACRC_PACR16(x) (((x)&0x0F)<<28) +#define SCM_PACRC_PACR17(x) (((x)&0x0F)<<24) +#define SCM_PACRC_PACR18(x) (((x)&0x0F)<<20) +#define SCM_PACRC_PACR19(x) (((x)&0x0F)<<16) +#define SCM_PACRC_PACR21(x) (((x)&0x0F)<<8) +#define SCM_PACRC_PACR22(x) (((x)&0x0F)<<4) +#define SCM_PACRC_PACR23(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for SCM_PACRD */ +#define SCM_PACRD_PACR24(x) (((x)&0x0F)<<28) +#define SCM_PACRD_PACR25(x) (((x)&0x0F)<<24) +#define SCM_PACRD_PACR26(x) (((x)&0x0F)<<20) +#define SCM_PACRD_PACR28(x) (((x)&0x0F)<<12) +#define SCM_PACRD_PACR29(x) (((x)&0x0F)<<8) +#define SCM_PACRD_PACR30(x) (((x)&0x0F)<<4) +#define SCM_PACRD_PACR31(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for SCM_PACRE */ +#define SCM_PACRE_PACR32(x) (((x)&0x0F)<<28) +#define SCM_PACRE_PACR33(x) (((x)&0x0F)<<24) +#define SCM_PACRE_PACR34(x) (((x)&0x0F)<<20) +#define SCM_PACRE_PACR35(x) (((x)&0x0F)<<16) +#define SCM_PACRE_PACR36(x) (((x)&0x0F)<<12) +#define SCM_PACRE_PACR37(x) (((x)&0x0F)<<8) +#define SCM_PACRE_PACR38(x) (((x)&0x0F)<<4) + +/* Bit definitions and macros for SCM_PACRF */ +#define SCM_PACRF_PACR40(x) (((x)&0x0F)<<28) +#define SCM_PACRF_PACR41(x) (((x)&0x0F)<<24) +#define SCM_PACRF_PACR42(x) (((x)&0x0F)<<20) +#define SCM_PACRF_PACR43(x) (((x)&0x0F)<<16) +#define SCM_PACRF_PACR44(x) (((x)&0x0F)<<12) +#define SCM_PACRF_PACR45(x) (((x)&0x0F)<<8) +#define SCM_PACRF_PACR46(x) (((x)&0x0F)<<4) +#define SCM_PACRF_PACR47(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for SCM_PACRG */ +#define SCM_PACRG_PACR48(x) (((x)&0x0F)<<28) + +/* Bit definitions and macros for SCM_PACRH */ +#define SCM_PACRH_PACR56(x) (((x)&0x0F)<<28) +#define SCM_PACRH_PACR57(x) (((x)&0x0F)<<24) +#define SCM_PACRH_PACR58(x) (((x)&0x0F)<<20) + +/* PACRn Assignments */ +#define PACR0(x) SCM_PACRA_PACR0(x) +#define PACR1(x) SCM_PACRA_PACR1(x) +#define PACR2(x) SCM_PACRA_PACR2(x) +#define PACR8(x) SCM_PACRB_PACR8(x) +#define PACR12(x) SCM_PACRB_PACR12(x) +#define PACR16(x) SCM_PACRC_PACR16(x) +#define PACR17(x) SCM_PACRC_PACR17(x) +#define PACR18(x) SCM_PACRC_PACR18(x) +#define PACR19(x) SCM_PACRC_PACR19(x) +#define PACR21(x) SCM_PACRC_PACR21(x) +#define PACR22(x) SCM_PACRC_PACR22(x) +#define PACR23(x) SCM_PACRC_PACR23(x) +#define PACR24(x) SCM_PACRD_PACR24(x) +#define PACR25(x) SCM_PACRD_PACR25(x) +#define PACR26(x) SCM_PACRD_PACR26(x) +#define PACR28(x) SCM_PACRD_PACR28(x) +#define PACR29(x) SCM_PACRD_PACR29(x) +#define PACR30(x) SCM_PACRD_PACR30(x) +#define PACR31(x) SCM_PACRD_PACR31(x) +#define PACR32(x) SCM_PACRE_PACR32(x) +#define PACR33(x) SCM_PACRE_PACR33(x) +#define PACR34(x) SCM_PACRE_PACR34(x) +#define PACR35(x) SCM_PACRE_PACR35(x) +#define PACR36(x) SCM_PACRE_PACR36(x) +#define PACR37(x) SCM_PACRE_PACR37(x) +#define PACR38(x) SCM_PACRE_PACR38(x) +#define PACR40(x) SCM_PACRF_PACR40(x) +#define PACR41(x) SCM_PACRF_PACR41(x) +#define PACR42(x) SCM_PACRF_PACR42(x) +#define PACR43(x) SCM_PACRF_PACR43(x) +#define PACR44(x) SCM_PACRF_PACR44(x) +#define PACR45(x) SCM_PACRF_PACR45(x) +#define PACR46(x) SCM_PACRF_PACR46(x) +#define PACR47(x) SCM_PACRF_PACR47(x) +#define PACR48(x) SCM_PACRG_PACR48(x) +#define PACR56(x) SCM_PACRH_PACR56(x) +#define PACR57(x) SCM_PACRH_PACR57(x) +#define PACR58(x) SCM_PACRH_PACR58(x) + +/* Bit definitions and macros for SCM_CWCR */ +#define CWCR_RO (0x8000) +#define CWCR_CWR_WH (0x0100) +#define CWCR_CWE (0x0080) +#define CWRI_WINDOW (0x0060) +#define CWRI_RESET (0x0040) +#define CWRI_INT_RESET (0x0020) +#define CWRI_INT (0x0000) +#define CWCR_CWT(x) (((x)&0x001F)) + +/* Bit definitions and macros for SCM_ISR */ +#define SCMISR_CFEI (0x02) +#define SCMISR_CWIC (0x01) + +/* Bit definitions and macros for SCM_BCR */ +#define BCR_GBR (0x00000200) +#define BCR_GBW (0x00000100) +#define BCR_S7 (0x00000080) +#define BCR_S6 (0x00000040) +#define BCR_S4 (0x00000010) +#define BCR_S1 (0x00000002) + +/* Bit definitions and macros for SCM_CFIER */ +#define CFIER_ECFEI (0x01) + +/* Bit definitions and macros for SCM_CFLOC */ +#define CFLOC_LOC (0x80) + +/* Bit definitions and macros for SCM_CFATR */ +#define CFATR_WRITE (0x80) +#define CFATR_SZ32 (0x20) +#define CFATR_SZ16 (0x10) +#define CFATR_SZ08 (0x00) +#define CFATR_CACHE (0x08) +#define CFATR_MODE (0x02) +#define CFATR_TYPE (0x01) + +/********************************************************************* +* +* Random Number Generator (RNG) +* +*********************************************************************/ +/* Bit definitions and macros for RNG_RNGCR */ +#define RNGCR_CI (0x00000008) +#define RNGCR_IM (0x00000004) +#define RNGCR_HA (0x00000002) +#define RNGCR_GO (0x00000001) + +/* Bit definitions and macros for RNG_RNGSR */ +#define RNGSR_OFS(x) (((x)&0xFF)<<16) +#define RNGSR_OFL(x) (((x)&0xFF)<<8) +#define RNGSR_EI (0x00000008) +#define RNGSR_FUF (0x00000004) +#define RNGSR_LRS (0x00000002) +#define RNGSR_SV (0x00000001) + +/********************************************************************* +* FlexBus Chip Selects (FBCS) +*********************************************************************/ +/* Bit definitions and macros for FBCS_CSAR */ +#define CSAR_BA(x) (((x)&0xFFFF)<<16) + +/* Bit definitions and macros for FBCS_CSMR */ +#define CSMR_BAM(x) (((x)&0xFFFF)<<16) +#define CSMR_BAM_4G (0xFFFF0000) +#define CSMR_BAM_2G (0x7FFF0000) +#define CSMR_BAM_1G (0x3FFF0000) +#define CSMR_BAM_1024M (0x3FFF0000) +#define CSMR_BAM_512M (0x1FFF0000) +#define CSMR_BAM_256M (0x0FFF0000) +#define CSMR_BAM_128M (0x07FF0000) +#define CSMR_BAM_64M (0x03FF0000) +#define CSMR_BAM_32M (0x01FF0000) +#define CSMR_BAM_16M (0x00FF0000) +#define CSMR_BAM_8M (0x007F0000) +#define CSMR_BAM_4M (0x003F0000) +#define CSMR_BAM_2M (0x001F0000) +#define CSMR_BAM_1M (0x000F0000) +#define CSMR_BAM_1024K (0x000F0000) +#define CSMR_BAM_512K (0x00070000) +#define CSMR_BAM_256K (0x00030000) +#define CSMR_BAM_128K (0x00010000) +#define CSMR_BAM_64K (0x00000000) +#define CSMR_WP (0x00000100) +#define CSMR_V (0x00000001) + +/* Bit definitions and macros for FBCS_CSCR */ +#define CSCR_SWS(x) (((x)&0x3F)<<26) +#define CSCR_ASET(x) (((x)&0x03)<<20) +#define CSCR_SWSEN (0x00800000) +#define CSCR_ASET_4CLK (0x00300000) +#define CSCR_ASET_3CLK (0x00200000) +#define CSCR_ASET_2CLK (0x00100000) +#define CSCR_ASET_1CLK (0x00000000) +#define CSCR_RDAH(x) (((x)&0x03)<<18) +#define CSCR_RDAH_4CYC (0x000C0000) +#define CSCR_RDAH_3CYC (0x00080000) +#define CSCR_RDAH_2CYC (0x00040000) +#define CSCR_RDAH_1CYC (0x00000000) +#define CSCR_WRAH(x) (((x)&0x03)<<16) +#define CSCR_WDAH_4CYC (0x00003000) +#define CSCR_WDAH_3CYC (0x00002000) +#define CSCR_WDAH_2CYC (0x00001000) +#define CSCR_WDAH_1CYC (0x00000000) +#define CSCR_WS(x) (((x)&0x3F)<<10) +#define CSCR_SBM (0x00000200) +#define CSCR_AA (0x00000100) +#define CSCR_PS_MASK (0x000000C0) +#define CSCR_PS_32 (0x00000000) +#define CSCR_PS_16 (0x00000080) +#define CSCR_PS_8 (0x00000040) +#define CSCR_BEM (0x00000020) +#define CSCR_BSTR (0x00000010) +#define CSCR_BSTW (0x00000008) + +/********************************************************************* +* FlexCAN Module (CAN) +*********************************************************************/ +/* Bit definitions and macros for CAN_CANMCR */ +#define CANMCR_MDIS (0x80000000) +#define CANMCR_FRZ (0x40000000) +#define CANMCR_HALT (0x10000000) +#define CANMCR_NORDY (0x08000000) +#define CANMCR_SOFTRST (0x02000000) +#define CANMCR_FRZACK (0x01000000) +#define CANMCR_SUPV (0x00800000) +#define CANMCR_LPMACK (0x00100000) +#define CANMCR_MAXMB(x) (((x)&0x0F)) + +/* Bit definitions and macros for CAN_CANCTRL */ +#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) +#define CANCTRL_RJW(x) (((x)&0x03)<<22) +#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) +#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) +#define CANCTRL_BOFFMSK (0x00008000) +#define CANCTRL_ERRMSK (0x00004000) +#define CANCTRL_CLKSRC (0x00002000) +#define CANCTRL_LPB (0x00001000) +#define CANCTRL_SMP (0x00000080) +#define CANCTRL_BOFFREC (0x00000040) +#define CANCTRL_TSYNC (0x00000020) +#define CANCTRL_LBUF (0x00000010) +#define CANCTRL_LOM (0x00000008) +#define CANCTRL_PROPSEG(x) (((x)&0x07)) + +/* Bit definitions and macros for CAN_TIMER */ +#define TIMER_TIMER(x) ((x)&0xFFFF) + +/* Bit definitions and macros for CAN_RXGMASK */ +#define RXGMASK_MI(x) ((x)&0x1FFFFFFF) + +/* Bit definitions and macros for CAN_ERRCNT */ +#define ERRCNT_TXECTR(x) (((x)&0xFF)) +#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) + +/* Bit definitions and macros for CAN_ERRSTAT */ +#define ERRSTAT_BITERR1 (0x00008000) +#define ERRSTAT_BITERR0 (0x00004000) +#define ERRSTAT_ACKERR (0x00002000) +#define ERRSTAT_CRCERR (0x00001000) +#define ERRSTAT_FRMERR (0x00000800) +#define ERRSTAT_STFERR (0x00000400) +#define ERRSTAT_TXWRN (0x00000200) +#define ERRSTAT_RXWRN (0x00000100) +#define ERRSTAT_IDLE (0x00000080) +#define ERRSTAT_TXRX (0x00000040) +#define ERRSTAT_FLT_BUSOFF (0x00000020) +#define ERRSTAT_FLT_PASSIVE (0x00000010) +#define ERRSTAT_FLT_ACTIVE (0x00000000) +#define ERRSTAT_BOFFINT (0x00000004) +#define ERRSTAT_ERRINT (0x00000002) +#define ERRSTAT_WAKINT (0x00000001) + +/* Bit definitions and macros for CAN_IMASK */ +#define IMASK_BUF15M (0x00008000) +#define IMASK_BUF14M (0x00004000) +#define IMASK_BUF13M (0x00002000) +#define IMASK_BUF12M (0x00001000) +#define IMASK_BUF11M (0x00000800) +#define IMASK_BUF10M (0x00000400) +#define IMASK_BUF9M (0x00000200) +#define IMASK_BUF8M (0x00000100) +#define IMASK_BUF7M (0x00000080) +#define IMASK_BUF6M (0x00000040) +#define IMASK_BUF5M (0x00000020) +#define IMASK_BUF4M (0x00000010) +#define IMASK_BUF3M (0x00000008) +#define IMASK_BUF2M (0x00000004) +#define IMASK_BUF1M (0x00000002) +#define IMASK_BUF0M (0x00000001) + +/* Bit definitions and macros for CAN_IFLAG */ +#define IFLAG_BUF15I (0x00008000) +#define IFLAG_BUF14I (0x00004000) +#define IFLAG_BUF13I (0x00002000) +#define IFLAG_BUF12I (0x00001000) +#define IFLAG_BUF11I (0x00000800) +#define IFLAG_BUF10I (0x00000400) +#define IFLAG_BUF9I (0x00000200) +#define IFLAG_BUF8I (0x00000100) +#define IFLAG_BUF7I (0x00000080) +#define IFLAG_BUF6I (0x00000040) +#define IFLAG_BUF5I (0x00000020) +#define IFLAG_BUF4I (0x00000010) +#define IFLAG_BUF3I (0x00000008) +#define IFLAG_BUF2I (0x00000004) +#define IFLAG_BUF1I (0x00000002) +#define IFLAG_BUF0I (0x00000001) + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INTC0_EPORT INTC_IPRL_INT1 + +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_RSVD1 (29) +#define INT0_LO_I2C (30) +#define INT0_LO_QSPI (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_FEC_TXF (36) +#define INT0_HI_FEC_TXB (37) +#define INT0_HI_FEC_UN (38) +#define INT0_HI_FEC_RL (39) +#define INT0_HI_FEC_RXF (40) +#define INT0_HI_FEC_RXB (41) +#define INT0_HI_FEC_MII (42) +#define INT0_HI_FEC_LC (43) +#define INT0_HI_FEC_HBERR (44) +#define INT0_HI_FEC_GRA (45) +#define INT0_HI_FEC_EBERR (46) +#define INT0_HI_FEC_BABT (47) +#define INT0_HI_FEC_BABR (48) +/* 49 - 61 Reserved */ +#define INT0_HI_SCM (62) + +/*#define INT1_HI_ */ + +/* Bit definitions and macros for INTC_IPRH */ +#define INTC_IPRH_INT63 (0x80000000) +#define INTC_IPRH_INT62 (0x40000000) +#define INTC_IPRH_INT61 (0x20000000) +#define INTC_IPRH_INT60 (0x10000000) +#define INTC_IPRH_INT59 (0x08000000) +#define INTC_IPRH_INT58 (0x04000000) +#define INTC_IPRH_INT57 (0x02000000) +#define INTC_IPRH_INT56 (0x01000000) +#define INTC_IPRH_INT55 (0x00800000) +#define INTC_IPRH_INT54 (0x00400000) +#define INTC_IPRH_INT53 (0x00200000) +#define INTC_IPRH_INT52 (0x00100000) +#define INTC_IPRH_INT51 (0x00080000) +#define INTC_IPRH_INT50 (0x00040000) +#define INTC_IPRH_INT49 (0x00020000) +#define INTC_IPRH_INT48 (0x00010000) +#define INTC_IPRH_INT47 (0x00008000) +#define INTC_IPRH_INT46 (0x00004000) +#define INTC_IPRH_INT45 (0x00002000) +#define INTC_IPRH_INT44 (0x00001000) +#define INTC_IPRH_INT43 (0x00000800) +#define INTC_IPRH_INT42 (0x00000400) +#define INTC_IPRH_INT41 (0x00000200) +#define INTC_IPRH_INT40 (0x00000100) +#define INTC_IPRH_INT39 (0x00000080) +#define INTC_IPRH_INT38 (0x00000040) +#define INTC_IPRH_INT37 (0x00000020) +#define INTC_IPRH_INT36 (0x00000010) +#define INTC_IPRH_INT35 (0x00000008) +#define INTC_IPRH_INT34 (0x00000004) +#define INTC_IPRH_INT33 (0x00000002) +#define INTC_IPRH_INT32 (0x00000001) + +/* Bit definitions and macros for INTC_IPRL */ +#define INTC_IPRL_INT31 (0x80000000) +#define INTC_IPRL_INT30 (0x40000000) +#define INTC_IPRL_INT29 (0x20000000) +#define INTC_IPRL_INT28 (0x10000000) +#define INTC_IPRL_INT27 (0x08000000) +#define INTC_IPRL_INT26 (0x04000000) +#define INTC_IPRL_INT25 (0x02000000) +#define INTC_IPRL_INT24 (0x01000000) +#define INTC_IPRL_INT23 (0x00800000) +#define INTC_IPRL_INT22 (0x00400000) +#define INTC_IPRL_INT21 (0x00200000) +#define INTC_IPRL_INT20 (0x00100000) +#define INTC_IPRL_INT19 (0x00080000) +#define INTC_IPRL_INT18 (0x00040000) +#define INTC_IPRL_INT17 (0x00020000) +#define INTC_IPRL_INT16 (0x00010000) +#define INTC_IPRL_INT15 (0x00008000) +#define INTC_IPRL_INT14 (0x00004000) +#define INTC_IPRL_INT13 (0x00002000) +#define INTC_IPRL_INT12 (0x00001000) +#define INTC_IPRL_INT11 (0x00000800) +#define INTC_IPRL_INT10 (0x00000400) +#define INTC_IPRL_INT9 (0x00000200) +#define INTC_IPRL_INT8 (0x00000100) +#define INTC_IPRL_INT7 (0x00000080) +#define INTC_IPRL_INT6 (0x00000040) +#define INTC_IPRL_INT5 (0x00000020) +#define INTC_IPRL_INT4 (0x00000010) +#define INTC_IPRL_INT3 (0x00000008) +#define INTC_IPRL_INT2 (0x00000004) +#define INTC_IPRL_INT1 (0x00000002) +#define INTC_IPRL_INT0 (0x00000001) + +/* Bit definitions and macros for INTC_ICONFIG */ +#define INTC_ICFG_ELVLPRI7 (0x8000) +#define INTC_ICFG_ELVLPRI6 (0x4000) +#define INTC_ICFG_ELVLPRI5 (0x2000) +#define INTC_ICFG_ELVLPRI4 (0x1000) +#define INTC_ICFG_ELVLPRI3 (0x0800) +#define INTC_ICFG_ELVLPRI2 (0x0400) +#define INTC_ICFG_ELVLPRI1 (0x0200) +#define INTC_ICFG_EMASK (0x0020) + +/* Bit definitions and macros for INTC_SIMR */ +#define INTC_SIMR_SALL (0x40) +#define INTC_SIMR_SIMR(x) ((x)&0x3F) + +/* Bit definitions and macros for INTC_CIMR */ +#define INTC_CIMR_CALL (0x40) +#define INTC_CIMR_CIMR(x) ((x)&0x3F) + +/* Bit definitions and macros for INTC_CLMASK */ +#define INTC_CLMASK_CLMASK(x) ((x)&0x0F) + +/* Bit definitions and macros for INTC_SLMASK */ +#define INTC_SLMASK_SLMASK(x) ((x)&0x0F) + +/* Bit definitions and macros for INTC_ICR */ +#define INTC_ICR_IL(x) ((x)&0x07) + +/********************************************************************* +* I2C Module (I2C) +*********************************************************************/ +/* Bit definitions and macros for I2C_AR */ +#define I2C_AR_ADR(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for I2C_FDR */ +#define I2C_FDR_IC(x) ((x)&0x3F) + +/* Bit definitions and macros for I2C_CR */ +#define I2C_CR_IEN (0x80) +#define I2C_CR_IIEN (0x40) +#define I2C_CR_MSTA (0x20) +#define I2C_CR_MTX (0x10) +#define I2C_CR_TXAK (0x08) +#define I2C_CR_RSTA (0x04) + +/* Bit definitions and macros for I2C_SR */ +#define I2C_SR_ICF (0x80) +#define I2C_SR_IAAS (0x40) +#define I2C_SR_IBB (0x20) +#define I2C_SR_IAL (0x10) +#define I2C_SR_SRW (0x04) +#define I2C_SR_IIF (0x02) +#define I2C_SR_RXAK (0x01) + +/* Bit definitions and macros for I2C_ICR */ +#define I2C_ICR_BNBE (0x08) +#define I2C_ICR_TE (0x04) +#define I2C_ICR_RE (0x02) +#define I2C_ICR_IE (0x01) + +/********************************************************************* +* Queued Serial Peripheral Interface (QSPI) +*********************************************************************/ +/* Bit definitions and macros for QSPI_QMR */ +#define QSPI_QMR_MSTR (0x8000) +#define QSPI_QMR_DOHIE (0x4000) +#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define QSPI_QMR_CPOL (0x0200) +#define QSPI_QMR_CPHA (0x0100) +#define QSPI_QMR_BAUD(x) ((x)&0x00FF) + +/* Bit definitions and macros for QSPI_QDLYR */ +#define QSPI_QDLYR_SPE (0x8000) +#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define QSPI_QDLYR_DTL(x) ((x)&0x00FF) + +/* Bit definitions and macros for QSPI_QWR */ +#define QSPI_QWR_NEWQP(x) ((x)&0x000F) +#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define QSPI_QWR_CSIV (0x1000) +#define QSPI_QWR_WRTO (0x2000) +#define QSPI_QWR_WREN (0x4000) +#define QSPI_QWR_HALT (0x8000) + +/* Bit definitions and macros for QSPI_QIR */ +#define QSPI_QIR_WCEFB (0x8000) +#define QSPI_QIR_ABRTB (0x4000) +#define QSPI_QIR_ABRTL (0x1000) +#define QSPI_QIR_WCEFE (0x0800) +#define QSPI_QIR_ABRTE (0x0400) +#define QSPI_QIR_SPIFE (0x0100) +#define QSPI_QIR_WCEF (0x0008) +#define QSPI_QIR_ABRT (0x0004) +#define QSPI_QIR_SPIF (0x0001) + +/* Bit definitions and macros for QSPI_QAR */ +#define QSPI_QAR_ADDR(x) ((x)&0x003F) +#define QSPI_QAR_TRANS (0x0000) +#define QSPI_QAR_RECV (0x0010) +#define QSPI_QAR_CMD (0x0020) + +/* Bit definitions and macros for QSPI_QDR */ +#define QSPI_QDR_CONT (0x8000) +#define QSPI_QDR_BITSE (0x4000) +#define QSPI_QDR_DT (0x2000) +#define QSPI_QDR_DSCK (0x1000) +#define QSPI_QDR_QSPI_CS3 (0x0800) +#define QSPI_QDR_QSPI_CS2 (0x0400) +#define QSPI_QDR_QSPI_CS1 (0x0200) +#define QSPI_QDR_QSPI_CS0 (0x0100) + +/********************************************************************* +* Pulse Width Modulation (PWM) +*********************************************************************/ +/* Bit definitions and macros for PWM_E */ +#define PWM_EN_PWME7 (0x80) +#define PWM_EN_PWME5 (0x20) +#define PWM_EN_PWME3 (0x08) +#define PWM_EN_PWME1 (0x02) + +/* Bit definitions and macros for PWM_POL */ +#define PWM_POL_PPOL7 (0x80) +#define PWM_POL_PPOL5 (0x20) +#define PWM_POL_PPOL3 (0x08) +#define PWM_POL_PPOL1 (0x02) + +/* Bit definitions and macros for PWM_CLK */ +#define PWM_CLK_PCLK7 (0x80) +#define PWM_CLK_PCLK5 (0x20) +#define PWM_CLK_PCLK3 (0x08) +#define PWM_CLK_PCLK1 (0x02) + +/* Bit definitions and macros for PWM_PRCLK */ +#define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4) +#define PWM_PRCLK_PCKA(x) ((x)&0x07) + +/* Bit definitions and macros for PWM_CAE */ +#define PWM_CAE_CAE7 (0x80) +#define PWM_CAE_CAE5 (0x20) +#define PWM_CAE_CAE3 (0x08) +#define PWM_CAE_CAE1 (0x02) + +/* Bit definitions and macros for PWM_CTL */ +#define PWM_CTL_CON67 (0x80) +#define PWM_CTL_CON45 (0x40) +#define PWM_CTL_CON23 (0x20) +#define PWM_CTL_CON01 (0x10) +#define PWM_CTL_PSWAR (0x08) +#define PWM_CTL_PFRZ (0x04) + +/* Bit definitions and macros for PWM_SDN */ +#define PWM_SDN_IF (0x80) +#define PWM_SDN_IE (0x40) +#define PWM_SDN_RESTART (0x20) +#define PWM_SDN_LVL (0x10) +#define PWM_SDN_PWM7IN (0x04) +#define PWM_SDN_PWM7IL (0x02) +#define PWM_SDN_SDNEN (0x01) + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ +/* Bit definitions and macros for WTM_WCR */ +#define WTM_WCR_WAIT (0x0008) +#define WTM_WCR_DOZE (0x0004) +#define WTM_WCR_HALTED (0x0002) +#define WTM_WCR_EN (0x0001) + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ +/* Bit definitions and macros for CCM_CCR */ +#define CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) +#define CCM_CCR_LIMP (0x0041) +#define CCM_CCR_LOAD (0x0021) +#define CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) +#define CCM_CCR_OSC_MODE (0x0005) +#define CCM_CCR_PLL_MODE (0x0003) +#define CCM_CCR_RESERVED (0x0001) + +/* Bit definitions and macros for CCM_RCON */ +#define CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) +#define CCM_RCON_LIMP (0x0041) +#define CCM_RCON_LOAD (0x0021) +#define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) +#define CCM_RCON_OSC_MODE (0x0005) +#define CCM_RCON_PLL_MODE (0x0003) +#define CCM_RCON_RESERVED (0x0001) + +/* Bit definitions and macros for CCM_CIR */ +#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) +#define CCM_CIR_PRN(x) ((x)&0x003F) + +/* Bit definitions and macros for CCM_MISCCR */ +#define CCM_MISCCR_PLL_LOCK (0x2000) +#define CCM_MISCCR_LIMP (0x1000) +#define CCM_MISCCR_LCD_CHEN (0x0100) +#define CCM_MISCCR_SSI_PUE (0x0080) +#define CCM_MISCCR_SSI_PUS (0x0040) +#define CCM_MISCCR_TIM_DMA (0x0020) +#define CCM_MISCCR_SSI_SRC (0x0010) +#define CCM_MISCCR_USBDIV (0x0002) +#define CCM_MISCCR_USBSRC (0x0001) + +/* Bit definitions and macros for CCM_CDR */ +#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) +#define CCM_CDR_SSIDIV(x) ((x)&0x000F) + +/* Bit definitions and macros for CCM_UHCSR */ +#define CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) +#define CCM_UHCSR_WKUP (0x0004) +#define CCM_UHCSR_UHMIE (0x0002) +#define CCM_UHCSR_XPDE (0x0001) + +/* Bit definitions and macros for CCM_UOCSR */ +#define CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) +#define CCM_UOCSR_DPPD (0x2000) +#define CCM_UOCSR_DMPD (0x1000) +#define CCM_UOCSR_DRV_VBUS (0x0800) +#define CCM_UOCSR_CRG_VBUS (0x0400) +#define CCM_UOCSR_DCR_VBUS (0x0200) +#define CCM_UOCSR_DPPU (0x0100) +#define CCM_UOCSR_AVLD (0x0080) +#define CCM_UOCSR_BVLD (0x0040) +#define CCM_UOCSR_VVLD (0x0020) +#define CCM_UOCSR_SEND (0x0010) +#define CCM_UOCSR_PWRFLT (0x0008) +#define CCM_UOCSR_WKUP (0x0004) +#define CCM_UOCSR_UOMIE (0x0002) +#define CCM_UOCSR_XPDE (0x0001) + +/* not done yet */ +/********************************************************************* +* General Purpose I/O (GPIO) +*********************************************************************/ +/* Bit definitions and macros for GPIO_PODR_FECH_L */ +#define GPIO_PODR_FECH_L7 (0x80) +#define GPIO_PODR_FECH_L6 (0x40) +#define GPIO_PODR_FECH_L5 (0x20) +#define GPIO_PODR_FECH_L4 (0x10) +#define GPIO_PODR_FECH_L3 (0x08) +#define GPIO_PODR_FECH_L2 (0x04) +#define GPIO_PODR_FECH_L1 (0x02) +#define GPIO_PODR_FECH_L0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_SSI */ +#define GPIO_PODR_SSI_4 (0x10) +#define GPIO_PODR_SSI_3 (0x08) +#define GPIO_PODR_SSI_2 (0x04) +#define GPIO_PODR_SSI_1 (0x02) +#define GPIO_PODR_SSI_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_BUSCTL */ +#define GPIO_PODR_BUSCTL_3 (0x08) +#define GPIO_PODR_BUSCTL_2 (0x04) +#define GPIO_PODR_BUSCTL_1 (0x02) +#define GPIO_PODR_BUSCTL_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_BE */ +#define GPIO_PODR_BE_3 (0x08) +#define GPIO_PODR_BE_2 (0x04) +#define GPIO_PODR_BE_1 (0x02) +#define GPIO_PODR_BE_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_CS */ +#define GPIO_PODR_CS_5 (0x20) +#define GPIO_PODR_CS_4 (0x10) +#define GPIO_PODR_CS_3 (0x08) +#define GPIO_PODR_CS_2 (0x04) +#define GPIO_PODR_CS_1 (0x02) + +/* Bit definitions and macros for GPIO_PODR_PWM */ +#define GPIO_PODR_PWM_5 (0x20) +#define GPIO_PODR_PWM_4 (0x10) +#define GPIO_PODR_PWM_3 (0x08) +#define GPIO_PODR_PWM_2 (0x04) + +/* Bit definitions and macros for GPIO_PODR_FECI2C */ +#define GPIO_PODR_FECI2C_3 (0x08) +#define GPIO_PODR_FECI2C_2 (0x04) +#define GPIO_PODR_FECI2C_1 (0x02) +#define GPIO_PODR_FECI2C_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_UART */ +#define GPIO_PODR_UART_7 (0x80) +#define GPIO_PODR_UART_6 (0x40) +#define GPIO_PODR_UART_5 (0x20) +#define GPIO_PODR_UART_4 (0x10) +#define GPIO_PODR_UART_3 (0x08) +#define GPIO_PODR_UART_2 (0x04) +#define GPIO_PODR_UART_1 (0x02) +#define GPIO_PODR_UART_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_QSPI */ +#define GPIO_PODR_QSPI_5 (0x20) +#define GPIO_PODR_QSPI_4 (0x10) +#define GPIO_PODR_QSPI_3 (0x08) +#define GPIO_PODR_QSPI_2 (0x04) +#define GPIO_PODR_QSPI_1 (0x02) +#define GPIO_PODR_QSPI_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_TIMER */ +#define GPIO_PODR_TIMER_3 (0x08) +#define GPIO_PODR_TIMER_2 (0x04) +#define GPIO_PODR_TIMER_1 (0x02) +#define GPIO_PODR_TIMER_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDDATAH */ +#define GPIO_PODR_LCDDATAH_1 (0x02) +#define GPIO_PODR_LCDDATAH_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDDATAM */ +#define GPIO_PODR_LCDDATAM_7 (0x80) +#define GPIO_PODR_LCDDATAM_6 (0x40) +#define GPIO_PODR_LCDDATAM_5 (0x20) +#define GPIO_PODR_LCDDATAM_4 (0x10) +#define GPIO_PODR_LCDDATAM_3 (0x08) +#define GPIO_PODR_LCDDATAM_2 (0x04) +#define GPIO_PODR_LCDDATAM_1 (0x02) +#define GPIO_PODR_LCDDATAM_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDDATAL */ +#define GPIO_PODR_LCDDATAL_7 (0x80) +#define GPIO_PODR_LCDDATAL_6 (0x40) +#define GPIO_PODR_LCDDATAL_5 (0x20) +#define GPIO_PODR_LCDDATAL_4 (0x10) +#define GPIO_PODR_LCDDATAL_3 (0x08) +#define GPIO_PODR_LCDDATAL_2 (0x04) +#define GPIO_PODR_LCDDATAL_1 (0x02) +#define GPIO_PODR_LCDDATAL_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDCTLH */ +#define GPIO_PODR_LCDCTLH_0 (0x01) + +/* Bit definitions and macros for GPIO_PODR_LCDCTLL */ +#define GPIO_PODR_LCDCTLL_7 (0x80) +#define GPIO_PODR_LCDCTLL_6 (0x40) +#define GPIO_PODR_LCDCTLL_5 (0x20) +#define GPIO_PODR_LCDCTLL_4 (0x10) +#define GPIO_PODR_LCDCTLL_3 (0x08) +#define GPIO_PODR_LCDCTLL_2 (0x04) +#define GPIO_PODR_LCDCTLL_1 (0x02) +#define GPIO_PODR_LCDCTLL_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_FECH */ +#define GPIO_PDDR_FECH_L7 (0x80) +#define GPIO_PDDR_FECH_L6 (0x40) +#define GPIO_PDDR_FECH_L5 (0x20) +#define GPIO_PDDR_FECH_L4 (0x10) +#define GPIO_PDDR_FECH_L3 (0x08) +#define GPIO_PDDR_FECH_L2 (0x04) +#define GPIO_PDDR_FECH_L1 (0x02) +#define GPIO_PDDR_FECH_L0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_SSI */ +#define GPIO_PDDR_SSI_4 (0x10) +#define GPIO_PDDR_SSI_3 (0x08) +#define GPIO_PDDR_SSI_2 (0x04) +#define GPIO_PDDR_SSI_1 (0x02) +#define GPIO_PDDR_SSI_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_BUSCTL */ +#define GPIO_PDDR_BUSCTL_3 (0x08) +#define GPIO_PDDR_BUSCTL_2 (0x04) +#define GPIO_PDDR_BUSCTL_1 (0x02) +#define GPIO_PDDR_BUSCTL_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_BE */ +#define GPIO_PDDR_BE_3 (0x08) +#define GPIO_PDDR_BE_2 (0x04) +#define GPIO_PDDR_BE_1 (0x02) +#define GPIO_PDDR_BE_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_CS */ +#define GPIO_PDDR_CS_1 (0x02) +#define GPIO_PDDR_CS_2 (0x04) +#define GPIO_PDDR_CS_3 (0x08) +#define GPIO_PDDR_CS_4 (0x10) +#define GPIO_PDDR_CS_5 (0x20) + +/* Bit definitions and macros for GPIO_PDDR_PWM */ +#define GPIO_PDDR_PWM_2 (0x04) +#define GPIO_PDDR_PWM_3 (0x08) +#define GPIO_PDDR_PWM_4 (0x10) +#define GPIO_PDDR_PWM_5 (0x20) + +/* Bit definitions and macros for GPIO_PDDR_FECI2C */ +#define GPIO_PDDR_FECI2C_0 (0x01) +#define GPIO_PDDR_FECI2C_1 (0x02) +#define GPIO_PDDR_FECI2C_2 (0x04) +#define GPIO_PDDR_FECI2C_3 (0x08) + +/* Bit definitions and macros for GPIO_PDDR_UART */ +#define GPIO_PDDR_UART_0 (0x01) +#define GPIO_PDDR_UART_1 (0x02) +#define GPIO_PDDR_UART_2 (0x04) +#define GPIO_PDDR_UART_3 (0x08) +#define GPIO_PDDR_UART_4 (0x10) +#define GPIO_PDDR_UART_5 (0x20) +#define GPIO_PDDR_UART_6 (0x40) +#define GPIO_PDDR_UART_7 (0x80) + +/* Bit definitions and macros for GPIO_PDDR_QSPI */ +#define GPIO_PDDR_QSPI_0 (0x01) +#define GPIO_PDDR_QSPI_1 (0x02) +#define GPIO_PDDR_QSPI_2 (0x04) +#define GPIO_PDDR_QSPI_3 (0x08) +#define GPIO_PDDR_QSPI_4 (0x10) +#define GPIO_PDDR_QSPI_5 (0x20) + +/* Bit definitions and macros for GPIO_PDDR_TIMER */ +#define GPIO_PDDR_TIMER_0 (0x01) +#define GPIO_PDDR_TIMER_1 (0x02) +#define GPIO_PDDR_TIMER_2 (0x04) +#define GPIO_PDDR_TIMER_3 (0x08) + +/* Bit definitions and macros for GPIO_PDDR_LCDDATAH */ +#define GPIO_PDDR_LCDDATAH_0 (0x01) +#define GPIO_PDDR_LCDDATAH_1 (0x02) + +/* Bit definitions and macros for GPIO_PDDR_LCDDATAM */ +#define GPIO_PDDR_LCDDATAM_0 (0x01) +#define GPIO_PDDR_LCDDATAM_1 (0x02) +#define GPIO_PDDR_LCDDATAM_2 (0x04) +#define GPIO_PDDR_LCDDATAM_3 (0x08) +#define GPIO_PDDR_LCDDATAM_4 (0x10) +#define GPIO_PDDR_LCDDATAM_5 (0x20) +#define GPIO_PDDR_LCDDATAM_6 (0x40) +#define GPIO_PDDR_LCDDATAM_7 (0x80) + +/* Bit definitions and macros for GPIO_PDDR_LCDDATAL */ +#define GPIO_PDDR_LCDDATAL_0 (0x01) +#define GPIO_PDDR_LCDDATAL_1 (0x02) +#define GPIO_PDDR_LCDDATAL_2 (0x04) +#define GPIO_PDDR_LCDDATAL_3 (0x08) +#define GPIO_PDDR_LCDDATAL_4 (0x10) +#define GPIO_PDDR_LCDDATAL_5 (0x20) +#define GPIO_PDDR_LCDDATAL_6 (0x40) +#define GPIO_PDDR_LCDDATAL_7 (0x80) + +/* Bit definitions and macros for GPIO_PDDR_LCDCTLH */ +#define GPIO_PDDR_LCDCTLH_0 (0x01) + +/* Bit definitions and macros for GPIO_PDDR_LCDCTLL */ +#define GPIO_PDDR_LCDCTLL_0 (0x01) +#define GPIO_PDDR_LCDCTLL_1 (0x02) +#define GPIO_PDDR_LCDCTLL_2 (0x04) +#define GPIO_PDDR_LCDCTLL_3 (0x08) +#define GPIO_PDDR_LCDCTLL_4 (0x10) +#define GPIO_PDDR_LCDCTLL_5 (0x20) +#define GPIO_PDDR_LCDCTLL_6 (0x40) +#define GPIO_PDDR_LCDCTLL_7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_FECH */ +#define GPIO_PPDSDR_FECH_L0 (0x01) +#define GPIO_PPDSDR_FECH_L1 (0x02) +#define GPIO_PPDSDR_FECH_L2 (0x04) +#define GPIO_PPDSDR_FECH_L3 (0x08) +#define GPIO_PPDSDR_FECH_L4 (0x10) +#define GPIO_PPDSDR_FECH_L5 (0x20) +#define GPIO_PPDSDR_FECH_L6 (0x40) +#define GPIO_PPDSDR_FECH_L7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_SSI */ +#define GPIO_PPDSDR_SSI_0 (0x01) +#define GPIO_PPDSDR_SSI_1 (0x02) +#define GPIO_PPDSDR_SSI_2 (0x04) +#define GPIO_PPDSDR_SSI_3 (0x08) +#define GPIO_PPDSDR_SSI_4 (0x10) + +/* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */ +#define GPIO_PPDSDR_BUSCTL_0 (0x01) +#define GPIO_PPDSDR_BUSCTL_1 (0x02) +#define GPIO_PPDSDR_BUSCTL_2 (0x04) +#define GPIO_PPDSDR_BUSCTL_3 (0x08) + +/* Bit definitions and macros for GPIO_PPDSDR_BE */ +#define GPIO_PPDSDR_BE_0 (0x01) +#define GPIO_PPDSDR_BE_1 (0x02) +#define GPIO_PPDSDR_BE_2 (0x04) +#define GPIO_PPDSDR_BE_3 (0x08) + +/* Bit definitions and macros for GPIO_PPDSDR_CS */ +#define GPIO_PPDSDR_CS_1 (0x02) +#define GPIO_PPDSDR_CS_2 (0x04) +#define GPIO_PPDSDR_CS_3 (0x08) +#define GPIO_PPDSDR_CS_4 (0x10) +#define GPIO_PPDSDR_CS_5 (0x20) + +/* Bit definitions and macros for GPIO_PPDSDR_PWM */ +#define GPIO_PPDSDR_PWM_2 (0x04) +#define GPIO_PPDSDR_PWM_3 (0x08) +#define GPIO_PPDSDR_PWM_4 (0x10) +#define GPIO_PPDSDR_PWM_5 (0x20) + +/* Bit definitions and macros for GPIO_PPDSDR_FECI2C */ +#define GPIO_PPDSDR_FECI2C_0 (0x01) +#define GPIO_PPDSDR_FECI2C_1 (0x02) +#define GPIO_PPDSDR_FECI2C_2 (0x04) +#define GPIO_PPDSDR_FECI2C_3 (0x08) + +/* Bit definitions and macros for GPIO_PPDSDR_UART */ +#define GPIO_PPDSDR_UART_0 (0x01) +#define GPIO_PPDSDR_UART_1 (0x02) +#define GPIO_PPDSDR_UART_2 (0x04) +#define GPIO_PPDSDR_UART_3 (0x08) +#define GPIO_PPDSDR_UART_4 (0x10) +#define GPIO_PPDSDR_UART_5 (0x20) +#define GPIO_PPDSDR_UART_6 (0x40) +#define GPIO_PPDSDR_UART_7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_QSPI */ +#define GPIO_PPDSDR_QSPI_0 (0x01) +#define GPIO_PPDSDR_QSPI_1 (0x02) +#define GPIO_PPDSDR_QSPI_2 (0x04) +#define GPIO_PPDSDR_QSPI_3 (0x08) +#define GPIO_PPDSDR_QSPI_4 (0x10) +#define GPIO_PPDSDR_QSPI_5 (0x20) + +/* Bit definitions and macros for GPIO_PPDSDR_TIMER */ +#define GPIO_PPDSDR_TIMER_0 (0x01) +#define GPIO_PPDSDR_TIMER_1 (0x02) +#define GPIO_PPDSDR_TIMER_2 (0x04) +#define GPIO_PPDSDR_TIMER_3 (0x08) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */ +#define GPIO_PPDSDR_LCDDATAH_0 (0x01) +#define GPIO_PPDSDR_LCDDATAH_1 (0x02) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */ +#define GPIO_PPDSDR_LCDDATAM_0 (0x01) +#define GPIO_PPDSDR_LCDDATAM_1 (0x02) +#define GPIO_PPDSDR_LCDDATAM_2 (0x04) +#define GPIO_PPDSDR_LCDDATAM_3 (0x08) +#define GPIO_PPDSDR_LCDDATAM_4 (0x10) +#define GPIO_PPDSDR_LCDDATAM_5 (0x20) +#define GPIO_PPDSDR_LCDDATAM_6 (0x40) +#define GPIO_PPDSDR_LCDDATAM_7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */ +#define GPIO_PPDSDR_LCDDATAL_0 (0x01) +#define GPIO_PPDSDR_LCDDATAL_1 (0x02) +#define GPIO_PPDSDR_LCDDATAL_2 (0x04) +#define GPIO_PPDSDR_LCDDATAL_3 (0x08) +#define GPIO_PPDSDR_LCDDATAL_4 (0x10) +#define GPIO_PPDSDR_LCDDATAL_5 (0x20) +#define GPIO_PPDSDR_LCDDATAL_6 (0x40) +#define GPIO_PPDSDR_LCDDATAL_7 (0x80) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */ +#define GPIO_PPDSDR_LCDCTLH_0 (0x01) + +/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */ +#define GPIO_PPDSDR_LCDCTLL_0 (0x01) +#define GPIO_PPDSDR_LCDCTLL_1 (0x02) +#define GPIO_PPDSDR_LCDCTLL_2 (0x04) +#define GPIO_PPDSDR_LCDCTLL_3 (0x08) +#define GPIO_PPDSDR_LCDCTLL_4 (0x10) +#define GPIO_PPDSDR_LCDCTLL_5 (0x20) +#define GPIO_PPDSDR_LCDCTLL_6 (0x40) +#define GPIO_PPDSDR_LCDCTLL_7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_FECH */ +#define GPIO_PCLRR_FECH_L0 (0x01) +#define GPIO_PCLRR_FECH_L1 (0x02) +#define GPIO_PCLRR_FECH_L2 (0x04) +#define GPIO_PCLRR_FECH_L3 (0x08) +#define GPIO_PCLRR_FECH_L4 (0x10) +#define GPIO_PCLRR_FECH_L5 (0x20) +#define GPIO_PCLRR_FECH_L6 (0x40) +#define GPIO_PCLRR_FECH_L7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_SSI */ +#define GPIO_PCLRR_SSI_0 (0x01) +#define GPIO_PCLRR_SSI_1 (0x02) +#define GPIO_PCLRR_SSI_2 (0x04) +#define GPIO_PCLRR_SSI_3 (0x08) +#define GPIO_PCLRR_SSI_4 (0x10) + +/* Bit definitions and macros for GPIO_PCLRR_BUSCTL */ +#define GPIO_PCLRR_BUSCTL_L0 (0x01) +#define GPIO_PCLRR_BUSCTL_L1 (0x02) +#define GPIO_PCLRR_BUSCTL_L2 (0x04) +#define GPIO_PCLRR_BUSCTL_L3 (0x08) + +/* Bit definitions and macros for GPIO_PCLRR_BE */ +#define GPIO_PCLRR_BE_0 (0x01) +#define GPIO_PCLRR_BE_1 (0x02) +#define GPIO_PCLRR_BE_2 (0x04) +#define GPIO_PCLRR_BE_3 (0x08) + +/* Bit definitions and macros for GPIO_PCLRR_CS */ +#define GPIO_PCLRR_CS_1 (0x02) +#define GPIO_PCLRR_CS_2 (0x04) +#define GPIO_PCLRR_CS_3 (0x08) +#define GPIO_PCLRR_CS_4 (0x10) +#define GPIO_PCLRR_CS_5 (0x20) + +/* Bit definitions and macros for GPIO_PCLRR_PWM */ +#define GPIO_PCLRR_PWM_2 (0x04) +#define GPIO_PCLRR_PWM_3 (0x08) +#define GPIO_PCLRR_PWM_4 (0x10) +#define GPIO_PCLRR_PWM_5 (0x20) + +/* Bit definitions and macros for GPIO_PCLRR_FECI2C */ +#define GPIO_PCLRR_FECI2C_0 (0x01) +#define GPIO_PCLRR_FECI2C_1 (0x02) +#define GPIO_PCLRR_FECI2C_2 (0x04) +#define GPIO_PCLRR_FECI2C_3 (0x08) + +/* Bit definitions and macros for GPIO_PCLRR_UART */ +#define GPIO_PCLRR_UART0 (0x01) +#define GPIO_PCLRR_UART1 (0x02) +#define GPIO_PCLRR_UART2 (0x04) +#define GPIO_PCLRR_UART3 (0x08) +#define GPIO_PCLRR_UART4 (0x10) +#define GPIO_PCLRR_UART5 (0x20) +#define GPIO_PCLRR_UART6 (0x40) +#define GPIO_PCLRR_UART7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_QSPI */ +#define GPIO_PCLRR_QSPI0 (0x01) +#define GPIO_PCLRR_QSPI1 (0x02) +#define GPIO_PCLRR_QSPI2 (0x04) +#define GPIO_PCLRR_QSPI3 (0x08) +#define GPIO_PCLRR_QSPI4 (0x10) +#define GPIO_PCLRR_QSPI5 (0x20) + +/* Bit definitions and macros for GPIO_PCLRR_TIMER */ +#define GPIO_PCLRR_TIMER0 (0x01) +#define GPIO_PCLRR_TIMER1 (0x02) +#define GPIO_PCLRR_TIMER2 (0x04) +#define GPIO_PCLRR_TIMER3 (0x08) + +/* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */ +#define GPIO_PCLRR_LCDDATAH0 (0x01) +#define GPIO_PCLRR_LCDDATAH1 (0x02) + +/* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */ +#define GPIO_PCLRR_LCDDATAM0 (0x01) +#define GPIO_PCLRR_LCDDATAM1 (0x02) +#define GPIO_PCLRR_LCDDATAM2 (0x04) +#define GPIO_PCLRR_LCDDATAM3 (0x08) +#define GPIO_PCLRR_LCDDATAM4 (0x10) +#define GPIO_PCLRR_LCDDATAM5 (0x20) +#define GPIO_PCLRR_LCDDATAM6 (0x40) +#define GPIO_PCLRR_LCDDATAM7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */ +#define GPIO_PCLRR_LCDDATAL0 (0x01) +#define GPIO_PCLRR_LCDDATAL1 (0x02) +#define GPIO_PCLRR_LCDDATAL2 (0x04) +#define GPIO_PCLRR_LCDDATAL3 (0x08) +#define GPIO_PCLRR_LCDDATAL4 (0x10) +#define GPIO_PCLRR_LCDDATAL5 (0x20) +#define GPIO_PCLRR_LCDDATAL6 (0x40) +#define GPIO_PCLRR_LCDDATAL7 (0x80) + +/* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */ +#define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) + +/* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */ +#define GPIO_PCLRR_LCDCTLL0 (0x01) +#define GPIO_PCLRR_LCDCTLL1 (0x02) +#define GPIO_PCLRR_LCDCTLL2 (0x04) +#define GPIO_PCLRR_LCDCTLL3 (0x08) +#define GPIO_PCLRR_LCDCTLL4 (0x10) +#define GPIO_PCLRR_LCDCTLL5 (0x20) +#define GPIO_PCLRR_LCDCTLL6 (0x40) +#define GPIO_PCLRR_LCDCTLL7 (0x80) + +/* Bit definitions and macros for GPIO_PAR_FEC */ +#define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0) +#define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2) +#define GPIO_PAR_FEC_7W_GPIO (0x00) +#define GPIO_PAR_FEC_7W_URTS1 (0x04) +#define GPIO_PAR_FEC_7W_FEC (0x0C) +#define GPIO_PAR_FEC_MII_GPIO (0x00) +#define GPIO_PAR_FEC_MII_UART (0x01) +#define GPIO_PAR_FEC_MII_FEC (0x03) + +/* Bit definitions and macros for GPIO_PAR_PWM */ +#define GPIO_PAR_PWM1(x) (((x)&0x03)<<0) +#define GPIO_PAR_PWM3(x) (((x)&0x03)<<2) +#define GPIO_PAR_PWM5 (0x10) +#define GPIO_PAR_PWM7 (0x20) + +/* Bit definitions and macros for GPIO_PAR_BUSCTL */ +#define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<3) +#define GPIO_PAR_BUSCTL_RWB (0x20) +#define GPIO_PAR_BUSCTL_TA (0x40) +#define GPIO_PAR_BUSCTL_OE (0x80) +#define GPIO_PAR_BUSCTL_OE_GPIO (0x00) +#define GPIO_PAR_BUSCTL_OE_OE (0x80) +#define GPIO_PAR_BUSCTL_TA_GPIO (0x00) +#define GPIO_PAR_BUSCTL_TA_TA (0x40) +#define GPIO_PAR_BUSCTL_RWB_GPIO (0x00) +#define GPIO_PAR_BUSCTL_RWB_RWB (0x20) +#define GPIO_PAR_BUSCTL_TS_GPIO (0x00) +#define GPIO_PAR_BUSCTL_TS_DACK0 (0x10) +#define GPIO_PAR_BUSCTL_TS_TS (0x18) + +/* Bit definitions and macros for GPIO_PAR_FECI2C */ +#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x03)<<0) +#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) +#define GPIO_PAR_FECI2C_MDIO(x) (((x)&0x03)<<4) +#define GPIO_PAR_FECI2C_MDC(x) (((x)&0x03)<<6) +#define GPIO_PAR_FECI2C_MDC_GPIO (0x00) +#define GPIO_PAR_FECI2C_MDC_UTXD2 (0x40) +#define GPIO_PAR_FECI2C_MDC_SCL (0x80) +#define GPIO_PAR_FECI2C_MDC_EMDC (0xC0) +#define GPIO_PAR_FECI2C_MDIO_GPIO (0x00) +#define GPIO_PAR_FECI2C_MDIO_URXD2 (0x10) +#define GPIO_PAR_FECI2C_MDIO_SDA (0x20) +#define GPIO_PAR_FECI2C_MDIO_EMDIO (0x30) +#define GPIO_PAR_FECI2C_SCL_GPIO (0x00) +#define GPIO_PAR_FECI2C_SCL_UTXD2 (0x04) +#define GPIO_PAR_FECI2C_SCL_SCL (0x0C) +#define GPIO_PAR_FECI2C_SDA_GPIO (0x00) +#define GPIO_PAR_FECI2C_SDA_URXD2 (0x02) +#define GPIO_PAR_FECI2C_SDA_SDA (0x03) + +/* Bit definitions and macros for GPIO_PAR_BE */ +#define GPIO_PAR_BE0 (0x01) +#define GPIO_PAR_BE1 (0x02) +#define GPIO_PAR_BE2 (0x04) +#define GPIO_PAR_BE3 (0x08) + +/* Bit definitions and macros for GPIO_PAR_CS */ +#define GPIO_PAR_CS1 (0x02) +#define GPIO_PAR_CS2 (0x04) +#define GPIO_PAR_CS3 (0x08) +#define GPIO_PAR_CS4 (0x10) +#define GPIO_PAR_CS5 (0x20) +#define GPIO_PAR_CS1_GPIO (0x00) +#define GPIO_PAR_CS1_SDCS1 (0x01) +#define GPIO_PAR_CS1_CS1 (0x03) + +/* Bit definitions and macros for GPIO_PAR_SSI */ +#define GPIO_PAR_SSI_MCLK (0x0080) +#define GPIO_PAR_SSI_TXD(x) (((x)&0x0003)<<8) +#define GPIO_PAR_SSI_RXD(x) (((x)&0x0003)<<10) +#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<12) +#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for GPIO_PAR_UART */ +#define GPIO_PAR_UART_TXD0 (0x0001) +#define GPIO_PAR_UART_RXD0 (0x0002) +#define GPIO_PAR_UART_RTS0 (0x0004) +#define GPIO_PAR_UART_CTS0 (0x0008) +#define GPIO_PAR_UART_TXD1(x) (((x)&0x0003)<<4) +#define GPIO_PAR_UART_RXD1(x) (((x)&0x0003)<<6) +#define GPIO_PAR_UART_RTS1(x) (((x)&0x0003)<<8) +#define GPIO_PAR_UART_CTS1(x) (((x)&0x0003)<<10) +#define GPIO_PAR_UART_CTS1_GPIO (0x0000) +#define GPIO_PAR_UART_CTS1_SSI_BCLK (0x0800) +#define GPIO_PAR_UART_CTS1_ULPI_D7 (0x0400) +#define GPIO_PAR_UART_CTS1_UCTS1 (0x0C00) +#define GPIO_PAR_UART_RTS1_GPIO (0x0000) +#define GPIO_PAR_UART_RTS1_SSI_FS (0x0200) +#define GPIO_PAR_UART_RTS1_ULPI_D6 (0x0100) +#define GPIO_PAR_UART_RTS1_URTS1 (0x0300) +#define GPIO_PAR_UART_RXD1_GPIO (0x0000) +#define GPIO_PAR_UART_RXD1_SSI_RXD (0x0080) +#define GPIO_PAR_UART_RXD1_ULPI_D5 (0x0040) +#define GPIO_PAR_UART_RXD1_URXD1 (0x00C0) +#define GPIO_PAR_UART_TXD1_GPIO (0x0000) +#define GPIO_PAR_UART_TXD1_SSI_TXD (0x0020) +#define GPIO_PAR_UART_TXD1_ULPI_D4 (0x0010) +#define GPIO_PAR_UART_TXD1_UTXD1 (0x0030) + +/* Bit definitions and macros for GPIO_PAR_QSPI */ +#define GPIO_PAR_QSPI_SCK(x) (((x)&0x0003)<<4) +#define GPIO_PAR_QSPI_DOUT(x) (((x)&0x0003)<<6) +#define GPIO_PAR_QSPI_DIN(x) (((x)&0x0003)<<8) +#define GPIO_PAR_QSPI_PCS0(x) (((x)&0x0003)<<10) +#define GPIO_PAR_QSPI_PCS1(x) (((x)&0x0003)<<12) +#define GPIO_PAR_QSPI_PCS2(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for GPIO_PAR_TIMER */ +#define GPIO_PAR_TIN0(x) (((x)&0x03)<<0) +#define GPIO_PAR_TIN1(x) (((x)&0x03)<<2) +#define GPIO_PAR_TIN2(x) (((x)&0x03)<<4) +#define GPIO_PAR_TIN3(x) (((x)&0x03)<<6) +#define GPIO_PAR_TIN3_GPIO (0x00) +#define GPIO_PAR_TIN3_TOUT3 (0x80) +#define GPIO_PAR_TIN3_URXD2 (0x40) +#define GPIO_PAR_TIN3_TIN3 (0xC0) +#define GPIO_PAR_TIN2_GPIO (0x00) +#define GPIO_PAR_TIN2_TOUT2 (0x20) +#define GPIO_PAR_TIN2_UTXD2 (0x10) +#define GPIO_PAR_TIN2_TIN2 (0x30) +#define GPIO_PAR_TIN1_GPIO (0x00) +#define GPIO_PAR_TIN1_TOUT1 (0x08) +#define GPIO_PAR_TIN1_DACK1 (0x04) +#define GPIO_PAR_TIN1_TIN1 (0x0C) +#define GPIO_PAR_TIN0_GPIO (0x00) +#define GPIO_PAR_TIN0_TOUT0 (0x02) +#define GPIO_PAR_TIN0_DREQ0 (0x01) +#define GPIO_PAR_TIN0_TIN0 (0x03) + +/* Bit definitions and macros for GPIO_PAR_LCDDATA */ +#define GPIO_PAR_LCDDATA_LD7_0(x) ((x)&0x03) +#define GPIO_PAR_LCDDATA_LD15_8(x) (((x)&0x03)<<2) +#define GPIO_PAR_LCDDATA_LD16(x) (((x)&0x03)<<4) +#define GPIO_PAR_LCDDATA_LD17(x) (((x)&0x03)<<6) + +/* Bit definitions and macros for GPIO_PAR_LCDCTL */ +#define GPIO_PAR_LCDCTL_CLS (0x0001) +#define GPIO_PAR_LCDCTL_PS (0x0002) +#define GPIO_PAR_LCDCTL_REV (0x0004) +#define GPIO_PAR_LCDCTL_SPL_SPR (0x0008) +#define GPIO_PAR_LCDCTL_CONTRAST (0x0010) +#define GPIO_PAR_LCDCTL_LSCLK (0x0020) +#define GPIO_PAR_LCDCTL_LP_HSYNC (0x0040) +#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x0080) +#define GPIO_PAR_LCDCTL_ACD_OE (0x0100) + +/* Bit definitions and macros for GPIO_PAR_IRQ */ +#define GPIO_PAR_IRQ1(x) (((x)&0x0003)<<4) +#define GPIO_PAR_IRQ2(x) (((x)&0x0003)<<6) +#define GPIO_PAR_IRQ4(x) (((x)&0x0003)<<8) +#define GPIO_PAR_IRQ5(x) (((x)&0x0003)<<10) +#define GPIO_PAR_IRQ6(x) (((x)&0x0003)<<12) + +/* Bit definitions and macros for GPIO_MSCR_FLEXBUS */ +#define GPIO_MSCR_FLEXBUS_ADDRCTL(x) ((x)&0x03) +#define GPIO_MSCR_FLEXBUS_DLOWER(x) (((x)&0x03)<<2) +#define GPIO_MSCR_FLEXBUS_DUPPER(x) (((x)&0x03)<<4) + +/* Bit definitions and macros for GPIO_MSCR_SDRAM */ +#define GPIO_MSCR_SDRAM_SDRAM(x) ((x)&0x03) +#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) +#define GPIO_MSCR_SDRAM_SDCLKB(x) (((x)&0x03)<<4) + +/* Bit definitions and macros for GPIO_DSCR_I2C */ +#define GPIO_DSCR_I2C_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_PWM */ +#define GPIO_DSCR_PWM_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_FEC */ +#define GPIO_DSCR_FEC_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_UART */ +#define GPIO_DSCR_UART0_DSE(x) ((x)&0x03) +#define GPIO_DSCR_UART1_DSE(x) (((x)&0x03)<<2) + +/* Bit definitions and macros for GPIO_DSCR_QSPI */ +#define GPIO_DSCR_QSPI_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_TIMER */ +#define GPIO_DSCR_TIMER_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_SSI */ +#define GPIO_DSCR_SSI_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_LCD */ +#define GPIO_DSCR_LCD_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_DEBUG */ +#define GPIO_DSCR_DEBUG_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_CLKRST */ +#define GPIO_DSCR_CLKRST_DSE(x) ((x)&0x03) + +/* Bit definitions and macros for GPIO_DSCR_IRQ */ +#define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03) + +/* not done yet */ +/********************************************************************* +* LCD Controller (LCDC) +*********************************************************************/ +/* Bit definitions and macros for LCDC_LSSAR */ +#define LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for LCDC_LSR */ +#define LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0) +#define LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20) + +/* Bit definitions and macros for LCDC_LVPWR */ +#define LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0) + +/* Bit definitions and macros for LCDC_LCPR */ +#define LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0) +#define LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16) +#define LCDC_LCPR_OP (0x10000000) +#define LCDC_LCPR_CC(x) (((x)&0x00000003)<<30) +#define LCDC_LCPR_CC_TRANSPARENT (0x00000000) +#define LCDC_LCPR_CC_OR (0x40000000) +#define LCDC_LCPR_CC_XOR (0x80000000) +#define LCDC_LCPR_CC_AND (0xC0000000) +#define LCDC_LCPR_OP_ON (0x10000000) +#define LCDC_LCPR_OP_OFF (0x00000000) + +/* Bit definitions and macros for LCDC_LCWHBR */ +#define LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0) +#define LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16) +#define LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24) +#define LCDC_LCWHBR_BK_EN (0x80000000) +#define LCDC_LCWHBR_BK_EN_ON (0x80000000) +#define LCDC_LCWHBR_BK_EN_OFF (0x00000000) + +/* Bit definitions and macros for LCDC_LCCMR */ +#define LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0) +#define LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) +#define LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) + +/* Bit definitions and macros for LCDC_LPCR */ +#define LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0) +#define LCDC_LPCR_SHARP (0x00000040) +#define LCDC_LPCR_SCLKSEL (0x00000080) +#define LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8) +#define LCDC_LPCR_ACDSEL (0x00008000) +#define LCDC_LPCR_REV_VS (0x00010000) +#define LCDC_LPCR_SWAP_SEL (0x00020000) +#define LCDC_LPCR_ENDSEL (0x00040000) +#define LCDC_LPCR_SCLKIDLE (0x00080000) +#define LCDC_LPCR_OEPOL (0x00100000) +#define LCDC_LPCR_CLKPOL (0x00200000) +#define LCDC_LPCR_LPPOL (0x00400000) +#define LCDC_LPCR_FLM (0x00800000) +#define LCDC_LPCR_PIXPOL (0x01000000) +#define LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25) +#define LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28) +#define LCDC_LPCR_COLOR (0x40000000) +#define LCDC_LPCR_TFT (0x80000000) +#define LCDC_LPCR_MODE_MONOCHROME (0x00000000) +#define LCDC_LPCR_MODE_CSTN (0x40000000) +#define LCDC_LPCR_MODE_TFT (0xC0000000) +#define LCDC_LPCR_PBSIZ_1 (0x00000000) +#define LCDC_LPCR_PBSIZ_2 (0x10000000) +#define LCDC_LPCR_PBSIZ_4 (0x20000000) +#define LCDC_LPCR_PBSIZ_8 (0x30000000) +#define LCDC_LPCR_BPIX_1bpp (0x00000000) +#define LCDC_LPCR_BPIX_2bpp (0x02000000) +#define LCDC_LPCR_BPIX_4bpp (0x04000000) +#define LCDC_LPCR_BPIX_8bpp (0x06000000) +#define LCDC_LPCR_BPIX_12bpp (0x08000000) +#define LCDC_LPCR_BPIX_16bpp (0x0A000000) +#define LCDC_LPCR_BPIX_18bpp (0x0C000000) + +#define LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30) + +/* Bit definitions and macros for LCDC_LHCR */ +#define LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0) +#define LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) +#define LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26) + +/* Bit definitions and macros for LCDC_LVCR */ +#define LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0) +#define LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) +#define LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26) + +/* Bit definitions and macros for LCDC_LPOR */ +#define LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0) + +/* Bit definitions and macros for LCDC_LPCCR */ +#define LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0) +#define LCDC_LPCCR_CC_EN (0x00000100) +#define LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9) +#define LCDC_LPCCR_LDMSK (0x00008000) +#define LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16) +#define LCDC_LPCCR_SCR_LINEPULSE (0x00000000) +#define LCDC_LPCCR_SCR_PIXELCLK (0x00002000) +#define LCDC_LPCCR_SCR_LCDCLOCK (0x00004000) + +/* Bit definitions and macros for LCDC_LDCR */ +#define LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0) +#define LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16) +#define LCDC_LDCR_BURST (0x80000000) + +/* Bit definitions and macros for LCDC_LRMCR */ +#define LCDC_LRMCR_SEL_REF (0x00000001) + +/* Bit definitions and macros for LCDC_LICR */ +#define LCDC_LICR_INTCON (0x00000001) +#define LCDC_LICR_INTSYN (0x00000004) +#define LCDC_LICR_GW_INT_CON (0x00000010) + +/* Bit definitions and macros for LCDC_LIER */ +#define LCDC_LIER_BOF_EN (0x00000001) +#define LCDC_LIER_EOF_EN (0x00000002) +#define LCDC_LIER_ERR_RES_EN (0x00000004) +#define LCDC_LIER_UDR_ERR_EN (0x00000008) +#define LCDC_LIER_GW_BOF_EN (0x00000010) +#define LCDC_LIER_GW_EOF_EN (0x00000020) +#define LCDC_LIER_GW_ERR_RES_EN (0x00000040) +#define LCDC_LIER_GW_UDR_ERR_EN (0x00000080) + +/* Bit definitions and macros for LCDC_LISR */ +#define LCDC_LISR_BOF (0x00000001) +#define LCDC_LISR_EOF (0x00000002) +#define LCDC_LISR_ERR_RES (0x00000004) +#define LCDC_LISR_UDR_ERR (0x00000008) +#define LCDC_LISR_GW_BOF (0x00000010) +#define LCDC_LISR_GW_EOF (0x00000020) +#define LCDC_LISR_GW_ERR_RES (0x00000040) +#define LCDC_LISR_GW_UDR_ERR (0x00000080) + +/* Bit definitions and macros for LCDC_LGWSAR */ +#define LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for LCDC_LGWSR */ +#define LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0) +#define LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20) + +/* Bit definitions and macros for LCDC_LGWVPWR */ +#define LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0) + +/* Bit definitions and macros for LCDC_LGWPOR */ +#define LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0) + +/* Bit definitions and macros for LCDC_LGWPR */ +#define LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0) +#define LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16) + +/* Bit definitions and macros for LCDC_LGWCR */ +#define LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0) +#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) +#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) +#define LCDC_LGWCR_GW_RVS (0x00200000) +#define LCDC_LGWCR_GWE (0x00400000) +#define LCDC_LGWCR_GWCKE (0x00800000) +#define LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for LCDC_LGWDCR */ +#define LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0) +#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) +#define LCDC_LGWDCR_GWBT (0x80000000) + +/* Bit definitions and macros for LCDC_BPLUT_BASE */ +#define LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for LCDC_GWLUT_BASE */ +#define LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) + +/* not done yet */ +/********************************************************************* +* USB Controller (USB) +*********************************************************************/ +/* Bit definitions and macros for USB_HCSPARAMS */ +#define USB_HCSPARAMS_N_PORTS(x) ((x)&0x0000000F) +#define USB_HCSPARAMS_PPC (0x00000010) +#define USB_HCSPARAMS_N_PCC(x) (((x)&0x0000000F)<<8) +#define USB_HCSPARAMS_N_CC(x) (((x)&0x0000000F)<<12) +#define USB_HCSPARAMS_PI (0x00010000) +#define USB_HCSPARAMS_N_PTT(x) (((x)&0x0000000F)<<20) +#define USB_HCSPARAMS_N_TT(x) (((x)&0x0000000F)<<24) + +/* Bit definitions and macros for USB_HCCPARAMS */ +#define USB_HCCPARAMS_ADC (0x00000001) +#define USB_HCCPARAMS_PFL (0x00000002) +#define USB_HCCPARAMS_ASP (0x00000004) +#define USB_HCCPARAMS_IST(x) (((x)&0x0000000F)<<4) +#define USB_HCCPARAMS_EECP(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for USB_DCIVERSION */ +#define USB_DCIVERSION_DCIVERSION(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for USB_DCCPARAMS */ +#define USB_DCCPARAMS_DEN(x) (((x)&0x0000001F)<<0) +#define USB_DCCPARAMS_DC (0x00000080) +#define USB_DCCPARAMS_HC (0x00000100) + +/* Bit definitions and macros for USB_USBCMD */ +#define USB_USBCMD_RS (0x00000001) +#define USB_USBCMD_RST (0x00000002) +#define USB_USBCMD_FS0 (0x00000004) +#define USB_USBCMD_FS1 (0x00000008) +#define USB_USBCMD_PSE (0x00000010) +#define USB_USBCMD_ASE (0x00000020) +#define USB_USBCMD_IAA (0x00000040) +#define USB_USBCMD_LR (0x00000080) +#define USB_USBCMD_ASP(x) (((x)&0x00000003)<<8) +#define USB_USBCMD_ASPE (0x00000800) +#define USB_USBCMD_SUTW (0x00002000) +#define USB_USBCMD_ATDTW (0x00004000) +#define USB_USBCMD_FS2 (0x00008000) +#define USB_USBCMD_ITC(x) (((x)&0x000000FF)<<16) +#define USB_USBCMD_ITC_IMM (0x00000000) +#define USB_USBCMD_ITC_1 (0x00010000) +#define USB_USBCMD_ITC_2 (0x00020000) +#define USB_USBCMD_ITC_4 (0x00040000) +#define USB_USBCMD_ITC_8 (0x00080000) +#define USB_USBCMD_ITC_16 (0x00100000) +#define USB_USBCMD_ITC_32 (0x00200000) +#define USB_USBCMD_ITC_40 (0x00400000) +#define USB_USBCMD_FS_1024 (0x00000000) +#define USB_USBCMD_FS_512 (0x00000004) +#define USB_USBCMD_FS_256 (0x00000008) +#define USB_USBCMD_FS_128 (0x0000000C) +#define USB_USBCMD_FS_64 (0x00008000) +#define USB_USBCMD_FS_32 (0x00008004) +#define USB_USBCMD_FS_16 (0x00008008) +#define USB_USBCMD_FS_8 (0x0000800C) + +/* Bit definitions and macros for USB_USBSTS */ +#define USB_USBSTS_UI (0x00000001) +#define USB_USBSTS_UEI (0x00000002) +#define USB_USBSTS_PCI (0x00000004) +#define USB_USBSTS_FRI (0x00000008) +#define USB_USBSTS_SEI (0x00000010) +#define USB_USBSTS_AAI (0x00000020) +#define USB_USBSTS_URI (0x00000040) +#define USB_USBSTS_SRI (0x00000080) +#define USB_USBSTS_SLI (0x00000100) +#define USB_USBSTS_HCH (0x00001000) +#define USB_USBSTS_RCL (0x00002000) +#define USB_USBSTS_PS (0x00004000) +#define USB_USBSTS_AS (0x00008000) + +/* Bit definitions and macros for USB_USBINTR */ +#define USB_USBINTR_UE (0x00000001) +#define USB_USBINTR_UEE (0x00000002) +#define USB_USBINTR_PCE (0x00000004) +#define USB_USBINTR_FRE (0x00000008) +#define USB_USBINTR_SEE (0x00000010) +#define USB_USBINTR_AAE (0x00000020) +#define USB_USBINTR_URE (0x00000040) +#define USB_USBINTR_SRE (0x00000080) +#define USB_USBINTR_SLE (0x00000100) + +/* Bit definitions and macros for USB_FRINDEX */ +#define USB_FRINDEX_FRINDEX(x) (((x)&0x00003FFF)<<0) + +/* Bit definitions and macros for USB_PERIODICLISTBASE */ +#define USB_PERIODICLISTBASE_PERBASE(x) (((x)&0x000FFFFF)<<12) + +/* Bit definitions and macros for USB_DEVICEADDR */ +#define USB_DEVICEADDR_USBADR(x) (((x)&0x0000007F)<<25) + +/* Bit definitions and macros for USB_ASYNCLISTADDR */ +#define USB_ASYNCLISTADDR_ASYBASE(x) (((x)&0x07FFFFFF)<<5) + +/* Bit definitions and macros for USB_EPLISTADDR */ +#define USB_EPLISTADDR_EPBASE(x) (((x)&0x001FFFFF)<<11) + +/* Bit definitions and macros for USB_ASNCTTSTS */ +#define USB_ASNCTTSTS_TTAS (0x00000001) +#define USB_ASNCTTSTS_TTAC (0x00000002) + +/* Bit definitions and macros for USB_BURSTSIZE */ +#define USB_BURSTSIZE_RXPBURST(x) (((x)&0x000000FF)<<0) +#define USB_BURSTSIZE_TXPBURST(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for USB_TXFILLTUNING */ +#define USB_TXFILLTUNING_TXSCHOH(x) (((x)&0x000000FF)<<0) +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((x)&0x0000001F)<<8) +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((x)&0x0000003F)<<16) + +/* Bit definitions and macros for USB_TXTTFILLTUNING */ +#define USB_TXTTFILLTUNING_TXTTSCHOH(x) (((x)&0x0000001F)<<0) +#define USB_TXTTFILLTUNING_TXTTSCHHEALTH(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for USB_ULPI_VIEWPORT */ +#define USB_ULPI_VIEWPORT_ULPI_DATWR(x) (((x)&0x000000FF)<<0) +#define USB_ULPI_VIEWPORT_ULPI_DATRD(x) (((x)&0x000000FF)<<8) +#define USB_ULPI_VIEWPORT_ULPI_ADDR(x) (((x)&0x000000FF)<<16) +#define USB_ULPI_VIEWPORT_ULPI_PORT(x) (((x)&0x00000007)<<24) +#define USB_ULPI_VIEWPORT_ULPI_SS (0x08000000) +#define USB_ULPI_VIEWPORT_ULPI_RW (0x20000000) +#define USB_ULPI_VIEWPORT_ULPI_RUN (0x40000000) +#define USB_ULPI_VIEWPORT_ULPI_WU (0x80000000) + +/* Bit definitions and macros for USB_CONFIGFLAG */ +#define USB_CONFIGFLAG_CONFIGFLAG(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for USB_PORTSC */ +#define USB_PORTSC_CCS (0x00000001) +#define USB_PORTSC_CSC (0x00000002) +#define USB_PORTSC_PE (0x00000004) +#define USB_PORTSC_PEC (0x00000008) +#define USB_PORTSC_OCA (0x00000010) +#define USB_PORTSC_OCC (0x00000020) +#define USB_PORTSC_FPR (0x00000040) +#define USB_PORTSC_SUSP (0x00000080) +#define USB_PORTSC_PR (0x00000100) +#define USB_PORTSC_LS(x) (((x)&0x00000003)<<10) +#define USB_PORTSC_PP (0x00001000) +#define USB_PORTSC_PO (0x00002000) +#define USB_PORTSC_PIC(x) (((x)&0x00000003)<<14) +#define USB_PORTSC_PTC(x) (((x)&0x0000000F)<<16) +#define USB_PORTSC_WLCN (0x00100000) +#define USB_PORTSC_WKDS (0x00200000) +#define USB_PORTSC_WKOC (0x00400000) +#define USB_PORTSC_PHCD (0x00800000) +#define USB_PORTSC_PFSC (0x01000000) +#define USB_PORTSC_PSPD(x) (((x)&0x00000003)<<26) +#define USB_PORTSC_PTS(x) (((x)&0x00000003)<<30) +#define USB_PORTSC_PTS_ULPI (0x80000000) +#define USB_PORTSC_PTS_FS_LS (0xC0000000) +#define USB_PORTSC_PSPD_FULL (0x00000000) +#define USB_PORTSC_PSPD_LOW (0x04000000) +#define USB_PORTSC_PSPD_HIGH (0x08000000) +#define USB_PORTSC_PTC_DISBALE (0x00000000) +#define USB_PORTSC_PTC_JSTATE (0x00010000) +#define USB_PORTSC_PTC_KSTATE (0x00020000) +#define USB_PORTSC_PTC_SEQ_NAK (0x00030000) +#define USB_PORTSC_PTC_PACKET (0x00040000) +#define USB_PORTSC_PTC_FORCE_ENABLE (0x00050000) +#define USB_PORTSC_PIC_OFF (0x00000000) +#define USB_PORTSC_PIC_AMBER (0x00004000) +#define USB_PORTSC_PIC_GREEN (0x00008000) +#define USB_PORTSC_LS_SE0 (0x00000000) +#define USB_PORTSC_LS_JSTATE (0x00000400) +#define USB_PORTSC_LS_KSTATE (0x00000800) + +/* Bit definitions and macros for USB_OTGSC */ +#define USB_OTGSC_VD (0x00000001) +#define USB_OTGSC_VC (0x00000002) +#define USB_OTGSC_OT (0x00000008) +#define USB_OTGSC_DP (0x00000010) +#define USB_OTGSC_ID (0x00000100) +#define USB_OTGSC_AVV (0x00000200) +#define USB_OTGSC_ASV (0x00000400) +#define USB_OTGSC_BSV (0x00000800) +#define USB_OTGSC_BSE (0x00001000) +#define USB_OTGSC_1MST (0x00002000) +#define USB_OTGSC_DPS (0x00004000) +#define USB_OTGSC_IDIS (0x00010000) +#define USB_OTGSC_AVVIS (0x00020000) +#define USB_OTGSC_ASVIS (0x00040000) +#define USB_OTGSC_BSVIS (0x00080000) +#define USB_OTGSC_BSEIS (0x00100000) +#define USB_OTGSC_1MSS (0x00200000) +#define USB_OTGSC_DPIS (0x00400000) +#define USB_OTGSC_IDIE (0x01000000) +#define USB_OTGSC_AVVIE (0x02000000) +#define USB_OTGSC_ASVIE (0x04000000) +#define USB_OTGSC_BSVIE (0x08000000) +#define USB_OTGSC_BSEIE (0x10000000) +#define USB_OTGSC_1MSE (0x20000000) +#define USB_OTGSC_DPIE (0x40000000) +#define USB_OTGSC_CLEAR (0x007F0000) +#define USB_OTGSC_ENABLE_ALL (0x7F000000) + +/* Bit definitions and macros for USB_USBMODE */ +#define USB_USBMODE_CM(x) (((x)&0x00000003)<<0) +#define USB_USBMODE_SLOM (0x00000008) +#define USB_USBMODE_SDIS (0x00000010) +#define USB_USBMODE_CM_IDLE (0x00000000) +#define USB_USBMODE_CM_DEVICE (0x00000002) +#define USB_USBMODE_CM_HOST (0x00000003) +#define USB_USBMODE_ES (0x00000004) + +/* Bit definitions and macros for USB_EPSETUPSR */ +#define USB_EPSETUPSR_EPSETUPSTAT(x) (((x)&0x0000003F)<<0) + +/* Bit definitions and macros for USB_EPPRIME */ +#define USB_EPPRIME_PERB(x) (((x)&0x0000003F)<<0) +#define USB_EPPRIME_PETB(x) (((x)&0x0000003F)<<16) +#define USB_EPPRIME_PETB0 (0x00010000) +#define USB_EPPRIME_PETB1 (0x00020000) +#define USB_EPPRIME_PETB2 (0x00040000) +#define USB_EPPRIME_PETB3 (0x00080000) +#define USB_EPPRIME_PETB4 (0x00100000) +#define USB_EPPRIME_PETB5 (0x00200000) +#define USB_EPPRIME_PERB0 (0x00000001) +#define USB_EPPRIME_PERB1 (0x00000002) +#define USB_EPPRIME_PERB2 (0x00000004) +#define USB_EPPRIME_PERB3 (0x00000008) +#define USB_EPPRIME_PERB4 (0x00000010) +#define USB_EPPRIME_PERB5 (0x00000020) + +/* Bit definitions and macros for USB_EPFLUSH */ +#define USB_EPFLUSH_FERB(x) (((x)&0x0000003F)<<0) +#define USB_EPFLUSH_FETB(x) (((x)&0x0000003F)<<16) +#define USB_EPFLUSH_FETB0 (0x00010000) +#define USB_EPFLUSH_FETB1 (0x00020000) +#define USB_EPFLUSH_FETB2 (0x00040000) +#define USB_EPFLUSH_FETB3 (0x00080000) +#define USB_EPFLUSH_FETB4 (0x00100000) +#define USB_EPFLUSH_FETB5 (0x00200000) +#define USB_EPFLUSH_FERB0 (0x00000001) +#define USB_EPFLUSH_FERB1 (0x00000002) +#define USB_EPFLUSH_FERB2 (0x00000004) +#define USB_EPFLUSH_FERB3 (0x00000008) +#define USB_EPFLUSH_FERB4 (0x00000010) +#define USB_EPFLUSH_FERB5 (0x00000020) + +/* Bit definitions and macros for USB_EPSR */ +#define USB_EPSR_ERBR(x) (((x)&0x0000003F)<<0) +#define USB_EPSR_ETBR(x) (((x)&0x0000003F)<<16) +#define USB_EPSR_ETBR0 (0x00010000) +#define USB_EPSR_ETBR1 (0x00020000) +#define USB_EPSR_ETBR2 (0x00040000) +#define USB_EPSR_ETBR3 (0x00080000) +#define USB_EPSR_ETBR4 (0x00100000) +#define USB_EPSR_ETBR5 (0x00200000) +#define USB_EPSR_ERBR0 (0x00000001) +#define USB_EPSR_ERBR1 (0x00000002) +#define USB_EPSR_ERBR2 (0x00000004) +#define USB_EPSR_ERBR3 (0x00000008) +#define USB_EPSR_ERBR4 (0x00000010) +#define USB_EPSR_ERBR5 (0x00000020) + +/* Bit definitions and macros for USB_EPCOMPLETE */ +#define USB_EPCOMPLETE_ERCE(x) (((x)&0x0000003F)<<0) +#define USB_EPCOMPLETE_ETCE(x) (((x)&0x0000003F)<<16) +#define USB_EPCOMPLETE_ETCE0 (0x00010000) +#define USB_EPCOMPLETE_ETCE1 (0x00020000) +#define USB_EPCOMPLETE_ETCE2 (0x00040000) +#define USB_EPCOMPLETE_ETCE3 (0x00080000) +#define USB_EPCOMPLETE_ETCE4 (0x00100000) +#define USB_EPCOMPLETE_ETCE5 (0x00200000) +#define USB_EPCOMPLETE_ERCE0 (0x00000001) +#define USB_EPCOMPLETE_ERCE1 (0x00000002) +#define USB_EPCOMPLETE_ERCE2 (0x00000004) +#define USB_EPCOMPLETE_ERCE3 (0x00000008) +#define USB_EPCOMPLETE_ERCE4 (0x00000010) +#define USB_EPCOMPLETE_ERCE5 (0x00000020) + +/* Bit definitions and macros for USB_EPCR0 */ +#define USB_EPCR0_RXS (0x00000001) +#define USB_EPCR0_RXT(x) (((x)&0x00000003)<<2) +#define USB_EPCR0_RXE (0x00000080) +#define USB_EPCR0_TXS (0x00010000) +#define USB_EPCR0_TXT(x) (((x)&0x00000003)<<18) +#define USB_EPCR0_TXE (0x00800000) + +/* Bit definitions and macros for USB_EPCR */ +#define USB_EPCR_RXS (0x00000001) +#define USB_EPCR_RXD (0x00000002) +#define USB_EPCR_RXT(x) (((x)&0x00000003)<<2) +#define USB_EPCR_RXI (0x00000020) +#define USB_EPCR_RXR (0x00000040) +#define USB_EPCR_RXE (0x00000080) +#define USB_EPCR_TXS (0x00010000) +#define USB_EPCR_TXD (0x00020000) +#define USB_EPCR_TXT(x) (((x)&0x00000003)<<18) +#define USB_EPCR_TXI (0x00200000) +#define USB_EPCR_TXR (0x00400000) +#define USB_EPCR_TXE (0x00800000) +#define USB_EPCR_TXT_CONTROL (0x00000000) +#define USB_EPCR_TXT_ISO (0x00040000) +#define USB_EPCR_TXT_BULK (0x00080000) +#define USB_EPCR_TXT_INT (0x000C0000) +#define USB_EPCR_RXT_CONTROL (0x00000000) +#define USB_EPCR_RXT_ISO (0x00000004) +#define USB_EPCR_RXT_BULK (0x00000008) +#define USB_EPCR_RXT_INT (0x0000000C) + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ +/* Bit definitions and macros for SDRAMC_SDMR */ +#define SDRAMC_SDMR_BNKAD_LEMR (0x40000000) +#define SDRAMC_SDMR_BNKAD_LMR (0x00000000) +#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) +#define SDRAMC_SDMR_CMD (0x00010000) + +/* Bit definitions and macros for SDRAMC_SDCR */ +#define SDRAMC_SDCR_MODE_EN (0x80000000) +#define SDRAMC_SDCR_CKE (0x40000000) +#define SDRAMC_SDCR_DDR (0x20000000) +#define SDRAMC_SDCR_REF (0x10000000) +#define SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) +#define SDRAMC_SDCR_OE_RULE (0x00400000) +#define SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) +#define SDRAMC_SDCR_PS_32 (0x00000000) +#define SDRAMC_SDCR_PS_16 (0x00002000) +#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) +#define SDRAMC_SDCR_IREF (0x00000004) +#define SDRAMC_SDCR_IPALL (0x00000002) + +/* Bit definitions and macros for SDRAMC_SDCFG1 */ +#define SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) +#define SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) +#define SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) +#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) +#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) +#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) +#define SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) + +/* Bit definitions and macros for SDRAMC_SDCFG2 */ +#define SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) +#define SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) +#define SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) +#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) + +/* Bit definitions and macros for SDRAMC_SDDS */ +#define SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) +#define SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) +#define SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) +#define SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) +#define SDRAMC_SDDS_SB_D(x) ((x)&0x00000003) + +/* Bit definitions and macros for SDRAMC_SDCS */ +#define SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) +#define SDRAMC_SDCS_CSSZ(x) ((x)&0x0000001F) +#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) +#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) + +/********************************************************************* +* Synchronous Serial Interface (SSI) +*********************************************************************/ +/* Bit definitions and macros for SSI_CR */ +#define SSI_CR_CIS (0x00000200) +#define SSI_CR_TCH (0x00000100) +#define SSI_CR_MCE (0x00000080) +#define SSI_CR_I2S_SLAVE (0x00000040) +#define SSI_CR_I2S_MASTER (0x00000020) +#define SSI_CR_I2S_NORMAL (0x00000000) +#define SSI_CR_SYN (0x00000010) +#define SSI_CR_NET (0x00000008) +#define SSI_CR_RE (0x00000004) +#define SSI_CR_TE (0x00000002) +#define SSI_CR_SSI_EN (0x00000001) + +/* Bit definitions and macros for SSI_ISR */ +#define SSI_ISR_CMDAU (0x00040000) +#define SSI_ISR_CMDDU (0x00020000) +#define SSI_ISR_RXT (0x00010000) +#define SSI_ISR_RDR1 (0x00008000) +#define SSI_ISR_RDR0 (0x00004000) +#define SSI_ISR_TDE1 (0x00002000) +#define SSI_ISR_TDE0 (0x00001000) +#define SSI_ISR_ROE1 (0x00000800) +#define SSI_ISR_ROE0 (0x00000400) +#define SSI_ISR_TUE1 (0x00000200) +#define SSI_ISR_TUE0 (0x00000100) +#define SSI_ISR_TFS (0x00000080) +#define SSI_ISR_RFS (0x00000040) +#define SSI_ISR_TLS (0x00000020) +#define SSI_ISR_RLS (0x00000010) +#define SSI_ISR_RFF1 (0x00000008) +#define SSI_ISR_RFF0 (0x00000004) +#define SSI_ISR_TFE1 (0x00000002) +#define SSI_ISR_TFE0 (0x00000001) + +/* Bit definitions and macros for SSI_IER */ +#define SSI_IER_RDMAE (0x00400000) +#define SSI_IER_RIE (0x00200000) +#define SSI_IER_TDMAE (0x00100000) +#define SSI_IER_TIE (0x00080000) +#define SSI_IER_CMDAU (0x00040000) +#define SSI_IER_CMDU (0x00020000) +#define SSI_IER_RXT (0x00010000) +#define SSI_IER_RDR1 (0x00008000) +#define SSI_IER_RDR0 (0x00004000) +#define SSI_IER_TDE1 (0x00002000) +#define SSI_IER_TDE0 (0x00001000) +#define SSI_IER_ROE1 (0x00000800) +#define SSI_IER_ROE0 (0x00000400) +#define SSI_IER_TUE1 (0x00000200) +#define SSI_IER_TUE0 (0x00000100) +#define SSI_IER_TFS (0x00000080) +#define SSI_IER_RFS (0x00000040) +#define SSI_IER_TLS (0x00000020) +#define SSI_IER_RLS (0x00000010) +#define SSI_IER_RFF1 (0x00000008) +#define SSI_IER_RFF0 (0x00000004) +#define SSI_IER_TFE1 (0x00000002) +#define SSI_IER_TFE0 (0x00000001) + +/* Bit definitions and macros for SSI_TCR */ +#define SSI_TCR_TXBIT0 (0x00000200) +#define SSI_TCR_TFEN1 (0x00000100) +#define SSI_TCR_TFEN0 (0x00000080) +#define SSI_TCR_TFDIR (0x00000040) +#define SSI_TCR_TXDIR (0x00000020) +#define SSI_TCR_TSHFD (0x00000010) +#define SSI_TCR_TSCKP (0x00000008) +#define SSI_TCR_TFSI (0x00000004) +#define SSI_TCR_TFSL (0x00000002) +#define SSI_TCR_TEFS (0x00000001) + +/* Bit definitions and macros for SSI_RCR */ +#define SSI_RCR_RXEXT (0x00000400) +#define SSI_RCR_RXBIT0 (0x00000200) +#define SSI_RCR_RFEN1 (0x00000100) +#define SSI_RCR_RFEN0 (0x00000080) +#define SSI_RCR_RSHFD (0x00000010) +#define SSI_RCR_RSCKP (0x00000008) +#define SSI_RCR_RFSI (0x00000004) +#define SSI_RCR_RFSL (0x00000002) +#define SSI_RCR_REFS (0x00000001) + +/* Bit definitions and macros for SSI_CCR */ +#define SSI_CCR_DIV2 (0x00040000) +#define SSI_CCR_PSR (0x00020000) +#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13) +#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8) +#define SSI_CCR_PM(x) ((x)&0x000000FF) + +/* Bit definitions and macros for SSI_FCSR */ +#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) +#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) +#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) +#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) +#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) +#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) +#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) +#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F) + +/* Bit definitions and macros for SSI_ACR */ +#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) +#define SSI_ACR_WR (0x00000010) +#define SSI_ACR_RD (0x00000008) +#define SSI_ACR_TIF (0x00000004) +#define SSI_ACR_FV (0x00000002) +#define SSI_ACR_AC97EN (0x00000001) + +/* Bit definitions and macros for SSI_ACADD */ +#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF) + +/* Bit definitions and macros for SSI_ACDAT */ +#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF) + +/* Bit definitions and macros for SSI_ATAG */ +#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF) + +/********************************************************************* +* Phase Locked Loop (PLL) +*********************************************************************/ +/* Bit definitions and macros for PLL_PODR */ +#define PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) +#define PLL_PODR_BUSDIV(x) ((x)&0x0F) + +/* Bit definitions and macros for PLL_PLLCR */ +#define PLL_PLLCR_DITHEN (0x80) +#define PLL_PLLCR_DITHDEV(x) ((x)&0x07) + +#endif /* mcf5329_h */ diff --git a/include/asm-m68k/mcfrtc.h b/include/asm-m68k/mcfrtc.h new file mode 100644 index 00000000000..70785354fb9 --- /dev/null +++ b/include/asm-m68k/mcfrtc.h @@ -0,0 +1,108 @@ +/* + * RealTime Clock + * + * (C) Copyright 2007 + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MCFRTC_H__ +#define __MCFRTC_H__ + +/* Real time Clock */ +typedef struct rtc_ctrl { + u32 hourmin; /* 0x00 Hours and Minutes Counter Register */ + u32 seconds; /* 0x04 Seconds Counter Register */ + u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */ + u32 alrm_sec; /* 0x0C Seconds Alarm Register */ + u32 cr; /* 0x10 Control Register */ + u32 isr; /* 0x14 Interrupt Status Register */ + u32 ier; /* 0x18 Interrupt Enable Register */ + u32 stpwach; /* 0x1C Stopwatch Minutes Register */ + u32 days; /* 0x20 Days Counter Register */ + u32 alrm_day; /* 0x24 Days Alarm Register */ +} rtc_t; + +/* Bit definitions and macros for HOURMIN */ +#define RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)) +#define RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for SECONDS */ +#define RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)) + +/* Bit definitions and macros for ALRM_HM */ +#define RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)) +#define RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8) + +/* Bit definitions and macros for ALRM_SEC */ +#define RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)) + +/* Bit definitions and macros for CR */ +#define RTC_CR_SWR (0x00000001) +#define RTC_CR_XTL(x) (((x)&0x00000003)<<5) +#define RTC_CR_EN (0x00000080) +#define RTC_CR_32768 (0x0) +#define RTC_CR_32000 (0x1) +#define RTC_CR_38400 (0x2) + +/* Bit definitions and macros for ISR */ +#define RTC_ISR_SW (0x00000001) +#define RTC_ISR_MIN (0x00000002) +#define RTC_ISR_ALM (0x00000004) +#define RTC_ISR_DAY (0x00000008) +#define RTC_ISR_1HZ (0x00000010) +#define RTC_ISR_HR (0x00000020) +#define RTC_ISR_2HZ (0x00000080) +#define RTC_ISR_SAM0 (0x00000100) +#define RTC_ISR_SAM1 (0x00000200) +#define RTC_ISR_SAM2 (0x00000400) +#define RTC_ISR_SAM3 (0x00000800) +#define RTC_ISR_SAM4 (0x00001000) +#define RTC_ISR_SAM5 (0x00002000) +#define RTC_ISR_SAM6 (0x00004000) +#define RTC_ISR_SAM7 (0x00008000) + +/* Bit definitions and macros for IER */ +#define RTC_IER_SW (0x00000001) +#define RTC_IER_MIN (0x00000002) +#define RTC_IER_ALM (0x00000004) +#define RTC_IER_DAY (0x00000008) +#define RTC_IER_1HZ (0x00000010) +#define RTC_IER_HR (0x00000020) +#define RTC_IER_2HZ (0x00000080) +#define RTC_IER_SAM0 (0x00000100) +#define RTC_IER_SAM1 (0x00000200) +#define RTC_IER_SAM2 (0x00000400) +#define RTC_IER_SAM3 (0x00000800) +#define RTC_IER_SAM4 (0x00001000) +#define RTC_IER_SAM5 (0x00002000) +#define RTC_IER_SAM6 (0x00004000) +#define RTC_IER_SAM7 (0x00008000) + +/* Bit definitions and macros for STPWCH */ +#define RTC_STPWCH_CNT(x) (((x)&0x0000003F)) + +/* Bit definitions and macros for DAYS */ +#define RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)) + +/* Bit definitions and macros for ALRM_DAY */ +#define RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)) + +#endif /* __MCFRTC_H__ */ diff --git a/include/asm-m68k/mcftimer.h b/include/asm-m68k/mcftimer.h index a73b80eaf81..988860d07f5 100644 --- a/include/asm-m68k/mcftimer.h +++ b/include/asm-m68k/mcftimer.h @@ -35,32 +35,31 @@ * Get address specific defines for this ColdFire member. */ #if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ +#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ #elif defined(CONFIG_M5272) -#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ -#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ +#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ +#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ +#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ +#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ #elif defined(CONFIG_M5282) | defined(CONFIG_M5271) -#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */ +#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */ +#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */ #define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */ #endif /* * Define the TIMER register set addresses. */ -#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ -#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */ -#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */ -#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */ -#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ - +#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ +#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */ +#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */ +#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */ +#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ /* * Define the TIMER register set addresses for 5282. @@ -73,29 +72,29 @@ * Bit definitions for the Timer Mode Register (TMR). * Register bit flags are common accross ColdFires. */ -#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ -#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ -#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ -#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ -#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ -#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ -#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ -#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ -#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ -#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ -#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ -#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ -#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ -#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ -#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ -#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ -#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ +#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ +#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ +#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ +#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ +#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ +#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ +#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ +#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ +#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ +#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ +#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ +#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ +#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ +#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ +#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ +#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ +#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ /* * Bit definitions for the Timer Event Registers (TER). */ -#define MCFTIMER_TER_CAP 0x01 /* Capture event */ -#define MCFTIMER_TER_REF 0x02 /* Refernece event */ +#define MCFTIMER_TER_CAP 0x01 /* Capture event */ +#define MCFTIMER_TER_REF 0x02 /* Refernece event */ /* * Bit definitions for the 5282 PIT Control and Status Register (PCSR). @@ -108,6 +107,77 @@ #define MCFTIMER_PCSR_HALTED 0x0020 #define MCFTIMER_PCSR_DOZE 0x0040 +/****************************************************************************/ +/* New Timer structure */ +/****************************************************************************/ +/* DMA Timer module registers */ +typedef struct dtimer_ctrl { + u16 tmr; /* 0x00 Mode register */ + u8 txmr; /* 0x02 Extended Mode register */ + u8 ter; /* 0x03 Event register */ + u32 trr; /* 0x04 Reference register */ + u32 tcr; /* 0x08 Capture register */ + u32 tcn; /* 0x0C Counter register */ +} dtmr_t; + +/*Programmable Interrupt Timer */ +typedef struct pit_ctrl { + u16 pcsr; /* 0x00 Control and Status Register */ + u16 pmr; /* 0x02 Modulus Register */ + u16 pcntr; /* 0x04 Count Register */ +} pit_t; + +/********************************************************************* +* DMA Timers (DTIM) +*********************************************************************/ +/* Bit definitions and macros for DTMR */ +#define DTIM_DTMR_RST (0x0001) /* Reset */ +#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */ +#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */ +#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */ +#define DTIM_DTMR_OM (0x0020) /* Output Mode */ +#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */ +#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */ +#define DTIM_DTMR_RST_EN (0x0001) +#define DTIM_DTMR_RST_RST (0x0000) +#define DTIM_DTMR_CE_ANY (0x00C0) +#define DTIM_DTMR_CE_FALL (0x0080) +#define DTIM_DTMR_CE_RISE (0x0040) +#define DTIM_DTMR_CE_NONE (0x0000) +#define DTIM_DTMR_CLK_DTIN (0x0006) +#define DTIM_DTMR_CLK_DIV16 (0x0004) +#define DTIM_DTMR_CLK_DIV1 (0x0002) +#define DTIM_DTMR_CLK_STOP (0x0000) + +/* Bit definitions and macros for DTXMR */ +#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */ +#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */ + +/* Bit definitions and macros for DTER */ +#define DTIM_DTER_CAP (0x01) /* Capture event */ +#define DTIM_DTER_REF (0x02) /* Output reference event */ + +/********************************************************************* +* +* Programmable Interrupt Timer Modules (PIT) +* +*********************************************************************/ + +/* Bit definitions and macros for PCSR */ +#define PIT_PCSR_EN (0x0001) +#define PIT_PCSR_RLD (0x0002) +#define PIT_PCSR_PIF (0x0004) +#define PIT_PCSR_PIE (0x0008) +#define PIT_PCSR_OVW (0x0010) +#define PIT_PCSR_HALTED (0x0020) +#define PIT_PCSR_DOZE (0x0040) +#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8) + +/* Bit definitions and macros for PMR */ +#define PIT_PMR_PM(x) (x) + +/* Bit definitions and macros for PCNTR */ +#define PIT_PCNTR_PC(x) (x) /****************************************************************************/ -#endif /* mcftimer_h */ +#endif /* mcftimer_h */ diff --git a/include/asm-m68k/mcfuart.h b/include/asm-m68k/mcfuart.h index 7c0999d61d8..43b49a87c6c 100644 --- a/include/asm-m68k/mcfuart.h +++ b/include/asm-m68k/mcfuart.h @@ -36,106 +36,105 @@ * space. */ #if defined(CONFIG_M5272) -#define MCFUART_BASE1 0x100 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#define MCFUART_BASE1 0x100 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ #elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) #if defined(CONFIG_NETtel) -#define MCFUART_BASE1 0x180 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#define MCFUART_BASE1 0x180 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ #else -#define MCFUART_BASE1 0x140 /* Base address of UART1 */ -#define MCFUART_BASE2 0x180 /* Base address of UART2 */ +#define MCFUART_BASE1 0x140 /* Base address of UART1 */ +#define MCFUART_BASE2 0x180 /* Base address of UART2 */ #endif #elif defined(CONFIG_M5282) || defined(CONFIG_M5271) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x240 /* Base address of UART2 */ +#define MCFUART_BASE3 0x280 /* Base address of UART3 */ #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) #if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ #else -#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ -#define MCFUART_BASE2 0x200 /* Base address of UART2 */ +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ #endif #endif - /* * Define the ColdFire UART register set addresses. */ -#define MCFUART_UMR 0x00 /* Mode register (r/w) */ -#define MCFUART_USR 0x04 /* Status register (r) */ -#define MCFUART_UCSR 0x04 /* Clock Select (w) */ -#define MCFUART_UCR 0x08 /* Command register (w) */ -#define MCFUART_URB 0x0c /* Receiver Buffer (r) */ -#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ -#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ -#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ -#define MCFUART_UISR 0x14 /* Interrup Status (r) */ -#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ -#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ -#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ +#define MCFUART_UMR 0x00 /* Mode register (r/w) */ +#define MCFUART_USR 0x04 /* Status register (r) */ +#define MCFUART_UCSR 0x04 /* Clock Select (w) */ +#define MCFUART_UCR 0x08 /* Command register (w) */ +#define MCFUART_URB 0x0c /* Receiver Buffer (r) */ +#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ +#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ +#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ +#define MCFUART_UISR 0x14 /* Interrup Status (r) */ +#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ +#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ +#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ #ifdef CONFIG_M5272 -#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ -#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ -#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ +#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ +#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ +#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ #else -#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ +#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ #endif -#define MCFUART_UIPR 0x34 /* Input Port (r) */ -#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ -#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ +#define MCFUART_UIPR 0x34 /* Input Port (r) */ +#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ +#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ #ifdef CONFIG_M5249 /* Note: This isn't in the 5249 docs */ -#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ +#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ #endif /* * Define bit flags in Mode Register 1 (MR1). */ -#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ -#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ -#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ -#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ -#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ - -#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ -#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ -#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ -#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ -#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ - -#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ -#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ -#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ -#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ +#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ +#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ +#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ +#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ +#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ + +#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ +#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ +#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ +#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ +#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ + +#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ +#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ +#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ +#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ /* * Define bit flags in Mode Register 2 (MR2). */ -#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ -#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ -#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ -#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ -#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ +#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ +#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ +#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ +#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ +#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ -#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ -#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ -#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ +#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ +#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ +#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ /* * Define bit flags in Status Register (USR). */ -#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ -#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ -#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ -#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ -#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ -#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ -#define MCFUART_USR_RXFULL 0x02 /* Receiver full */ -#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ +#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ +#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ +#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ +#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ +#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ +#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ +#define MCFUART_USR_RXFULL 0x02 /* Receiver full */ +#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ #define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) @@ -143,13 +142,13 @@ /* * Define bit flags in Clock Select Register (UCSR). */ -#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ -#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ -#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ +#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ +#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ +#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ -#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ -#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ -#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ +#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ +#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ +#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ /* * Define bit flags in Command Register (UCR). @@ -163,59 +162,200 @@ #define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ #define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ -#define MCFUART_UCR_TXNULL 0x00 /* No TX command */ -#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ -#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ -#define MCFUART_UCR_RXNULL 0x00 /* No RX command */ -#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ -#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ +#define MCFUART_UCR_TXNULL 0x00 /* No TX command */ +#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ +#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ +#define MCFUART_UCR_RXNULL 0x00 /* No RX command */ +#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ +#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ /* * Define bit flags in Input Port Change Register (UIPCR). */ -#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ -#define MCFUART_UIPCR_CTS 0x01 /* CTS value */ +#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ +#define MCFUART_UIPCR_CTS 0x01 /* CTS value */ /* * Define bit flags in Input Port Register (UIP). */ -#define MCFUART_UIPR_CTS 0x01 /* CTS value */ +#define MCFUART_UIPR_CTS 0x01 /* CTS value */ /* * Define bit flags in Output Port Registers (UOP). * Clear bit by writing to UOP0, set by writing to UOP1. */ -#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ +#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ /* * Define bit flags in the Auxiliary Control Register (UACR). */ -#define MCFUART_UACR_IEC 0x01 /* Input enable control */ +#define MCFUART_UACR_IEC 0x01 /* Input enable control */ /* * Define bit flags in Interrupt Status Register (UISR). * These same bits are used for the Interrupt Mask Register (UIMR). */ -#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ -#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ -#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ -#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ +#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ +#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ +#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ +#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ #ifdef CONFIG_M5272 /* * Define bit flags in the Transmitter FIFO Register (UTF). */ -#define MCFUART_UTF_TXB 0x1f /* transmitter data level */ -#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */ -#define MCFUART_UTF_TXS 0xc0 /* transmitter status */ +#define MCFUART_UTF_TXB 0x1f /* transmitter data level */ +#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */ +#define MCFUART_UTF_TXS 0xc0 /* transmitter status */ /* * Define bit flags in the Receiver FIFO Register (URF). */ -#define MCFUART_URF_RXB 0x1f /* receiver data level */ -#define MCFUART_URF_FULL 0x20 /* receiver fifo full */ -#define MCFUART_URF_RXS 0xc0 /* receiver status */ +#define MCFUART_URF_RXB 0x1f /* receiver data level */ +#define MCFUART_URF_FULL 0x20 /* receiver fifo full */ +#define MCFUART_URF_RXS 0xc0 /* receiver status */ #endif +#ifdef CONFIG_MCFUART +/* UART module registers */ +/* Register read/write struct */ +typedef struct uart { + u8 umr; /* 0x00 Mode Register */ + u8 resv0[0x3]; + union { + u8 usr; /* 0x04 Status Register */ + u8 ucsr; /* 0x04 Clock Select Register */ + }; + u8 resv1[0x3]; + u8 ucr; /* 0x08 Command Register */ + u8 resv2[0x3]; + union { + u8 utb; /* 0x0c Transmit Buffer */ + u8 urb; /* 0x0c Receive Buffer */ + }; + u8 resv3[0x3]; + union { + u8 uipcr; /* 0x10 Input Port Change Register */ + u8 uacr; /* 0x10 Auxiliary Control reg */ + }; + u8 resv4[0x3]; + union { + u8 uimr; /* 0x14 Interrupt Mask reg */ + u8 uisr; /* 0x14 Interrupt Status reg */ + }; + u8 resv5[0x3]; + u8 ubg1; /* 0x18 Counter Timer Upper Register */ + u8 resv6[0x3]; + u8 ubg2; /* 0x1c Counter Timer Lower Register */ + u8 resv7[0x17]; + u8 uip; /* 0x34 Input Port Register */ + u8 resv8[0x3]; + u8 uop1; /* 0x38 Output Port Set Register */ + u8 resv9[0x3]; + u8 uop0; /* 0x3c Output Port Reset Register */ +} uart_t; + +/********************************************************************* +* Universal Asynchronous Receiver Transmitter (UART) +*********************************************************************/ +/* Bit definitions and macros for UMR */ +#define UART_UMR_BC(x) (((x)&0x03)) +#define UART_UMR_PT (0x04) +#define UART_UMR_PM(x) (((x)&0x03)<<3) +#define UART_UMR_ERR (0x20) +#define UART_UMR_RXIRQ (0x40) +#define UART_UMR_RXRTS (0x80) +#define UART_UMR_SB(x) (((x)&0x0F)) +#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */ +#define UART_UMR_TXRTS (0x20) /* Transmit RTS */ +#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */ +#define UART_UMR_PM_MULTI_ADDR (0x1C) +#define UART_UMR_PM_MULTI_DATA (0x18) +#define UART_UMR_PM_NONE (0x10) +#define UART_UMR_PM_FORCE_HI (0x0C) +#define UART_UMR_PM_FORCE_LO (0x08) +#define UART_UMR_PM_ODD (0x04) +#define UART_UMR_PM_EVEN (0x00) +#define UART_UMR_BC_5 (0x00) +#define UART_UMR_BC_6 (0x01) +#define UART_UMR_BC_7 (0x02) +#define UART_UMR_BC_8 (0x03) +#define UART_UMR_CM_NORMAL (0x00) +#define UART_UMR_CM_ECH (0x40) +#define UART_UMR_CM_LOCAL_LOOP (0x80) +#define UART_UMR_CM_REMOTE_LOOP (0xC0) +#define UART_UMR_SB_STOP_BITS_1 (0x07) +#define UART_UMR_SB_STOP_BITS_15 (0x08) +#define UART_UMR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for USR */ +#define UART_USR_RXRDY (0x01) +#define UART_USR_FFULL (0x02) +#define UART_USR_TXRDY (0x04) +#define UART_USR_TXEMP (0x08) +#define UART_USR_OE (0x10) +#define UART_USR_PE (0x20) +#define UART_USR_FE (0x40) +#define UART_USR_RB (0x80) + +/* Bit definitions and macros for UCSR */ +#define UART_UCSR_TCS(x) (((x)&0x0F)) +#define UART_UCSR_RCS(x) (((x)&0x0F)<<4) +#define UART_UCSR_RCS_SYS_CLK (0xD0) +#define UART_UCSR_RCS_CTM16 (0xE0) +#define UART_UCSR_RCS_CTM (0xF0) +#define UART_UCSR_TCS_SYS_CLK (0x0D) +#define UART_UCSR_TCS_CTM16 (0x0E) +#define UART_UCSR_TCS_CTM (0x0F) + +/* Bit definitions and macros for UCR */ +#define UART_UCR_RXC(x) (((x)&0x03)) +#define UART_UCR_TXC(x) (((x)&0x03)<<2) +#define UART_UCR_MISC(x) (((x)&0x07)<<4) +#define UART_UCR_NONE (0x00) +#define UART_UCR_STOP_BREAK (0x70) +#define UART_UCR_START_BREAK (0x60) +#define UART_UCR_BKCHGINT (0x50) +#define UART_UCR_RESET_ERROR (0x40) +#define UART_UCR_RESET_TX (0x30) +#define UART_UCR_RESET_RX (0x20) +#define UART_UCR_RESET_MR (0x10) +#define UART_UCR_TX_DISABLED (0x08) +#define UART_UCR_TX_ENABLED (0x04) +#define UART_UCR_RX_DISABLED (0x02) +#define UART_UCR_RX_ENABLED (0x01) + +/* Bit definitions and macros for UIPCR */ +#define UART_UIPCR_CTS (0x01) +#define UART_UIPCR_COS (0x10) + +/* Bit definitions and macros for UACR */ +#define UART_UACR_IEC (0x01) + +/* Bit definitions and macros for UIMR */ +#define UART_UIMR_TXRDY (0x01) +#define UART_UIMR_RXRDY_FU (0x02) +#define UART_UIMR_DB (0x04) +#define UART_UIMR_COS (0x80) + +/* Bit definitions and macros for UISR */ +#define UART_UISR_TXRDY (0x01) +#define UART_UISR_RXRDY_FU (0x02) +#define UART_UISR_DB (0x04) +#define UART_UISR_RXFTO (0x08) +#define UART_UISR_TXFIFO (0x10) +#define UART_UISR_RXFIFO (0x20) +#define UART_UISR_COS (0x80) + +/* Bit definitions and macros for UIP */ +#define UART_UIP_CTS (0x01) + +/* Bit definitions and macros for UOP1 */ +#define UART_UOP1_RTS (0x01) + +/* Bit definitions and macros for UOP0 */ +#define UART_UOP0_RTS (0x01) +#endif /* CONFIG_MCFUART */ + /****************************************************************************/ -#endif /* mcfuart_h */ +#endif /* mcfuart_h */ diff --git a/include/asm-m68k/ptrace.h b/include/asm-m68k/ptrace.h index 75b241883f3..01535beb15d 100644 --- a/include/asm-m68k/ptrace.h +++ b/include/asm-m68k/ptrace.h @@ -28,32 +28,32 @@ #ifndef __ASSEMBLY__ struct pt_regs { - ulong d0; - ulong d1; - ulong d2; - ulong d3; - ulong d4; - ulong d5; - ulong d6; - ulong d7; - ulong a0; - ulong a1; - ulong a2; - ulong a3; - ulong a4; - ulong a5; - ulong a6; -#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249) || defined(CONFIG_M5271) - unsigned format : 4; /* frame format specifier */ - unsigned vector : 12; /* vector offset */ + ulong d0; + ulong d1; + ulong d2; + ulong d3; + ulong d4; + ulong d5; + ulong d6; + ulong d7; + ulong a0; + ulong a1; + ulong a2; + ulong a3; + ulong a4; + ulong a5; + ulong a6; +#if defined(__M68K__) + unsigned format:4; /* frame format specifier */ + unsigned vector:12; /* vector offset */ unsigned short sr; - unsigned long pc; + unsigned long pc; #else unsigned short sr; - unsigned long pc; + unsigned long pc; #endif }; -#endif /* #ifndef __ASSEMBLY__ */ +#endif /* #ifndef __ASSEMBLY__ */ -#endif /* #ifndef _M68K_PTRACE_H */ +#endif /* #ifndef _M68K_PTRACE_H */ diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h index 7a6a8c1ff1b..70dbda464c0 100644 --- a/include/asm-m68k/u-boot.h +++ b/include/asm-m68k/u-boot.h @@ -37,24 +37,36 @@ #ifndef __ASSEMBLY__ typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_mbar_base; /* base of internal registers */ - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_boot_params; /* where this board expects params */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned char bi_enetaddr[6]; /* Ethernet adress */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ - unsigned long bi_baudrate; /* Console Baudrate */ + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ + unsigned long bi_mbar_base; /* base of internal registers */ + unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ + unsigned long bi_intfreq; /* Internal Freq, in MHz */ + unsigned long bi_busfreq; /* Bus Freq, in MHz */ + unsigned long bi_baudrate; /* Console Baudrate */ + +#ifdef CONFIG_HAS_ETH1 + /* second onboard ethernet port */ + unsigned char bi_enet1addr[6]; +#endif +#ifdef CONFIG_HAS_ETH2 + /* third onboard ethernet port */ + unsigned char bi_enet2addr[6]; +#endif +#ifdef CONFIG_HAS_ETH3 + unsigned char bi_enet3addr[6]; +#endif } bd_t; -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLY__ */ -#endif /* __U_BOOT_H__ */ +#endif /* __U_BOOT_H__ */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h new file mode 100644 index 00000000000..ac529dfbc29 --- /dev/null +++ b/include/configs/M5329EVB.h @@ -0,0 +1,275 @@ +/* + * Configuation settings for the Freescale MCF5329 FireEngine board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5329EVB_H +#define _M5329EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF532x /* define processor family */ +#define CONFIG_M5329 /* define processor type */ + +#undef DEBUG + +#define CONFIG_MCFSERIAL +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ + +#define CFG_NUM_IRQS 128 + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF | \ + CFG_CMD_FLASH | \ + (CFG_CMD_LOADB | CFG_CMD_LOADS) | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO \ + ) + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_IOBASE 0xFC030000 +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#define CONFIG_MCFUART +#ifdef CONFIG_MCFUART +# define CFG_UART_PORT (0) +# define CFG_UART_BASE (0xFC060000) +#endif + +#define CONFIG_MCFRTC +#ifdef CONFIG_MCFRTC +# define CFG_MCFRTC_BASE (0xFC0A8000) +# undef RTC_DEBUG +#endif + +/* Timer */ +#define CONFIG_MCFTMR +#ifdef CONFIG_MCFTMR +# define CFG_UDELAY_BASE (0xFC070000) +# define CFG_TMR_BASE (0xFC074000) +# define CFG_TMRINTR_NO (33) +# define CFG_TMRINTR_MASK (2) +# define CFG_TMRINTR_PRI (6) +# define CFG_TIMER_PRESCALER (((CFG_CLK / 1000000) - 1) << 8) +#endif + +#undef CONFIG_MCFPIT +#ifdef CONFIG_MCFPIT +# define CFG_UDELAY_BASE (0xFC080000) +# define CFG_PIT_BASE (0xFC084000) +# define CFG_PIT_PRESCALE (6) +#endif + +#define CONFIG_MCFINTC +#ifdef CONFIG_MCFINTC +# define CFG_INTR_BASE (0xFC048000) +# define CFG_NUM_IRQ0 64 +# define CFG_NUM_IRQ1 64 +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M5329EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 2ffff;" \ + "era 0 2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x40010000 + +#define CFG_HZ 1000 +#define CFG_CLK 80000000 +#define CFG_CPU_CLK CFG_CLK * 3 + +#define CFG_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x80000000 +#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x221 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x40000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SDRAM_CFG1 0x53722730 +#define CFG_SDRAM_CFG2 0x56670000 +#define CFG_SDRAM_CTRL 0xE1092000 +#define CFG_SDRAM_EMOD 0x40010000 +#define CFG_SDRAM_MODE 0x018D0000 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#undef CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#else +# define CFG_FLASH_UNLOCK_TOUT 1000 +# define CFG_FLASH_WRITE_TOUT 1000 +#endif + +#define CFG_FLASH_BASE 0 +#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 1000 +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_IS_EMBEDDED 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - NAND Flash 16, 32, or 64MB + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x007f0001 +#define CFG_CS0_CTRL 0x00001fa0 + +#define CFG_CS1_BASE 0x1000 +#define CFG_CS1_MASK 0x001f0001 +#define CFG_CS1_CTRL 0x002A3780 + +#ifdef NANDFLASH_SIZE +#define CFG_CS2_BASE 0x00800000 +#define CFG_CS2_MASK 0x00ff0001 +#define CFG_CS2_CTRL 0x00001f60 +#endif + +#define CONFIG_UDP_CHECKSUM + +#endif /* _M5329EVB_H */ diff --git a/lib_m68k/Makefile b/lib_m68k/Makefile index 82165f098ae..03784fd84e2 100644 --- a/lib_m68k/Makefile +++ b/lib_m68k/Makefile @@ -27,7 +27,7 @@ LIB = $(obj)lib$(ARCH).a SOBJS = -COBJS = cache.o traps.o time.o board.o m68k_linux.o +COBJS = cache.o traps.o time.o interrupts.o board.o m68k_linux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 6aaf60991c6..1b515a4c599 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -221,6 +221,7 @@ static int init_func_i2c (void) */ init_fnc_t *init_sequence[] = { + get_clocks, env_init, init_baudrate, serial_init, @@ -371,6 +372,10 @@ board_init_f (ulong bootflag) */ bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */ bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ +#ifdef CFG_INIT_RAM_ADDR + bd->bi_sramstart = CFG_INIT_RAM_ADDR; /* start of SRAM memory */ + bd->bi_sramsize = CFG_INIT_RAM_END; /* size of SRAM memory */ +#endif bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ @@ -430,6 +435,10 @@ void board_init_r (gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ +#ifdef CONFIG_SERIAL_MULTI + serial_initialize(); +#endif + debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); WATCHDOG_RESET (); @@ -489,7 +498,7 @@ void board_init_r (gd_t *id, ulong dest_addr) /* * Setup trap handlers */ - trap_init (0); + trap_init (CFG_SDRAM_BASE); #if !defined(CFG_NO_FLASH) puts ("FLASH: "); @@ -562,12 +571,48 @@ void board_init_r (gd_t *id, ulong dest_addr) if (s) s = (*e) ? e + 1 : e; } +#ifdef CONFIG_HAS_ETH1 + /* handle the 2nd ethernet address */ + + s = getenv ("eth1addr"); + for (i = 0; i < 6; ++i) { + bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif +#ifdef CONFIG_HAS_ETH2 + /* handle the 3rd ethernet address */ + + s = getenv ("eth2addr"); + for (i = 0; i < 6; ++i) { + bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif + +#ifdef CONFIG_HAS_ETH3 + /* handle 4th ethernet address */ + s = getenv("eth3addr"); + for (i = 0; i < 6; ++i) { + bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif /* IP Address */ bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); WATCHDOG_RESET (); +#if defined(CONFIG_PCI) + /* + * Do pci configuration + */ + pci_init (); +#endif /** leave this here (after malloc(), environment and PCI are working) **/ /* Initialize devices */ @@ -640,15 +685,33 @@ void board_init_r (gd_t *id, ulong dest_addr) nand_init(); /* go init the NAND */ #endif -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) WATCHDOG_RESET(); +#if defined(FEC_ENET) eth_init(bd); #endif +#if defined(CONFIG_NET_MULTI) + puts ("Net: "); + eth_initialize (bd); +#endif +#endif #ifdef CONFIG_POST post_run (NULL, POST_RAM | post_bootmode_get(0)); #endif +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE) + WATCHDOG_RESET (); + puts ("PCMCIA:"); + pcmcia_init (); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + WATCHDOG_RESET (); + puts ("IDE: "); + ide_init (); +#endif /* CFG_CMD_IDE */ + #ifdef CONFIG_LAST_STAGE_INIT WATCHDOG_RESET (); /* diff --git a/lib_m68k/interrupts.c b/lib_m68k/interrupts.c new file mode 100644 index 00000000000..6b3ce8975db --- /dev/null +++ b/lib_m68k/interrupts.c @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_MCFINTC +#define NR_IRQS (CFG_NUM_IRQS) + +/* + * Interrupt vector functions. + */ +struct interrupt_action { + interrupt_handler_t *handler; + void *arg; +}; + +static struct interrupt_action irq_vecs[NR_IRQS]; + +static __inline__ unsigned short get_sr (void) +{ + unsigned short sr; + + asm volatile ("move.w %%sr,%0":"=r" (sr):); + + return sr; +} + +static __inline__ void set_sr (unsigned short sr) +{ + asm volatile ("move.w %0,%%sr"::"r" (sr)); +} + +/************************************************************************/ +/* + * Install and free an interrupt handler + */ +void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) +{ + if ((vec < 0) || (vec > NR_IRQS)) { + printf ("irq_install_handler: wrong interrupt vector %d\n", + vec); + return; + } + + irq_vecs[vec].handler = handler; + irq_vecs[vec].arg = arg; +} + +void irq_free_handler (int vec) +{ + if ((vec < 0) || (vec > NR_IRQS)) { + return; + } + + irq_vecs[vec].handler = NULL; + irq_vecs[vec].arg = NULL; +} + +void enable_interrupts (void) +{ + unsigned short sr; + + sr = get_sr (); + set_sr (sr & ~0x0700); +} + +int disable_interrupts (void) +{ + unsigned short sr; + + sr = get_sr (); + set_sr (sr | 0x0700); + + return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */ +} + +void int_handler (struct pt_regs *fp) +{ + int vec; + + vec = (fp->vector >> 2) & 0xff; + if (vec > 0x40) + vec -= 0x40; + else + return; + + if (irq_vecs[vec].handler != NULL) { + irq_vecs[vec].handler (irq_vecs[vec].arg); + } else { + printf ("\nBogus External Interrupt Vector %d\n", vec); + } +} +#endif /* CONFIG_MCFINTC */ \ No newline at end of file diff --git a/lib_m68k/time.c b/lib_m68k/time.c index 12e38f0577f..0e4efa473c7 100644 --- a/lib_m68k/time.c +++ b/lib_m68k/time.c @@ -46,13 +46,11 @@ #include #endif - static ulong timestamp; #if defined(CONFIG_M5282) || defined(CONFIG_M5271) static unsigned short lastinc; #endif - #if defined(CONFIG_M5272) /* * We use timer 3 which is running with a period of 1 us @@ -293,6 +291,171 @@ void set_timer (ulong t) } #endif +#if defined(CONFIG_MCFTMR) +#ifndef CFG_UDELAY_BASE +# error "uDelay base not defined!" +#endif + +#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK) +# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!" +#endif + +#include + +extern void dtimer_interrupt(void *not_used); +extern void dtimer_interrupt_setup(void); +extern void dtimer_interrupt_enable(void); + +void udelay(unsigned long usec) +{ + volatile dtmr_t *timerp = (dtmr_t *) (CFG_UDELAY_BASE); + uint start, now, tmp; + + while (usec > 0) { + if (usec > 65000) + tmp = 65000; + else + tmp = usec; + usec = usec - tmp; + + /* Set up TIMER 3 as timebase clock */ + timerp->tmr = DTIM_DTMR_RST_RST; + timerp->tcn = 0; + /* set period to 1 us */ + timerp->tmr = + (((CFG_CLK / 1000000) - + 1) << 8) | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR | DTIM_DTMR_RST_EN; + + start = now = timerp->tcn; + while (now < start + tmp) + now = timerp->tcn; + } +} + +void dtimer_interrupt(void *not_used) +{ + volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE); + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* check for timer interrupt asserted */ + if ((intp->iprh0 & CFG_TMRINTR_MASK) == CFG_TMRINTR_MASK) { + timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF); + timestamp++; + return; + } +} + +void timer_init(void) +{ + volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE); + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + timestamp = 0; + + timerp->tcn = 0; + timerp->trr = 0; + + /* Set up TIMER 4 as clock */ + timerp->tmr = DTIM_DTMR_RST_RST; + + /* initialize and enable timer 4 interrupt */ + irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0); + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + + timerp->tcn = 0; + timerp->trr = 1000; /* Interrupt every ms */ + + intp->imrh0 &= ~CFG_TMRINTR_MASK; + + /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ + timerp->tmr = CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | + DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN; +} + +void reset_timer(void) +{ + timestamp = 0; +} + +ulong get_timer(ulong base) +{ + return (timestamp - base); +} + +void set_timer(ulong t) +{ + timestamp = t; +} +#endif /* CONFIG_MCFTMR */ + +#if defined(CONFIG_MCFPIT) +#if !defined(CFG_PIT_BASE) +# error "CFG_PIT_BASE not defined!" +#endif + +static unsigned short lastinc; + +void udelay(unsigned long usec) +{ + volatile pit_t *timerp = (pit_t *) (CFG_UDELAY_BASE); + uint tmp; + + while (usec > 0) { + if (usec > 65000) + tmp = 65000; + else + tmp = usec; + usec = usec - tmp; + + /* Set up TIMER 3 as timebase clock */ + timerp->pcsr = PIT_PCSR_OVW; + timerp->pmr = 0; + /* set period to 1 us */ + timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN; + + timerp->pmr = tmp; + while (timerp->pcntr > 0) ; + } +} + +void timer_init(void) +{ + volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE); + timestamp = 0; + + /* Set up TIMER 4 as poll clock */ + timerp->pcsr = PIT_PCSR_OVW; + timerp->pmr = lastinc = 0; + timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN; +} + +void set_timer(ulong t) +{ + volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE); + + timestamp = 0; + timerp->pmr = lastinc = 0; +} + +ulong get_timer(ulong base) +{ + unsigned short now, diff; + volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE); + + now = timerp->pcntr; + diff = -(now - lastinc); + + timestamp += diff; + lastinc = now; + return timestamp - base; +} + +void wait_ticks(unsigned long ticks) +{ + set_timer(0); + while (get_timer(0) < ticks) ; +} +#endif /* CONFIG_MCFPIT */ /* * This function is derived from PowerPC code (read timebase as long long). diff --git a/net/eth.c b/net/eth.c index 0fc22115dc2..cefd30ff231 100644 --- a/net/eth.c +++ b/net/eth.c @@ -58,6 +58,7 @@ extern int npe_initialize(bd_t *); extern int uec_initialize(int); extern int bfin_EMAC_initialize(bd_t *); extern int atstk1000_eth_initialize(bd_t *); +extern int mcffec_initialize(bd_t*); static struct eth_device *eth_devices, *eth_current; diff --git a/rtc/Makefile b/rtc/Makefile index 96c68c0ce71..2e6f3bdddf0 100644 --- a/rtc/Makefile +++ b/rtc/Makefile @@ -31,7 +31,8 @@ COBJS = date.o \ bf5xx_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \ ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o ds3231.o \ m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \ - mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o + mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o \ + mcfrtc.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/rtc/mcfrtc.c b/rtc/mcfrtc.c new file mode 100644 index 00000000000..c7eb53fb46a --- /dev/null +++ b/rtc/mcfrtc.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2007 + * Freescale Semiconductor Tsi-Chung.Liew@freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include + +#if defined(CONFIG_MCFRTC) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +#undef RTC_DEBUG + +#ifndef CFG_MCFRTC_BASE +#error RTC_BASE is not defined! +#endif + +#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0) +#define STARTOFTIME 1970 + +void rtc_get(struct rtc_time *tmp) +{ + volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); + + int rtc_days, rtc_hrs, rtc_mins; + int tim; + + rtc_days = rtc->days; + rtc_hrs = rtc->hourmin >> 8; + rtc_mins = RTC_HOURMIN_MINUTES(rtc->hourmin); + + tim = (rtc_days * 24) + rtc_hrs; + tim = (tim * 60) + rtc_mins; + tim = (tim * 60) + rtc->seconds; + + to_tm(tim, tmp); + + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + +#ifdef RTC_DEBUG + printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif +} + +void rtc_set(struct rtc_time *tmp) +{ + volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); + + static int month_days[12] = { + 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 + }; + int days, i, months; + + if (tmp->tm_year > 2037) { + printf("Unable to handle. Exceeding integer limitation!\n"); + tmp->tm_year = 2027; + } +#ifdef RTC_DEBUG + printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + + /* calculate days by years */ + for (i = STARTOFTIME, days = 0; i < tmp->tm_year; i++) { + days += 365 + isleap(i); + } + + /* calculate days by months */ + months = tmp->tm_mon - 1; + for (i = 0; i < months; i++) { + days += month_days[i]; + + if (i == 1) + days += isleap(i); + } + + days += tmp->tm_mday - 1; + + rtc->days = days; + rtc->hourmin = (tmp->tm_hour << 8) | tmp->tm_min; + rtc->seconds = tmp->tm_sec; +} + +void rtc_reset(void) +{ + volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); + + if ((rtc->cr & RTC_CR_EN) == 0) { + printf("real-time-clock was stopped. Now starting...\n"); + rtc->cr |= RTC_CR_EN; + } + + rtc->cr |= RTC_CR_SWR; +} + +#endif /* CONFIG_MCFRTC && CFG_CMD_DATE */ -- cgit v1.3.1 From f2208fbc2eb9de3f4285bfaa021c6ebae16c9b0e Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:13:58 -0500 Subject: Header file update, clean up and cache handling Replaced immap_5329.h and m5329.h with immap.h. Included cache_invalid. Signed-off-by: TsiChungLiew --- drivers/net/mcffec.c | 66 ++++++++++++++++++++++++++-------------------------- 1 file changed, 33 insertions(+), 33 deletions(-) (limited to 'drivers') diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index d1c84caee0d..609210de19e 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007 + * (C) Copyright 2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,8 +28,7 @@ #include #include -#include -#include +#include #include #include @@ -41,17 +40,8 @@ #undef MII_DEBUG /* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -/* - NOTE: PKT_MAXBUF_SIZE must be larger or equal to PKT_MAXBLR_SIZE, - see M54455 User Manual for MAX_FL of Receive Control Register for more - description. If PKT_MAXBUF_SIZE set to 1518, the FEC bandwidth will - reduce to about 20~40% of normal bandwidth. Changing PKT_MAXBLR_SIZE - will not make any improvement on speed -*/ +#define DBUF_LENGTH 1520 +#define TX_BUF_CNT 2 #define PKT_MAXBUF_SIZE 1518 #define PKT_MINBUF_SIZE 64 #define PKT_MAXBLR_SIZE 1520 @@ -102,12 +92,6 @@ struct fec_info_s fec_info[] = { #endif }; -/* - * FEC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - int fec_send(struct eth_device *dev, volatile void *packet, int length); int fec_recv(struct eth_device *dev); int fec_init(struct eth_device *dev, bd_t * bd); @@ -166,15 +150,23 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) * Wait for ready */ j = 0; +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + icache_invalid(); +#endif while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && (j < MCFFEC_TOUT_LOOP)) { udelay(1); j++; +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + icache_invalid(); +#endif } if (j >= MCFFEC_TOUT_LOOP) { printf("TX not ready\n"); } - +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + icache_invalid(); +#endif info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; info->txbd[info->txIdx].cbd_datlen = length; info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; @@ -183,10 +175,16 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) fecp->tdar = 0x01000000; /* Descriptor polling active */ j = 0; +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + icache_invalid(); +#endif while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && (j < MCFFEC_TOUT_LOOP)) { udelay(1); j++; +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + icache_invalid(); +#endif } if (j >= MCFFEC_TOUT_LOOP) { printf("TX timeout\n"); @@ -199,6 +197,9 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) #endif /* return only status bits */ ; +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + icache_invalid(); +#endif rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; @@ -257,12 +258,6 @@ int fec_recv(struct eth_device *dev) return length; } -/************************************************************** - * - * FEC Ethernet Initialization Routine - * - *************************************************************/ - #ifdef ET_DEBUG void dbgFecRegs(struct eth_device *dev) { @@ -419,7 +414,7 @@ int fec_init(struct eth_device *dev, bd_t * bd) struct fec_info_s *info = dev->priv; volatile fec_t *fecp = (fec_t *) (info->iobase); int i; - u8 *ea; + u8 *ea = NULL; fecpin_setclear(dev, 1); @@ -549,7 +544,9 @@ int mcffec_initialize(bd_t * bis) for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { - dev = (struct eth_device *)malloc(sizeof *dev); + dev = + (struct eth_device *)memalign(CFG_CACHELINE_SIZE, + sizeof *dev); if (dev == NULL) hang(); @@ -565,16 +562,19 @@ int mcffec_initialize(bd_t * bis) /* setup Receive and Transmit buffer descriptor */ fec_info[i].rxbd = - (cbd_t *) memalign(32, (PKTBUFSRX * sizeof(cbd_t) + 31)); + (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (PKTBUFSRX * sizeof(cbd_t))); fec_info[i].txbd = - (cbd_t *) memalign(32, (TX_BUF_CNT * sizeof(cbd_t) + 31)); - fec_info[i].txbuf = (char *)memalign(32, DBUF_LENGTH + 31); + (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (TX_BUF_CNT * sizeof(cbd_t))); + fec_info[i].txbuf = + (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); #ifdef ET_DEBUG printf("rxbd %x txbd %x\n", (int)fec_info[i].rxbd, (int)fec_info[i].txbd); #endif - fec_info[i].phy_name = (char *)malloc(32); + fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); eth_register(dev); -- cgit v1.3.1 From 2bd806fe4fc23958b8f78778199e7a6e3f8f6ad5 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 23:17:36 -0500 Subject: Rename mcfserial.c. Update include header Renamed mcfserial.c to mcfuart.c. Modified Makefile for mcfuart.o from mcfserial.o. Replace immap_5329.h and m5329.h to immap.h Signed-off-by: TsiChungLiew --- drivers/serial/Makefile | 2 +- drivers/serial/mcfserial.c | 126 -------------------------------------------- drivers/serial/mcfuart.c | 127 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 128 insertions(+), 127 deletions(-) delete mode 100644 drivers/serial/mcfserial.c create mode 100644 drivers/serial/mcfuart.c (limited to 'drivers') diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 2208a08a71c..93c68dd2e08 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libserial.a -COBJS := mcfserial.o +COBJS := mcfuart.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/serial/mcfserial.c b/drivers/serial/mcfserial.c deleted file mode 100644 index a8ca78ad8ca..00000000000 --- a/drivers/serial/mcfserial.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2004, Freescale, Inc - * TsiChung Liew, Tsi-Chung.Liew@freescale.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* - * Minimal serial functions needed to use one of the uart ports - * as serial console interface. - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_MCFSERIAL -int serial_init(void) -{ - volatile uart_t *uart; - u32 counter; - - uart = (volatile uart_t *)(CFG_UART_BASE); - - /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ - uart->ucr = UART_UCR_RESET_RX; - uart->ucr = UART_UCR_RESET_TX; - uart->ucr = UART_UCR_RESET_ERROR; - uart->ucr = UART_UCR_RESET_MR; - __asm__("nop"); - - uart->uimr = 0; - - /* write to CSR: RX/TX baud rate from timers */ - uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK); - - uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE); - uart->umr = UART_UMR_SB_STOP_BITS_1; - - /* Setting up BaudRate */ - counter = (u32) (gd->bus_clk / (gd->baudrate)); - counter >>= 5; - - /* write to CTUR: divide counter upper byte */ - uart->ubg1 = (u8) ((counter & 0xff00) >> 8); - /* write to CTLR: divide counter lower byte */ - uart->ubg2 = (u8) (counter & 0x00ff); - - uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED); - - return (0); -} - -void serial_putc(const char c) -{ - volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); - - if (c == '\n') - serial_putc('\r'); - - /* Wait for last character to go. */ - while (!(uart->usr & UART_USR_TXRDY)) ; - - uart->utb = c; -} - -void serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - -int serial_getc(void) -{ - volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); - - /* Wait for a character to arrive. */ - while (!(uart->usr & UART_USR_RXRDY)) ; - return uart->urb; -} - -int serial_tstc(void) -{ - volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); - - return (uart->usr & UART_USR_RXRDY); -} - -void serial_setbrg(void) -{ - volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); - u32 counter; - - counter = ((gd->bus_clk / gd->baudrate)) >> 5; - counter++; - - /* write to CTUR: divide counter upper byte */ - uart->ubg1 = ((counter & 0xff00) >> 8); - /* write to CTLR: divide counter lower byte */ - uart->ubg2 = (counter & 0x00ff); - - uart->ucr = UART_UCR_RESET_RX; - uart->ucr = UART_UCR_RESET_TX; - - uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED; -} -#endif /* CONFIG_MCFSERIAL */ diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c new file mode 100644 index 00000000000..f54aabec268 --- /dev/null +++ b/drivers/serial/mcfuart.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew, Tsi-Chung.Liew@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Minimal serial functions needed to use one of the uart ports + * as serial console interface. + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_MCFSERIAL +int serial_init(void) +{ + volatile uart_t *uart; + u32 counter; + + uart = (volatile uart_t *)(CFG_UART_BASE); + + /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ + uart->ucr = UART_UCR_RESET_RX; + uart->ucr = UART_UCR_RESET_TX; + uart->ucr = UART_UCR_RESET_ERROR; + uart->ucr = UART_UCR_RESET_MR; + __asm__("nop"); + + uart->uimr = 0; + + /* write to CSR: RX/TX baud rate from timers */ + uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK); + + uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE); + uart->umr = UART_UMR_SB_STOP_BITS_1; + + /* Setting up BaudRate */ + counter = (u32) (gd->bus_clk / (gd->baudrate)); + counter >>= 5; + + /* write to CTUR: divide counter upper byte */ + uart->ubg1 = (u8) ((counter & 0xff00) >> 8); + /* write to CTLR: divide counter lower byte */ + uart->ubg2 = (u8) (counter & 0x00ff); + + uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED); + + return (0); +} + +void serial_putc(const char c) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + + if (c == '\n') + serial_putc('\r'); + + /* Wait for last character to go. */ + while (!(uart->usr & UART_USR_TXRDY)) ; + + uart->utb = c; +} + +void serial_puts(const char *s) +{ + while (*s) { + serial_putc(*s++); + } +} + +int serial_getc(void) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + + /* Wait for a character to arrive. */ + while (!(uart->usr & UART_USR_RXRDY)) ; + return uart->urb; +} + +int serial_tstc(void) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + + return (uart->usr & UART_USR_RXRDY); +} + +void serial_setbrg(void) +{ + volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + u32 counter; + + counter = ((gd->bus_clk / gd->baudrate)) >> 5; + counter++; + + /* write to CTUR: divide counter upper byte */ + uart->ubg1 = ((counter & 0xff00) >> 8); + /* write to CTLR: divide counter lower byte */ + uart->ubg2 = (counter & 0x00ff); + + uart->ucr = UART_UCR_RESET_RX; + uart->ucr = UART_UCR_RESET_TX; + + uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED; +} +#endif /* CONFIG_MCFSERIAL */ -- cgit v1.3.1 From 0dca874db62718e41253659e60f3a1de7eb418ce Mon Sep 17 00:00:00 2001 From: TsiChung Date: Tue, 10 Jul 2007 15:45:43 -0500 Subject: Cache update and added CFG_UNIFY_CACHE Enabled cache in cpu_init_f() for faster flash to mem allocation. Updated cache handling in start.S. Applied cache invalidate in fec_send() and fec_recv(). Added CFG_UNIFY_CACHE for CF V3 only. Signed-off-by: TsiChung --- cpu/mcf532x/cpu_init.c | 3 ++- cpu/mcf532x/start.S | 12 +++++------- drivers/net/mcffec.c | 26 ++++++++------------------ include/configs/M5329EVB.h | 26 ++++++++++++++------------ 4 files changed, 29 insertions(+), 38 deletions(-) (limited to 'drivers') diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c index b056fbe310f..32711a17443 100644 --- a/cpu/mcf532x/cpu_init.c +++ b/cpu/mcf532x/cpu_init.c @@ -113,6 +113,8 @@ void cpu_init_f(void) fbcs->cscr5 = CFG_CS5_CTRL; fbcs->csmr5 = CFG_CS5_MASK; #endif + + icache_enable(); } /* @@ -120,6 +122,5 @@ void cpu_init_f(void) */ int cpu_init_r(void) { - icache_enable(); return (0); } diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index acd34941a9b..ac44aaabec7 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -270,8 +270,6 @@ icache_enable: movec %d0, %CACR /* Invalidate cache */ move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ movec %d0, %ACR0 /* Enable cache */ - move.l #(CFG_CS0_BASE + 0x0000), %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ move.l #0x80000200, %d0 /* Setup cache mask */ movec %d0, %CACR /* Enable cache */ @@ -284,11 +282,11 @@ icache_enable: .globl icache_disable icache_disable: - move.l #0x00000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ + move.l #0x01000000, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Disable cache */ clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - movec %d0, %ACR1 /* Enable cache */ + movec %d0, %ACR0 + movec %d0, %ACR1 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 moveq #0, %d0 @@ -303,7 +301,7 @@ icache_status: .globl icache_invalid icache_invalid: - move.l #0x01000000, %d0 /* Setup cache mask */ + move.l #0x81000200, %d0 /* Setup cache mask */ movec %d0, %CACR /* Enable cache */ rts diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 609210de19e..11f67218972 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -150,23 +150,15 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) * Wait for ready */ j = 0; -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) - icache_invalid(); -#endif while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && (j < MCFFEC_TOUT_LOOP)) { udelay(1); j++; -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) - icache_invalid(); -#endif } if (j >= MCFFEC_TOUT_LOOP) { printf("TX not ready\n"); } -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) - icache_invalid(); -#endif + info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; info->txbd[info->txIdx].cbd_datlen = length; info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; @@ -174,21 +166,19 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) /* Activate transmit Buffer Descriptor polling */ fecp->tdar = 0x01000000; /* Descriptor polling active */ - j = 0; -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) +#ifdef CFG_UNIFY_CACHE icache_invalid(); #endif + j = 0; while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && (j < MCFFEC_TOUT_LOOP)) { udelay(1); j++; -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) - icache_invalid(); -#endif } if (j >= MCFFEC_TOUT_LOOP) { printf("TX timeout\n"); } + #ifdef ET_DEBUG printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", __FILE__, __LINE__, __FUNCTION__, j, @@ -196,10 +186,7 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); #endif - /* return only status bits */ ; -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) - icache_invalid(); -#endif + /* return only status bits */ rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; @@ -213,6 +200,9 @@ int fec_recv(struct eth_device *dev) int length; for (;;) { +#ifdef CFG_UNIFY_CACHE + icache_invalid(); +#endif /* section 16.9.23.2 */ if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { length = -1; diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index c90773c5011..d1ac3400481 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -47,18 +47,20 @@ #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_FLASH | \ - (CFG_CMD_LOADB | CFG_CMD_LOADS) | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO \ - ) + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF | \ + CFG_CMD_FLASH | \ + (CFG_CMD_LOADB | CFG_CMD_LOADS) | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO \ + ) + +#define CFG_UNIFY_CACHE #define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC -- cgit v1.3.1 From 9998bd37ead85e93953559720710d3b0685c81e6 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 03:19:10 -0500 Subject: Renamed CONFIG_MCFSERIAL to CONFIG_MCFUART Signed-off-by: TsiChungLiew --- drivers/serial/mcfuart.c | 4 ++-- include/configs/M5329EVB.h | 6 ++---- 2 files changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index f54aabec268..39d4e18166b 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_MCFSERIAL +#ifdef CONFIG_MCFUART int serial_init(void) { volatile uart_t *uart; @@ -124,4 +124,4 @@ void serial_setbrg(void) uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED; } -#endif /* CONFIG_MCFSERIAL */ +#endif /* CONFIG_MCFUART */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index d1ac3400481..50be03fe378 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -39,7 +39,8 @@ #undef DEBUG -#define CONFIG_MCFSERIAL +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -84,9 +85,6 @@ # endif /* CFG_DISCOVER_PHY */ #endif -#define CONFIG_MCFUART -#define CFG_UART_PORT (0) - #define CONFIG_MCFRTC #undef RTC_DEBUG -- cgit v1.3.1 From 9e737d8476e7d6a596d16caaf6a3853a9a1190a2 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 03:30:44 -0500 Subject: Declared attributes of void __mii_init(void) as an alias for int mii_init(void) Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/mii.c | 4 +++- drivers/net/mcffec.c | 2 +- include/common.h | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c index 691b14459b7..68dc04fd9a9 100644 --- a/board/freescale/m5329evb/mii.c +++ b/board/freescale/m5329evb/mii.c @@ -203,7 +203,9 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -void mii_init(void) +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) { volatile fec_t *fecp; struct fec_info_s *info; diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 11f67218972..fde1aaecb62 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -101,7 +101,7 @@ void fec_reset(struct eth_device *dev); extern int fecpin_setclear(struct eth_device *dev, int setclear); #ifdef CFG_DISCOVER_PHY -extern void mii_init(void); +extern void __mii_init(void); extern uint mii_send(uint mii_cmd); extern int mii_discover_phy(struct eth_device *dev); extern int mcffec_miiphy_read(char *devname, unsigned char addr, diff --git a/include/common.h b/include/common.h index 23f93907ee4..a1a329071a3 100644 --- a/include/common.h +++ b/include/common.h @@ -539,7 +539,7 @@ ulong bootcount_load (void); #define BOOTCOUNT_MAGIC 0xB001C041 /* $(CPU)/.../ */ -void mii_init (void); +/*void mii_init (void);*/ /* $(CPU)/.../lcd.c */ ulong lcd_setmem (ulong); -- cgit v1.3.1 From 8d1d66af54d305de29d0bbf4aa8c9e6375f7f731 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 03:55:21 -0500 Subject: Added uart_gpio_conf() in serial_init(), seperated uart port configuration from cpu_init() to uart_gpio_conf() Signed-off-by: TsiChungLiew --- cpu/mcf532x/cpu_init.c | 35 +++++++++++++++++++++-------------- drivers/serial/mcfuart.c | 4 ++++ 2 files changed, 25 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c index 32711a17443..5a26ae0317a 100644 --- a/cpu/mcf532x/cpu_init.c +++ b/cpu/mcf532x/cpu_init.c @@ -60,20 +60,6 @@ void cpu_init_f(void) scm2->pacrg = 0; scm1->pacrh = 0; - /* Setup Ports: */ - switch (CFG_UART_PORT) { - case 0: - gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); - break; - case 1: - gpio->par_uart = - (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); - break; - case 2: - gpio->par_uart = (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); - break; - } - /* Port configuration */ gpio->par_cs = 0x3E; @@ -124,3 +110,24 @@ int cpu_init_r(void) { return (0); } + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + break; + case 1: + gpio->par_uart = + (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + break; + case 2: + gpio->par_timer &= 0x0F; + gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); + break; + } +} + diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index 39d4e18166b..bc7077de79e 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -34,6 +34,8 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_MCFUART +extern void uart_port_conf(void); + int serial_init(void) { volatile uart_t *uart; @@ -41,6 +43,8 @@ int serial_init(void) uart = (volatile uart_t *)(CFG_UART_BASE); + uart_port_conf(); + /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ uart->ucr = UART_UCR_RESET_RX; uart->ucr = UART_UCR_RESET_TX; -- cgit v1.3.1 From 936b3e69b667c3eb9a61ece4e78647d3fce9fc2a Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:44 -0500 Subject: pciauto_setup_device bars_num fix Passing bars_num=0 to pciauto_setup_device should assign no bars. Signed-off-by: Ed Swarthout Acked-by: Shinya Kuribayashi Acked-by: Andy Fleming --- drivers/pci_auto.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index a3c609ba49c..2378553be5a 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -94,7 +94,7 @@ void pciauto_setup_device(struct pci_controller *hose, pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; - for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) { + for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) { /* Tickle the BAR and get the response */ pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); pci_hose_read_config_dword(hose, dev, bar, &bar_response); -- cgit v1.3.1 From 2e4d94f1e3c2961428967a33b6ff2520568391b3 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:45 -0500 Subject: fsl_pci_init cleanup. Do not enable normal errors created during probe (master abort, perr, and pcie Invalid Configuration access). Add CONFIG_PCI_NOSCAN board option to prevent bus scan. Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- drivers/fsl_pci_init.c | 46 +++++++++++++++------------------------------ include/asm-ppc/processor.h | 2 +- 2 files changed, 16 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 1d1f6df997a..1084dc6b787 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -15,7 +15,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#define DEBUG + #include #ifdef CONFIG_FSL_PCI_INIT @@ -93,7 +93,11 @@ fsl_pci_init(struct pci_controller *hose) hose->current_busno = hose->first_busno; pci->pedr = 0xffffffff; /* Clear any errors */ - pci->peer = 0xffffffff; /* Enable Error Interupts */ + pci->peer = ~0x20140; /* Enable All Error Interupts except + * - Master abort (pci) + * - Master PERR (pci) + * - ICCA (PCIe) + */ pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32); temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); @@ -108,7 +112,7 @@ fsl_pci_init(struct pci_controller *hose) if (!enabled) { debug("....PCIE link error. Skipping scan." - "LTSSM=0x%02x\n", temp16); + "LTSSM=0x%02x\n", ltssm); hose->last_busno = hose->first_busno; return; } @@ -118,61 +122,41 @@ fsl_pci_init(struct pci_controller *hose) #ifdef DEBUG pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); neg_link_w = (temp16 & 0x3f0 ) >> 4; - debug("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", + printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", ltssm, neg_link_w); #endif hose->current_busno++; /* Start scan with secondary */ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); - } else { -#if 0 -/* done in pci_hose_config_device() */ - pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); - temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, temp16); - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); -#endif } /* Call setup to allocate PCSRBAR window */ pciauto_setup_device(hose, dev, 1, hose->pci_mem, hose->pci_prefetch, hose->pci_io); - +#ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); if ( bridge ) { /* update limit regs and subordinate busno */ pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); } +#else + hose->last_busno = hose->current_busno; +#endif /* Clear all error indications */ - if (pci->pme_msg_det && pci->pme_msg_det != 0xffffffff) { - debug("pci_fsl_init: pme_msg_det@%x=%x. Clearing\n", - &pci->pme_msg_det, pci->pme_msg_det); - pci->pme_msg_det = 0xffffffff; - } - - if (pci->pedr) { - debug("pci_fsl_init: pedr@%x=%x. Clearing\n", - &pci->pedr, pci->pedr); - pci->pedr = 0xffffffff; - } + pci->pme_msg_det = 0xffffffff; + pci->pedr = 0xffffffff; pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); if (temp16) { - debug("pci_fsl_init: PCI_DSR@%x=%x. Clearing\n", - PCI_DSR, temp16); pci_hose_write_config_word(hose, dev, - PCI_DSR, 0xffff); + PCI_DSR, 0xffff); } pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); if (temp16) { - debug("pci_fsl_init: PCI_SEC_STATUS@%x=%x. Clearing\n", - PCI_SEC_STATUS, temp16); pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); } } diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index b806cc09f1f..9be5a279e26 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -532,7 +532,7 @@ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) -#define MSSCR0 SPRN_MSSCRO +#define MSSCR0 SPRN_MSSCR0 #endif #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR -- cgit v1.3.1 From be5d72d10d47609326226225181e301fb9a33b58 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 13 Aug 2007 21:57:53 +0200 Subject: Minor coding style cleanup. Update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 74 +++++++++++++++++++++++++++++++++++++++++++++ board/cm5200/cm5200.c | 6 ++-- board/cm5200/cm5200.h | 2 +- board/cm5200/cmd_cm5200.c | 2 +- doc/README.generic_usb_ohci | 5 +-- drivers/nand/nand_util.c | 10 +++--- drivers/usb_ohci.c | 11 ------- include/configs/cm5200.h | 21 +------------ libfdt/fdt_ro.c | 1 - 9 files changed, 86 insertions(+), 46 deletions(-) (limited to 'drivers') diff --git a/CHANGELOG b/CHANGELOG index 1228908a5ad..57299b65f2d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,53 @@ +commit a08458303e7f9db67f296980036d3292c35cb45c +Author: Haavard Skinnemoen +Date: Fri Jun 29 18:38:51 2007 +0200 + + atmel_mci: Fix data timeout value + + Calculate the data timeout based on values from the CSD instead of + just using a hardcoded DTOR value. This is a backport of a similar fix + in BSP 2.0, with one additional fix: the DTOCYC value is rounded up + instead of down. + + Signed-off-by: Haavard Skinnemoen + +commit 0ba8eed28b575626b17e0a7882f923b83e0d7584 +Author: Haavard Skinnemoen +Date: Mon Aug 13 17:22:31 2007 +0200 + + AVR32: Include instead of + + include/asm-avr32/div64.h was recently moved to include/div64.h, but + cpu/at32ap/interrupts.c wasn't properly updated (an earlier version of + the patch was merged perhaps?) + + This patch updates cpu/at32ap/interrupts.c so that the avr32 port + compiles again. + + Signed-off-by: Haavard Skinnemoen + +commit f0d1246ed7cb5a88522244c596d7ae7e6f161283 +Author: Haavard Skinnemoen +Date: Wed Jun 27 13:34:26 2007 +0200 + + atmel_mci: Use 512 byte blocksize if possible + + Instead of always using the largest blocksize the card supports, check + if it can support smaller block sizes and use 512 bytes if possible. + Most cards do support this, and other parts of u-boot seem to have + trouble with block sizes different from 512 bytes. + + Also enable underrun/overrun protection. + + Signed-off-by: Haavard Skinnemoen + Acked-by: Hans-Christian Egtvedt + +commit 9986bc3e40e899bea372a99a2bca4071bdf2e24b +Author: Wolfgang Denk +Date: Sun Aug 12 21:34:50 2007 +0200 + + Update CHANGELOG + commit 77d19a8bf3b0b1e401cb9f23c81e2ef419705c1a Author: Wolfgang Denk Date: Sun Aug 12 21:34:34 2007 +0200 @@ -3928,6 +3978,30 @@ Date: Fri Jan 5 09:15:34 2007 +0100 Signed-off-by Dan Malek, +commit f2134f8e9eb006bdcd729e89f309c07b2fa45180 +Author: Haavard Skinnemoen +Date: Wed May 2 13:31:53 2007 +0200 + + macb: Don't restart autonegotiation if we already have link + + Rework macb_phy_init so that it doesn't attempt to re-negotiate if the + link is already up. + + Signed-off-by: Haavard Skinnemoen + +commit 04fcb5d38bc90779cd9a710d60702075986f0e29 +Author: Haavard Skinnemoen +Date: Wed May 2 13:22:38 2007 +0200 + + macb: Introduce a few barriers when dealing with DMA descriptors + + There were a few theoretical possibilities that the compiler might + optimize away DMA descriptor reads and/or writes and thus cause + synchronization problems with the hardware. Insert barriers where + we depend on reads/writes actually hitting memory. + + Signed-off-by: Haavard Skinnemoen + commit ffa621a0d12a1ccd81c936c567f8917a213787a8 Author: Andy Fleming Date: Sat Feb 24 01:08:13 2007 -0600 diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index 6804e33c27e..b74ac08bce3 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -122,7 +122,7 @@ long int initdram(int board_type) mem_conf_t *mem_conf; mem_conf = get_mem_config(board_type); - + /* configure SDRAM start/end for detection */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ @@ -303,7 +303,7 @@ int checkboard(void) hw_id_t hw_id_tmp; char module_name_tmp[MODULE_NAME_MAXLEN] = ""; - /* + /* * We need I2C to access HW ID data from EEPROM, so we call i2c_init() * here despite the fact that it will be called again later on. We * also use a little trick to silence I2C-related output. @@ -321,7 +321,7 @@ int checkboard(void) else printf("Board: unrecognized cm5200 module (%s)\n", module_name_tmp); - + return 0; } diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h index a6cbc88f47c..b2ea5ce0d8a 100644 --- a/board/cm5200/cm5200.h +++ b/board/cm5200/cm5200.h @@ -138,7 +138,7 @@ static char **hw_id_list[] = { cmu1_qa_hw_id, }; -/* indices to the above list - keep in sync */ +/* indices to the above list - keep in sync */ enum { CM1_QA, CM11_QA, diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c index fd9b914ae3d..513c3655372 100644 --- a/board/cm5200/cmd_cm5200.c +++ b/board/cm5200/cmd_cm5200.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2007 Markus Kappeler * - * Adapted for U-Boot 1.2 by Piotr Kruszynski + * Adapted for U-Boot 1.2 by Piotr Kruszynski * * See file CREDITS for list of people who contributed to this * project. diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index c343dfdf90a..494dd1f5d92 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -41,7 +41,7 @@ mpc5xxx. For these the config option CFG_OHCI_BE_CONTROLLER -needs to be defined. +needs to be defined. PCI Controllers @@ -55,6 +55,3 @@ PCI Controllers need to do byte swapping on register accesses, so they should to define: CFG_OHCI_SWAP_REG_ACCESS - - - diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c index aee87270390..cf05043c0af 100644 --- a/drivers/nand/nand_util.c +++ b/drivers/nand/nand_util.c @@ -209,7 +209,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) } if (!opts->quiet) { - unsigned long long n =(unsigned long long) + unsigned long long n =(unsigned long long) (erase.addr+meminfo->erasesize-opts->offset) * 100; int percent = (int)do_div(n, erase_length); @@ -476,8 +476,8 @@ int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts) imglen -= readlen; if (!opts->quiet) { - unsigned long long n = (unsigned long long) - (opts->length-imglen) * 100; + unsigned long long n = (unsigned long long) + (opts->length-imglen) * 100; int percent = (int)do_div(n, opts->length); /* output progress message only at whole percent * steps to reduce the number of messages printed @@ -651,8 +651,8 @@ int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts) } if (!opts->quiet) { - unsigned long long n = (unsigned long long) - (opts->length-imglen) * 100; + unsigned long long n = (unsigned long long) + (opts->length-imglen) * 100; int percent = (int)do_div(n ,opts->length); /* output progress message only at whole percent * steps to reduce the number of messages printed diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index d6b745fadd6..f0a37b20a71 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -132,8 +132,6 @@ int got_rhsc; /* device which was disconnected */ struct usb_device *devgone; - - /*-------------------------------------------------------------------------*/ /* AMD-756 (D2 rev) reports corrupt register contents in some cases. @@ -157,7 +155,6 @@ static inline u32 roothub_status (struct ohci *hc) static u32 roothub_portstatus (struct ohci *hc, int i) { return read_roothub (hc, portstatus [i], 0xffe0fce0); } - /* forward declaration */ static int hc_interrupt (void); static void @@ -412,8 +409,6 @@ static void ohci_dump (ohci_t *controller, int verbose) ep_print_int_eds (controller, "hcca"); dbg ("hcca frame #%04x", controller->hcca->frame_no); ohci_dump_roothub (controller, 1); -} - #endif /* DEBUG */ @@ -701,7 +696,6 @@ static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed, } } - /* unlink an ed from one of the HC chains. * just the link to the ed is unlinked. * the link from the ed still points to another operational ed or 0 @@ -759,7 +753,6 @@ static int ep_unlink (ohci_t *ohci, ed_t *edi) return 0; } - /*-------------------------------------------------------------------------*/ /* add/reinit an endpoint; this should be done once at the @@ -939,7 +932,6 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf * Done List handling functions *-------------------------------------------------------------------------*/ - /* calculate the transfer length and update the urb */ static void dl_transfer_length(td_t * td) @@ -951,7 +943,6 @@ static void dl_transfer_length(td_t * td) tdBE = m32_swap (td->hwBE); tdCBP = m32_swap (td->hwCBP); - if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { if (tdBE != 0) { @@ -1094,7 +1085,6 @@ static __u8 root_hub_dev_des[] = 0x01 /* __u8 bNumConfigurations; */ }; - /* Configuration descriptor */ static __u8 root_hub_config_des[] = { @@ -1172,7 +1162,6 @@ static unsigned char root_hub_str_index1[] = /* Hub class-specific descriptor is constructed dynamically */ - /*-------------------------------------------------------------------------*/ #define OK(x) len = (x); break diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index 56c0ecb4d97..d554348021f 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -31,7 +31,6 @@ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_CM5200 1 /* ... on CM5200 platform */ - /* * Supported commands */ @@ -60,7 +59,6 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */ - /* * Ethernet configuration */ @@ -71,7 +69,6 @@ #define CONFIG_MISC_INIT_R 1 #define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ - /* * POST support */ @@ -80,11 +77,9 @@ /* List of I2C addresses to be verified by POST */ #define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM } - /* display image timestamps */ #define CONFIG_TIMESTAMP 1 - /* * Autobooting */ @@ -137,19 +132,16 @@ "" #define CONFIG_BOOTCOMMAND "run flash_flash" - /* * Low level configuration */ - /* * Clock configuration */ #define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ #define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ - /* * Memory map */ @@ -184,7 +176,7 @@ */ #define CFG_FLASH_CFI 1 #define CFG_FLASH_CFI_DRIVER 1 -#define CFG_FLASH_BASE 0xfc000000 +#define CFG_FLASH_BASE 0xfc000000 /* we need these despite using CFI */ #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ @@ -215,7 +207,6 @@ #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x00000001 - /* * SDRAM configuration * settings for k4s561632E-xx75, assuming XLB = 132 MHz @@ -225,8 +216,6 @@ #define SDRAM_CONFIG1 0xE2333900 #define SDRAM_CONFIG2 0x8EE70000 - - /* * MTD configuration */ @@ -238,7 +227,6 @@ "2m(kernel),27904k(rootfs)," \ "-(config)" - /* * I2C configuration */ @@ -249,13 +237,11 @@ #define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ #define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */ - /* * RTC configuration */ #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - /* * USB configuration */ @@ -284,7 +270,6 @@ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - /* * Pin multiplexing configuration */ @@ -302,7 +287,6 @@ */ #define CFG_GPS_PORT_CONFIG 0x10559C44 - /* * Miscellaneous configurable options */ @@ -322,7 +306,6 @@ #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Various low-level settings */ @@ -334,7 +317,6 @@ #define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */ - /* * Cache Configuration */ @@ -343,7 +325,6 @@ #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif - /* * Flat Device Tree support */ diff --git a/libfdt/fdt_ro.c b/libfdt/fdt_ro.c index ffd9209b193..46d525db145 100644 --- a/libfdt/fdt_ro.c +++ b/libfdt/fdt_ro.c @@ -534,4 +534,3 @@ int fdt_get_reservemap(void *fdt, int n, struct fdt_reserve_entry *re) } #endif /* CONFIG_OF_LIBFDT */ - -- cgit v1.3.1 From 50cca8b976ec74069860208c36e64ce8f4d5e4c1 Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Sun, 12 Aug 2007 08:48:27 +0300 Subject: Add ability to take MAC address from the environment to DM9000 driver Signed-off-by: Mike Rapoport Signed-off-by: Ben Warren --- drivers/dm9000x.c | 15 +++++++++++++++ include/net.h | 23 +++++++++++++++++++++++ 2 files changed, 38 insertions(+) (limited to 'drivers') diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c index 687707627e5..78acb097ef8 100644 --- a/drivers/dm9000x.c +++ b/drivers/dm9000x.c @@ -302,6 +302,21 @@ eth_init(bd_t * bd) /* Set Node address */ for (i = 0; i < 6; i++) ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); + + if (!is_zero_ether_addr(bd->bi_enetaddr) && + !is_mutlicast_ether_addr(bd->bi_enetaddr)) { + /* try reading from environment */ + u8 i; + char *s, *e; + s = getenv ("ethaddr"); + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? + simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + } + printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0], bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]); diff --git a/include/net.h b/include/net.h index 96719480097..aa58e333a62 100644 --- a/include/net.h +++ b/include/net.h @@ -435,6 +435,29 @@ static inline void NetCopyLong(ulong *to, ulong *from) memcpy((void*)to, (void*)from, sizeof(ulong)); } +/** + * is_zero_ether_addr - Determine if give Ethernet address is all zeros. + * @addr: Pointer to a six-byte array containing the Ethernet address + * + * Return true if the address is all zeroes. + */ +static inline int is_zero_ether_addr(const u8 *addr) +{ + return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]); +} + +/** + * is_multicast_ether_addr - Determine if the Ethernet address is a multicast. + * @addr: Pointer to a six-byte array containing the Ethernet address + * + * Return true if the address is a multicast address. + * By definition the broadcast address is also a multicast address. + */ +static inline int is_multicast_ether_addr(const u8 *addr) +{ + return (0x01 & addr[0]); +} + /* Convert an IP address to a string */ extern void ip_to_string (IPaddr_t x, char *s); -- cgit v1.3.1 From 53a5c424bf8655b7b4e2c305a441963259a26a81 Mon Sep 17 00:00:00 2001 From: David Updegraff Date: Mon, 11 Jun 2007 10:41:07 -0500 Subject: multicast tftp: RFC2090 Implemented IETF RFC2090, Multicast TFTP. Initial implementation on Realtek RTL8139 and Freescale TSEC. Signed-off-by: David Updegraff Signed-off-by: Ben Warren --- README | 10 +++ drivers/rtl8139.c | 7 ++ drivers/tsec.c | 48 +++++++++++ include/net.h | 11 ++- net/eth.c | 45 +++++++++++ net/net.c | 8 ++ net/tftp.c | 238 ++++++++++++++++++++++++++++++++++++++++++++++++++++-- 7 files changed, 360 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/README b/README index 6af6aaa02f1..291b3046889 100644 --- a/README +++ b/README @@ -1066,6 +1066,16 @@ The following options need to be configured: Defines a default value for theIP address of a TFTP server to contact when using the "tftboot" command. +- Multicast TFTP Mode: + CONFIG_MCAST_TFTP + + Defines whether you want to support multicast TFTP as per + rfc-2090; for example to work with atftp. Lets lots of targets + tftp down the same boot image concurrently. Note: the ethernet + driver in use must provide a function: mcast() to join/leave a + multicast group. + + CONFIG_BOOTP_RANDOM_DELAY - BOOTP Recovery Mode: CONFIG_BOOTP_RANDOM_DELAY diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index 9045523a312..3e259b6b1ba 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -193,6 +193,10 @@ static void rtl_reset(struct eth_device *dev); static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length); static int rtl_poll(struct eth_device *dev); static void rtl_disable(struct eth_device *dev); +#ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */ +static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set) + { return (0); } +#endif static struct pci_device_id supported[] = { {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, @@ -228,6 +232,9 @@ int rtl8139_initialize(bd_t *bis) dev->halt = rtl_disable; dev->send = rtl_transmit; dev->recv = rtl_poll; +#ifdef CONFIG_MCAST_TFTP + dev->mcast = rtl_bcast_addr; +#endif eth_register (dev); diff --git a/drivers/tsec.c b/drivers/tsec.c index c0111234940..fd21ed4edc4 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -129,6 +129,9 @@ static int tsec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value); static int tsec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value); +#ifdef CONFIG_MCAST_TFTP +static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); +#endif /* Initialize device structure. Returns success if PHY * initialization succeeded (i.e. if it recognizes the PHY) @@ -167,6 +170,9 @@ int tsec_initialize(bd_t * bis, int index, char *devname) dev->halt = tsec_halt; dev->send = tsec_send; dev->recv = tsec_recv; +#ifdef CONFIG_MCAST_TFTP + dev->mcast = tsec_mcast_addr; +#endif /* Tell u-boot to get the addr from the env */ for (i = 0; i < 6; i++) @@ -1539,4 +1545,46 @@ static int tsec_miiphy_write(char *devname, unsigned char addr, #endif +#ifdef CONFIG_MCAST_TFTP + +/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ + +/* Set the appropriate hash bit for the given addr */ + +/* The algorithm works like so: + * 1) Take the Destination Address (ie the multicast address), and + * do a CRC on it (little endian), and reverse the bits of the + * result. + * 2) Use the 8 most significant bits as a hash into a 256-entry + * table. The table is controlled through 8 32-bit registers: + * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is + * gaddr7. This means that the 3 most significant bits in the + * hash index which gaddr register to use, and the 5 other bits + * indicate which bit (assuming an IBM numbering scheme, which + * for PowerPC (tm) is usually the case) in the tregister holds + * the entry. */ +static int +tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) +{ + struct tsec_private *priv = privlist[1]; + volatile tsec_t *regs = priv->regs; + volatile u32 *reg_array, value; + u8 result, whichbit, whichreg; + + result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); + whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ + whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ + value = (1 << (31-whichbit)); + + reg_array = &(regs->hash.gaddr0); + + if (set) { + reg_array[whichreg] |= value; + } else { + reg_array[whichreg] &= ~value; + } + return 0; +} +#endif /* Multicast TFTP ? */ + #endif /* CONFIG_TSEC_ENET */ diff --git a/include/net.h b/include/net.h index aa58e333a62..603452ab328 100644 --- a/include/net.h +++ b/include/net.h @@ -99,10 +99,12 @@ struct eth_device { int state; int (*init) (struct eth_device*, bd_t*); - int (*send) (struct eth_device*, volatile void* pachet, int length); + int (*send) (struct eth_device*, volatile void* packet, int length); int (*recv) (struct eth_device*); void (*halt) (struct eth_device*); - +#ifdef CONFIG_MCAST_TFTP + int (*mcast) (struct eth_device*, u32 ip, u8 set); +#endif struct eth_device *next; void *priv; }; @@ -124,6 +126,11 @@ extern int eth_rx(void); /* Check for received packets */ extern void eth_halt(void); /* stop SCC */ extern char *eth_get_name(void); /* get name of current device */ +#ifdef CONFIG_MCAST_TFTP +int eth_mcast_join( IPaddr_t mcast_addr, u8 join); +u32 ether_crc (size_t len, unsigned char const *p); +#endif + /**********************************************************************/ /* diff --git a/net/eth.c b/net/eth.c index c8f92a52634..9ccbccac0fb 100644 --- a/net/eth.c +++ b/net/eth.c @@ -353,6 +353,51 @@ void eth_set_enetaddr(int num, char *addr) { memcpy(dev->enetaddr, enetaddr, 6); } +#ifdef CONFIG_MCAST_TFTP +/* Multicast. + * mcast_addr: multicast ipaddr from which multicast Mac is made + * join: 1=join, 0=leave. + */ +int eth_mcast_join( IPaddr_t mcast_ip, u8 join) +{ + u8 mcast_mac[6]; + if (!eth_current || !eth_current->mcast) + return -1; + mcast_mac[5] = htonl(mcast_ip) & 0xff; + mcast_mac[4] = (htonl(mcast_ip)>>8) & 0xff; + mcast_mac[3] = (htonl(mcast_ip)>>16) & 0x7f; + mcast_mac[2] = 0x5e; + mcast_mac[1] = 0x0; + mcast_mac[0] = 0x1; + return eth_current->mcast(eth_current, mcast_mac, join); +} + +/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c + * and this is the ethernet-crc method needed for TSEC -- and perhaps + * some other adapter -- hash tables + */ +#define CRCPOLY_LE 0xedb88320 +u32 ether_crc (size_t len, unsigned char const *p) +{ + int i; + u32 crc; + crc = ~0; + while (len--) { + crc ^= *p++; + for (i = 0; i < 8; i++) + crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); + } + /* an reverse the bits, cuz of way they arrive -- last-first */ + crc = (crc >> 16) | (crc << 16); + crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00); + crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0); + crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc); + crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa); + return crc; +} + +#endif + int eth_init(bd_t *bis) { diff --git a/net/net.c b/net/net.c index e9d77576419..2b11a136574 100644 --- a/net/net.c +++ b/net/net.c @@ -118,6 +118,10 @@ char NetOurHostName[32]={0,}; /* Our hostname */ char NetOurRootPath[64]={0,}; /* Our bootpath */ ushort NetBootFileSize=0; /* Our bootfile size in blocks */ +#ifdef CONFIG_MCAST_TFTP /* Multicast TFTP */ +IPaddr_t Mcast_addr; +#endif + /** END OF BOOTP EXTENTIONS **/ ulong NetBootFileXferSize; /* The actual transferred size of the bootfile (in bytes) */ @@ -1386,6 +1390,9 @@ NetReceive(volatile uchar * inpkt, int len) } tmp = NetReadIP(&ip->ip_dst); if (NetOurIP && tmp != NetOurIP && tmp != 0xFFFFFFFF) { +#ifdef CONFIG_MCAST_TFTP + if (Mcast_addr != tmp) +#endif return; } /* @@ -1492,6 +1499,7 @@ NetReceive(volatile uchar * inpkt, int len) } #endif + #ifdef CONFIG_NETCONSOLE nc_input_packet((uchar *)ip +IP_HDR_SIZE, ntohs(ip->udp_dst), diff --git a/net/tftp.c b/net/tftp.c index d56e30b5b5c..95fee775ec9 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -61,10 +61,43 @@ static char *tftp_filename; extern flash_info_t flash_info[]; #endif +/* 512 is poor choice for ethernet, MTU is typically 1500. + * Minus eth.hdrs thats 1468. Can get 2x better throughput with + * almost-MTU block sizes. At least try... fall back to 512 if need be. + */ +#define TFTP_MTU_BLOCKSIZE 1468 +static unsigned short TftpBlkSize=TFTP_BLOCK_SIZE; +static unsigned short TftpBlkSizeOption=TFTP_MTU_BLOCKSIZE; + +#ifdef CONFIG_MCAST_TFTP +#include +#define MTFTP_BITMAPSIZE 0x1000 +static unsigned *Bitmap; +static int PrevBitmapHole,Mapsize=MTFTP_BITMAPSIZE; +static uchar ProhibitMcast=0, MasterClient=0; +static uchar Multicast=0; +extern IPaddr_t Mcast_addr; +static int Mcast_port; +static ulong TftpEndingBlock; /* can get 'last' block before done..*/ + +static void parse_multicast_oack(char *pkt,int len); + +static void +mcast_cleanup(void) +{ + if (Mcast_addr) eth_mcast_join(Mcast_addr, 0); + if (Bitmap) free(Bitmap); + Bitmap=NULL; + Mcast_addr = Multicast = Mcast_port = 0; + TftpEndingBlock = -1; +} + +#endif /* CONFIG_MCAST_TFTP */ + static __inline__ void store_block (unsigned block, uchar * src, unsigned len) { - ulong offset = block * TFTP_BLOCK_SIZE + TftpBlockWrapOffset; + ulong offset = block * TftpBlkSize + TftpBlockWrapOffset; ulong newsize = offset + len; #ifdef CFG_DIRECT_FLASH_TFTP int i, rc = 0; @@ -90,6 +123,10 @@ store_block (unsigned block, uchar * src, unsigned len) { (void)memcpy((void *)(load_addr + offset), src, len); } +#ifdef CONFIG_MCAST_TFTP + if (Multicast) + ext2_set_bit(block, Bitmap); +#endif if (NetBootFileXferSize < newsize) NetBootFileXferSize = newsize; @@ -108,6 +145,13 @@ TftpSend (void) int len = 0; volatile ushort *s; +#ifdef CONFIG_MCAST_TFTP + /* Multicast TFTP.. non-MasterClients do not ACK data. */ + if (Multicast + && (TftpState == STATE_DATA) + && (MasterClient == 0)) + return; +#endif /* * We will always be sending some sort of packet, so * cobble together the packet headers now. @@ -132,11 +176,30 @@ TftpSend (void) printf("send option \"timeout %s\"\n", (char *)pkt); #endif pkt += strlen((char *)pkt) + 1; + /* try for more effic. blk size */ + pkt += sprintf((char *)pkt,"blksize%c%d%c", + 0,htons(TftpBlkSizeOption),0); +#ifdef CONFIG_MCAST_TFTP + /* Check all preconditions before even trying the option */ + if (!ProhibitMcast + && (Bitmap=malloc(Mapsize)) + && eth_get_dev()->mcast) { + free(Bitmap); + Bitmap=NULL; + pkt += sprintf((char *)pkt,"multicast%c%c",0,0); + } +#endif /* CONFIG_MCAST_TFTP */ len = pkt - xp; break; - case STATE_DATA: case STATE_OACK: +#ifdef CONFIG_MCAST_TFTP + /* My turn! Start at where I need blocks I missed.*/ + if (Multicast) + TftpBlock=ext2_find_next_zero_bit(Bitmap,(Mapsize*8),0); + /*..falling..*/ +#endif + case STATE_DATA: xp = pkt; s = (ushort *)pkt; *s++ = htons(TFTP_ACK); @@ -177,8 +240,13 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) { ushort proto; ushort *s; + int i; if (dest != TftpOurPort) { +#ifdef CONFIG_MCAST_TFTP + if (Multicast + && (!Mcast_port || (dest != Mcast_port))) +#endif return; } if (TftpState != STATE_RRQ && src != TftpServerPort) { @@ -208,6 +276,24 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) #endif TftpState = STATE_OACK; TftpServerPort = src; + /* Check for 'blksize' option */ + for (i=0;i>20); } else { if (((TftpBlock - 1) % 10) == 0) { @@ -248,6 +334,11 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) TftpBlockWrap = 0; TftpBlockWrapOffset = 0; +#ifdef CONFIG_MCAST_TFTP + if (Multicast) { /* start!=1 common if mcast */ + TftpLastBlock = TftpBlock - 1; + } else +#endif if (TftpBlock != 1) { /* Assertion */ printf ("\nTFTP error: " "First block is not block 1 (%ld)\n" @@ -274,9 +365,44 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) * Acknoledge the block just received, which will prompt * the server for the next one. */ +#ifdef CONFIG_MCAST_TFTP + /* if I am the MasterClient, actively calculate what my next + * needed block is; else I'm passive; not ACKING + */ + if (Multicast) { + if (len < TftpBlkSize) { + TftpEndingBlock = TftpBlock; + } else if (MasterClient) { + TftpBlock = PrevBitmapHole = + ext2_find_next_zero_bit( + Bitmap, + (Mapsize*8), + PrevBitmapHole); + if (TftpBlock > ((Mapsize*8) - 1)) { + printf ("tftpfile too big\n"); + /* try to double it and retry */ + Mapsize<<=1; + mcast_cleanup(); + NetStartAgain (); + return; + } + TftpLastBlock = TftpBlock; + } + } +#endif TftpSend (); - if (len < TFTP_BLOCK_SIZE) { +#ifdef CONFIG_MCAST_TFTP + if (Multicast) { + if (MasterClient && (TftpBlock >= TftpEndingBlock)) { + puts ("\nMulticast tftp done\n"); + mcast_cleanup(); + NetState = NETLOOP_SUCCESS; + } + } + else +#endif + if (len < TftpBlkSize) { /* * We received the whole thing. Try to * run it. @@ -290,6 +416,9 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) printf ("\nTFTP error: '%s' (%d)\n", pkt + 2, ntohs(*(ushort *)pkt)); puts ("Starting again\n\n"); +#ifdef CONFIG_MCAST_TFTP + mcast_cleanup(); +#endif NetStartAgain (); break; } @@ -301,6 +430,9 @@ TftpTimeout (void) { if (++TftpTimeoutCount > TIMEOUT_COUNT) { puts ("\nRetry count exceeded; starting again\n"); +#ifdef CONFIG_MCAST_TFTP + mcast_cleanup(); +#endif NetStartAgain (); } else { puts ("T "); @@ -370,6 +502,7 @@ TftpStart (void) TftpState = STATE_RRQ; /* Use a pseudo-random port unless a specific port is set */ TftpOurPort = 1024 + (get_timer(0) % 3072); + #ifdef CONFIG_TFTP_PORT if ((ep = getenv("tftpdstp")) != NULL) { TftpServerPort = simple_strtol(ep, NULL, 10); @@ -382,8 +515,103 @@ TftpStart (void) /* zero out server ether in case the server ip has changed */ memset(NetServerEther, 0, 6); + /* Revert TftpBlkSize to dflt */ + TftpBlkSize = TFTP_BLOCK_SIZE; +#ifdef CONFIG_MCAST_TFTP + mcast_cleanup(); +#endif TftpSend (); } -#endif +#ifdef CONFIG_MCAST_TFTP +/* Credits: atftp project. + */ + +/* pick up BcastAddr, Port, and whether I am [now] the master-client. * + * Frame: + * +-------+-----------+---+-------~~-------+---+ + * | opc | multicast | 0 | addr, port, mc | 0 | + * +-------+-----------+---+-------~~-------+---+ + * The multicast addr/port becomes what I listen to, and if 'mc' is '1' then + * I am the new master-client so must send ACKs to DataBlocks. If I am not + * master-client, I'm a passive client, gathering what DataBlocks I may and + * making note of which ones I got in my bitmask. + * In theory, I never go from master->passive.. + * .. this comes in with pkt already pointing just past opc + */ +static void parse_multicast_oack(char *pkt, int len) +{ + int i; + IPaddr_t addr; + char *mc_adr, *port, *mc; + + mc_adr=port=mc=NULL; + /* march along looking for 'multicast\0', which has to start at least + * 14 bytes back from the end. + */ + for (i=0;i= (len-14)) /* non-Multicast OACK, ign. */ + return; + + i+=10; /* strlen multicast */ + mc_adr = pkt+i; + for (;i Date: Tue, 14 Aug 2007 00:14:25 -0500 Subject: Add support for UEC to 8568 Signed-off-by: Haiying Wang Signed-off-by: Andy Fleming --- Makefile | 3 ++ board/mpc8568mds/bcsr.c | 7 ++++ board/mpc8568mds/bcsr.h | 1 + board/mpc8568mds/mpc8568mds.c | 61 ++++++++++++++++++++++++++++++- cpu/mpc85xx/Makefile | 2 +- cpu/mpc85xx/cpu.c | 24 +++++++++++- cpu/mpc85xx/cpu_init.c | 33 +++++++++++++++++ cpu/mpc85xx/qe_io.c | 85 +++++++++++++++++++++++++++++++++++++++++++ drivers/qe/uec.c | 27 +++++++++----- drivers/qe/uec.h | 1 + drivers/qe/uec_phy.c | 14 +++---- drivers/qe/uec_phy.h | 6 +-- include/asm-ppc/global_data.h | 8 ++-- include/asm-ppc/immap_qe.h | 20 +++++++++- include/configs/MPC8568MDS.h | 56 ++++++++++++++++++++++++---- 15 files changed, 313 insertions(+), 35 deletions(-) create mode 100644 cpu/mpc85xx/qe_io.c (limited to 'drivers') diff --git a/Makefile b/Makefile index f51688961b3..a5698cf7c95 100644 --- a/Makefile +++ b/Makefile @@ -212,6 +212,9 @@ LIBS += drivers/nand_legacy/libnand_legacy.a ifeq ($(CPU),mpc83xx) LIBS += drivers/qe/qe.a endif +ifeq ($(CPU),mpc85xx) +LIBS += drivers/qe/qe.a +endif LIBS += drivers/sk98lin/libsk98lin.a LIBS += post/libpost.a post/drivers/libpostdrivers.a LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \ diff --git a/board/mpc8568mds/bcsr.c b/board/mpc8568mds/bcsr.c index 2e2e8cd18fa..aae0f98e038 100644 --- a/board/mpc8568mds/bcsr.c +++ b/board/mpc8568mds/bcsr.c @@ -47,3 +47,10 @@ void disable_8568mds_flash_write() bcsr[9] &= ~(0x01); } + +void enable_8568mds_qe_mdio() +{ + u8 *bcsr = (u8 *)(CFG_BCSR); + + bcsr[7] |= 0x01; +} diff --git a/board/mpc8568mds/bcsr.h b/board/mpc8568mds/bcsr.h index 8d4cb2f1412..aefd9bf54d3 100644 --- a/board/mpc8568mds/bcsr.h +++ b/board/mpc8568mds/bcsr.h @@ -95,5 +95,6 @@ void enable_8568mds_duart(void); void enable_8568mds_flash_write(void); void disable_8568mds_flash_write(void); +void enable_8568mds_qe_mdio(void); #endif /* __BCSR_H_ */ diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c index 23caaec72f2..818ff138a99 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/mpc8568mds/mpc8568mds.c @@ -28,9 +28,65 @@ #include #include #include +#include #include "bcsr.h" +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* GETH1 */ + {4, 10, 1, 0, 2}, /* TxD0 */ + {4, 9, 1, 0, 2}, /* TxD1 */ + {4, 8, 1, 0, 2}, /* TxD2 */ + {4, 7, 1, 0, 2}, /* TxD3 */ + {4, 23, 1, 0, 2}, /* TxD4 */ + {4, 22, 1, 0, 2}, /* TxD5 */ + {4, 21, 1, 0, 2}, /* TxD6 */ + {4, 20, 1, 0, 2}, /* TxD7 */ + {4, 15, 2, 0, 2}, /* RxD0 */ + {4, 14, 2, 0, 2}, /* RxD1 */ + {4, 13, 2, 0, 2}, /* RxD2 */ + {4, 12, 2, 0, 2}, /* RxD3 */ + {4, 29, 2, 0, 2}, /* RxD4 */ + {4, 28, 2, 0, 2}, /* RxD5 */ + {4, 27, 2, 0, 2}, /* RxD6 */ + {4, 26, 2, 0, 2}, /* RxD7 */ + {4, 11, 1, 0, 2}, /* TX_EN */ + {4, 24, 1, 0, 2}, /* TX_ER */ + {4, 16, 2, 0, 2}, /* RX_DV */ + {4, 30, 2, 0, 2}, /* RX_ER */ + {4, 17, 2, 0, 2}, /* RX_CLK */ + {4, 19, 1, 0, 2}, /* GTX_CLK */ + {1, 31, 2, 0, 3}, /* GTX125 */ + + /* GETH2 */ + {5, 10, 1, 0, 2}, /* TxD0 */ + {5, 9, 1, 0, 2}, /* TxD1 */ + {5, 8, 1, 0, 2}, /* TxD2 */ + {5, 7, 1, 0, 2}, /* TxD3 */ + {5, 23, 1, 0, 2}, /* TxD4 */ + {5, 22, 1, 0, 2}, /* TxD5 */ + {5, 21, 1, 0, 2}, /* TxD6 */ + {5, 20, 1, 0, 2}, /* TxD7 */ + {5, 15, 2, 0, 2}, /* RxD0 */ + {5, 14, 2, 0, 2}, /* RxD1 */ + {5, 13, 2, 0, 2}, /* RxD2 */ + {5, 12, 2, 0, 2}, /* RxD3 */ + {5, 29, 2, 0, 2}, /* RxD4 */ + {5, 28, 2, 0, 2}, /* RxD5 */ + {5, 27, 2, 0, 3}, /* RxD6 */ + {5, 26, 2, 0, 2}, /* RxD7 */ + {5, 11, 1, 0, 2}, /* TX_EN */ + {5, 24, 1, 0, 2}, /* TX_ER */ + {5, 16, 2, 0, 2}, /* RX_DV */ + {5, 30, 2, 0, 2}, /* RX_ER */ + {5, 17, 2, 0, 2}, /* RX_CLK */ + {5, 19, 1, 0, 2}, /* GTX_CLK */ + {1, 31, 2, 0, 3}, /* GTX125 */ + {4, 6, 3, 0, 2}, /* MDIO */ + {4, 5, 1, 0, 2}, /* MDC */ + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -50,6 +106,9 @@ int board_early_init_f (void) enable_8568mds_duart(); enable_8568mds_flash_write(); +#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) + enable_8568mds_qe_mdio(); +#endif #ifdef CFG_I2C2_OFFSET /* Enable I2C2_SCL and I2C2_SDA */ @@ -335,6 +394,6 @@ pci_init_board(void) { #ifdef CONFIG_PCI pib_init(); - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(hose); #endif } diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index ff67dcdd353..32091fa4e1d 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(CPU).a START = start.o resetvec.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o + pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 1d791c9b9b3..08e04685f59 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -280,7 +280,7 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); -#if defined(CONFIG_TSEC1) +#if defined(CONFIG_HAS_ETH0) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); if (p) memcpy(p, bd->bi_enetaddr, 6); @@ -308,6 +308,17 @@ ft_cpu_setup(void *blob, bd_t *bd) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len); if (p) memcpy(p, bd->bi_enet2addr, 6); + +#ifdef CONFIG_UEC_ETH + p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enet2addr, 6); + + p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len); + if (p) + memcpy(p, bd->bi_enet2addr, 6); + +#endif #endif #if defined(CONFIG_HAS_ETH3) @@ -318,6 +329,17 @@ ft_cpu_setup(void *blob, bd_t *bd) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len); if (p) memcpy(p, bd->bi_enet3addr, 6); + +#ifdef CONFIG_UEC_ETH + p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enet3addr, 6); + + p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len); + if (p) + memcpy(p, bd->bi_enet3addr, 6); + +#endif #endif } diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c7fe130ee0e..7b9961013c0 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -34,6 +34,29 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_QE +extern qe_iop_conf_t qe_iop_conf_tab[]; +extern void qe_config_iopin(u8 port, u8 pin, int dir, + int open_drain, int assign); +extern void qe_init(uint qe_base); +extern void qe_reset(void); + +static void config_qe_ioports(void) +{ + u8 port, pin; + int dir, open_drain, assign; + int i; + + for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { + port = qe_iop_conf_tab[i].port; + pin = qe_iop_conf_tab[i].pin; + dir = qe_iop_conf_tab[i].dir; + open_drain = qe_iop_conf_tab[i].open_drain; + assign = qe_iop_conf_tab[i].assign; + qe_config_iopin(port, pin, dir, open_drain, assign); + } +} +#endif #ifdef CONFIG_CPM2 static void config_8560_ioports (volatile immap_t * immr) @@ -181,6 +204,11 @@ void cpu_init_f (void) #if defined(CONFIG_CPM2) m8560_cpm_reset(); #endif +#ifdef CONFIG_QE + /* Config QE ioports */ + config_qe_ioports(); +#endif + } @@ -262,6 +290,11 @@ int cpu_init_r(void) #else printf("L2 cache: disabled\n"); #endif +#ifdef CONFIG_QE + uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */ + qe_init(qe_base); + qe_reset(); +#endif return 0; } diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c new file mode 100644 index 00000000000..8878bc53193 --- /dev/null +++ b/cpu/mpc85xx/qe_io.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "common.h" +#include "asm/errno.h" +#include "asm/io.h" +#include "asm/immap_85xx.h" + +#if defined(CONFIG_QE) +#define NUM_OF_PINS 32 +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +{ + u32 pin_2bit_mask; + u32 pin_2bit_dir; + u32 pin_2bit_assign; + u32 pin_1bit_mask; + u32 tmp_val; + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile par_io_t *par_io = (volatile par_io_t *) + &(im->im_gur.qe_par_io); + + /* Caculate pin location and 2bit mask and dir */ + pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); + pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); + + /* Setup the direction */ + tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \ + in_be32(&par_io[port].cpdir2) : + in_be32(&par_io[port].cpdir1); + + if (pin > (NUM_OF_PINS/2) -1) { + out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val); + } else { + out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val); + } + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Setup the open drain */ + tmp_val = in_be32(&par_io[port].cpodr); + if (open_drain) + out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val); + else + out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val); + + /* Setup the assignment */ + tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? + in_be32(&par_io[port].cppar2): + in_be32(&par_io[port].cppar1); + pin_2bit_assign = (u32)(assign + << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2)); + + /* Clear and set 2 bits mask */ + if (pin > (NUM_OF_PINS/2) - 1) { + out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cppar2, pin_2bit_assign | tmp_val); + } else { + out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cppar1, pin_2bit_assign | tmp_val); + } +} + +#endif /* CONFIG_QE */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index c416a67c832..89a72798232 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -391,17 +391,17 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode) return 0; } -static int init_mii_management_configuration(uec_t *uec_regs) +static int init_mii_management_configuration(uec_mii_t *uec_mii_regs) { uint timeout = 0x1000; u32 miimcfg = 0; - miimcfg = in_be32(&uec_regs->miimcfg); + miimcfg = in_be32(&uec_mii_regs->miimcfg); miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE; - out_be32(&uec_regs->miimcfg, miimcfg); + out_be32(&uec_mii_regs->miimcfg, miimcfg); /* Wait until the bus is free */ - while ((in_be32(&uec_regs->miimcfg) & MIIMIND_BUSY) && timeout--); + while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--); if (timeout <= 0) { printf("%s: The MII Bus is stuck!", __FUNCTION__); return -ETIMEDOUT; @@ -413,13 +413,13 @@ static int init_mii_management_configuration(uec_t *uec_regs) static int init_phy(struct eth_device *dev) { uec_private_t *uec; - uec_t *uec_regs; + uec_mii_t *umii_regs; struct uec_mii_info *mii_info; struct phy_info *curphy; int err; uec = (uec_private_t *)dev->priv; - uec_regs = uec->uec_regs; + umii_regs = uec->uec_mii_regs; uec->oldlink = 0; uec->oldspeed = 0; @@ -451,19 +451,19 @@ static int init_phy(struct eth_device *dev) mii_info->mii_id = uec->uec_info->phy_address; mii_info->dev = dev; - mii_info->mdio_read = &read_phy_reg; - mii_info->mdio_write = &write_phy_reg; + mii_info->mdio_read = &uec_read_phy_reg; + mii_info->mdio_write = &uec_write_phy_reg; uec->mii_info = mii_info; - if (init_mii_management_configuration(uec_regs)) { + if (init_mii_management_configuration(umii_regs)) { printf("%s: The MII Bus is stuck!", dev->name); err = -1; goto bus_fail; } /* get info for this PHY */ - curphy = get_phy_info(uec->mii_info); + curphy = uec_get_phy_info(uec->mii_info); if (!curphy) { printf("%s: No PHY found", dev->name); err = -1; @@ -989,6 +989,13 @@ static int uec_startup(uec_private_t *uec) /* Setup MAC interface mode */ uec_set_mac_if_mode(uec, uec_info->enet_interface); + /* Setup MII management base */ +#ifndef CONFIG_eTSEC_MDIO_BUS + uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg); +#else + uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS; +#endif + /* Setup MII master clock source */ qe_set_mii_clk_src(uec_info->uf_info.ucc_num); diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 04950264b89..c384055cebf 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -675,6 +675,7 @@ typedef struct uec_private { ucc_fast_private_t *uccf; struct eth_device *dev; uec_t *uec_regs; + uec_mii_t *uec_mii_regs; /* enet init command parameter */ uec_init_cmd_pram_t *p_init_enet_param; u32 init_enet_param_offset; diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 76fd38896a8..ca6faa6ef4e 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -60,14 +60,14 @@ void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val); /* Write value to the PHY for this device to the register at regnum, */ /* waiting until the write is done before it returns. All PHY */ /* configuration has to be done through the TSEC1 MIIM regs */ -void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) +void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) { uec_private_t *ugeth = (uec_private_t *) dev->priv; - uec_t *ug_regs; + uec_mii_t *ug_regs; enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; u32 tmp_reg; - ug_regs = ugeth->uec_regs; + ug_regs = ugeth->uec_mii_regs; /* Stop the MII management read cycle */ out_be32 (&ug_regs->miimcom, 0); @@ -87,15 +87,15 @@ void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) /* Reads from register regnum in the PHY for device dev, */ /* returning the value. Clears miimcom first. All PHY */ /* configuration has to be done through the TSEC1 MIIM regs */ -int read_phy_reg (struct eth_device *dev, int mii_id, int regnum) +int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum) { uec_private_t *ugeth = (uec_private_t *) dev->priv; - uec_t *ug_regs; + uec_mii_t *ug_regs; enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; u32 tmp_reg; u16 value; - ug_regs = ugeth->uec_regs; + ug_regs = ugeth->uec_mii_regs; /* Setting up the MII Mangement Address Register */ tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; @@ -521,7 +521,7 @@ void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val) /* Use the PHY ID registers to determine what type of PHY is attached * to device dev. return a struct phy_info structure describing that PHY */ -struct phy_info *get_phy_info (struct uec_mii_info *mii_info) +struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info) { u16 phy_reg; u32 phy_ID; diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index 9bd926ddd5a..e59a940e0dd 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -249,10 +249,10 @@ struct phy_info { void (*close) (struct uec_mii_info * mii_info); }; -struct phy_info *get_phy_info (struct uec_mii_info *mii_info); -void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, +struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info); +void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value); -int read_phy_reg (struct eth_device *dev, int mii_id, int regnum); +int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum); void mii_clear_phy_interrupt (struct uec_mii_info *mii_info); void mii_configure_phy_interrupt (struct uec_mii_info *mii_info, u32 interrupts); diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index bbaeb3f575f..1f1583a9231 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -71,16 +71,16 @@ typedef struct global_data { u32 lclk_clk; u32 ddr_clk; u32 pci_clk; +#if defined(CONFIG_MPC8360) + u32 ddr_sec_clk; +#endif /* CONFIG_MPC8360 */ +#endif #if defined(CONFIG_QE) u32 qe_clk; u32 brg_clk; uint mp_alloc_base; uint mp_alloc_top; #endif /* CONFIG_QE */ -#if defined (CONFIG_MPC8360) - u32 ddr_sec_clk; -#endif /* CONFIG_MPC8360 */ -#endif #if defined(CONFIG_MPC5xxx) unsigned long ipb_clk; unsigned long pci_clk; diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index 950b9497f8a..a16a6d3fc5f 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -281,6 +281,17 @@ typedef struct ucc_slow { u8 res4[0x200 - 0x091]; } __attribute__ ((packed)) ucc_slow_t; +typedef struct ucc_mii_mng { + u32 miimcfg; /* MII management configuration reg */ + u32 miimcom; /* MII management command reg */ + u32 miimadd; /* MII management address reg */ + u32 miimcon; /* MII management control reg */ + u32 miimstat; /* MII management status reg */ + u32 miimind; /* MII management indication reg */ + u32 ifctl; /* interface control reg */ + u32 ifstat; /* interface statux reg */ +} __attribute__ ((packed))uec_mii_t; + typedef struct ucc_ethernet { u32 maccfg1; /* mac configuration reg. 1 */ u32 maccfg2; /* mac configuration reg. 2 */ @@ -540,14 +551,21 @@ typedef struct qe_immap { u8 res14[0x300]; u8 res15[0x3A00]; u8 res16[0x8000]; /* 0x108000 - 0x110000 */ +#if defined(CONFIG_MPC8568) + u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */ + u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */ +#else u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ +#endif } __attribute__ ((packed)) qe_map_t; extern qe_map_t *qe_immr; -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC8568) +#define QE_MURAM_SIZE 0x10000UL +#elif defined(CONFIG_MPC8360) #define QE_MURAM_SIZE 0xc000UL #elif defined(CONFIG_MPC832X) #define QE_MURAM_SIZE 0x4000UL diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 5bc953adc42..dc9cb1ff545 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -28,20 +28,21 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ #define CONFIG_MPC8568 1 /* MPC8568 specific */ #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ /*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ /*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ -/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ +/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -297,6 +298,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8568@0" #define OF_SOC "soc8568@e0000000" +#define OF_QE "qe@e0080000" #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600" @@ -311,7 +313,7 @@ extern unsigned long get_clock_freq(void); #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x52 #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0,0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 @@ -340,6 +342,44 @@ extern unsigned long get_clock_freq(void); #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#ifdef CONFIG_QE +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#ifndef CONFIG_TSEC_ENET +#define CONFIG_ETHPRIME "Freescale GETH" +#endif +#define CONFIG_PHY_MODE_NEED_CHANGE +#define CONFIG_eTSEC_MDIO_BUS + +#ifdef CONFIG_eTSEC_MDIO_BUS +#define CONFIG_MIIM_ADDRESS 0xE0024520 +#endif + +#define CONFIG_UEC_ETH1 /* GETH1 */ + +#ifdef CONFIG_UEC_ETH1 +#define CFG_UEC1_UCC_NUM 0 /* UCC1 */ +#define CFG_UEC1_RX_CLK QE_CLK_NONE +#define CFG_UEC1_TX_CLK QE_CLK16 +#define CFG_UEC1_ETH_TYPE GIGA_ETH +#define CFG_UEC1_PHY_ADDR 7 +#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII +#endif + +#define CONFIG_UEC_ETH2 /* GETH2 */ + +#ifdef CONFIG_UEC_ETH2 +#define CFG_UEC2_UCC_NUM 1 /* UCC2 */ +#define CFG_UEC2_RX_CLK QE_CLK_NONE +#define CFG_UEC2_TX_CLK QE_CLK16 +#define CFG_UEC2_ETH_TYPE GIGA_ETH +#define CFG_UEC2_PHY_ADDR 1 +#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII +#endif +#endif /* CONFIG_QE */ + #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -348,13 +388,12 @@ extern unsigned long get_clock_freq(void); #endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - #ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 #endif +#if defined(CONFIG_TSEC_ENET) + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC0" @@ -460,12 +499,15 @@ extern unsigned long get_clock_freq(void); */ /* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 -- cgit v1.3.1 From 85eb5caf6b906f7ec5b54814e8c7c74f55986bb7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 14 Aug 2007 09:47:27 +0200 Subject: Coding style cleanup; rebuild CHANGELOG --- CHANGELOG | 153 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/rtl8139.c | 6 ++- net/eth.c | 8 +-- net/net.c | 2 +- net/tftp.c | 36 ++++++------- 5 files changed, 180 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/CHANGELOG b/CHANGELOG index 57299b65f2d..6ebf48725b9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,56 @@ +commit 53a5c424bf8655b7b4e2c305a441963259a26a81 +Author: David Updegraff +Date: Mon Jun 11 10:41:07 2007 -0500 + + multicast tftp: RFC2090 + + Implemented IETF RFC2090, Multicast TFTP. Initial implementation + on Realtek RTL8139 and Freescale TSEC. + + Signed-off-by: David Updegraff + Signed-off-by: Ben Warren + +commit 5d110f0aa69f065ee386ec1840dfee1e8cc46bc1 +Author: Wilson Callan +Date: Sat Jul 28 10:56:13 2007 -0400 + + New CONFIG_BOOTP_SERVERIP option + + Added CONFIG_BOOTP_SERVERIP to allow the tftp server to be different + from the bootp server + + Signed-off-by: Wilson Callan + Signed-off-by: Ben Warren + +commit 50cca8b976ec74069860208c36e64ce8f4d5e4c1 +Author: Mike Rapoport +Date: Sun Aug 12 08:48:27 2007 +0300 + + Add ability to take MAC address from the environment to DM9000 driver + + Signed-off-by: Mike Rapoport + Signed-off-by: Ben Warren + +commit be5d72d10d47609326226225181e301fb9a33b58 +Author: Wolfgang Denk +Date: Mon Aug 13 21:57:53 2007 +0200 + + Minor coding style cleanup. Update CHANGELOG. + + Signed-off-by: Wolfgang Denk + +commit cca34967cbd13ff6bd352be29e3f1cc88ab24c05 +Author: Joe Hamman +Date: Sat Aug 11 06:54:58 2007 -0500 + + Modify SBC8641D to use new Freescale PCI routines + + PCI-Express sockets 1 and 2 verified working with Intel Pro/1000 PT + adapter. + + Signed-off-by: Joe Hamman + Signde-off-by: Jon Loeliger + commit a08458303e7f9db67f296980036d3292c35cb45c Author: Haavard Skinnemoen Date: Fri Jun 29 18:38:51 2007 +0200 @@ -365,6 +418,30 @@ Date: Fri Aug 10 15:48:59 2007 +0800 Signed-off-by: Dave Liu +commit c646bba6465a45c60746d4cc1602cd06c1960f2d +Author: Joe Hamman +Date: Thu Aug 9 15:11:03 2007 -0500 + + Add support for SBC8641D. Config files. + + Add support for Wind River's SBC8641D reference board. + + Signed-off by: Joe Hamman + Acked-by: Wolfgang Denk + Acked-by: Jon Loeliger + +commit 8ac273271d57321f90505c7a51cdb1ef2113b628 +Author: Joe Hamman +Date: Thu Aug 9 15:10:53 2007 -0500 + + Add support for SBC8641D. Board files. + + Add support for Wind River's SBC8641D reference board. + + Signed-off by: Joe Hamman + Acked-by: Wolfgang Denk + Acked-by: Jon Loeliger + commit c2c0ab4aff86622b837a48a0e560351f9afafb95 Author: Stefan Roese Date: Fri Aug 10 20:34:58 2007 +0200 @@ -420,6 +497,62 @@ Date: Fri Aug 10 20:26:18 2007 +0200 Acked-by: Zach Sadecki Acked-by: Stefan Roese +commit 2e4d94f1e3c2961428967a33b6ff2520568391b3 +Author: Ed Swarthout +Date: Fri Jul 27 01:50:45 2007 -0500 + + fsl_pci_init cleanup. + + Do not enable normal errors created during probe (master abort, perr, + and pcie Invalid Configuration access). + + Add CONFIG_PCI_NOSCAN board option to prevent bus scan. + + Signed-off-by: Ed Swarthout + Acked-by: Andy Fleming + +commit 936b3e69b667c3eb9a61ece4e78647d3fce9fc2a +Author: Ed Swarthout +Date: Fri Jul 27 01:50:44 2007 -0500 + + pciauto_setup_device bars_num fix + + Passing bars_num=0 to pciauto_setup_device should assign no bars. + + Signed-off-by: Ed Swarthout + Acked-by: Shinya Kuribayashi + Acked-by: Andy Fleming + +commit cf0b185e58ca0aec8ae2b2a8804ec0ef58ee21d4 +Author: Jon Loeliger +Date: Mon Aug 6 17:39:44 2007 -0500 + + 8641hpcn: Do correct sized pointer math. + + When I rebased Ed's patch and cleaned up a few compilation + problems, I apparently rebased my brain on crack first. + Fix that by doing (char *) sized pointer math as needed. + + Signed-off-by: Jon Loeliger + +commit cfc7a7f5bb3273c9951173c788001d45118f141f +Author: Jon Loeliger +Date: Thu Aug 2 14:42:20 2007 -0500 + + cpu/86xx fixes. + + Remove rev 1 fixes. + Always set PICGCR_MODE. + Enable machine check and provide board config option + to set and handle SoC error interrupts. + + Include MSSSR0 in error message. + + Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. + + Signed-off-by: Ed Swarthout + Signed-off-by: Jon Loeliger + commit 3a6d56c20989fe27360afe743bd2a7ad4d76e48f Author: Dirk Behme Date: Thu Aug 2 17:42:08 2007 +0200 @@ -2887,6 +3020,26 @@ Date: Fri Jun 8 09:55:24 2007 +0200 Signed-off-by: Benoit Monin Signed-off-by: Stefan Roese +commit f539edc076cfe52bff919dd512ba8d7af0e22092 +Author: Vadim Bendebury +Date: Thu May 24 15:52:25 2007 -0700 + + cosmetic changes to bcm570x driver + + This is a cosmetic only changes submission. + It affects files relevant to bcm570x driver. + the commands used to generate this change was + + cd drivers + Lindent -pcs -l80 bcm570x.c bcm570x_lm.h bcm570x_mm.h tigon3.c tigon3.h + + The BMW target (the only one using this chip so far) builds cleanly, the + `before and after' generated object files for drivers/bcm570x.c and + drivers/tigon3.o are identical as reported by objdump -d + + Signed-off-by: Vadim Bendebury + Signed-off-by: Ben Warren + commit 725671ccd2cd04c9ebc50c9e5a94dd8cbade66b7 Author: Wolfgang Denk Date: Wed Jun 6 16:26:56 2007 +0200 diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index 3e259b6b1ba..23671800579 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -194,8 +194,10 @@ static int rtl_transmit(struct eth_device *dev, volatile void *packet, int lengt static int rtl_poll(struct eth_device *dev); static void rtl_disable(struct eth_device *dev); #ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */ -static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set) - { return (0); } +static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set) +{ + return (0); +} #endif static struct pci_device_id supported[] = { diff --git a/net/eth.c b/net/eth.c index 9ccbccac0fb..c2c23f6f1c3 100644 --- a/net/eth.c +++ b/net/eth.c @@ -356,12 +356,12 @@ void eth_set_enetaddr(int num, char *addr) { #ifdef CONFIG_MCAST_TFTP /* Multicast. * mcast_addr: multicast ipaddr from which multicast Mac is made - * join: 1=join, 0=leave. + * join: 1=join, 0=leave. */ int eth_mcast_join( IPaddr_t mcast_ip, u8 join) { u8 mcast_mac[6]; - if (!eth_current || !eth_current->mcast) + if (!eth_current || !eth_current->mcast) return -1; mcast_mac[5] = htonl(mcast_ip) & 0xff; mcast_mac[4] = (htonl(mcast_ip)>>8) & 0xff; @@ -372,8 +372,8 @@ int eth_mcast_join( IPaddr_t mcast_ip, u8 join) return eth_current->mcast(eth_current, mcast_mac, join); } -/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c - * and this is the ethernet-crc method needed for TSEC -- and perhaps +/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c + * and this is the ethernet-crc method needed for TSEC -- and perhaps * some other adapter -- hash tables */ #define CRCPOLY_LE 0xedb88320 diff --git a/net/net.c b/net/net.c index 2b11a136574..c47610e7455 100644 --- a/net/net.c +++ b/net/net.c @@ -1391,7 +1391,7 @@ NetReceive(volatile uchar * inpkt, int len) tmp = NetReadIP(&ip->ip_dst); if (NetOurIP && tmp != NetOurIP && tmp != 0xFFFFFFFF) { #ifdef CONFIG_MCAST_TFTP - if (Mcast_addr != tmp) + if (Mcast_addr != tmp) #endif return; } diff --git a/net/tftp.c b/net/tftp.c index 95fee775ec9..888ec987cfc 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -61,8 +61,8 @@ static char *tftp_filename; extern flash_info_t flash_info[]; #endif -/* 512 is poor choice for ethernet, MTU is typically 1500. - * Minus eth.hdrs thats 1468. Can get 2x better throughput with +/* 512 is poor choice for ethernet, MTU is typically 1500. + * Minus eth.hdrs thats 1468. Can get 2x better throughput with * almost-MTU block sizes. At least try... fall back to 512 if need be. */ #define TFTP_MTU_BLOCKSIZE 1468 @@ -145,11 +145,11 @@ TftpSend (void) int len = 0; volatile ushort *s; -#ifdef CONFIG_MCAST_TFTP +#ifdef CONFIG_MCAST_TFTP /* Multicast TFTP.. non-MasterClients do not ACK data. */ - if (Multicast - && (TftpState == STATE_DATA) - && (MasterClient == 0)) + if (Multicast + && (TftpState == STATE_DATA) + && (MasterClient == 0)) return; #endif /* @@ -179,10 +179,10 @@ TftpSend (void) /* try for more effic. blk size */ pkt += sprintf((char *)pkt,"blksize%c%d%c", 0,htons(TftpBlkSizeOption),0); -#ifdef CONFIG_MCAST_TFTP +#ifdef CONFIG_MCAST_TFTP /* Check all preconditions before even trying the option */ - if (!ProhibitMcast - && (Bitmap=malloc(Mapsize)) + if (!ProhibitMcast + && (Bitmap=malloc(Mapsize)) && eth_get_dev()->mcast) { free(Bitmap); Bitmap=NULL; @@ -244,7 +244,7 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) if (dest != TftpOurPort) { #ifdef CONFIG_MCAST_TFTP - if (Multicast + if (Multicast && (!Mcast_port || (dest != Mcast_port))) #endif return; @@ -290,7 +290,7 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) } #ifdef CONFIG_MCAST_TFTP parse_multicast_oack((char *)pkt,len-1); - if ((Multicast) && (!MasterClient)) + if ((Multicast) && (!MasterClient)) TftpState = STATE_DATA; /* passive.. */ else #endif @@ -366,14 +366,14 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) * the server for the next one. */ #ifdef CONFIG_MCAST_TFTP - /* if I am the MasterClient, actively calculate what my next - * needed block is; else I'm passive; not ACKING + /* if I am the MasterClient, actively calculate what my next + * needed block is; else I'm passive; not ACKING */ if (Multicast) { if (len < TftpBlkSize) { TftpEndingBlock = TftpBlock; } else if (MasterClient) { - TftpBlock = PrevBitmapHole = + TftpBlock = PrevBitmapHole = ext2_find_next_zero_bit( Bitmap, (Mapsize*8), @@ -398,7 +398,7 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) puts ("\nMulticast tftp done\n"); mcast_cleanup(); NetState = NETLOOP_SUCCESS; - } + } } else #endif @@ -555,7 +555,7 @@ static void parse_multicast_oack(char *pkt, int len) break; if (i >= (len-14)) /* non-Multicast OACK, ign. */ return; - + i+=10; /* strlen multicast */ mc_adr = pkt+i; for (;i Date: Tue, 14 Aug 2007 10:10:52 +0100 Subject: Add MACH_TYPE records for several AT91 boards. Merge to two at45.c files into a common file, split to at45.c and spi.c Fix spelling error in DM9161 PHY Support. Initialize at91rm9200 board (and set LED). Add PIO control for at91rm9200dk LEDs and Mux. Change dataflash partition boundaries to be compatible with Linux 2.6. Signed-off-by: Peter Pearse Signed-off-by: Ulf Samuelsson --- board/at91rm9200dk/Makefile | 2 +- common/soft_i2c.c | 2 +- cpu/arm920t/at91rm9200/Makefile | 2 +- cpu/arm920t/at91rm9200/dm9161.c | 11 +- cpu/arm920t/start.S | 93 ++++++++- drivers/dataflash.c | 279 ++++++++++++++++++++------- include/asm-arm/arch-at91rm9200/AT91RM9200.h | 139 +++++++------ include/asm-arm/mach-types.h | 69 +++++++ include/config_cmd_all.h | 1 + include/configs/at91rm9200dk.h | 5 + include/dataflash.h | 43 ++++- include/dm9161.h | 4 +- include/flash.h | 5 + 13 files changed, 516 insertions(+), 139 deletions(-) (limited to 'drivers') diff --git a/board/at91rm9200dk/Makefile b/board/at91rm9200dk/Makefile index 0fcafd9b0fc..7dfc27f0a74 100644 --- a/board/at91rm9200dk/Makefile +++ b/board/at91rm9200dk/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := at91rm9200dk.o at45.o flash.o +COBJS := at91rm9200dk.o at45.o flash.o led.o mux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/common/soft_i2c.c b/common/soft_i2c.c index 0f6e3a938d2..c5d7e205e54 100644 --- a/common/soft_i2c.c +++ b/common/soft_i2c.c @@ -29,7 +29,7 @@ #ifdef CONFIG_MPC8260 /* only valid for MPC8260 */ #include #endif -#ifdef CONFIG_AT91RM9200DK /* need this for the at91rm9200dk */ +#ifdef CONFIG_AT91RM9200 /* need this for the at91rm9200 */ #include #include #endif diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile index eaabad26a0c..ab4c52c8fb0 100644 --- a/cpu/arm920t/at91rm9200/Makefile +++ b/cpu/arm920t/at91rm9200/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a COBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \ - lxt972.o serial.o usb.o + lxt972.o serial.o usb.o spi.o SOBJS = lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm920t/at91rm9200/dm9161.c b/cpu/arm920t/at91rm9200/dm9161.c index 968f653081f..1beb6e8ba11 100644 --- a/cpu/arm920t/at91rm9200/dm9161.c +++ b/cpu/arm920t/at91rm9200/dm9161.c @@ -95,7 +95,7 @@ UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac) return TRUE; } - if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) { + if ((stat1 & DM9161_100BASE_TX_HD) && (stat2 & DM9161_100HDX)) { /*set MII for 100BaseTX and Half Duplex */ p_mac->EMAC_CFG = (p_mac->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) @@ -140,7 +140,7 @@ UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac) at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue); /* set FDX, SPD, Link, INTR masks */ IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK | - DM9161_LINK_MASK | DM9161_INTR_MASK); + DM9161_LINK_MASK | DM9161_INTR_MASK); at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue); at91rm9200_EmacDisableMDIO (p_mac); @@ -174,10 +174,11 @@ UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status) if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value)) return FALSE; - /* Set the Auto_negotiation Advertisement Register */ - /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ + /* Set the Auto_negotiation Advertisement Register */ + /* MII advertising for Next page, 100BaseTxFD and HD, */ + /* 10BaseTFD and HD, IEEE 802.3 */ PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX | - DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3; + DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3; if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar)) return FALSE; diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 346f0d09ea7..b9c364bc672 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -27,7 +27,9 @@ #include #include - +#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF) +#include +#endif /* ************************************************************************* @@ -116,6 +118,69 @@ reset: orr r0,r0,#0xd3 msr cpsr,r0 +#if CONFIG_AT91RM9200 +#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF) + bl LED_init + bl red_LED_on +#endif + +#ifdef CONFIG_BOOTBINFUNC +/* code based on entry.S from ATMEL */ +#define AT91C_BASE_CKGR 0xFFFFFC20 +#define CKGR_MOR 0 + /* Get the CKGR Base Address */ + ldr r1, =AT91C_BASE_CKGR + +/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */ +/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */ + ldr r0, =0x0000FF01 + str r0, [r1, #CKGR_MOR] + /* Add loop to compensate Main Oscillator startup time */ + ldr r0, =0x00000010 +LoopOsc: + subs r0, r0, #1 + bhi LoopOsc + /* scratch stack */ + ldr r1, =0x00204000 + /* Insure word alignment */ + bic r1, r1, #3 + /* Init stack SYS */ + mov sp, r1 + /* + * This does a lot more than just set up the memory, which + * is why it's called lowlevelinit + */ + bl lowlevelinit /* in memsetup.S */ + bl icache_enable; + /* ------------------------------------ + * Read/modify/write CP15 control register + * ------------------------------------- + * read cp15 control register (cp15 r1) in r0 + * ------------------------------------ + */ + mrc p15, 0, r0, c1, c0, 0 + /* Reset bit :Little Endian end fast bus mode */ + ldr r3, =0xC0000080 + /* Set bit :Asynchronous clock mode, Not Fast Bus */ + ldr r4, =0xC0000000 + bic r0, r0, r3 + orr r0, r0, r4 + /* write r0 in cp15 control register (cp15 r1) */ + mcr p15, 0, r0, c1, c0, 0 +#endif /* CONFIG_BOOTBINFUNC */ + /* + * relocate exeception table + */ + ldr r0, =_start + ldr r1, =0x0 + mov r2, #16 +copyex: + subs r2, r2, #1 + ldr r3, [r0], #4 + str r3, [r1], #4 + bne copyex +#endif + /* turn off the watchdog */ #if defined(CONFIG_S3C2400) # define pWTCON 0x15300000 @@ -160,6 +225,26 @@ reset: bl cpu_init_crit #endif +#ifdef CONFIG_AT91RM9200 +#ifdef CONFIG_BOOTBINFUNC +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop +#endif /* CONFIG_BOOTBINFUNC */ +#else #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ @@ -178,7 +263,7 @@ copy_loop: cmp r0, r2 /* until source end addreee [r2] */ ble copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - +#endif /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ @@ -262,7 +347,11 @@ cpu_init_crit: * find a lowlevel_init.S in your board directory. */ mov ip, lr +#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF) + +#else bl lowlevel_init +#endif mov lr, ip mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/drivers/dataflash.c b/drivers/dataflash.c index 17eb8597f8c..3b068d7125c 100644 --- a/drivers/dataflash.c +++ b/drivers/dataflash.c @@ -26,18 +26,67 @@ AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; static AT91S_DataFlash DataFlashInst; +#ifdef CONFIG_AT91SAM9260EK +int cs[][CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ + {CFG_DATAFLASH_LOGIC_ADDR_CS1, 1} +}; +#elif defined(CONFIG_AT91SAM9263EK) +int cs[][CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0} /* Logical adress, CS */ +}; +#else int cs[][CFG_MAX_DATAFLASH_BANKS] = { {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ {CFG_DATAFLASH_LOGIC_ADDR_CS3, 3} }; +#endif /*define the area offsets*/ +#if defined(CONFIG_AT91SAM9261EK) || defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AT91SAM9263EK) +#if defined(CONFIG_NEW_PARTITION) +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x00003FFF, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */ + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, /* u-boot environment */ + {0x00008400, 0x0003DDFF, FLAG_PROTECT_SET, 0, "U-Boot"}, /* u-boot code */ + {0x0003DE00, 0x00041FFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "MON"}, /* Room for alternative boot monitor */ + {0x00042000, 0x0018BFFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "OS"}, /* data area size to tune */ + {0x0018C000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "FS"}, /* data area size to tune */ +}; +#else +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0, 0x3fff, FLAG_PROTECT_SET}, /* ROM code */ + {0x4000, 0x7fff, FLAG_PROTECT_CLEAR}, /* u-boot environment */ + {0x8000, 0x37fff, FLAG_PROTECT_SET}, /* u-boot code */ + {0x38000, 0x1fffff, FLAG_PROTECT_CLEAR}, /* data area size to tune */ +}; +#endif +#elif defined(CONFIG_NEW_PARTITION) +/*define the area offsets*/ +/* Invalid partitions should be defined with start > end */ +dataflash_protect_t area_list[NB_DATAFLASH_AREA*CFG_MAX_DATAFLASH_BANKS] = { + {0x00000000, 0x000083ff, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */ + {0x00008400, 0x00020fff, FLAG_PROTECT_SET, 0, "U-Boot"}, /* u-boot code */ + {0x00021000, 0x000293ff, FLAG_PROTECT_CLEAR, 0, "Environment"}, /* u-boot environment 8Kb */ + {0x00029400, 0x00041fff, FLAG_PROTECT_INVALID, 0, ""}, /* Rest of Sector 1 */ + {0x00042000, 0x0018Bfff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "OS"}, /* data area size to tune */ + {0x0018C000, 0xffffffff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "FS"}, /* data area size to tune */ + + {0x00000000, 0xffffffff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "Data"}, /* data area */ + {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, ""}, /* Invalid */ + {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, ""}, /* Invalid */ + {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, ""}, /* Invalid */ + {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, ""}, /* Invalid */ + {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, ""}, /* Invalid */ +}; +#else dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0, 0x7fff, FLAG_PROTECT_SET}, /* ROM code */ {0x8000, 0x1ffff, FLAG_PROTECT_SET}, /* u-boot code */ {0x20000, 0x27fff, FLAG_PROTECT_CLEAR}, /* u-boot environment */ {0x28000, 0x1fffff, FLAG_PROTECT_CLEAR}, /* data area size to tune */ }; +#endif extern void AT91F_SpiInit (void); extern int AT91F_DataflashProbe (int i, AT91PS_DataflashDesc pDesc); @@ -45,22 +94,28 @@ extern int AT91F_DataFlashRead (AT91PS_DataFlash pDataFlash, unsigned long addr, unsigned long size, char *buffer); extern int AT91F_DataFlashWrite( AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ); + unsigned char *src, + int dest, + int size ); int AT91F_DataflashInit (void) { int i, j; int dfcode; + int part = 0; + int last_part; + int found[CFG_MAX_DATAFLASH_BANKS]; + unsigned char protected; AT91F_SpiInit (); for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { + found[i] = 0; dataflash_info[i].Desc.state = IDLE; dataflash_info[i].id = 0; dataflash_info[i].Device.pages_number = 0; - dfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc); + dfcode = AT91F_DataflashProbe (cs[i][1], + &dataflash_info[i].Desc); switch (dfcode) { case AT45DB161: @@ -72,6 +127,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i][0]; dataflash_info[i].id = dfcode; + found[i] += dfcode;; break; case AT45DB321: @@ -83,6 +139,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i][0]; dataflash_info[i].id = dfcode; + found[i] += dfcode;; break; case AT45DB642: @@ -94,7 +151,9 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i][0]; dataflash_info[i].id = dfcode; + found[i] += dfcode;; break; + case AT45DB128: dataflash_info[i].Device.pages_number = 16384; dataflash_info[i].Device.pages_size = 1056; @@ -104,9 +163,11 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i][0]; dataflash_info[i].id = dfcode; + found[i] += dfcode;; break; default: + dfcode = 0; break; } /* set the last area end to the dataflash size*/ @@ -114,16 +175,64 @@ int AT91F_DataflashInit (void) (dataflash_info[i].Device.pages_number * dataflash_info[i].Device.pages_size)-1; + last_part=0; /* set the area addresses */ for(j = 0; j (pdataFlash->pDevice->pages_size * pdataFlash->pDevice->pages_number)) return 0; /* is too large for the dataflash */ if (size > ((pdataFlash->pDevice->pages_size * - pdataFlash->pDevice->pages_number) - ((int)addr & 0x0FFFFFFF))) return 0; + pdataFlash->pDevice->pages_number) - + ((int)addr & 0x0FFFFFFF))) return 0; return 1; } -/*-----------------------------------------------------------------------------*/ -/* Function Name : prot_dataflash */ -/* Object : Test if destination area is protected */ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/* Function Name : prot_dataflash */ +/* Object : Test if destination area is protected */ +/*---------------------------------------------------------------------------*/ int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr) { int area; @@ -241,17 +368,23 @@ int area; (addr < pdataFlash->pDevice->area_list[area].end)) break; } - if (area == NB_DATAFLASH_AREA) return -1; + if (area == NB_DATAFLASH_AREA) + return -1; + /*test protection value*/ - if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET) return 0; + if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET) + return 0; + if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_INVALID) + return 0; return 1; } -/*-----------------------------------------------------------------------------*/ -/* Function Name : dataflash_real_protect */ -/* Object : protect/unprotect area */ -/*-----------------------------------------------------------------------------*/ -int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr) +/*--------------------------------------------------------------------------*/ +/* Function Name : dataflash_real_protect */ +/* Object : protect/unprotect area */ +/*--------------------------------------------------------------------------*/ +int dataflash_real_protect (int flag, unsigned long start_addr, + unsigned long end_addr) { int i,j, area1, area2, addr_valid = 0; /* find dataflash */ @@ -267,27 +400,38 @@ int i,j, area1, area2, addr_valid = 0; } /* find start area */ for (area1=0; area1 < NB_DATAFLASH_AREA; area1++) { - if (start_addr == dataflash_info[i].Device.area_list[area1].start) break; + if (start_addr == dataflash_info[i].Device.area_list[area1].start) + break; } if (area1 == NB_DATAFLASH_AREA) return -1; /* find end area */ for (area2=0; area2 < NB_DATAFLASH_AREA; area2++) { - if (end_addr == dataflash_info[i].Device.area_list[area2].end) break; + if (end_addr == dataflash_info[i].Device.area_list[area2].end) + break; } - if (area2 == NB_DATAFLASH_AREA) return -1; + if (area2 == NB_DATAFLASH_AREA) + return -1; /*set protection value*/ for(j = area1; j < area2+1 ; j++) - if (flag == 0) dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_CLEAR; - else dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_SET; + if(dataflash_info[i].Device.area_list[j].protected + != FLAG_PROTECT_INVALID) { + if (flag == 0) { + dataflash_info[i].Device.area_list[j].protected + = FLAG_PROTECT_CLEAR; + } else { + dataflash_info[i].Device.area_list[j].protected + = FLAG_PROTECT_SET; + } + } return (area2-area1+1); } -/*------------------------------------------------------------------------------*/ -/* Function Name : read_dataflash */ -/* Object : dataflash memory read */ -/*------------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/* Function Name : read_dataflash */ +/* Object : dataflash memory read */ +/*---------------------------------------------------------------------------*/ int read_dataflash (unsigned long addr, unsigned long size, char *result) { unsigned long AddrToRead = addr; @@ -305,12 +449,12 @@ int read_dataflash (unsigned long addr, unsigned long size, char *result) } -/*-----------------------------------------------------------------------------*/ -/* Function Name : write_dataflash */ -/* Object : write a block in dataflash */ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/* Function Name : write_dataflash */ +/* Object : write a block in dataflash */ +/*---------------------------------------------------------------------------*/ int write_dataflash (unsigned long addr_dest, unsigned long addr_src, - unsigned long size) + unsigned long size) { unsigned long AddrToWrite = addr_dest; AT91PS_DataFlash pFlash = &DataFlashInst; @@ -329,7 +473,8 @@ int write_dataflash (unsigned long addr_dest, unsigned long addr_src, if (AddrToWrite == -1) return -1; - return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, AddrToWrite, size); + return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, + AddrToWrite, size); } @@ -339,22 +484,22 @@ void dataflash_perror (int err) case ERR_OK: break; case ERR_TIMOUT: - printf ("Timeout writing to DataFlash\n"); + printf("Timeout writing to DataFlash\n"); break; case ERR_PROTECTED: - printf ("Can't write to protected DataFlash sectors\n"); + printf("Can't write to protected/invalid DataFlash sectors\n"); break; case ERR_INVAL: - printf ("Outside available DataFlash\n"); + printf("Outside available DataFlash\n"); break; case ERR_UNKNOWN_FLASH_TYPE: - printf ("Unknown Type of DataFlash\n"); + printf("Unknown Type of DataFlash\n"); break; case ERR_PROG_ERROR: - printf ("General DataFlash Programming Error\n"); + printf("General DataFlash Programming Error\n"); break; default: - printf ("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err); + printf("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err); break; } } diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 97d470484c3..0e01005a915 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -27,9 +27,9 @@ typedef volatile unsigned int AT91_REG; /* Hardware register definition */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/*****************************************************************************/ typedef struct _AT91S_TC { AT91_REG TC_CCR; /* Channel Control Register */ @@ -45,24 +45,24 @@ typedef struct _AT91S_TC AT91_REG TC_IMR; /* Interrupt Mask Register */ } AT91S_TC, *AT91PS_TC; -#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ -#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ -#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ -#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ -#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */ -#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ -#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ -#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ - -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Usart */ -/******************************************************************************/ +#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ +#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ +#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ +#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ +#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK*/ +#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ +#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ +#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ + +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Usart */ +/*****************************************************************************/ typedef struct _AT91S_USART { AT91_REG US_CR; /* Control Register */ @@ -94,9 +94,9 @@ typedef struct _AT91S_USART AT91_REG US_PTSR; /* PDC Transfer Status Register */ } AT91S_USART, *AT91PS_USART; -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ +/*****************************************************************************/ typedef struct _AT91S_CKGR { AT91_REG CKGR_MOR; /* Main Oscillator Register */ @@ -141,9 +141,9 @@ typedef struct _AT91S_CKGR #define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */ #define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ +/*****************************************************************************/ typedef struct _AT91S_PIO { AT91_REG PIO_PER; /* PIO Enable Register */ @@ -184,9 +184,9 @@ typedef struct _AT91S_PIO } AT91S_PIO, *AT91PS_PIO; -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Debug Unit */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/*****************************************************************************/ typedef struct _AT91S_DBGU { AT91_REG DBGU_CR; /* Control Register */ @@ -242,9 +242,9 @@ typedef struct _AT91S_DBGU #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */ #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ +/*****************************************************************************/ typedef struct _AT91S_SMC2 { AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ @@ -267,9 +267,9 @@ typedef struct _AT91S_SMC2 #define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ #define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Power Management Controler */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Power Management Controler */ +/*****************************************************************************/ typedef struct _AT91S_PMC { AT91_REG PMC_SCER; /* System Clock Enable Register */ @@ -341,9 +341,9 @@ typedef struct _AT91S_PMC /*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/ /*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Ethernet MAC */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Ethernet MAC */ +/*****************************************************************************/ typedef struct _AT91S_EMAC { AT91_REG EMAC_CTL; /* Network Control Register */ @@ -424,11 +424,11 @@ typedef struct _AT91S_EMAC #define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */ #define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */ -/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */ +/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */ #define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */ #define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */ -/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */ #define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */ #define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */ #define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */ @@ -442,7 +442,7 @@ typedef struct _AT91S_EMAC #define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ #define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */ -/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */ #define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */ #define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */ #define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */ @@ -456,8 +456,8 @@ typedef struct _AT91S_EMAC #define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */ #define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */ -/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ -/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */ /* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ /* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ #define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ @@ -471,9 +471,9 @@ typedef struct _AT91S_EMAC #define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */ #define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/*****************************************************************************/ typedef struct _AT91S_SPI { AT91_REG SPI_CR; /* Control Register */ @@ -536,7 +536,7 @@ typedef struct _AT91S_SPI #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */ /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */ /* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ /* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */ @@ -555,9 +555,9 @@ typedef struct _AT91S_SPI #define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */ #define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */ -/******************************************************************************/ -/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ -/******************************************************************************/ +/*****************************************************************************/ +/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ +/*****************************************************************************/ typedef struct _AT91S_PDC { AT91_REG PDC_RPR; /* Receive Pointer Register */ @@ -692,11 +692,15 @@ typedef struct _AT91S_PDC #define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */ #define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB3 */ +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB3 */ +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PB3 */ #define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */ #define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */ #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */ #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ #define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ #define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ @@ -737,19 +741,36 @@ typedef struct _AT91S_PDC #define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ #define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */ -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) /* (AIC) Base Address */ +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ +#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ +#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) /* (PIOC) Base Address */ #define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ +#if 0 +#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) /* (PMC) Base Address */ +#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) /* (PMC) Base Address */ +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) /* (PMC) Base Address */ +#endif + #define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA4000) /* (TC0) Base Address */ +#if 0 +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) /* (TC0) Base Address */ +#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) /* (TC0) Base Address */ +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) /* (TC0) Base Address */ +#endif +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ +#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */ +#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */ +#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ + #define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */ -#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ #define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ #define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ #define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ #define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ #define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 7d7888ed8c7..f6a5b4f1611 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -736,7 +736,11 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_LN2410SBC 725 #define MACH_TYPE_CB3RUFC 726 #define MACH_TYPE_MP2USB 727 +#define MACH_TYPE_AT91SAM9261EK 848 #define MACH_TYPE_PDNB3 1002 +#define MACH_TYPE_AT91SAM9260EK 1099 +#define MACH_TYPE_AT91RM9200DF 1119 +#define MACH_TYPE_AT91SAM9263EK 1202 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -9402,6 +9406,71 @@ extern unsigned int __machine_arch_type; # define machine_is_mp2usb() (0) #endif +#ifdef CONFIG_MACH_AT91SAM9261EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9261EK +# endif +# define machine_is_at91sam9261ek() \ + (machine_arch_type == MACH_TYPE_AT91SAM9261EK) +#else +# define machine_is_at91sam9261ek() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9260EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9260EK +# endif +# define machine_is_at91sam9260ek() \ + (machine_arch_type == MACH_TYPE_AT91SAM9260EK) +#else +# define machine_is_at91sam9260ek() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263EK +# endif +# define machine_is_at91sam9263ek() \ + (machine_arch_type == MACH_TYPE_AT91SAM9263EK) +#else +# define machine_is_at91sam9263ek() (0) +#endif + +#ifdef CONFIG_MACH_AT91RM9200DF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200DF +# endif +# define machine_is_at91rm9200df() \ + (machine_arch_type == MACH_TYPE_AT91RM9200DF) +#else +# define machine_is_at91rm9200df() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263EK +# endif +# define machine_is_at91sam9263ek() \ + (machine_arch_type == MACH_TYPE_AT91SAM9263EK) +#else +# define machine_is_at91sam9263ek() (0) +#endif + /* * These have not yet been registered */ diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 14801b565c0..3d91e99b97f 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -76,5 +76,6 @@ #define CONFIG_CMD_USB /* USB Support */ #define CONFIG_CMD_VFD /* VFD support (TRAB) */ #define CONFIG_CMD_XIMG /* Load part of Multi Image */ +#define CONFIG_CMD_MUX /* AT91 MMC/SPI Mux Support */ #endif /* _CONFIG_CMD_ALL_H */ diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index ecfa21d8280..a65c5f3422f 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -163,6 +163,11 @@ #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91C_USE_RMII +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + #define CONFIG_HAS_DATAFLASH 1 #define CFG_SPI_WRITE_TOUT (5*CFG_HZ) #define CFG_MAX_DATAFLASH_BANKS 2 diff --git a/include/dataflash.h b/include/dataflash.h index 650454e7ee5..c597e69f17d 100644 --- a/include/dataflash.h +++ b/include/dataflash.h @@ -38,13 +38,47 @@ #include "config.h" /*number of protected area*/ -#define NB_DATAFLASH_AREA 4 +#ifdef CONFIG_NEW_PARTITION +# define NB_DATAFLASH_AREA 6 +#else +# define NB_DATAFLASH_AREA 4 +#endif + +#ifdef CFG_NO_FLASH + +/*----------------------------------------------------------------------- + * return codes from flash_write(): + */ +# define ERR_OK 0 +# define ERR_TIMOUT 1 +# define ERR_NOT_ERASED 2 +# define ERR_PROTECTED 4 +# define ERR_INVAL 8 +# define ERR_ALIGN 16 +# define ERR_UNKNOWN_FLASH_VENDOR 32 +# define ERR_UNKNOWN_FLASH_TYPE 64 +# define ERR_PROG_ERROR 128 + +/*----------------------------------------------------------------------- + * Protection Flags for flash_protect(): + */ +# define FLAG_PROTECT_SET 0x01 +# define FLAG_PROTECT_CLEAR 0x02 +# define FLAG_PROTECT_INVALID 0x03 + +/*----------------------------------------------------------------------- + * Set Environment according to label: + */ +# define FLAG_SETENV 0x80 +#endif /* CFG_NO_FLASH */ /*define the area structure*/ typedef struct { unsigned long start; unsigned long end; unsigned char protected; + unsigned char setenv; + unsigned char label[20]; } dataflash_protect_t; typedef unsigned int AT91S_DataFlashStatus; @@ -96,6 +130,7 @@ typedef struct _AT91S_DATAFLASH_INFO { AT91S_DataflashDesc Desc; AT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */ unsigned long logical_address; + unsigned long end_address; unsigned int id; /* device id */ } AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO; @@ -106,6 +141,7 @@ typedef struct _AT91S_DATAFLASH_INFO { #define AT45DB321 0x34 #define AT45DB642 0x3c #define AT45DB128 0x10 +#define PAGES_PER_BLOCK 8 #define AT91C_DATAFLASH_TIMEOUT 10000 /* For AT91F_DataFlashWaitReady */ @@ -168,6 +204,7 @@ typedef struct _AT91S_DATAFLASH_INFO { extern int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr, unsigned long size); extern int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr); +extern int addr2ram(ulong addr); extern int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr); extern int addr_dataflash (unsigned long addr); extern int read_dataflash (unsigned long addr, unsigned long size, char *result); @@ -175,4 +212,8 @@ extern int write_dataflash (unsigned long addr, unsigned long dest, unsigned lon extern void dataflash_print_info (void); extern void dataflash_perror (int err); +#ifdef CONFIG_NEW_DF_PARTITION +extern int AT91F_DataflashSetEnv (void); #endif +#endif + #endif diff --git a/include/dm9161.h b/include/dm9161.h index f5bfb1960d4..d5d0e8d3ab0 100644 --- a/include/dm9161.h +++ b/include/dm9161.h @@ -43,9 +43,9 @@ #define DM9161_COLLISION_TEST (1 << 7) /*--Bit definitions: DM9161_BMSR */ -#define DM9161_100BASE_T4 (1 << 15) +#define DM9161_100BASE_TX (1 << 15) #define DM9161_100BASE_TX_FD (1 << 14) -#define DM9161_100BASE_T4_HD (1 << 13) +#define DM9161_100BASE_TX_HD (1 << 13) #define DM9161_10BASE_T_FD (1 << 12) #define DM9161_10BASE_T_HD (1 << 11) #define DM9161_MF_PREAMB_SUPPR (1 << 6) diff --git a/include/flash.h b/include/flash.h index 43b9c6bdca6..b0bf733f18d 100644 --- a/include/flash.h +++ b/include/flash.h @@ -119,6 +119,11 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of */ #define FLAG_PROTECT_SET 0x01 #define FLAG_PROTECT_CLEAR 0x02 +#define FLAG_PROTECT_INVALID 0x03 +/*----------------------------------------------------------------------- + * Set Environment according to label: + */ +#define FLAG_SETENV 0x80 /*----------------------------------------------------------------------- * Device IDs -- cgit v1.3.1 From dcbfd2e5649f97aa04fbbc6ea2b008aa4486e225 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 10:14:05 +0100 Subject: Add the files. --- board/at91rm9200dk/led.c | 80 +++++++ board/at91rm9200dk/mux.c | 39 +++ cpu/arm920t/at91rm9200/spi.c | 153 ++++++++++++ drivers/at45.c | 550 +++++++++++++++++++++++++++++++++++++++++++ include/at45.h | 69 ++++++ include/led.h | 46 ++++ 6 files changed, 937 insertions(+) create mode 100644 board/at91rm9200dk/led.c create mode 100644 board/at91rm9200dk/mux.c create mode 100644 cpu/arm920t/at91rm9200/spi.c create mode 100644 drivers/at45.c create mode 100644 include/at45.h create mode 100644 include/led.h (limited to 'drivers') diff --git a/board/at91rm9200dk/led.c b/board/at91rm9200dk/led.c new file mode 100644 index 00000000000..051891883f6 --- /dev/null +++ b/board/at91rm9200dk/led.c @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2006 + * Atmel Nordic AB + * Ulf Samuelsson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define GREEN_LED AT91C_PIO_PB0 +#define YELLOW_LED AT91C_PIO_PB1 +#define RED_LED AT91C_PIO_PB2 + +void green_LED_on(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_CODR = GREEN_LED; +} + +void yellow_LED_on(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_CODR = YELLOW_LED; +} + +void red_LED_on(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_CODR = RED_LED; +} + +void green_LED_off(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_SODR = GREEN_LED; +} + +void yellow_LED_off(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_SODR = YELLOW_LED; +} + +void red_LED_off(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_SODR = RED_LED; +} + + +void LED_init (void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + AT91PS_PMC PMC = AT91C_BASE_PMC; + PMC->PMC_PCER = (1 << AT91C_ID_PIOB); /* Enable PIOB clock */ + /* Disable peripherals on LEDs */ + PIOB->PIO_PER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; + /* Enable pins as outputs */ + PIOB->PIO_OER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; + /* Turn all LEDs OFF */ + PIOB->PIO_SODR = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; +} diff --git a/board/at91rm9200dk/mux.c b/board/at91rm9200dk/mux.c new file mode 100644 index 00000000000..d573923c1b4 --- /dev/null +++ b/board/at91rm9200dk/mux.c @@ -0,0 +1,39 @@ +#include +#include +#include +#include + +int AT91F_GetMuxStatus(void) { +#ifdef DATAFLASH_MMC_SELECT + AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ + + + if(AT91C_BASE_PIOB->PIO_ODSR & DATAFLASH_MMC_SELECT) { + return 1; + } else { + return 0; + } +#endif + return 0; +} + +void AT91F_SelectMMC(void) { +#ifdef DATAFLASH_MMC_SELECT + AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ + /* Set Output */ + AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT; +#endif +} + +void AT91F_SelectSPI(void) { +#ifdef DATAFLASH_MMC_SELECT + AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ + /* Clear Output */ + AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT; +#endif +} + + diff --git a/cpu/arm920t/at91rm9200/spi.c b/cpu/arm920t/at91rm9200/spi.c new file mode 100644 index 00000000000..7469e538208 --- /dev/null +++ b/cpu/arm920t/at91rm9200/spi.c @@ -0,0 +1,153 @@ +/* Driver for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +#ifdef CONFIG_HAS_DATAFLASH +#include + +#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to + the Continuous Array Read function */ + +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +#define AT91C_TIMEOUT_WRDY 200000 +#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0: NPCS0%1110 */ +#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ + +/*-------------------------------------------------------------------*/ +/* SPI DataFlash Init */ +/*-------------------------------------------------------------------*/ +void AT91F_SpiInit(void) +{ + /* Configure PIOs */ + AT91C_BASE_PIOA->PIO_ASR = + AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | + AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO | + AT91C_PA2_SPCK; + AT91C_BASE_PIOA->PIO_PDR = + AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | + AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO | + AT91C_PA2_SPCK; + /* Enable CLock */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; + + /* Reset the SPI */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; + + /* Configure SPI in Master Mode with No CS selected !!! */ + AT91C_BASE_SPI->SPI_MR = + AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; + + /* Configure CS0 and CS3 */ + *(AT91C_SPI_CSR + 0) = + AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); + + *(AT91C_SPI_CSR + 3) = + AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); +} + +void AT91F_SpiEnable(int cs) +{ + switch(cs) { + case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= + ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & + AT91C_SPI_PCS); + break; + case 3: /* Configure SPI CS3 for Serial DataFlash Card */ + /* Set up PIO SDC_TYPE to switch on DataFlash Card */ + /* and not MMC/SDCard */ + AT91C_BASE_PIOB->PIO_PER = + AT91C_PIO_PB7; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = + AT91C_PIO_PB7; /* Configure in output */ + /* Clear Output */ + AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; + /* Configure PCS */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= + ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); + break; + } + + /* SPI_Enable */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; } + +/*---------------------------------------------------------------------------*/ +/* \fn AT91F_SpiWrite */ +/* \brief Set the PDC registers for a transfert */ +/*---------------------------------------------------------------------------*/ +unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) +{ + unsigned int timeout; + + pDesc->state = BUSY; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + + /* Initialize the Transmit and Receive Pointer */ + AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; + AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; + + /* Intialize the Transmit and Receive Counters */ + AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; + AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; + + if ( pDesc->tx_data_size != 0 ) { + /* Initialize the Next Transmit and Next Receive Pointer */ + AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; + AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; + + /* Intialize the Next Transmit and Next Receive Counters */ + AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; + AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + timeout = 0; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; + while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && + ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + pDesc->state = IDLE; + + if (timeout >= CFG_SPI_WRITE_TOUT){ + printf("Error Timeout\n\r"); + return DATAFLASH_ERROR; + } + + return DATAFLASH_OK; +} + +#endif + diff --git a/drivers/at45.c b/drivers/at45.c new file mode 100644 index 00000000000..35c9ecce450 --- /dev/null +++ b/drivers/at45.c @@ -0,0 +1,550 @@ +/* Driver for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include + +#ifdef CONFIG_HAS_DATAFLASH +#include + + +#define AT91C_TIMEOUT_WRDY 200000 + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashSendCommand */ +/* \brief Generic function to send a command to the dataflash */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashSendCommand( + AT91PS_DataFlash pDataFlash, + unsigned char OpCode, + unsigned int CmdSize, + unsigned int DataflashAddress) +{ + unsigned int adr; + + if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* process the address to obtain page address and byte address */ + adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << + pDataFlash->pDevice->page_offset) + (DataflashAddress % + (pDataFlash->pDevice->pages_size)); + + /* fill the command buffer */ + pDataFlash->pDataFlashDesc->command[0] = OpCode; + if (pDataFlash->pDevice->pages_number >= 16384) { + pDataFlash->pDataFlashDesc->command[1] = + (unsigned char)((adr & 0x0F000000) >> 24); + pDataFlash->pDataFlashDesc->command[2] = + (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[3] = + (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[4] = + (unsigned char)(adr & 0x000000FF); + } else { + pDataFlash->pDataFlashDesc->command[1] = + (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[2] = + (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[3] = + (unsigned char)(adr & 0x000000FF); + pDataFlash->pDataFlashDesc->command[4] = 0; + } + pDataFlash->pDataFlashDesc->command[5] = 0; + pDataFlash->pDataFlashDesc->command[6] = 0; + pDataFlash->pDataFlashDesc->command[7] = 0; + + /* Initialize the SpiData structure for the spi write fuction */ + pDataFlash->pDataFlashDesc->tx_cmd_pt = + pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize; + pDataFlash->pDataFlashDesc->rx_cmd_pt = + pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize; + + /* send the command and read the data */ + return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); } + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashGetStatus */ +/* \brief Read the status register of the dataflash */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) +{ + AT91S_DataFlashStatus status; + + /* if a transfert is in progress ==> return 0 */ + if( (pDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* first send the read status command (D7H) */ + pDesc->command[0] = DB_STATUS; + pDesc->command[1] = 0; + + pDesc->DataFlash_state = GET_STATUS; + pDesc->tx_data_size = 0; /* Transmit the command */ + /* and receive response */ + pDesc->tx_cmd_pt = pDesc->command; + pDesc->rx_cmd_pt = pDesc->command; + pDesc->rx_cmd_size = 2; + pDesc->tx_cmd_size = 2; + status = AT91F_SpiWrite (pDesc); + + pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); + + return status; +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashWaitReady */ +/* \brief wait for dataflash ready (bit7 of the status register == 1) */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc +pDataFlashDesc, unsigned int timeout) +{ + pDataFlashDesc->DataFlash_state = IDLE; + + do { + AT91F_DataFlashGetStatus(pDataFlashDesc); + timeout--; + } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && + (timeout > 0) ); + + if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) + return DATAFLASH_ERROR; + + return DATAFLASH_OK; +} + + +/*--------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashContinuousRead */ +/* Object : Continuous stream Read */ +/* Input Parameters : DataFlash Service */ +/* : = dataflash address */ +/* : <*dataBuffer> = data buffer pointer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*--------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( + AT91PS_DataFlash pDataFlash, + int src, + unsigned char *dataBuffer, + int sizeToRead ) +{ + AT91S_DataFlashStatus status; + /* Test the size to read in the device */ + if ( (src + sizeToRead) > + (pDataFlash->pDevice->pages_size * + (pDataFlash->pDevice->pages_number))) + return DATAFLASH_MEMORY_OVERFLOW; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; + + status = AT91F_DataFlashSendCommand + (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); + /* Send the command to the dataflash */ + return(status); +} + + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashPagePgmBuf */ +/* Object : Main memory page program thru buffer 1 or buffer 2 */ +/* Input Parameters : DataFlash Service */ +/* : <*src> = Source buffer */ +/* : = dataflash destination address */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int SizeToWrite) +{ + int cmdsize; + pDataFlash->pDataFlashDesc->tx_data_pt = src; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite; + pDataFlash->pDataFlashDesc->rx_data_pt = src; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; + + cmdsize = 4; + /* Send the command to the dataflash */ + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, +cmdsize, dest)); } + + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_MainMemoryToBufferTransfert */ +/* Object : Read a page in the SRAM Buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_PAGE_2_BUF1_TRF) + && (BufferCommand != DB_PAGE_2_BUF2_TRF)) + return DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, +page*pDataFlash->pDevice->pages_size)); +} + + +/*-------------------------------------------------------------------------- */ +/* Function Name : AT91F_DataFlashWriteBuffer */ +/* Object : Write data to the internal sram buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : = command to write buffer1 or 2 */ +/* : <*dataBuffer> = data buffer to write */ +/* : = address in the internal buffer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned char *dataBuffer, + unsigned int bufferAddress, + int SizeToWrite ) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_BUF1_WRITE) + && (BufferCommand != DB_BUF2_WRITE)) + return DATAFLASH_BAD_COMMAND; + + /* buffer address must be lower than page size */ + if (bufferAddress > pDataFlash->pDevice->pages_size) + return DATAFLASH_BAD_ADDRESS; + + if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* Send first Write Command */ + pDataFlash->pDataFlashDesc->command[0] = BufferCommand; + pDataFlash->pDataFlashDesc->command[1] = 0; + if (pDataFlash->pDevice->pages_number >= 16384) { + pDataFlash->pDataFlashDesc->command[2] = 0; + pDataFlash->pDataFlashDesc->command[3] = + (unsigned char)(((unsigned int)(bufferAddress & + pDataFlash->pDevice->byte_mask)) >> 8); + pDataFlash->pDataFlashDesc->command[4] = + (unsigned char)((unsigned int)bufferAddress & 0x00FF); + cmdsize = 5; + } else { + pDataFlash->pDataFlashDesc->command[2] = + (unsigned char)(((unsigned int)(bufferAddress & + pDataFlash->pDevice->byte_mask)) >> 8); + pDataFlash->pDataFlashDesc->command[3] = + (unsigned char)((unsigned int)bufferAddress & 0x00FF); + pDataFlash->pDataFlashDesc->command[4] = 0; + cmdsize = 4; + } + + pDataFlash->pDataFlashDesc->tx_cmd_pt = + pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize; + pDataFlash->pDataFlashDesc->rx_cmd_pt = + pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite; + + return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); +} + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_PageErase */ +/* Object : Erase a page */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_PageErase( + AT91PS_DataFlash pDataFlash, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, +page*pDataFlash->pDevice->pages_size)); +} + + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_BlockErase */ +/* Object : Erase a Block */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_BlockErase( + AT91PS_DataFlash pDataFlash, + unsigned int block) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, +block*8*pDataFlash->pDevice->pages_size)); +} + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_WriteBufferToMain */ +/* Object : Write buffer to the main memory */ +/* Input Parameters : DataFlash Service */ +/* : = command to send to buffer1 or buffer2 */ +/* : = main memory address */ +/* Return value : State of the dataflash */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_WriteBufferToMain ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int dest ) +{ + int cmdsize; + /* Test if the buffer command is correct */ + if ((BufferCommand != DB_BUF1_PAGE_PGM) && + (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && + (BufferCommand != DB_BUF2_PAGE_PGM) && + (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) + return DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + /* Send the command to the dataflash */ + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, + dest)); } + + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_PartialPageWrite */ +/* Object : Erase partielly a page */ +/* Input Parameters : = page number */ +/* : = adr to begin the fading */ +/* : = Number of bytes to erase */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_PartialPageWrite ( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int size) +{ + unsigned int page; + unsigned int AdrInPage; + + page = dest / (pDataFlash->pDevice->pages_size); + AdrInPage = dest % (pDataFlash->pDevice->pages_size); + + /* Read the contents of the page in the Sram Buffer */ + AT91F_MainMemoryToBufferTransfert(pDataFlash, + DB_PAGE_2_BUF1_TRF, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + /*Update the SRAM buffer */ + AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, + AdrInPage, size); + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + + /* Erase page if a 128 Mbits device */ + if (pDataFlash->pDevice->pages_number >= 16384) { + AT91F_PageErase(pDataFlash, page); + /* Rewrite the modified Sram Buffer in the main memory */ + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + } + + /* Rewrite the modified Sram Buffer in the main memory */ + return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, + (page*pDataFlash->pDevice->pages_size))); +} + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashWrite */ +/* Object : */ +/* Input Parameters : <*src> = Source buffer */ +/* : = dataflash adress */ +/* : = data buffer size */ +/*---------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWrite( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + int dest, + int size ) +{ + unsigned int length; + unsigned int page; + unsigned int status; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if ( (dest + size) > (pDataFlash->pDevice->pages_size * + (pDataFlash->pDevice->pages_number))) + return DATAFLASH_MEMORY_OVERFLOW; + + /* If destination does not fit a page start address */ + if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) + { + length = pDataFlash->pDevice->pages_size - + (dest % + ((unsigned int) + (pDataFlash->pDevice->pages_size))); + + if (size < length) + length = size; + + if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + + /* Update size, source and destination pointers */ + size -= length; + dest += length; + src += length; + } + + while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { + /* program dataflash page */ + page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); + + status = AT91F_DataFlashWriteBuffer(pDataFlash, + DB_BUF1_WRITE, src, 0, + pDataFlash->pDevice->pages_size); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + + status = AT91F_PageErase(pDataFlash, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + if (!status) + return DATAFLASH_ERROR; + + status = AT91F_WriteBufferToMain (pDataFlash, + DB_BUF1_PAGE_PGM, dest); + if(!status) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + + /* Update size, source and destination pointers */ + size -= pDataFlash->pDevice->pages_size; + dest += pDataFlash->pDevice->pages_size; + src += pDataFlash->pDevice->pages_size; + } + + /* If still some bytes to read */ + if ( size > 0 ) { + /* program dataflash page */ + if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY); + } + return DATAFLASH_OK; +} + + +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashRead */ +/* Object : Read a block in dataflash */ +/* Input Parameters : */ +/* Return value : */ +/*---------------------------------------------------------------------------*/ +int AT91F_DataFlashRead( + AT91PS_DataFlash pDataFlash, + unsigned long addr, + unsigned long size, + char *buffer) +{ + unsigned long SizeToRead; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + return -1; + + while (size) { + SizeToRead = (size < 0x8000)? size:0x8000; + + if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + return -1; + + if (AT91F_DataFlashContinuousRead (pDataFlash, addr, + (uchar *) buffer, SizeToRead) != DATAFLASH_OK) + return -1; + + size -= SizeToRead; + addr += SizeToRead; + buffer += SizeToRead; + } + + return DATAFLASH_OK; +} + + diff --git a/include/at45.h b/include/at45.h new file mode 100644 index 00000000000..1f71a3b4e98 --- /dev/null +++ b/include/at45.h @@ -0,0 +1,69 @@ + +#ifndef _AT45_H_ +#define _AT45_H_ +#ifdef DATAFLASH_MMC_SELECT +extern void AT91F_SelectMMC(void); +extern void AT91F_SelectSPI(void); +extern int AT91F_GetMuxStatus(void); +#endif +extern void AT91F_SpiInit(void); +extern void AT91F_SpiEnable(int cs); +extern unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ); +extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand( + AT91PS_DataFlash pDataFlash, + unsigned char OpCode, + unsigned int CmdSize, + unsigned int DataflashAddress); +extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus ( + AT91PS_DataflashDesc pDesc); +extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady ( + AT91PS_DataflashDesc pDataFlashDesc, + unsigned int timeout); +extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( + AT91PS_DataFlash pDataFlash, + int src, + unsigned char *dataBuffer, + int sizeToRead ); +extern AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int SizeToWrite); +extern AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int page); +extern AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned char *dataBuffer, + unsigned int bufferAddress, + int SizeToWrite ); +extern AT91S_DataFlashStatus AT91F_PageErase( + AT91PS_DataFlash pDataFlash, + unsigned int page); +extern AT91S_DataFlashStatus AT91F_BlockErase( + AT91PS_DataFlash pDataFlash, + unsigned int block); +extern AT91S_DataFlashStatus AT91F_WriteBufferToMain ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int dest ); +extern AT91S_DataFlashStatus AT91F_PartialPageWrite ( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int size); +extern AT91S_DataFlashStatus AT91F_DataFlashWrite( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + int dest, + int size ); +extern int AT91F_DataFlashRead( + AT91PS_DataFlash pDataFlash, + unsigned long addr, + unsigned long size, + char *buffer); +extern int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc); + +#endif diff --git a/include/led.h b/include/led.h new file mode 100644 index 00000000000..a261f1bf23c --- /dev/null +++ b/include/led.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2006 + * Atmel Nordic AB + * Ulf Samuelsson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + #ifndef __LED_H +#define __LED_H + +#ifndef __ASSEMBLY__ +extern void LED_init (void); +extern void red_LED_on(void); +extern void red_LED_off(void); +extern void green_LED_on(void); +extern void green_LED_off(void); +extern void yellow_LED_on(void); +extern void yellow_LED_off(void); +#else + .extern LED_init + .extern red_LED_on + .extern red_LED_off + .extern yellow_LED_on + .extern yellow_LED_off + .extern green_LED_on + .extern green_LED_off +#endif +#endif + -- cgit v1.3.1 From 65d7ada64557e76094b4fd3bad30a0f18f5fb2b2 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 10:30:06 +0100 Subject: Update Makefiles for merged and split at45.c. --- board/at91rm9200dk/Makefile | 2 +- board/cmc_pu2/Makefile | 2 +- drivers/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) mode change 100644 => 100755 board/at91rm9200dk/Makefile mode change 100644 => 100755 board/cmc_pu2/Makefile mode change 100644 => 100755 drivers/Makefile (limited to 'drivers') diff --git a/board/at91rm9200dk/Makefile b/board/at91rm9200dk/Makefile old mode 100644 new mode 100755 index 7dfc27f0a74..01f3bc30a32 --- a/board/at91rm9200dk/Makefile +++ b/board/at91rm9200dk/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := at91rm9200dk.o at45.o flash.o led.o mux.o +COBJS := at91rm9200dk.o flash.o led.o mux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/cmc_pu2/Makefile b/board/cmc_pu2/Makefile old mode 100644 new mode 100755 index d445f287cba..f7a136034ed --- a/board/cmc_pu2/Makefile +++ b/board/cmc_pu2/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o +COBJS := cmc_pu2.o flash.o load_sernum_ethaddr.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/Makefile b/drivers/Makefile old mode 100644 new mode 100755 index fc980407623..3ee6312e9db --- a/drivers/Makefile +++ b/drivers/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libdrivers.a -COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \ +COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ e1000.o eepro100.o enc28j60.o \ -- cgit v1.3.1 From 0c42f36f15074bd9808a7dbd7ef611fad9bf537c Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 10:46:32 +0100 Subject: Replace lost end of at45.c. --- drivers/at45.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) mode change 100644 => 100755 drivers/at45.c (limited to 'drivers') diff --git a/drivers/at45.c b/drivers/at45.c old mode 100644 new mode 100755 index 35c9ecce450..4c12ca7a31d --- a/drivers/at45.c +++ b/drivers/at45.c @@ -547,4 +547,18 @@ int AT91F_DataFlashRead( return DATAFLASH_OK; } +/*---------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataflashProbe */ +/* Object : */ +/* Input Parameters : */ +/* Return value : Dataflash status register */ +/*---------------------------------------------------------------------------*/ +int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) { + AT91F_SpiEnable(cs); + AT91F_DataFlashGetStatus(pDesc); + return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); +} + +#endif + -- cgit v1.3.1 From e54b970173769307a116bd34028b6d0c2eea2a4e Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 15:40:00 +0100 Subject: Supply spi interface in at45.c --- drivers/at45.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/at45.c b/drivers/at45.c index 4c12ca7a31d..7d35695b100 100755 --- a/drivers/at45.c +++ b/drivers/at45.c @@ -24,6 +24,11 @@ #ifdef CONFIG_HAS_DATAFLASH #include +/* + * spi.c API + */ +extern unsigned int AT91F_SpiWrite (AT91PS_DataflashDesc pDesc); +extern void AT91F_SpiEnable(int cs); #define AT91C_TIMEOUT_WRDY 200000 -- cgit v1.3.1 From f01dbb5424a81453c81190dd30e945891466f621 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 14 Aug 2007 18:42:36 +0200 Subject: Coding style cleanup. Update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 68 ++++++++++++++++++++++ board/at91rm9200dk/mux.c | 10 ++-- cpu/arm920t/at91rm9200/spi.c | 2 - drivers/at45.c | 133 +++++++++++++++++++++---------------------- drivers/dataflash.c | 50 ++++++++-------- include/at45.h | 2 +- include/dataflash.h | 2 +- include/led.h | 3 +- 8 files changed, 165 insertions(+), 105 deletions(-) (limited to 'drivers') diff --git a/CHANGELOG b/CHANGELOG index 5472c8fe530..a8345681497 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,71 @@ +commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 +Author: Andy Fleming +Date: Tue Aug 14 10:32:59 2007 -0500 + + Fix initrd/dtb interaction + + The original code would wrongly relocate the blob to be right before + the initrd if it existed. The blob *must* be within CFG_BOOTMAPSZ, + if it is defined. So we make two changes: + + 1) flag the blob for relocation whenever its address is above BOOTMAPSZ + + 2) If the blob is being relocated, relocate it before kbd, not initrd + + Signed-off-by: Andy Fleming + +commit e54b970173769307a116bd34028b6d0c2eea2a4e +Author: Peter Pearse +Date: Tue Aug 14 15:40:00 2007 +0100 + + Supply spi interface in at45.c + +commit 0c42f36f15074bd9808a7dbd7ef611fad9bf537c +Author: Peter Pearse +Date: Tue Aug 14 10:46:32 2007 +0100 + + Replace lost end of at45.c. + +commit 65d7ada64557e76094b4fd3bad30a0f18f5fb2b2 +Author: Peter Pearse +Date: Tue Aug 14 10:30:06 2007 +0100 + + Update Makefiles for merged and split at45.c. + +commit 3454cece2db57cb9eb7087995f7e73066a163f71 +Author: Peter Pearse +Date: Tue Aug 14 10:21:06 2007 +0100 + + Delete the merged files. + +commit dcbfd2e5649f97aa04fbbc6ea2b008aa4486e225 +Author: Peter Pearse +Date: Tue Aug 14 10:14:05 2007 +0100 + + Add the files. + +commit d4fc6012fd0a5c211b825691f44b06f8032c0551 +Author: Peter Pearse +Date: Tue Aug 14 10:10:52 2007 +0100 + + Add MACH_TYPE records for several AT91 boards. + Merge to two at45.c files into a common file, split to at45.c and spi.c + Fix spelling error in DM9161 PHY Support. + Initialize at91rm9200 board (and set LED). + Add PIO control for at91rm9200dk LEDs and Mux. + Change dataflash partition boundaries to be compatible with Linux 2.6. + + Signed-off-by: Peter Pearse + Signed-off-by: Ulf Samuelsson + +commit 4ef35e53c693556c54b0c22d6f873de87bade253 +Author: Wolfgang Denk +Date: Tue Aug 14 09:54:46 2007 +0200 + + Coding style cleanup, update CHANGELOG + + Signed-off-by: Wolfgang Denk + commit 85eb5caf6b906f7ec5b54814e8c7c74f55986bb7 Author: Wolfgang Denk Date: Tue Aug 14 09:47:27 2007 +0200 diff --git a/board/at91rm9200dk/mux.c b/board/at91rm9200dk/mux.c index d573923c1b4..767d28090d1 100644 --- a/board/at91rm9200dk/mux.c +++ b/board/at91rm9200dk/mux.c @@ -23,8 +23,8 @@ void AT91F_SelectMMC(void) { AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ /* Set Output */ - AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT; -#endif + AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT; +#endif } void AT91F_SelectSPI(void) { @@ -32,8 +32,6 @@ void AT91F_SelectSPI(void) { AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT; -#endif + AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT; +#endif } - - diff --git a/cpu/arm920t/at91rm9200/spi.c b/cpu/arm920t/at91rm9200/spi.c index 7469e538208..265d18525f0 100644 --- a/cpu/arm920t/at91rm9200/spi.c +++ b/cpu/arm920t/at91rm9200/spi.c @@ -148,6 +148,4 @@ unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) return DATAFLASH_OK; } - #endif - diff --git a/drivers/at45.c b/drivers/at45.c index 7d35695b100..507ff36d478 100755 --- a/drivers/at45.c +++ b/drivers/at45.c @@ -36,7 +36,7 @@ extern void AT91F_SpiEnable(int cs); /*----------------------------------------------------------------------*/ /* \fn AT91F_DataFlashSendCommand */ /* \brief Generic function to send a command to the dataflash */ -/*----------------------------------------------------------------------*/ +/*----------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_DataFlashSendCommand( AT91PS_DataFlash pDataFlash, unsigned char OpCode, @@ -49,27 +49,27 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand( return DATAFLASH_BUSY; /* process the address to obtain page address and byte address */ - adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << - pDataFlash->pDevice->page_offset) + (DataflashAddress % + adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << + pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); /* fill the command buffer */ pDataFlash->pDataFlashDesc->command[0] = OpCode; if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[1] = + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); - pDataFlash->pDataFlashDesc->command[2] = + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[3] = + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[4] = + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); } else { - pDataFlash->pDataFlashDesc->command[1] = + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[2] = + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[3] = + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF); pDataFlash->pDataFlashDesc->command[4] = 0; } @@ -78,10 +78,10 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand( pDataFlash->pDataFlashDesc->command[7] = 0; /* Initialize the SpiData structure for the spi write fuction */ - pDataFlash->pDataFlashDesc->tx_cmd_pt = + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize; - pDataFlash->pDataFlashDesc->rx_cmd_pt = + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize; @@ -92,8 +92,8 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand( /*----------------------------------------------------------------------*/ /* \fn AT91F_DataFlashGetStatus */ /* \brief Read the status register of the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) { AT91S_DataFlashStatus status; @@ -123,16 +123,16 @@ AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) /*----------------------------------------------------------------------*/ /* \fn AT91F_DataFlashWaitReady */ /* \brief wait for dataflash ready (bit7 of the status register == 1) */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc -pDataFlashDesc, unsigned int timeout) +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc +pDataFlashDesc, unsigned int timeout) { pDataFlashDesc->DataFlash_state = IDLE; do { AT91F_DataFlashGetStatus(pDataFlashDesc); timeout--; - } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && + } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) @@ -150,7 +150,7 @@ pDataFlashDesc, unsigned int timeout) /* : <*dataBuffer> = data buffer pointer */ /* : = data buffer size */ /* Return value : State of the dataflash */ -/*--------------------------------------------------------------------------*/ +/*--------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( AT91PS_DataFlash pDataFlash, int src, @@ -159,8 +159,8 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( { AT91S_DataFlashStatus status; /* Test the size to read in the device */ - if ( (src + sizeToRead) > - (pDataFlash->pDevice->pages_size * + if ( (src + sizeToRead) > + (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) return DATAFLASH_MEMORY_OVERFLOW; @@ -169,7 +169,7 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; - status = AT91F_DataFlashSendCommand + status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); /* Send the command to the dataflash */ return(status); @@ -184,7 +184,7 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( /* : = dataflash destination address */ /* : = data buffer size */ /* Return value : State of the dataflash */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( AT91PS_DataFlash pDataFlash, unsigned char *src, @@ -201,7 +201,7 @@ AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( /* Send the command to the dataflash */ if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); } @@ -212,7 +212,7 @@ cmdsize, dest)); } /* : Page concerned */ /* : */ /* Return value : State of the dataflash */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( AT91PS_DataFlash pDataFlash, unsigned char BufferCommand, @@ -220,7 +220,7 @@ AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( { int cmdsize; /* Test if the buffer command is legal */ - if ((BufferCommand != DB_PAGE_2_BUF1_TRF) + if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) return DATAFLASH_BAD_COMMAND; @@ -229,7 +229,7 @@ AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); } @@ -253,7 +253,7 @@ AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( { int cmdsize; /* Test if the buffer command is legal */ - if ((BufferCommand != DB_BUF1_WRITE) + if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) return DATAFLASH_BAD_COMMAND; @@ -269,26 +269,26 @@ AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( pDataFlash->pDataFlashDesc->command[1] = 0; if (pDataFlash->pDevice->pages_number >= 16384) { pDataFlash->pDataFlashDesc->command[2] = 0; - pDataFlash->pDataFlashDesc->command[3] = - (unsigned char)(((unsigned int)(bufferAddress & + pDataFlash->pDataFlashDesc->command[3] = + (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8); - pDataFlash->pDataFlashDesc->command[4] = + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF); cmdsize = 5; } else { - pDataFlash->pDataFlashDesc->command[2] = - (unsigned char)(((unsigned int)(bufferAddress & + pDataFlash->pDataFlashDesc->command[2] = + (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8); - pDataFlash->pDataFlashDesc->command[3] = + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF); pDataFlash->pDataFlashDesc->command[4] = 0; cmdsize = 4; } - pDataFlash->pDataFlashDesc->tx_cmd_pt = + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize; - pDataFlash->pDataFlashDesc->rx_cmd_pt = + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize; @@ -320,7 +320,7 @@ AT91S_DataFlashStatus AT91F_PageErase( cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); } @@ -332,7 +332,7 @@ page*pDataFlash->pDevice->pages_size)); /* : Page concerned */ /* : */ /* Return value : State of the dataflash */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_BlockErase( AT91PS_DataFlash pDataFlash, unsigned int block) @@ -344,7 +344,7 @@ AT91S_DataFlashStatus AT91F_BlockErase( cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, + return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); } @@ -355,7 +355,7 @@ block*8*pDataFlash->pDevice->pages_size)); /* : = command to send to buffer1 or buffer2 */ /* : = main memory address */ /* Return value : State of the dataflash */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_WriteBufferToMain ( AT91PS_DataFlash pDataFlash, unsigned char BufferCommand, @@ -386,7 +386,7 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain ( /* Input Parameters : = page number */ /* : = adr to begin the fading */ /* : = Number of bytes to erase */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_PartialPageWrite ( AT91PS_DataFlash pDataFlash, unsigned char *src, @@ -400,27 +400,27 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite ( AdrInPage = dest % (pDataFlash->pDevice->pages_size); /* Read the contents of the page in the Sram Buffer */ - AT91F_MainMemoryToBufferTransfert(pDataFlash, + AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); /*Update the SRAM buffer */ - AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, + AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); /* Erase page if a 128 Mbits device */ if (pDataFlash->pDevice->pages_number >= 16384) { AT91F_PageErase(pDataFlash, page); /* Rewrite the modified Sram Buffer in the main memory */ - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); } /* Rewrite the modified Sram Buffer in the main memory */ - return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, + return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); } @@ -430,7 +430,7 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite ( /* Input Parameters : <*src> = Source buffer */ /* : = dataflash adress */ /* : = data buffer size */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_DataFlashWrite( AT91PS_DataFlash pDataFlash, unsigned char *src, @@ -443,15 +443,15 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite( AT91F_SpiEnable(pDataFlash->pDevice->cs); - if ( (dest + size) > (pDataFlash->pDevice->pages_size * + if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) return DATAFLASH_MEMORY_OVERFLOW; /* If destination does not fit a page start address */ - if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) + if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { - length = pDataFlash->pDevice->pages_size - - (dest % + length = pDataFlash->pDevice->pages_size - + (dest % ((unsigned int) (pDataFlash->pDevice->pages_size))); @@ -461,7 +461,7 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite( if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) return DATAFLASH_ERROR; - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); /* Update size, source and destination pointers */ @@ -474,24 +474,24 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite( /* program dataflash page */ page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); - status = AT91F_DataFlashWriteBuffer(pDataFlash, - DB_BUF1_WRITE, src, 0, + status = AT91F_DataFlashWriteBuffer(pDataFlash, + DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); status = AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); if (!status) return DATAFLASH_ERROR; - status = AT91F_WriteBufferToMain (pDataFlash, + status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); if(!status) return DATAFLASH_ERROR; - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); /* Update size, source and destination pointers */ @@ -506,7 +506,7 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite( if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) return DATAFLASH_ERROR; - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); } return DATAFLASH_OK; @@ -529,18 +529,18 @@ int AT91F_DataFlashRead( AT91F_SpiEnable(pDataFlash->pDevice->cs); - if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) return -1; while (size) { SizeToRead = (size < 0x8000)? size:0x8000; - if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) return -1; - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, + if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *) buffer, SizeToRead) != DATAFLASH_OK) return -1; @@ -557,13 +557,10 @@ int AT91F_DataFlashRead( /* Object : */ /* Input Parameters : */ /* Return value : Dataflash status register */ -/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) { AT91F_SpiEnable(cs); AT91F_DataFlashGetStatus(pDesc); - return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); + return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); } - #endif - - diff --git a/drivers/dataflash.c b/drivers/dataflash.c index 3b068d7125c..91903c8c8f7 100644 --- a/drivers/dataflash.c +++ b/drivers/dataflash.c @@ -63,7 +63,7 @@ dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { #endif #elif defined(CONFIG_NEW_PARTITION) /*define the area offsets*/ -/* Invalid partitions should be defined with start > end */ +/* Invalid partitions should be defined with start > end */ dataflash_protect_t area_list[NB_DATAFLASH_AREA*CFG_MAX_DATAFLASH_BANKS] = { {0x00000000, 0x000083ff, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */ {0x00008400, 0x00020fff, FLAG_PROTECT_SET, 0, "U-Boot"}, /* u-boot code */ @@ -114,7 +114,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.state = IDLE; dataflash_info[i].id = 0; dataflash_info[i].Device.pages_number = 0; - dfcode = AT91F_DataflashProbe (cs[i][1], + dfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc); switch (dfcode) { @@ -179,26 +179,26 @@ int AT91F_DataflashInit (void) /* set the area addresses */ for(j = 0; jpDevice->pages_number)) return 0; /* is too large for the dataflash */ if (size > ((pdataFlash->pDevice->pages_size * - pdataFlash->pDevice->pages_number) - + pdataFlash->pDevice->pages_number) - ((int)addr & 0x0FFFFFFF))) return 0; return 1; @@ -368,13 +368,13 @@ int area; (addr < pdataFlash->pDevice->area_list[area].end)) break; } - if (area == NB_DATAFLASH_AREA) + if (area == NB_DATAFLASH_AREA) return -1; /*test protection value*/ - if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET) + if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET) return 0; - if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_INVALID) + if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_INVALID) return 0; return 1; @@ -383,7 +383,7 @@ int area; /* Function Name : dataflash_real_protect */ /* Object : protect/unprotect area */ /*--------------------------------------------------------------------------*/ -int dataflash_real_protect (int flag, unsigned long start_addr, +int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr) { int i,j, area1, area2, addr_valid = 0; @@ -400,27 +400,27 @@ int i,j, area1, area2, addr_valid = 0; } /* find start area */ for (area1=0; area1 < NB_DATAFLASH_AREA; area1++) { - if (start_addr == dataflash_info[i].Device.area_list[area1].start) + if (start_addr == dataflash_info[i].Device.area_list[area1].start) break; } if (area1 == NB_DATAFLASH_AREA) return -1; /* find end area */ for (area2=0; area2 < NB_DATAFLASH_AREA; area2++) { - if (end_addr == dataflash_info[i].Device.area_list[area2].end) + if (end_addr == dataflash_info[i].Device.area_list[area2].end) break; } - if (area2 == NB_DATAFLASH_AREA) + if (area2 == NB_DATAFLASH_AREA) return -1; /*set protection value*/ for(j = area1; j < area2+1 ; j++) - if(dataflash_info[i].Device.area_list[j].protected + if(dataflash_info[i].Device.area_list[j].protected != FLAG_PROTECT_INVALID) { if (flag == 0) { - dataflash_info[i].Device.area_list[j].protected + dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_CLEAR; } else { - dataflash_info[i].Device.area_list[j].protected + dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_SET; } } @@ -473,7 +473,7 @@ int write_dataflash (unsigned long addr_dest, unsigned long addr_src, if (AddrToWrite == -1) return -1; - return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, + return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, AddrToWrite, size); } diff --git a/include/at45.h b/include/at45.h index 1f71a3b4e98..40bb4a08bd4 100644 --- a/include/at45.h +++ b/include/at45.h @@ -17,7 +17,7 @@ extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand( extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus ( AT91PS_DataflashDesc pDesc); extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady ( - AT91PS_DataflashDesc pDataFlashDesc, + AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout); extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( AT91PS_DataFlash pDataFlash, diff --git a/include/dataflash.h b/include/dataflash.h index c597e69f17d..fbd5e17f44c 100644 --- a/include/dataflash.h +++ b/include/dataflash.h @@ -78,7 +78,7 @@ typedef struct { unsigned long end; unsigned char protected; unsigned char setenv; - unsigned char label[20]; + unsigned char label[20]; } dataflash_protect_t; typedef unsigned int AT91S_DataFlashStatus; diff --git a/include/led.h b/include/led.h index a261f1bf23c..57c2b4a3777 100644 --- a/include/led.h +++ b/include/led.h @@ -22,7 +22,7 @@ * MA 02111-1307 USA */ - #ifndef __LED_H +#ifndef __LED_H #define __LED_H #ifndef __ASSEMBLY__ @@ -43,4 +43,3 @@ extern void yellow_LED_off(void); .extern green_LED_off #endif #endif - -- cgit v1.3.1 From 594e79838ce5078a90d0c27abb2b2d61d5f8e8a7 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Tue, 14 Aug 2007 14:06:45 -0500 Subject: Fix malloc size error in ahci_init_one. Typically this causes scsi init to corrupt the devlist and break the coninfo command. Fix a compiler size warning. Signed-off-by: Jason Jin Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- drivers/ahci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/ahci.c b/drivers/ahci.c index ccd4d71e8ae..3d82c625a35 100644 --- a/drivers/ahci.c +++ b/drivers/ahci.c @@ -259,8 +259,8 @@ static int ahci_init_one(pci_dev_t pdev) memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); - probe_ent = malloc(sizeof(probe_ent)); - memset(probe_ent, 0, sizeof(probe_ent)); + probe_ent = malloc(sizeof(struct ahci_probe_ent)); + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); probe_ent->dev = pdev; pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); -- cgit v1.3.1 From 002275a3ed8b114885f6702d6d544d0780dfe689 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 16 Aug 2007 08:54:10 +0200 Subject: Bios emulator - fix microblaze toolchain problem microblaze CPU have problem with bios_emulator code. Microblaze toolchain doesn't support PRAGMA PACK. Signed-off-by: Michal Simek --- drivers/bios_emulator/besys.c | 5 ++++- drivers/bios_emulator/bios.c | 5 ++++- drivers/bios_emulator/biosemu.c | 4 +++- drivers/bios_emulator/x86emu/debug.c | 4 +++- drivers/bios_emulator/x86emu/decode.c | 5 +++-- drivers/bios_emulator/x86emu/ops.c | 4 +++- drivers/bios_emulator/x86emu/ops2.c | 4 +++- drivers/bios_emulator/x86emu/prim_ops.c | 5 ++++- drivers/bios_emulator/x86emu/sys.c | 4 +++- 9 files changed, 30 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c index 4c4bc8d7ba1..8f1d8b29d59 100644 --- a/drivers/bios_emulator/besys.c +++ b/drivers/bios_emulator/besys.c @@ -47,9 +47,12 @@ * ****************************************************************************/ -#include "biosemui.h" +#include #if defined(CONFIG_BIOSEMU) + +#include "biosemui.h" + /*------------------------- Global Variables ------------------------------*/ #ifndef __i386__ diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c index 7aa1bfb2eb6..70e9ce143b4 100644 --- a/drivers/bios_emulator/bios.c +++ b/drivers/bios_emulator/bios.c @@ -41,9 +41,12 @@ * ****************************************************************************/ -#include "biosemui.h" +#include #if defined(CONFIG_BIOSEMU) + +#include "biosemui.h" + /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c index 4c3aedf4130..ccfc872f788 100644 --- a/drivers/bios_emulator/biosemu.c +++ b/drivers/bios_emulator/biosemu.c @@ -45,11 +45,13 @@ * ****************************************************************************/ -#include "biosemui.h" #include +#include #if defined(CONFIG_BIOSEMU) +#include "biosemui.h" + BE_sysEnv _BE_env = {{0}}; static X86EMU_memFuncs _BE_mem __attribute__((section(".got2"))) = { BE_rdb, diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index 915739c5b03..5cbcc950183 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -37,11 +37,13 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" #include +#include #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*----------------------------- Implementation ----------------------------*/ #ifdef DEBUG diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c index 879f0a06d17..7a9a1ddbff9 100644 --- a/drivers/bios_emulator/x86emu/decode.c +++ b/drivers/bios_emulator/x86emu/decode.c @@ -36,11 +36,12 @@ * instruction decoding and accessess of immediate data via IP. etc. * ****************************************************************************/ - -#include "x86emu/x86emui.h" +#include #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index d334fb5b1cf..a77bd9b4924 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -75,10 +75,12 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" +#include #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*----------------------------- Implementation ----------------------------*/ /* constant arrays to do several instructions in just one function */ diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index 81c0d49a333..d6a210c9736 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -44,10 +44,12 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" +#include #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c index c1152eae341..2a254a4e671 100644 --- a/drivers/bios_emulator/x86emu/prim_ops.c +++ b/drivers/bios_emulator/x86emu/prim_ops.c @@ -97,11 +97,14 @@ * ****************************************************************************/ +#include + #define PRIM_OPS_NO_REDEFINE_ASM -#include "x86emu/x86emui.h" #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*------------------------- Global Variables ------------------------------*/ static u32 x86emu_parity_tab[8] = diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c index 566389f5862..dd44ff1e738 100644 --- a/drivers/bios_emulator/x86emu/sys.c +++ b/drivers/bios_emulator/x86emu/sys.c @@ -39,10 +39,12 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" +#include #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*------------------------- Global Variables ------------------------------*/ X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ -- cgit v1.3.1 From 3a79013e2adda53332dfd0b511066a805e929a9d Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 15 Aug 2007 20:03:25 -0500 Subject: Define tsec flag values in config files The tsec_info structure and array has a "flags" field for each ethernet controller. This field is the only reason there are settings. Switch to defining TSECn_FLAGS for each controller in the config header, and we can greatly simplify the array, and also simplify the addition of future boards. Signed-off-by: Andy Fleming --- drivers/tsec.c | 30 +++++++++++------------------- include/configs/MPC8313ERDB.h | 2 ++ include/configs/MPC8349EMDS.h | 2 ++ include/configs/MPC8349ITX.h | 2 ++ include/configs/MPC8540ADS.h | 3 +++ include/configs/MPC8540EVAL.h | 4 ++++ include/configs/MPC8541CDS.h | 5 ++--- include/configs/MPC8544DS.h | 8 +++----- include/configs/MPC8548CDS.h | 4 ++++ include/configs/MPC8555CDS.h | 5 ++--- include/configs/MPC8560ADS.h | 3 ++- include/configs/MPC8568MDS.h | 6 +++--- include/configs/MPC8641HPCN.h | 4 ++++ include/configs/PM854.h | 3 +++ include/configs/PM856.h | 3 ++- include/configs/TQM834x.h | 2 ++ include/configs/TQM85xx.h | 3 +++ include/configs/sbc8349.h | 2 ++ include/configs/sbc8641d.h | 4 ++++ include/configs/stxgp3.h | 3 ++- include/configs/stxssa.h | 3 ++- 21 files changed, 64 insertions(+), 37 deletions(-) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index fd21ed4edc4..1df8f7dc256 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -65,38 +65,30 @@ struct tsec_info_struct { * FEC_PHYIDX */ static struct tsec_info_struct tsec_info[] = { -#if defined(CONFIG_TSEC1) -#if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN) - {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, -#else - {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, -#endif +#ifdef CONFIG_TSEC1 + {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX}, #else {0, 0, 0}, #endif -#if defined(CONFIG_TSEC2) -#if defined(CONFIG_MPC8641HPCN) - {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, -#else - {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, -#endif +#ifdef CONFIG_TSEC2 + {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX}, #else {0, 0, 0}, #endif #ifdef CONFIG_MPC85XX_FEC - {FEC_PHY_ADDR, 0, FEC_PHYIDX}, + {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX}, #else -#if defined(CONFIG_TSEC3) - {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, +#ifdef CONFIG_TSEC3 + {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX}, #else {0, 0, 0}, #endif -#if defined(CONFIG_TSEC4) - {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, +#ifdef CONFIG_TSEC4 + {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX}, #else {0, 0, 0}, -#endif -#endif +#endif /* CONFIG_TSEC4 */ +#endif /* CONFIG_MPC85XX_FEC */ }; #define MAXCONTROLLERS (4) diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 81db96f4661..f92dce541f8 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -310,6 +310,8 @@ #define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0x1c #define TSEC2_PHY_ADDR 4 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 1567fcfae32..10af5f0bc8a 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -440,6 +440,8 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 44649d05090..58ee13d3f37 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -382,6 +382,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ #define TSEC1_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT #endif #ifdef CONFIG_TSEC2 @@ -391,6 +392,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ #define TSEC2_PHY_ADDR 4 #define TSEC2_PHYIDX 0 +#define TSEC2_FLAGS TSEC_GIGABIT #endif #define CONFIG_ETHPRIME "Freescale TSEC" diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5a7c879a533..b7749926717 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -374,6 +374,8 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #if CONFIG_HAS_FEC @@ -381,6 +383,7 @@ #define CONFIG_MPC85XX_FEC_NAME "FEC" #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 #endif /* Options are: TSEC[0-1], FEC */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 0ce25cf24e7..5c03ac8c95e 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -224,6 +224,10 @@ #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define FEC_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define FEC_FLAGS 0 + /* Options are: TSEC[0-1], FEC */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 232f1716bcc..33a153e3460 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -384,13 +384,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 -#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 32934e15506..78634473317 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -364,15 +364,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_TSEC1_NAME "eTSEC1" #define CONFIG_TSEC3 1 #define CONFIG_TSEC3_NAME "eTSEC3" -#undef CONFIG_MPC85XX_FEC - -#define CONFIG_TSEC_TBI 1 /* enable internal TBI phy */ -#define CONFIG_SGMII_RISER -#define TSEC1_SGMII_PHY_ADDR_OFFSET 0x1c /* sgmii phy base */ #define TSEC1_PHY_ADDR 0 #define TSEC3_PHY_ADDR 1 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + #define TSEC1_PHYIDX 0 #define TSEC3_PHYIDX 0 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index cda9fd5c1c7..7345a3e10f0 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -447,6 +447,10 @@ extern unsigned long get_clock_freq(void); #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index e8fe99aaf13..48a2663b5c6 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -384,13 +384,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 -#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index c10e551e408..da41dadcd27 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -360,11 +360,12 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index dc9cb1ff545..6b824ed9ddb 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -399,9 +399,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC1_NAME "eTSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "eTSEC1" -#undef CONFIG_TSEC3 -#undef CONFIG_TSEC4 -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 3 @@ -409,6 +406,9 @@ extern unsigned long get_clock_freq(void); #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 64dcbd01093..e912331f31c 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -417,6 +417,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define CONFIG_ETHPRIME "eTSEC1" diff --git a/include/configs/PM854.h b/include/configs/PM854.h index dbf94228ae6..93090b981c3 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -270,11 +270,14 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_MPC85XX_FEC 1 #define CONFIG_MPC85XX_FEC_NAME "FEC" #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 6bdfa5d8f1f..6105747c70e 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -262,11 +262,12 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #endif /* CONFIG_TSEC_ENET */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 661712b227b..91c1694f2ca 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -253,6 +253,8 @@ extern int tqm834x_num_flash_banks; #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index d5ce3ba7169..cb9bf549295 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -266,8 +266,11 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 1831bef0de1..aa515ea6148 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -410,6 +410,8 @@ #define TSEC2_PHY_ADDR 0x1a #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 277b611409d..760b754e6c5 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -380,6 +380,10 @@ #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS TSEC_GIGABIT +#define TSEC4_FLAGS TSEC_GIGABIT #define CFG_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 1f41cf7699e..43b185bee6f 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -234,12 +234,13 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 4 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_ETHPRIME "TSEC0" #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 55e2c8da20d..3dae27ac11b 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -260,12 +260,13 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 4 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_ETHPRIME "TSEC0" #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ -- cgit v1.3.1 From b96c83d4ae475a70ef2635cd0e748174c44c8601 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 15 Aug 2007 20:03:34 -0500 Subject: Fix numerous bugs in the 8568 UEC support Actually, fixed a large bug in the UEC for *all* platforms. How did this ever work? uec_init() did not follow the spec for eth_init(), and returned 0 on success. Switch it to return the link like tsec_init() (and 0 on error) The immap for the 8568 was defined based on MPC8568, rather than CONFIG_MPC8568 CONFIG_QE was off CONFIG_ETHPRIME was set to "Freescale GETH". Now is "FSL UEC0" Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is enabled Signed-off-by: Andy Fleming --- drivers/qe/uec.c | 6 +++--- include/asm-ppc/immap_85xx.h | 2 +- include/configs/MPC8568MDS.h | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 89a72798232..dc2765bb09e 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1110,7 +1110,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd) if (dev->enetaddr[0] & 0x01) { printf("%s: MacAddress is multcast address\n", __FUNCTION__); - return -EINVAL; + return 0; } uec_set_mac_address(uec, dev->enetaddr); uec->the_first_run = 1; @@ -1119,10 +1119,10 @@ static int uec_init(struct eth_device* dev, bd_t *bd) err = uec_open(uec, COMM_DIR_RX_AND_TX); if (err) { printf("%s: cannot enable UEC device\n", dev->name); - return err; + return 0; } - return 0; + return uec->mii_info->link; } static void uec_halt(struct eth_device* dev) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 3d4816f3a99..496fc72da34 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1596,7 +1596,7 @@ typedef struct ccsr_gur { uint svr; /* 0xe00a4 - System version register */ char res10a[8]; uint rstcr; /* 0xe00b0 - Reset control register */ -#ifdef MPC8568 +#ifdef CONFIG_MPC8568 char res10b[76]; par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */ char res10c[3136]; diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 6b824ed9ddb..80ccda51f7c 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -35,7 +35,7 @@ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_QE /* Enable QE */ +#define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -348,7 +348,7 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_UEC_ETH #ifndef CONFIG_TSEC_ENET -#define CONFIG_ETHPRIME "Freescale GETH" +#define CONFIG_ETHPRIME "FSL UEC0" #endif #define CONFIG_PHY_MODE_NEED_CHANGE #define CONFIG_eTSEC_MDIO_BUS @@ -409,7 +409,7 @@ extern unsigned long get_clock_freq(void); #define TSEC1_FLAGS TSEC_GIGABIT #define TSEC2_FLAGS TSEC_GIGABIT -/* Options are: eTSEC[0-3] */ +/* Options are: eTSEC[0-1] */ #define CONFIG_ETHPRIME "eTSEC0" #endif /* CONFIG_TSEC_ENET */ -- cgit v1.3.1 From 7613afda77d5eec0f47d303025b0c661b70e4c73 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 15 Aug 2007 20:03:44 -0500 Subject: Don't wait for disconnected TSECs The TSEC driver's PHY code waits a long time for autonegotiation to complete, even if the link is down. The PHY knows the link is down or up before autonegotiation completes, so we can short-circuit the process if the link is down. Signed-off-by: Andy Fleming --- drivers/tsec.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index 1df8f7dc256..6bca4dc0f33 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -347,17 +347,16 @@ uint mii_cr_init(uint mii_reg, struct tsec_private * priv) uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) { /* - * Wait if PHY is capable of autonegotiation and autonegotiation - * is not complete. + * Wait if the link is up, and autonegotiation is in progress + * (ie - we're capable and it's not done) */ mii_reg = read_phy_reg(priv, MIIM_STATUS); - if ((mii_reg & PHY_BMSR_AUTN_ABLE) + if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { int i = 0; puts("Waiting for PHY auto negotiation to complete"); - while (!((mii_reg & PHY_BMSR_AUTN_COMP) - && (mii_reg & MIIM_STATUS_LINK))) { + while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { /* * Timeout reached ? */ @@ -377,7 +376,10 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) priv->link = 1; udelay(500000); /* another 500 ms (results in faster booting) */ } else { - priv->link = 1; + if (mii_reg & MIIM_STATUS_LINK) + priv->link = 1; + else + priv->link = 0; } return 0; @@ -517,16 +519,13 @@ uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); - if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && - (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { + if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && + !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { int i = 0; puts("Waiting for PHY realtime link"); - while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && - (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { - /* - * Timeout reached ? - */ + while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { + /* Timeout reached ? */ if (i > PHY_AUTONEGOTIATE_TIMEOUT) { puts(" TIMEOUT !\n"); priv->link = 0; @@ -541,6 +540,11 @@ uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) } puts(" done\n"); udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) + priv->link = 1; + else + priv->link = 0; } if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) -- cgit v1.3.1 From ab77bc547ba561c25ea34457ed17aa0b2f7c2723 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 15:39:17 -0500 Subject: ColdFire: MCF5329 Update and cleanup Signed-off-by: TsiChungLiew --- Makefile | 2 +- board/freescale/m5329evb/mii.c | 8 ++--- board/freescale/m5329evb/nand.c | 2 +- common/cmd_bdinfo.c | 12 +++---- drivers/net/mcffec.c | 10 +++--- include/asm-m68k/immap.h | 2 ++ include/asm-m68k/io.h | 62 ++++++++++++++++++------------------ include/asm-m68k/timer.h | 14 +++++++++ include/configs/M5329EVB.h | 69 +++++++++++++++++++---------------------- lib_m68k/board.c | 2 +- lib_m68k/time.c | 3 +- rtc/mcfrtc.c | 4 +-- 12 files changed, 100 insertions(+), 90 deletions(-) (limited to 'drivers') diff --git a/Makefile b/Makefile index 2bb11b6f883..79ab40b1a05 100644 --- a/Makefile +++ b/Makefile @@ -1682,7 +1682,7 @@ M5329BFEE_config : unconfig esac; \ >include/config.h ; \ if [ "$${NAND}" != "0" ] ; then \ - echo "#define NANDFLASH_SIZE $${NAND}" >> include/config.h ; \ + echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \ fi @$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c index 68dc04fd9a9..31f1510cc9f 100644 --- a/board/freescale/m5329evb/mii.c +++ b/board/freescale/m5329evb/mii.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) #undef MII_DEBUG #undef ET_DEBUG @@ -50,7 +50,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear) return 0; } -#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) #include /* Make MII read/write commands for the FEC. */ @@ -134,7 +134,7 @@ uint mii_send(uint mii_cmd) return (mii_reply & 0xffff); /* data read from phy */ } -#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ +#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ #if defined(CFG_DISCOVER_PHY) int mii_discover_phy(struct eth_device *dev) @@ -303,4 +303,4 @@ int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, return 0; } -#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index 2272a244675..fefb42e614c 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_CMD_NAND) #include #include diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 58ee9f350f6..889cff8411f 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -225,7 +225,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CFG_MBAR) print_num ("mbar", bd->bi_mbar_base ); #endif -#if defined(CFG_CMD_NET) +#if defined(CONFIG_CMD_NET) puts ("ethaddr ="); for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); @@ -239,22 +239,22 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif #if defined(CONFIG_HAS_ETH2) - puts ("\neth2addr ="); - for (i=0; i<6; ++i) { + puts ("\neth2addr ="); + for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]); } #endif #if defined(CONFIG_HAS_ETH3) - puts ("\neth3addr ="); - for (i=0; i<6; ++i) { + puts ("\neth3addr ="); + for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]); } #endif puts ("\nip_addr = "); print_IPaddr (bd->bi_ip_addr); -#endif /* CFG_CMD_NET */ +#endif /* CONFIG_CMD_NET */ printf ("\nbaudrate = %d bps\n", bd->bi_baudrate); return 0; diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index fde1aaecb62..68a0ee640d2 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -51,7 +51,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) struct fec_info_s fec_info[] = { #ifdef CFG_FEC0_IOBASE @@ -410,7 +410,7 @@ int fec_init(struct eth_device *dev, bd_t * bd) fec_reset(dev); -#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined (CONFIG_MII) || \ +#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ defined (CFG_DISCOVER_PHY) mii_init(); @@ -420,7 +420,7 @@ int fec_init(struct eth_device *dev, bd_t * bd) #ifndef CFG_DISCOVER_PHY setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); #endif /* ifndef CFG_DISCOVER_PHY */ -#endif /* CFG_CMD_MII || CONFIG_MII */ +#endif /* CONFIG_CMD_MII || CONFIG_MII */ /* We use strictly polling mode only */ fecp->eimr = 0; @@ -568,7 +568,7 @@ int mcffec_initialize(bd_t * bis) eth_register(dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, mcffec_miiphy_read, mcffec_miiphy_write); #endif @@ -580,5 +580,5 @@ int mcffec_initialize(bd_t * bis) return 1; } -#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ #endif /* CONFIG_MCFFEC */ diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index 7c267af56ea..2555e7e8294 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -38,8 +38,10 @@ #ifdef CONFIG_MCFTMR #define CFG_UDELAY_BASE (MMAP_DTMR0) #define CFG_TMR_BASE (MMAP_DTMR1) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) #define CFG_TMRINTR_NO (INT0_HI_DTMR1) #define CFG_TMRINTR_MASK (INTC_IPRH_INT33) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) #define CFG_TMRINTR_PRI (6) #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 114efb15d7e..e14a581dc16 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -28,18 +28,18 @@ #include -#define readb(addr) in_8((volatile u8 *)(addr)) -#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) +#define readb(addr) in_8((volatile u8 *)(addr)) +#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) #if !defined(__BIG_ENDIAN) -#define readw(addr) (*(volatile u16 *) (addr)) -#define readl(addr) (*(volatile u32 *) (addr)) -#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) +#define readw(addr) (*(volatile u16 *) (addr)) +#define readl(addr) (*(volatile u32 *) (addr)) +#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) +#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) #else -#define readw(addr) in_le16((volatile u16 *)(addr)) -#define readl(addr) in_le32((volatile u32 *)(addr)) -#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) +#define readw(addr) in_le16((volatile u16 *)(addr)) +#define readl(addr) in_le32((volatile u32 *)(addr)) +#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) +#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) #endif /* @@ -48,25 +48,25 @@ * are arrays of bytes, and byte-swapping is not appropriate in * that case. - paulus */ -#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) - -#define inb(port) in_8((u8 *)((port)+_IO_BASE)) -#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) +#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + +#define inb(port) in_8((u8 *)((port)+_IO_BASE)) +#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) #if !defined(__BIG_ENDIAN) -#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) +#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) #else -#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) +#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) #endif extern inline void _insb(volatile u8 * port, void *buf, int ns) @@ -151,10 +151,10 @@ extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) * Neither do the standard versions now, these are just here * for older code. */ -#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) #define IO_SPACE_LIMIT ~0 diff --git a/include/asm-m68k/timer.h b/include/asm-m68k/timer.h index d8f4e2a6ac4..3ec710d1f68 100644 --- a/include/asm-m68k/timer.h +++ b/include/asm-m68k/timer.h @@ -33,12 +33,26 @@ /****************************************************************************/ /* DMA Timer module registers */ typedef struct dtimer_ctrl { +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) u16 tmr; /* 0x00 Mode register */ + u16 res1; /* 0x02 */ + u16 trr; /* 0x04 Reference register */ + u16 res2; /* 0x06 */ + u16 tcr; /* 0x08 Capture register */ + u16 res3; /* 0x0A */ + u16 tcn; /* 0x0C Counter register */ + u16 res4; /* 0x0E */ + u8 res6; /* 0x10 */ + u8 ter; /* 0x11 Event register */ + u16 res7; /* 0x12 */ +#else + u16 tmr; /* 0x00 Mode register */ u8 txmr; /* 0x02 Extended Mode register */ u8 ter; /* 0x03 Event register */ u32 trr; /* 0x04 Reference register */ u32 tcr; /* 0x08 Capture register */ u32 tcn; /* 0x0C Counter register */ +#endif } dtmr_t; /*Programmable Interrupt Timer */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 6a7e052a055..d3b160505be 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -47,25 +47,23 @@ #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ -#define DEFAULT_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_FLASH | \ - CFG_CMD_I2C | \ - (CFG_CMD_LOADB | CFG_CMD_LOADS) | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO \ - ) +/* Command line configuration */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO #ifdef NANDFLASH_SIZE -# define CONFIG_COMMANDS (DEFAULT_COMMANDS | CFG_CMD_NAND) -#else -# define CONFIG_COMMANDS (DEFAULT_COMMANDS) +# define CONFIG_CMD_NAND #endif #define CFG_UNIFY_CACHE @@ -108,9 +106,9 @@ #define CFG_I2C_OFFSET 0x58000 #define CFG_IMMR CFG_MBAR -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_UDP_CHECKSUM + #ifdef CONFIG_MCFFEC # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 # define CONFIG_IPADDR 192.162.1.2 @@ -137,7 +135,7 @@ #define CFG_PROMPT "-> " #define CFG_LONGHELP /* undef to save memory */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -154,7 +152,7 @@ #define CFG_MBAR 0xFC000000 -#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000) +#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000) /* * Low Level Configuration Settings @@ -168,7 +166,7 @@ #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ #define CFG_INIT_RAM_CTRL 0x221 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /*----------------------------------------------------------------------- @@ -198,7 +196,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -214,20 +212,19 @@ #endif #ifdef NANDFLASH_SIZE -# define CFG_MAX_NAND_DEVICE 1 -# define CFG_NAND_BASE (CFG_CS2_BASE << 16) -# define CFG_NAND_SIZE 1 -# define CFG_NAND_BASE_LIST { CFG_NAND_BASE } -# define NAND_MAX_CHIPS 1 -# define NAND_ALLOW_ERASE_ALL 1 -# define CONFIG_JFFS2_NAND 1 -# define CONFIG_JFFS2_DEV "nand0" -# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1) -# define CONFIG_JFFS2_PART_OFFSET 0x00000000 +# define CFG_MAX_NAND_DEVICE 1 +# define CFG_NAND_BASE (CFG_CS2_BASE << 16) +# define CFG_NAND_SIZE 1 +# define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +# define NAND_MAX_CHIPS 1 +# define NAND_ALLOW_ERASE_ALL 1 +# define CONFIG_JFFS2_NAND 1 +# define CONFIG_JFFS2_DEV "nand0" +# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1) +# define CONFIG_JFFS2_PART_OFFSET 0x00000000 #endif -#define CFG_FLASH_BASE 0 -#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) +#define CFG_FLASH_BASE (CFG_CS0_BASE << 16) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -267,6 +264,4 @@ #define CFG_CS2_CTRL 0x00001f60 #endif -#define CONFIG_UDP_CHECKSUM - #endif /* _M5329EVB_H */ diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 395018c41f9..778ec788a81 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -692,7 +692,7 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif #if defined(CONFIG_NET_MULTI) puts ("Net: "); - eth_initialize (bd); + eth_initialize (bd); #endif #endif diff --git a/lib_m68k/time.c b/lib_m68k/time.c index 3dbce07213e..6c19059e62b 100644 --- a/lib_m68k/time.c +++ b/lib_m68k/time.c @@ -347,10 +347,9 @@ void udelay(unsigned long usec) void dtimer_interrupt(void *not_used) { volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE); - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); /* check for timer interrupt asserted */ - if ((intp->iprh0 & CFG_TMRINTR_MASK) == CFG_TMRINTR_MASK) { + if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) { timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF); timestamp++; return; diff --git a/rtc/mcfrtc.c b/rtc/mcfrtc.c index 0be587426c0..76bb5107f6a 100644 --- a/rtc/mcfrtc.c +++ b/rtc/mcfrtc.c @@ -28,7 +28,7 @@ #include #include -#if defined(CONFIG_MCFRTC) && (CONFIG_COMMANDS & CFG_CMD_DATE) +#if defined(CONFIG_MCFRTC) && defined(CONFIG_CMD_DATE) #undef RTC_DEBUG @@ -118,4 +118,4 @@ void rtc_reset(void) rtc->cr |= RTC_CR_SWR; } -#endif /* CONFIG_MCFRTC && CFG_CMD_DATE */ +#endif /* CONFIG_MCFRTC && CONFIG_CMD_DATE */ -- cgit v1.3.1 From 8ae158cd87a4a25722b27835261b6ff0fa2aa6a7 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 16 Aug 2007 15:05:11 -0500 Subject: ColdFire: Add M54455EVB for MCF5445x Signed-off-by: TsiChungLiew --- CREDITS | 2 +- MAINTAINERS | 9 + MAKEALL | 1 + Makefile | 28 + README | 1 + board/freescale/m54455evb/Makefile | 44 + board/freescale/m54455evb/config.mk | 25 + board/freescale/m54455evb/flash.c | 974 +++++++++++++++++++++ board/freescale/m54455evb/m54455evb.c | 165 ++++ board/freescale/m54455evb/mii.c | 320 +++++++ board/freescale/m54455evb/u-boot.lds | 144 +++ common/cmd_bdinfo.c | 22 +- cpu/mcf5445x/Makefile | 48 + cpu/mcf5445x/config.mk | 27 + cpu/mcf5445x/cpu.c | 97 +++ cpu/mcf5445x/cpu_init.c | 140 +++ cpu/mcf5445x/interrupts.c | 52 ++ cpu/mcf5445x/pci.c | 189 ++++ cpu/mcf5445x/speed.c | 186 ++++ cpu/mcf5445x/start.S | 388 +++++++++ doc/README.m54455evb | 416 +++++++++ drivers/net/mcffec.c | 27 +- include/asm-m68k/global_data.h | 8 + include/asm-m68k/immap.h | 40 + include/asm-m68k/immap_5445x.h | 937 ++++++++++++++++++++ include/asm-m68k/m5445x.h | 1541 +++++++++++++++++++++++++++++++++ include/asm-m68k/rtc.h | 3 +- include/asm-m68k/u-boot.h | 8 + include/configs/M54455EVB.h | 391 +++++++++ lib_m68k/board.c | 30 +- lib_m68k/interrupts.c | 0 lib_m68k/m68k_linux.c | 376 ++++---- 32 files changed, 6459 insertions(+), 180 deletions(-) create mode 100644 board/freescale/m54455evb/Makefile create mode 100644 board/freescale/m54455evb/config.mk create mode 100644 board/freescale/m54455evb/flash.c create mode 100644 board/freescale/m54455evb/m54455evb.c create mode 100644 board/freescale/m54455evb/mii.c create mode 100644 board/freescale/m54455evb/u-boot.lds create mode 100644 cpu/mcf5445x/Makefile create mode 100644 cpu/mcf5445x/config.mk create mode 100644 cpu/mcf5445x/cpu.c create mode 100644 cpu/mcf5445x/cpu_init.c create mode 100644 cpu/mcf5445x/interrupts.c create mode 100644 cpu/mcf5445x/pci.c create mode 100644 cpu/mcf5445x/speed.c create mode 100644 cpu/mcf5445x/start.S create mode 100644 doc/README.m54455evb create mode 100644 include/asm-m68k/immap_5445x.h create mode 100644 include/asm-m68k/m5445x.h create mode 100644 include/configs/M54455EVB.h mode change 100755 => 100644 lib_m68k/interrupts.c (limited to 'drivers') diff --git a/CREDITS b/CREDITS index b1abad32a21..f30b2228fbb 100644 --- a/CREDITS +++ b/CREDITS @@ -491,7 +491,7 @@ W: www.monstr.eu N: TsiChung Liew E: Tsi-Chung.Liew@freescale.com -D: Support for ColdFire MCF532x +D: Support for ColdFire MCF532x, MCF5445x W: www.freescale.com N: Hayden Fraser diff --git a/MAINTAINERS b/MAINTAINERS index d5249e51553..7fde6d99efe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -606,6 +606,15 @@ Zachary P. Landau r5200 mcf52x2 +TsiChung Liew + + M5329EVB mcf532x + M54455EVB mcf5445x + +Hayden Fraser + + M5253EVBE mcf52x2 + ######################################################################### # AVR32 Systems: # # # diff --git a/MAKEALL b/MAKEALL index 890ee39a78f..b7ed0f4305c 100755 --- a/MAKEALL +++ b/MAKEALL @@ -624,6 +624,7 @@ LIST_coldfire=" \ M5272C3 \ M5282EVB \ M5329EVB \ + M54455EVB \ r5200 \ TASREG \ " diff --git a/Makefile b/Makefile index e5995ebfc40..201ad0e7789 100644 --- a/Makefile +++ b/Makefile @@ -1692,6 +1692,34 @@ M5329BFEE_config : unconfig fi @$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale +M54455EVB_config \ +M54455EVB_atmel_config \ +M54455EVB_intel_config \ +M54455EVB_a33_config \ +M54455EVB_a66_config \ +M54455EVB_i33_config \ +M54455EVB_i66_config : unconfig + @case "$@" in \ + M54455EVB_config) FLASH=ATMEL; FREQ=33333333;; \ + M54455EVB_atmel_config) FLASH=ATMEL; FREQ=33333333;; \ + M54455EVB_intel_config) FLASH=INTEL; FREQ=33333333;; \ + M54455EVB_a33_config) FLASH=ATMEL; FREQ=33333333;; \ + M54455EVB_a66_config) FLASH=ATMEL; FREQ=66666666;; \ + M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \ + M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \ + esac; \ + >include/config.h ; \ + if [ "$${FLASH}" == "INTEL" ] ; then \ + echo "#undef CFG_ATMEL_BOOT" >> include/config.h ; \ + echo "... with INTEL boot..." ; \ + else \ + echo "#define CFG_ATMEL_BOOT" >> include/config.h ; \ + echo "... with ATMEL boot..." ; \ + fi; \ + echo "#define CFG_INPUT_CLKSRC $${FREQ}" >>include/config.h ; \ + echo "... with $${FREQ}Hz input clock" + @$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale + ######################################################################### ## MPC83xx Systems ######################################################################### diff --git a/README b/README index 4f2acb40d1f..4b1982b221f 100644 --- a/README +++ b/README @@ -137,6 +137,7 @@ Directory Hierarchy: - ixp Files specific to Intel XScale IXP CPUs - mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs - mcf532x Files specific to Freescale ColdFire MCF5329 CPUs + - mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs - mips Files specific to MIPS CPUs - mpc5xx Files specific to Freescale MPC5xx CPUs - mpc5xxx Files specific to Freescale MPC5xxx CPUs diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile new file mode 100644 index 00000000000..ca9a7729e1c --- /dev/null +++ b/board/freescale/m54455evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o mii.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### \ No newline at end of file diff --git a/board/freescale/m54455evb/config.mk b/board/freescale/m54455evb/config.mk new file mode 100644 index 00000000000..ce014edca8f --- /dev/null +++ b/board/freescale/m54455evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0 diff --git a/board/freescale/m54455evb/flash.c b/board/freescale/m54455evb/flash.c new file mode 100644 index 00000000000..de2cca863a9 --- /dev/null +++ b/board/freescale/m54455evb/flash.c @@ -0,0 +1,974 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include + +#ifndef CFG_FLASH_CFI +typedef unsigned char FLASH_PORT_WIDTH; +typedef volatile unsigned char FLASH_PORT_WIDTHV; + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CFG_FLASH_NONCFI_WIDTH FLASH_CFI_8BIT + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x00100010 +#define INTEL_ERASE 0x00200020 +#define INTEL_WRSETUP 0x00400040 +#define INTEL_CLEAR 0x00500050 +#define INTEL_LOCKBIT 0x00600060 +#define INTEL_PROTECT 0x00010001 +#define INTEL_STATUS 0x00700070 +#define INTEL_READID 0x00900090 +#define INTEL_CFIQRY 0x00980098 +#define INTEL_SUSERASE 0x00B000B0 +#define INTEL_PROTPROG 0x00C000C0 +#define INTEL_CONFIRM 0x00D000D0 +#define INTEL_WRBLK 0x00e800e8 +#define INTEL_RESET 0x00FF00FF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x00800080 +#define INTEL_OK 0x00800080 +#define INTEL_ERASESUS 0x00600060 +#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS) + +/* 28F160C3B CFI Data offset - This could vary */ +#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */ +#define INTEL_CFI_PART 0x01 /* Product ID */ +#define INTEL_CFI_LOCK 0x02 /* */ +#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */ +#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */ +#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */ +#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */ +#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */ +#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */ +#define INTEL_CFI_CAP 0x28 +#define INTEL_CFI_WRBUF 0x2A +#define INTEL_CFI_BANK 0x2C /* Number of Bank */ +#define INTEL_CFI_BLK1A 0x2D /* Number of Blocks */ +#define INTEL_CFI_BLK1B 0x2E /* Number of Blocks */ +#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */ +#define INTEL_CFI_SZ1B 0x30 +#define INTEL_CFI_BLK2A 0x31 +#define INTEL_CFI_BLK2B 0x32 +#define INTEL_CFI_SZ2A 0x33 +#define INTEL_CFI_SZ2B 0x34 + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x0aaa + +#define WR_BLOCK 0x20 + +/* not in the flash.h yet */ +#define FLASH_28F64P30T 0x00B9 /* Intel 28F64P30T ( 64M) */ +#define FLASH_28F64P30B 0x00BA /* Intel 28F64P30B ( 64M) */ +#define FLASH_28F128P30T 0x00BB /* Intel 28F128P30T ( 128M = 8M x 16 ) */ +#define FLASH_28F128P30B 0x00BC /* Intel 28F128P30B ( 128M = 8M x 16 ) */ +#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */ +#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */ + +#define SYNC __asm__("nop") + +/*----------------------------------------------------------------------- + * Functions + */ + +ulong flash_get_size(FPWV * addr, flash_info_t * info); +int flash_get_offsets(ulong base, flash_info_t * info); +int flash_cmd_rd(volatile u16 * addr, int index); +int write_data(flash_info_t * info, ulong dest, FPW data); +int write_data_block(flash_info_t * info, ulong src, ulong dest); +int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data); +void inline spin_wheel(void); +void flash_sync_real_protect(flash_info_t * info); +uchar intel_sector_protected(flash_info_t * info, ushort sector); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +ulong flash_init(void) +{ + int i; + ulong size = 0; + ulong fbase = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + memset(&flash_info[i], 0, sizeof(flash_info_t)); + + switch (i) { + case 0: + fbase = (ulong) CFG_FLASH0_BASE; + break; + case 1: + fbase = (ulong) CFG_FLASH1_BASE; + break; + } + + flash_get_size((FPWV *) fbase, &flash_info[i]); + flash_get_offsets((ulong) fbase, &flash_info[i]); + fbase += flash_info[i].size; + size += flash_info[i].size; + + /* get the h/w and s/w protection status in sync */ + flash_sync_real_protect(&flash_info[i]); + } + + /* Protect monitor and environment sectors */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + + return size; +} + +int flash_get_offsets(ulong base, flash_info_t * info) +{ + int i, j, k; + int sectors, bs, banks; + ulong start; + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) { + int sect[] = CFG_ATMEL_SECT; + int sectsz[] = CFG_ATMEL_SECTSZ; + + info->start[0] = base; + for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) { + for (j = 0; j < sect[i]; j++, k++) { + info->start[k + 1] = info->start[k] + sectsz[i]; + info->protect[k] = 0; + } + } + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + volatile u16 *addr16 = (volatile u16 *)base; + + *addr16 = (FPW) INTEL_RESET; /* restore read mode */ + *addr16 = (FPW) INTEL_READID; + + banks = addr16[INTEL_CFI_BANK] & 0xff; + + sectors = 0; + info->start[0] = base; + + for (k = 0, i = 0; i < banks; i++) { + /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. + * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count + * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count + */ + bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8) + | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) * + 0x100); + sectors = + (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1; + + for (j = 0; j < sectors; j++, k++) { + info->start[k + 1] = info->start[k] + bs; + } + } + + *addr16 = (FPW) INTEL_RESET; /* restore read mode */ + } + + return ERR_OK; +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf("INTEL "); + break; + case FLASH_MAN_ATM: + printf("ATMEL "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AT040: + printf("AT49BV040A\n"); + break; + case FLASH_28F128J3A: + printf("Intel 28F128J3A\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + } + + if (info->size > 0x100000) { + int remainder; + + printf(" Size: %ld", info->size >> 20); + + remainder = (info->size % 0x100000); + if (remainder) { + remainder >>= 10; + remainder = (int)((float) + (((float)remainder / (float)1024) * + 10000)); + printf(".%d ", remainder); + } + + printf("MB in %d Sectors\n", info->sector_count); + } else + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size(FPWV * addr, flash_info_t * info) +{ + volatile u16 *addr16 = (volatile u16 *)addr; + int intel = 0, banks = 0; + u16 value; + int i; + + addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */ + + switch (addr[0] & 0xff) { + case (u8) ATM_MANUFACT: + info->flash_id = FLASH_MAN_ATM; + value = addr[1]; + break; + case (u8) INTEL_MANUFACT: + /* Terminate Atmel ID read */ + addr[0] = (FPWV) 0x00F000F0; + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + *addr16 = (FPW) INTEL_RESET; /* restore read mode */ + *addr16 = (FPW) INTEL_READID; + + info->flash_id = FLASH_MAN_INTEL; + value = (addr16[INTEL_CFI_MFG] << 8); + value |= addr16[INTEL_CFI_PART] & 0xff; + intel = 1; + break; + default: + printf("Unknown Flash\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + + *addr = (FPW) 0x00F000F0; + *addr = (FPW) INTEL_RESET; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + switch (value) { + case (u8) ATM_ID_LV040: + info->flash_id += FLASH_AT040; + break; + case (u16) INTEL_ID_28F128J3: + info->flash_id += FLASH_28F128J3A; + break; + case (u16) INTEL_ID_28F64P30T: + info->flash_id += FLASH_28F64P30T; + break; + case (u16) INTEL_ID_28F64P30B: + info->flash_id += FLASH_28F64P30B; + break; + case (u16) INTEL_ID_28F128P30T: + info->flash_id += FLASH_28F128P30T; + break; + case (u16) INTEL_ID_28F128P30B: + info->flash_id += FLASH_28F128P30B; + break; + case (u16) INTEL_ID_28F256P30T: + info->flash_id += FLASH_28F256P30T; + break; + case (u16) INTEL_ID_28F256P30B: + info->flash_id += FLASH_28F256P30B; + break; + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (intel) { + /* Intel spec. under CFI section */ + u32 sz; + int sectors, bs; + + banks = addr16[INTEL_CFI_BANK] & 0xff; + + sectors = sz = 0; + for (i = 0; i < banks; i++) { + /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. + * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count + * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count + */ + bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8) + | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) * + 0x100); + sectors += + (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1; + sz += (bs * sectors); + } + + info->sector_count = sectors; + info->size = sz; + *addr = (FPW) INTEL_RESET; /* restore read mode */ + } else { + int sect[] = CFG_ATMEL_SECT; + int sectsz[] = CFG_ATMEL_SECTSZ; + + info->sector_count = 0; + info->size = 0; + for (i = 0; i < CFG_ATMEL_REGION; i++) { + info->sector_count += sect[i]; + info->size += sect[i] * sectsz[i]; + } + + /* reset ID mode */ + addr[0] = (FPWV) 0x00F000F0; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + return (info->size); +} + +int flash_cmd_rd(volatile u16 * addr, int index) +{ + return (int)addr[index]; +} + +/* + * This function gets the u-boot flash sector protection status + * (flash_info_t.protect[]) in sync with the sector protection + * status stored in hardware. + */ +void flash_sync_real_protect(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + for (i = 0; i < info->sector_count; ++i) { + info->protect[i] = intel_sector_protected(info, i); + } + break; + default: + /* no h/w protect support */ + break; + } +} + +/* + * checks if "sector" in bank "info" is protected. Should work on intel + * strata flash chips 28FxxxJ3x in 8-bit mode. + * Returns 1 if sector is protected (or timed-out while trying to read + * protection status), 0 if it is not. + */ +uchar intel_sector_protected(flash_info_t * info, ushort sector) +{ + FPWV *addr; + FPWV *lock_conf_addr; + ulong start; + unsigned char ret; + + /* + * first, wait for the WSM to be finished. The rationale for + * waiting for the WSM to become idle for at most + * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * because of: (1) erase, (2) program or (3) lock bit + * configuration. So we just wait for the longest timeout of + * the (1)-(3), i.e. the erase timeout. + */ + + /* wait at least 35ns (W12) before issuing Read Status Register */ + /*udelay(1); */ + addr = (FPWV *) info->start[sector]; + *addr = (FPW) INTEL_STATUS; + + start = get_timer(0); + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + printf("WSM busy too long, can't get prot status\n"); + return 1; + } + } + + /* issue the Read Identifier Codes command */ + *addr = (FPW) INTEL_READID; + + /* Intel example code uses offset of 4 for 8-bit flash */ + lock_conf_addr = (FPWV *) info->start[sector]; + ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0; + + /* put flash back in read mode */ + *addr = (FPW) INTEL_RESET; + + return ret; +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0, intel = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + + if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) { + if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) { + type = (info->flash_id & FLASH_VENDMASK); + printf + ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + } + + if (type == FLASH_MAN_INTEL) + intel = 1; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf("\n"); + + start = get_timer(0); + last = start; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + + FPWV *addr = (FPWV *) (info->start[sect]); + int min = 0; + + printf("."); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + if (intel) { + *addr = (FPW) INTEL_READID; + min = addr[INTEL_CFI_TERB] & 0xff; + min = 1 << min; /* ms */ + min = (min / info->sector_count) * 1000; + + /* start erase block */ + *addr = (FPW) INTEL_CLEAR; /* clear status register */ + *addr = (FPW) INTEL_ERASE; /* erase setup */ + *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ + + while ((*addr & (FPW) INTEL_FINISHED) != + (FPW) INTEL_FINISHED) { + + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = (FPW) INTEL_SUSERASE; /* suspend erase */ + *addr = (FPW) INTEL_RESET; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *addr = (FPW) INTEL_RESET; /* resest to read mode */ + } else { + FPWV *base; /* first address in bank */ + FPWV *atmeladdr; + + flag = disable_interrupts(); + + atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */ + base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */ + + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + *atmeladdr = (u8) 0x00300030; /* erase sector */ + + if (flag) + enable_interrupts(); + + while ((*atmeladdr & (u8) 0x00800080) != + (u8) 0x00800080) { + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ + } /* Atmel or Intel */ + } + } + printf(" done\n"); + + return rcode; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + if (info->flash_id == FLASH_UNKNOWN) + return 4; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_ATM: + { + u16 data = 0; + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= + sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left) + data += *((uchar *) addr + i); + else + data += *src++; + } + + data = (data >> 8) | (data << 8); + res = write_word_atm(info, (FPWV *) addr, data); + } + return res; + } /* case FLASH_MAN_ATM */ + + case FLASH_MAN_INTEL: + { + ulong cp, wp; + u16 data; + int count, i, l, rc, port_width; + + /* get lower word aligned address */ + wp = addr; + port_width = sizeof(FPW); + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < port_width; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + if ((rc = write_data(info, wp, data)) != 0) + return (rc); + + wp += port_width; + } + + if (cnt > WR_BLOCK) { + /* + * handle word aligned part + */ + count = 0; + while (cnt >= WR_BLOCK) { + + if ((rc = + write_data_block(info, + (ulong) src, + wp)) != 0) + return (rc); + + wp += WR_BLOCK; + src += WR_BLOCK; + cnt -= WR_BLOCK; + + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + } + + /* handle word aligned part */ + if (cnt < WR_BLOCK) { + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) + data = (data << 8) | *src++; + + if ((rc = + write_data(info, + (ulong) ((FPWV *) wp), + (FPW) (data))) != 0) + return (rc); + + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; + ++i, ++cp) { + data = (data << 8) | (*src++); + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return write_data(info, (ulong) ((FPWV *) wp), + (FPW) data); + + } /* case FLASH_MAN_INTEL */ + + } /* switch */ + + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_data_block(flash_info_t * info, ulong src, ulong dest) +{ + FPWV *srcaddr = (FPWV *) src; + FPWV *dstaddr = (FPWV *) dest; + ulong start; + int flag, i; + + /* Check if Flash is (sufficiently) erased */ + for (i = 0; i < WR_BLOCK; i++) + if ((*dstaddr++ & 0xff) != 0xff) { + printf("not erased at %08lx (%lx)\n", + (ulong) dstaddr, *dstaddr); + return (2); + } + + dstaddr = (FPWV *) dest; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *dstaddr = (FPW) INTEL_WRBLK; /* write block setup */ + + if (flag) + enable_interrupts(); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ + return (1); + } + } + + *dstaddr = (FPW) WR_BLOCK - 1; /* write 32 to buffer */ + for (i = 0; i < WR_BLOCK; i++) + *dstaddr++ = *srcaddr++; + + dstaddr -= 1; + *dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */ + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ + return (1); + } + } + + *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_data(flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf("not erased at %08lx (%lx)\n", (ulong) addr, + (ulong) * addr); + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = (int)disable_interrupts(); + + *addr = (FPW) INTEL_CLEAR; + *addr = (FPW) INTEL_RESET; + + *addr = (FPW) INTEL_WRSETUP; /* write setup */ + *addr = data; + + if (flag) + enable_interrupts(); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) INTEL_SUSERASE; /* suspend mode */ + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* reset */ + return (1); + } + } + + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for ATMEL FLASH + * A word is 16 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data) +{ + ulong start; + int flag, i; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile u16 *)dest) & data) != data) { + return (2); + } + + base = (FPWV *) (CFG_ATMEL_BASE); + + for (i = 0; i < sizeof(u16); i++) { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* data polling for D7 */ + while (res == 0 + && (*dest & (u8) 0x00800080) != + (data & (u8) 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (u8) 0x00F000F0; /* reset bank */ + res = 1; + } + } + + *dest++ = (u8) 0x00F000F0; /* reset bank */ + data >>= 8; + } + + return (res); +} + +void inline spin_wheel(void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t * info, long sector, int prot) +{ + int rcode = 0; /* assume success */ + FPWV *addr; /* address of sector */ + FPW value; + + addr = (FPWV *) (info->start[sector]); + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + *addr = (FPW) INTEL_RESET; /* make sure in read mode */ + *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */ + + if (prot) + *addr = (FPW) INTEL_PROTECT; /* lock sector */ + else + *addr = (FPW) INTEL_CONFIRM; /* unlock sector */ + + /* now see if it really is locked/unlocked as requested */ + *addr = (FPW) INTEL_READID; + + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but return failure. Mixed protected and + * unprotected devices within a sector should never happen. + */ + value = addr[2] & (FPW) INTEL_PROTECT; + if (value == 0) + info->protect[sector] = 0; + else if (value == (FPW) INTEL_PROTECT) + info->protect[sector] = 1; + else { + /* error, mixed protected and unprotected */ + rcode = 1; + info->protect[sector] = 1; + } + if (info->protect[sector] != prot) + rcode = 1; /* failed to protect/unprotect as requested */ + + /* reload all protection bits from hardware for now */ + flash_sync_real_protect(info); + break; + + default: + /* no hardware protect that we support */ + info->protect[sector] = prot; + break; + } + + return rcode; +} +#endif +#endif diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c new file mode 100644 index 00000000000..1411a1a4c2d --- /dev/null +++ b/board/freescale/m54455evb/m54455evb.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M54455 EVB\n"); + return 0; +}; + +long int initdram(int board_type) +{ + volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); + volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + u32 dramsize, i; + + dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + gpio->mscr_sdram = 0xAA; + + sdram->sdcs0 = (CFG_SDRAM_BASE | i); + sdram->sdcs1 = (CFG_SDRAM_BASE1 | i); + + sdram->sdcfg1 = CFG_SDRAM_CFG1; + sdram->sdcfg2 = CFG_SDRAM_CFG2; + + /* Issue PALL */ + sdram->sdcr = CFG_SDRAM_CTRL | 2; + + /* Issue LEMR */ + sdram->sdmr = CFG_SDRAM_EMOD | 0x408; + sdram->sdmr = CFG_SDRAM_MODE | 0x300; + + udelay(500); + + /* Issue PALL */ + sdram->sdcr = CFG_SDRAM_CTRL | 2; + + /* Perform two refresh cycles */ + sdram->sdcr = CFG_SDRAM_CTRL | 4; + sdram->sdcr = CFG_SDRAM_CTRL | 4; + + sdram->sdmr = CFG_SDRAM_MODE | 0x200; + + sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + + udelay(100); + + return (dramsize << 1); +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#if defined(CONFIG_CMD_IDE) +#include + +int ide_preinit(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10; + gpio->par_feci2c |= + (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | + GPIO_PAR_FECI2C_MDIO1_ATA_DIOW); + gpio->par_ata |= + (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 | + GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 + | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ | + GPIO_PAR_ATA_IORDY_IORDY); + gpio->par_pci |= + (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ); + + return (0); +} + +void ide_set_reset(int idereset) +{ + volatile atac_t *ata = (atac_t *) MMAP_ATA; + long period; + /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ + int piotms[5][9] = { + {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ + {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ + {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ + {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ + {25, 70, 20, 10, 20, 5, 10, 0, 35} + }; /* PIO 4 */ + + if (idereset) { + ata->cr = 0; /* control reset */ + udelay(10000); + } else { +#define CALC_TIMING(t) (t + period - 1) / period + period = 1000000000 / gd->bus_clk; /* period in ns */ + + /*ata->ton = CALC_TIMING (180); */ + ata->t1 = CALC_TIMING(piotms[2][0]); + ata->t2w = CALC_TIMING(piotms[2][1]); + ata->t2r = CALC_TIMING(piotms[2][1]); + ata->ta = CALC_TIMING(piotms[2][8]); + ata->trd = CALC_TIMING(piotms[2][7]); + ata->t4 = CALC_TIMING(piotms[2][3]); + ata->t9 = CALC_TIMING(piotms[2][6]); + + ata->cr = 0x40; /* IORDY enable */ + udelay(200000); + ata->cr |= 0x01; /* IORDY enable */ + } +} +#endif + +#if defined(CONFIG_PCI) +/* + * Initialize PCI devices, report devices found. + */ +static struct pci_controller hose; +extern void pci_mcf5445x_init(struct pci_controller *hose); + +void pci_init_board(void) +{ + pci_mcf5445x_init(&hose); +} +#endif /* CONFIG_PCI */ + diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c new file mode 100644 index 00000000000..c067183aadf --- /dev/null +++ b/board/freescale/m54455evb/mii.c @@ -0,0 +1,320 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + struct fec_info_s *info = (struct fec_info_s *)dev->priv; + + if (setclear) { + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CFG_FEC0_IOBASE) + gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; + else + gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; + } else { + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CFG_FEC0_IOBASE) + gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; + else + gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + struct eth_device *dev; + int i, miispd; + u16 rst = 0; + + dev = eth_get_dev(); + + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET); + for (i = 0; i < FEC_RESET_DELAY; ++i) { + udelay(500); + miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst); + if ((rst & PHY_BMCR_RESET) == 0) + break; + } + if (i == FEC_RESET_DELAY) + printf("Mii reset timeout %d\n", i); +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + strcpy(info->phy_name, + STR_ID_DP83848VV); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + printf(STR_ID_DP83848VV); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds new file mode 100644 index 00000000000..bda68e4f824 --- /dev/null +++ b/board/freescale/m54455evb/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf5445x/start.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 889cff8411f..7686080f351 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -208,24 +208,36 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } #elif defined(CONFIG_M68K) /* M68K */ +static void print_str(const char *, const char *); int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int i; bd_t *bd = gd->bd; + char buf[32]; + print_num ("memstart", (ulong)bd->bi_memstart); print_num ("memsize", (ulong)bd->bi_memsize); print_num ("flashstart", (ulong)bd->bi_flashstart); print_num ("flashsize", (ulong)bd->bi_flashsize); print_num ("flashoffset", (ulong)bd->bi_flashoffset); #if defined(CFG_INIT_RAM_ADDR) - print_num ("sramstart", (ulong)bd->bi_sramstart); - print_num ("sramsize", (ulong)bd->bi_sramsize); + print_num ("sramstart", (ulong)bd->bi_sramstart); + print_num ("sramsize", (ulong)bd->bi_sramsize); #endif #if defined(CFG_MBAR) - print_num ("mbar", bd->bi_mbar_base ); + print_num ("mbar", bd->bi_mbar_base); #endif -#if defined(CONFIG_CMD_NET) + print_str ("busfreq", strmhz(buf, bd->bi_busfreq)); +#ifdef CONFIG_PCI + print_str ("pcifreq", strmhz(buf, bd->bi_pcifreq)); +#endif +#ifdef CONFIG_EXTRA_CLOCK + print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq)); + print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq)); + print_str ("vcofreq", strmhz(buf, bd->bi_vcofreq)); +#endif +#if defined(CFG_CMD_NET) puts ("ethaddr ="); for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); @@ -323,7 +335,7 @@ static void print_num(const char *name, ulong value) printf ("%-12s= 0x%08lX\n", name, value); } -#ifdef CONFIG_PPC +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) static void print_str(const char *name, const char *str) { printf ("%-12s= %6s MHz\n", name, str); diff --git a/cpu/mcf5445x/Makefile b/cpu/mcf5445x/Makefile new file mode 100644 index 00000000000..26ec29895ee --- /dev/null +++ b/cpu/mcf5445x/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = start.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mcf5445x/config.mk b/cpu/mcf5445x/config.mk new file mode 100644 index 00000000000..d0c72fb6b0e --- /dev/null +++ b/cpu/mcf5445x/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 Josef Baumgartner +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data +PLATFORM_CPPFLAGS += -m5407 -fPIC diff --git a/cpu/mcf5445x/cpu.c b/cpu/mcf5445x/cpu.c new file mode 100644 index 00000000000..e601b8949b6 --- /dev/null +++ b/cpu/mcf5445x/cpu.c @@ -0,0 +1,97 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM); + udelay(1000); + rcm->rcr |= RCM_RCR_SOFTRST; + + /* we don't return! */ + return 0; +}; + +int checkcpu(void) +{ + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + u16 msk; + u16 id = 0; + u8 ver; + + puts("CPU: "); + msk = (ccm->cir >> 6); + ver = (ccm->cir & 0x003f); + switch (msk) { + case 0x48: + id = 54455; + break; + case 0x49: + id = 54454; + break; + case 0x4a: + id = 54453; + break; + case 0x4b: + id = 54452; + break; + case 0x4d: + id = 54451; + break; + case 0x4f: + id = 54450; + break; + } + + if (id) { + printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, + ver); + printf(" CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n", + (int)(gd->cpu_clk / 1000000), + (int)(gd->bus_clk / 1000000), + (int)(gd->flb_clk / 1000000)); +#ifdef CONFIG_PCI + printf(" PCI CLK %d Mhz INP CLK %d Mhz VCO CLK %d Mhz\n", + (int)(gd->pci_clk / 1000000), + (int)(gd->inp_clk / 1000000), + (int)(gd->vco_clk / 1000000)); +#else + printf(" INP CLK %d Mhz VCO CLK %d Mhz\n", + (int)(gd->inp_clk / 1000000), + (int)(gd->vco_clk / 1000000)); +#endif + } + + return 0; +} diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c new file mode 100644 index 00000000000..6622eeea981 --- /dev/null +++ b/cpu/mcf5445x/cpu_init.c @@ -0,0 +1,140 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + + scm1->mpr = 0x77777777; + scm1->pacra = 0; + scm1->pacrb = 0; + scm1->pacrc = 0; + scm1->pacrd = 0; + scm1->pacre = 0; + scm1->pacrf = 0; + scm1->pacrg = 0; + + /* FlexBus */ + gpio->par_be = + GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 | + GPIO_PAR_BE_BE0_BE0; + gpio->par_fbctl = + GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW | + GPIO_PAR_FBCTL_TS_TS; + +#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) + fbcs->csar0 = CFG_CS0_BASE; + fbcs->cscr0 = CFG_CS0_CTRL; + fbcs->csmr0 = CFG_CS0_MASK; +#endif + +#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) + /* Latch chipselect */ + fbcs->csar1 = CFG_CS1_BASE; + fbcs->cscr1 = CFG_CS1_CTRL; + fbcs->csmr1 = CFG_CS1_MASK; +#endif + +#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) + fbcs->csar2 = CFG_CS2_BASE; + fbcs->cscr2 = CFG_CS2_CTRL; + fbcs->csmr2 = CFG_CS2_MASK; +#endif + +#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) + fbcs->csar3 = CFG_CS3_BASE; + fbcs->cscr3 = CFG_CS3_CTRL; + fbcs->csmr3 = CFG_CS3_MASK; +#endif + +#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) + fbcs->csar4 = CFG_CS4_BASE; + fbcs->cscr4 = CFG_CS4_CTRL; + fbcs->csmr4 = CFG_CS4_MASK; +#endif + +#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) + fbcs->csar5 = CFG_CS5_BASE; + fbcs->cscr5 = CFG_CS5_CTRL; + fbcs->csmr5 = CFG_CS5_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ +#ifdef CONFIG_MCFTMR + volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE); + volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; + u32 oscillator = CFG_RTC_OSCILLATOR; + + rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF; + rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF; +#endif + + return (0); +} + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart = + (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + break; + case 1: + gpio->par_uart = + (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + break; + } +} diff --git a/cpu/mcf5445x/interrupts.c b/cpu/mcf5445x/interrupts.c new file mode 100644 index 00000000000..9572a7bc32b --- /dev/null +++ b/cpu/mcf5445x/interrupts.c @@ -0,0 +1,52 @@ +/* + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* CPU specific interrupt routine */ +#include +#include + +int interrupt_init(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrh0 |= 0xFFFFFFFF; + intp->imrl0 |= 0xFFFFFFFF; + + enable_interrupts(); + return 0; +} + +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->imrh0 &= ~CFG_TMRINTR_MASK; +} +#endif diff --git a/cpu/mcf5445x/pci.c b/cpu/mcf5445x/pci.c new file mode 100644 index 00000000000..8ace53630f8 --- /dev/null +++ b/cpu/mcf5445x/pci.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI Configuration space access support + */ +#include +#include +#include +#include + +#if defined(CONFIG_PCI) +/* System RAM mapped over PCI */ +#define CFG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CFG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CFG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define cfg_read(val, addr, type, op) *val = op((type)(addr)); +#define cfg_write(val, addr, type, op) op((type *)(addr), (val)); + +#define PCI_OP(rw, size, type, op, mask) \ +int pci_##rw##_cfg_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + u32 addr = 0; \ + u16 cfg_type = 0; \ + addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ + out_be32(hose->cfg_addr, addr); \ + __asm__ __volatile__("nop"); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + out_be32(hose->cfg_addr, addr & 0x7fffffff); \ + __asm__ __volatile__("nop"); \ + return 0; \ +} + +PCI_OP(read, byte, u8 *, in_8, 3) +PCI_OP(read, word, u16 *, in_le16, 2) +PCI_OP(write, byte, u8, out_8, 3) +PCI_OP(write, word, u16, out_le16, 2) +PCI_OP(write, dword, u32, out_le32, 0) + +int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev, + int offset, u32 * val) +{ + u32 addr; + u32 tmpv; + u32 mask = 2; /* word access */ + /* Read lower 16 bits */ + addr = ((offset & 0xfc) | (dev) | 0x80000000); + out_be32(hose->cfg_addr, addr); + __asm__ __volatile__("nop"); + *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); + out_be32(hose->cfg_addr, addr & 0x7fffffff); + __asm__ __volatile__("nop"); + + /* Read upper 16 bits */ + offset += 2; + addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000); + out_be32(hose->cfg_addr, addr); + __asm__ __volatile__("nop"); + tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); + out_be32(hose->cfg_addr, addr & 0x7fffffff); + __asm__ __volatile__("nop"); + + /* combine results into dword value */ + *val = (tmpv << 16) | *val; + + return 0; +} + +void pci_mcf5445x_init(struct pci_controller *hose) +{ + volatile pci_t *pci = (volatile pci_t *)MMAP_PCI; + volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + u32 barEn = 0; + + pciarb->acr = 0x001f001f; + + /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT, + PCIREQ2, PCIGNT2 */ + gpio->par_pci = + GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 | + GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 | + GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0; + + pci->tcr1 |= PCI_TCR1_P; + + /* Initiator windows */ + pci->iw0btar = CFG_PCI_MEM_PHYS; + pci->iw1btar = CFG_PCI_IO_PHYS; + pci->iw2btar = CFG_PCI_CFG_PHYS; + + pci->iwcr = + PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | + PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO; + + /* Enable bus master and mem access */ + pci->scr = PCI_SCR_MW | PCI_SCR_B | PCI_SCR_M; + + /* Cache line size and master latency */ + pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xFF); + pci->cr2 = 0; + +#ifdef CFG_PCI_BAR0 + pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0); + pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B0E; +#endif +#ifdef CFG_PCI_BAR1 + pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1); + pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B1E; +#endif +#ifdef CFG_PCI_BAR2 + pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2); + pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B2E; +#endif +#ifdef CFG_PCI_BAR3 + pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3); + pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B3E; +#endif +#ifdef CFG_PCI_BAR4 + pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4); + pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B4E; +#endif +#ifdef CFG_PCI_BAR5 + pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5); + pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN; + barEn |= PCI_TCR1_B5E; +#endif + + pci->tcr2 = barEn; + + /* Deassert reset bit */ + pci->gscr &= ~PCI_GSCR_PR; + udelay(1000); + + /* Enable PCI bus master support */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS, + CFG_PCI_MEM_SIZE, PCI_REGION_MEM); + + pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS, + CFG_PCI_IO_SIZE, PCI_REGION_IO); + + pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS, + CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 3; + + hose->cfg_addr = &(pci->car); + hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS; + + pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, + pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, + pci_write_cfg_dword); + + /* Hose scan */ + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); +} +#endif /* CONFIG_PCI */ diff --git a/cpu/mcf5445x/speed.c b/cpu/mcf5445x/speed.c new file mode 100644 index 00000000000..967becfdd07 --- /dev/null +++ b/cpu/mcf5445x/speed.c @@ -0,0 +1,186 @@ +/* + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Low Power Divider specifications + */ +#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */ +#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */ + +#define CLOCK_PLL_FVCO_MAX 540000000 +#define CLOCK_PLL_FVCO_MIN 300000000 + +#define CLOCK_PLL_FSYS_MAX 266666666 +#define CLOCK_PLL_FSYS_MIN 100000000 +#define MHZ 1000000 + +void clock_enter_limp(int lpdiv) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + int i, j; + + /* Check bounds of divider */ + if (lpdiv < CLOCK_LPD_MIN) + lpdiv = CLOCK_LPD_MIN; + if (lpdiv > CLOCK_LPD_MAX) + lpdiv = CLOCK_LPD_MAX; + + /* Round divider down to nearest power of two */ + for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; + + /* Apply the divider to the system clock */ + ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i); + + /* Enable Limp Mode */ + ccm->misccr |= CCM_MISCCR_LIMP; +} + +/* + * brief Exit Limp mode + * warning The PLL should be set and locked prior to exiting Limp mode + */ +void clock_exit_limp(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + + /* Exit Limp mode */ + ccm->misccr &= ~CCM_MISCCR_LIMP; + + /* Wait for the PLL to lock */ + while (!(pll->psr & PLL_PSR_LOCK)) ; +} + +/* + * get_clocks() fills in gd->cpu_clock and gd->bus_clk + */ +int get_clocks(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3); + volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14); + int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 }; + int pllmult_pci[] = { 12, 6, 16, 8 }; + int vco, bPci, temp, fbtemp, pcrvalue; + int *pPllmult = NULL; + u16 fbpll_mask; + u8 cpldmode; + + /* To determine PCI is present or not */ + if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || + ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { + pPllmult = &pllmult_pci[0]; + fbpll_mask = 3; + bPci = 1; + } else { + pPllmult = &pllmult_nopci[0]; + fbpll_mask = 7; +#ifdef CONFIG_PCI + gd->pci_clk = 0; +#endif + bPci = 0; + } + +#ifdef CONFIG_M54455EVB + /* Temporary place here, belongs in board/freescale/... */ + /* Temporary read from CCR- fixed fb issue, must be the same clock + as pci or input clock, causing cpld/fpga read inconsistancy */ + fbtemp = pPllmult[ccm->ccr & fbpll_mask]; + + /* Break down into small pieces, code still in flex bus */ + pcrvalue = pll->pcr & 0xFFFFF0FF; + temp = fbtemp - 1; + pcrvalue |= PLL_PCR_OUTDIV3(temp); + + pll->pcr = pcrvalue; + + cpldmode = *cpld & 0x03; + if (cpldmode == 0) { + /* RCON mode */ + vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC; + + if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { + /* invaild range, re-set in PCR */ + int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + int i, j, bus; + + j = (pll->pcr & 0xFF000000) >> 24; + for (i = j; i < 0xFF; i++) { + vco = i * CFG_INPUT_CLKSRC; + if (vco >= CLOCK_PLL_FVCO_MIN) { + bus = vco / temp; + if (bus <= CLOCK_PLL_FSYS_MIN - MHZ) + continue; + else + break; + } + } + pcrvalue = pll->pcr & 0x00FF00FF; + fbtemp = ((i - 1) << 8) | ((i - 1) << 12); + pcrvalue |= ((i << 24) | fbtemp); + + pll->pcr = pcrvalue; + } + gd->vco_clk = vco; /* Vco clock */ + } else if (cpldmode == 2) { + /* Normal mode */ + vco = pPllmult[ccm->ccr & fbpll_mask] * CFG_INPUT_CLKSRC; + gd->vco_clk = vco; /* Vco clock */ + } else if (cpldmode == 3) { + /* serial mode */ + } +#endif /* CONFIG_M54455EVB */ + + if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { + /* Limp mode */ + } else { + gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */ + + temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1; + gd->cpu_clk = vco / temp; /* cpu clock */ + + temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + gd->bus_clk = vco / temp; /* bus clock */ + + temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1; + gd->flb_clk = vco / temp; /* FlexBus clock */ + +#ifdef CONFIG_PCI + if (bPci) { + temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1; + gd->pci_clk = vco / temp; /* PCI clock */ + } +#endif + } + + return (0); +} diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S new file mode 100644 index 00000000000..cd989ab6261 --- /dev/null +++ b/cpu/mcf5445x/start.S @@ -0,0 +1,388 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "version.h" + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* last three long word reserved for cache status */ +#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12) +#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8) +#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4) + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR0 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(CACR_STATUS), %a1 /* CACR */ + move.l #(ICACHE_STATUS), %a2 /* icache */ + move.l #(DCACHE_STATUS), %a3 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + move.l %d0, (%a3) + + /* invalidate and disable cache */ + move.l #0x01004100, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + movec %d0, %ACR2 + movec %d0, %ACR3 + + /* set stackpointer to end of internal ram to get some stackspace for + the first c-code */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CFG_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CFG_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CFG_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CFG_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CFG_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CFG_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ +/* cache functions */ + .globl icache_enable +icache_enable: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d1 + + move.l #0x00040100, %d0 /* Invalidate icache */ + or.l %d1, %d0 + movec %d0, %CACR + + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup icache */ + movec %d0, %ACR2 + + or.l #0x00088400, %d1 /* Enable bcache and icache */ + movec %d1, %CACR + + move.l #(ICACHE_STATUS), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl icache_disable +icache_disable: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d0 + + and.l #0xFFF77BFF, %d0 + or.l #0x00040100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Invalidate icache */ + clr.l %d0 + movec %d0, %ACR2 + movec %d0, %ACR3 + + move.l #(ICACHE_STATUS), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl icache_status +icache_status: + move.l #(ICACHE_STATUS), %a1 + move.l (%a1), %d0 + rts + + .globl icache_invalid +icache_invalid: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d0 + + or.l #0x00040100, %d0 /* Invalidate icache */ + movec %d0, %CACR /* Enable and invalidate cache */ + rts + + .globl dcache_enable +dcache_enable: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d1 + + move.l #0x01000000, %d0 + or.l %d1, %d0 + movec %d0, %CACR /* Invalidate dcache */ + + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 + movec %d0, %ACR0 + move.l #0, %d0 + movec %d0, %ACR1 + + or.l #0x80000000, %d1 /* Enable bcache and icache */ + movec %d1, %CACR + + move.l #(DCACHE_STATUS), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_disable +dcache_disable: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d0 + + and.l #0x7FFFFFFF, %d0 + or.l #0x01000000, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Disable dcache */ + clr.l %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + move.l #(DCACHE_STATUS), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_invalid +dcache_invalid: + move.l #(CACR_STATUS), %a1 /* read CACR Status */ + move.l (%a1), %d0 + + or.l #0x01000000, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable and invalidate cache */ + rts + + .globl dcache_status +dcache_status: + move.l #(DCACHE_STATUS), %a1 + move.l (%a1), %d0 + rts + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/doc/README.m54455evb b/doc/README.m54455evb new file mode 100644 index 00000000000..c768fc8a409 --- /dev/null +++ b/doc/README.m54455evb @@ -0,0 +1,416 @@ +Freescale MCF54455EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created 4/08/07 +=========================================== + + +Changed files: +============== + +- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init +- board/freescale/m54455evb/flash.c Atmel and INTEL flash support +- board/freescale/m54455evb/Makefile Makefile +- board/freescale/m54455evb/config.mk config make +- board/freescale/m54455evb/u-boot.lds Linker description + +- common/cmd_bdinfo.c Clock frequencies output +- common/cmd_mii.c mii support + +- cpu/mcf5445x/cpu.c cpu specific code +- cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs +- cpu/mcf5445x/interrupts.c cpu specific interrupt support +- cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock +- cpu/mcf5445x/Makefile Makefile +- cpu/mcf5445x/config.mk config make +- cpu/mcf5445x/start.S start up assembly code + +- doc/README.m54455evb This readme file + +- drivers/net/mcffec.c ColdFire common FEC driver +- drivers/serial/mcfuart.c ColdFire common UART driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_5445x.h mcf5445x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m5445x.h mcf5445x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M54455EVB.h Board specific configuration file + +- lib_m68k/board.c board init function +- lib_m68k/cache.c +- lib_m68k/interrupts Coldfire common interrupt functions +- lib_m68k/m68k_linux.c +- lib_m68k/time.c Timer functions (Dma timer and PIT) +- lib_m68k/traps.c Exception init code + +- rtc/mcfrtc.c Realtime clock Driver + +1 MCF5445x specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M54455EVB Development Board +CONFIG_MCF5445x -- define for all MCF5445x CPUs +CONFIG_M54455 -- define for all Freescale MCF54455 CPUs +CONFIG_M54455EVB -- define for M54455EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CFG_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CFG_MCFRTC_BASE -- provide base address for RTC in immap.h +CFG_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CFG_CMD_DATE -- enable to use date feature in u-boot + +CONFIG_MCFFEC -- define to use common CF FEC driver +CONFIG_NET_MULTI -- define to use multi FEC in u-boot +CONFIG_MII -- enable to use MII driver +CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c +CFG_DISCOVER_PHY -- enable PHY discovery +CFG_RX_ETH_BUFFER -- Set FEC Receive buffer +CFG_FAULT_ECHO_LINK_DOWN-- +CFG_FEC0_PINMUX -- Set FEC0 Pin configuration +CFG_FEC1_PINMUX -- Set FEC1 Pin configuration +CFG_FEC0_MIIBASE -- Set FEC0 MII base register +CFG_FEC1_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop +CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot + +CONFIG_ISO_PARTITION -- enable ISO read/write +CONFIG_DOS_PARTITION -- enable DOS read/write +CONFIG_IDE_RESET -- define ide_reset() +CONFIG_IDE_PREINIT -- define ide_preinit() +CONFIG_ATAPI -- define ATAPI support +CONFIG_LBA48 -- define LBA48 (larger than 120GB) support +CFG_IDE_MAXBUS -- define max channel +CFG_IDE_MAXDEVICE -- define max devices per channel +CFG_ATA_BASE_ADDR -- define ATA base address +CFG_ATA_IDE0_OFFSET -- define ATA IDE0 offset +CFG_ATA_DATA_OFFSET -- define ATA data IO +CFG_ATA_REG_OFFSET -- define for normal register accesses +CFG_ATA_ALT_OFFSET -- define for alternate registers +CFG_ATA_STRIDE -- define for Interval between registers +_IO_BASE -- define for IO base address + +CONFIG_MCFTMR -- define to use DMA timer +CONFIG_MCFPIT -- define to use PIT timer + +CONFIG_FSL_I2C -- define to use FSL common I2C driver +CONFIG_HARD_I2C -- define for I2C hardware support +CONFIG_SOFT_I2C -- define for I2C bit-banged +CFG_I2C_SPEED -- define for I2C speed +CFG_I2C_SLAVE -- define for I2C slave address +CFG_I2C_OFFSET -- define for I2C base address offset +CFG_IMMR -- define for MBAR offset + +CONFIG_PCI -- define for PCI support +CONFIG_PCI_PNP -- define for Plug n play support +CFG_PCI_MEM_BUS -- PCI memory logical offset +CFG_PCI_MEM_PHYS -- PCI memory physical offset +CFG_PCI_MEM_SIZE -- PCI memory size +CFG_PCI_IO_BUS -- PCI IO logical offset +CFG_PCI_IO_PHYS -- PCI IO physical offset +CFG_PCI_IO_SIZE -- PCI IO size +CFG_PCI_CFG_BUS -- PCI Configuration logical offset +CFG_PCI_CFG_PHYS -- PCI Configuration physical offset +CFG_PCI_CFG_SIZE -- PCI Configuration size + +CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc + +CFG_MBAR -- define MBAR offset + +CFG_ATMEL_BOOT -- To determine the u-boot is booted from Atmel or Intel + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CFG_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM + +CFG_CSn_BASE -- defines the Chip Select Base register +CFG_CSn_MASK -- defines the Chip Select Mask register +CFG_CSn_CTRL -- defines the Chip Select Control register + +CFG_ATMEL_BASE -- defines the Atmel Flash base +CFG_INTEL_BASE -- defines the Intel Flash base + +CFG_SDRAM_BASE -- defines the DRAM Base +CFG_SDRAM_BASE1 -- defines the DRAM Base 1 + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + ATA: 0x90000000-0x9FFFFFFF (256MB) + PCI: 0xA0000000-0xBFFFFFFF (512MB) + FlexBus: 0xC0000000-0xDFFFFFFF (512MB) + IP: 0xF0000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + Atmel boot: + Flash0: 0x00000000-0x0007FFFF (512KB) + Flash1: 0x04000000-0x05FFFFFF (32MB) + Intel boot: + Flash0: 0x00000000-0x01FFFFFF (32MB) + Flash1: 0x04000000-0x0407FFFF (512KB) + + CPLD: 0x08000000-0x08FFFFFF (16MB) + FPGA: 0x09000000-0x09FFFFFF (16MB) + DDR: 0x40000000-0x4FFFFFFF (256MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. SWITCH SETTINGS +================== +3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL + SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state + SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down + 1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active + SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down + SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL + +4. COMPILATION +============== +4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version) +from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +4.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1.x.x + make distclean + make M54455EVB_config, or - default to atmel 33Mhz input clock + make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock + make M54455EVB_a33_config, or - default to atmel 33Mhz input clock + make M54455EVB_a66_config, or - default to atmel 66Mhz input clock + make M54455EVB_intel_config, or - default to intel 33Mhz input clock + make M54455EVB_i33_config, or - default to intel 33Mhz input clock + make M54455EVB_i66_config, or - default to intel 66Mhz input clock + make + +5. SCREEN DUMP +============== +5.1 M54455EVB Development board + Boot from Atmel (NOTE: May not show exactly the same) + +U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08) + +CPU: Freescale MCF54455 (Mask:48 Version:1) + CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz + PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz +Board: Freescale M54455 EVB +I2C: ready +DRAM: 256 MB +FLASH: 16.5 MB +In: serial +Out: serial +Err: serial +Net: FEC0, FEC1 +IDE: Bus 0: not available +-> print +bootargs=root=/dev/ram rw +bootdelay=1 +baudrate=115200 +ethaddr=00:e0:0c:bc:e5:60 +eth1addr=00:e0:0c:bc:e5:61 +hostname=M54455EVB +netdev=eth0 +inpclk=33333333 +loadaddr=40010000 +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save +ethact=FEC0 +mtdids=nor0=M54455EVB-1 +mtdparts=M54455EVB-1:16m(user) +u-boot=u-boot54455.bin +filesize=292b4 +fileaddr=40010000 +gatewayip=192.168.1.1 +netmask=255.255.255.0 +ipaddr=192.168.1.3 +serverip=192.168.1.2 +stdin=serial +stdout=serial +stderr=serial +mem=261632k + +Environment size: 563/8188 bytes +-> bdinfo +memstart = 0x40000000 +memsize = 0x10000000 +flashstart = 0x00000000 +flashsize = 0x01080000 +flashoffset = 0x00000000 +sramstart = 0x80000000 +sramsize = 0x00008000 +mbar = 0xFC000000 +busfreq = 133.333 MHz +pcifreq = 33.333 MHz +flbfreq = 66.666 MHz +inpfreq = 33.333 MHz +vcofreq = 533.333 MHz +ethaddr = 00:E0:0C:BC:E5:60 +eth1addr = 00:E0:0C:BC:E5:61 +ip_addr = 192.168.1.3 +baudrate = 115200 bps +-> +-> help +? - alias for 'help' +autoscr - run script from memory +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd' +bootelf - Boot from an ELF image in memory +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootvx - Boot vxWorks from an ELF image +cmp - memory compare +coninfo - print console devices and information +cp - memory copy +crc32 - checksum calculation +date - get/set/reset date & time +dcache - enable or disable data cache +diskboot- boot from IDE device +echo - echo args to console +erase - erase FLASH memory +ext2load- load binary file from a Ext2 filesystem +ext2ls - list files in a directory (default /) +fatinfo - print information about filesystem +fatload - load binary file from a dos filesystem +fatls - list files in a directory (default /) +flinfo - print FLASH memory information +fsinfo - print information about filesystems +fsload - load binary file from a filesystem image +go - start application at address 'addr' +help - print online help +icache - enable or disable instruction cache +icrc32 - checksum calculation +ide - IDE sub-system +iloop - infinite loop on address range +imd - i2c memory display +iminfo - print header information for application image +imls - list all images found in flash +imm - i2c memory modify (auto-incrementing) +imw - memory write (fill) +inm - memory modify (constant address) +iprobe - probe to discover valid I2C chip addresses +itest - return true/false on integer compare +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loady - load binary file over serial line (ymodem mode) +loop - infinite loop on address range +ls - list files in a directory (default /) +md - memory display +mii - MII utility commands +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nfs - boot image via network using NFS protocol +nm - memory modify (constant address) +pci - list and access PCI Configuration Space +ping - send ICMP ECHO_REQUEST to network host +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +tftpboot- boot image via network using TFTP protocol +version - print monitor version +->bootm 4000000 + +## Booting image at 04000000 ... + Image Name: Linux Kernel Image + Created: 2007-08-14 15:13:00 UTC + Image Type: M68K Linux Kernel Image (uncompressed) + Data Size: 2301952 Bytes = 2.2 MB + Load Address: 40020000 + Entry Point: 40020000 + Verifying Checksum ... OK +OK +Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr +erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007 +starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB +Built 1 zonelists. Total pages: 32624 +Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph +ysmap-flash.0:5M(kernel)ro,-(jffs2) +PID hash table entries: 1024 (order: 10, 4096 bytes) +Console: colour dummy device 80x25 +Dentry cache hash table entries: 32768 (order: 4, 131072 bytes) +Inode-cache hash table entries: 16384 (order: 3, 65536 bytes) +Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init) +Mount-cache hash table entries: 1024 +NET: Registered protocol family 16 +SCSI subsystem initialized +NET: Registered protocol family 2 +IP route cache hash table entries: 2048 (order: 0, 8192 bytes) +TCP established hash table entries: 8192 (order: 2, 32768 bytes) +TCP bind hash table entries: 4096 (order: 1, 16384 bytes) +TCP: Hash tables configured (established 8192 bind 4096) +TCP reno registered +JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc. +io scheduler noop registered +io scheduler anticipatory registered +io scheduler deadline registered +io scheduler cfq registered (default) +ColdFire internal UART serial driver version 1.00 +ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART +ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART +ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART +RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize +loop: loaded (max 8 devices) +FEC ENET Version 0.2 +fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849 +eth0: ethernet 00:08:ee:00:e4:19 +physmap platform flash device: 01000000 at 04000000 +physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank + Intel/Sharp Extended Query Table at 0x0031 +Using buffer write method +cfi_cmdset_0001: Erase suspend on write enabled +2 cmdlinepart partitions found on MTD device physmap-flash.0 +Creating 2 MTD partitions on "physmap-flash.0": +0x00000000-0x00500000 : "kernel" +mtd: Giving out device 0 to kernel +0x00500000-0x01000000 : "jffs2" +mtd: Giving out device 1 to jffs2 +mice: PS/2 mouse device common for all mice +i2c /dev entries driver +TCP cubic registered +NET: Registered protocol family 1 +NET: Registered protocol family 17 +NET: Registered protocol family 15 +VFS: Mounted root (jffs2 filesystem). +Setting the hostname to freescale +Mounting filesystems +mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory +Starting syslogd and klogd +Setting up networking on loopback device: +Setting up networking on eth0: +eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX. +Adding static route for default gateway to 172.27.255.254: +Setting nameserver to 172.27.0.1 in /etc/resolv.conf: +Starting inetd: +/ # diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 68a0ee640d2..2e0ddeb7772 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -430,20 +430,33 @@ int fec_init(struct eth_device *dev, bd_t * bd) /* Set station address */ if ((u32) fecp == CFG_FEC0_IOBASE) { +#ifdef CFG_FEC1_IOBASE + volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE); + ea = &bd->bi_enet1addr[0]; + fecp1->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp1->paur = (ea[4] << 24) | (ea[5] << 16); +#endif ea = &bd->bi_enetaddr[0]; + fecp->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->paur = (ea[4] << 24) | (ea[5] << 16); } else { +#ifdef CFG_FEC0_IOBASE + volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE); + ea = &bd->bi_enetaddr[0]; + fecp0->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp0->paur = (ea[4] << 24) | (ea[5] << 16); +#endif #ifdef CFG_FEC1_IOBASE ea = &bd->bi_enet1addr[0]; + fecp->palr = + (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->paur = (ea[4] << 24) | (ea[5] << 16); #endif } - fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); - fecp->paur = (ea[4] << 24) | (ea[5] << 16); -#ifdef ET_DEBUG - printf("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n", - ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); -#endif - /* Clear unicast address hash table */ fecp->iaur = 0; fecp->ialr = 0; diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h index f68352f1206..9d9894b1a2e 100644 --- a/include/asm-m68k/global_data.h +++ b/include/asm-m68k/global_data.h @@ -39,6 +39,14 @@ typedef struct global_data { unsigned long baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; +#ifdef CONFIG_PCI + unsigned long pci_clk; +#endif +#ifdef CONFIG_EXTRA_CLOCK + unsigned long inp_clk; + unsigned long vco_clk; + unsigned long flb_clk; +#endif unsigned long ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long reset_status; /* reset status register at boot */ diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index bf7b51becfa..d66c1619b16 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -170,4 +170,44 @@ #define CFG_NUM_IRQS (128) #endif /* CONFIG_M5329 */ +#ifdef CONFIG_M54455 +#include +#include + +#define CFG_FEC0_IOBASE (MMAP_FEC0) +#define CFG_FEC1_IOBASE (MMAP_FEC1) + +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) + +#define CFG_MCFRTC_BASE (MMAP_RTC) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR1) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) +#define CFG_TMRINTR_NO (INT0_HI_DTMR1) +#define CFG_TMRINTR_MASK (INTC_IPRH_INT33) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (6) +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif + +#ifdef CONFIG_MCFPIT +#define CFG_UDELAY_BASE (MMAP_PIT0) +#define CFG_PIT_BASE (MMAP_PIT1) +#define CFG_PIT_PRESCALE (6) +#endif + +#define CFG_INTR_BASE (MMAP_INTC0) +#define CFG_NUM_IRQS (128) + +#ifdef CONFIG_PCI +#define CFG_PCI_BAR0 CFG_SDRAM_BASE +#define CFG_PCI_BAR4 CFG_SDRAM_BASE +#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE) +#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE) +#endif +#endif /* CONFIG_M54455 */ + #endif /* __IMMAP_H */ diff --git a/include/asm-m68k/immap_5445x.h b/include/asm-m68k/immap_5445x.h new file mode 100644 index 00000000000..d091d7b73c7 --- /dev/null +++ b/include/asm-m68k/immap_5445x.h @@ -0,0 +1,937 @@ +/* + * MCF5445x Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5445X__ +#define __IMMAP_5445X__ + +/* Module Base Addresses */ +#define MMAP_SCM1 0xFC000000 +#define MMAP_XBS 0xFC004000 +#define MMAP_FBCS 0xFC008000 +#define MMAP_FEC0 0xFC030000 +#define MMAP_FEC1 0xFC034000 +#define MMAP_RTC 0xFC03C000 +#define MMAP_EDMA 0xFC044000 +#define MMAP_INTC0 0xFC048000 +#define MMAP_INTC1 0xFC04C000 +#define MMAP_IACK 0xFC054000 +#define MMAP_I2C 0xFC058000 +#define MMAP_DSPI 0xFC05C000 +#define MMAP_UART0 0xFC060000 +#define MMAP_UART1 0xFC064000 +#define MMAP_UART2 0xFC068000 +#define MMAP_DTMR0 0xFC070000 +#define MMAP_DTMR1 0xFC074000 +#define MMAP_DTMR2 0xFC078000 +#define MMAP_DTMR3 0xFC07C000 +#define MMAP_PIT0 0xFC080000 +#define MMAP_PIT1 0xFC084000 +#define MMAP_PIT2 0xFC088000 +#define MMAP_PIT3 0xFC08C000 +#define MMAP_EPORT 0xFC094000 +#define MMAP_WTM 0xFC098000 +#define MMAP_SBF 0xFC0A0000 +#define MMAP_RCM 0xFC0A0000 +#define MMAP_CCM 0xFC0A0000 +#define MMAP_GPIO 0xFC0A4000 +#define MMAP_PCI 0xFC0A8000 +#define MMAP_PCIARB 0xFC0AC000 +#define MMAP_RNG 0xFC0B4000 +#define MMAP_SDRAM 0xFC0B8000 +#define MMAP_SSI 0xFC0BC000 +#define MMAP_PLL 0xFC0C4000 +#define MMAP_ATA 0x90000000 + +/********************************************************************* +* ATA +*********************************************************************/ + +typedef struct atac { + /* PIO */ + u8 toff; /* 0x00 */ + u8 ton; /* 0x01 */ + u8 t1; /* 0x02 */ + u8 t2w; /* 0x03 */ + u8 t2r; /* 0x04 */ + u8 ta; /* 0x05 */ + u8 trd; /* 0x06 */ + u8 t4; /* 0x07 */ + u8 t9; /* 0x08 */ + + /* DMA */ + u8 tm; /* 0x09 */ + u8 tn; /* 0x0A */ + u8 td; /* 0x0B */ + u8 tk; /* 0x0C */ + u8 tack; /* 0x0D */ + u8 tenv; /* 0x0E */ + u8 trp; /* 0x0F */ + u8 tzah; /* 0x10 */ + u8 tmli; /* 0x11 */ + u8 tdvh; /* 0x12 */ + u8 tdzfs; /* 0x13 */ + u8 tdvs; /* 0x14 */ + u8 tcvh; /* 0x15 */ + u8 tss; /* 0x16 */ + u8 tcyc; /* 0x17 */ + + /* FIFO */ + u32 fifo32; /* 0x18 */ + u16 fifo16; /* 0x1C */ + u8 rsvd0[2]; + u8 ffill; /* 0x20 */ + u8 rsvd1[3]; + + /* ATA */ + u8 cr; /* 0x24 */ + u8 rsvd2[3]; + u8 isr; /* 0x28 */ + u8 rsvd3[3]; + u8 ier; /* 0x2C */ + u8 rsvd4[3]; + u8 icr; /* 0x30 */ + u8 rsvd5[3]; + u8 falarm; /* 0x34 */ + u8 rsvd6[106]; +} atac_t; + +/********************************************************************* +* Cross-bar switch (XBS) +*********************************************************************/ + +typedef struct xbs { + u8 resv0[0x100]; + u32 prs1; /* XBS Priority Register */ + u8 resv1[0xC]; + u32 crs1; /* XBS Control Register */ + u8 resv2[0xEC]; + u32 prs2; /* XBS Priority Register */ + u8 resv3[0xC]; + u32 crs2; /* XBS Control Register */ + u8 resv4[0xEC]; + u32 prs3; /* XBS Priority Register */ + u8 resv5[0xC]; + u32 crs3; /* XBS Control Register */ + u8 resv6[0xEC]; + u32 prs4; /* XBS Priority Register */ + u8 resv7[0xC]; + u32 crs4; /* XBS Control Register */ + u8 resv8[0xEC]; + u32 prs5; /* XBS Priority Register */ + u8 resv9[0xC]; + u32 crs5; /* XBS Control Register */ + u8 resv10[0xEC]; + u32 prs6; /* XBS Priority Register */ + u8 resv11[0xC]; + u32 crs6; /* XBS Control Register */ + u8 resv12[0xEC]; + u32 prs7; /* XBS Priority Register */ + u8 resv13[0xC]; + u32 crs7; /* XBS Control Register */ +} xbs_t; + +/********************************************************************* +* FlexBus Chip Selects (FBCS) +*********************************************************************/ + +typedef struct fbcs { + u32 csar0; /* Chip-select Address Register */ + u32 csmr0; /* Chip-select Mask Register */ + u32 cscr0; /* Chip-select Control Register */ + u32 csar1; /* Chip-select Address Register */ + u32 csmr1; /* Chip-select Mask Register */ + u32 cscr1; /* Chip-select Control Register */ + u32 csar2; /* Chip-select Address Register */ + u32 csmr2; /* Chip-select Mask Register */ + u32 cscr2; /* Chip-select Control Register */ + u32 csar3; /* Chip-select Address Register */ + u32 csmr3; /* Chip-select Mask Register */ + u32 cscr3; /* Chip-select Control Register */ +} fbcs_t; + +/********************************************************************* +* Enhanced DMA (EDMA) +*********************************************************************/ + +typedef struct edma { + u32 cr; + u32 es; + u8 resv0[0x6]; + u16 erq; + u8 resv1[0x6]; + u16 eei; + u8 serq; + u8 cerq; + u8 seei; + u8 ceei; + u8 cint; + u8 cerr; + u8 ssrt; + u8 cdne; + u8 resv2[0x6]; + u16 intr; + u8 resv3[0x6]; + u16 err; + u8 resv4[0xD0]; + u8 dchpri0; + u8 dchpri1; + u8 dchpri2; + u8 dchpri3; + u8 dchpri4; + u8 dchpri5; + u8 dchpri6; + u8 dchpri7; + u8 dchpri8; + u8 dchpri9; + u8 dchpri10; + u8 dchpri11; + u8 dchpri12; + u8 dchpri13; + u8 dchpri14; + u8 dchpri15; + u8 resv5[0xEF0]; + u32 tcd0_saddr; + u16 tcd0_attr; + u16 tcd0_soff; + u32 tcd0_nbytes; + u32 tcd0_slast; + u32 tcd0_daddr; + union { + u16 tcd0_citer_elink; + u16 tcd0_citer; + }; + u16 tcd0_doff; + u32 tcd0_dlast_sga; + union { + u16 tcd0_biter_elink; + u16 tcd0_biter; + }; + u16 tcd0_csr; + u32 tcd1_saddr; + u16 tcd1_attr; + u16 tcd1_soff; + u32 tcd1_nbytes; + u32 tcd1_slast; + u32 tcd1_daddr; + union { + u16 tcd1_citer_elink; + u16 tcd1_citer; + }; + u16 tcd1_doff; + u32 tcd1_dlast_sga; + union { + u16 tcd1_biter; + u16 tcd1_biter_elink; + }; + u16 tcd1_csr; + u32 tcd2_saddr; + u16 tcd2_attr; + u16 tcd2_soff; + u32 tcd2_nbytes; + u32 tcd2_slast; + u32 tcd2_daddr; + union { + u16 tcd2_citer; + u16 tcd2_citer_elink; + }; + u16 tcd2_doff; + u32 tcd2_dlast_sga; + union { + u16 tcd2_biter_elink; + u16 tcd2_biter; + }; + u16 tcd2_csr; + u32 tcd3_saddr; + u16 tcd3_attr; + u16 tcd3_soff; + u32 tcd3_nbytes; + u32 tcd3_slast; + u32 tcd3_daddr; + union { + u16 tcd3_citer; + u16 tcd3_citer_elink; + }; + u16 tcd3_doff; + u32 tcd3_dlast_sga; + union { + u16 tcd3_biter_elink; + u16 tcd3_biter; + }; + u16 tcd3_csr; + u32 tcd4_saddr; + u16 tcd4_attr; + u16 tcd4_soff; + u32 tcd4_nbytes; + u32 tcd4_slast; + u32 tcd4_daddr; + union { + u16 tcd4_citer; + u16 tcd4_citer_elink; + }; + u16 tcd4_doff; + u32 tcd4_dlast_sga; + union { + u16 tcd4_biter; + u16 tcd4_biter_elink; + }; + u16 tcd4_csr; + u32 tcd5_saddr; + u16 tcd5_attr; + u16 tcd5_soff; + u32 tcd5_nbytes; + u32 tcd5_slast; + u32 tcd5_daddr; + union { + u16 tcd5_citer; + u16 tcd5_citer_elink; + }; + u16 tcd5_doff; + u32 tcd5_dlast_sga; + union { + u16 tcd5_biter_elink; + u16 tcd5_biter; + }; + u16 tcd5_csr; + u32 tcd6_saddr; + u16 tcd6_attr; + u16 tcd6_soff; + u32 tcd6_nbytes; + u32 tcd6_slast; + u32 tcd6_daddr; + union { + u16 tcd6_citer; + u16 tcd6_citer_elink; + }; + u16 tcd6_doff; + u32 tcd6_dlast_sga; + union { + u16 tcd6_biter_elink; + u16 tcd6_biter; + }; + u16 tcd6_csr; + u32 tcd7_saddr; + u16 tcd7_attr; + u16 tcd7_soff; + u32 tcd7_nbytes; + u32 tcd7_slast; + u32 tcd7_daddr; + union { + u16 tcd7_citer; + u16 tcd7_citer_elink; + }; + u16 tcd7_doff; + u32 tcd7_dlast_sga; + union { + u16 tcd7_biter_elink; + u16 tcd7_biter; + }; + u16 tcd7_csr; + u32 tcd8_saddr; + u16 tcd8_attr; + u16 tcd8_soff; + u32 tcd8_nbytes; + u32 tcd8_slast; + u32 tcd8_daddr; + union { + u16 tcd8_citer; + u16 tcd8_citer_elink; + }; + u16 tcd8_doff; + u32 tcd8_dlast_sga; + union { + u16 tcd8_biter_elink; + u16 tcd8_biter; + }; + u16 tcd8_csr; + u32 tcd9_saddr; + u16 tcd9_attr; + u16 tcd9_soff; + u32 tcd9_nbytes; + u32 tcd9_slast; + u32 tcd9_daddr; + union { + u16 tcd9_citer_elink; + u16 tcd9_citer; + }; + u16 tcd9_doff; + u32 tcd9_dlast_sga; + union { + u16 tcd9_biter_elink; + u16 tcd9_biter; + }; + u16 tcd9_csr; + u32 tcd10_saddr; + u16 tcd10_attr; + u16 tcd10_soff; + u32 tcd10_nbytes; + u32 tcd10_slast; + u32 tcd10_daddr; + union { + u16 tcd10_citer_elink; + u16 tcd10_citer; + }; + u16 tcd10_doff; + u32 tcd10_dlast_sga; + union { + u16 tcd10_biter; + u16 tcd10_biter_elink; + }; + u16 tcd10_csr; + u32 tcd11_saddr; + u16 tcd11_attr; + u16 tcd11_soff; + u32 tcd11_nbytes; + u32 tcd11_slast; + u32 tcd11_daddr; + union { + u16 tcd11_citer; + u16 tcd11_citer_elink; + }; + u16 tcd11_doff; + u32 tcd11_dlast_sga; + union { + u16 tcd11_biter; + u16 tcd11_biter_elink; + }; + u16 tcd11_csr; + u32 tcd12_saddr; + u16 tcd12_attr; + u16 tcd12_soff; + u32 tcd12_nbytes; + u32 tcd12_slast; + u32 tcd12_daddr; + union { + u16 tcd12_citer; + u16 tcd12_citer_elink; + }; + u16 tcd12_doff; + u32 tcd12_dlast_sga; + union { + u16 tcd12_biter; + u16 tcd12_biter_elink; + }; + u16 tcd12_csr; + u32 tcd13_saddr; + u16 tcd13_attr; + u16 tcd13_soff; + u32 tcd13_nbytes; + u32 tcd13_slast; + u32 tcd13_daddr; + union { + u16 tcd13_citer_elink; + u16 tcd13_citer; + }; + u16 tcd13_doff; + u32 tcd13_dlast_sga; + union { + u16 tcd13_biter_elink; + u16 tcd13_biter; + }; + u16 tcd13_csr; + u32 tcd14_saddr; + u16 tcd14_attr; + u16 tcd14_soff; + u32 tcd14_nbytes; + u32 tcd14_slast; + u32 tcd14_daddr; + union { + u16 tcd14_citer; + u16 tcd14_citer_elink; + }; + u16 tcd14_doff; + u32 tcd14_dlast_sga; + union { + u16 tcd14_biter_elink; + u16 tcd14_biter; + }; + u16 tcd14_csr; + u32 tcd15_saddr; + u16 tcd15_attr; + u16 tcd15_soff; + u32 tcd15_nbytes; + u32 tcd15_slast; + u32 tcd15_daddr; + union { + u16 tcd15_citer_elink; + u16 tcd15_citer; + }; + u16 tcd15_doff; + u32 tcd15_dlast_sga; + union { + u16 tcd15_biter; + u16 tcd15_biter_elink; + }; + u16 tcd15_csr; +} edma_t; + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ + +typedef struct int0_ctrl { + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 - 0x19 */ + u16 icfg0; /* 0x1A Configuration Register */ + u8 simr0; /* 0x1C Set Interrupt Mask */ + u8 cimr0; /* 0x1D Clear Interrupt Mask */ + u8 clmask0; /* 0x1E Current Level Mask */ + u8 slmask; /* 0x1F Saved Level Mask */ + u32 res2[8]; /* 0x20 - 0x3F */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; + +typedef struct int1_ctrl { + /* Interrupt Controller 1 */ + u32 iprh1; /* 0x00 Pending Register High */ + u32 iprl1; /* 0x04 Pending Register Low */ + u32 imrh1; /* 0x08 Mask Register High */ + u32 imrl1; /* 0x0C Mask Register Low */ + u32 frch1; /* 0x10 Force Register High */ + u32 frcl1; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 */ + u16 icfg1; /* 0x1A Configuration Register */ + u8 simr1; /* 0x1C Set Interrupt Mask */ + u8 cimr1; /* 0x1D Clear Interrupt Mask */ + u16 res2; /* 0x1E - 0x1F */ + u32 res3[8]; /* 0x20 - 0x3F */ + u8 icr1[64]; /* 0x40 - 0x7F */ + u32 res4[24]; /* 0x80 - 0xDF */ + u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */ + u8 res5[3]; /* 0xE1 - 0xE3 */ + u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */ + u8 res6[3]; /* 0xE5 - 0xE7 */ + u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */ + u8 res7[3]; /* 0xE9 - 0xEB */ + u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */ + u8 res8[3]; /* 0xED - 0xEF */ + u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */ + u8 res9[3]; /* 0xF1 - 0xF3 */ + u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */ + u8 resa[3]; /* 0xF5 - 0xF7 */ + u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */ + u8 resb[3]; /* 0xF9 - 0xFB */ + u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */ + u8 resc[3]; /* 0xFD - 0xFF */ +} int1_t; + +/********************************************************************* +* Global Interrupt Acknowledge (IACK) +*********************************************************************/ + +typedef struct iack { + u8 resv0[0xE0]; + u8 gswiack; + u8 resv1[0x3]; + u8 gl1iack; + u8 resv2[0x3]; + u8 gl2iack; + u8 resv3[0x3]; + u8 gl3iack; + u8 resv4[0x3]; + u8 gl4iack; + u8 resv5[0x3]; + u8 gl5iack; + u8 resv6[0x3]; + u8 gl6iack; + u8 resv7[0x3]; + u8 gl7iack; +} iack_t; + +/********************************************************************* +* DMA Serial Peripheral Interface (DSPI) +*********************************************************************/ + +typedef struct dspi { + u32 dmcr; + u8 resv0[0x4]; + u32 dtcr; + u32 dctar0; + u32 dctar1; + u32 dctar2; + u32 dctar3; + u32 dctar4; + u32 dctar5; + u32 dctar6; + u32 dctar7; + u32 dsr; + u32 dirsr; + u32 dtfr; + u32 drfr; + u32 dtfdr0; + u32 dtfdr1; + u32 dtfdr2; + u32 dtfdr3; + u8 resv1[0x30]; + u32 drfdr0; + u32 drfdr1; + u32 drfdr2; + u32 drfdr3; +} dspi_t; + +/********************************************************************* +* Edge Port Module (EPORT) +*********************************************************************/ + +typedef struct eport { + u16 eppar; + u8 epddr; + u8 epier; + u8 epdr; + u8 eppdr; + u8 epfr; +} eport_t; + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ + +typedef struct wtm { + u16 wcr; + u16 wmr; + u16 wcntr; + u16 wsr; +} wtm_t; + +/********************************************************************* +* Serial Boot Facility (SBF) +*********************************************************************/ + +typedef struct sbf { + u8 resv0[0x18]; + u16 sbfsr; /* Serial Boot Facility Status Register */ + u8 resv1[0x6]; + u16 sbfcr; /* Serial Boot Facility Control Register */ +} sbf_t; + +/********************************************************************* +* Reset Controller Module (RCM) +*********************************************************************/ + +typedef struct rcm { + u8 rcr; + u8 rsr; +} rcm_t; + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ + +typedef struct ccm { + u8 ccm_resv0[0x4]; + u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */ + u8 resv1[0x2]; + u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */ + u16 cir; /* Chip Identification Register (Read-only) */ + u8 resv2[0x4]; + u16 misccr; /* Miscellaneous Control Register */ + u16 cdr; /* Clock Divider Register */ + u16 uocsr; /* USB On-the-Go Controller Status Register */ +} ccm_t; + +/********************************************************************* +* General Purpose I/O Module (GPIO) +*********************************************************************/ + +typedef struct gpio { + u8 podr_fec0h; /* FEC0 High Port Output Data Register */ + u8 podr_fec0l; /* FEC0 Low Port Output Data Register */ + u8 podr_ssi; /* SSI Port Output Data Register */ + u8 podr_fbctl; /* Flexbus Control Port Output Data Register */ + u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */ + u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */ + u8 podr_dma; /* DMA Port Output Data Register */ + u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */ + u8 resv0[0x1]; + u8 podr_uart; /* UART Port Output Data Register */ + u8 podr_dspi; /* DSPI Port Output Data Register */ + u8 podr_timer; /* Timer Port Output Data Register */ + u8 podr_pci; /* PCI Port Output Data Register */ + u8 podr_usb; /* USB Port Output Data Register */ + u8 podr_atah; /* ATA High Port Output Data Register */ + u8 podr_atal; /* ATA Low Port Output Data Register */ + u8 podr_fec1h; /* FEC1 High Port Output Data Register */ + u8 podr_fec1l; /* FEC1 Low Port Output Data Register */ + u8 resv1[0x2]; + u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */ + u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */ + u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */ + u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */ + u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */ + u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */ + u8 pddr_ssi; /* SSI Port Data Direction Register */ + u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */ + u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */ + u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */ + u8 pddr_dma; /* DMA Port Data Direction Register */ + u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */ + u8 resv2[0x1]; + u8 pddr_uart; /* UART Port Data Direction Register */ + u8 pddr_dspi; /* DSPI Port Data Direction Register */ + u8 pddr_timer; /* Timer Port Data Direction Register */ + u8 pddr_pci; /* PCI Port Data Direction Register */ + u8 pddr_usb; /* USB Port Data Direction Register */ + u8 pddr_atah; /* ATA High Port Data Direction Register */ + u8 pddr_atal; /* ATA Low Port Data Direction Register */ + u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */ + u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */ + u8 resv3[0x2]; + u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */ + u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */ + u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */ + u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */ + u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */ + u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */ + u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */ + u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */ + u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */ + u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */ + u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */ + u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */ + u8 resv4[0x1]; + u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */ + u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */ + u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */ + u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */ + u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */ + u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */ + u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */ + u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */ + u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */ + u8 resv5[0x2]; + u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */ + u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */ + u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */ + u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */ + u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */ + u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */ + u8 pclrr_ssi; /* SSI Port Clear Output Data Register */ + u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */ + u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */ + u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */ + u8 pclrr_dma; /* DMA Port Clear Output Data Register */ + u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */ + u8 resv6[0x1]; + u8 pclrr_uart; /* UART Port Clear Output Data Register */ + u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */ + u8 pclrr_timer; /* Timer Port Clear Output Data Register */ + u8 pclrr_pci; /* PCI Port Clear Output Data Register */ + u8 pclrr_usb; /* USB Port Clear Output Data Register */ + u8 pclrr_atah; /* ATA High Port Clear Output Data Register */ + u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */ + u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */ + u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */ + u8 resv7[0x2]; + u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */ + u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */ + u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */ + u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */ + u8 par_fec; /* FEC Pin Assignment Register */ + u8 par_dma; /* DMA Pin Assignment Register */ + u8 par_fbctl; /* Flexbus Control Pin Assignment Register */ + u8 par_dspi; /* DSPI Pin Assignment Register */ + u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */ + u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */ + u8 par_timer; /* Time Pin Assignment Register */ + u8 par_usb; /* USB Pin Assignment Register */ + u8 resv8[0x1]; + u8 par_uart; /* UART Pin Assignment Register */ + u16 par_feci2c; /* FEC / I2C Pin Assignment Register */ + u16 par_ssi; /* SSI Pin Assignment Register */ + u16 par_ata; /* ATA Pin Assignment Register */ + u8 par_irq; /* IRQ Pin Assignment Register */ + u8 resv9[0x1]; + u16 par_pci; /* PCI Pin Assignment Register */ + u8 mscr_sdram; /* SDRAM Mode Select Control Register */ + u8 mscr_pci; /* PCI Mode Select Control Register */ + u8 resv10[0x2]; + u8 dscr_i2c; /* I2C Drive Strength Control Register */ + u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */ + u8 dscr_fec; /* FEC Drive Strength Control Register */ + u8 dscr_uart; /* UART Drive Strength Control Register */ + u8 dscr_dspi; /* DSPI Drive Strength Control Register */ + u8 dscr_timer; /* TIMER Drive Strength Control Register */ + u8 dscr_ssi; /* SSI Drive Strength Control Register */ + u8 dscr_dma; /* DMA Drive Strength Control Register */ + u8 dscr_debug; /* DEBUG Drive Strength Control Register */ + u8 dscr_reset; /* RESET Drive Strength Control Register */ + u8 dscr_irq; /* IRQ Drive Strength Control Register */ + u8 dscr_usb; /* USB Drive Strength Control Register */ + u8 dscr_ata; /* ATA Drive Strength Control Register */ +} gpio_t; + +/********************************************************************* +* Random Number Generator (RNG) +*********************************************************************/ + +typedef struct rng { + u32 rngcr; + u32 rngsr; + u32 rnger; + u32 rngout; +} rng_t; + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ + +typedef struct sdramc { + u32 sdmr; /* SDRAM Mode/Extended Mode Register */ + u32 sdcr; /* SDRAM Control Register */ + u32 sdcfg1; /* SDRAM Configuration Register 1 */ + u32 sdcfg2; /* SDRAM Chip Select Register */ + u8 resv0[0x100]; + u32 sdcs0; /* SDRAM Mode/Extended Mode Register */ + u32 sdcs1; /* SDRAM Mode/Extended Mode Register */ +} sdramc_t; + +/********************************************************************* +* Synchronous Serial Interface (SSI) +*********************************************************************/ + +typedef struct ssi { + u32 tx0; + u32 tx1; + u32 rx0; + u32 rx1; + u32 cr; + u32 isr; + u32 ier; + u32 tcr; + u32 rcr; + u32 ccr; + u8 resv0[0x4]; + u32 fcsr; + u8 resv1[0x8]; + u32 acr; + u32 acadd; + u32 acdat; + u32 atag; + u32 tmask; + u32 rmask; +} ssi_t; + +/********************************************************************* +* Phase Locked Loop (PLL) +*********************************************************************/ + +typedef struct pll { + u32 pcr; /* PLL Control Register */ + u32 psr; /* PLL Status Register */ +} pll_t; + +typedef struct pci { + u32 idr; /* 0x00 Device Id / Vendor Id Register */ + u32 scr; /* 0x04 Status / command Register */ + u32 ccrir; /* 0x08 Class Code / Revision Id Register */ + u32 cr1; /* 0x0c Configuration 1 Register */ + u32 bar0; /* 0x10 Base address register 0 Register */ + u32 bar1; /* 0x14 Base address register 1 Register */ + u32 bar2; /* 0x18 Base address register 2 Register */ + u32 bar3; /* 0x1c Base address register 3 Register */ + u32 bar4; /* 0x20 Base address register 4 Register */ + u32 bar5; /* 0x24 Base address register 5 Register */ + u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */ + u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */ + u32 erbar; /* 0x30 Expansion ROM Base Address Register */ + u32 cpr; /* 0x34 Capabilities Pointer Register */ + u32 rsvd1; /* 0x38 */ + u32 cr2; /* 0x3c Configuration Register 2 */ + u32 rsvd2[8]; /* 0x40 - 0x5f */ + + /* General control / status registers */ + u32 gscr; /* 0x60 Global Status / Control Register */ + u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */ + u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */ + u32 tcr1; /* 0x6c Target Control 1 Register */ + u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */ + u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */ + u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */ + u32 rsvd3; /* 0x7c */ + u32 iwcr; /* 0x80 Initiator Window Configuration Register */ + u32 icr; /* 0x84 Initiator Control Register */ + u32 isr; /* 0x88 Initiator Status Register */ + u32 tcr2; /* 0x8c Target Control 2 Register */ + u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */ + u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */ + u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */ + u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */ + u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */ + u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */ + u32 intr; /* 0xa8 Interrupt Register */ + u32 rsvd4[19]; /* 0xac - 0xf7 */ + u32 car; /* 0xf8 Configuration Address Register */ +} pci_t; + +typedef struct pci_arbiter { + /* Pci Arbiter Registers */ + union { + u32 acr; /* Arbiter Control Register */ + u32 asr; /* Arbiter Status Register */ + }; +} pciarb_t; + +/* Register read/write struct */ +typedef struct scm1 { + u32 mpr; /* 0x00 Master Privilege Register */ + u32 rsvd1[7]; + u32 pacra; /* 0x20 Peripheral Access Control Register A */ + u32 pacrb; /* 0x24 Peripheral Access Control Register B */ + u32 pacrc; /* 0x28 Peripheral Access Control Register C */ + u32 pacrd; /* 0x2C Peripheral Access Control Register D */ + u32 rsvd2[4]; + u32 pacre; /* 0x40 Peripheral Access Control Register E */ + u32 pacrf; /* 0x44 Peripheral Access Control Register F */ + u32 pacrg; /* 0x48 Peripheral Access Control Register G */ +} scm1_t; +/********************************************************************/ + +typedef struct rtcex { + u32 rsvd1[3]; + u32 gocu; + u32 gocl; +} rtcex_t; +#endif /* __IMMAP_5445X__ */ diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h new file mode 100644 index 00000000000..8b886b0b605 --- /dev/null +++ b/include/asm-m68k/m5445x.h @@ -0,0 +1,1541 @@ +/* + * MCF5445x Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MCF5445X__ +#define __MCF5445X__ + +/********************************************************************* +* Cross-bar switch (XBS) +*********************************************************************/ + +/* Bit definitions and macros for PRS group */ +#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */ +#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */ +#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */ +#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */ +#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */ +#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */ +#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */ + +/* Bit definitions and macros for CRS group */ +#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */ +#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */ +#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */ +#define XBS_CRS_RO (0x80000000) /* Read Only */ + +#define XBS_CRS_PCTL_PARK_FIELD (0) +#define XBS_CRS_PCTL_PARK_ON_LAST (1) +#define XBS_CRS_PCTL_PARK_NONE (2) +#define XBS_CRS_PCTL_PARK_CORE (0) +#define XBS_CRS_PCTL_PARK_EDMA (1) +#define XBS_CRS_PCTL_PARK_FEC0 (2) +#define XBS_CRS_PCTL_PARK_FEC1 (3) +#define XBS_CRS_PCTL_PARK_PCI (5) +#define XBS_CRS_PCTL_PARK_USB (6) +#define XBS_CRS_PCTL_PARK_SBF (7) + +/********************************************************************* +* FlexBus Chip Selects (FBCS) +*********************************************************************/ + +/* Bit definitions and macros for CSAR group */ +#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for CSMR group */ +#define FBCS_CSMR_V (0x00000001) /* Valid bit */ +#define FBCS_CSMR_WP (0x00000100) /* Write protect */ +#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ +#define FBCS_CSMR_BAM_4G (0xFFFF0000) +#define FBCS_CSMR_BAM_2G (0x7FFF0000) +#define FBCS_CSMR_BAM_1G (0x3FFF0000) +#define FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define FBCS_CSMR_BAM_512M (0x1FFF0000) +#define FBCS_CSMR_BAM_256M (0x0FFF0000) +#define FBCS_CSMR_BAM_128M (0x07FF0000) +#define FBCS_CSMR_BAM_64M (0x03FF0000) +#define FBCS_CSMR_BAM_32M (0x01FF0000) +#define FBCS_CSMR_BAM_16M (0x00FF0000) +#define FBCS_CSMR_BAM_8M (0x007F0000) +#define FBCS_CSMR_BAM_4M (0x003F0000) +#define FBCS_CSMR_BAM_2M (0x001F0000) +#define FBCS_CSMR_BAM_1M (0x000F0000) +#define FBCS_CSMR_BAM_1024K (0x000F0000) +#define FBCS_CSMR_BAM_512K (0x00070000) +#define FBCS_CSMR_BAM_256K (0x00030000) +#define FBCS_CSMR_BAM_128K (0x00010000) +#define FBCS_CSMR_BAM_64K (0x00000000) + +/* Bit definitions and macros for CSCR group */ +#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */ +#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */ +#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */ +#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */ +#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */ +#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ +#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */ +#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */ +#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ +#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */ +#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */ + +#define FBCS_CSCR_PS_8 (0x00000040) +#define FBCS_CSCR_PS_16 (0x00000080) +#define FBCS_CSCR_PS_32 (0x00000000) + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_RSVD1 (29) +#define INT0_LO_I2C (30) +#define INT0_LO_QSPI (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_FEC0_TXF (36) +#define INT0_HI_FEC0_TXB (37) +#define INT0_HI_FEC0_UN (38) +#define INT0_HI_FEC0_RL (39) +#define INT0_HI_FEC0_RXF (40) +#define INT0_HI_FEC0_RXB (41) +#define INT0_HI_FEC0_MII (42) +#define INT0_HI_FEC0_LC (43) +#define INT0_HI_FEC0_HBERR (44) +#define INT0_HI_FEC0_GRA (45) +#define INT0_HI_FEC0_EBERR (46) +#define INT0_HI_FEC0_BABT (47) +#define INT0_HI_FEC0_BABR (48) +#define INT0_HI_FEC1_TXF (49) +#define INT0_HI_FEC1_TXB (50) +#define INT0_HI_FEC1_UN (51) +#define INT0_HI_FEC1_RL (52) +#define INT0_HI_FEC1_RXF (53) +#define INT0_HI_FEC1_RXB (54) +#define INT0_HI_FEC1_MII (55) +#define INT0_HI_FEC1_LC (56) +#define INT0_HI_FEC1_HBERR (57) +#define INT0_HI_FEC1_GRA (58) +#define INT0_HI_FEC1_EBERR (59) +#define INT0_HI_FEC1_BABT (60) +#define INT0_HI_FEC1_BABR (61) +#define INT0_HI_SCMIR (62) +#define INT0_HI_RTC_ISR (63) + +#define INT1_HI_DSPI_EOQF (33) +#define INT1_HI_DSPI_TFFF (34) +#define INT1_HI_DSPI_TCF (35) +#define INT1_HI_DSPI_TFUF (36) +#define INT1_HI_DSPI_RFDF (37) +#define INT1_HI_DSPI_RFOF (38) +#define INT1_HI_DSPI_RFOF_TFUF (39) +#define INT1_HI_RNG_EI (40) +#define INT1_HI_PIT0_PIF (43) +#define INT1_HI_PIT1_PIF (44) +#define INT1_HI_PIT2_PIF (45) +#define INT1_HI_PIT3_PIF (46) +#define INT1_HI_USBOTG_USBSTS (47) +#define INT1_HI_SSI_ISR (49) +#define INT1_HI_CCM_UOCSR (53) +#define INT1_HI_ATA_ISR (54) +#define INT1_HI_PCI_SCR (55) +#define INT1_HI_PCI_ASR (56) +#define INT1_HI_PLL_LOCKS (57) + +/* Bit definitions and macros for IPRH */ +#define INTC_IPRH_INT32 (0x00000001) +#define INTC_IPRH_INT33 (0x00000002) +#define INTC_IPRH_INT34 (0x00000004) +#define INTC_IPRH_INT35 (0x00000008) +#define INTC_IPRH_INT36 (0x00000010) +#define INTC_IPRH_INT37 (0x00000020) +#define INTC_IPRH_INT38 (0x00000040) +#define INTC_IPRH_INT39 (0x00000080) +#define INTC_IPRH_INT40 (0x00000100) +#define INTC_IPRH_INT41 (0x00000200) +#define INTC_IPRH_INT42 (0x00000400) +#define INTC_IPRH_INT43 (0x00000800) +#define INTC_IPRH_INT44 (0x00001000) +#define INTC_IPRH_INT45 (0x00002000) +#define INTC_IPRH_INT46 (0x00004000) +#define INTC_IPRH_INT47 (0x00008000) +#define INTC_IPRH_INT48 (0x00010000) +#define INTC_IPRH_INT49 (0x00020000) +#define INTC_IPRH_INT50 (0x00040000) +#define INTC_IPRH_INT51 (0x00080000) +#define INTC_IPRH_INT52 (0x00100000) +#define INTC_IPRH_INT53 (0x00200000) +#define INTC_IPRH_INT54 (0x00400000) +#define INTC_IPRH_INT55 (0x00800000) +#define INTC_IPRH_INT56 (0x01000000) +#define INTC_IPRH_INT57 (0x02000000) +#define INTC_IPRH_INT58 (0x04000000) +#define INTC_IPRH_INT59 (0x08000000) +#define INTC_IPRH_INT60 (0x10000000) +#define INTC_IPRH_INT61 (0x20000000) +#define INTC_IPRH_INT62 (0x40000000) +#define INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for IPRL */ +#define INTC_IPRL_INT0 (0x00000001) +#define INTC_IPRL_INT1 (0x00000002) +#define INTC_IPRL_INT2 (0x00000004) +#define INTC_IPRL_INT3 (0x00000008) +#define INTC_IPRL_INT4 (0x00000010) +#define INTC_IPRL_INT5 (0x00000020) +#define INTC_IPRL_INT6 (0x00000040) +#define INTC_IPRL_INT7 (0x00000080) +#define INTC_IPRL_INT8 (0x00000100) +#define INTC_IPRL_INT9 (0x00000200) +#define INTC_IPRL_INT10 (0x00000400) +#define INTC_IPRL_INT11 (0x00000800) +#define INTC_IPRL_INT12 (0x00001000) +#define INTC_IPRL_INT13 (0x00002000) +#define INTC_IPRL_INT14 (0x00004000) +#define INTC_IPRL_INT15 (0x00008000) +#define INTC_IPRL_INT16 (0x00010000) +#define INTC_IPRL_INT17 (0x00020000) +#define INTC_IPRL_INT18 (0x00040000) +#define INTC_IPRL_INT19 (0x00080000) +#define INTC_IPRL_INT20 (0x00100000) +#define INTC_IPRL_INT21 (0x00200000) +#define INTC_IPRL_INT22 (0x00400000) +#define INTC_IPRL_INT23 (0x00800000) +#define INTC_IPRL_INT24 (0x01000000) +#define INTC_IPRL_INT25 (0x02000000) +#define INTC_IPRL_INT26 (0x04000000) +#define INTC_IPRL_INT27 (0x08000000) +#define INTC_IPRL_INT28 (0x10000000) +#define INTC_IPRL_INT29 (0x20000000) +#define INTC_IPRL_INT30 (0x40000000) +#define INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for IMRH */ +#define INTC_IMRH_INT_MASK32 (0x00000001) +#define INTC_IMRH_INT_MASK33 (0x00000002) +#define INTC_IMRH_INT_MASK34 (0x00000004) +#define INTC_IMRH_INT_MASK35 (0x00000008) +#define INTC_IMRH_INT_MASK36 (0x00000010) +#define INTC_IMRH_INT_MASK37 (0x00000020) +#define INTC_IMRH_INT_MASK38 (0x00000040) +#define INTC_IMRH_INT_MASK39 (0x00000080) +#define INTC_IMRH_INT_MASK40 (0x00000100) +#define INTC_IMRH_INT_MASK41 (0x00000200) +#define INTC_IMRH_INT_MASK42 (0x00000400) +#define INTC_IMRH_INT_MASK43 (0x00000800) +#define INTC_IMRH_INT_MASK44 (0x00001000) +#define INTC_IMRH_INT_MASK45 (0x00002000) +#define INTC_IMRH_INT_MASK46 (0x00004000) +#define INTC_IMRH_INT_MASK47 (0x00008000) +#define INTC_IMRH_INT_MASK48 (0x00010000) +#define INTC_IMRH_INT_MASK49 (0x00020000) +#define INTC_IMRH_INT_MASK50 (0x00040000) +#define INTC_IMRH_INT_MASK51 (0x00080000) +#define INTC_IMRH_INT_MASK52 (0x00100000) +#define INTC_IMRH_INT_MASK53 (0x00200000) +#define INTC_IMRH_INT_MASK54 (0x00400000) +#define INTC_IMRH_INT_MASK55 (0x00800000) +#define INTC_IMRH_INT_MASK56 (0x01000000) +#define INTC_IMRH_INT_MASK57 (0x02000000) +#define INTC_IMRH_INT_MASK58 (0x04000000) +#define INTC_IMRH_INT_MASK59 (0x08000000) +#define INTC_IMRH_INT_MASK60 (0x10000000) +#define INTC_IMRH_INT_MASK61 (0x20000000) +#define INTC_IMRH_INT_MASK62 (0x40000000) +#define INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for IMRL */ +#define INTC_IMRL_INT_MASK0 (0x00000001) +#define INTC_IMRL_INT_MASK1 (0x00000002) +#define INTC_IMRL_INT_MASK2 (0x00000004) +#define INTC_IMRL_INT_MASK3 (0x00000008) +#define INTC_IMRL_INT_MASK4 (0x00000010) +#define INTC_IMRL_INT_MASK5 (0x00000020) +#define INTC_IMRL_INT_MASK6 (0x00000040) +#define INTC_IMRL_INT_MASK7 (0x00000080) +#define INTC_IMRL_INT_MASK8 (0x00000100) +#define INTC_IMRL_INT_MASK9 (0x00000200) +#define INTC_IMRL_INT_MASK10 (0x00000400) +#define INTC_IMRL_INT_MASK11 (0x00000800) +#define INTC_IMRL_INT_MASK12 (0x00001000) +#define INTC_IMRL_INT_MASK13 (0x00002000) +#define INTC_IMRL_INT_MASK14 (0x00004000) +#define INTC_IMRL_INT_MASK15 (0x00008000) +#define INTC_IMRL_INT_MASK16 (0x00010000) +#define INTC_IMRL_INT_MASK17 (0x00020000) +#define INTC_IMRL_INT_MASK18 (0x00040000) +#define INTC_IMRL_INT_MASK19 (0x00080000) +#define INTC_IMRL_INT_MASK20 (0x00100000) +#define INTC_IMRL_INT_MASK21 (0x00200000) +#define INTC_IMRL_INT_MASK22 (0x00400000) +#define INTC_IMRL_INT_MASK23 (0x00800000) +#define INTC_IMRL_INT_MASK24 (0x01000000) +#define INTC_IMRL_INT_MASK25 (0x02000000) +#define INTC_IMRL_INT_MASK26 (0x04000000) +#define INTC_IMRL_INT_MASK27 (0x08000000) +#define INTC_IMRL_INT_MASK28 (0x10000000) +#define INTC_IMRL_INT_MASK29 (0x20000000) +#define INTC_IMRL_INT_MASK30 (0x40000000) +#define INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for INTFRCH */ +#define INTC_INTFRCH_INTFRC32 (0x00000001) +#define INTC_INTFRCH_INTFRC33 (0x00000002) +#define INTC_INTFRCH_INTFRC34 (0x00000004) +#define INTC_INTFRCH_INTFRC35 (0x00000008) +#define INTC_INTFRCH_INTFRC36 (0x00000010) +#define INTC_INTFRCH_INTFRC37 (0x00000020) +#define INTC_INTFRCH_INTFRC38 (0x00000040) +#define INTC_INTFRCH_INTFRC39 (0x00000080) +#define INTC_INTFRCH_INTFRC40 (0x00000100) +#define INTC_INTFRCH_INTFRC41 (0x00000200) +#define INTC_INTFRCH_INTFRC42 (0x00000400) +#define INTC_INTFRCH_INTFRC43 (0x00000800) +#define INTC_INTFRCH_INTFRC44 (0x00001000) +#define INTC_INTFRCH_INTFRC45 (0x00002000) +#define INTC_INTFRCH_INTFRC46 (0x00004000) +#define INTC_INTFRCH_INTFRC47 (0x00008000) +#define INTC_INTFRCH_INTFRC48 (0x00010000) +#define INTC_INTFRCH_INTFRC49 (0x00020000) +#define INTC_INTFRCH_INTFRC50 (0x00040000) +#define INTC_INTFRCH_INTFRC51 (0x00080000) +#define INTC_INTFRCH_INTFRC52 (0x00100000) +#define INTC_INTFRCH_INTFRC53 (0x00200000) +#define INTC_INTFRCH_INTFRC54 (0x00400000) +#define INTC_INTFRCH_INTFRC55 (0x00800000) +#define INTC_INTFRCH_INTFRC56 (0x01000000) +#define INTC_INTFRCH_INTFRC57 (0x02000000) +#define INTC_INTFRCH_INTFRC58 (0x04000000) +#define INTC_INTFRCH_INTFRC59 (0x08000000) +#define INTC_INTFRCH_INTFRC60 (0x10000000) +#define INTC_INTFRCH_INTFRC61 (0x20000000) +#define INTC_INTFRCH_INTFRC62 (0x40000000) +#define INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for INTFRCL */ +#define INTC_INTFRCL_INTFRC0 (0x00000001) +#define INTC_INTFRCL_INTFRC1 (0x00000002) +#define INTC_INTFRCL_INTFRC2 (0x00000004) +#define INTC_INTFRCL_INTFRC3 (0x00000008) +#define INTC_INTFRCL_INTFRC4 (0x00000010) +#define INTC_INTFRCL_INTFRC5 (0x00000020) +#define INTC_INTFRCL_INTFRC6 (0x00000040) +#define INTC_INTFRCL_INTFRC7 (0x00000080) +#define INTC_INTFRCL_INTFRC8 (0x00000100) +#define INTC_INTFRCL_INTFRC9 (0x00000200) +#define INTC_INTFRCL_INTFRC10 (0x00000400) +#define INTC_INTFRCL_INTFRC11 (0x00000800) +#define INTC_INTFRCL_INTFRC12 (0x00001000) +#define INTC_INTFRCL_INTFRC13 (0x00002000) +#define INTC_INTFRCL_INTFRC14 (0x00004000) +#define INTC_INTFRCL_INTFRC15 (0x00008000) +#define INTC_INTFRCL_INTFRC16 (0x00010000) +#define INTC_INTFRCL_INTFRC17 (0x00020000) +#define INTC_INTFRCL_INTFRC18 (0x00040000) +#define INTC_INTFRCL_INTFRC19 (0x00080000) +#define INTC_INTFRCL_INTFRC20 (0x00100000) +#define INTC_INTFRCL_INTFRC21 (0x00200000) +#define INTC_INTFRCL_INTFRC22 (0x00400000) +#define INTC_INTFRCL_INTFRC23 (0x00800000) +#define INTC_INTFRCL_INTFRC24 (0x01000000) +#define INTC_INTFRCL_INTFRC25 (0x02000000) +#define INTC_INTFRCL_INTFRC26 (0x04000000) +#define INTC_INTFRCL_INTFRC27 (0x08000000) +#define INTC_INTFRCL_INTFRC28 (0x10000000) +#define INTC_INTFRCL_INTFRC29 (0x20000000) +#define INTC_INTFRCL_INTFRC30 (0x40000000) +#define INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for ICONFIG */ +#define INTC_ICONFIG_EMASK (0x0020) +#define INTC_ICONFIG_ELVLPRI1 (0x0200) +#define INTC_ICONFIG_ELVLPRI2 (0x0400) +#define INTC_ICONFIG_ELVLPRI3 (0x0800) +#define INTC_ICONFIG_ELVLPRI4 (0x1000) +#define INTC_ICONFIG_ELVLPRI5 (0x2000) +#define INTC_ICONFIG_ELVLPRI6 (0x4000) +#define INTC_ICONFIG_ELVLPRI7 (0x8000) + +/* Bit definitions and macros for SIMR */ +#define INTC_SIMR_SIMR(x) (((x)&0x7F)) + +/* Bit definitions and macros for CIMR */ +#define INTC_CIMR_CIMR(x) (((x)&0x7F)) + +/* Bit definitions and macros for CLMASK */ +#define INTC_CLMASK_CLMASK(x) (((x)&0x0F)) + +/* Bit definitions and macros for SLMASK */ +#define INTC_SLMASK_SLMASK(x) (((x)&0x0F)) + +/* Bit definitions and macros for ICR group */ +#define INTC_ICR_IL(x) (((x)&0x07)) + +/********************************************************************* +* DMA Serial Peripheral Interface (DSPI) +*********************************************************************/ + +/* Bit definitions and macros for DMCR */ +#define DSPI_DMCR_HALT (0x00000001) +#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) +#define DSPI_DMCR_CRXF (0x00000400) +#define DSPI_DMCR_CTXF (0x00000800) +#define DSPI_DMCR_DRXF (0x00001000) +#define DSPI_DMCR_DTXF (0x00002000) +#define DSPI_DMCR_CSIS0 (0x00010000) +#define DSPI_DMCR_CSIS2 (0x00040000) +#define DSPI_DMCR_CSIS3 (0x00080000) +#define DSPI_DMCR_CSIS5 (0x00200000) +#define DSPI_DMCR_ROOE (0x01000000) +#define DSPI_DMCR_PCSSE (0x02000000) +#define DSPI_DMCR_MTFE (0x04000000) +#define DSPI_DMCR_FRZ (0x08000000) +#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) +#define DSPI_DMCR_CSCK (0x40000000) +#define DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for DTCR */ +#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for DCTAR group */ +#define DSPI_DCTAR_BR(x) (((x)&0x0000000F)) +#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) +#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) +#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) +#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) +#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) +#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) +#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) +#define DSPI_DCTAR_LSBFE (0x01000000) +#define DSPI_DCTAR_CPHA (0x02000000) +#define DSPI_DCTAR_CPOL (0x04000000) +#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) +#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000) +#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000) +#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000) +#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000) +#define DSPI_DCTAR_PASC_1CLK (0x00000000) +#define DSPI_DCTAR_PASC_3CLK (0x00100000) +#define DSPI_DCTAR_PASC_5CLK (0x00200000) +#define DSPI_DCTAR_PASC_7CLK (0x00300000) +#define DSPI_DCTAR_PDT_1CLK (0x00000000) +#define DSPI_DCTAR_PDT_3CLK (0x00040000) +#define DSPI_DCTAR_PDT_5CLK (0x00080000) +#define DSPI_DCTAR_PDT_7CLK (0x000A0000) +#define DSPI_DCTAR_PBR_1CLK (0x00000000) +#define DSPI_DCTAR_PBR_3CLK (0x00010000) +#define DSPI_DCTAR_PBR_5CLK (0x00020000) +#define DSPI_DCTAR_PBR_7CLK (0x00030000) + +/* Bit definitions and macros for DSR */ +#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F)) +#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) +#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) +#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) +#define DSPI_DSR_RFDF (0x00020000) +#define DSPI_DSR_RFOF (0x00080000) +#define DSPI_DSR_TFFF (0x02000000) +#define DSPI_DSR_TFUF (0x08000000) +#define DSPI_DSR_EOQF (0x10000000) +#define DSPI_DSR_TXRXS (0x40000000) +#define DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for DIRSR */ +#define DSPI_DIRSR_RFDFS (0x00010000) +#define DSPI_DIRSR_RFDFE (0x00020000) +#define DSPI_DIRSR_RFOFE (0x00080000) +#define DSPI_DIRSR_TFFFS (0x01000000) +#define DSPI_DIRSR_TFFFE (0x02000000) +#define DSPI_DIRSR_TFUFE (0x08000000) +#define DSPI_DIRSR_EOQFE (0x10000000) +#define DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for DTFR */ +#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)) +#define DSPI_DTFR_CS0 (0x00010000) +#define DSPI_DTFR_CS2 (0x00040000) +#define DSPI_DTFR_CS3 (0x00080000) +#define DSPI_DTFR_CS5 (0x00200000) +#define DSPI_DTFR_CTCNT (0x04000000) +#define DSPI_DTFR_EOQ (0x08000000) +#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) +#define DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for DRFR */ +#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)) + +/* Bit definitions and macros for DTFDR group */ +#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF)) +#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for DRFDR group */ +#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF)) + +/********************************************************************* +* Edge Port Module (EPORT) +*********************************************************************/ + +/* Bit definitions and macros for EPPAR */ +#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define EPORT_EPPAR_LEVEL (0) +#define EPORT_EPPAR_RISING (1) +#define EPORT_EPPAR_FALLING (2) +#define EPORT_EPPAR_BOTH (3) +#define EPORT_EPPAR_EPPA7_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA7_RISING (0x4000) +#define EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define EPORT_EPPAR_EPPA6_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA6_RISING (0x1000) +#define EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define EPORT_EPPAR_EPPA5_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA5_RISING (0x0400) +#define EPORT_EPPAR_EPPA5_FALLING (0x0800) +#define EPORT_EPPAR_EPPA5_BOTH (0x0C00) +#define EPORT_EPPAR_EPPA4_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA4_RISING (0x0100) +#define EPORT_EPPAR_EPPA4_FALLING (0x0200) +#define EPORT_EPPAR_EPPA4_BOTH (0x0300) +#define EPORT_EPPAR_EPPA3_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA3_RISING (0x0040) +#define EPORT_EPPAR_EPPA3_FALLING (0x0080) +#define EPORT_EPPAR_EPPA3_BOTH (0x00C0) +#define EPORT_EPPAR_EPPA2_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA2_RISING (0x0010) +#define EPORT_EPPAR_EPPA2_FALLING (0x0020) +#define EPORT_EPPAR_EPPA2_BOTH (0x0030) +#define EPORT_EPPAR_EPPA1_LEVEL (0x0000) +#define EPORT_EPPAR_EPPA1_RISING (0x0004) +#define EPORT_EPPAR_EPPA1_FALLING (0x0008) +#define EPORT_EPPAR_EPPA1_BOTH (0x000C) + +/* Bit definitions and macros for EPDDR */ +#define EPORT_EPDDR_EPDD1 (0x02) +#define EPORT_EPDDR_EPDD2 (0x04) +#define EPORT_EPDDR_EPDD3 (0x08) +#define EPORT_EPDDR_EPDD4 (0x10) +#define EPORT_EPDDR_EPDD5 (0x20) +#define EPORT_EPDDR_EPDD6 (0x40) +#define EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for EPIER */ +#define EPORT_EPIER_EPIE1 (0x02) +#define EPORT_EPIER_EPIE2 (0x04) +#define EPORT_EPIER_EPIE3 (0x08) +#define EPORT_EPIER_EPIE4 (0x10) +#define EPORT_EPIER_EPIE5 (0x20) +#define EPORT_EPIER_EPIE6 (0x40) +#define EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for EPDR */ +#define EPORT_EPDR_EPD1 (0x02) +#define EPORT_EPDR_EPD2 (0x04) +#define EPORT_EPDR_EPD3 (0x08) +#define EPORT_EPDR_EPD4 (0x10) +#define EPORT_EPDR_EPD5 (0x20) +#define EPORT_EPDR_EPD6 (0x40) +#define EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for EPPDR */ +#define EPORT_EPPDR_EPPD1 (0x02) +#define EPORT_EPPDR_EPPD2 (0x04) +#define EPORT_EPPDR_EPPD3 (0x08) +#define EPORT_EPPDR_EPPD4 (0x10) +#define EPORT_EPPDR_EPPD5 (0x20) +#define EPORT_EPPDR_EPPD6 (0x40) +#define EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for EPFR */ +#define EPORT_EPFR_EPF1 (0x02) +#define EPORT_EPFR_EPF2 (0x04) +#define EPORT_EPFR_EPF3 (0x08) +#define EPORT_EPFR_EPF4 (0x10) +#define EPORT_EPFR_EPF5 (0x20) +#define EPORT_EPFR_EPF6 (0x40) +#define EPORT_EPFR_EPF7 (0x80) + +/********************************************************************* +* Watchdog Timer Modules (WTM) +*********************************************************************/ + +/* Bit definitions and macros for WCR */ +#define WTM_WCR_EN (0x0001) +#define WTM_WCR_HALTED (0x0002) +#define WTM_WCR_DOZE (0x0004) +#define WTM_WCR_WAIT (0x0008) + +/********************************************************************* +* Serial Boot Facility (SBF) +*********************************************************************/ + +/* Bit definitions and macros for SBFCR */ +#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */ +#define SBF_SBFCR_FR (0x0010) /* Fast read */ + +/********************************************************************* +* Reset Controller Module (RCM) +*********************************************************************/ + +/* Bit definitions and macros for RCR */ +#define RCM_RCR_FRCRSTOUT (0x40) +#define RCM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for RSR */ +#define RCM_RSR_LOL (0x01) +#define RCM_RSR_WDR_CORE (0x02) +#define RCM_RSR_EXT (0x04) +#define RCM_RSR_POR (0x08) +#define RCM_RSR_SOFT (0x20) + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ + +/* Bit definitions and macros for CCR_360 */ +#define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */ +#define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ +#define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */ +#define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ +#define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */ +#define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */ +#define CCM_CCR_360_FBCONFIG_MASK (0x00E0) +#define CCM_CCR_360_PLLMULT2_MASK (0x0003) +#define CCM_CCR_360_PLLMULT3_MASK (0x0007) +#define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000) +#define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020) +#define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040) +#define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060) +#define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080) +#define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0) +#define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0) +#define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0) +#define CCM_CCR_360_PLLMULT2_12X (0x0000) +#define CCM_CCR_360_PLLMULT2_6X (0x0001) +#define CCM_CCR_360_PLLMULT2_16X (0x0002) +#define CCM_CCR_360_PLLMULT2_8X (0x0003) +#define CCM_CCR_360_PLLMULT3_20X (0x0000) +#define CCM_CCR_360_PLLMULT3_10X (0x0001) +#define CCM_CCR_360_PLLMULT3_24X (0x0002) +#define CCM_CCR_360_PLLMULT3_18X (0x0003) +#define CCM_CCR_360_PLLMULT3_12X (0x0004) +#define CCM_CCR_360_PLLMULT3_6X (0x0005) +#define CCM_CCR_360_PLLMULT3_16X (0x0006) +#define CCM_CCR_360_PLLMULT3_8X (0x0007) + +/* Bit definitions and macros for CCR_256 */ +#define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */ +#define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */ +#define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ +#define CCM_CCR_256_FBCONFIG_MASK (0x00E0) +#define CCM_CCR_256_FBCONFIG_NM_32 (0x0000) +#define CCM_CCR_256_FBCONFIG_NM_8 (0x0020) +#define CCM_CCR_256_FBCONFIG_NM_16 (0x0040) +#define CCM_CCR_256_FBCONFIG_M_32 (0x0080) +#define CCM_CCR_256_FBCONFIG_M_8 (0x00A0) +#define CCM_CCR_256_FBCONFIG_M_16 (0x00C0) +#define CCM_CCR_256_PLLMULT3_MASK (0x0007) +#define CCM_CCR_256_PLLMULT3_20X (0x0000) +#define CCM_CCR_256_PLLMULT3_10X (0x0001) +#define CCM_CCR_256_PLLMULT3_24X (0x0002) +#define CCM_CCR_256_PLLMULT3_18X (0x0003) +#define CCM_CCR_256_PLLMULT3_12X (0x0004) +#define CCM_CCR_256_PLLMULT3_6X (0x0005) +#define CCM_CCR_256_PLLMULT3_16X (0x0006) +#define CCM_CCR_256_PLLMULT3_8X (0x0007) + +/* Bit definitions and macros for RCON_360 */ +#define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ +#define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ +#define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */ +#define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ + +/* Bit definitions and macros for RCON_256 */ +#define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */ +#define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */ +#define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */ +#define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ + +/* Bit definitions and macros for CIR */ +#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ +#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ +#define CCM_CIR_PIN_MASK (0xFFC0) +#define CCM_CIR_PRN_MASK (0x003F) +#define CCM_CIR_PIN_MCF54450 (0x4F<<6) +#define CCM_CIR_PIN_MCF54451 (0x4D<<6) +#define CCM_CIR_PIN_MCF54452 (0x4B<<6) +#define CCM_CIR_PIN_MCF54453 (0x49<<6) +#define CCM_CIR_PIN_MCF54454 (0x4A<<6) +#define CCM_CIR_PIN_MCF54455 (0x48<<6) + +/* Bit definitions and macros for MISCCR */ +#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ +#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */ +#define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */ +#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ +#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ +#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ +#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ +#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */ +#define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */ +#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ +#define CCM_MISCCR_BMT_65536 (0) +#define CCM_MISCCR_BMT_32768 (1) +#define CCM_MISCCR_BMT_16384 (2) +#define CCM_MISCCR_BMT_8192 (3) +#define CCM_MISCCR_BMT_4096 (4) +#define CCM_MISCCR_BMT_2048 (5) +#define CCM_MISCCR_BMT_1024 (6) +#define CCM_MISCCR_BMT_512 (7) +#define CCM_MISCCR_SSIPUS_UP (1) +#define CCM_MISCCR_SSIPUS_DOWN (0) +#define CCM_MISCCR_TIMDMA_TIM (1) +#define CCM_MISCCR_TIMDMA_SSI (0) +#define CCM_MISCCR_SSISRC_CLKIN (0) +#define CCM_MISCCR_SSISRC_PLL (1) +#define CCM_MISCCR_USBOC_ACTHI (0) +#define CCM_MISCCR_USBOV_ACTLO (1) +#define CCM_MISCCR_USBSRC_CLKIN (0) +#define CCM_MISCCR_USBSRC_PLL (1) + +/* Bit definitions and macros for CDR */ +#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */ +#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */ + +/* Bit definitions and macros for UOCSR */ +#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */ +#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */ +#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ +#define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */ +#define CCM_UOCSR_SEND (0x0010) /* Session end */ +#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ +#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ +#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ +#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */ +#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */ +#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */ +#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */ +#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */ + +/********************************************************************* +* General Purpose I/O Module (GPIO) +*********************************************************************/ + +/* Bit definitions and macros for PAR_FEC */ +#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) +#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) +#define GPIO_PAR_FEC_FEC1_MASK (0x8F) +#define GPIO_PAR_FEC_FEC1_MII (0x70) +#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) +#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) +#define GPIO_PAR_FEC_FEC1_ATA (0x10) +#define GPIO_PAR_FEC_FEC1_GPIO (0x00) +#define GPIO_PAR_FEC_FEC0_MASK (0xF8) +#define GPIO_PAR_FEC_FEC0_MII (0x07) +#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) +#define GPIO_PAR_FEC_FEC0_RMII_ATA (0x02) +#define GPIO_PAR_FEC_FEC0_ATA (0x01) +#define GPIO_PAR_FEC_FEC0_GPIO (0x00) + +/* Bit definitions and macros for PAR_DMA */ +#define GPIO_PAR_DMA_DREQ0 (0x01) +#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) +#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) +#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) +#define GPIO_PAR_DMA_DACK1_MASK (0x3F) +#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0) +#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) +#define GPIO_PAR_DMA_DACK1_GPIO (0x00) +#define GPIO_PAR_DMA_DREQ1_MASK (0xCF) +#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) +#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) +#define GPIO_PAR_DMA_DREQ1_GPIO (0x00) +#define GPIO_PAR_DMA_DACK0_MASK (0xF3) +#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) +#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) +#define GPIO_PAR_DMA_DACK0_GPIO (0x00) +#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) +#define GPIO_PAR_DMA_DREQ0_GPIO (0x00) + +/* Bit definitions and macros for PAR_FBCTL */ +#define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) +#define GPIO_PAR_FBCTL_RW (0x20) +#define GPIO_PAR_FBCTL_TA (0x40) +#define GPIO_PAR_FBCTL_OE (0x80) +#define GPIO_PAR_FBCTL_OE_OE (0x80) +#define GPIO_PAR_FBCTL_OE_GPIO (0x00) +#define GPIO_PAR_FBCTL_TA_TA (0x40) +#define GPIO_PAR_FBCTL_TA_GPIO (0x00) +#define GPIO_PAR_FBCTL_RW_RW (0x20) +#define GPIO_PAR_FBCTL_RW_GPIO (0x00) +#define GPIO_PAR_FBCTL_TS_MASK (0xE7) +#define GPIO_PAR_FBCTL_TS_TS (0x18) +#define GPIO_PAR_FBCTL_TS_ALE (0x10) +#define GPIO_PAR_FBCTL_TS_TBST (0x08) +#define GPIO_PAR_FBCTL_TS_GPIO (0x80) + +/* Bit definitions and macros for PAR_DSPI */ +#define GPIO_PAR_DSPI_SCK (0x01) +#define GPIO_PAR_DSPI_SOUT (0x02) +#define GPIO_PAR_DSPI_SIN (0x04) +#define GPIO_PAR_DSPI_PCS0 (0x08) +#define GPIO_PAR_DSPI_PCS1 (0x10) +#define GPIO_PAR_DSPI_PCS2 (0x20) +#define GPIO_PAR_DSPI_PCS5 (0x40) +#define GPIO_PAR_DSPI_PCS5_PCS5 (0x40) +#define GPIO_PAR_DSPI_PCS5_GPIO (0x00) +#define GPIO_PAR_DSPI_PCS2_PCS2 (0x20) +#define GPIO_PAR_DSPI_PCS2_GPIO (0x00) +#define GPIO_PAR_DSPI_PCS1_PCS1 (0x10) +#define GPIO_PAR_DSPI_PCS1_GPIO (0x00) +#define GPIO_PAR_DSPI_PCS0_PCS0 (0x08) +#define GPIO_PAR_DSPI_PCS0_GPIO (0x00) +#define GPIO_PAR_DSPI_SIN_SIN (0x04) +#define GPIO_PAR_DSPI_SIN_GPIO (0x00) +#define GPIO_PAR_DSPI_SOUT_SOUT (0x02) +#define GPIO_PAR_DSPI_SOUT_GPIO (0x00) +#define GPIO_PAR_DSPI_SCK_SCK (0x01) +#define GPIO_PAR_DSPI_SCK_GPIO (0x00) + +/* Bit definitions and macros for PAR_BE */ +#define GPIO_PAR_BE_BS0 (0x01) +#define GPIO_PAR_BE_BS1 (0x04) +#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) +#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) +#define GPIO_PAR_BE_BE3_MASK (0x3F) +#define GPIO_PAR_BE_BE3_BE3 (0xC0) +#define GPIO_PAR_BE_BE3_TSIZ1 (0x80) +#define GPIO_PAR_BE_BE3_GPIO (0x00) +#define GPIO_PAR_BE_BE2_MASK (0xCF) +#define GPIO_PAR_BE_BE2_BE2 (0x30) +#define GPIO_PAR_BE_BE2_TSIZ0 (0x20) +#define GPIO_PAR_BE_BE2_GPIO (0x00) +#define GPIO_PAR_BE_BE1_BE1 (0x04) +#define GPIO_PAR_BE_BE1_GPIO (0x00) +#define GPIO_PAR_BE_BE0_BE0 (0x01) +#define GPIO_PAR_BE_BE0_GPIO (0x00) + +/* Bit definitions and macros for PAR_CS */ +#define GPIO_PAR_CS_CS1 (0x02) +#define GPIO_PAR_CS_CS2 (0x04) +#define GPIO_PAR_CS_CS3 (0x08) +#define GPIO_PAR_CS_CS3_CS3 (0x08) +#define GPIO_PAR_CS_CS3_GPIO (0x00) +#define GPIO_PAR_CS_CS2_CS2 (0x04) +#define GPIO_PAR_CS_CS2_GPIO (0x00) +#define GPIO_PAR_CS_CS1_CS1 (0x02) +#define GPIO_PAR_CS_CS1_GPIO (0x00) + +/* Bit definitions and macros for PAR_TIMER */ +#define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) +#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) +#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) +#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) +#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) +#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) +#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40) +#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) +#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) +#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10) +#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) +#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) +#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04) +#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) +#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) +#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01) +#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) + +/* Bit definitions and macros for PAR_USB */ +#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) +#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) +#define GPIO_PAR_USB_VBUSEN_MASK (0xF3) +#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) +#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) +#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) +#define GPIO_PAR_USB_VBUSEN_GPIO (0x00) +#define GPIO_PAR_USB_VBUSOC_MASK (0xFC) +#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) +#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) +#define GPIO_PAR_USB_VBUSOC_GPIO (0x00) + +/* Bit definitions and macros for PAR_UART */ +#define GPIO_PAR_UART_U0TXD (0x01) +#define GPIO_PAR_UART_U0RXD (0x02) +#define GPIO_PAR_UART_U0RTS (0x04) +#define GPIO_PAR_UART_U0CTS (0x08) +#define GPIO_PAR_UART_U1TXD (0x10) +#define GPIO_PAR_UART_U1RXD (0x20) +#define GPIO_PAR_UART_U1RTS (0x40) +#define GPIO_PAR_UART_U1CTS (0x80) +#define GPIO_PAR_UART_U1CTS_U1CTS (0x80) +#define GPIO_PAR_UART_U1CTS_GPIO (0x00) +#define GPIO_PAR_UART_U1RTS_U1RTS (0x40) +#define GPIO_PAR_UART_U1RTS_GPIO (0x00) +#define GPIO_PAR_UART_U1RXD_U1RXD (0x20) +#define GPIO_PAR_UART_U1RXD_GPIO (0x00) +#define GPIO_PAR_UART_U1TXD_U1TXD (0x10) +#define GPIO_PAR_UART_U1TXD_GPIO (0x00) +#define GPIO_PAR_UART_U0CTS_U0CTS (0x08) +#define GPIO_PAR_UART_U0CTS_GPIO (0x00) +#define GPIO_PAR_UART_U0RTS_U0RTS (0x04) +#define GPIO_PAR_UART_U0RTS_GPIO (0x00) +#define GPIO_PAR_UART_U0RXD_U0RXD (0x02) +#define GPIO_PAR_UART_U0RXD_GPIO (0x00) +#define GPIO_PAR_UART_U0TXD_U0TXD (0x01) +#define GPIO_PAR_UART_U0TXD_GPIO (0x00) + +/* Bit definitions and macros for PAR_FECI2C */ +#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) +#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) +#define GPIO_PAR_FECI2C_MDIO0 (0x0010) +#define GPIO_PAR_FECI2C_MDC0 (0x0040) +#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) +#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) +#define GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF) +#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) +#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) +#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) +#define GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF) +#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) +#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) +#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) +#define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040) +#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) +#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) +#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) +#define GPIO_PAR_FECI2C_SCL_MASK (0xFFF3) +#define GPIO_PAR_FECI2C_SCL_SCL (0x000C) +#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) +#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000) +#define GPIO_PAR_FECI2C_SDA_MASK (0xFFFC) +#define GPIO_PAR_FECI2C_SDA_SDA (0x0003) +#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) +#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000) + +/* Bit definitions and macros for PAR_SSI */ +#define GPIO_PAR_SSI_MCLK (0x0001) +#define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) +#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) +#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) +#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) +#define GPIO_PAR_SSI_BCLK_MASK (0xFCFF) +#define GPIO_PAR_SSI_BCLK_BCLK (0x0300) +#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200) +#define GPIO_PAR_SSI_BCLK_GPIO (0x0000) +#define GPIO_PAR_SSI_FS_MASK (0xFF3F) +#define GPIO_PAR_SSI_FS_FS (0x00C0) +#define GPIO_PAR_SSI_FS_U1RTS (0x0080) +#define GPIO_PAR_SSI_FS_GPIO (0x0000) +#define GPIO_PAR_SSI_SRXD_MASK (0xFFCF) +#define GPIO_PAR_SSI_SRXD_SRXD (0x0030) +#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020) +#define GPIO_PAR_SSI_SRXD_GPIO (0x0000) +#define GPIO_PAR_SSI_STXD_MASK (0xFFF3) +#define GPIO_PAR_SSI_STXD_STXD (0x000C) +#define GPIO_PAR_SSI_STXD_U1TXD (0x0008) +#define GPIO_PAR_SSI_STXD_GPIO (0x0000) +#define GPIO_PAR_SSI_MCLK_MCLK (0x0001) +#define GPIO_PAR_SSI_MCLK_GPIO (0x0000) + +/* Bit definitions and macros for PAR_ATA */ +#define GPIO_PAR_ATA_IORDY (0x0001) +#define GPIO_PAR_ATA_DMARQ (0x0002) +#define GPIO_PAR_ATA_RESET (0x0004) +#define GPIO_PAR_ATA_DA0 (0x0020) +#define GPIO_PAR_ATA_DA1 (0x0040) +#define GPIO_PAR_ATA_DA2 (0x0080) +#define GPIO_PAR_ATA_CS0 (0x0100) +#define GPIO_PAR_ATA_CS1 (0x0200) +#define GPIO_PAR_ATA_BUFEN (0x0400) +#define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400) +#define GPIO_PAR_ATA_BUFEN_GPIO (0x0000) +#define GPIO_PAR_ATA_CS1_CS1 (0x0200) +#define GPIO_PAR_ATA_CS1_GPIO (0x0000) +#define GPIO_PAR_ATA_CS0_CS0 (0x0100) +#define GPIO_PAR_ATA_CS0_GPIO (0x0000) +#define GPIO_PAR_ATA_DA2_DA2 (0x0080) +#define GPIO_PAR_ATA_DA2_GPIO (0x0000) +#define GPIO_PAR_ATA_DA1_DA1 (0x0040) +#define GPIO_PAR_ATA_DA1_GPIO (0x0000) +#define GPIO_PAR_ATA_DA0_DA0 (0x0020) +#define GPIO_PAR_ATA_DA0_GPIO (0x0000) +#define GPIO_PAR_ATA_RESET_RESET (0x0004) +#define GPIO_PAR_ATA_RESET_GPIO (0x0000) +#define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002) +#define GPIO_PAR_ATA_DMARQ_GPIO (0x0000) +#define GPIO_PAR_ATA_IORDY_IORDY (0x0001) +#define GPIO_PAR_ATA_IORDY_GPIO (0x0000) + +/* Bit definitions and macros for PAR_IRQ */ +#define GPIO_PAR_IRQ_IRQ1 (0x02) +#define GPIO_PAR_IRQ_IRQ4 (0x10) +#define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10) +#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) +#define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02) +#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) + +/* Bit definitions and macros for PAR_PCI */ +#define GPIO_PAR_PCI_REQ0 (0x0001) +#define GPIO_PAR_PCI_REQ1 (0x0004) +#define GPIO_PAR_PCI_REQ2 (0x0010) +#define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) +#define GPIO_PAR_PCI_GNT0 (0x0100) +#define GPIO_PAR_PCI_GNT1 (0x0400) +#define GPIO_PAR_PCI_GNT2 (0x1000) +#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) +#define GPIO_PAR_PCI_GNT3_MASK (0x3FFF) +#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000) +#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) +#define GPIO_PAR_PCI_GNT3_GPIO (0x0000) +#define GPIO_PAR_PCI_GNT2_GNT2 (0x1000) +#define GPIO_PAR_PCI_GNT2_GPIO (0x0000) +#define GPIO_PAR_PCI_GNT1_GNT1 (0x0400) +#define GPIO_PAR_PCI_GNT1_GPIO (0x0000) +#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100) +#define GPIO_PAR_PCI_GNT0_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ3_MASK (0xFF3F) +#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) +#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) +#define GPIO_PAR_PCI_REQ3_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ2_REQ2 (0x0010) +#define GPIO_PAR_PCI_REQ2_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ1_REQ1 (0x0040) +#define GPIO_PAR_PCI_REQ1_GPIO (0x0000) +#define GPIO_PAR_PCI_REQ0_REQ0 (0x0001) +#define GPIO_PAR_PCI_REQ0_GPIO (0x0000) + +/* Bit definitions and macros for MSCR_SDRAM */ +#define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) +#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) +#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) +#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) +#define GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F) +#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) +#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) +#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) +#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) +#define GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF) +#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) +#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) +#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) +#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) +#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) +#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) +#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) +#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) +#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) +#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) +#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) +#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) +#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) +#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00) + +/* Bit definitions and macros for MSCR_PCI */ +#define GPIO_MSCR_PCI_PCI (0x01) +#define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01) +#define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00) + +/* Bit definitions and macros for DSCR_I2C */ +#define GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) +#define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03) +#define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02) +#define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01) +#define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_FLEXBUS */ +#define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) +#define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) +#define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) +#define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40) +#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10) +#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04) +#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01) +#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_FEC */ +#define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) +#define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) +#define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C) +#define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08) +#define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04) +#define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00) +#define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03) +#define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02) +#define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01) +#define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_UART */ +#define GPIO_DSCR_UART_UART0(x) (((x)&0x03)) +#define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) +#define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C) +#define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08) +#define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04) +#define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00) +#define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03) +#define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02) +#define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01) +#define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DSPI */ +#define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) +#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03) +#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02) +#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01) +#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_TIMER */ +#define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) +#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03) +#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02) +#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01) +#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_SSI */ +#define GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) +#define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03) +#define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02) +#define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01) +#define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DMA */ +#define GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) +#define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03) +#define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02) +#define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01) +#define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DEBUG */ +#define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01) +#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_RESET */ +#define GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) +#define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03) +#define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02) +#define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01) +#define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_IRQ */ +#define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) +#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03) +#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02) +#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01) +#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_USB */ +#define GPIO_DSCR_USB_USB(x) (((x)&0x03)) +#define GPIO_DSCR_USB_USB_LOAD_50PF (0x03) +#define GPIO_DSCR_USB_USB_LOAD_30PF (0x02) +#define GPIO_DSCR_USB_USB_LOAD_20PF (0x01) +#define GPIO_DSCR_USB_USB_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_ATA */ +#define GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) +#define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03) +#define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02) +#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01) +#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00) + +/********************************************************************* +* Random Number Generator (RNG) +*********************************************************************/ + +/* Bit definitions and macros for RNGCR */ +#define RNG_RNGCR_GO (0x00000001) +#define RNG_RNGCR_HA (0x00000002) +#define RNG_RNGCR_IM (0x00000004) +#define RNG_RNGCR_CI (0x00000008) + +/* Bit definitions and macros for RNGSR */ +#define RNG_RNGSR_SV (0x00000001) +#define RNG_RNGSR_LRS (0x00000002) +#define RNG_RNGSR_FUF (0x00000004) +#define RNG_RNGSR_EI (0x00000008) +#define RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) +#define RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ + +/* Bit definitions and macros for SDMR */ +#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ +#define SDRAMC_SDMR_CMD (0x00010000) /* Command */ +#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ +#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ +#define SDRAMC_SDMR_BK_LMR (0x00000000) +#define SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for SDCR */ +#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ +#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ +#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ +#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ +#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ +#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ +#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ +#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ +#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ +#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ +#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ +#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ +#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ +#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) + +/* Bit definitions and macros for SDCFG1 */ +#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ +#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ +#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ +#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ +#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ +#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ +#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ + +/* Bit definitions and macros for SDCFG2 */ +#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ +#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ +#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ +#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ + +/* Bit definitions and macros for SDCS group */ +#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ +#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ +#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) +#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) +#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) + +/********************************************************************* +* Synchronous Serial Interface (SSI) +*********************************************************************/ + +/* Bit definitions and macros for CR */ +#define SSI_CR_SSI_EN (0x00000001) +#define SSI_CR_TE (0x00000002) +#define SSI_CR_RE (0x00000004) +#define SSI_CR_NET (0x00000008) +#define SSI_CR_SYN (0x00000010) +#define SSI_CR_I2S(x) (((x)&0x00000003)<<5) +#define SSI_CR_MCE (0x00000080) +#define SSI_CR_TCH (0x00000100) +#define SSI_CR_CIS (0x00000200) +#define SSI_CR_I2S_NORMAL (0x00000000) +#define SSI_CR_I2S_MASTER (0x00000020) +#define SSI_CR_I2S_SLAVE (0x00000040) + +/* Bit definitions and macros for ISR */ +#define SSI_ISR_TFE0 (0x00000001) +#define SSI_ISR_TFE1 (0x00000002) +#define SSI_ISR_RFF0 (0x00000004) +#define SSI_ISR_RFF1 (0x00000008) +#define SSI_ISR_RLS (0x00000010) +#define SSI_ISR_TLS (0x00000020) +#define SSI_ISR_RFS (0x00000040) +#define SSI_ISR_TFS (0x00000080) +#define SSI_ISR_TUE0 (0x00000100) +#define SSI_ISR_TUE1 (0x00000200) +#define SSI_ISR_ROE0 (0x00000400) +#define SSI_ISR_ROE1 (0x00000800) +#define SSI_ISR_TDE0 (0x00001000) +#define SSI_ISR_TDE1 (0x00002000) +#define SSI_ISR_RDR0 (0x00004000) +#define SSI_ISR_RDR1 (0x00008000) +#define SSI_ISR_RXT (0x00010000) +#define SSI_ISR_CMDDU (0x00020000) +#define SSI_ISR_CMDAU (0x00040000) + +/* Bit definitions and macros for IER */ +#define SSI_IER_TFE0 (0x00000001) +#define SSI_IER_TFE1 (0x00000002) +#define SSI_IER_RFF0 (0x00000004) +#define SSI_IER_RFF1 (0x00000008) +#define SSI_IER_RLS (0x00000010) +#define SSI_IER_TLS (0x00000020) +#define SSI_IER_RFS (0x00000040) +#define SSI_IER_TFS (0x00000080) +#define SSI_IER_TUE0 (0x00000100) +#define SSI_IER_TUE1 (0x00000200) +#define SSI_IER_ROE0 (0x00000400) +#define SSI_IER_ROE1 (0x00000800) +#define SSI_IER_TDE0 (0x00001000) +#define SSI_IER_TDE1 (0x00002000) +#define SSI_IER_RDR0 (0x00004000) +#define SSI_IER_RDR1 (0x00008000) +#define SSI_IER_RXT (0x00010000) +#define SSI_IER_CMDU (0x00020000) +#define SSI_IER_CMDAU (0x00040000) +#define SSI_IER_TIE (0x00080000) +#define SSI_IER_TDMAE (0x00100000) +#define SSI_IER_RIE (0x00200000) +#define SSI_IER_RDMAE (0x00400000) + +/* Bit definitions and macros for TCR */ +#define SSI_TCR_TEFS (0x00000001) +#define SSI_TCR_TFSL (0x00000002) +#define SSI_TCR_TFSI (0x00000004) +#define SSI_TCR_TSCKP (0x00000008) +#define SSI_TCR_TSHFD (0x00000010) +#define SSI_TCR_TXDIR (0x00000020) +#define SSI_TCR_TFDIR (0x00000040) +#define SSI_TCR_TFEN0 (0x00000080) +#define SSI_TCR_TFEN1 (0x00000100) +#define SSI_TCR_TXBIT0 (0x00000200) + +/* Bit definitions and macros for RCR */ +#define SSI_RCR_REFS (0x00000001) +#define SSI_RCR_RFSL (0x00000002) +#define SSI_RCR_RFSI (0x00000004) +#define SSI_RCR_RSCKP (0x00000008) +#define SSI_RCR_RSHFD (0x00000010) +#define SSI_RCR_RFEN0 (0x00000080) +#define SSI_RCR_RFEN1 (0x00000100) +#define SSI_RCR_RXBIT0 (0x00000200) +#define SSI_RCR_RXEXT (0x00000400) + +/* Bit definitions and macros for CCR */ +#define SSI_CCR_PM(x) (((x)&0x000000FF)) +#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8) +#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13) +#define SSI_CCR_PSR (0x00020000) +#define SSI_CCR_DIV2 (0x00040000) + +/* Bit definitions and macros for FCSR */ +#define SSI_FCSR_TFWM0(x) (((x)&0x0000000F)) +#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) +#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) +#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) +#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) +#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) +#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) +#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for ACR */ +#define SSI_ACR_AC97EN (0x00000001) +#define SSI_ACR_FV (0x00000002) +#define SSI_ACR_TIF (0x00000004) +#define SSI_ACR_RD (0x00000008) +#define SSI_ACR_WR (0x00000010) +#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) + +/* Bit definitions and macros for ACADD */ +#define SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF)) + +/* Bit definitions and macros for ACDAT */ +#define SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF)) + +/* Bit definitions and macros for ATAG */ +#define SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF)) + +/********************************************************************* +* Phase Locked Loop (PLL) +*********************************************************************/ + +/* Bit definitions and macros for PCR */ +#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ +#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */ +#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */ +#define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */ +#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ +#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ +#define PLL_PCR_PFDR_MASK (0x000F0000) +#define PLL_PCR_OUTDIV5_MASK (0x000F0000) +#define PLL_PCR_OUTDIV4_MASK (0x0000F000) +#define PLL_PCR_OUTDIV3_MASK (0x00000F00) +#define PLL_PCR_OUTDIV2_MASK (0x000000F0) +#define PLL_PCR_OUTDIV1_MASK (0x0000000F) + +/* Bit definitions and macros for PSR */ +#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ +#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ +#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ +#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ + +/********************************************************************* +* PCI +*********************************************************************/ + +/* Bit definitions and macros for SCR */ +#define PCI_SCR_PE (0x80000000) /* Parity Error detected */ +#define PCI_SCR_SE (0x40000000) /* System error signalled */ +#define PCI_SCR_MA (0x20000000) /* Master aboart received */ +#define PCI_SCR_TR (0x10000000) /* Target abort received */ +#define PCI_SCR_TS (0x08000000) /* Target abort signalled */ +#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */ +#define PCI_SCR_DP (0x01000000) /* Master data parity err */ +#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */ +#define PCI_SCR_R (0x00400000) /* Reserved */ +#define PCI_SCR_66M (0x00200000) /* 66Mhz */ +#define PCI_SCR_C (0x00100000) /* Capabilities list */ +#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */ +#define PCI_SCR_S (0x00000100) /* SERR enable */ +#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */ +#define PCI_SCR_PER (0x00000040) /* Parity error response */ +#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */ +#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */ +#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */ +#define PCI_SCR_B (0x00000004) /* Bus master enable */ +#define PCI_SCR_M (0x00000002) /* Memory access control */ +#define PCI_SCR_IO (0x00000001) /* I/O access control */ + +#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */ +#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */ +#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */ +#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */ + +#define PCI_BAR_BAR0(x) (x & 0xFFFC0000) +#define PCI_BAR_BAR1(x) (x & 0xFFF00000) +#define PCI_BAR_BAR2(x) (x & 0xFFC00000) +#define PCI_BAR_BAR3(x) (x & 0xFF000000) +#define PCI_BAR_BAR4(x) (x & 0xF8000000) +#define PCI_BAR_BAR5(x) (x & 0xE0000000) +#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */ +#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */ +#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */ + +#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */ +#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */ +#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */ +#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */ + +#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */ +#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */ +#define PCI_GSCR_SE (0x10000000) /* SERR detected */ +#define PCI_GSCR_ER (0x08000000) /* Error response detected */ +#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */ +#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */ +#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */ +#define PCI_GSCR_PR (0x00000001) /* PCI reset */ + +#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */ +#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */ +#define PCI_TCR1_P (0x00010000) /* Prefetch reads */ +#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */ + +#define PCI_TCR1_B5E (0x00002000) /* */ +#define PCI_TCR1_B4E (0x00001000) /* */ +#define PCI_TCR1_B3E (0x00000800) /* */ +#define PCI_TCR1_B2E (0x00000400) /* */ +#define PCI_TCR1_B1E (0x00000200) /* */ +#define PCI_TCR1_B0E (0x00000100) /* */ +#define PCI_TCR1_CR (0x00000001) /* */ + +#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20) +#define PCI_TBATR_EN (0x00000001) /* Enable */ + +#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */ +#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */ +#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */ +#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */ +#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */ +#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */ +#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */ +#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */ +#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */ +#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */ +#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */ +#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */ +#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */ +#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */ +#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */ + +#define PCI_ICR_REE (0x04000000) /* Retry error enable */ +#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */ +#define PCI_ICR_TAE (0x01000000) /* Target abort enable */ + +#define PCI_IDR_DEVID ( + +/********************************************************************/ + +#endif /* __MCF5445X__ */ diff --git a/include/asm-m68k/rtc.h b/include/asm-m68k/rtc.h index f955bc5fe14..7651ca93258 100644 --- a/include/asm-m68k/rtc.h +++ b/include/asm-m68k/rtc.h @@ -35,9 +35,10 @@ typedef struct rtc_ctrl { u32 cr; /* 0x10 Control Register */ u32 isr; /* 0x14 Interrupt Status Register */ u32 ier; /* 0x18 Interrupt Enable Register */ - u32 stpwach; /* 0x1C Stopwatch Minutes Register */ + u32 stpwatch; /* 0x1C Stopwatch Minutes Register */ u32 days; /* 0x20 Days Counter Register */ u32 alrm_day; /* 0x24 Days Alarm Register */ + void *extended; } rtc_t; /* Bit definitions and macros for HOURMIN */ diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h index 70dbda464c0..93a6959ff14 100644 --- a/include/asm-m68k/u-boot.h +++ b/include/asm-m68k/u-boot.h @@ -52,6 +52,14 @@ typedef struct bd_info { unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ +#ifdef CONFIG_PCI + unsigned long bi_pcifreq; /* pci Freq in MHz */ +#endif +#ifdef CONFIG_EXTRA_CLOCK + unsigned long bi_inpfreq; /* input Freq in MHz */ + unsigned long bi_vcofreq; /* vco Freq in MHz */ + unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ +#endif unsigned long bi_baudrate; /* Console Baudrate */ #ifdef CONFIG_HAS_ETH1 diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h new file mode 100644 index 00000000000..6f4859c2380 --- /dev/null +++ b/include/configs/M54455EVB.h @@ -0,0 +1,391 @@ +/* + * Configuation settings for the Freescale MCF54455 EVB board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _JAMICA54455_H +#define _JAMICA54455_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF5445x /* define processor family */ +#define CONFIG_M54455 /* define processor type */ +#define CONFIG_M54455EVB /* M54455EVB board */ + +#undef DEBUG + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Command line configuration */ +#include + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +/* Network configuration */ +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CONFIG_CF_DOMII +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC1_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +# define CONFIG_HAS_ETH1 + +# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 +# define CONFIG_ETHPRIME "FEC0" +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE + +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#define CONFIG_HOSTNAME M54455EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 2ffff;" \ + "era 0 2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +/* ATA configuration */ +#define CONFIG_ISO_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_IDE_RESET 1 +#define CONFIG_IDE_PREINIT 1 +#define CONFIG_ATAPI +#undef CONFIG_LBA48 + +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 2 + +#define CFG_ATA_BASE_ADDR 0x90000000 +#define CFG_ATA_IDE0_OFFSET 0 + +#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 4 /* Interval between registers */ +#define _IO_BASE 0 + +/* Realtime clock */ +#define CONFIG_MCFRTC +#undef RTC_DEBUG +#define CFG_RTC_OSCILLATOR (32 * CFG_HZ) + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2c */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x58000 +#define CFG_IMMR CFG_MBAR + +/* PCI */ +#define CONFIG_PCI 1 + +#define CFG_PCI_MEM_BUS 0xA0000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS +#define CFG_PCI_MEM_SIZE 0x10000000 + +#define CFG_PCI_IO_BUS 0xB1000000 +#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS +#define CFG_PCI_IO_SIZE 0x01000000 + +#define CFG_PCI_CFG_BUS 0xB0000000 +#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS +#define CFG_PCI_CFG_SIZE 0x01000000 + +/* FPGA - Spartan 2 */ +/* experiment +#define CONFIG_FPGA CFG_SPARTAN3 +#define CONFIG_FPGA_COUNT 1 +#define CFG_FPGA_PROG_FEEDBACK +#define CFG_FPGA_CHECK_CTRLC +*/ + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 512 /* 512 KB */ + +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) + +#define CFG_HZ 1000 + +#define CFG_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x80000000 +#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x221 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x40000000 +#define CFG_SDRAM_BASE1 0x48000000 +#define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */ +#define CFG_SDRAM_CFG1 0x65311610 +#define CFG_SDRAM_CFG2 0x59670000 +#define CFG_SDRAM_CTRL 0xEA0B2000 +#define CFG_SDRAM_EMOD 0x40010000 +#define CFG_SDRAM_MODE 0x00010033 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OVERWRITE 1 +#undef CFG_ENV_IS_EMBEDDED + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CFG_ATMEL_BOOT +# define CFG_FLASH_BASE 0 +# define CFG_FLASH0_BASE CFG_CS0_BASE +# define CFG_FLASH1_BASE CFG_CS1_BASE +#else +# define CFG_FLASH_BASE CFG_FLASH0_BASE +# define CFG_FLASH0_BASE CFG_CS1_BASE +# define CFG_FLASH1_BASE CFG_CS0_BASE +#endif + +/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system +/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system + keep reset. */ +#undef CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI + +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM +# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE } + +#else + +# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ + +# define CFG_ATMEL_REGION 4 +# define CFG_ATMEL_TOTALSECT 11 +# define CFG_ATMEL_SECT {1, 2, 1, 7} +# define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} +# define CFG_INTEL_SECT 137 + +/* max number of sectors on one chip */ +# define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT) +# define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */ +# define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +# define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +# define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM + +#endif + +/* + * This is setting for JFFS2 support in u-boot. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + */ +#ifdef CFG_ATMEL_BOOT +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE 0x01000000 +# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE +#else +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) +# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - CPLD + * CS3 - FPGA + * CS4 - Available + * CS5 - Available + */ + +#ifdef CFG_ATMEL_BOOT + /* Atmel Flash */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x00070001 +#define CFG_CS0_CTRL 0x00001140 +/* Intel Flash */ +#define CFG_CS1_BASE 0x04000000 +#define CFG_CS1_MASK 0x01FF0001 +#define CFG_CS1_CTRL 0x003F3D60 + +#define CFG_ATMEL_BASE CFG_CS0_BASE +#else +/* Intel Flash */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x01FF0001 +#define CFG_CS0_CTRL 0x003F3D60 + /* Atmel Flash */ +#define CFG_CS1_BASE 0x04000000 +#define CFG_CS1_MASK 0x00070001 +#define CFG_CS1_CTRL 0x00001140 + +#define CFG_ATMEL_BASE CFG_CS1_BASE +#endif + +/* CPLD */ +#define CFG_CS2_BASE 0x08000000 +#define CFG_CS2_MASK 0x00070001 +#define CFG_CS2_CTRL 0x003f1140 + +/* FPGA */ +#define CFG_CS3_BASE 0x09000000 +#define CFG_CS3_MASK 0x00070001 +#define CFG_CS3_CTRL 0x00000020 + +#endif /* _JAMICA54455_H */ diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 778ec788a81..43f97c404da 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -30,9 +30,7 @@ #include #include -#ifdef CONFIG_M5272 -#include -#endif +#include #if defined(CONFIG_CMD_IDE) #include @@ -139,19 +137,19 @@ void *sbrk (ptrdiff_t increment) char *strmhz(char *buf, long hz) { - long l, n; - long m; + long l, n; + long m; - n = hz / 1000000L; + n = hz / 1000000L; - l = sprintf (buf, "%ld", n); + l = sprintf (buf, "%ld", n); - m = (hz % 1000000L) / 1000L; + m = (hz % 1000000L) / 1000L; - if (m != 0) - sprintf (buf+l, ".%03ld", m); + if (m != 0) + sprintf (buf+l, ".%03ld", m); - return (buf); + return (buf); } /* @@ -169,7 +167,7 @@ char *strmhz(char *buf, long hz) typedef int (init_fnc_t) (void); /************************************************************************ - * Init Utilities * + * Init Utilities ************************************************************************ * Some of this code should be moved into the core functions, * but let's get it working (again) first... @@ -383,6 +381,14 @@ board_init_f (ulong bootflag) WATCHDOG_RESET (); bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ +#ifdef CONFIG_PCI + bd->bi_pcifreq = gd->pci_clk; /* PCI Freq in Hz */ +#endif +#ifdef CONFIG_EXTRA_CLOCK + bd->bi_inpfreq = gd->inp_clk; /* input Freq in Hz */ + bd->bi_vcofreq = gd->vco_clk; /* vco Freq in Hz */ + bd->bi_flbfreq = gd->flb_clk; /* flexbus Freq in Hz */ +#endif bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ #ifdef CFG_EXTBDINFO diff --git a/lib_m68k/interrupts.c b/lib_m68k/interrupts.c old mode 100755 new mode 100644 diff --git a/lib_m68k/m68k_linux.c b/lib_m68k/m68k_linux.c index 6c194f80aa7..fde1744e45c 100644 --- a/lib_m68k/m68k_linux.c +++ b/lib_m68k/m68k_linux.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -34,103 +36,189 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -extern image_header_t header; /* from cmd_bootm.c */ - -extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); - -static int linux_argc; -static char **linux_argv; - -static char **linux_env; -static char *linux_env_p; -static int linux_env_idx; +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif -static void linux_params_init (ulong start, char *commandline); -static void linux_env_set (char *env_name, char *env_val); +extern image_header_t header; -void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], - ulong addr, ulong * len_ptr, int verify) +void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, + int argc, char *argv[], + ulong addr, ulong * len_ptr, int verify) { - ulong len = 0, checksum; + ulong sp; + ulong len, checksum; ulong initrd_start, initrd_end; + ulong cmd_start, cmd_end; + ulong initrd_high; ulong data; - void (*theKernel) (int, char **, char **, int *); + int initrd_copy_to_ram = 1; + char *cmdline; + char *s; + bd_t *kbd; + void (*kernel) (bd_t *, ulong, ulong, ulong, ulong); image_header_t *hdr = &header; - char *commandline = getenv ("bootargs"); - char env_buf[12]; - theKernel = - (void (*)(int, char **, char **, int *)) ntohl (hdr->ih_ep); + if ((s = getenv("initrd_high")) != NULL) { + /* a value of "no" or a similar string will act like 0, + * turning the "load high" feature off. This is intentional. + */ + initrd_high = simple_strtoul(s, NULL, 16); + if (initrd_high == ~0) + initrd_copy_to_ram = 0; + } else { /* not set, no restrictions to load high */ + initrd_high = ~0; + } + +#ifdef CONFIG_LOGBUFFER + kbd = gd->bd; + /* Prevent initrd from overwriting logbuffer */ + if (initrd_high < (kbd->bi_memsize - LOGBUFF_LEN - LOGBUFF_OVERHEAD)) + initrd_high = kbd->bi_memsize - LOGBUFF_LEN - LOGBUFF_OVERHEAD; + debug("## Logbuffer at 0x%08lX ", kbd->bi_memsize - LOGBUFF_LEN); +#endif + + /* + * Booting a (Linux) kernel image + * + * Allocate space for command line and board info - the + * address should be as high as possible within the reach of + * the kernel (see CFG_BOOTMAPSZ settings), but in unused + * memory, which means far enough below the current stack + * pointer. + */ + asm("movel %%a7, %%d0\n" + "movel %%d0, %0\n": "=d"(sp): :"%d0"); + debug("## Current stack ends at 0x%08lX ", sp); + + sp -= 2048; /* just to be sure */ + if (sp > CFG_BOOTMAPSZ) + sp = CFG_BOOTMAPSZ; + sp &= ~0xF; + + debug("=> set upper limit to 0x%08lX\n", sp); + + cmdline = (char *)((sp - CFG_BARGSIZE) & ~0xF); + kbd = (bd_t *) (((ulong) cmdline - sizeof(bd_t)) & ~0xF); + + if ((s = getenv("bootargs")) == NULL) + s = ""; + + strcpy(cmdline, s); + + cmd_start = (ulong) & cmdline[0]; + cmd_end = cmd_start + strlen(cmdline); + + *kbd = *(gd->bd); + +#ifdef DEBUG + printf("## cmdline at 0x%08lX ... 0x%08lX\n", cmd_start, cmd_end); + + do_bdinfo(NULL, 0, 0, NULL); +#endif + + if ((s = getenv("clocks_in_mhz")) != NULL) { + /* convert all clock information to MHz */ + kbd->bi_intfreq /= 1000000L; + kbd->bi_busfreq /= 1000000L; + } + + kernel = + (void (*)(bd_t *, ulong, ulong, ulong, ulong))ntohl(hdr->ih_ep); /* * Check if there is an initrd image */ + if (argc >= 3) { - show_boot_progress (9); + debug("Not skipping initrd\n"); + SHOW_BOOT_PROGRESS(9); - addr = simple_strtoul (argv[2], NULL, 16); + addr = simple_strtoul(argv[2], NULL, 16); - printf ("## Loading Ramdisk Image at %08lx ...\n", addr); + printf("## Loading RAMDisk Image at %08lx ...\n", addr); /* Copy header so we can blank CRC field for re-calculation */ - memcpy (&header, (char *) addr, sizeof (image_header_t)); + memmove(&header, (char *)addr, sizeof(image_header_t)); - if (ntohl (hdr->ih_magic) != IH_MAGIC) { - printf ("Bad Magic Number\n"); - show_boot_progress (-10); - do_reset (cmdtp, flag, argc, argv); + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + puts("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS(-10); + do_reset(cmdtp, flag, argc, argv); } data = (ulong) & header; - len = sizeof (image_header_t); + len = sizeof(image_header_t); - checksum = ntohl (hdr->ih_hcrc); + checksum = ntohl(hdr->ih_hcrc); hdr->ih_hcrc = 0; - if (crc32 (0, (char *) data, len) != checksum) { - printf ("Bad Header Checksum\n"); - show_boot_progress (-11); - do_reset (cmdtp, flag, argc, argv); + if (crc32(0, (uchar *) data, len) != checksum) { + puts("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS(-11); + do_reset(cmdtp, flag, argc, argv); } - show_boot_progress (10); + SHOW_BOOT_PROGRESS(10); - print_image_hdr (hdr); + print_image_hdr(hdr); - data = addr + sizeof (image_header_t); - len = ntohl (hdr->ih_size); + data = addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); if (verify) { ulong csum = 0; +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + ulong cdata = data, edata = cdata + len; +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ - printf (" Verifying Checksum ... "); - csum = crc32 (0, (char *) data, len); - if (csum != ntohl (hdr->ih_dcrc)) { - printf ("Bad Data CRC\n"); - show_boot_progress (-12); - do_reset (cmdtp, flag, argc, argv); + puts(" Verifying Checksum ... "); + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + + while (cdata < edata) { + ulong chunk = edata - cdata; + + if (chunk > CHUNKSZ) + chunk = CHUNKSZ; + csum = crc32(csum, (uchar *) cdata, chunk); + cdata += chunk; + + WATCHDOG_RESET(); } - printf ("OK\n"); +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + csum = crc32(0, (uchar *) data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + + if (csum != ntohl(hdr->ih_dcrc)) { + puts("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS(-12); + do_reset(cmdtp, flag, argc, argv); + } + puts("OK\n"); } - show_boot_progress (11); + SHOW_BOOT_PROGRESS(11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_M68K) || (hdr->ih_type != IH_TYPE_RAMDISK)) { - printf ("No Linux M68K Ramdisk Image\n"); - show_boot_progress (-13); - do_reset (cmdtp, flag, argc, argv); + puts("No Linux ColdFire Ramdisk Image\n"); + SHOW_BOOT_PROGRESS(-13); + do_reset(cmdtp, flag, argc, argv); } /* * Now check if we have a multifile image */ } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { - ulong tail = ntohl (len_ptr[0]) % 4; + u_long tail = ntohl(len_ptr[0]) % 4; int i; - show_boot_progress (13); + SHOW_BOOT_PROGRESS(13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -138,130 +226,110 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], for (i = 1; len_ptr[i]; ++i) data += 4; /* add kernel length, and align */ - data += ntohl (len_ptr[0]); + data += ntohl(len_ptr[0]); if (tail) { data += 4 - tail; } - len = ntohl (len_ptr[1]); + len = ntohl(len_ptr[1]); } else { /* * no initrd image */ - show_boot_progress (14); + SHOW_BOOT_PROGRESS(14); - data = 0; + len = data = 0; } -#ifdef DEBUG if (!data) { - printf ("No initrd\n"); + debug("No initrd\n"); } -#endif if (data) { - initrd_start = data; - initrd_end = initrd_start + len; - } else { - initrd_start = 0; - initrd_end = 0; - } - - show_boot_progress (15); - -#ifdef DEBUG - printf ("## Transferring control to Linux (at address %08lx) ...\n", - (ulong) theKernel); -#endif - - linux_params_init (PHYSADDR (gd->bd->bi_boot_params), commandline); - - sprintf (env_buf, "%lu", gd->ram_size >> 20); - linux_env_set ("memsize", env_buf); - - sprintf (env_buf, "0x%08X", (uint) PHYSADDR (initrd_start)); - linux_env_set ("initrd_start", env_buf); - - sprintf (env_buf, "0x%X", (uint) (initrd_end - initrd_start)); - linux_env_set ("initrd_size", env_buf); - - sprintf (env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart)); - linux_env_set ("flash_start", env_buf); - - sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); - linux_env_set ("flash_size", env_buf); - - /* we assume that the kernel is in place */ - printf ("\nStarting kernel ...\n\n"); - - theKernel (linux_argc, linux_argv, linux_env, 0); -} - -static void linux_params_init (ulong start, char *line) -{ - char *next, *quote, *argp; - - linux_argc = 1; - linux_argv = (char **) start; - linux_argv[0] = 0; - argp = (char *) (linux_argv + LINUX_MAX_ARGS); - - next = line; - - while (line && *line && linux_argc < LINUX_MAX_ARGS) { - quote = strchr (line, '"'); - next = strchr (line, ' '); - - while (next != NULL && quote != NULL && quote < next) { - /* we found a left quote before the next blank - * now we have to find the matching right quote - */ - next = strchr (quote + 1, '"'); - if (next != NULL) { - quote = strchr (next + 1, '"'); - next = strchr (next + 1, ' '); + if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ + initrd_start = data; + initrd_end = initrd_start + len; + } else { + initrd_start = (ulong) kbd - len; + initrd_start &= ~(4096 - 1); /* align on page */ + + if (initrd_high) { + ulong nsp; + + /* + * the inital ramdisk does not need to be within + * CFG_BOOTMAPSZ as it is not accessed until after + * the mm system is initialised. + * + * do the stack bottom calculation again and see if + * the initrd will fit just below the monitor stack + * bottom without overwriting the area allocated + * above for command line args and board info. + */ + asm("movel %%a7, %%d0\n" + "movel %%d0, %0\n": "=d"(nsp): :"%d0"); + nsp -= 2048; /* just to be sure */ + nsp &= ~0xF; + + if (nsp > initrd_high) /* limit as specified */ + nsp = initrd_high; + + nsp -= len; + nsp &= ~(4096 - 1); /* align on page */ + + if (nsp >= sp) + initrd_start = nsp; } - } - if (next == NULL) { - next = line + strlen (line); + SHOW_BOOT_PROGRESS(12); + + debug + ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", + data, data + len - 1, len, len); + + initrd_end = initrd_start + len; + printf(" Loading Ramdisk to %08lx, end %08lx ... ", + initrd_start, initrd_end); +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + { + size_t l = len; + void *to = (void *)initrd_start; + void *from = (void *)data; + + while (l > 0) { + size_t tail = + (l > CHUNKSZ) ? CHUNKSZ : l; + WATCHDOG_RESET(); + memmove(to, from, tail); + to += tail; + from += tail; + l -= tail; + } + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + memmove((void *)initrd_start, (void *)data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + puts("OK\n"); } - - linux_argv[linux_argc] = argp; - memcpy (argp, line, next - line); - argp[next - line] = 0; - - argp += next - line + 1; - linux_argc++; - - if (*next) - next++; - - line = next; + } else { + initrd_start = 0; + initrd_end = 0; } - linux_env = (char **) (((ulong) argp + 15) & ~15); - linux_env[0] = 0; - linux_env_p = (char *) (linux_env + LINUX_MAX_ENVS); - linux_env_idx = 0; -} - -static void linux_env_set (char *env_name, char *env_val) -{ - if (linux_env_idx < LINUX_MAX_ENVS - 1) { - linux_env[linux_env_idx] = linux_env_p; - - strcpy (linux_env_p, env_name); - linux_env_p += strlen (env_name); + debug("## Transferring control to Linux (at address %08lx) ...\n", + (ulong) kernel); - strcpy (linux_env_p, "="); - linux_env_p += 1; + SHOW_BOOT_PROGRESS(15); - strcpy (linux_env_p, env_val); - linux_env_p += strlen (env_val); - - linux_env_p++; - linux_env[++linux_env_idx] = 0; - } + /* + * Linux Kernel Parameters (passing board info data): + * r3: ptr to board info data + * r4: initrd_start or 0 if no initrd + * r5: initrd_end - unused if r4 is 0 + * r6: Start of command line string + * r7: End of command line string + */ + (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); + /* does not return */ } -- cgit v1.3.1 From 815b5bd5b18569917c3e04b9757511e6ed23b9f6 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Fri, 17 Aug 2007 12:43:44 +0900 Subject: PCI_READ_VIA_DWORD_OP: Fix *val uninitialized bug This patch has been sent on: - 6 Jun 2007 Many users of PCI config read routines tend to ignore the function ret value, and are only concerned about the contents of *val. Based on this, pci_hose_read_config_{byte,word}_via_dword should initialize the *val on dword read error. Without this fix, for example, we'll go on scanning bus with vendor or header_type uninitialized. This brings many unnecessary config trials. Signed-off-by: Shinya Kuribayashi --- drivers/pci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci.c b/drivers/pci.c index 41589192c1c..50ca6b0bad6 100644 --- a/drivers/pci.c +++ b/drivers/pci.c @@ -82,8 +82,10 @@ int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ { \ u32 val32; \ \ - if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ + if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ + *val = -1; \ return -1; \ + } \ \ *val = (val32 >> ((offset & (int)off_mask) * 8)); \ \ -- cgit v1.3.1 From 3e66c078003607a7d1d214c15a5f262bc1b4032f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 19 Aug 2007 10:27:34 +0200 Subject: Fix some build errors. Signed-off-by: Wolfgang Denk --- drivers/net/mcffec.c | 4 ++-- drivers/serial/mcfuart.c | 4 +++- rtc/mcfrtc.c | 6 +++--- 3 files changed, 8 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 2e0ddeb7772..3b812585b76 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -27,15 +27,15 @@ #include #include +#ifdef CONFIG_MCFFEC + #include #include #include -#include #include #include -#ifdef CONFIG_MCFFEC #undef ET_DEBUG #undef MII_DEBUG diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index bc7077de79e..88f3eb10abf 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -28,12 +28,14 @@ */ #include + +#ifdef CONFIG_MCFUART + #include #include DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_MCFUART extern void uart_port_conf(void); int serial_init(void) diff --git a/rtc/mcfrtc.c b/rtc/mcfrtc.c index 76bb5107f6a..27386e586a6 100644 --- a/rtc/mcfrtc.c +++ b/rtc/mcfrtc.c @@ -22,14 +22,14 @@ */ #include + +#if defined(CONFIG_MCFRTC) && defined(CONFIG_CMD_DATE) + #include #include - #include #include -#if defined(CONFIG_MCFRTC) && defined(CONFIG_CMD_DATE) - #undef RTC_DEBUG #ifndef CFG_MCFRTC_BASE -- cgit v1.3.1 From 16e23c3f5dab6937f5109365416808c7f15c122b Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Mon, 20 Aug 2007 23:55:33 -0500 Subject: fsl_pci_init - Remove self PCSRBAR allocation CPU physical address space was being wasted by allocating a PCSRBAR PCI inbound region to it's memory space. As a rule, PCSRBAR should be left alone since it does not affect transactions from self and other masters may have changed it. Signed-off-by: Ed Swarthout --- drivers/fsl_pci_init.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 1084dc6b787..3a13eea1f2b 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -130,9 +130,14 @@ fsl_pci_init(struct pci_controller *hose) } - /* Call setup to allocate PCSRBAR window */ - pciauto_setup_device(hose, dev, 1, hose->pci_mem, + /* Use generic setup_device to initialize standard pci regs, + * but do not allocate any windows since any BAR found (such + * as PCSRBAR) is not in this cpu's memory space. + */ + + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + #ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); -- cgit v1.3.1 From 4a8527ef086ec7c89f40674ef024ae6f988a614a Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Tue, 21 Aug 2007 12:40:34 +0200 Subject: MPC5xxx: fix some compiler warnings in USB code Fix the following warnings: - usb.c:xx: warning: function declaration isn't a prototype - usb_ohci.c:xxx: warning: passing argument 1 of '__fswab32' makes integer from pointer wihtout a cast Signed-off-by: Martin Krause --- cpu/mpc5xxx/usb.c | 6 +++--- drivers/usb_ohci.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/cpu/mpc5xxx/usb.c b/cpu/mpc5xxx/usb.c index ce709fc652c..ed467ab3b88 100644 --- a/cpu/mpc5xxx/usb.c +++ b/cpu/mpc5xxx/usb.c @@ -27,7 +27,7 @@ #include -int usb_cpu_init() +int usb_cpu_init(void) { /* Set the USB Clock */ *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK; @@ -41,12 +41,12 @@ int usb_cpu_init() return 0; } -int usb_cpu_stop() +int usb_cpu_stop(void) { return 0; } -int usb_cpu_init_fail() +int usb_cpu_init_fail(void) { return 0; } diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index f0a37b20a71..14984a5f39c 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -669,7 +669,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi) ed_p = &(((ed_t *)ed_p)->hwNextED)) inter = ep_rev (6, ((ed_t *)ed_p)->int_interval); ed->hwNextED = *ed_p; - *ed_p = m32_swap(ed); + *ed_p = m32_swap((unsigned long)ed); } break; } @@ -687,11 +687,11 @@ static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed, /* ED might have been unlinked through another path */ while (*ed_p != 0) { - if (((struct ed *)m32_swap (ed_p)) == ed) { + if (((struct ed *)m32_swap ((unsigned long)ed_p)) == ed) { *ed_p = ed->hwNextED; break; } - ed_p = & (((struct ed *)m32_swap (ed_p))->hwNextED); + ed_p = & (((struct ed *)m32_swap ((unsigned long)ed_p))->hwNextED); } } } -- cgit v1.3.1 From 5f470948570526e9186f053a3003da7719604e90 Mon Sep 17 00:00:00 2001 From: stefano babic Date: Tue, 21 Aug 2007 15:50:33 +0200 Subject: Fix MAC address setting in DM9000 driver. The logic to check if there is a correct MAC address in the DM9000 EEPROM, added in the last patch, is wrong. Now the MAC address is always taken from the environment, even if a suitable MAC is present in the EEPROM. Signed-off-by: Stefano Babic --- drivers/dm9000x.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c index 78acb097ef8..e0d531bd917 100644 --- a/drivers/dm9000x.c +++ b/drivers/dm9000x.c @@ -303,8 +303,8 @@ eth_init(bd_t * bd) for (i = 0; i < 6; i++) ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); - if (!is_zero_ether_addr(bd->bi_enetaddr) && - !is_mutlicast_ether_addr(bd->bi_enetaddr)) { + if (is_zero_ether_addr(bd->bi_enetaddr) || + is_multicast_ether_addr(bd->bi_enetaddr)) { /* try reading from environment */ u8 i; char *s, *e; @@ -542,7 +542,7 @@ read_srom_word(int offset) { DM9000_iow(DM9000_EPAR, offset); DM9000_iow(DM9000_EPCR, 0x4); - udelay(200); + udelay(8000); DM9000_iow(DM9000_EPCR, 0x0); return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); } -- cgit v1.3.1 From 9468e6804b7e25b0f6f52e53f47bce3175400a16 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 20 Aug 2007 09:44:00 -0500 Subject: Fix MPC8544DS PCIe3 scsi. The problem is pciauto_setup_device() getting called from fsl_pci_init.c is allocating memory space it doesn't need. Signed-off-by: Ed Swarthout Signed-off-by: Andy Fleming --- drivers/fsl_pci_init.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 3a13eea1f2b..a4ce458a5ab 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -54,6 +54,7 @@ fsl_pci_init(struct pci_controller *hose) u8 temp8; int r; int bridge; + unsigned long bus_lower_temp; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; pci_dev_t dev = PCI_BDF(busno,0,0); @@ -134,9 +135,10 @@ fsl_pci_init(struct pci_controller *hose) * but do not allocate any windows since any BAR found (such * as PCSRBAR) is not in this cpu's memory space. */ - + bus_lower_temp = hose->pci_mem->bus_lower; pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + hose->pci_mem->bus_lower = bus_lower_temp; #ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); -- cgit v1.3.1 From 1900fbf255acba8b94fb442a16408ea85a1d46a6 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Thu, 30 Aug 2007 02:26:17 -0500 Subject: Revert "Fix MPC8544DS PCIe3 scsi." This reverts commit 9468e680. Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient. Signed-off-by: Ed Swarthout --- drivers/fsl_pci_init.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index a4ce458a5ab..3a13eea1f2b 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -54,7 +54,6 @@ fsl_pci_init(struct pci_controller *hose) u8 temp8; int r; int bridge; - unsigned long bus_lower_temp; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; pci_dev_t dev = PCI_BDF(busno,0,0); @@ -135,10 +134,9 @@ fsl_pci_init(struct pci_controller *hose) * but do not allocate any windows since any BAR found (such * as PCSRBAR) is not in this cpu's memory space. */ - bus_lower_temp = hose->pci_mem->bus_lower; + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); - hose->pci_mem->bus_lower = bus_lower_temp; #ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); -- cgit v1.3.1 From 81b73dec16fd1227369a191e725e10044a9d56b8 Mon Sep 17 00:00:00 2001 From: Gary Jennejohn Date: Fri, 31 Aug 2007 15:21:46 +0200 Subject: ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese . o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese . o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn Signed-off-by: Stefan Roese --- board/amcc/sequoia/init.S | 3 +++ drivers/pci_auto.c | 8 +++++++- include/configs/sequoia.h | 3 ++- 3 files changed, 12 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 45bcd4bef75..5fe3af9a092 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -126,6 +126,9 @@ tlbtab: /* TLB-entry for peripherals */ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + /* TLB-entry PCI IO Space - from sr@denx.de */ + tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbtab_end #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 2378553be5a..acfda83ba50 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -28,6 +28,11 @@ #define PCIAUTO_IDE_MODE_MASK 0x05 +/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */ +#ifndef CFG_PCI_CACHE_LINE_SIZE +#define CFG_PCI_CACHE_LINE_SIZE 8 +#endif + /* * */ @@ -150,7 +155,8 @@ void pciauto_setup_device(struct pci_controller *hose, } pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, + CFG_PCI_CACHE_LINE_SIZE); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); } diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 824a81240cd..c2e1386217f 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -400,7 +400,8 @@ *----------------------------------------------------------------------*/ /* General PCI */ #define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ -- cgit v1.3.1 From 041a2554ad619e80dce520c1a33210affcb6a3f2 Mon Sep 17 00:00:00 2001 From: Gary Jennejohn Date: Fri, 31 Aug 2007 14:29:04 +0200 Subject: Add support for Sil680 IDE controller. o add drivers/sil680.c to support the Sil680 IDE-controller. o drivers/Makefile: add sil680.o. Signed-off-by: Gary Jennejohn --- drivers/Makefile | 2 +- drivers/sil680.c | 110 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 drivers/sil680.c (limited to 'drivers') diff --git a/drivers/Makefile b/drivers/Makefile index 3ee6312e9db..6bf05ccad19 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -43,7 +43,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \ sed13806.o sed156x.o \ serial.o serial_max3100.o \ serial_pl010.o serial_pl011.o serial_xuartlite.o \ - sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ + sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ status_led.o sym53c8xx.o systemace.o ahci.o \ ti_pci1410a.o tigon3.o tsec.o \ tsi108_eth.o tsi108_i2c.o tsi108_pci.o \ diff --git a/drivers/sil680.c b/drivers/sil680.c new file mode 100644 index 00000000000..a6143df4c06 --- /dev/null +++ b/drivers/sil680.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2007 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* sil680.c - ide support functions for the Sil0680A controller */ + +/* + * The following parameters must be defined in the configuration file + * of the target board: + * + * #define CFG_IDE_SIL680 + * + * #define CONFIG_PCI_PNP + * NOTE it may also be necessary to define this if the default of 8 is + * incorrect for the target board (e.g. the sequoia board requires 0). + * #define CFG_PCI_CACHE_LINE_SIZE 0 + * + * #define CONFIG_CMD_IDE + * #undef CONFIG_IDE_8xx_DIRECT + * #undef CONFIG_IDE_LED + * #undef CONFIG_IDE_RESET + * #define CONFIG_IDE_PREINIT + * #define CFG_IDE_MAXBUS 2 - modify to suit + * #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) - modify to suit + * #define CFG_ATA_BASE_ADDR 0 + * #define CFG_ATA_IDE0_OFFSET 0 + * #define CFG_ATA_IDE1_OFFSET 0 + * #define CFG_ATA_DATA_OFFSET 0 + * #define CFG_ATA_REG_OFFSET 0 + * #define CFG_ATA_ALT_OFFSET 0x0004 + * + * The mapping for PCI IO-space. + * NOTE this is the value for the sequoia board. Modify to suit. + * #define CFG_PCI0_IO_SPACE 0xE8000000 + */ + +#include +#if defined(CFG_IDE_SIL680) +#include +#include +#include + +extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; + +int ide_preinit (void) +{ + int status; + pci_dev_t devbusfn; + int l; + + status = 1; + for (l = 0; l < CFG_IDE_MAXBUS; l++) { + ide_bus_offset[l] = -ATA_STATUS; + } + devbusfn = pci_find_device (0x1095, 0x0680, 0); + if (devbusfn != -1) { + status = 0; + + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, + (u32 *) &ide_bus_offset[0]); + ide_bus_offset[0] &= 0xfffffff8; + ide_bus_offset[0] += CFG_PCI0_IO_SPACE; + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, + (u32 *) &ide_bus_offset[1]); + ide_bus_offset[1] &= 0xfffffff8; + ide_bus_offset[1] += CFG_PCI0_IO_SPACE; + /* init various things - taken from the Linux driver */ + /* set PIO mode */ + pci_write_config_byte(devbusfn, 0x80, 0x00); + pci_write_config_byte(devbusfn, 0x84, 0x00); + /* IDE0 */ + pci_write_config_byte(devbusfn, 0xA1, 0x02); + pci_write_config_word(devbusfn, 0xA2, 0x328A); + pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD); + pci_write_config_dword(devbusfn, 0xA8, 0x43924392); + pci_write_config_dword(devbusfn, 0xAC, 0x40094009); + /* IDE1 */ + pci_write_config_byte(devbusfn, 0xB1, 0x02); + pci_write_config_word(devbusfn, 0xB2, 0x328A); + pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD); + pci_write_config_dword(devbusfn, 0xB8, 0x43924392); + pci_write_config_dword(devbusfn, 0xBC, 0x40094009); + } + return (status); +} + +void ide_set_reset (int flag) { + return; +} + +#endif /* CFG_IDE_SIL680 */ -- cgit v1.3.1 From 1d2ca446e1a731df420206d04fe278c27ea6b8e8 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Thu, 30 Aug 2007 18:19:05 +0800 Subject: Add BUILD_DIR support for bios emulator. Signed-off-by: Jason Jin --- drivers/bios_emulator/Makefile | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index 586e83be8f2..90c64dad602 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -2,9 +2,11 @@ include $(TOPDIR)/config.mk LIB := $(obj)libatibiosemu.a -X86DIR = ./x86emu +X86DIR = x86emu -OBJS = atibios.o biosemu.o besys.o bios.o \ +$(shell mkdir -p $(obj)$(X86DIR)) + +COBJS = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/decode.o \ $(X86DIR)/ops2.o \ $(X86DIR)/ops.o \ @@ -12,19 +14,24 @@ OBJS = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/sys.o \ $(X86DIR)/debug.o -CFLAGS += -I. -I./include -I$(X86DIR) -I$(TOPDIR)/include \ +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \ -D__PPC__ -D__BIG_ENDIAN__ +CFLAGS += $(EXTRA_CFLAGS) +HOST_CFLAGS += $(EXTRA_CFLAGS) + all: $(LIB) -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) ######################################################################### -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude $(obj).depend ######################################################################### -- cgit v1.3.1 From 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3 Mon Sep 17 00:00:00 2001 From: stefano babic Date: Thu, 30 Aug 2007 23:01:49 +0200 Subject: PXA270: Added support for TrizepsIV board. This patch add support for the Trizeps IV module (520Mhz). Signed-off-by: Stefano Babic --- Makefile | 3 + board/trizepsiv/Makefile | 51 ++++ board/trizepsiv/config.mk | 3 + board/trizepsiv/conxs.c | 146 ++++++++++++ board/trizepsiv/eeprom.c | 85 +++++++ board/trizepsiv/lowlevel_init.S | 503 ++++++++++++++++++++++++++++++++++++++++ board/trizepsiv/pxavoltage.S | 31 +++ board/trizepsiv/u-boot.lds | 56 +++++ drivers/dm9000x.c | 16 +- include/configs/trizepsiv.h | 325 ++++++++++++++++++++++++++ 10 files changed, 1217 insertions(+), 2 deletions(-) create mode 100644 board/trizepsiv/Makefile create mode 100644 board/trizepsiv/config.mk create mode 100644 board/trizepsiv/conxs.c create mode 100644 board/trizepsiv/eeprom.c create mode 100644 board/trizepsiv/lowlevel_init.S create mode 100644 board/trizepsiv/pxavoltage.S create mode 100644 board/trizepsiv/u-boot.lds create mode 100644 include/configs/trizepsiv.h (limited to 'drivers') diff --git a/Makefile b/Makefile index 0477cd3dc2e..0371d4619d4 100644 --- a/Makefile +++ b/Makefile @@ -2334,6 +2334,9 @@ scpu_config: unconfig pxa255_idp_config: unconfig @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp +trizepsiv_config : unconfig + @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv + wepep250_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa wepep250 diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile new file mode 100644 index 00000000000..115e17ded92 --- /dev/null +++ b/board/trizepsiv/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := conxs.o eeprom.o +SOBJS := lowlevel_init.o pxavoltage.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/trizepsiv/config.mk b/board/trizepsiv/config.mk new file mode 100644 index 00000000000..4486f6b96db --- /dev/null +++ b/board/trizepsiv/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE =0xa1f00000 +# 0xa1700000 +#TEXT_BASE = 0 diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c new file mode 100644 index 00000000000..7c6c8550074 --- /dev/null +++ b/board/trizepsiv/conxs.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ + +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +void usb_board_init(void) +{ + UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + UHCHR |= UHCHR_FSBIR; + + while (UHCHR & UHCHR_FSBIR); + + UHCHR &= ~UHCHR_SSE; + UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + + /* Clear any OTG Pin Hold */ + if (PSSR & PSSR_OTGPH) + PSSR |= PSSR_OTGPH; + + UHCRHDA &= ~(RH_A_NPS); + UHCRHDA |= RH_A_PSM; + + /* Set port power control mask bits, only 3 ports. */ + UHCRHDB |= (0x7<<17); +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + UHCHR |= UHCHR_FHR; + udelay(11); + UHCHR &= ~UHCHR_FHR; + + UHCCOMS |= 1; + udelay(10); + + CKEN &= ~CKEN10_USBHOST; + + puts("Called USB STOP\n"); + return; +} + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of ConXS Board */ + gd->bd->bi_arch_number = 776; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa000003c; + + return 0; +} + +int board_late_init(void) +{ +#if defined(CONFIG_SERIAL_MULTI) + char *console=getenv("boot_console"); + + if ((strcmp(console,"serial_btuart") == 0) || + (strcmp(console,"serial_stuart") == 0) || + (strcmp(console,"serial_ffuart") == 0)) { + setenv("stdout",console); + setenv("stdin", console); + setenv("stderr",console); + } else { + setenv("stdout", "serial"); + setenv("stdin", "serial"); + setenv("stderr", "serial"); + } +#endif + return 0; +} + +struct serial_device *default_serial_console (void) +{ + return &serial_ffuart_device; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c new file mode 100644 index 00000000000..3d3bc00221b --- /dev/null +++ b/board/trizepsiv/eeprom.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +static unsigned char srom[128]; +extern u16 read_srom_word(int); +extern void write_srom_word(int offset, u16 val); + +static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int i; + + for (i=0; i < 0x40; i++) { + if (!(i % 0x10)) + printf("\n%08lx:", i); + printf(" %04x", read_srom_word(i)); + } + printf ("\n"); + return (0); +} + +static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int offset,value; + + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + offset=simple_strtoul(argv[2],NULL,16); + value=simple_strtoul(argv[3],NULL,16); + if (offset > 0x40) { + printf("Wrong offset : 0x%x\n",offset); + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + write_srom_word(offset, value); + return (0); +} + +int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp (argv[1],"read") == 0) { + return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else if (strcmp (argv[1],"write") == 0) { + return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } +} + +U_BOOT_CMD( + dm9000ee,4,1,do_dm9000_eeprom, + "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n", + "\ndm9000ee write \n" + "\tdm9000ee read \n" + "\tword:\t\t00-02 : MAC Address\n" + "\t\t\t03-07 : DM9000 Configuration\n" + "\t\t\t08-63 : User data\n"); diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S new file mode 100644 index 00000000000..d8869381acc --- /dev/null +++ b/board/trizepsiv/lowlevel_init.S @@ -0,0 +1,503 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CFG_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CFG_GPCR3_VAL + str r1, [r0] + + ldr r0, =GRER0 + ldr r1, =CFG_GRER0_VAL + str r1, [r0] + + ldr r0, =GRER1 + ldr r1, =CFG_GRER1_VAL + str r1, [r0] + + ldr r0, =GRER2 + ldr r1, =CFG_GRER2_VAL + str r1, [r0] + + ldr r0, =GRER3 + ldr r1, =CFG_GRER3_VAL + str r1, [r0] + + ldr r0, =GFER0 + ldr r1, =CFG_GFER0_VAL + str r1, [r0] + + ldr r0, =GFER1 + ldr r1, =CFG_GFER1_VAL + str r1, [r0] + + ldr r0, =GFER2 + ldr r1, =CFG_GFER2_VAL + str r1, [r0] + + ldr r0, =GFER3 + ldr r1, =CFG_GFER3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CFG_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CFG_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CFG_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + ldr r2, =CFG_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CFG_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + bic r4, r4, #MDREFR_K2FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + ldr r2, =CFG_SXCNFG_VAL + str r2, [r1, #SXCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ + + +setvoltage: + + mov r10, lr + bl initPXAvoltage /* In case the board is rebooting with a */ + mov lr, r10 /* low voltage raise it up to a good one. */ + +#if 1 + b initirqs +#endif + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CFG_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CFG_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MEMC_BASE + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#else +#error "RTC not defined" +#endif + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/trizepsiv/pxavoltage.S b/board/trizepsiv/pxavoltage.S new file mode 100644 index 00000000000..5e411321f30 --- /dev/null +++ b/board/trizepsiv/pxavoltage.S @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + + .global initPXAvoltage + +initPXAvoltage: + mov pc, lr + diff --git a/board/trizepsiv/u-boot.lds b/board/trizepsiv/u-boot.lds new file mode 100644 index 00000000000..f0102391b34 --- /dev/null +++ b/board/trizepsiv/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c index e0d531bd917..6131b5c3570 100644 --- a/drivers/dm9000x.c +++ b/drivers/dm9000x.c @@ -99,7 +99,7 @@ void eth_halt(void); static int dm9000_probe(void); static u16 phy_read(int); static void phy_write(int, u16); -static u16 read_srom_word(int); +u16 read_srom_word(int); static u8 DM9000_ior(int); static void DM9000_iow(int reg, u8 value); @@ -537,7 +537,7 @@ eth_rx(void) /* Read a word data from SROM */ -static u16 +u16 read_srom_word(int offset) { DM9000_iow(DM9000_EPAR, offset); @@ -547,6 +547,18 @@ read_srom_word(int offset) return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); } +void +write_srom_word(int offset, u16 val) +{ + DM9000_iow(DM9000_EPAR, offset); + DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); + DM9000_iow(DM9000_EPDRL, (val & 0xff)); + DM9000_iow(DM9000_EPCR, 0x12); + udelay(8000); + DM9000_iow(DM9000_EPCR, 0); +} + + /* Read a byte from I/O port */ diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h new file mode 100644 index 00000000000..84998d4392a --- /dev/null +++ b/include/configs/trizepsiv.h @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the LUBBOCK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ + +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ + +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define RTC + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_FFUART 1 /* we use FFUART on Conxs */ +#define CONFIG_BTUART 1 /* we use BTUART on Conxs */ +#define CONFIG_STUART 1 /* we use STUART on Conxs */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IMLS +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SERVERIP 192.168.1.99 +#define CONFIG_BOOTCOMMAND "run boot_flash" +#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ + " rw root=/dev/ram initrd=0xa0800000,5m" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "program_boot_mmc=" \ + "mw.b 0xa0010000 0xff 0x20000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x1ffff; " \ + "erase 0x0 0x1ffff; " \ + "cp.b 0xa0010000 0x0 0x20000; " \ + "fi\0" \ + "program_uzImage_mmc=" \ + "mw.b 0xa0010000 0xff 0x180000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 uzImage; " \ + "then " \ + "protect off 0x40000 0x1bffff; " \ + "erase 0x40000 0x1bffff; " \ + "cp.b 0xa0010000 0x40000 0x180000; " \ + "fi\0" \ + "program_ramdisk_mmc=" \ + "mw.b 0xa0010000 0xff 0x500000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 ramdisk.gz; " \ + "then " \ + "protect off 0x1c0000 0x6bffff; " \ + "erase 0x1c0000 0x6bffff; " \ + "cp.b 0xa0010000 0x1c0000 0x500000; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmcinit && " \ + "fatload mmc 0 0xa0030000 uzImage && " \ + "fatload mmc 0 0xa0800000 ramdisk.gz; " \ + "then " \ + "bootm 0xa0030000; " \ + "fi\0" \ + "boot_flash=" \ + "cp.b 0x1c0000 0xa0800000 0x500000; " \ + "bootm 0x40000\0" \ + +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +/* #define CONFIG_INITRD_TAG 1 */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MMC_BASE 0xF0000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00018000 +#define CFG_GPSR1_VAL 0x00000000 +#define CFG_GPSR2_VAL 0x400dc000 +#define CFG_GPSR3_VAL 0x00000000 +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPCR3_VAL 0x00000000 +#define CFG_GPDR0_VAL 0x00018000 +#define CFG_GPDR1_VAL 0x00028801 +#define CFG_GPDR2_VAL 0x520dc000 +#define CFG_GPDR3_VAL 0x0001E000 +#define CFG_GAFR0_L_VAL 0x801c0000 +#define CFG_GAFR0_U_VAL 0x00000013 +#define CFG_GAFR1_L_VAL 0x6990100A +#define CFG_GAFR1_U_VAL 0x00000008 +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x010900F2 +#define CFG_GAFR3_L_VAL 0x54000003 +#define CFG_GAFR3_U_VAL 0x00002401 +#define CFG_GRER0_VAL 0x00000000 +#define CFG_GRER1_VAL 0x00000000 +#define CFG_GRER2_VAL 0x00000000 +#define CFG_GRER3_VAL 0x00000000 +#define CFG_GFER0_VAL 0x00000000 +#define CFG_GFER1_VAL 0x00000000 +#define CFG_GFER2_VAL 0x00000000 +#define CFG_GFER3_VAL 0x00000020 + + +#define CFG_PSSR_VAL 0x20 /* CHECK */ + +/* + * Clock settings + */ +#define CFG_CKEN 0x01FFFFFF /* CHECK */ +#define CFG_CCCR 0x02000290 /* 520Mhz */ + +/* + * Memory settings + */ + +#define CFG_MSC0_VAL 0x4df84df0 +#define CFG_MSC1_VAL 0x7ff87ff4 +#define CFG_MSC2_VAL 0xa26936d4 +#define CFG_MDCNFG_VAL 0x880009C9 +#define CFG_MDREFR_VAL 0x20ca201e +#define CFG_MDMRS_VAL 0x00220022 + +#define CFG_FLYCNFG_VAL 0x00000000 +#define CFG_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000001 +#define CFG_MCMEM0_VAL 0x00004204 +#define CFG_MCMEM1_VAL 0x00010204 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00008407 +#define CFG_MCIO1_VAL 0x0000c108 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x08000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) +/* #define CONFIG_DM9000_USE_8BIT */ +/* #define CONFIG_DM9000_USE_16BIT */ +#define CONFIG_DM9000_USE_32BIT + +#define CONFIG_USB_OHCI_NEW 1 +#define CFG_USB_OHCI_BOARD_INIT 1 +#define CFG_USB_OHCI_MAX_ROOT_PORTS 3 +#define CFG_USB_OHCI_REGS_BASE 0x4C000000 +#define CFG_USB_OHCI_SLOT_NAME "trizepsiv" +#define CONFIG_USB_STORAGE 1 +#define CFG_USB_OHCI_CPU_INIT 1 + +/* + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_MONITOR_BASE 0 +#define CFG_MONITOR_LEN 0x40000 + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* write flash less slowly */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* Flash environment locations */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 1218abf1b5817a39a82399b4b928b00750575bda Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 15 Sep 2007 20:48:41 +0200 Subject: Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as global Signed-off-by: Wolfgang Denk --- board/amcc/katmai/katmai.c | 4 ++-- board/amcc/taishan/taishan.c | 4 ++-- board/amcc/yucca/yucca.c | 4 ++-- board/bf533-ezkit/bf533-ezkit.c | 3 ++- board/bf533-stamp/bf533-stamp.c | 3 ++- board/bf537-stamp/bf537-stamp.c | 3 ++- board/bf561-ezkit/bf561-ezkit.c | 3 ++- board/freescale/mpc8313erdb/sdram.c | 3 ++- board/lpc2292sodimm/lpc2292sodimm.c | 7 +------ board/mpc7448hpc2/mpc7448hpc2.c | 4 ++-- board/mpc7448hpc2/tsi108_init.c | 4 ++-- board/mpl/vcma9/cmd_vcma9.c | 4 ++-- board/sbc2410x/sbc2410x.c | 5 +---- board/siemens/SMN42/smn42.c | 7 +------ board/tqm5200/tqm5200.c | 4 ++-- cpu/arm720t/serial.c | 2 -- cpu/bf533/serial.c | 1 - cpu/bf537/i2c.c | 3 ++- cpu/bf537/serial.c | 3 ++- cpu/bf561/serial.c | 3 ++- cpu/mcf532x/cpu.c | 4 ++-- cpu/mcf532x/speed.c | 4 ++-- cpu/mpc86xx/cpu_init.c | 3 ++- cpu/mpc86xx/speed.c | 2 +- cpu/mpc86xx/traps.c | 4 ++-- drivers/qe/qe.c | 7 ++----- drivers/usbdcore_mpc8xx.c | 3 ++- include/configs/atstk1002.h | 3 +-- lib_blackfin/board.c | 7 ++----- lib_blackfin/post.c | 10 ++-------- 30 files changed, 51 insertions(+), 70 deletions(-) (limited to 'drivers') diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index afd60ece624..a49066fcc94 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -34,6 +34,8 @@ #undef PCIE_ENDPOINT /* #define PCIE_ENDPOINT 1 */ +DECLARE_GLOBAL_DATA_PTR; + int ppc440spe_init_pcie_rootport(int port); void ppc440spe_setup_pcie(struct pci_controller *hose, int port); @@ -322,8 +324,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index bc976c75261..f00397ed197 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -32,6 +32,8 @@ void show_reset_reg(void); #endif +DECLARE_GLOBAL_DATA_PTR; + int lcd_init(void); int board_early_init_f (void) @@ -266,8 +268,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 397b01873f4..d7cc384ba0b 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -34,6 +34,8 @@ #include "yucca.h" #include "../cpu/ppc4xx/440spe_pcie.h" +DECLARE_GLOBAL_DATA_PTR; + #undef PCIE_ENDPOINT /* #define PCIE_ENDPOINT 1 */ @@ -668,8 +670,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 1dd4a3fe2e0..98ed6f81d2b 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -30,6 +30,8 @@ #include "psd4256.h" #endif +DECLARE_GLOBAL_DATA_PTR; + int checkboard(void) { #if (BFIN_CPU == ADSP_BF531) @@ -46,7 +48,6 @@ int checkboard(void) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG int brate; char *tmp = getenv("baudrate"); diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index b9dff99171a..69e425bf974 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -30,6 +30,8 @@ #include #include "bf533-stamp.h" +DECLARE_GLOBAL_DATA_PTR; + #define STATUS_LED_OFF 0 #define STATUS_LED_ON 1 @@ -55,7 +57,6 @@ int checkboard(void) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG printf("SDRAM attributes:\n"); printf diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 919cef688db..b3d8bda9bf6 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -32,6 +32,8 @@ #include #include "ether_bf537.h" +DECLARE_GLOBAL_DATA_PTR; + #define POST_WORD_ADDR 0xFF903FFC /* @@ -132,7 +134,6 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG int brate; char *tmp = getenv("baudrate"); diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 989b0194c1e..2ff44a7152a 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -29,6 +29,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + int checkboard(void) { printf("CPU: ADSP BF561\n"); @@ -39,7 +41,6 @@ int checkboard(void) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG int brate; char *tmp = getenv("baudrate"); diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index e6e84107eb2..16ec4bbf546 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -33,10 +33,11 @@ #include +DECLARE_GLOBAL_DATA_PTR; + #ifndef CFG_8313ERDB_BROKEN_PMC static void resume_from_sleep(void) { - DECLARE_GLOBAL_DATA_PTR; u32 magic = *(u32 *)0; typedef void (*func_t)(void); diff --git a/board/lpc2292sodimm/lpc2292sodimm.c b/board/lpc2292sodimm/lpc2292sodimm.c index d212c63328b..9c2d1af2fcb 100644 --- a/board/lpc2292sodimm/lpc2292sodimm.c +++ b/board/lpc2292sodimm/lpc2292sodimm.c @@ -28,8 +28,7 @@ #include #include -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -37,8 +36,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* Activate LED flasher */ IO_LEDFLSH = 0x40; @@ -53,8 +50,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/mpc7448hpc2/mpc7448hpc2.c index 63c99de1756..81846eba77d 100644 --- a/board/mpc7448hpc2/mpc7448hpc2.c +++ b/board/mpc7448hpc2/mpc7448hpc2.c @@ -38,6 +38,8 @@ extern void ft_cpu_setup (void *blob, bd_t *bd); #undef DEBUG +DECLARE_GLOBAL_DATA_PTR; + extern void flush_data_cache (void); extern void invalidate_l1_instruction_cache (void); extern void tsi108_init_f (void); @@ -46,8 +48,6 @@ int display_mem_map (void); void after_reloc (ulong dest_addr) { - DECLARE_GLOBAL_DATA_PTR; - /* * Jump to the main U-Boot board init code */ diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c index 8a7efef7723..30ae17d8729 100644 --- a/board/mpc7448hpc2/tsi108_init.c +++ b/board/mpc7448hpc2/tsi108_init.c @@ -33,6 +33,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + extern void mpicInit (int verbose); /* @@ -141,7 +143,6 @@ unsigned long get_board_bus_clk (void) int board_early_init_f (void) { - DECLARE_GLOBAL_DATA_PTR; ulong i; gd->mem_clk = 0; @@ -583,7 +584,6 @@ unsigned long get_l2cr (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; #ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ ulong i; diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index 44b41125546..227c49272ce 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -40,6 +40,8 @@ static uchar cs8900_chksum(ushort data) #endif +DECLARE_GLOBAL_DATA_PTR; + extern void print_vcma9_info(void); extern int vcma9_cantest(int); extern int vcma9_nandtest(void); @@ -53,8 +55,6 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - DECLARE_GLOBAL_DATA_PTR; - if (strcmp(argv[1], "info") == 0) { print_vcma9_info(); diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index b4865e1229c..6c894a3869e 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -35,7 +35,7 @@ #include #endif -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; #define FCLK_SPEED 1 @@ -74,7 +74,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); @@ -128,8 +127,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/siemens/SMN42/smn42.c b/board/siemens/SMN42/smn42.c index cbfc76c4639..52d1d7e5f38 100644 --- a/board/siemens/SMN42/smn42.c +++ b/board/siemens/SMN42/smn42.c @@ -31,8 +31,7 @@ #include #include -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscellaneous platform dependent initialisations @@ -40,8 +39,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number MACH_TYPE_ARMADILLO - not official*/ gd->bd->bi_arch_number = 83; @@ -53,8 +50,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 21f67aa4e53..29d6f00427f 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -43,6 +43,8 @@ #include "mt48lc16m16a2-75.h" #endif +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_PS2MULT void ps2mult_early_init(void); #endif @@ -477,8 +479,6 @@ int silent_boot (void) int board_early_init_f (void) { - DECLARE_GLOBAL_DATA_PTR; - if (silent_boot()) gd->flags |= GD_FLG_SILENT; diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c index 15c54af08b7..27eb73ad889 100644 --- a/cpu/arm720t/serial.c +++ b/cpu/arm720t/serial.c @@ -129,8 +129,6 @@ serial_puts (const char *s) void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - unsigned short divisor = 0; switch (gd->baudrate) { diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c index 6cab5daac79..8ac6e3ff64e 100644 --- a/cpu/bf533/serial.c +++ b/cpu/bf533/serial.c @@ -76,7 +76,6 @@ void calc_baud(void) void serial_setbrg(void) { int i; - DECLARE_GLOBAL_DATA_PTR; calc_baud(); diff --git a/cpu/bf537/i2c.c b/cpu/bf537/i2c.c index 3b0d026e0dc..0daba63b68a 100644 --- a/cpu/bf537/i2c.c +++ b/cpu/bf537/i2c.c @@ -22,6 +22,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #define bfin_read16(addr) ({ unsigned __v; \ __asm__ __volatile__ (\ "%0 = w[%1] (z);\n\t"\ @@ -68,7 +70,6 @@ #ifdef DEBUG_I2C #define PRINTD(fmt,args...) do { \ - DECLARE_GLOBAL_DATA_PTR; \ if (gd->have_console) \ printf(fmt ,##args); \ } while (0) diff --git a/cpu/bf537/serial.c b/cpu/bf537/serial.c index e04d08a0e77..f7a2483ffbe 100644 --- a/cpu/bf537/serial.c +++ b/cpu/bf537/serial.c @@ -52,6 +52,8 @@ #include #include "serial.h" +DECLARE_GLOBAL_DATA_PTR; + unsigned long pll_div_fact; void calc_baud(void) @@ -74,7 +76,6 @@ void calc_baud(void) void serial_setbrg(void) { int i; - DECLARE_GLOBAL_DATA_PTR; calc_baud(); diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c index 7f5c6953618..bc5a4f57260 100644 --- a/cpu/bf561/serial.c +++ b/cpu/bf561/serial.c @@ -52,6 +52,8 @@ #include "serial.h" #include +DECLARE_GLOBAL_DATA_PTR; + unsigned long pll_div_fact; void calc_baud(void) @@ -74,7 +76,6 @@ void calc_baud(void) void serial_setbrg(void) { int i; - DECLARE_GLOBAL_DATA_PTR; calc_baud(); diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c index 520f5d69397..2f62e956cca 100644 --- a/cpu/mcf532x/cpu.c +++ b/cpu/mcf532x/cpu.c @@ -31,6 +31,8 @@ #include +DECLARE_GLOBAL_DATA_PTR; + int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) { volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); @@ -48,8 +50,6 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) int checkcpu(void) { - DECLARE_GLOBAL_DATA_PTR; - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; u16 msk; u16 id = 0; diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c index cf72609b42f..001b9f42d64 100644 --- a/cpu/mcf532x/speed.c +++ b/cpu/mcf532x/speed.c @@ -30,6 +30,8 @@ #include +DECLARE_GLOBAL_DATA_PTR; + /* PLL min/max specifications */ #define MAX_FVCO 500000 /* KHz */ #define MAX_FSYS 80000 /* KHz */ @@ -208,8 +210,6 @@ int clock_pll(int fsys, int flags) */ int get_clocks(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000; gd->cpu_clk = (gd->bus_clk * 3); return (0); diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index c8e46666949..4f8956e0afe 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -29,6 +29,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + /* * Breathe some life into the CPU... * @@ -38,7 +40,6 @@ void cpu_init_f(void) { - DECLARE_GLOBAL_DATA_PTR; volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 312ca128277..23161ca8cbe 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -29,6 +29,7 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; void get_sys_info(sys_info_t *sysInfo) { @@ -96,7 +97,6 @@ void get_sys_info(sys_info_t *sysInfo) int get_clocks(void) { - DECLARE_GLOBAL_DATA_PTR; sys_info_t sys_info; get_sys_info(&sys_info); diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index c84bfbf6aaa..04c2e1331b6 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -34,6 +34,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -50,8 +52,6 @@ extern unsigned long search_exception_table(unsigned long); void print_backtrace(unsigned long *sp) { - DECLARE_GLOBAL_DATA_PTR; - int cnt = 0; unsigned long i; diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 0f5232a72af..7559e922272 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -30,6 +30,8 @@ qe_map_t *qe_immr = NULL; static qe_snum_t snums[QE_NUM_OF_SNUM]; +DECLARE_GLOBAL_DATA_PTR; + void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) { u32 cecr; @@ -51,8 +53,6 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) uint qe_muram_alloc(uint size, uint align) { - DECLARE_GLOBAL_DATA_PTR; - uint retloc; uint align_mask, off; uint savebase; @@ -158,8 +158,6 @@ void qe_put_snum(u8 snum) void qe_init(uint qe_base) { - DECLARE_GLOBAL_DATA_PTR; - /* Init the QE IMMR base */ qe_immr = (qe_map_t *)qe_base; @@ -204,7 +202,6 @@ void qe_assign_page(uint snum, uint para_ram_base) int qe_set_brg(uint brg, uint rate) { - DECLARE_GLOBAL_DATA_PTR; volatile uint *bp; u32 divisor; int div16 = 0; diff --git a/drivers/usbdcore_mpc8xx.c b/drivers/usbdcore_mpc8xx.c index e87284b1787..d4c40965656 100644 --- a/drivers/usbdcore_mpc8xx.c +++ b/drivers/usbdcore_mpc8xx.c @@ -64,6 +64,8 @@ #include "usbdcore_mpc8xx.h" #include "usbdcore_ep0.h" +DECLARE_GLOBAL_DATA_PTR; + #define ERR(fmt, args...)\ serial_printf("ERROR : [%s] %s:%d: "fmt,\ __FILE__,__FUNCTION__,__LINE__, ##args) @@ -1216,7 +1218,6 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr, #elif defined(CFG_USB_BRGCLK) /* This has been tested with brgclk == 50MHz */ - DECLARE_GLOBAL_DATA_PTR; int divisor = 0; if (gd->cpu_clk < 48000000L) { diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index e1d8f74c5ec..75b153e4a85 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -183,10 +183,9 @@ #define CFG_LONGHELP 1 #define CFG_MEMTEST_START \ - ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; }) + ({ gd->bd->bi_dram[0].start; }) #define CFG_MEMTEST_END \ ({ \ - DECLARE_GLOBAL_DATA_PTR; \ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \ }) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index 36a969e7318..7c9990f8e0d 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -42,6 +42,8 @@ int post_flag; #endif +DECLARE_GLOBAL_DATA_PTR; + #ifndef CFG_NO_FLASH extern flash_info_t flash_info[]; #endif @@ -126,8 +128,6 @@ static void display_flash_config(ulong size) static int init_baudrate(void) { - DECLARE_GLOBAL_DATA_PTR; - char tmp[64]; int i = getenv_r("baudrate", tmp, sizeof(tmp)); gd->bd->bi_baudrate = gd->baudrate = (i > 0) @@ -139,7 +139,6 @@ static int init_baudrate(void) #ifdef DEBUG static void display_global_data(void) { - DECLARE_GLOBAL_DATA_PTR; bd_t *bd; bd = gd->bd; printf("--flags:%x\n", gd->flags); @@ -256,7 +255,6 @@ void init_cplbtables(void) void board_init_f(ulong bootflag) { - DECLARE_GLOBAL_DATA_PTR; ulong addr; bd_t *bd; int i; @@ -325,7 +323,6 @@ static int init_func_i2c(void) void board_init_r(gd_t * id, ulong dest_addr) { - DECLARE_GLOBAL_DATA_PTR; ulong size; extern void malloc_bin_reloc(void); char *s, *e; diff --git a/lib_blackfin/post.c b/lib_blackfin/post.c index 7c9478def5c..3c4d5c51dda 100644 --- a/lib_blackfin/post.c +++ b/lib_blackfin/post.c @@ -32,14 +32,14 @@ #ifdef CONFIG_POST +DECLARE_GLOBAL_DATA_PTR; + #define POST_MAX_NUMBER 32 #define BOOTMODE_MAGIC 0xDEAD0000 int post_init_f(void) { - DECLARE_GLOBAL_DATA_PTR; - int res = 0; unsigned int i; @@ -62,7 +62,6 @@ int post_init_f(void) void post_bootmode_init(void) { - DECLARE_GLOBAL_DATA_PTR; int bootmode = post_bootmode_get(0); int newword; @@ -109,20 +108,17 @@ int post_bootmode_get(unsigned int *last_test) /* POST tests run before relocation only mark status bits .... */ static void post_log_mark_start(unsigned long testid) { - DECLARE_GLOBAL_DATA_PTR; gd->post_log_word |= (testid) << 16; } static void post_log_mark_succ(unsigned long testid) { - DECLARE_GLOBAL_DATA_PTR; gd->post_log_word |= testid; } /* ... and the messages are output once we are relocated */ void post_output_backlog(void) { - DECLARE_GLOBAL_DATA_PTR; int j; for (j = 0; j < post_list_size; j++) { @@ -372,8 +368,6 @@ int post_log(char *format, ...) void post_reloc(void) { - DECLARE_GLOBAL_DATA_PTR; - unsigned int i; /* -- cgit v1.3.1 From 5bd7fe9aeb76906371f40b8fd07613f10922e3e7 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Tue, 11 Sep 2007 17:04:00 +0200 Subject: Fix do_div() usage in nand process output Fix usage of do_div() in nand erase|read|write process output. The last patch to nand_util.c introduced do_div() instead of libgcc's implementation. But do_div() returns the quotient in its first macro parameter and not as result. Signed-off-by: Matthias Fuchs --- common/cmd_nand.c | 2 +- drivers/nand/nand_util.c | 21 ++++++++++++++++----- 2 files changed, 17 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/common/cmd_nand.c b/common/cmd_nand.c index aeb76e5fb71..1fdd7a67f60 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -456,7 +456,7 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" "nand read[.jffs2] - addr off|partition size\n" - "nand write[.jffs2] - addr off|partiton size - read/write `size' bytes starting\n" + "nand write[.jffs2] - addr off|partition size - read/write `size' bytes starting\n" " at offset `off' to/from memory address `addr'\n" "nand erase [clean] [off size] - erase `size' bytes from\n" " offset `off' (entire device if not specified)\n" diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c index cf05043c0af..4fd4e166e6a 100644 --- a/drivers/nand/nand_util.c +++ b/drivers/nand/nand_util.c @@ -210,9 +210,12 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) if (!opts->quiet) { unsigned long long n =(unsigned long long) - (erase.addr+meminfo->erasesize-opts->offset) - * 100; - int percent = (int)do_div(n, erase_length); + (erase.addr + meminfo->erasesize - opts->offset) + * 100; + int percent; + + do_div(n, erase_length); + percent = (int)n; /* output progress message only at whole percent * steps to reduce the number of messages printed @@ -478,7 +481,11 @@ int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts) if (!opts->quiet) { unsigned long long n = (unsigned long long) (opts->length-imglen) * 100; - int percent = (int)do_div(n, opts->length); + int percent; + + do_div(n, opts->length); + percent = (int)n; + /* output progress message only at whole percent * steps to reduce the number of messages printed * on (slow) serial consoles @@ -653,7 +660,11 @@ int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts) if (!opts->quiet) { unsigned long long n = (unsigned long long) (opts->length-imglen) * 100; - int percent = (int)do_div(n ,opts->length); + int percent; + + do_div(n, opts->length); + percent = (int)n; + /* output progress message only at whole percent * steps to reduce the number of messages printed * on (slow) serial consoles -- cgit v1.3.1 From cd2d1602c54cc6957bdef3872272a4b264893960 Mon Sep 17 00:00:00 2001 From: "urwithsughosh@gmail.com" Date: Mon, 10 Sep 2007 14:54:56 -0400 Subject: Typo fix in tsec.c Fixup for the break statement in wrong place. [Patch by urwithsughosh@gmail.com] Acked-by: Andy Fleming Signed-off-by: Wolfgang Denk --- drivers/tsec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index 6bca4dc0f33..4ff3339c7de 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -1262,10 +1262,10 @@ uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) case MIIM_LXT971_SR2_100HDX: priv->speed = 100; priv->duplexity = 0; + break; default: priv->speed = 100; priv->duplexity = 1; - break; } } else { priv->speed = 0; -- cgit v1.3.1 From 97213f32416ead885deafea86774e912ffd60ad0 Mon Sep 17 00:00:00 2001 From: David Saada Date: Mon, 17 Sep 2007 17:04:47 +0200 Subject: Description: Add NEC's PCI OHCI module ID to the USB OHCI driver Signed-off-by: David Saada --- drivers/usb_ohci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index d6b745fadd6..388827fd001 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -93,6 +93,7 @@ #ifdef CONFIG_PCI_OHCI static struct pci_device_id ohci_pci_ids[] = { {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ + {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ /* Please add supported PCI OHCI controller ids here */ {0, 0} }; -- cgit v1.3.1