From 6aa3b740c3e04256d5e22dbae8bc5a802aa3b9b9 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 17 Aug 2020 18:15:08 -0500 Subject: remoteproc: k3-r5: Add support for J7200 R5Fs The K3 J7200 SoC family has a revised R5F sub-system and contains a subset of the R5F clusters present on J721E SoCs. The integration of these clusters is very much similar to J721E SoCs otherwise. The revised IP has the following two new features: 1. TCMs are auto-initialized during module power-up, and the behavior is programmable through a MMR bit controlled by System Firmware. 2. The LockStep-mode allows the Core1 TCMs to be combined with the Core0 TCMs effectively doubling the amount of TCMs available. The LockStep-mode on previous SoCs could only use the Core0 TCMs. This combined TCMs appear contiguous at the respective Core0 TCM addresses. Add the support to these clusters in the K3 R5F remoteproc driver using J7200 specific compatibles and revised logic accounting for the above IP features/differences. Signed-off-by: Suman Anna --- drivers/remoteproc/ti_k3_r5f_rproc.c | 99 ++++++++++++++++++++++++++++++++---- 1 file changed, 89 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index 1a7f1f8a005..8e21a38be7f 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -2,8 +2,9 @@ /* * Texas Instruments' K3 R5 Remoteproc driver * - * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla + * Suman Anna */ #include @@ -37,6 +38,8 @@ #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000 #define PROC_BOOT_CFG_FLAG_GEN_IGN_BOOTVECTOR 0x10000000 +/* Available from J7200 SoCs onwards */ +#define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x00004000 /* R5 TI-SCI Processor Control Flags */ #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 @@ -54,6 +57,16 @@ enum cluster_mode { CLUSTER_MODE_LOCKSTEP, }; +/** + * struct k3_r5f_ip_data - internal data structure used for IP variations + * @tcm_is_double: flag to denote the larger unified TCMs in certain modes + * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC + */ +struct k3_r5f_ip_data { + bool tcm_is_double; + bool tcm_ecc_autoinit; +}; + /** * struct k3_r5_mem - internal memory structure * @cpu_addr: MPU virtual address of the memory region @@ -74,6 +87,7 @@ struct k3_r5f_mem { * @cluster: pointer to the parent cluster. * @reset: reset control handle * @tsp: TI-SCI processor control handle + * @ipdata: cached pointer to R5F IP specific feature data * @mem: Array of available internal memories * @num_mem: Number of available memories * @atcm_enable: flag to control ATCM enablement @@ -86,6 +100,7 @@ struct k3_r5f_core { struct k3_r5f_cluster *cluster; struct reset_ctl reset; struct ti_sci_proc tsp; + struct k3_r5f_ip_data *ipdata; struct k3_r5f_mem *mem; int num_mems; u32 atcm_enable; @@ -257,6 +272,18 @@ static int k3_r5f_core_sanity_check(struct k3_r5f_core *core) return 0; } +/* Zero out TCMs so that ECC can be effective on all TCM addresses */ +void k3_r5f_init_tcm_memories(struct k3_r5f_core *core, bool auto_inited) +{ + if (core->ipdata->tcm_ecc_autoinit && auto_inited) + return; + + if (core->atcm_enable) + memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size); + if (core->btcm_enable) + memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size); +} + /** * k3_r5f_load() - Load up the Remote processor image * @dev: rproc device pointer @@ -268,7 +295,9 @@ static int k3_r5f_core_sanity_check(struct k3_r5f_core *core) static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size) { struct k3_r5f_core *core = dev_get_priv(dev); - u32 boot_vector; + u64 boot_vector; + u32 ctrl, sts, cfg = 0; + bool mem_auto_init; int ret; dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size); @@ -281,6 +310,12 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size) if (ret) return ret; + ret = ti_sci_proc_get_status(&core->tsp, &boot_vector, &cfg, &ctrl, + &sts); + if (ret) + return ret; + mem_auto_init = !(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS); + ret = k3_r5f_prepare(dev); if (ret) { dev_err(dev, "R5f prepare failed for core %d\n", @@ -288,11 +323,7 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size) goto proc_release; } - /* Zero out TCMs so that ECC can be effective on all TCM addresses */ - if (core->atcm_enable) - memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size); - if (core->btcm_enable) - memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size); + k3_r5f_init_tcm_memories(core, mem_auto_init); ret = rproc_elf_load_image(dev, addr, size); if (ret < 0) { @@ -302,7 +333,7 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size) boot_vector = rproc_elf_get_boot_addr(dev, addr); - dev_dbg(dev, "%s: Boot vector = 0x%x\n", __func__, boot_vector); + dev_dbg(dev, "%s: Boot vector = 0x%llx\n", __func__, boot_vector); ret = ti_sci_proc_set_config(&core->tsp, boot_vector, 0, 0); @@ -657,6 +688,8 @@ static int k3_r5f_of_to_priv(struct k3_r5f_core *core) return ret; } + core->ipdata = (struct k3_r5f_ip_data *)dev_get_driver_data(core->dev); + return 0; } @@ -702,6 +735,38 @@ static int k3_r5f_core_of_get_memories(struct k3_r5f_core *core) return 0; } +/* + * Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs, + * split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both + * cores are usable in Split-mode, but only the Core0 TCMs can be used in + * LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by + * leveraging the Core1 TCMs as well in certain modes where they would have + * otherwise been unusable (Eg: LockStep-mode on J7200 SoCs). This is done by + * making a Core1 TCM visible immediately after the corresponding Core0 TCM. + * The SoC memory map uses the larger 64 KB sizes for the Core0 TCMs, and the + * dts representation reflects this increased size on supported SoCs. The Core0 + * TCM sizes therefore have to be adjusted to only half the original size in + * Split mode. + */ +static void k3_r5f_core_adjust_tcm_sizes(struct k3_r5f_core *core) +{ + struct k3_r5f_cluster *cluster = core->cluster; + + if (cluster->mode == CLUSTER_MODE_LOCKSTEP) + return; + + if (!core->ipdata->tcm_is_double) + return; + + if (core == cluster->cores[0]) { + core->mem[0].size /= 2; + core->mem[1].size /= 2; + + dev_dbg(core->dev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n", + core->mem[0].size, core->mem[1].size); + } +} + /** * k3_r5f_probe() - Basic probe * @dev: corresponding k3 remote processor device @@ -755,6 +820,8 @@ static int k3_r5f_probe(struct udevice *dev) return ret; } + k3_r5f_core_adjust_tcm_sizes(core); + dev_dbg(dev, "Remoteproc successfully probed\n"); return 0; @@ -771,9 +838,20 @@ static int k3_r5f_remove(struct udevice *dev) return 0; } +static const struct k3_r5f_ip_data k3_data = { + .tcm_is_double = false, + .tcm_ecc_autoinit = false, +}; + +static const struct k3_r5f_ip_data j7200_data = { + .tcm_is_double = true, + .tcm_ecc_autoinit = true, +}; + static const struct udevice_id k3_r5f_rproc_ids[] = { - { .compatible = "ti,am654-r5f"}, - { .compatible = "ti,j721e-r5f"}, + { .compatible = "ti,am654-r5f", .data = (ulong)&k3_data, }, + { .compatible = "ti,j721e-r5f", .data = (ulong)&k3_data, }, + { .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_data, }, {} }; @@ -810,6 +888,7 @@ static int k3_r5f_cluster_probe(struct udevice *dev) static const struct udevice_id k3_r5fss_ids[] = { { .compatible = "ti,am654-r5fss"}, { .compatible = "ti,j721e-r5fss"}, + { .compatible = "ti,j7200-r5fss"}, {} }; -- cgit v1.3.1 From 280af011563574844fa3c20acd2cbbd7ee669da8 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Mon, 14 Sep 2020 12:11:14 +0530 Subject: spi: spi-uclass: Block dm_scan_fdt_dev with OF_CONTROL to prevent build failures There are devices which don't use OF_CONTROL or OF_PLATDATA but instead rely on statically defined platdata. Block dm_scan_fdt_dev() with both configs to avoid build failures under this condition. Signed-off-by: Faiz Abbas Reviewed-by: Jagan Teki --- drivers/spi/spi-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index cffd9cf0b0e..55a8eed8901 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -497,7 +497,7 @@ UCLASS_DRIVER(spi) = { .id = UCLASS_SPI, .name = "spi", .flags = DM_UC_FLAG_SEQ_ALIAS, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .post_bind = dm_scan_fdt_dev, #endif .post_probe = spi_post_probe, -- cgit v1.3.1 From 41cf3cb39ddbb8a0b892781388e1054653d33ed1 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Mon, 14 Sep 2020 12:11:15 +0530 Subject: arm: mach-omap2: am33xx: Add device structure for spi Add platform data and a device structure for the spi device present on am335x-icev2. This requires moving all omap3_spi platform data structures and symbols to an omap3_spi.h so that the board file can access them. Signed-off-by: Faiz Abbas --- arch/arm/mach-omap2/am33xx/board.c | 18 +++++++++ drivers/spi/omap3_spi.c | 70 +--------------------------------- include/configs/am335x_evm.h | 2 - include/omap3_spi.h | 78 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 97 insertions(+), 71 deletions(-) create mode 100644 include/omap3_spi.h (limited to 'drivers') diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index a7b56b6bb3d..2888390d240 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -49,6 +50,12 @@ #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC #define AM43XX_RDWRLVLFULL_START 0x80000000 +/* SPI flash. */ +#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL) +#define AM33XX_SPI0_BASE 0x48030000 +#define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET) +#endif + DECLARE_GLOBAL_DATA_PTR; int dram_init(void) @@ -142,6 +149,17 @@ U_BOOT_DEVICES(am33xx_gpios) = { #endif }; #endif +#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL) +static const struct omap3_spi_plat omap3_spi_pdata = { + .regs = (struct mcspi *)AM33XX_SPI0_OFFSET, + .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT, +}; + +U_BOOT_DEVICE(am33xx_spi) = { + .name = "omap3_spi", + .platdata = &omap3_spi_pdata, +}; +#endif #endif #if !CONFIG_IS_ENABLED(DM_GPIO) diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index fbf9575851a..fb1cf360fcd 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -22,82 +22,14 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -#define OMAP4_MCSPI_REG_OFFSET 0x100 - struct omap2_mcspi_platform_config { unsigned int regs_offset; }; -/* per-register bitmasks */ -#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3) -#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) -#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) -#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1) - -#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0) - -#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0) -#define OMAP3_MCSPI_MODULCTRL_MS BIT(2) -#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3) - -#define OMAP3_MCSPI_CHCONF_PHA BIT(0) -#define OMAP3_MCSPI_CHCONF_POL BIT(1) -#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2) -#define OMAP3_MCSPI_CHCONF_EPOL BIT(6) -#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7) -#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) -#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) -#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12) -#define OMAP3_MCSPI_CHCONF_DMAW BIT(14) -#define OMAP3_MCSPI_CHCONF_DMAR BIT(15) -#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16) -#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17) -#define OMAP3_MCSPI_CHCONF_IS BIT(18) -#define OMAP3_MCSPI_CHCONF_TURBO BIT(19) -#define OMAP3_MCSPI_CHCONF_FORCE BIT(20) - -#define OMAP3_MCSPI_CHSTAT_RXS BIT(0) -#define OMAP3_MCSPI_CHSTAT_TXS BIT(1) -#define OMAP3_MCSPI_CHSTAT_EOT BIT(2) - -#define OMAP3_MCSPI_CHCTRL_EN BIT(0) -#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0) - -#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0) -#define MCSPI_PINDIR_D0_IN_D1_OUT 0 -#define MCSPI_PINDIR_D0_OUT_D1_IN 1 - -#define OMAP3_MCSPI_MAX_FREQ 48000000 -#define SPI_WAIT_TIMEOUT 10 - -/* OMAP3 McSPI registers */ -struct mcspi_channel { - unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */ - unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */ - unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */ - unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */ - unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */ -}; - -struct mcspi { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned int irqstatus; /* 0x18 */ - unsigned int irqenable; /* 0x1C */ - unsigned int wakeupenable; /* 0x20 */ - unsigned int syst; /* 0x24 */ - unsigned int modulctrl; /* 0x28 */ - struct mcspi_channel channel[4]; - /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */ - /* channel1: 0x40 - 0x50, bus 0 & 1 */ - /* channel2: 0x54 - 0x64, bus 0 & 1 */ - /* channel3: 0x68 - 0x78, bus 0 */ -}; - struct omap3_spi_priv { struct mcspi *regs; unsigned int cs; diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 103c0461374..5af90d932d5 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -287,8 +287,6 @@ #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #endif -/* SPI flash. */ - /* Network. */ /* Enable Atheros phy driver */ diff --git a/include/omap3_spi.h b/include/omap3_spi.h new file mode 100644 index 00000000000..cae37705830 --- /dev/null +++ b/include/omap3_spi.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __OMAP3_SPI_H_ +#define __OMAP3_SPI_H_ + +/* per-register bitmasks */ +#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3) +#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) +#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) +#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1) + +#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0) + +#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0) +#define OMAP3_MCSPI_MODULCTRL_MS BIT(2) +#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3) + +#define OMAP3_MCSPI_CHCONF_PHA BIT(0) +#define OMAP3_MCSPI_CHCONF_POL BIT(1) +#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2) +#define OMAP3_MCSPI_CHCONF_EPOL BIT(6) +#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7) +#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) +#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) +#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12) +#define OMAP3_MCSPI_CHCONF_DMAW BIT(14) +#define OMAP3_MCSPI_CHCONF_DMAR BIT(15) +#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16) +#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17) +#define OMAP3_MCSPI_CHCONF_IS BIT(18) +#define OMAP3_MCSPI_CHCONF_TURBO BIT(19) +#define OMAP3_MCSPI_CHCONF_FORCE BIT(20) + +#define OMAP3_MCSPI_CHSTAT_RXS BIT(0) +#define OMAP3_MCSPI_CHSTAT_TXS BIT(1) +#define OMAP3_MCSPI_CHSTAT_EOT BIT(2) + +#define OMAP3_MCSPI_CHCTRL_EN BIT(0) +#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0) + +#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0) +#define MCSPI_PINDIR_D0_IN_D1_OUT 0 +#define MCSPI_PINDIR_D0_OUT_D1_IN 1 + +#define OMAP3_MCSPI_MAX_FREQ 48000000 +#define SPI_WAIT_TIMEOUT 10 + +#define OMAP4_MCSPI_REG_OFFSET 0x100 + +/* OMAP3 McSPI registers */ +struct mcspi_channel { + unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */ + unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */ + unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */ + unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */ + unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */ +}; + +struct mcspi { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int sysstatus; /* 0x14 */ + unsigned int irqstatus; /* 0x18 */ + unsigned int irqenable; /* 0x1C */ + unsigned int wakeupenable; /* 0x20 */ + unsigned int syst; /* 0x24 */ + unsigned int modulctrl; /* 0x28 */ + struct mcspi_channel channel[4]; + /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */ + /* channel1: 0x40 - 0x50, bus 0 & 1 */ + /* channel2: 0x54 - 0x64, bus 0 & 1 */ + /* channel3: 0x68 - 0x78, bus 0 */ +}; + +struct omap3_spi_plat { + struct mcspi *regs; + unsigned int pin_dir:1; +}; +#endif -- cgit v1.3.1 From afd4f15a39de0fa572792a3037545afbac386ee5 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Mon, 14 Sep 2020 12:11:16 +0530 Subject: spi: omap3_spi: Read platform data in ofdata_to_platdata() Add an ofdata_to_platdata() callback to access dts in U-boot and access all platform data in it. This prepares the driver for supporting both device tree as well as static platform data structures in SPL. Signed-off-by: Faiz Abbas --- drivers/spi/omap3_spi.c | 37 ++++++++++++++++++++++++++----------- 1 file changed, 26 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index fb1cf360fcd..56cb2174868 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -414,17 +414,10 @@ static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen) static int omap3_spi_probe(struct udevice *dev) { struct omap3_spi_priv *priv = dev_get_priv(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); + struct omap3_spi_plat *plat = dev_get_platdata(dev); - struct omap2_mcspi_platform_config* data = - (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev); - - priv->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset); - if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in")) - priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; - else - priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT; + priv->regs = plat->regs; + priv->pin_dir = plat->pin_dir; priv->wordlen = SPI_DEFAULT_WORDLEN; spi_reset(priv->regs); @@ -476,6 +469,7 @@ static const struct dm_spi_ops omap3_spi_ops = { */ }; +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) static struct omap2_mcspi_platform_config omap2_pdata = { .regs_offset = 0, }; @@ -484,16 +478,37 @@ static struct omap2_mcspi_platform_config omap4_pdata = { .regs_offset = OMAP4_MCSPI_REG_OFFSET, }; +static int omap3_spi_ofdata_to_platdata(struct udevice *dev) +{ + struct omap2_mcspi_platform_config *data = + (struct omap2_mcspi_platform_config *)dev_get_driver_data(dev); + struct omap3_spi_plat *plat = dev_get_platdata(dev); + + plat->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset); + + if (dev_read_bool(dev, "ti,pindir-d0-out-d1-in")) + plat->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; + else + plat->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT; + + return 0; +} + static const struct udevice_id omap3_spi_ids[] = { { .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata }, { .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata }, { } }; - +#endif U_BOOT_DRIVER(omap3_spi) = { .name = "omap3_spi", .id = UCLASS_SPI, + .flags = DM_FLAG_PRE_RELOC, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .of_match = omap3_spi_ids, + .ofdata_to_platdata = omap3_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct omap3_spi_plat), +#endif .probe = omap3_spi_probe, .ops = &omap3_spi_ops, .priv_auto_alloc_size = sizeof(struct omap3_spi_priv), -- cgit v1.3.1