From b6779274f2bdbcde2c7fa3a2f90d1db55c02951f Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 15 Jan 2020 02:15:13 -0700 Subject: net: zynq_gem: Use ulong instead of u32 data type flush_dcache_range() expects unsigned long in the arguments. Here u32 variable is unable to hold the higher address value when ddr mapped to higher addresses & flushing lower address dchache range instead which is unmapped causing to crash. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 288037e2a0f..7f9dc3435bf 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -655,7 +655,7 @@ static int zynq_gem_probe(struct udevice *dev) return -ENOMEM; memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); - u32 addr = (ulong)priv->rxbuffers; + ulong addr = (ulong)priv->rxbuffers; flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); barrier(); -- cgit v1.3.1 From 65bcca9f52af8ff88d46de317a9ca6e8a2da5d69 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Thu, 16 Jan 2020 03:55:05 -0800 Subject: versal: drivers: clk: Fix invalid clock name queries The clock driver makes EEMI call to get the name of invalid clk when executing versal_get_clock_info() function. This results in error messages. Added check for validating clock before saving clock attribute and calling versal_pm_clock_get_name() in versal_get_clock_info() function. Signed-off-by: Rajan Vaja Signed-off-by: Michal Simek --- drivers/clk/clk_versal.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 9d4d2149e32..d3673a5c8b8 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -571,6 +571,12 @@ static void versal_get_clock_info(void) continue; clock[i].valid = attr & CLK_VALID_MASK; + + /* skip query for Invalid clock */ + ret = versal_is_valid_clock(i); + if (ret != CLK_VALID_MASK) + continue; + clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ? CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT; nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK; -- cgit v1.3.1 From 4c2c28a46571498c55b38d988ace3d176368ed6b Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Sun, 19 Jan 2020 23:59:23 -0700 Subject: mtd: nand: Fix on-die ecc issues in arasan_nfc driver Fixed wrong enumeration of nand_config structure. Added chip select function before reading the nand chip for maf/dev id's, without this unable to access id's from some of the micron chips. Also added a print statement to identify if a nand flash is using on-die ecc. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- drivers/mtd/nand/raw/arasan_nfc.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index d1b1a4263a2..110c32b3961 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -1120,12 +1120,15 @@ static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command, static void arasan_check_ondie(struct mtd_info *mtd) { struct nand_chip *nand_chip = mtd_to_nand(mtd); - struct nand_config *nand = nand_get_controller_data(nand_chip); + struct nand_drv *info = nand_get_controller_data(nand_chip); + struct nand_config *nand = &info->config; u8 maf_id, dev_id; u8 get_feature[4]; u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00}; u32 i; + nand_chip->select_chip(mtd, 0); + /* Send the command for reading device ID */ nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0, -1); @@ -1150,10 +1153,12 @@ static void arasan_check_ondie(struct mtd_info *mtd) for (i = 0; i < 4; i++) get_feature[i] = nand_chip->read_byte(mtd); - if (get_feature[0] & ENABLE_ONDIE_ECC) + if (get_feature[0] & ENABLE_ONDIE_ECC) { nand->on_die_ecc_enabled = true; - else + printf("On-DIE ECC Enabled\n"); + } else { printf("%s: Unable to enable OnDie ECC\n", __func__); + } /* Use the BBT pattern descriptors */ nand_chip->bbt_td = &bbt_main_descr; -- cgit v1.3.1 From 380376520f726ee7544c2fcd3c114187f01a6f27 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 6 Feb 2020 15:59:23 +0100 Subject: net: phy: dp83867: Clean force link good bit On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which means FORCE_LINK_GOOD is already setup. Origin code was doing write but the new code is doing read/modify/write and keep this bit untouched. That's why ethernet stop to work. The patch is cleaning this bit when PHYCR value is composed. Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards. Fixes: 37d6265f2bfa ("net: phy: dp83867: refactor rgmii configuration") Signed-off-by: Michal Simek Reviewed-by: Grygorii Strashko --- drivers/net/phy/dp83867.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 08935d9c15f..0098997c0cd 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -65,6 +65,7 @@ #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 #define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14) #define DP83867_PHYCR_RESERVED_MASK BIT(11) +#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) #define DP83867_MDI_CROSSOVER 5 #define DP83867_MDI_CROSSOVER_MDIX 2 #define DP83867_PHYCTRL_SGMIIEN 0x0800 @@ -284,6 +285,9 @@ static int dp83867_config(struct phy_device *phydev) val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); + /* Do not force link good */ + val &= ~DP83867_PHYCR_FORCE_LINK_GOOD; + /* The code below checks if "port mirroring" N/A MODE4 has been * enabled during power on bootstrap. * -- cgit v1.3.1 From 58ecd9ad0be3b0c4c3e278b718dada687f7e0d9d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 6 Feb 2020 14:36:46 +0100 Subject: net: zynq: Free allocated buffers in case of error Driver probe function is called again and again in case of error. Malloc space is getting full which is is reported by: Insufficient RAM for page table: 0x15000 > 0x14000. Please increase the size in get_page_table_size() ### ERROR ### Please RESET the board ### The patch is freeing allocated buffers on error path to avoid panic. Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 7f9dc3435bf..5f2f87d352c 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -661,8 +661,10 @@ static int zynq_gem_probe(struct udevice *dev) /* Align bd_space to MMU_SECTION_SHIFT */ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); - if (!bd_space) - return -ENOMEM; + if (!bd_space) { + ret = -ENOMEM; + goto err1; + } mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE, DCACHE_OFF); @@ -674,7 +676,7 @@ static int zynq_gem_probe(struct udevice *dev) ret = clk_get_by_name(dev, "tx_clk", &priv->clk); if (ret < 0) { dev_err(dev, "failed to get clock\n"); - return -EINVAL; + goto err1; } priv->bus = mdio_alloc(); @@ -684,9 +686,19 @@ static int zynq_gem_probe(struct udevice *dev) ret = mdio_register_seq(priv->bus, dev->seq); if (ret) - return ret; + goto err2; - return zynq_phy_init(dev); + ret = zynq_phy_init(dev); + if (ret) + goto err2; + + return ret; + +err2: + free(priv->rxbuffers); +err1: + free(priv->tx_bd); + return ret; } static int zynq_gem_remove(struct udevice *dev) -- cgit v1.3.1