From fc8895035b0d00d22d4edc6b327cb1805baa5872 Mon Sep 17 00:00:00 2001 From: Oleg Kosheliev Date: Tue, 8 Oct 2013 15:49:55 +0300 Subject: ARMV7: OMAP4: Add struct for twl603x data The data struct is used to support different PMIC chip types. It contains the chip type and the data (e.g. registers addresses, adc multiplier) which is different for twl6030 and twl6032. Replaced some hardcoded values with the structure vars. Based on Balaji T K patches for TI u-boot. Signed-off-by: Oleg Kosheliev --- drivers/power/twl6030.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c index 0858b60e06d..6bf1a332864 100644 --- a/drivers/power/twl6030.c +++ b/drivers/power/twl6030.c @@ -9,6 +9,17 @@ #include +static struct twl6030_data *twl; + +static struct twl6030_data twl6030_info = { + .chip_type = chip_TWL6030, + .adc_rbase = GPCH0_LSB, + .adc_ctrl = CTRL_P2, + .adc_enable = CTRL_P2_SP2, + .vbat_mult = TWL6030_VBAT_MULT, + .vbat_shift = TWL6030_VBAT_SHIFT, +}; + static int twl6030_gpadc_read_channel(u8 channel_no) { u8 lsb = 0; @@ -16,12 +27,12 @@ static int twl6030_gpadc_read_channel(u8 channel_no) int ret = 0; ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, - GPCH0_LSB + channel_no * 2, &lsb); + twl->adc_rbase + channel_no * 2, &lsb); if (ret) return ret; ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, - GPCH0_MSB + channel_no * 2, &msb); + twl->adc_rbase + 1 + channel_no * 2, &msb); if (ret) return ret; @@ -33,7 +44,8 @@ static int twl6030_gpadc_sw2_trigger(void) u8 val; int ret = 0; - ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2, CTRL_P2_SP2); + ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, + twl->adc_ctrl, twl->adc_enable); if (ret) return ret; @@ -41,7 +53,8 @@ static int twl6030_gpadc_sw2_trigger(void) val = CTRL_P2_BUSY; while (!((val & CTRL_P2_EOCP2) && (!(val & CTRL_P2_BUSY)))) { - ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, CTRL_P2, &val); + ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, + twl->adc_ctrl, &val); if (ret) return ret; udelay(1000); @@ -116,7 +129,7 @@ int twl6030_get_battery_voltage(void) printf("Failed to read battery voltage\n"); return ret; } - battery_volt = (battery_volt * 25 * 1000) >> (10 + 2); + battery_volt = (battery_volt * twl->vbat_mult) >> twl->vbat_shift; printf("Battery Voltage: %d mV\n", battery_volt); return battery_volt; @@ -128,6 +141,8 @@ void twl6030_init_battery_charging(void) int battery_volt = 0; int ret = 0; + twl = &twl6030_info; + /* Enable VBAT measurement */ twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS); -- cgit v1.2.3 From 340e6c830053846d48ba97a73adfac3f5cadfd7e Mon Sep 17 00:00:00 2001 From: Oleg Kosheliev Date: Tue, 8 Oct 2013 15:49:56 +0300 Subject: ARMV7: OMAP4: Add twl6032 support Added chip type detection and twl6032 support in the battery control and charge functions. Based on Balaji T K patches for TI u-boot. Signed-off-by: Oleg Kosheliev --- drivers/power/twl6030.c | 54 +++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c index 6bf1a332864..a1c6663a2e3 100644 --- a/drivers/power/twl6030.c +++ b/drivers/power/twl6030.c @@ -20,6 +20,15 @@ static struct twl6030_data twl6030_info = { .vbat_shift = TWL6030_VBAT_SHIFT, }; +static struct twl6030_data twl6032_info = { + .chip_type = chip_TWL6032, + .adc_rbase = TWL6032_GPCH0_LSB, + .adc_ctrl = TWL6032_CTRL_P1, + .adc_enable = CTRL_P1_SP1, + .vbat_mult = TWL6032_VBAT_MULT, + .vbat_shift = TWL6032_VBAT_SHIFT, +}; + static int twl6030_gpadc_read_channel(u8 channel_no) { u8 lsb = 0; @@ -115,6 +124,18 @@ int twl6030_get_battery_voltage(void) { int battery_volt = 0; int ret = 0; + u8 vbatch; + + if (twl->chip_type == chip_TWL6030) { + vbatch = TWL6030_GPADC_VBAT_CHNL; + } else { + ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, + TWL6032_GPSELECT_ISB, + TWL6032_GPADC_VBAT_CHNL); + if (ret) + return ret; + vbatch = 0; + } /* Start GPADC SW conversion */ ret = twl6030_gpadc_sw2_trigger(); @@ -124,7 +145,7 @@ int twl6030_get_battery_voltage(void) } /* measure Vbat voltage */ - battery_volt = twl6030_gpadc_read_channel(7); + battery_volt = twl6030_gpadc_read_channel(vbatch); if (battery_volt < 0) { printf("Failed to read battery voltage\n"); return ret; @@ -137,14 +158,35 @@ int twl6030_get_battery_voltage(void) void twl6030_init_battery_charging(void) { - u8 stat1 = 0; + u8 val = 0; int battery_volt = 0; int ret = 0; - twl = &twl6030_info; + ret = twl6030_i2c_read_u8(TWL6030_CHIP_USB, USB_PRODUCT_ID_LSB, &val); + if (ret) { + puts("twl6030_init_battery_charging(): could not determine chip!\n"); + return; + } + if (val == 0x30) { + twl = &twl6030_info; + } else if (val == 0x32) { + twl = &twl6032_info; + } else { + puts("twl6030_init_battery_charging(): unsupported chip type\n"); + return; + } /* Enable VBAT measurement */ - twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS); + if (twl->chip_type == chip_TWL6030) { + twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS); + twl6030_i2c_write_u8(TWL6030_CHIP_ADC, + TWL6030_GPADC_CTRL, + GPADC_CTRL_SCALER_DIV4); + } else { + twl6030_i2c_write_u8(TWL6030_CHIP_ADC, + TWL6032_GPADC_CTRL2, + GPADC_CTRL2_CH18_SCALER_EN); + } /* Enable GPADC module */ ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TOGGLE1, FGS | GPADCS); @@ -161,10 +203,10 @@ void twl6030_init_battery_charging(void) printf("Main battery voltage too low!\n"); /* Check for the presence of USB charger */ - twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &stat1); + twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &val); /* check for battery presence indirectly via Fuel gauge */ - if ((stat1 & VBUS_DET) && (battery_volt < 3300)) + if ((val & VBUS_DET) && (battery_volt < 3300)) twl6030_start_usb_charging(); return; -- cgit v1.2.3 From d73763a4fbc741b3faee43d0a668dd220a81d772 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 11 Nov 2013 16:56:37 +0200 Subject: ahci: Error out with message on malloc() failure If malloc() fails, we don't want to continue in ahci_init() and ahci_init_one(). Also print a more informative error message on malloc() failures. CC: Rob Herring Signed-off-by: Roger Quadros --- drivers/block/ahci.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 0daad364d72..e24d634425f 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -379,6 +379,11 @@ static int ahci_init_one(pci_dev_t pdev) int rc; probe_ent = malloc(sizeof(struct ahci_probe_ent)); + if (!probe_ent) { + printf("%s: No memory for probe_ent\n", __func__); + return -ENOMEM; + } + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); probe_ent->dev = pdev; @@ -503,7 +508,7 @@ static int ahci_port_start(u8 port) mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); if (!mem) { free(pp); - printf("No mem for table!\n"); + printf("%s: No mem for table!\n", __func__); return -ENOMEM; } @@ -638,8 +643,10 @@ static int ata_scsiop_inquiry(ccb *pccb) /* Read id from sata */ port = pccb->target; tmpid = malloc(ATA_ID_WORDS * 2); - if (!tmpid) + if (!tmpid) { + printf("%s: No memory for tmpid\n", __func__); return -ENOMEM; + } if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) { @@ -889,6 +896,11 @@ int ahci_init(u32 base) u32 linkmap; probe_ent = malloc(sizeof(struct ahci_probe_ent)); + if (!probe_ent) { + printf("%s: No memory for probe_ent\n", __func__); + return -ENOMEM; + } + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); probe_ent->host_flags = ATA_FLAG_SATA -- cgit v1.2.3 From 2faf5fb82ed6f3df07635cddca0a2a54e3ef74ef Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 11 Nov 2013 16:56:38 +0200 Subject: ahci: Fix cache align error messages Align the ATA ID buffer to the cache-line boundary. This gets rid of the below error mesages on ARM v7 platforms. scanning bus for devices... ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xfee48818 CC: Aneesh V Signed-off-by: Roger Quadros --- drivers/block/ahci.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index e24d634425f..e64df4f98d6 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -623,7 +623,7 @@ static int ata_scsiop_inquiry(ccb *pccb) 95 - 4, }; u8 fis[20]; - u16 *tmpid; + ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); u8 port; /* Clean ccb data buffer */ @@ -642,16 +642,10 @@ static int ata_scsiop_inquiry(ccb *pccb) /* Read id from sata */ port = pccb->target; - tmpid = malloc(ATA_ID_WORDS * 2); - if (!tmpid) { - printf("%s: No memory for tmpid\n", __func__); - return -ENOMEM; - } if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) { debug("scsi_ahci: SCSI inquiry command failure.\n"); - free(tmpid); return -EIO; } -- cgit v1.2.3 From 74007b8519f4cfb4aa0f0af397ca71dde04172bf Mon Sep 17 00:00:00 2001 From: Vladimir Koutny Date: Thu, 28 Nov 2013 10:38:40 +0100 Subject: am335x: cpsw: optimize cpsw_recv to increase network performance In 48ec5291, only TX path was optimized; this does the same also for RX path. This results in huge increase of TFTP throughput on custom am3352 board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer timeouts. Signed-off-by: Vladimir Koutny Cc: Mugunthan V N Cc: Joe Hershberger Cc: Tom Rini --- drivers/net/cpsw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 39240d96621..50167aab63a 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -914,7 +914,7 @@ static int cpsw_recv(struct eth_device *dev) void *buffer; int len; - cpsw_update_link(priv); + cpsw_check_link(priv); while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) { invalidate_dcache_range((unsigned long)buffer, -- cgit v1.2.3 From 835a5559bd093627baf9a90e82cd626ec59fade9 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 2 Dec 2013 15:47:43 +0200 Subject: usb: ehci-omap: Reset the USB Host OMAP module In commit bb1f327 we removed the UHH reset to fix NFS root (over usb ethernet) problems with Beagleboard (3530 ES1.0). However, this seems to cause USB detection problems for Pandaboard, about (3/8). On further investigation, it seems that doing the UHH reset is not the cause of the original Beagleboard problem, but in the way the reset was done. This patch adds proper UHH RESET mechanism for OMAP3 and OMAP4/5 based on the UHH_REVISION register. This should fix the Beagleboard NFS problem as well as the Pandaboard USB detection problem. Reported-by: Tomi Valkeinen CC: Stefan Roese Reviewed-by: Stefan Roese Signed-off-by: Roger Quadros --- drivers/usb/host/ehci-omap.c | 57 ++++++++++++++++++++++++++++++++------------ 1 file changed, 42 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index c4ce4870875..1b215c25f68 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -28,21 +28,48 @@ static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE; static int omap_uhh_reset(void) { -/* - * Soft resetting the UHH module causes instability issues on - * all OMAPs so we just avoid it. - * - * See OMAP36xx Errata - * i571: USB host EHCI may stall when entering smart-standby mode - * i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock - * - * On OMAP4/5, soft-resetting the UHH module will put it into - * Smart-Idle mode and lead to a deadlock. - * - * On OMAP3, this doesn't seem to be the case but still instabilities - * are observed on beagle (3530 ES1.0) if soft-reset is used. - * e.g. NFS root failures with Linux kernel. - */ + int timeout = 0; + u32 rev; + + rev = readl(&uhh->rev); + + /* Soft RESET */ + writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc); + + switch (rev) { + case OMAP_USBHS_REV1: + /* Wait for soft RESET to complete */ + while (!(readl(&uhh->syss) & 0x1)) { + if (timeout > 100) { + printf("%s: RESET timeout\n", __func__); + return -1; + } + udelay(10); + timeout++; + } + + /* Set No-Idle, No-Standby */ + writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc); + break; + + default: /* Rev. 2 onwards */ + + udelay(2); /* Need to wait before accessing SYSCONFIG back */ + + /* Wait for soft RESET to complete */ + while ((readl(&uhh->sysc) & 0x1)) { + if (timeout > 100) { + printf("%s: RESET timeout\n", __func__); + return -1; + } + udelay(10); + timeout++; + } + + writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc); + break; + } + return 0; } -- cgit v1.2.3