From bd6eb5ddd715e7441d804c67f434418e172a1423 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sat, 11 Nov 2023 11:46:18 +0100 Subject: clk: stm32f: fix setting of division factor for LCD_CLK The value to be written to the register must be appropriately shifted, as is correctly done in other parts of the code. Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock") Signed-off-by: Dario Binacchi Reviewed-by: Patrice Chotard --- drivers/clk/stm32/clk-stm32f.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index ed7660196ef..4c186419335 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -530,7 +530,8 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate) /* set pll_saidivr with found value */ clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, - pllsaidivr_table[i]); + pllsaidivr_table[i] << + RCC_DCKCFGR_PLLSAIDIVR_SHIFT); return rate; } -- cgit v1.2.3 From 767ca6d6827281744641180e4ac2921f5b828893 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sat, 11 Nov 2023 11:46:19 +0100 Subject: clk: stm32f: fix setting of LCD clock Set pllsaidivr only if the PLLSAIR output frequency is an exact multiple of the pixel clock rate. Otherwise, we search through all combinations of pllsaidivr * pllsair and use the one which gives the rate closest to requested one. Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock") Signed-off-by: Dario Binacchi Reviewed-by: Patrice Chotard --- drivers/clk/stm32/clk-stm32f.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index 4c186419335..d68c75ed201 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -522,18 +522,20 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate) /* get the current PLLSAIR output freq */ pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR); - best_div = pllsair_rate / rate; - - /* look into pllsaidivr_table if this divider is available*/ - for (i = 0 ; i < sizeof(pllsaidivr_table); i++) - if (best_div == pllsaidivr_table[i]) { - /* set pll_saidivr with found value */ - clrsetbits_le32(®s->dckcfgr, - RCC_DCKCFGR_PLLSAIDIVR_MASK, - pllsaidivr_table[i] << - RCC_DCKCFGR_PLLSAIDIVR_SHIFT); - return rate; - } + if ((pllsair_rate % rate) == 0) { + best_div = pllsair_rate / rate; + + /* look into pllsaidivr_table if this divider is available */ + for (i = 0 ; i < sizeof(pllsaidivr_table); i++) + if (best_div == pllsaidivr_table[i]) { + /* set pll_saidivr with found value */ + clrsetbits_le32(®s->dckcfgr, + RCC_DCKCFGR_PLLSAIDIVR_MASK, + pllsaidivr_table[i] << + RCC_DCKCFGR_PLLSAIDIVR_SHIFT); + return rate; + } + } /* * As no pllsaidivr value is suitable to obtain requested freq, -- cgit v1.2.3 From 47256b040c61a08de6037954e15d4cba1d2a04a9 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 11 Dec 2023 23:05:55 +0100 Subject: board: stm32f469-disco: add support to display Add support to Orise Tech OTM8009A display on stm32f469-disco board. It was necessary to retrieve the framebuffer address from the device tree because the address returned by the video-uclass driver pointed to a memory area that was not usable. Signed-off-by: Dario Binacchi Reviewed-by: Patrice Chotard --- drivers/video/stm32/stm32_ltdc.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'drivers') diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index 6fd90e33919..4f60ba8ebee 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -495,6 +495,33 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr) setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN); } +#if IS_ENABLED(CONFIG_TARGET_STM32F469_DISCOVERY) +static int stm32_ltdc_alloc_fb(struct udevice *dev) +{ + u32 sdram_size = gd->ram_size; + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + phys_addr_t cpu; + dma_addr_t bus; + u64 dma_size; + int ret; + + ret = dev_get_dma_range(dev, &cpu, &bus, &dma_size); + if (ret) { + dev_err(dev, "failed to get dma address\n"); + return ret; + } + + uc_plat->base = bus + sdram_size - ALIGN(uc_plat->size, uc_plat->align); + return 0; +} +#else +static inline int stm32_ltdc_alloc_fb(struct udevice *dev) +{ + /* Delegate framebuffer allocation to video-uclass */ + return 0; +} +#endif + static int stm32_ltdc_probe(struct udevice *dev) { struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); @@ -605,6 +632,10 @@ static int stm32_ltdc_probe(struct udevice *dev) priv->crop_h = timings.vactive.typ; priv->alpha = 0xFF; + ret = stm32_ltdc_alloc_fb(dev); + if (ret) + return ret; + dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n", timings.hactive.typ, timings.vactive.typ, VNBITS(priv->l2bpp), uc_plat->base); -- cgit v1.2.3