From 6d87b1572f854435a68f868624f91673c91985e1 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 1 Feb 2023 02:55:53 -0700 Subject: arm64: zynqmp: Add missing ZYNQMP_FIRMWARE dependencies There are missing Kconfig dependencies in the code which is using firmware interface. The commit 71efd45a5fc7 ("arm64: zynqmp: Change firmware dependency") add option to also disable ZYNQMP_FIRMWARE. But not all Kconfig dependencies were properly described and also sdhci and gem drivers didn't protect the code properly. So, add the missing ZYNQMP_FIRMWARE dependencies. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230201095553.11219-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/clk/Kconfig | 4 ++-- drivers/fpga/Kconfig | 2 +- drivers/mmc/zynq_sdhci.c | 4 ++-- drivers/net/zynq_gem.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 09aa97ee8c0..42280cbf83a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -185,7 +185,7 @@ config CLK_VERSACLOCK config CLK_VERSAL bool "Enable clock driver support for Versal" depends on (ARCH_VERSAL || ARCH_VERSAL_NET) - select ZYNQMP_FIRMWARE + imply ZYNQMP_FIRMWARE help This clock driver adds support for clock realted settings for Versal platform. @@ -219,7 +219,7 @@ config CLK_ZYNQ config CLK_ZYNQMP bool "Enable clock driver support for ZynqMP" depends on ARCH_ZYNQMP - select ZYNQMP_FIRMWARE + imply ZYNQMP_FIRMWARE help This clock driver adds support for clock realted settings for ZynqMP platform. diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 61490d6d8de..62cb77b098c 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -75,7 +75,7 @@ config FPGA_XILINX config FPGA_ZYNQMPPL bool "Enable Xilinx FPGA driver for ZynqMP" - depends on FPGA_XILINX + depends on FPGA_XILINX && ZYNQMP_FIRMWARE help Enable FPGA driver for loading bitstream in BIT and BIN format on Xilinx Zynq UltraScale+ (ZynqMP) device. diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 91e309d2752..8b559d8a7ab 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -988,7 +988,7 @@ static const struct sdhci_ops arasan_ops = { }; #endif -#if defined(CONFIG_ARCH_ZYNQMP) +#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE) static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv, struct udevice *dev) { @@ -1090,7 +1090,7 @@ static int arasan_sdhci_probe(struct udevice *dev) host = priv->host; -#if defined(CONFIG_ARCH_ZYNQMP) +#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE) if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) { ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_SD_CONFIG); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index cc49788012f..211b2c6e556 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -738,7 +738,7 @@ static int gem_zynqmp_set_dynamic_config(struct udevice *dev) u32 pm_info[2]; int ret; - if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) { + if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) && IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { if (!zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_GEM_CONFIG)) { ret = ofnode_read_u32_array(dev_ofnode(dev), -- cgit v1.2.3 From 749cbcfeacd7063c83506ff5add037cd621fe451 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Tue, 14 Feb 2023 13:19:59 +0000 Subject: fpga: zynqmppl: fix fpga loads command for unencrypted use case When using the fpga loads command, the driver is passing the AES encryption key address is all cases. However, for the authenticated, but not encrypted use case, there is no AES encryption key, and this value is 0. When AES encryption is not used on the fpga bitstream, the pmufw assumes that the AES key address is a bitstream size value like what is used by the unsecure fpga load command. To fix the problem, this patch checks to see if the AES key address is zero. If the AES key address is zero, it means that AES is not being used on the bitstream and the bitstream size should be passed instead. Thus, matching the fpga load functionality. Signed-off-by: Neal Frager Acked-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230214131959.40298-1-neal.frager@amd.com Signed-off-by: Michal Simek --- drivers/fpga/zynqmppl.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index d1491da02c3..7b5128fe27a 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -332,10 +332,16 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize, buf_lo = lower_32_bits((ulong)buf); buf_hi = upper_32_bits((ulong)buf); - ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, + if ((u32)(uintptr_t)fpga_sec_info->userkey_addr) + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, buf_hi, - (u32)(uintptr_t)fpga_sec_info->userkey_addr, - flag, ret_payload); + (u32)(uintptr_t)fpga_sec_info->userkey_addr, + flag, ret_payload); + else + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, + buf_hi, (u32)bsize, + flag, ret_payload); + if (ret) puts("PL FPGA LOAD fail\n"); else -- cgit v1.2.3 From 4fffbc1108f3f5e2932cdefea8b5f831b46040c7 Mon Sep 17 00:00:00 2001 From: Jiajie Chen Date: Mon, 27 Feb 2023 23:09:39 +0800 Subject: spi: xilinx_spi: Fix spi reset It was incorrectly using an old priv->regs pointer, which was initialized to zero. SPI resets won't happen on first call. Signed-off-by: Jiajie Chen Link: https://lore.kernel.org/r/20230227150938.211820-1-c@jia.je Signed-off-by: Michal Simek --- drivers/spi/xilinx_spi.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 4e9115dafee..9e6255a172a 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -112,10 +112,9 @@ struct xilinx_spi_priv { static int xilinx_spi_probe(struct udevice *bus) { struct xilinx_spi_priv *priv = dev_get_priv(bus); - struct xilinx_spi_regs *regs = priv->regs; - - priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus); + struct xilinx_spi_regs *regs; + regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus); priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0); writel(SPISSR_RESET_VALUE, ®s->srr); -- cgit v1.2.3 From 437d77f16bf1a7791d74ec81ca4d669860c8b056 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 23 Feb 2023 22:07:06 -0700 Subject: mtd: nand: arasan: Remove hardcoded bbt option Bad block table option is hardcoded to read from flash with NAND_BBT_USE_FLASH option. This decision should be done based on DT property. Remove this hardcoding, to be able to use DT property. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230224050709.30014-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/mtd/nand/raw/arasan_nfc.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index 4621bfb03e3..ddb4cb1cbae 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -1248,7 +1248,6 @@ static int arasan_probe(struct udevice *dev) /* Buffer read/write routines */ nand_chip->read_buf = arasan_nand_read_buf; nand_chip->write_buf = arasan_nand_write_buf; - nand_chip->bbt_options = NAND_BBT_USE_FLASH; writel(0x0, &info->reg->cmd_reg); writel(0x0, &info->reg->pgm_reg); -- cgit v1.2.3 From 1e01769a2d24863247331205cf08bc504005b593 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Thu, 23 Feb 2023 22:07:07 -0700 Subject: mtd: nand: arasan: Set ofnode value Ofnode value is not set, so all the DT properties are not being read and due to this default values are being used. Find nand node and set chip->flash_node value. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230224050709.30014-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/mtd/nand/raw/arasan_nfc.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index ddb4cb1cbae..99e2681c14b 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -1230,12 +1230,16 @@ static int arasan_probe(struct udevice *dev) struct nand_drv *info = &arasan->nand_ctrl; struct nand_config *nand = &info->config; struct mtd_info *mtd; + ofnode child; int err = -1; info->reg = (struct nand_regs *)dev_read_addr(dev); mtd = nand_to_mtd(nand_chip); nand_set_controller_data(nand_chip, &arasan->nand_ctrl); + ofnode_for_each_subnode(child, dev_ofnode(dev)) + nand_set_flash_node(nand_chip, child); + #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE nand_chip->options |= NAND_NO_SUBPAGE_WRITE; #endif -- cgit v1.2.3 From cc24fd78593896ba038c71eb356b32fdaa1cd690 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 1 Mar 2023 03:33:33 -0700 Subject: xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write Add missing prototype to fix the sparse warning, warning: no previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230301103334.1455-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/mmc/zynq_sdhci.c | 1 + drivers/spi/zynqmp_gqspi.c | 5 +++++ 2 files changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 8b559d8a7ab..9dc310663f2 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -14,6 +14,7 @@ #include "mmc_private.h" #include #include +#include #include #include #include diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 335b458cb90..c4aee279aa4 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -183,6 +183,11 @@ struct zynqmp_qspi_priv { const struct spi_mem_op *op; }; +__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) +{ + return 0; +} + static int zynqmp_qspi_of_to_plat(struct udevice *bus) { struct zynqmp_qspi_plat *plat = dev_get_plat(bus); -- cgit v1.2.3