From cfd50dfb729ab2268a5a44eaeea00ffa557919cd Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 7 Sep 2021 17:16:58 -0500 Subject: clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna Signed-off-by: Dave Gerlach --- drivers/clk/ti/clk-k3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index e921894e7a2..e04c57eff25 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -2,7 +2,7 @@ /* * Texas Instruments K3 clock driver * - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ * Tero Kristo */ @@ -112,7 +112,7 @@ static int ti_clk_probe(struct udevice *dev) map_physmem(ti_clk_data->clk.div.reg, 0, MAP_NOCACHE), ti_clk_data->clk.div.shift, ti_clk_data->clk.div.width, - 0); + ti_clk_data->clk.div.div_flags); break; case CLK_TYPE_MUX: name = ti_clk_data->clk.mux.name; -- cgit v1.2.3