From dd649f1d0031eb2b8b315794867ea9d1b028a06c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 31 Mar 2014 13:01:09 +0900 Subject: mtd: delete unused files Signed-off-by: Masahiro Yamada Cc: Scott Wood --- drivers/mtd/nand/diskonchip.c | 1780 ----------------------------------------- 1 file changed, 1780 deletions(-) delete mode 100644 drivers/mtd/nand/diskonchip.c (limited to 'drivers') diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c deleted file mode 100644 index 4cd741ebbb4..00000000000 --- a/drivers/mtd/nand/diskonchip.c +++ /dev/null @@ -1,1780 +0,0 @@ -/* - * drivers/mtd/nand/diskonchip.c - * - * (C) 2003 Red Hat, Inc. - * (C) 2004 Dan Brown - * (C) 2004 Kalev Lember - * - * Author: David Woodhouse - * Additional Diskonchip 2000 and Millennium support by Dan Brown - * Diskonchip Millennium Plus support by Kalev Lember - * - * Error correction code lifted from the old docecc code - * Author: Fabrice Bellard (fabrice.bellard@netgem.com) - * Copyright (C) 2000 Netgem S.A. - * converted to the generic Reed-Solomon library by Thomas Gleixner - * - * Interface to generic NAND code for M-Systems DiskOnChip devices - */ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/* Where to look for the devices? */ -#ifndef CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS -#define CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS 0 -#endif - -static unsigned long __initdata doc_locations[] = { -#if defined (__alpha__) || defined(__i386__) || defined(__x86_64__) -#ifdef CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH - 0xfffc8000, 0xfffca000, 0xfffcc000, 0xfffce000, - 0xfffd0000, 0xfffd2000, 0xfffd4000, 0xfffd6000, - 0xfffd8000, 0xfffda000, 0xfffdc000, 0xfffde000, - 0xfffe0000, 0xfffe2000, 0xfffe4000, 0xfffe6000, - 0xfffe8000, 0xfffea000, 0xfffec000, 0xfffee000, -#else /* CONFIG_MTD_DOCPROBE_HIGH */ - 0xc8000, 0xca000, 0xcc000, 0xce000, - 0xd0000, 0xd2000, 0xd4000, 0xd6000, - 0xd8000, 0xda000, 0xdc000, 0xde000, - 0xe0000, 0xe2000, 0xe4000, 0xe6000, - 0xe8000, 0xea000, 0xec000, 0xee000, -#endif /* CONFIG_MTD_DOCPROBE_HIGH */ -#else -#warning Unknown architecture for DiskOnChip. No default probe locations defined -#endif - 0xffffffff }; - -static struct mtd_info *doclist = NULL; - -struct doc_priv { - void __iomem *virtadr; - unsigned long physadr; - u_char ChipID; - u_char CDSNControl; - int chips_per_floor; /* The number of chips detected on each floor */ - int curfloor; - int curchip; - int mh0_page; - int mh1_page; - struct mtd_info *nextdoc; -}; - -/* This is the syndrome computed by the HW ecc generator upon reading an empty - page, one with all 0xff for data and stored ecc code. */ -static u_char empty_read_syndrome[6] = { 0x26, 0xff, 0x6d, 0x47, 0x73, 0x7a }; - -/* This is the ecc value computed by the HW ecc generator upon writing an empty - page, one with all 0xff for data. */ -static u_char empty_write_ecc[6] = { 0x4b, 0x00, 0xe2, 0x0e, 0x93, 0xf7 }; - -#define INFTL_BBT_RESERVED_BLOCKS 4 - -#define DoC_is_MillenniumPlus(doc) ((doc)->ChipID == DOC_ChipID_DocMilPlus16 || (doc)->ChipID == DOC_ChipID_DocMilPlus32) -#define DoC_is_Millennium(doc) ((doc)->ChipID == DOC_ChipID_DocMil) -#define DoC_is_2000(doc) ((doc)->ChipID == DOC_ChipID_Doc2k) - -static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd, - unsigned int bitmask); -static void doc200x_select_chip(struct mtd_info *mtd, int chip); - -static int debug = 0; -module_param(debug, int, 0); - -static int try_dword = 1; -module_param(try_dword, int, 0); - -static int no_ecc_failures = 0; -module_param(no_ecc_failures, int, 0); - -static int no_autopart = 0; -module_param(no_autopart, int, 0); - -static int show_firmware_partition = 0; -module_param(show_firmware_partition, int, 0); - -#ifdef CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE -static int inftl_bbt_write = 1; -#else -static int inftl_bbt_write = 0; -#endif -module_param(inftl_bbt_write, int, 0); - -static unsigned long doc_config_location = CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS; -module_param(doc_config_location, ulong, 0); -MODULE_PARM_DESC(doc_config_location, "Physical memory address at which to probe for DiskOnChip"); - -/* Sector size for HW ECC */ -#define SECTOR_SIZE 512 -/* The sector bytes are packed into NB_DATA 10 bit words */ -#define NB_DATA (((SECTOR_SIZE + 1) * 8 + 6) / 10) -/* Number of roots */ -#define NROOTS 4 -/* First consective root */ -#define FCR 510 -/* Number of symbols */ -#define NN 1023 - -/* the Reed Solomon control structure */ -static struct rs_control *rs_decoder; - -/* - * The HW decoder in the DoC ASIC's provides us a error syndrome, - * which we must convert to a standard syndrome usable by the generic - * Reed-Solomon library code. - * - * Fabrice Bellard figured this out in the old docecc code. I added - * some comments, improved a minor bit and converted it to make use - * of the generic Reed-Solomon libary. tglx - */ -static int doc_ecc_decode(struct rs_control *rs, uint8_t *data, uint8_t *ecc) -{ - int i, j, nerr, errpos[8]; - uint8_t parity; - uint16_t ds[4], s[5], tmp, errval[8], syn[4]; - - /* Convert the ecc bytes into words */ - ds[0] = ((ecc[4] & 0xff) >> 0) | ((ecc[5] & 0x03) << 8); - ds[1] = ((ecc[5] & 0xfc) >> 2) | ((ecc[2] & 0x0f) << 6); - ds[2] = ((ecc[2] & 0xf0) >> 4) | ((ecc[3] & 0x3f) << 4); - ds[3] = ((ecc[3] & 0xc0) >> 6) | ((ecc[0] & 0xff) << 2); - parity = ecc[1]; - - /* Initialize the syndrome buffer */ - for (i = 0; i < NROOTS; i++) - s[i] = ds[0]; - /* - * Evaluate - * s[i] = ds[3]x^3 + ds[2]x^2 + ds[1]x^1 + ds[0] - * where x = alpha^(FCR + i) - */ - for (j = 1; j < NROOTS; j++) { - if (ds[j] == 0) - continue; - tmp = rs->index_of[ds[j]]; - for (i = 0; i < NROOTS; i++) - s[i] ^= rs->alpha_to[rs_modnn(rs, tmp + (FCR + i) * j)]; - } - - /* Calc s[i] = s[i] / alpha^(v + i) */ - for (i = 0; i < NROOTS; i++) { - if (syn[i]) - syn[i] = rs_modnn(rs, rs->index_of[s[i]] + (NN - FCR - i)); - } - /* Call the decoder library */ - nerr = decode_rs16(rs, NULL, NULL, 1019, syn, 0, errpos, 0, errval); - - /* Incorrectable errors ? */ - if (nerr < 0) - return nerr; - - /* - * Correct the errors. The bitpositions are a bit of magic, - * but they are given by the design of the de/encoder circuit - * in the DoC ASIC's. - */ - for (i = 0; i < nerr; i++) { - int index, bitpos, pos = 1015 - errpos[i]; - uint8_t val; - if (pos >= NB_DATA && pos < 1019) - continue; - if (pos < NB_DATA) { - /* extract bit position (MSB first) */ - pos = 10 * (NB_DATA - 1 - pos) - 6; - /* now correct the following 10 bits. At most two bytes - can be modified since pos is even */ - index = (pos >> 3) ^ 1; - bitpos = pos & 7; - if ((index >= 0 && index < SECTOR_SIZE) || index == (SECTOR_SIZE + 1)) { - val = (uint8_t) (errval[i] >> (2 + bitpos)); - parity ^= val; - if (index < SECTOR_SIZE) - data[index] ^= val; - } - index = ((pos >> 3) + 1) ^ 1; - bitpos = (bitpos + 10) & 7; - if (bitpos == 0) - bitpos = 8; - if ((index >= 0 && index < SECTOR_SIZE) || index == (SECTOR_SIZE + 1)) { - val = (uint8_t) (errval[i] << (8 - bitpos)); - parity ^= val; - if (index < SECTOR_SIZE) - data[index] ^= val; - } - } - } - /* If the parity is wrong, no rescue possible */ - return parity ? -EBADMSG : nerr; -} - -static void DoC_Delay(struct doc_priv *doc, unsigned short cycles) -{ - volatile char dummy; - int i; - - for (i = 0; i < cycles; i++) { - if (DoC_is_Millennium(doc)) - dummy = ReadDOC(doc->virtadr, NOP); - else if (DoC_is_MillenniumPlus(doc)) - dummy = ReadDOC(doc->virtadr, Mplus_NOP); - else - dummy = ReadDOC(doc->virtadr, DOCStatus); - } - -} - -#define CDSN_CTRL_FR_B_MASK (CDSN_CTRL_FR_B0 | CDSN_CTRL_FR_B1) - -/* DOC_WaitReady: Wait for RDY line to be asserted by the flash chip */ -static int _DoC_WaitReady(struct doc_priv *doc) -{ - void __iomem *docptr = doc->virtadr; - unsigned long timeo = jiffies + (HZ * 10); - - if (debug) - printk("_DoC_WaitReady...\n"); - /* Out-of-line routine to wait for chip response */ - if (DoC_is_MillenniumPlus(doc)) { - while ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) { - if (time_after(jiffies, timeo)) { - printk("_DoC_WaitReady timed out.\n"); - return -EIO; - } - udelay(1); - cond_resched(); - } - } else { - while (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) { - if (time_after(jiffies, timeo)) { - printk("_DoC_WaitReady timed out.\n"); - return -EIO; - } - udelay(1); - cond_resched(); - } - } - - return 0; -} - -static inline int DoC_WaitReady(struct doc_priv *doc) -{ - void __iomem *docptr = doc->virtadr; - int ret = 0; - - if (DoC_is_MillenniumPlus(doc)) { - DoC_Delay(doc, 4); - - if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) - /* Call the out-of-line routine to wait */ - ret = _DoC_WaitReady(doc); - } else { - DoC_Delay(doc, 4); - - if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) - /* Call the out-of-line routine to wait */ - ret = _DoC_WaitReady(doc); - DoC_Delay(doc, 2); - } - - if (debug) - printk("DoC_WaitReady OK\n"); - return ret; -} - -static void doc2000_write_byte(struct mtd_info *mtd, u_char datum) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - if (debug) - printk("write_byte %02x\n", datum); - WriteDOC(datum, docptr, CDSNSlowIO); - WriteDOC(datum, docptr, 2k_CDSN_IO); -} - -static u_char doc2000_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - u_char ret; - - ReadDOC(docptr, CDSNSlowIO); - DoC_Delay(doc, 2); - ret = ReadDOC(docptr, 2k_CDSN_IO); - if (debug) - printk("read_byte returns %02x\n", ret); - return ret; -} - -static void doc2000_writebuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - if (debug) - printk("writebuf of %d bytes: ", len); - for (i = 0; i < len; i++) { - WriteDOC_(buf[i], docptr, DoC_2k_CDSN_IO + i); - if (debug && i < 16) - printk("%02x ", buf[i]); - } - if (debug) - printk("\n"); -} - -static void doc2000_readbuf(struct mtd_info *mtd, u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - if (debug) - printk("readbuf of %d bytes: ", len); - - for (i = 0; i < len; i++) { - buf[i] = ReadDOC(docptr, 2k_CDSN_IO + i); - } -} - -static void doc2000_readbuf_dword(struct mtd_info *mtd, - u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - if (debug) - printk("readbuf_dword of %d bytes: ", len); - - if (unlikely((((unsigned long)buf) | len) & 3)) { - for (i = 0; i < len; i++) { - *(uint8_t *) (&buf[i]) = ReadDOC(docptr, 2k_CDSN_IO + i); - } - } else { - for (i = 0; i < len; i += 4) { - *(uint32_t*) (&buf[i]) = readl(docptr + DoC_2k_CDSN_IO + i); - } - } -} - -static int doc2000_verifybuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - for (i = 0; i < len; i++) - if (buf[i] != ReadDOC(docptr, 2k_CDSN_IO)) - return -EFAULT; - return 0; -} - -static uint16_t __init doc200x_ident_chip(struct mtd_info *mtd, int nr) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - uint16_t ret; - - doc200x_select_chip(mtd, nr); - doc200x_hwcontrol(mtd, NAND_CMD_READID, - NAND_CTRL_CLE | NAND_CTRL_CHANGE); - doc200x_hwcontrol(mtd, 0, NAND_CTRL_ALE | NAND_CTRL_CHANGE); - doc200x_hwcontrol(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - - /* We cant' use dev_ready here, but at least we wait for the - * command to complete - */ - udelay(50); - - ret = this->read_byte(mtd) << 8; - ret |= this->read_byte(mtd); - - if (doc->ChipID == DOC_ChipID_Doc2k && try_dword && !nr) { - /* First chip probe. See if we get same results by 32-bit access */ - union { - uint32_t dword; - uint8_t byte[4]; - } ident; - void __iomem *docptr = doc->virtadr; - - doc200x_hwcontrol(mtd, NAND_CMD_READID, - NAND_CTRL_CLE | NAND_CTRL_CHANGE); - doc200x_hwcontrol(mtd, 0, NAND_CTRL_ALE | NAND_CTRL_CHANGE); - doc200x_hwcontrol(mtd, NAND_CMD_NONE, - NAND_NCE | NAND_CTRL_CHANGE); - - udelay(50); - - ident.dword = readl(docptr + DoC_2k_CDSN_IO); - if (((ident.byte[0] << 8) | ident.byte[1]) == ret) { - printk(KERN_INFO "DiskOnChip 2000 responds to DWORD access\n"); - this->read_buf = &doc2000_readbuf_dword; - } - } - - return ret; -} - -static void __init doc2000_count_chips(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - uint16_t mfrid; - int i; - - /* Max 4 chips per floor on DiskOnChip 2000 */ - doc->chips_per_floor = 4; - - /* Find out what the first chip is */ - mfrid = doc200x_ident_chip(mtd, 0); - - /* Find how many chips in each floor. */ - for (i = 1; i < 4; i++) { - if (doc200x_ident_chip(mtd, i) != mfrid) - break; - } - doc->chips_per_floor = i; - printk(KERN_DEBUG "Detected %d chips per floor.\n", i); -} - -static int doc200x_wait(struct mtd_info *mtd, struct nand_chip *this) -{ - struct doc_priv *doc = this->priv; - - int status; - - DoC_WaitReady(doc); - this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); - DoC_WaitReady(doc); - status = (int)this->read_byte(mtd); - - return status; -} - -static void doc2001_write_byte(struct mtd_info *mtd, u_char datum) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - WriteDOC(datum, docptr, CDSNSlowIO); - WriteDOC(datum, docptr, Mil_CDSN_IO); - WriteDOC(datum, docptr, WritePipeTerm); -} - -static u_char doc2001_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - /*ReadDOC(docptr, CDSNSlowIO); */ - /* 11.4.5 -- delay twice to allow extended length cycle */ - DoC_Delay(doc, 2); - ReadDOC(docptr, ReadPipeInit); - /*return ReadDOC(docptr, Mil_CDSN_IO); */ - return ReadDOC(docptr, LastDataRead); -} - -static void doc2001_writebuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - for (i = 0; i < len; i++) - WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i); - /* Terminate write pipeline */ - WriteDOC(0x00, docptr, WritePipeTerm); -} - -static void doc2001_readbuf(struct mtd_info *mtd, u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - /* Start read pipeline */ - ReadDOC(docptr, ReadPipeInit); - - for (i = 0; i < len - 1; i++) - buf[i] = ReadDOC(docptr, Mil_CDSN_IO + (i & 0xff)); - - /* Terminate read pipeline */ - buf[i] = ReadDOC(docptr, LastDataRead); -} - -static int doc2001_verifybuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - /* Start read pipeline */ - ReadDOC(docptr, ReadPipeInit); - - for (i = 0; i < len - 1; i++) - if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) { - ReadDOC(docptr, LastDataRead); - return i; - } - if (buf[i] != ReadDOC(docptr, LastDataRead)) - return i; - return 0; -} - -static u_char doc2001plus_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - u_char ret; - - ReadDOC(docptr, Mplus_ReadPipeInit); - ReadDOC(docptr, Mplus_ReadPipeInit); - ret = ReadDOC(docptr, Mplus_LastDataRead); - if (debug) - printk("read_byte returns %02x\n", ret); - return ret; -} - -static void doc2001plus_writebuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - if (debug) - printk("writebuf of %d bytes: ", len); - for (i = 0; i < len; i++) { - WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i); - if (debug && i < 16) - printk("%02x ", buf[i]); - } - if (debug) - printk("\n"); -} - -static void doc2001plus_readbuf(struct mtd_info *mtd, u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - if (debug) - printk("readbuf of %d bytes: ", len); - - /* Start read pipeline */ - ReadDOC(docptr, Mplus_ReadPipeInit); - ReadDOC(docptr, Mplus_ReadPipeInit); - - for (i = 0; i < len - 2; i++) { - buf[i] = ReadDOC(docptr, Mil_CDSN_IO); - if (debug && i < 16) - printk("%02x ", buf[i]); - } - - /* Terminate read pipeline */ - buf[len - 2] = ReadDOC(docptr, Mplus_LastDataRead); - if (debug && i < 16) - printk("%02x ", buf[len - 2]); - buf[len - 1] = ReadDOC(docptr, Mplus_LastDataRead); - if (debug && i < 16) - printk("%02x ", buf[len - 1]); - if (debug) - printk("\n"); -} - -static int doc2001plus_verifybuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - - if (debug) - printk("verifybuf of %d bytes: ", len); - - /* Start read pipeline */ - ReadDOC(docptr, Mplus_ReadPipeInit); - ReadDOC(docptr, Mplus_ReadPipeInit); - - for (i = 0; i < len - 2; i++) - if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) { - ReadDOC(docptr, Mplus_LastDataRead); - ReadDOC(docptr, Mplus_LastDataRead); - return i; - } - if (buf[len - 2] != ReadDOC(docptr, Mplus_LastDataRead)) - return len - 2; - if (buf[len - 1] != ReadDOC(docptr, Mplus_LastDataRead)) - return len - 1; - return 0; -} - -static void doc2001plus_select_chip(struct mtd_info *mtd, int chip) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int floor = 0; - - if (debug) - printk("select chip (%d)\n", chip); - - if (chip == -1) { - /* Disable flash internally */ - WriteDOC(0, docptr, Mplus_FlashSelect); - return; - } - - floor = chip / doc->chips_per_floor; - chip -= (floor * doc->chips_per_floor); - - /* Assert ChipEnable and deassert WriteProtect */ - WriteDOC((DOC_FLASH_CE), docptr, Mplus_FlashSelect); - this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); - - doc->curchip = chip; - doc->curfloor = floor; -} - -static void doc200x_select_chip(struct mtd_info *mtd, int chip) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int floor = 0; - - if (debug) - printk("select chip (%d)\n", chip); - - if (chip == -1) - return; - - floor = chip / doc->chips_per_floor; - chip -= (floor * doc->chips_per_floor); - - /* 11.4.4 -- deassert CE before changing chip */ - doc200x_hwcontrol(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); - - WriteDOC(floor, docptr, FloorSelect); - WriteDOC(chip, docptr, CDSNDeviceSelect); - - doc200x_hwcontrol(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - - doc->curchip = chip; - doc->curfloor = floor; -} - -#define CDSN_CTRL_MSK (CDSN_CTRL_CE | CDSN_CTRL_CLE | CDSN_CTRL_ALE) - -static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - if (ctrl & NAND_CTRL_CHANGE) { - doc->CDSNControl &= ~CDSN_CTRL_MSK; - doc->CDSNControl |= ctrl & CDSN_CTRL_MSK; - if (debug) - printk("hwcontrol(%d): %02x\n", cmd, doc->CDSNControl); - WriteDOC(doc->CDSNControl, docptr, CDSNControl); - /* 11.4.3 -- 4 NOPs after CSDNControl write */ - DoC_Delay(doc, 4); - } - if (cmd != NAND_CMD_NONE) { - if (DoC_is_2000(doc)) - doc2000_write_byte(mtd, cmd); - else - doc2001_write_byte(mtd, cmd); - } -} - -static void doc2001plus_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - /* - * Must terminate write pipeline before sending any commands - * to the device. - */ - if (command == NAND_CMD_PAGEPROG) { - WriteDOC(0x00, docptr, Mplus_WritePipeTerm); - WriteDOC(0x00, docptr, Mplus_WritePipeTerm); - } - - /* - * Write out the command to the device. - */ - if (command == NAND_CMD_SEQIN) { - int readcmd; - - if (column >= mtd->writesize) { - /* OOB area */ - column -= mtd->writesize; - readcmd = NAND_CMD_READOOB; - } else if (column < 256) { - /* First 256 bytes --> READ0 */ - readcmd = NAND_CMD_READ0; - } else { - column -= 256; - readcmd = NAND_CMD_READ1; - } - WriteDOC(readcmd, docptr, Mplus_FlashCmd); - } - WriteDOC(command, docptr, Mplus_FlashCmd); - WriteDOC(0, docptr, Mplus_WritePipeTerm); - WriteDOC(0, docptr, Mplus_WritePipeTerm); - - if (column != -1 || page_addr != -1) { - /* Serially input address */ - if (column != -1) { - /* Adjust columns for 16 bit buswidth */ - if (this->options & NAND_BUSWIDTH_16) - column >>= 1; - WriteDOC(column, docptr, Mplus_FlashAddress); - } - if (page_addr != -1) { - WriteDOC((unsigned char)(page_addr & 0xff), docptr, Mplus_FlashAddress); - WriteDOC((unsigned char)((page_addr >> 8) & 0xff), docptr, Mplus_FlashAddress); - /* One more address cycle for higher density devices */ - if (this->chipsize & 0x0c000000) { - WriteDOC((unsigned char)((page_addr >> 16) & 0x0f), docptr, Mplus_FlashAddress); - printk("high density\n"); - } - } - WriteDOC(0, docptr, Mplus_WritePipeTerm); - WriteDOC(0, docptr, Mplus_WritePipeTerm); - /* deassert ALE */ - if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || - command == NAND_CMD_READOOB || command == NAND_CMD_READID) - WriteDOC(0, docptr, Mplus_FlashControl); - } - - /* - * program and erase have their own busy handlers - * status and sequential in needs no delay - */ - switch (command) { - - case NAND_CMD_PAGEPROG: - case NAND_CMD_ERASE1: - case NAND_CMD_ERASE2: - case NAND_CMD_SEQIN: - case NAND_CMD_STATUS: - return; - - case NAND_CMD_RESET: - if (this->dev_ready) - break; - udelay(this->chip_delay); - WriteDOC(NAND_CMD_STATUS, docptr, Mplus_FlashCmd); - WriteDOC(0, docptr, Mplus_WritePipeTerm); - WriteDOC(0, docptr, Mplus_WritePipeTerm); - while (!(this->read_byte(mtd) & 0x40)) ; - return; - - /* This applies to read commands */ - default: - /* - * If we don't have access to the busy pin, we apply the given - * command delay - */ - if (!this->dev_ready) { - udelay(this->chip_delay); - return; - } - } - - /* Apply this short delay always to ensure that we do wait tWB in - * any case on any machine. */ - ndelay(100); - /* wait until command is processed */ - while (!this->dev_ready(mtd)) ; -} - -static int doc200x_dev_ready(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - if (DoC_is_MillenniumPlus(doc)) { - /* 11.4.2 -- must NOP four times before checking FR/B# */ - DoC_Delay(doc, 4); - if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) { - if (debug) - printk("not ready\n"); - return 0; - } - if (debug) - printk("was ready\n"); - return 1; - } else { - /* 11.4.2 -- must NOP four times before checking FR/B# */ - DoC_Delay(doc, 4); - if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) { - if (debug) - printk("not ready\n"); - return 0; - } - /* 11.4.2 -- Must NOP twice if it's ready */ - DoC_Delay(doc, 2); - if (debug) - printk("was ready\n"); - return 1; - } -} - -static int doc200x_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) -{ - /* This is our last resort if we couldn't find or create a BBT. Just - pretend all blocks are good. */ - return 0; -} - -static void doc200x_enable_hwecc(struct mtd_info *mtd, int mode) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - /* Prime the ECC engine */ - switch (mode) { - case NAND_ECC_READ: - WriteDOC(DOC_ECC_RESET, docptr, ECCConf); - WriteDOC(DOC_ECC_EN, docptr, ECCConf); - break; - case NAND_ECC_WRITE: - WriteDOC(DOC_ECC_RESET, docptr, ECCConf); - WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, ECCConf); - break; - } -} - -static void doc2001plus_enable_hwecc(struct mtd_info *mtd, int mode) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - - /* Prime the ECC engine */ - switch (mode) { - case NAND_ECC_READ: - WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf); - WriteDOC(DOC_ECC_EN, docptr, Mplus_ECCConf); - break; - case NAND_ECC_WRITE: - WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf); - WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, Mplus_ECCConf); - break; - } -} - -/* This code is only called on write */ -static int doc200x_calculate_ecc(struct mtd_info *mtd, const u_char *dat, unsigned char *ecc_code) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - int i; - int emptymatch = 1; - - /* flush the pipeline */ - if (DoC_is_2000(doc)) { - WriteDOC(doc->CDSNControl & ~CDSN_CTRL_FLASH_IO, docptr, CDSNControl); - WriteDOC(0, docptr, 2k_CDSN_IO); - WriteDOC(0, docptr, 2k_CDSN_IO); - WriteDOC(0, docptr, 2k_CDSN_IO); - WriteDOC(doc->CDSNControl, docptr, CDSNControl); - } else if (DoC_is_MillenniumPlus(doc)) { - WriteDOC(0, docptr, Mplus_NOP); - WriteDOC(0, docptr, Mplus_NOP); - WriteDOC(0, docptr, Mplus_NOP); - } else { - WriteDOC(0, docptr, NOP); - WriteDOC(0, docptr, NOP); - WriteDOC(0, docptr, NOP); - } - - for (i = 0; i < 6; i++) { - if (DoC_is_MillenniumPlus(doc)) - ecc_code[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i); - else - ecc_code[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i); - if (ecc_code[i] != empty_write_ecc[i]) - emptymatch = 0; - } - if (DoC_is_MillenniumPlus(doc)) - WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf); - else - WriteDOC(DOC_ECC_DIS, docptr, ECCConf); -#if 0 - /* If emptymatch=1, we might have an all-0xff data buffer. Check. */ - if (emptymatch) { - /* Note: this somewhat expensive test should not be triggered - often. It could be optimized away by examining the data in - the writebuf routine, and remembering the result. */ - for (i = 0; i < 512; i++) { - if (dat[i] == 0xff) - continue; - emptymatch = 0; - break; - } - } - /* If emptymatch still =1, we do have an all-0xff data buffer. - Return all-0xff ecc value instead of the computed one, so - it'll look just like a freshly-erased page. */ - if (emptymatch) - memset(ecc_code, 0xff, 6); -#endif - return 0; -} - -static int doc200x_correct_data(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *isnull) -{ - int i, ret = 0; - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - void __iomem *docptr = doc->virtadr; - uint8_t calc_ecc[6]; - volatile u_char dummy; - int emptymatch = 1; - - /* flush the pipeline */ - if (DoC_is_2000(doc)) { - dummy = ReadDOC(docptr, 2k_ECCStatus); - dummy = ReadDOC(docptr, 2k_ECCStatus); - dummy = ReadDOC(docptr, 2k_ECCStatus); - } else if (DoC_is_MillenniumPlus(doc)) { - dummy = ReadDOC(docptr, Mplus_ECCConf); - dummy = ReadDOC(docptr, Mplus_ECCConf); - dummy = ReadDOC(docptr, Mplus_ECCConf); - } else { - dummy = ReadDOC(docptr, ECCConf); - dummy = ReadDOC(docptr, ECCConf); - dummy = ReadDOC(docptr, ECCConf); - } - - /* Error occured ? */ - if (dummy & 0x80) { - for (i = 0; i < 6; i++) { - if (DoC_is_MillenniumPlus(doc)) - calc_ecc[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i); - else - calc_ecc[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i); - if (calc_ecc[i] != empty_read_syndrome[i]) - emptymatch = 0; - } - /* If emptymatch=1, the read syndrome is consistent with an - all-0xff data and stored ecc block. Check the stored ecc. */ - if (emptymatch) { - for (i = 0; i < 6; i++) { - if (read_ecc[i] == 0xff) - continue; - emptymatch = 0; - break; - } - } - /* If emptymatch still =1, check the data block. */ - if (emptymatch) { - /* Note: this somewhat expensive test should not be triggered - often. It could be optimized away by examining the data in - the readbuf routine, and remembering the result. */ - for (i = 0; i < 512; i++) { - if (dat[i] == 0xff) - continue; - emptymatch = 0; - break; - } - } - /* If emptymatch still =1, this is almost certainly a freshly- - erased block, in which case the ECC will not come out right. - We'll suppress the error and tell the caller everything's - OK. Because it is. */ - if (!emptymatch) - ret = doc_ecc_decode(rs_decoder, dat, calc_ecc); - if (ret > 0) - printk(KERN_ERR "doc200x_correct_data corrected %d errors\n", ret); - } - if (DoC_is_MillenniumPlus(doc)) - WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf); - else - WriteDOC(DOC_ECC_DIS, docptr, ECCConf); - if (no_ecc_failures && mtd_is_eccerr(ret)) { - printk(KERN_ERR "suppressing ECC failure\n"); - ret = 0; - } - return ret; -} - -/*u_char mydatabuf[528]; */ - -/* The strange out-of-order .oobfree list below is a (possibly unneeded) - * attempt to retain compatibility. It used to read: - * .oobfree = { {8, 8} } - * Since that leaves two bytes unusable, it was changed. But the following - * scheme might affect existing jffs2 installs by moving the cleanmarker: - * .oobfree = { {6, 10} } - * jffs2 seems to handle the above gracefully, but the current scheme seems - * safer. The only problem with it is that any code that parses oobfree must - * be able to handle out-of-order segments. - */ -static struct nand_ecclayout doc200x_oobinfo = { - .eccbytes = 6, - .eccpos = {0, 1, 2, 3, 4, 5}, - .oobfree = {{8, 8}, {6, 2}} -}; - -/* Find the (I)NFTL Media Header, and optionally also the mirror media header. - On sucessful return, buf will contain a copy of the media header for - further processing. id is the string to scan for, and will presumably be - either "ANAND" or "BNAND". If findmirror=1, also look for the mirror media - header. The page #s of the found media headers are placed in mh0_page and - mh1_page in the DOC private structure. */ -static int __init find_media_headers(struct mtd_info *mtd, u_char *buf, const char *id, int findmirror) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - unsigned offs; - int ret; - size_t retlen; - - for (offs = 0; offs < mtd->size; offs += mtd->erasesize) { - ret = mtd_read(mtd, offs, mtd->writesize, &retlen, buf); - if (retlen != mtd->writesize) - continue; - if (ret) { - printk(KERN_WARNING "ECC error scanning DOC at 0x%x\n", offs); - } - if (memcmp(buf, id, 6)) - continue; - printk(KERN_INFO "Found DiskOnChip %s Media Header at 0x%x\n", id, offs); - if (doc->mh0_page == -1) { - doc->mh0_page = offs >> this->page_shift; - if (!findmirror) - return 1; - continue; - } - doc->mh1_page = offs >> this->page_shift; - return 2; - } - if (doc->mh0_page == -1) { - printk(KERN_WARNING "DiskOnChip %s Media Header not found.\n", id); - return 0; - } - /* Only one mediaheader was found. We want buf to contain a - mediaheader on return, so we'll have to re-read the one we found. */ - offs = doc->mh0_page << this->page_shift; - ret = mtd_read(mtd, offs, mtd->writesize, &retlen, buf); - if (retlen != mtd->writesize) { - /* Insanity. Give up. */ - printk(KERN_ERR "Read DiskOnChip Media Header once, but can't reread it???\n"); - return 0; - } - return 1; -} - -static inline int __init nftl_partscan(struct mtd_info *mtd, struct mtd_partition *parts) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - int ret = 0; - u_char *buf; - struct NFTLMediaHeader *mh; - const unsigned psize = 1 << this->page_shift; - int numparts = 0; - unsigned blocks, maxblocks; - int offs, numheaders; - - buf = kmalloc(mtd->writesize, GFP_KERNEL); - if (!buf) { - printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n"); - return 0; - } - if (!(numheaders = find_media_headers(mtd, buf, "ANAND", 1))) - goto out; - mh = (struct NFTLMediaHeader *)buf; - - le16_to_cpus(&mh->NumEraseUnits); - le16_to_cpus(&mh->FirstPhysicalEUN); - le32_to_cpus(&mh->FormattedSize); - - printk(KERN_INFO " DataOrgID = %s\n" - " NumEraseUnits = %d\n" - " FirstPhysicalEUN = %d\n" - " FormattedSize = %d\n" - " UnitSizeFactor = %d\n", - mh->DataOrgID, mh->NumEraseUnits, - mh->FirstPhysicalEUN, mh->FormattedSize, - mh->UnitSizeFactor); - - blocks = mtd->size >> this->phys_erase_shift; - maxblocks = min(32768U, mtd->erasesize - psize); - - if (mh->UnitSizeFactor == 0x00) { - /* Auto-determine UnitSizeFactor. The constraints are: - - There can be at most 32768 virtual blocks. - - There can be at most (virtual block size - page size) - virtual blocks (because MediaHeader+BBT must fit in 1). - */ - mh->UnitSizeFactor = 0xff; - while (blocks > maxblocks) { - blocks >>= 1; - maxblocks = min(32768U, (maxblocks << 1) + psize); - mh->UnitSizeFactor--; - } - printk(KERN_WARNING "UnitSizeFactor=0x00 detected. Correct value is assumed to be 0x%02x.\n", mh->UnitSizeFactor); - } - - /* NOTE: The lines below modify internal variables of the NAND and MTD - layers; variables with have already been configured by nand_scan. - Unfortunately, we didn't know before this point what these values - should be. Thus, this code is somewhat dependant on the exact - implementation of the NAND layer. */ - if (mh->UnitSizeFactor != 0xff) { - this->bbt_erase_shift += (0xff - mh->UnitSizeFactor); - mtd->erasesize <<= (0xff - mh->UnitSizeFactor); - printk(KERN_INFO "Setting virtual erase size to %d\n", mtd->erasesize); - blocks = mtd->size >> this->bbt_erase_shift; - maxblocks = min(32768U, mtd->erasesize - psize); - } - - if (blocks > maxblocks) { - printk(KERN_ERR "UnitSizeFactor of 0x%02x is inconsistent with device size. Aborting.\n", mh->UnitSizeFactor); - goto out; - } - - /* Skip past the media headers. */ - offs = max(doc->mh0_page, doc->mh1_page); - offs <<= this->page_shift; - offs += mtd->erasesize; - - if (show_firmware_partition == 1) { - parts[0].name = " DiskOnChip Firmware / Media Header partition"; - parts[0].offset = 0; - parts[0].size = offs; - numparts = 1; - } - - parts[numparts].name = " DiskOnChip BDTL partition"; - parts[numparts].offset = offs; - parts[numparts].size = (mh->NumEraseUnits - numheaders) << this->bbt_erase_shift; - - offs += parts[numparts].size; - numparts++; - - if (offs < mtd->size) { - parts[numparts].name = " DiskOnChip Remainder partition"; - parts[numparts].offset = offs; - parts[numparts].size = mtd->size - offs; - numparts++; - } - - ret = numparts; - out: - kfree(buf); - return ret; -} - -/* This is a stripped-down copy of the code in inftlmount.c */ -static inline int __init inftl_partscan(struct mtd_info *mtd, struct mtd_partition *parts) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - int ret = 0; - u_char *buf; - struct INFTLMediaHeader *mh; - struct INFTLPartition *ip; - int numparts = 0; - int blocks; - int vshift, lastvunit = 0; - int i; - int end = mtd->size; - - if (inftl_bbt_write) - end -= (INFTL_BBT_RESERVED_BLOCKS << this->phys_erase_shift); - - buf = kmalloc(mtd->writesize, GFP_KERNEL); - if (!buf) { - printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n"); - return 0; - } - - if (!find_media_headers(mtd, buf, "BNAND", 0)) - goto out; - doc->mh1_page = doc->mh0_page + (4096 >> this->page_shift); - mh = (struct INFTLMediaHeader *)buf; - - le32_to_cpus(&mh->NoOfBootImageBlocks); - le32_to_cpus(&mh->NoOfBinaryPartitions); - le32_to_cpus(&mh->NoOfBDTLPartitions); - le32_to_cpus(&mh->BlockMultiplierBits); - le32_to_cpus(&mh->FormatFlags); - le32_to_cpus(&mh->PercentUsed); - - printk(KERN_INFO " bootRecordID = %s\n" - " NoOfBootImageBlocks = %d\n" - " NoOfBinaryPartitions = %d\n" - " NoOfBDTLPartitions = %d\n" - " BlockMultiplerBits = %d\n" - " FormatFlgs = %d\n" - " OsakVersion = %d.%d.%d.%d\n" - " PercentUsed = %d\n", - mh->bootRecordID, mh->NoOfBootImageBlocks, - mh->NoOfBinaryPartitions, - mh->NoOfBDTLPartitions, - mh->BlockMultiplierBits, mh->FormatFlags, - ((unsigned char *) &mh->OsakVersion)[0] & 0xf, - ((unsigned char *) &mh->OsakVersion)[1] & 0xf, - ((unsigned char *) &mh->OsakVersion)[2] & 0xf, - ((unsigned char *) &mh->OsakVersion)[3] & 0xf, - mh->PercentUsed); - - vshift = this->phys_erase_shift + mh->BlockMultiplierBits; - - blocks = mtd->size >> vshift; - if (blocks > 32768) { - printk(KERN_ERR "BlockMultiplierBits=%d is inconsistent with device size. Aborting.\n", mh->BlockMultiplierBits); - goto out; - } - - blocks = doc->chips_per_floor << (this->chip_shift - this->phys_erase_shift); - if (inftl_bbt_write && (blocks > mtd->erasesize)) { - printk(KERN_ERR "Writeable BBTs spanning more than one erase block are not yet supported. FIX ME!\n"); - goto out; - } - - /* Scan the partitions */ - for (i = 0; (i < 4); i++) { - ip = &(mh->Partitions[i]); - le32_to_cpus(&ip->virtualUnits); - le32_to_cpus(&ip->firstUnit); - le32_to_cpus(&ip->lastUnit); - le32_to_cpus(&ip->flags); - le32_to_cpus(&ip->spareUnits); - le32_to_cpus(&ip->Reserved0); - - printk(KERN_INFO " PARTITION[%d] ->\n" - " virtualUnits = %d\n" - " firstUnit = %d\n" - " lastUnit = %d\n" - " flags = 0x%x\n" - " spareUnits = %d\n", - i, ip->virtualUnits, ip->firstUnit, - ip->lastUnit, ip->flags, - ip->spareUnits); - - if ((show_firmware_partition == 1) && - (i == 0) && (ip->firstUnit > 0)) { - parts[0].name = " DiskOnChip IPL / Media Header partition"; - parts[0].offset = 0; - parts[0].size = mtd->erasesize * ip->firstUnit; - numparts = 1; - } - - if (ip->flags & INFTL_BINARY) - parts[numparts].name = " DiskOnChip BDK partition"; - else - parts[numparts].name = " DiskOnChip BDTL partition"; - parts[numparts].offset = ip->firstUnit << vshift; - parts[numparts].size = (1 + ip->lastUnit - ip->firstUnit) << vshift; - numparts++; - if (ip->lastUnit > lastvunit) - lastvunit = ip->lastUnit; - if (ip->flags & INFTL_LAST) - break; - } - lastvunit++; - if ((lastvunit << vshift) < end) { - parts[numparts].name = " DiskOnChip Remainder partition"; - parts[numparts].offset = lastvunit << vshift; - parts[numparts].size = end - parts[numparts].offset; - numparts++; - } - ret = numparts; - out: - kfree(buf); - return ret; -} - -static int __init nftl_scan_bbt(struct mtd_info *mtd) -{ - int ret, numparts; - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - struct mtd_partition parts[2]; - - memset((char *)parts, 0, sizeof(parts)); - /* On NFTL, we have to find the media headers before we can read the - BBTs, since they're stored in the media header eraseblocks. */ - numparts = nftl_partscan(mtd, parts); - if (!numparts) - return -EIO; - this->bbt_td->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT | - NAND_BBT_SAVECONTENT | NAND_BBT_WRITE | - NAND_BBT_VERSION; - this->bbt_td->veroffs = 7; - this->bbt_td->pages[0] = doc->mh0_page + 1; - if (doc->mh1_page != -1) { - this->bbt_md->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT | - NAND_BBT_SAVECONTENT | NAND_BBT_WRITE | - NAND_BBT_VERSION; - this->bbt_md->veroffs = 7; - this->bbt_md->pages[0] = doc->mh1_page + 1; - } else { - this->bbt_md = NULL; - } - - /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set. - At least as nand_bbt.c is currently written. */ - if ((ret = nand_scan_bbt(mtd, NULL))) - return ret; - add_mtd_device(mtd); -#ifdef CONFIG_MTD_PARTITIONS - if (!no_autopart) - add_mtd_partitions(mtd, parts, numparts); -#endif - return 0; -} - -static int __init inftl_scan_bbt(struct mtd_info *mtd) -{ - int ret, numparts; - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - struct mtd_partition parts[5]; - - if (this->numchips > doc->chips_per_floor) { - printk(KERN_ERR "Multi-floor INFTL devices not yet supported.\n"); - return -EIO; - } - - if (DoC_is_MillenniumPlus(doc)) { - this->bbt_td->options = NAND_BBT_2BIT | NAND_BBT_ABSPAGE; - if (inftl_bbt_write) - this->bbt_td->options |= NAND_BBT_WRITE; - this->bbt_td->pages[0] = 2; - this->bbt_md = NULL; - } else { - this->bbt_td->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT | NAND_BBT_VERSION; - if (inftl_bbt_write) - this->bbt_td->options |= NAND_BBT_WRITE; - this->bbt_td->offs = 8; - this->bbt_td->len = 8; - this->bbt_td->veroffs = 7; - this->bbt_td->maxblocks = INFTL_BBT_RESERVED_BLOCKS; - this->bbt_td->reserved_block_code = 0x01; - this->bbt_td->pattern = "MSYS_BBT"; - - this->bbt_md->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT | NAND_BBT_VERSION; - if (inftl_bbt_write) - this->bbt_md->options |= NAND_BBT_WRITE; - this->bbt_md->offs = 8; - this->bbt_md->len = 8; - this->bbt_md->veroffs = 7; - this->bbt_md->maxblocks = INFTL_BBT_RESERVED_BLOCKS; - this->bbt_md->reserved_block_code = 0x01; - this->bbt_md->pattern = "TBB_SYSM"; - } - - /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set. - At least as nand_bbt.c is currently written. */ - if ((ret = nand_scan_bbt(mtd, NULL))) - return ret; - memset((char *)parts, 0, sizeof(parts)); - numparts = inftl_partscan(mtd, parts); - /* At least for now, require the INFTL Media Header. We could probably - do without it for non-INFTL use, since all it gives us is - autopartitioning, but I want to give it more thought. */ - if (!numparts) - return -EIO; - add_mtd_device(mtd); -#ifdef CONFIG_MTD_PARTITIONS - if (!no_autopart) - add_mtd_partitions(mtd, parts, numparts); -#endif - return 0; -} - -static inline int __init doc2000_init(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - - this->read_byte = doc2000_read_byte; - this->write_buf = doc2000_writebuf; - this->read_buf = doc2000_readbuf; - this->verify_buf = doc2000_verifybuf; - this->scan_bbt = nftl_scan_bbt; - - doc->CDSNControl = CDSN_CTRL_FLASH_IO | CDSN_CTRL_ECC_IO; - doc2000_count_chips(mtd); - mtd->name = "DiskOnChip 2000 (NFTL Model)"; - return (4 * doc->chips_per_floor); -} - -static inline int __init doc2001_init(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - - this->read_byte = doc2001_read_byte; - this->write_buf = doc2001_writebuf; - this->read_buf = doc2001_readbuf; - this->verify_buf = doc2001_verifybuf; - - ReadDOC(doc->virtadr, ChipID); - ReadDOC(doc->virtadr, ChipID); - ReadDOC(doc->virtadr, ChipID); - if (ReadDOC(doc->virtadr, ChipID) != DOC_ChipID_DocMil) { - /* It's not a Millennium; it's one of the newer - DiskOnChip 2000 units with a similar ASIC. - Treat it like a Millennium, except that it - can have multiple chips. */ - doc2000_count_chips(mtd); - mtd->name = "DiskOnChip 2000 (INFTL Model)"; - this->scan_bbt = inftl_scan_bbt; - return (4 * doc->chips_per_floor); - } else { - /* Bog-standard Millennium */ - doc->chips_per_floor = 1; - mtd->name = "DiskOnChip Millennium"; - this->scan_bbt = nftl_scan_bbt; - return 1; - } -} - -static inline int __init doc2001plus_init(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - struct doc_priv *doc = this->priv; - - this->read_byte = doc2001plus_read_byte; - this->write_buf = doc2001plus_writebuf; - this->read_buf = doc2001plus_readbuf; - this->verify_buf = doc2001plus_verifybuf; - this->scan_bbt = inftl_scan_bbt; - this->cmd_ctrl = NULL; - this->select_chip = doc2001plus_select_chip; - this->cmdfunc = doc2001plus_command; - this->ecc.hwctl = doc2001plus_enable_hwecc; - - doc->chips_per_floor = 1; - mtd->name = "DiskOnChip Millennium Plus"; - - return 1; -} - -static int __init doc_probe(unsigned long physadr) -{ - unsigned char ChipID; - struct mtd_info *mtd; - struct nand_chip *nand; - struct doc_priv *doc; - void __iomem *virtadr; - unsigned char save_control; - unsigned char tmp, tmpb, tmpc; - int reg, len, numchips; - int ret = 0; - - virtadr = ioremap(physadr, DOC_IOREMAP_LEN); - if (!virtadr) { - printk(KERN_ERR "Diskonchip ioremap failed: 0x%x bytes at 0x%lx\n", DOC_IOREMAP_LEN, physadr); - return -EIO; - } - - /* It's not possible to cleanly detect the DiskOnChip - the - * bootup procedure will put the device into reset mode, and - * it's not possible to talk to it without actually writing - * to the DOCControl register. So we store the current contents - * of the DOCControl register's location, in case we later decide - * that it's not a DiskOnChip, and want to put it back how we - * found it. - */ - save_control = ReadDOC(virtadr, DOCControl); - - /* Reset the DiskOnChip ASIC */ - WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, virtadr, DOCControl); - WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, virtadr, DOCControl); - - /* Enable the DiskOnChip ASIC */ - WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, virtadr, DOCControl); - WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, virtadr, DOCControl); - - ChipID = ReadDOC(virtadr, ChipID); - - switch (ChipID) { - case DOC_ChipID_Doc2k: - reg = DoC_2k_ECCStatus; - break; - case DOC_ChipID_DocMil: - reg = DoC_ECCConf; - break; - case DOC_ChipID_DocMilPlus16: - case DOC_ChipID_DocMilPlus32: - case 0: - /* Possible Millennium Plus, need to do more checks */ - /* Possibly release from power down mode */ - for (tmp = 0; (tmp < 4); tmp++) - ReadDOC(virtadr, Mplus_Power); - - /* Reset the Millennium Plus ASIC */ - tmp = DOC_MODE_RESET | DOC_MODE_MDWREN | DOC_MODE_RST_LAT | DOC_MODE_BDECT; - WriteDOC(tmp, virtadr, Mplus_DOCControl); - WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm); - - mdelay(1); - /* Enable the Millennium Plus ASIC */ - tmp = DOC_MODE_NORMAL | DOC_MODE_MDWREN | DOC_MODE_RST_LAT | DOC_MODE_BDECT; - WriteDOC(tmp, virtadr, Mplus_DOCControl); - WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm); - mdelay(1); - - ChipID = ReadDOC(virtadr, ChipID); - - switch (ChipID) { - case DOC_ChipID_DocMilPlus16: - reg = DoC_Mplus_Toggle; - break; - case DOC_ChipID_DocMilPlus32: - printk(KERN_ERR "DiskOnChip Millennium Plus 32MB is not supported, ignoring.\n"); - default: - ret = -ENODEV; - goto notfound; - } - break; - - default: - ret = -ENODEV; - goto notfound; - } - /* Check the TOGGLE bit in the ECC register */ - tmp = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; - tmpb = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; - tmpc = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; - if ((tmp == tmpb) || (tmp != tmpc)) { - printk(KERN_WARNING "Possible DiskOnChip at 0x%lx failed TOGGLE test, dropping.\n", physadr); - ret = -ENODEV; - goto notfound; - } - - for (mtd = doclist; mtd; mtd = doc->nextdoc) { - unsigned char oldval; - unsigned char newval; - nand = mtd->priv; - doc = nand->priv; - /* Use the alias resolution register to determine if this is - in fact the same DOC aliased to a new address. If writes - to one chip's alias resolution register change the value on - the other chip, they're the same chip. */ - if (ChipID == DOC_ChipID_DocMilPlus16) { - oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution); - newval = ReadDOC(virtadr, Mplus_AliasResolution); - } else { - oldval = ReadDOC(doc->virtadr, AliasResolution); - newval = ReadDOC(virtadr, AliasResolution); - } - if (oldval != newval) - continue; - if (ChipID == DOC_ChipID_DocMilPlus16) { - WriteDOC(~newval, virtadr, Mplus_AliasResolution); - oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution); - WriteDOC(newval, virtadr, Mplus_AliasResolution); /* restore it */ - } else { - WriteDOC(~newval, virtadr, AliasResolution); - oldval = ReadDOC(doc->virtadr, AliasResolution); - WriteDOC(newval, virtadr, AliasResolution); /* restore it */ - } - newval = ~newval; - if (oldval == newval) { - printk(KERN_DEBUG "Found alias of DOC at 0x%lx to 0x%lx\n", doc->physadr, physadr); - goto notfound; - } - } - - printk(KERN_NOTICE "DiskOnChip found at 0x%lx\n", physadr); - - len = sizeof(struct mtd_info) + - sizeof(struct nand_chip) + sizeof(struct doc_priv) + (2 * sizeof(struct nand_bbt_descr)); - mtd = kzalloc(len, GFP_KERNEL); - if (!mtd) { - printk(KERN_ERR "DiskOnChip kmalloc (%d bytes) failed!\n", len); - ret = -ENOMEM; - goto fail; - } - - nand = (struct nand_chip *) (mtd + 1); - doc = (struct doc_priv *) (nand + 1); - nand->bbt_td = (struct nand_bbt_descr *) (doc + 1); - nand->bbt_md = nand->bbt_td + 1; - - mtd->priv = nand; - mtd->owner = THIS_MODULE; - - nand->priv = doc; - nand->select_chip = doc200x_select_chip; - nand->cmd_ctrl = doc200x_hwcontrol; - nand->dev_ready = doc200x_dev_ready; - nand->waitfunc = doc200x_wait; - nand->block_bad = doc200x_block_bad; - nand->ecc.hwctl = doc200x_enable_hwecc; - nand->ecc.calculate = doc200x_calculate_ecc; - nand->ecc.correct = doc200x_correct_data; - - nand->ecc.layout = &doc200x_oobinfo; - nand->ecc.mode = NAND_ECC_HW_SYNDROME; - nand->ecc.size = 512; - nand->ecc.bytes = 6; - nand->ecc.strength = 2; - nand->bbt_options = NAND_BBT_USE_FLASH; - - doc->physadr = physadr; - doc->virtadr = virtadr; - doc->ChipID = ChipID; - doc->curfloor = -1; - doc->curchip = -1; - doc->mh0_page = -1; - doc->mh1_page = -1; - doc->nextdoc = doclist; - - if (ChipID == DOC_ChipID_Doc2k) - numchips = doc2000_init(mtd); - else if (ChipID == DOC_ChipID_DocMilPlus16) - numchips = doc2001plus_init(mtd); - else - numchips = doc2001_init(mtd); - - if ((ret = nand_scan(mtd, numchips))) { - /* DBB note: i believe nand_release is necessary here, as - buffers may have been allocated in nand_base. Check with - Thomas. FIX ME! */ - /* nand_release will call del_mtd_device, but we haven't yet - added it. This is handled without incident by - del_mtd_device, as far as I can tell. */ - nand_release(mtd); - kfree(mtd); - goto fail; - } - - /* Success! */ - doclist = mtd; - return 0; - - notfound: - /* Put back the contents of the DOCControl register, in case it's not - actually a DiskOnChip. */ - WriteDOC(save_control, virtadr, DOCControl); - fail: - iounmap(virtadr); - return ret; -} - -static void release_nanddoc(void) -{ - struct mtd_info *mtd, *nextmtd; - struct nand_chip *nand; - struct doc_priv *doc; - - for (mtd = doclist; mtd; mtd = nextmtd) { - nand = mtd->priv; - doc = nand->priv; - - nextmtd = doc->nextdoc; - nand_release(mtd); - iounmap(doc->virtadr); - kfree(mtd); - } -} - -static int __init init_nanddoc(void) -{ - int i, ret = 0; - - /* We could create the decoder on demand, if memory is a concern. - * This way we have it handy, if an error happens - * - * Symbolsize is 10 (bits) - * Primitve polynomial is x^10+x^3+1 - * first consecutive root is 510 - * primitve element to generate roots = 1 - * generator polinomial degree = 4 - */ - rs_decoder = init_rs(10, 0x409, FCR, 1, NROOTS); - if (!rs_decoder) { - printk(KERN_ERR "DiskOnChip: Could not create a RS decoder\n"); - return -ENOMEM; - } - - if (doc_config_location) { - printk(KERN_INFO "Using configured DiskOnChip probe address 0x%lx\n", doc_config_location); - ret = doc_probe(doc_config_location); - if (ret < 0) - goto outerr; - } else { - for (i = 0; (doc_locations[i] != 0xffffffff); i++) { - doc_probe(doc_locations[i]); - } - } - /* No banner message any more. Print a message if no DiskOnChip - found, so the user knows we at least tried. */ - if (!doclist) { - printk(KERN_INFO "No valid DiskOnChip devices found\n"); - ret = -ENODEV; - goto outerr; - } - return 0; - outerr: - free_rs(rs_decoder); - return ret; -} - -static void __exit cleanup_nanddoc(void) -{ - /* Cleanup the nand/DoC resources */ - release_nanddoc(); - - /* Free the reed solomon resources */ - if (rs_decoder) { - free_rs(rs_decoder); - } -} - -module_init(init_nanddoc); -module_exit(cleanup_nanddoc); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("David Woodhouse "); -MODULE_DESCRIPTION("M-Systems DiskOnChip 2000, Millennium and Millennium Plus device driver\n"); -- cgit v1.3.1 From 4fb3925ff8b64422eb904c630e914c29ed824e85 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Apr 2014 15:25:06 +0900 Subject: powerpc: remove RPXClassic, RPXlite boards support Enough time has passed since these boards were moved to Orphan. Remove. - Remove board/RPXlite/* - Remove board/RPXClassic/* - Remove include/configs/RPXlite.h - Remove include/configs/RPXClassic.h - Clean-up defined(CONFIG_RPXCLASSIC) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc8xx/cpu_init.c | 5 - arch/powerpc/cpu/mpc8xx/scc.c | 7 - arch/powerpc/cpu/mpc8xx/serial.c | 2 +- board/RPXClassic/Makefile | 8 - board/RPXClassic/README | 19 - board/RPXClassic/RPXClassic.c | 260 ----------- board/RPXClassic/eccx.c | 335 -------------- board/RPXClassic/flash.c | 431 ------------------ board/RPXClassic/u-boot.lds | 82 ---- board/RPXClassic/u-boot.lds.debug | 121 ----- board/RPXlite/Makefile | 8 - board/RPXlite/README | 877 ------------------------------------- board/RPXlite/README.PlanetCore | 163 ------- board/RPXlite/RPXlite.c | 149 ------- board/RPXlite/flash.c | 508 --------------------- board/RPXlite/u-boot.lds | 82 ---- board/RPXlite/u-boot.lds.debug | 121 ----- boards.cfg | 2 - doc/README.scrapyard | 2 + drivers/pcmcia/mpc8xx_pcmcia.c | 2 +- drivers/pcmcia/rpx_pcmcia.c | 4 +- include/common.h | 4 - include/commproc.h | 35 -- include/configs/RPXClassic.h | 483 -------------------- include/configs/RPXlite.h | 395 ----------------- include/pcmcia.h | 2 +- post/cpu/mpc8xx/ether.c | 7 - post/cpu/mpc8xx/uart.c | 2 +- 28 files changed, 8 insertions(+), 4108 deletions(-) delete mode 100644 board/RPXClassic/Makefile delete mode 100644 board/RPXClassic/README delete mode 100644 board/RPXClassic/RPXClassic.c delete mode 100644 board/RPXClassic/eccx.c delete mode 100644 board/RPXClassic/flash.c delete mode 100644 board/RPXClassic/u-boot.lds delete mode 100644 board/RPXClassic/u-boot.lds.debug delete mode 100644 board/RPXlite/Makefile delete mode 100644 board/RPXlite/README delete mode 100644 board/RPXlite/README.PlanetCore delete mode 100644 board/RPXlite/RPXlite.c delete mode 100644 board/RPXlite/flash.c delete mode 100644 board/RPXlite/u-boot.lds delete mode 100644 board/RPXlite/u-boot.lds.debug delete mode 100644 include/configs/RPXClassic.h delete mode 100644 include/configs/RPXlite.h (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 69455c7be02..9c3102dc69f 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -138,7 +138,6 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_MHPC) || \ defined(CONFIG_R360MPI) || \ defined(CONFIG_RMU) || \ - defined(CONFIG_RPXCLASSIC) || \ defined(CONFIG_RPXLITE) || \ defined(CONFIG_SPC1920) || \ defined(CONFIG_SPD823TS) @@ -207,10 +206,6 @@ void cpu_init_f (volatile immap_t * immr) __asm__ ("eieio"); } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); -#ifdef CONFIG_RPXCLASSIC - rpxclassic_init (); -#endif - #if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM) rpxlite_init (); #endif diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 647f05817bc..5da697366de 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -461,11 +461,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined #endif -#ifdef CONFIG_RPXCLASSIC - *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; - *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); -#endif - #ifdef CONFIG_RPXLITE *((uchar *) BCSR0) |= BCSR0_ETHEN; #endif @@ -512,8 +507,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) */ #if defined (CONFIG_FADS) udelay (10000); /* wait 10 ms */ -#elif defined(CONFIG_RPXCLASSIC) - udelay (100000); /* wait 100 ms */ #endif return 1; diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c index f7ca11e3945..932141144ce 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -182,7 +182,7 @@ static int smc_init (void) #endif #endif /* CONFIG_FADS */ -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) +#if defined(CONFIG_RPXLITE) /* Enable Monitor Port Transceiver */ *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ; #endif /* CONFIG_RPXLITE */ diff --git a/board/RPXClassic/Makefile b/board/RPXClassic/Makefile deleted file mode 100644 index 87db754faa2..00000000000 --- a/board/RPXClassic/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = RPXClassic.o flash.o eccx.o diff --git a/board/RPXClassic/README b/board/RPXClassic/README deleted file mode 100644 index e03f670d1c1..00000000000 --- a/board/RPXClassic/README +++ /dev/null @@ -1,19 +0,0 @@ -# Porting U-Boot onto RPXClassic LF_BW31 board -# Written by Pierre AUBERT -# E-Mail p.aubert@staubli.com -# Stäubli Faverges - -# -# Sept. 20 2001 -# -# Cross compile: Montavista Hardhat ported on HP-UX 10.20 -# - -Flash memories : AM29DL323B (2 banks flash memories) 16 Mb from 0xff000000 -DRAM : 16 Mb from 0 -NVRAM : 512 kb from 0xfa000000 - - -- environment is stored in NVRAM -- Mac address is read from EEPROM -- ethernet on SCC1 or fast ethernet on FEC are running (depending on the - configuration flag CONFIG_FEC_ENET) diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c deleted file mode 100644 index 15b7232fd7b..00000000000 --- a/board/RPXClassic/RPXClassic.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * (C) Copyright 2001 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * U-Boot port on RPXClassic LF (CLLF_BW31) board - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static unsigned char aschex_to_byte (unsigned char *cp); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, - 0x0CFFCC00, 0x33FFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXClassic\n"); - return (0); -} - -/*----------------------------------------------------------------------------- - * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM - *----------------------------------------------------------------------------- - */ -static void board_get_enetaddr(uchar *enet) -{ - int i; - char buff[256], *cp; - - /* Initialize I2C */ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x54, 0, 1, (uchar *)buff, 128); - i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128); - - /* Retrieve MAC address in buffer (key EA) */ - for (cp = buff;;) { - if (cp[0] == 'E' && cp[1] == 'A') { - cp += 3; - /* Read MAC address */ - for (i = 0; i < 6; i++, cp += 2) { - enet[i] = aschex_to_byte ((unsigned char *)cp); - } - } - /* Scan to the end of the record */ - while ((*cp != '\n') && (*cp != (char)0xff)) { - cp++; - } - /* If the next character is a \n, 0 or ff, we are done. */ - cp++; - if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff)) - break; - } - -#ifdef CONFIG_FEC_ENET - /* The MAC address is the same as normal ethernet except the 3rd byte */ - /* (See the E.P. Planet Core Overview manual */ - enet[3] |= 0x80; -#endif - - printf("MAC address = %pM\n", enet); -} - -int misc_init_r(void) -{ - uchar enetaddr[6]; - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - return 0; -} - -void rpxclassic_init (void) -{ - /* Enable NVRAM */ - *((uchar *) BCSR0) |= BCSR0_ENNVRAM; - -#ifdef CONFIG_FEC_ENET - - /* Validate the fast ethernet tranceiver */ - *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL; - *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN; - *((volatile uchar *) BCSR2) |= BCSR2_MIIRST; - *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN; -#endif - -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size10; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000000; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 10 column mode - */ - - size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - return (size10); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} -/*----------------------------------------------------------------------------- - * aschex_to_byte -- - *----------------------------------------------------------------------------- - */ -static unsigned char aschex_to_byte (unsigned char *cp) -{ - u_char byte, c; - - c = *cp++; - - if ((c >= 'A') && (c <= 'F')) { - c -= 'A'; - c += 10; - } else if ((c >= 'a') && (c <= 'f')) { - c -= 'a'; - c += 10; - } else { - c -= '0'; - } - - byte = c * 16; - - c = *cp; - - if ((c >= 'A') && (c <= 'F')) { - c -= 'A'; - c += 10; - } else if ((c >= 'a') && (c <= 'f')) { - c -= 'a'; - c += 10; - } else { - c -= '0'; - } - - byte += c; - - return (byte); -} diff --git a/board/RPXClassic/eccx.c b/board/RPXClassic/eccx.c deleted file mode 100644 index 766a19eb1e8..00000000000 --- a/board/RPXClassic/eccx.c +++ /dev/null @@ -1,335 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* Video support for the ECCX daughter board */ - - -#include -#include - -#ifdef CONFIG_VIDEO_SED13806 -#include - - -/* Screen configurations: the initialization of the SD13806 depends on - screen and on display mode. We handle only 8bpp and 16 bpp modes */ - -/* ECCX board is supplied with a NEC NL6448BC20 screen */ -#ifdef CONFIG_NEC_NL6448BC20 -#define DISPLAY_WIDTH 640 -#define DISPLAY_HEIGHT 480 - -#ifdef CONFIG_VIDEO_SED13806_8BPP -static const S1D_REGS init_regs [] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0xe5}, /* General IO Pins Control Register 0 */ - {0x0009,0x1f}, /* General IO Pins Control Register 1 */ - {0x0010,0x02}, /* Memory Clock Configuration Register */ - {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x04}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x03}, /* LCD Display Mode Register */ - {0x0041,0x02}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x40}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x01}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x00}, /* TV Output Control Register */ - {0x0060,0x03}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01E4,0x00}, /* Look-Up Table Data Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ - {0, 0} -}; -#endif /* CONFIG_VIDEO_SED13806_8BPP */ - -#ifdef CONFIG_VIDEO_SED13806_16BPP - -static const S1D_REGS init_regs [] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0xe5}, /* General IO Pins Control Register 0 */ - {0x0009,0x1f}, /* General IO Pins Control Register 1 */ - {0x0010,0x02}, /* Memory Clock Configuration Register */ - {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x04}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x05}, /* LCD Display Mode Register */ - {0x0041,0x02}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x00}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x01}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01E4,0x00}, /* Look-Up Table Data Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ - {0, 0} -}; - -#endif /* CONFIG_VIDEO_SED13806_16BPP */ -#endif /* CONFIG_NEC_NL6448BC20 */ - - -#ifdef CONFIG_CONSOLE_EXTRA_INFO - -/*----------------------------------------------------------------------------- - * video_get_info_str -- setup a board string: type, speed, etc. - * line_number= location to place info string beside logo - * info= buffer for info string - *----------------------------------------------------------------------------- - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { - strcpy (info, " RPXClassic board"); - } - else { - info [0] = '\0'; - } - -} -#endif - -/*----------------------------------------------------------------------------- - * board_video_init -- init de l'EPSON, config du CS - *----------------------------------------------------------------------------- - */ -unsigned int board_video_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Program ECCX registers */ - *(ECCX_CSR12) |= ECCX_860; - *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2; - *(ECCX_CSR8) |= ECCX_ENEPSON; - - memctl->memc_or2 = SED13806_OR; - memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES; - - return (SED13806_REG_ADDR); -} - -/*----------------------------------------------------------------------------- - * board_validate_screen -- - *----------------------------------------------------------------------------- - */ -void board_validate_screen (unsigned int base) -{ - /* Activate the panel bias power */ - *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80; -} -/*----------------------------------------------------------------------------- - * board_get_regs -- - *----------------------------------------------------------------------------- - */ -const S1D_REGS *board_get_regs (void) -{ - return (init_regs); -} -/*----------------------------------------------------------------------------- - * board_get_width -- - *----------------------------------------------------------------------------- - */ -int board_get_width (void) -{ - return (DISPLAY_WIDTH); -} - -/*----------------------------------------------------------------------------- - * board_get_height -- - *----------------------------------------------------------------------------- - */ -int board_get_height (void) -{ - return (DISPLAY_HEIGHT); -} - -#endif /* CONFIG_VIDEO_SED13806 */ diff --git a/board/RPXClassic/flash.c b/board/RPXClassic/flash.c deleted file mode 100644 index 97ffa68aa21..00000000000 --- a/board/RPXClassic/flash.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2001 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * U-Boot port on RPXClassic LF (CLLF_BW31) board - * - * RPXClassic uses Am29DL323B flash memory with 2 banks - * - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL323B: - printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Reset flash componeny */ - addr [0] = 0xf0f0f0f0; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0xAAAAAAAA ; - addr[0x555] = 0x55555555 ; - addr[0xAAA] = 0x90909090 ; - - value = addr[0] ; - - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - - switch (value & 0x00FF00FF) { - case (AMD_ID_DL323B & 0x00FF00FF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; /* 16 Mb */ - - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /* set up sector start address table */ - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - - /* check for protected sectors */ - for (i = 0; i < 23; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - /* Check for protected sectors in the 2nd bank */ - addr[0x100AAA] = 0xAAAAAAAA ; - addr[0x100555] = 0x55555555 ; - addr[0x100AAA] = 0x90909090 ; - - for (i = 23; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank 1 */ - addr = (volatile unsigned long *)info->start[23]; - - *addr = 0xF0F0F0F0; /* reset bank 2 */ - - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds deleted file mode 100644 index 0eb2fba00c2..00000000000 --- a/board/RPXClassic/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug deleted file mode 100644 index b9c84c77d64..00000000000 --- a/board/RPXClassic/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite/Makefile b/board/RPXlite/Makefile deleted file mode 100644 index c17cbacf329..00000000000 --- a/board/RPXlite/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = RPXlite.o flash.o diff --git a/board/RPXlite/README b/board/RPXlite/README deleted file mode 100644 index 3ca671126d4..00000000000 --- a/board/RPXlite/README +++ /dev/null @@ -1,877 +0,0 @@ -# Porting U-Boot onto RPXlite board -# Written by Yoo. Jonghoon -# E-Mail : yooth@ipone.co.kr -# IP ONE Inc. - -# Since 2001. 1. 29 - -# Shell : bash -# Cross-compile tools : Montavista Hardhat -# Debugging tools : Windriver VisionProbe (PowerPC BDM) -# ppcboot ver. : ppcboot-0.8.1 - -############################################################### -# 1. Hardware setting -############################################################### - -1.1. Board, BDM settings - Install board, BDM, connect each other - -1.2. Save Register value - Boot with board-on monitor program and save the - register values with BDM. - -1.3. Configure flash programmer - Check flash memory area in the memory map. - 0xFFC00000 - 0xFFFFFFFF - - Boot monitor program is at - 0xFFF00000 - - You can program on-board flash memory with VisionClick - flash programmer. Set the target flash device as: - - 29DL800B - - (?) The flash memory device in the board *is* 29LV800B, - but I cannot program it with '29LV800B' option. - (in VisionClick flash programming tools) - I don't know why... - -1.4. Save boot monitor program *IMPORTANT* - Upload boot monitor program from board to file. - boot monitor program starts at 0xFFF00000 - -1.5. Test flash memory programming - Try to erase boot program in the flash memory, - and re-write them. - *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE - BEFORE ERASING FLASH - -############################################################### -# 2. U-Boot setting -############################################################### - -2.1. Download U-Boot tarball at - ftp://ftp.denx.de - (The latest version is ppcboot-0.8.1.tar.bz2) - - To extract the archive use the following syntax : - > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf - - -2.2. Add the following lines in '.profile' - export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin - -2.3. Make board specific config, for example: - > cd ppcboot-0.8.1 - > make TQM860L_config - - Now we can build ppcboot bin files. - After make all, you must see these files in your - ppcboot root directory. - - ppcboot - ppcboot.bin - ppcboot.srec - ppcboot.map - -2.4. Make your own board directory into the - ppcboot-0.8.1/board - and make your board-specific files here. - - For exmanple, tqm8xx files are composed of - .depend : Nothing - Makefile : To make config file - config.mk : Sets base address - flash.c : Flash memory control files - ppcboot.lds : linker(ld) script? (I don't know this yet) - tqm8xx.c : DRAM control and board check routines - - And, add your board config lines in the - ppcboot-0.8.1/Makefile - - Finally, add config_(your board).h file in the - ppcboot-0.8.1/include/ - - I've made board/rpxlite directory, and just copied - tqm8xx settings for now. - - Rebuild ppcboot for rpxlite board: - > make rpxlite_config - > make - -############################################################### -# 3. U-Boot porting -############################################################### - -3.1. My RPXlite files are based on tqm8xx board files. - > cd board - > cp -r tqm8xx RPXLITE - > cd RPXLITE - > mv tqm8xx.c RPXLITE.c - > cd ../../include - > cp config_tqm8xx.h config_RPXLITE.h - -3.2. Modified files are: - board/RPXLITE/RPXLITE.c /* DRAM-related routines */ - board/RPXLITE/flash.c /* flash-related routines */ - board/RPXLITE/config.mk /* set text base address */ - arch/powerpc/cpu/mpc8xx/serial.c /* board specific register setting */ - include/config_RPXLITE.h /* board specific registers */ - - See 'reg_config.txt' for register values in detail. - -############################################################### -# 4. Running Linux -############################################################### - - -############################################################### -# Misc Information -############################################################### - -mem_config.txt: -=============== - -Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device -manufacturer id : 01 (AMD) -device id : 5B (AM29LV800B) -size : 4Mbyte -sector # : 19 - -Sector information : - -number start addr. size -00 FFC0_0000 64 -01 FFC1_0000 32 -02 FFC1_8000 32 -03 FFC2_0000 128 -04 FFC4_0000 256 -05 FFC8_0000 256 -06 FFCC_0000 256 -07 FFD0_0000 256 -08 FFD4_0000 256 -09 FFD8_0000 256 -10 FFDC_0000 256 -11 FFE0_0000 256 -12 FFE4_0000 256 -13 FFE8_0000 256 -14 FFEC_0000 256 -15 FFF0_0000 256 -16 FFF4_0000 256 -17 FFF8_0000 256 -18 FFFC_0000 256 - - -reg_config.txt: -=============== - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* SIU (System Interface Unit) */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ - - -/*### IMMR */ -/*### Internal Memory Map Register */ -/*### Chap. 11.4.1 */ - - ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */ - PARTNUM = 0x21 - MASKNUM = 0x00 - - => 0xFA20 2100 - ---------------------------------------------------------------------- - -/*### SIUMCR */ -/*### SIU Module Configuration Register */ -/*### Chap. 11.4.2 */ -/*### Offset : 0x0000 0000 */ - - EARB = 0 - EARP = 0 - DSHW = 0 - DBGC = 0 - DBPC = 0 - FRC = 0 - DLK = 0 - OPAR = 0 - PNCS = 0 - DPC = 0 - MPRE = 0 - MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */ - AEME = 0 - SEME = 0 - BSC = 0 - GB5E = 0 - B2DD = 0 - B3DD = 0 - - => 0x0000 0800 - ---------------------------------------------------------------------- - -/*### SYPCR */ -/*### System Protection Control Register */ -/*### Chap. 11.4.3 */ -/*### Offset : 0x0000 0004 */ - - SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */ - BMT = 0x06 /* BUS monitoring timing */ - BME = 1 /* BUS monitor enable */ - SWF = 1 - SWE = 0 /* SW watchdog disable */ - SWRI = 0 - SWP = 1 - - => 0xFFFF 0689 - ---------------------------------------------------------------------- - -/*### TESR */ -/*### Transfer Error Status Register */ -/*### Chap. 11.4.4 */ -/*### Offset : 0x0000 0020 */ - - IEXT = 0 - ITMT = 0 - IPB = 0000 - DEXT = 0 - DTMT = 0 - DPB = 0000 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIPEND */ -/*### SIU Interrupt Pending Register */ -/*### Chap. 11.5.4.1 */ -/*### Offset : 0x0000 0010 */ - - IRQ0~IRQ7 = 0 - LVL0~LVL7 = 0 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIMASK */ -/*### SIU Interrupt Mask Register */ -/*### Chap. 11.5.4.2 */ -/*### Offset : 0x0000 0014 */ - - IRM0~IRM7 = 0 /* Mask all interrupts */ - LVL0~LVL7 = 0 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIEL */ -/*### SIU Interrupt Edge/Level Register */ -/*### Chap. 11.5.4.3 */ -/*### Offset : 0x0000 0018 */ - - ED0~ED7 = 0 /* Low level triggered */ - WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */ - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIVEC */ -/*### SIU Interrupt Vector Register */ -/*### Chap. 11.5.4.4 */ -/*### Offset : 0x0000 001C */ - - INTC = 3C /* The lowest interrupt is pending..(?) */ - - => 0x3C00 0000 - ---------------------------------------------------------------------- - -/*### SWSR */ -/*### Software Service Register */ -/*### Chap. 11.7.1 */ -/*### Offset : 0x0000 001E */ - - SEQ = 0 - - => 0x0000 - ---------------------------------------------------------------------- - -/*### SDCR */ -/*### SDMA Configuration Register */ -/*### Chap. 20.2.1 */ -/*### Offset : 0x0000 0032 */ - - FRZ = 0 - RAID = 01 /* Priority level 5 (BR5) (normal operation) */ - - => 0x0000 0001 - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* UPMA (User Programmable Machine A) */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ - -/*### Chap. 16.6.4.1 */ -/*### Offset = 0x0000 017c */ - - T0 = CFFF CC24 /* Single Read */ - T1 = 0FFF CC04 - T2 = 0CAF CC04 - T3 = 03AF CC08 - T4 = 3FBF CC27 /* last */ - T5 = FFFF CC25 - T6 = FFFF CC25 - T7 = FFFF CC25 - T8 = CFFF CC24 /* Burst Read */ - T9 = 0FFF CC04 - T10 = 0CAF CC84 - T11 = 03AF CC88 - T12 = 3FBF CC27 /* last */ - T13 = FFFF CC25 - T14 = FFFF CC25 - T15 = FFFF CC25 - T16 = FFFF CC25 - T17 = FFFF CC25 - T18 = FFFF CC25 - T19 = FFFF CC25 - T20 = FFFF CC25 - T21 = FFFF CC25 - T22 = FFFF CC25 - T23 = FFFF CC25 - T24 = CFFF CC24 /* Single Write */ - T25 = 0FFF CC04 - T26 = 0CFF CC04 - T27 = 03FF CC00 - T28 = 3FFF CC27 /* last */ - T29 = FFFF CC25 - T30 = FFFF CC25 - T31 = FFFF CC25 - T32 = CFFF CC24 /* Burst Write */ - T33 = 0FFF CC04 - T34 = 0CFF CC80 - T35 = 03FF CC8C - T36 = 0CFF CC00 - T37 = 33FF CC27 /* last */ - T38 = FFFF CC25 - T39 = FFFF CC25 - T40 = FFFF CC25 - T41 = FFFF CC25 - T42 = FFFF CC25 - T43 = FFFF CC25 - T44 = FFFF CC25 - T45 = FFFF CC25 - T46 = FFFF CC25 - T47 = FFFF CC25 - T48 = C0FF CC24 /* Refresh */ - T49 = 03FF CC24 - T50 = 0FFF CC24 - T51 = 0FFF CC24 - T52 = 3FFF CC27 /* last */ - T53 = FFFF CC25 - T54 = FFFF CC25 - T55 = FFFF CC25 - T56 = FFFF CC25 - T57 = FFFF CC25 - T58 = FFFF CC25 - T59 = FFFF CC25 - T60 = FFFF CC25 /* Exception */ - T61 = FFFF CC25 - T62 = FFFF CC25 - T63 = FFFF CC25 - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* UPMB */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### Chap. 16.6.4.1 */ - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* MEMC */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### BR0 & OR0 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */ -/*### Flash memory */ - - BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFE00 0001 - - AM = 1111 1110 0000 0000 0 /* 32MBytes */ - ATM = 000 - CSNT/SAM = 0 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0100 /* cycle length = 4 */ - SETA = 0 - TRLX = 0 - EHTR = 0 - - => 0xFE00 0140 - -/*### BR1 & OR1 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */ -/*### SDRAM */ - - BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 1 /* UPMA */ - V = 1 /* Valid */ - - => 0x0000 0081 - - AM = 1111 1110 0000 0000 /* 32MBytes */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 11 - BIH = 0 - SCY = 0000 /* cycle length = 0 */ - SETA = 0 - TRLX = 0 - EHTR = 0 - - => 0xFE00 0E00 - -/*### BR2 & OR2 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */ - - BR2 & OR2 = 0x0000 0000 /* Not used */ - -/*### BR3 & OR3 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */ -/*### BCSR */ - - BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFA40 0001 - - AM = 1111 1111 0111 1111 1 /* (?) */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0001 /* cycle length = 1 */ - SETA = 0 - TRLX = 0 - - => 0xFF7F 8910 - -/*### BR4 & OR4 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */ -/*### NVRAM & SRAM */ - - BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */ - AT = 000 - PS = 01 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFA00 0401 - - AM = 1111 1111 1111 1000 0 /* 8MByte */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0111 /* cycle length = 7 */ - SETA = 0 - TRLX = 0 - - => 0xFFF8 0970 - -/*### BR5 & OR5 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */ - - BR5 & OR5 = 0x0000 0000 /* Not used */ - -/*### BR6 & OR6 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */ - - BR6 & OR6 = 0x0000 0000 /* Not used */ - -/*### BR7 & OR7 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */ - - BR7 & OR7 = 0x0000 0000 /* Not used */ - -/*### MAR */ -/*### Memory Address Register */ -/*### Chap. 16.4.7 */ -/*### Offset : 0x0000 0164 */ - - MA = External memory address - -/*### MCR */ -/*### Memory Command Register */ -/*### Chap. 16.4.5 */ -/*### Offset : 0x0000 0168 */ - - OP = xx /* Command op code */ - UM = 1 /* Select UPMA */ - MB = 001 /* Select CS1 */ - MCLF = xxxx /* Loop times */ - MAD = xx xxxx /* Memory array index */ - -/*### MAMR */ -/*### Machine A Mode Register */ -/*### Chap. 16.4.4 */ -/*### Offset : 0x0000 0170 */ - - PTA = 0101 1000 - PTAE = 1 /* Periodic timer A enabled */ - AMA = 010 - DSA = 00 - G0CLA = 000 - GPLA4DIS = 1 - RLFA = 0100 - WLFA = 0011 - TLFA = 0000 - - => 0x58A0 1430 - -/*### MBMR */ -/*### Machine B Mode Register */ -/*### Chap. 16.4.4 */ -/*### Offset : 0x0000 0174 */ - - PTA = 0100 1110 - PTAE = 0 /* Periodic timer B disabled */ - AMA = 000 - DSA = 00 - G0CLA = 000 - GPLA4DIS = 1 - RLFA = 0000 - WLFA = 0000 - TLFA = 0000 - - => 0x4E00 1000 - -/*### MSTAT */ -/*### Memory Status Register */ -/*### Chap. 16.4.3 */ -/*### Offset : 0x0000 0178 */ - - PER0~PER7 = Parity error - WPER = Write protection error - - => 0x0000 - -/*### MPTPR */ -/*### Memory Periodic Timer Prescaler Register */ -/*### Chap. 16.4.8 */ -/*### Offset : 0x0000 017A */ - - PTP = 0000 1000 /* Divide by 8 */ - - => 0x0800 - -/*### MDR */ -/*### Memory Data Register */ -/*### Chap. 16.4.6 */ -/*### Offset : 0x0000 017C */ - - MD = Memory data contains the RAM array word - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* TIMERS */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### TBREFx */ -/*### Timebase Reference Registers */ -/*### Chap. 11.9.2 */ -/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */ -/*### (Locked) */ - - TBREFF0 = 0xFFFF FFFF - TBREFF1 = 0xFFFF FFFF - ---------------------------------------------------------------------- - -/*### TBSCR */ -/*### Timebase Status and Control Registers */ -/*### Chap. 11.9.3 */ -/*### Offset : 0x0000 0200 */ -/*### (Locked) */ - - TBIRQ = 00000000 - REF0 = 0 - REF1 = 0 - REFE0 = 0 /* Reference interrupt disable */ - REFE1 = 0 - TBF = 1 - TBE = 1 /* Timebase enable */ - - => 0x0003 - ---------------------------------------------------------------------- - -/*### RTCSC */ -/*### Real-Time Clock Status and Control Registers */ -/*### Chap. 11.10.1 */ -/*### Offset : 0x0000 0220 */ -/*### (Locked) */ - - RTCIRQ = 00000000 - SEC = 1 - ALR = 0 - 38K = 0 /* PITRTCLK is driven by 32.768KHz */ - SIE = 0 - ALE = 0 - RTF = 0 - RTE = 1 /* Real-Time clock enabled */ - - => 0x0081 - ---------------------------------------------------------------------- - -/*### RTC */ -/*### Real-Time Clock Registers */ -/*### Chap. 11.10.2 */ -/*### Offset : 0x0000 0224 */ -/*### (Locked) */ - - RTC = Real time clock measured in second - ---------------------------------------------------------------------- - -/*### RTCAL */ -/*### Real-Time Clock Alarm Registers */ -/*### Chap. 11.10.3 */ -/*### Offset : 0x0000 022C */ -/*### (Locked) */ - - ALARM = 0xFFFF FFFF - ---------------------------------------------------------------------- - -/*### RTSEC */ -/*### Real-Time Clock Alarm Second Registers */ -/*### Chap. 11.10.4 */ -/*### Offset : 0x0000 0228 */ -/*### (Locked) */ - - COUNTER = Counter bits(fraction of a second) - ---------------------------------------------------------------------- - -/*### PISCR */ -/*### Periodic Interrupt Status and Control Register */ -/*### Chap. 11.11.1 */ -/*### Offset : 0x0000 0240 */ -/*### (Locked) */ - - PIRQ = 0 - PS = 0 /* Write 1 to clear */ - PIE = 0 - PITF = 1 - PTE = 0 /* PIT disabled */ - ---------------------------------------------------------------------- - -/*### PITC */ -/*### PIT Count Register */ -/*### Chap. 11.11.2 */ -/*### Offset : 0x0000 0244 */ -/*### (Locked) */ - - PITC = PIT count - ---------------------------------------------------------------------- - -/*### PITR */ -/*### PIT Register */ -/*### Chap. 11.11.3 */ -/*### Offset : 0x0000 0248 */ -/*### (Locked) */ - - PIT = PIT count /* Read only */ - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* CLOCKS */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - - ---------------------------------------------------------------------- - -/*### SCCR */ -/*### System Clock and Reset Control Register */ -/*### Chap. 15.6.1 */ -/*### Offset : 0x0000 0280 */ -/*### (Locked) */ - - COM = 11 /* Clock output disabled */ - TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */ - RTDIV = 0 /* The clock is divided by 4 */ - RTSEL = 0 /* OSCM(Crystal oscillator) is selected */ - CRQEN = 0 - PRQEN = 0 - EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */ - DFSYNC = 00 /* Divided by 1 (normal operation) */ - DFBRG = 00 /* Divided by 1 (normal operation) */ - DFNL = 000 - DFNH = 000 - - => 0x6200 0000 - ---------------------------------------------------------------------- - -/*### PLPRCR */ -/*### PLL, Low-Power, and Reset Control Register */ -/*### Chap. 15.6.2 */ -/*### Offset : 0x0000 0284 */ -/*### (Locked) */ - - MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */ - SPLSS = 0 - TEXPS = 0 - TMIST = 0 - CSRC = 0 /* The general system clock is generated by the DFNH field */ - LPM = 00 /* Normal high/normal low mode */ - CSR = 0 - LOLRE = 0 - FIOPD = 0 - - => 0x0050 0000 - ---------------------------------------------------------------------- - -/*### RSR */ -/*### Reset Status Register */ -/*### Chap. 12.2 */ -/*### Offset : 0x0000 0288 */ -/*### (Locked) */ - - EHRS = External hard reset - ESRS = External soft reset - LLRS = Loss-of-lock reset - SWRS = Software watchdog reset - CSRS = Check stop reset - DBHRS = Debug port hard reset - DBSRS = Debug port soft reset - JTRS = JTAG reset - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* DMA */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### SDSR */ -/*### SDMA Status Register */ -/*### Chap. 20.2.2 */ -/*### Offset : 0x0000 0908 */ - - SBER = 0 /* SDMA channel bus error */ - DSP2 = 0 /* DSP chain2 (Tx) interrupt */ - DSP1 = 0 /* DSP chain1 (Rx) interrupt */ - - => 0x00 - -/*### SDMR */ -/*### SDMA Mask Register */ -/*### Chap. 20.2.3 */ -/*### Offset : 0x0000 090C */ - - SBER = 0 - DSP2 = 0 - DSP1 = 0 /* All interrupts are masked */ - - => 0x00 - -/*### SDAR */ -/*### SDMA Address Register */ -/*### Chap. 20.2.4 */ -/*### Offset : 0x0000 0904 */ - - AR = 0xxxxx xxxx /* current system address */ - - => 0xFA20 23AC - -/*### IDSRx */ -/*### IDMA Status Register */ -/*### Chap. 20.3.3.2 */ -/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */ - - AD = 0 - DONE = 0 - OB = 0 - - => 0x00 - -/*### IDMRx */ -/*### IDMA Mask Register */ -/*### Chap. 20.3.3.3 */ -/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */ - - AD = 0 - DONE = 0 - OB = 0 diff --git a/board/RPXlite/README.PlanetCore b/board/RPXlite/README.PlanetCore deleted file mode 100644 index b73c5f5a87d..00000000000 --- a/board/RPXlite/README.PlanetCore +++ /dev/null @@ -1,163 +0,0 @@ -After several heart-struck failure, I got one workable way to program -each other in FLASH between PlanetCore and U-Boot. - -Hardware Platform : RPXlite DW(EP 823 H1 DW) - -1. From U-Boot to PlanetCore - -Utilities : PlanetCore Boot Loader - PCL200.mot - -[root@sam tftpboot]# ppc_8xx-objcopy -O ppcboot -PCL200.mot pcl200.bin - -[Target Operation] -u-boot>t 100000 pcl200.bin -u-boot>go 0x100000 -## Starting application at 0x00100000 ... - -MPC8xx PlanetCore Flash Burner v2.00 -Copyright 2001 Embedded Planet. All rights reserved. - -Construct Flash Device.....done. - - -Program MPC8xx PlanetCore Boot Loader v2.00 -Built Sep 19, 2001 at 14:34:42 -Image located from FC000000 to FC01B5D1. -(Skipping an image, only loading low boot image) - -Low boot board detected, skipping high boot image. -Erasing, programming and verifying will start in 20 -seconds -Press P to start immediately or ESC to cancel -Press Space or Enter for more options. -.............. - -Erasing -Programming -FLASH programmed successfully! -Press R to induce a hard reset - -MPC8xx PlanetCore Boot Loader v2.00 -Copyright 2001 Embedded Planet. All rights reserved. -DRAM available size = 64 MB -wvCV -DRAM OK -> - -2. From PlanetCore to U-Boot - -Utilities : PlanetCore FLASH Burner - PCB200.mot - -Use Flash Burner to finish the work: - -First, TFTP the U-Boot image file to RAM; For example, -RPXlite_DW.bin to 0x400000 -Second, TFTP FLASH Burner to RAM; For example, -0x100000 -Third, run the FLASH Burner and Program the U-Boot -image into the correct location in FLASH. - -[Target Operation] -MPC8xx PlanetCore Boot Loader v2.00 -Copyright 2001 Embedded Planet. All rights reserved. -DRAM available size = 64 MB -wvCV -DRAM OK ->t -Load using tftp via Ethernet -Enter server IP address <172.16.115.6> : -Enter server filename : RPXlite_DW.bin -Enter (B)inary or (S)record input mode : B -Enter address offset : <00400000 hex> : - -Total bytes = 120096 in 232184 uSecs -Loaded addresses 00400000 through 0041D51F. -Start address = 00400000 ->t -Load using tftp via Ethernet -Enter server IP address <172.16.115.6> : -Enter server filename : PCB200.mot -Enter (B)inary or (S)record input mode : S -Enter address offset : <00000000 hex> : -.512.1024..2048....4096..... -Total bytes = 326280 in 2570249 uSecs -Loaded addresses 00100000 through 0011BB51. -Start address = 00100000 ->go -[Go 00100000] - -MPC8xx PlanetCore Flash Burner v2.00 -Copyright 2001 Embedded Planet. All rights reserved. - -Construct Flash Device.....done. - -Bad start address -Start = 0xFFFFFFFF, target = 0xFFFFFFFF, length = -0xFFFFFFFF -Forcing Menu Interface - -h[elp] Show commands. -c[ode] Show information on code to be loaded. -di[splay] Display all flash sections. -du[mp] Dump memory. d ? for more info. -e[rase] Erase flash sections. -f[ill] Fill flash sections. -im[age] Toggle load high, low, or both flash -images. -in[fo] Show flash information. -ma[p] Show memory map. -mo[dify] Modify memory. m ? for more info. -p[rogram] Erase, program, and verify now. -reset Restart the loader. -s[how] Show flash sections to erase and program. -t[est] Test flash sections. -q[uit] Quit without programming. -#program 400000 ff000000 1D51F -doProgram( 400000 ff000000 1D51F ) - -Start = 0x00400000, target = 0xFF000000, length = -0x0001D51F -Erasing sector 0xFF000000, length 0x008000. -Erasing sector 0xFF008000, length 0x008000. -Erasing sector 0xFF010000, length 0x008000. -Erasing sector 0xFF018000, length 0x008000. -Programming FF000000 through FF01D51E -FLASH programmed successfully! -Press R to induce a hard reset - -Forcing Hard Reset by MachineCheck and -ResetOnCheckstop... - -U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) - -CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB -D-Cache -Board: RPXlite_DW -DRAM: 64 MB -FLASH: 16 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET -u-boot> - -------------------------------------------------- - -Well, sometimes network function of PlanetCore couldn't work when -switching from U-Boot to PlanetCore. For example, you couldn't -download a file from HOST PC via TFTP. Don't worry, just restart your -HOST PC and everything would work as smooth as clockwork. I don't -know the reason WHY:-) - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Merry Christmas and Happy New Year! - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -===== -Best regards, - -Sam diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c deleted file mode 100644 index 08575a4930c..00000000000 --- a/board/RPXlite/RPXlite.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * DRAM related UPMA register values are modified. - * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = { - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, - 0x0CFFCC00, 0x33FFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXlite\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size10; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000000; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 10 column mode - */ - - size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - return (size10); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} diff --git a/board/RPXlite/flash.c b/board/RPXlite/flash.c deleted file mode 100644 index 21b11d4e90c..00000000000 --- a/board/RPXlite/flash.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -/* volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; */ -/* volatile memctl8xx_t *memctl = &immap->im_memctl; */ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; -%%%*/ - /* Re-do sizing to get full correct info */ - - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0x00AA00AA ; - addr[0x555] = 0x00550055 ; - addr[0xAAA] = 0x00900090 ; - - value = addr[0] ; - - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - - switch (value & 0x00FF00FF) { - case (AMD_ID_LV400T & 0x00FF00FF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & 0x00FF00FF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & 0x00FF00FF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & 0x00FF00FF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /*%%% Size doubled by yooth */ - break; /* => 4 MB */ - - case (AMD_ID_LV160T & 0x00FF00FF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & 0x00FF00FF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /*%%% sector start address modified */ - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds deleted file mode 100644 index 0eb2fba00c2..00000000000 --- a/board/RPXlite/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug deleted file mode 100644 index b9c84c77d64..00000000000 --- a/board/RPXlite/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index 2125e9042f4..1faa906c379 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1246,5 +1246,3 @@ Orphan powerpc 74xx_7xx - - evb64260 Orphan powerpc mpc824x - - mousse MOUSSE - - Orphan powerpc mpc8260 - - - rsdproto - - Orphan powerpc mpc8260 - - rpxsuper RPXsuper - - -Orphan powerpc mpc8xx - - - RPXClassic - - -Orphan powerpc mpc8xx - - - RPXlite - - diff --git a/doc/README.scrapyard b/doc/README.scrapyard index b068544c3ba..99155007df7 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,8 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +RPXClassic powerpc mpc8xx - 2014-04-04 +RPXlite powerpc mpc8xx - 2014-04-04 genietv powerpc mpc8xx - 2014-04-04 mbx8xx powerpc mpc8xx - 2014-04-04 nx823 powerpc mpc8xx - 2014-04-04 diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c index 37325838381..663827780e9 100644 --- a/drivers/pcmcia/mpc8xx_pcmcia.c +++ b/drivers/pcmcia/mpc8xx_pcmcia.c @@ -211,7 +211,7 @@ static u_int m8xx_get_graycode(u_int size) #if 0 -#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) +#if defined(CONFIG_RPXLITE) /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. * SYPCR is write once only, therefore must the slowest memory be faster diff --git a/drivers/pcmcia/rpx_pcmcia.c b/drivers/pcmcia/rpx_pcmcia.c index c7c425b93cf..5b24f0bfbe4 100644 --- a/drivers/pcmcia/rpx_pcmcia.c +++ b/drivers/pcmcia/rpx_pcmcia.c @@ -18,7 +18,7 @@ #endif #if defined(CONFIG_PCMCIA) \ - && (defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)) + && defined(CONFIG_RPXLITE) #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" @@ -70,4 +70,4 @@ static int pcmcia_hardware_disable(int slot) #endif -#endif /* CONFIG_PCMCIA && (CONFIG_RPXCLASSIC || CONFIG_RPXLITE) */ +#endif /* CONFIG_PCMCIA && CONFIG_RPXLITE */ diff --git a/include/common.h b/include/common.h index 580615b9ef1..baf361b3e55 100644 --- a/include/common.h +++ b/include/common.h @@ -505,10 +505,6 @@ extern ssize_t spi_read (uchar *, int, uchar *, int); extern ssize_t spi_write (uchar *, int, uchar *, int); #endif -#ifdef CONFIG_RPXCLASSIC -void rpxclassic_init (void); -#endif - void rpxlite_init (void); #ifdef CONFIG_HERMES diff --git a/include/commproc.h b/include/commproc.h index 605aac2ec22..29a3e61e803 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -954,41 +954,6 @@ typedef struct scc_enet { #endif /* CONFIG_QS860T */ -/*** RPXCLASSIC *****************************************************/ - -#ifdef CONFIG_RPXCLASSIC - -#ifdef CONFIG_FEC_ENET - -# define FEC_ENET /* use FEC for EThernet */ -# undef SCC_ENET - -#else /* ! CONFIG_FEC_ENET */ - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00001000) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) - -#endif /* CONFIG_FEC_ENET */ - -#endif /* CONFIG_RPXCLASSIC */ - /*** RPXLITE ********************************************************/ #ifdef CONFIG_RPXLITE diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h deleted file mode 100644 index 0f07d0cfe97..00000000000 --- a/include/configs/RPXClassic.h +++ /dev/null @@ -1,483 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define RPXClassic_50MHz - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_RPXCLASSIC 1 - -#define CONFIG_SYS_TEXT_BASE 0xff000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ - -/* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */ -#define CONFIG_FEC_ENET -#ifdef CONFIG_FEC_ENET -#define CONFIG_SYS_DISCOVER_PHY 1 -#define CONFIG_MII 1 -#endif /* CONFIG_FEC_ENET */ -#define CONFIG_MISC_INIT_R - -/* Video console (graphic: Epson SED13806 on ECCX board, no keyboard */ -#if 1 -#define CONFIG_VIDEO_SED13806 -#define CONFIG_NEC_NL6448BC20 -#define CONFIG_VIDEO_SED13806_16BPP - -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#endif - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_ZERO_BOOTDELAY_CHECK 1 - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ELF - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_RESET_ADDRESS 0x80000000 -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFA200000 - -/*----------------------------------------------------------------------------- - * I2C Configuration - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0x34 - - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ - -#if defined(CONFIG_SYS_I2C_SOFT) -#define CONFIG_SYS_I2C 1 -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000010) -#define I2C_TRISTATE (iop->pdir &= ~0x00000010) -#define I2C_READ ((iop->pdat & 0x00000010) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ - else iop->pdat &= ~0x00000010 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ - else iop->pdat &= ~0x00000020 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - - -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x34 -#endif - -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 - -#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE 0xFF000000 -/*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if 0 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x8000 -#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ -#else -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_ADDR 0xfa000100 -#define CONFIG_ENV_SIZE 0x1000 -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/* #define CONFIG_SYS_DER 0x2002000F */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */ -#define CONFIG_SYS_OR3_PRELIM 0xff7f8970 -#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CONFIG_SYS_OR4_PRELIM 0xFFF80970 - -/* ECCX CS settings */ -#define SED13806_OR 0xFFC00108 /* - 4 Mo - - Burst inhibit - - external TA */ -#define SED13806_REG_ADDR 0xa0000000 -#define SED13806_ACCES 0x801 /* 16 bit access */ - - -/* Global definitions for the ECCX board */ -#define ECCX_CSR_ADDR (0xfac00000) -#define ECCX_CSR8_OFFSET (0x8) -#define ECCX_CSR11_OFFSET (0xB) -#define ECCX_CSR12_OFFSET (0xC) - -#define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET) -#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET) -#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET) - - -#define REG_GPIO_CTRL 0x008 - -/* Definitions for CSR8 */ -#define ECCX_ENEPSON 0x80 /* Bit 0: - 0= disable and reset SED1386 - 1= enable SED1386 */ -/* Bit 1: 0= SED1386 in Big Endian mode */ -/* 1= SED1386 in little endian mode */ -#define ECCX_LE 0x40 -#define ECCX_BE 0x00 - -/* Bit 2,3: Selection */ -/* 00 = Disabled */ -/* 01 = CS2 is used for the SED1386 */ -/* 10 = CS5 is used for the SED1386 */ -/* 11 = reserved */ -#define ECCX_CS2 0x10 -#define ECCX_CS5 0x20 - -/* Definitions for CSR12 */ -#define ECCX_ID 0x02 -#define ECCX_860 0x01 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 58 - -/* - * Refresh clock Prescalar - */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ - MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) - -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* Configuration variable added by yooth. */ -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_MIIRST 0x80 -#define BCSR2_MIIPWRDWN 0x40 -#define BCSR2_MIICTL 0x08 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - - -/* - * Environment setting - */ - -/* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */ -/* #define CONFIG_IPADDR 10.10.106.1 */ -/* #define CONFIG_SERVERIP 10.10.104.11 */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h deleted file mode 100644 index a28230a5d74..00000000000 --- a/include/configs/RPXlite.h +++ /dev/null @@ -1,395 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define RPXLite_50MHz - -/* - * High Level Configuration Options - * (easy to change) - */ - -#undef CONFIG_MPC860 -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_RPXLITE 1 - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 40000 /* 40 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* Software (bit-bang) I2C driver configuration */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if (bit) \ - immr->im_cpm.cp_pbdat |= PB_SDA; \ - else \ - immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if (bit) \ - immr->im_cpm.cp_pbdat |= PB_SCL; \ - else \ - immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -/* M41T11 Serial Access Timekeeper(R) SRAM */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -/* play along with the linux driver */ -#define CONFIG_SYS_M41T11_BASE_YEAR 1900 - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_RESET_ADDRESS 0x09900000 - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFA200000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */ -#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910 -#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 58 - -/* - * Refresh clock Prescalar - */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ - MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) - -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* Configuration variable added by yooth. */ -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_ENPA5HDR 0x08 /* USB Control */ -#define BCSR2_ENUSBCLK 0x10 -#define BCSR2_USBPWREN 0x20 -#define BCSR2_USBSPD 0x40 -#define BCSR2_USBSUSP 0x80 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - -#endif /* __CONFIG_H */ diff --git a/include/pcmcia.h b/include/pcmcia.h index 1ad3e636a9c..952a67c17c2 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -22,7 +22,7 @@ #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) /* The RPX series use SLOT_B */ -#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) +#if defined(CONFIG_RPXLITE) # define CONFIG_PCMCIA_SLOT_B #elif defined(CONFIG_FADS) /* The FADS series are a mess */ # if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821) diff --git a/post/cpu/mpc8xx/ether.c b/post/cpu/mpc8xx/ether.c index 53c0e4dfda1..d12250018ae 100644 --- a/post/cpu/mpc8xx/ether.c +++ b/post/cpu/mpc8xx/ether.c @@ -365,11 +365,6 @@ static void scc_init (int scc_index) immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC | SCC_PSMR_NIB22 | SCC_PSMR_LPB; -#ifdef CONFIG_RPXCLASSIC - *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; - *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); -#endif - #ifdef CONFIG_RPXLITE *((uchar *) BCSR0) |= BCSR0_ETHEN; #endif @@ -386,8 +381,6 @@ static void scc_init (int scc_index) */ #if defined (CONFIG_FADS) udelay (10000); /* wait 10 ms */ -#elif defined(CONFIG_RPXCLASSIC) - udelay (100000); /* wait 100 ms */ #endif } diff --git a/post/cpu/mpc8xx/uart.c b/post/cpu/mpc8xx/uart.c index 25d63d8120f..5214c71b085 100644 --- a/post/cpu/mpc8xx/uart.c +++ b/post/cpu/mpc8xx/uart.c @@ -106,7 +106,7 @@ static void smc_init (int smc_index) ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2); #endif -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) +#if defined(CONFIG_RPXLITE) /* Enable Monitor Port Transceiver */ *((uchar *) BCSR0) |= BCSR0_ENMONXCVR; #endif -- cgit v1.3.1 From 36bf57b6fb37089510b6dcfa6487dc5e2445c9f2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Apr 2014 15:25:11 +0900 Subject: arm: remove lubbock board support Enough time has passed since this board was moved to Orphan. Remove. - Remove board/lubbock/* - Remove include/configs/lubbock.h - Cleanup defined(CONFIG_LUBBOCK) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada --- board/lubbock/Makefile | 8 - board/lubbock/flash.c | 412 ---------------------------------------------- board/lubbock/lubbock.c | 81 --------- boards.cfg | 1 - doc/README.scrapyard | 1 + drivers/net/lan91c96.h | 6 - include/configs/lubbock.h | 236 -------------------------- 7 files changed, 1 insertion(+), 744 deletions(-) delete mode 100644 board/lubbock/Makefile delete mode 100644 board/lubbock/flash.c delete mode 100644 board/lubbock/lubbock.c delete mode 100644 include/configs/lubbock.h (limited to 'drivers') diff --git a/board/lubbock/Makefile b/board/lubbock/Makefile deleted file mode 100644 index 8aa513ac44f..00000000000 --- a/board/lubbock/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := lubbock.o flash.o diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c deleted file mode 100644 index f6bb22c2e47..00000000000 --- a/board/lubbock/flash.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c deleted file mode 100644 index 0daff9abf14..00000000000 --- a/board/lubbock/lubbock.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of Lubbock-Board */ - gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Configure GPIO6 and GPIO8 as OUT, AF1. */ - setbits_le32(GPDR0, (1 << 6) | (1 << 8)); - clrsetbits_le32(GAFR0_L, (3 << 12) | (3 << 16), (1 << 12) | (1 << 16)); - - return 0; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/boards.cfg b/boards.cfg index 6dd9e7513a0..c83aff3b141 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1241,4 +1241,3 @@ Orphan powerpc ppc4xx - sandburst metrobox # The following were move to "Orphan" in September, 2013 Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski -Orphan arm pxa - - - lubbock - (dead address) Kyle Harris diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 0e4d329ed18..15c39e76758 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +lubbock arm pxa - 2014-04-04 Kyle Harris MOUSSE powerpc mpc824x - 2014-04-04 rsdproto powerpc mpc8260 - 2014-04-04 RPXsuper powerpc mpc8260 - 2014-04-04 diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h index 2f0d640adec..3e914ce5ad5 100644 --- a/drivers/net/lan91c96.h +++ b/drivers/net/lan91c96.h @@ -58,13 +58,7 @@ typedef unsigned long int dword; #ifdef CONFIG_CPU_PXA25X -#ifdef CONFIG_LUBBOCK -#define SMC_IO_SHIFT 2 -#undef USE_32_BIT - -#else #define SMC_IO_SHIFT 0 -#endif #define SMCREG(edev, r) ((edev)->iobase+((r)< - * Marius Groeger - * - * Configuation settings for the LUBBOCK board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */ -#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ -#define CONFIG_LCD 1 -#ifdef CONFIG_LCD -#define CONFIG_PXA_LCD -#define CONFIG_SHARP_LM8V31 -#endif -#define CONFIG_MMC -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_TEXT_BASE 0x0 - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x0C000000 - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ -#define CONFIG_CONS_INDEX 3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_FAT - - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.250 -#define CONFIG_BOOTCOMMAND "bootm 80000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" -#define CONFIG_CMDLINE_TAG -#define CONFIG_TIMESTAMP - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ -#else -#endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ - -#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ - -#ifdef CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 -#define CONFIG_SYS_DRAM_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 - -#define FPGA_REGS_BASE_PHYSICAL 0x08000000 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x00008000 -#define CONFIG_SYS_GPSR1_VAL 0x00FC0382 -#define CONFIG_SYS_GPSR2_VAL 0x0001FFFF -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0x0060A800 -#define CONFIG_SYS_GPDR1_VAL 0x00FF0382 -#define CONFIG_SYS_GPDR2_VAL 0x0001C000 -#define CONFIG_SYS_GAFR0_L_VAL 0x98400000 -#define CONFIG_SYS_GAFR0_U_VAL 0x00002950 -#define CONFIG_SYS_GAFR1_L_VAL 0x000A9558 -#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA -#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 -#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 - -#define CONFIG_SYS_PSSR_VAL 0x20 - -#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 -#define CONFIG_SYS_CKEN 0x0 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x23F223F2 -#define CONFIG_SYS_MSC1_VAL 0x3FF1A441 -#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1 -#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9 -#define CONFIG_SYS_MDREFR_VAL 0x00018018 -#define CONFIG_SYS_MDMRS_VAL 0x00000000 - -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 -#define CONFIG_SYS_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00010504 -#define CONFIG_SYS_MCMEM1_VAL 0x00010504 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00004715 -#define CONFIG_SYS_MCIO1_VAL 0x00004715 - -#define _LED 0x08000010 -#define LED_BLANK 0x08000040 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* NOTE: many default partitioning schemes assume the kernel starts at the - * second sector, not an environment. You have been warned! - */ -#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) -#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) - - -/* - * FPGA Offsets - */ -#define WHOAMI_OFFSET 0x00 -#define HEXLED_OFFSET 0x10 -#define BLANKLED_OFFSET 0x40 -#define DISCRETELED_OFFSET 0x40 -#define CNFG_SWITCHES_OFFSET 0x50 -#define USER_SWITCHES_OFFSET 0x60 -#define MISC_WR_OFFSET 0x80 -#define MISC_RD_OFFSET 0x90 -#define INT_MASK_OFFSET 0xC0 -#define INT_CLEAR_OFFSET 0xD0 -#define GP_OFFSET 0x100 - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From f1ae382dfd3850f4fbf34d794a31b8a1d1a5c389 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 7 Apr 2014 16:41:46 +0100 Subject: pcnet: access descriptor rings & init block uncached The prior accesses to the descriptor rings & init block via cached memory had a few issues: - The memory needs cache flushes or invalidation at the appropriate times, but was not necessarily aligned on cache line boundaries. This could lead to data being incorrectly lost or written back to RAM at the wrong time. - There are points where ordering of writes to the memory is important, but because it's cached memory the pcnet controller would see cache lines written back ordered by address. This could occasionally lead to hardware seeing descriptors in an incorrect state. - Flushing the cache constantly is inefficient. So, to avoid all of those issues simply access the descriptors & init block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is used to do this (retrieving an address in kseg1) as I could see no existing generic solution. Since the MIPS Malta board is the only user of the pcnet driver, hopefully this doesn't matter. Signed-off-by: Paul Burton --- drivers/net/pcnet.c | 66 ++++++++++++++++++++++++++++------------------------- 1 file changed, 35 insertions(+), 31 deletions(-) (limited to 'drivers') diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 71a3110712d..8c334c7abcc 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -71,10 +71,14 @@ struct pcnet_init_block { u32 reserved2; }; -typedef struct pcnet_priv { +struct pcnet_uncached_priv { struct pcnet_rx_head rx_ring[RX_RING_SIZE]; struct pcnet_tx_head tx_ring[TX_RING_SIZE]; struct pcnet_init_block init_block; +}; + +typedef struct pcnet_priv { + struct pcnet_uncached_priv *uc; /* Receive Buffer space */ unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; int cur_rx; @@ -283,6 +287,7 @@ static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr) static int pcnet_init(struct eth_device *dev, bd_t *bis) { + struct pcnet_uncached_priv *uc; int i, val; u32 addr; @@ -325,24 +330,31 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); addr = (addr + 0xf) & ~0xf; lp = (pcnet_priv_t *)addr; + + addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc)); + flush_dcache_range(addr, addr + sizeof(*lp->uc)); + addr = UNCACHED_SDRAM(addr); + lp->uc = (struct pcnet_uncached_priv *)addr; } - lp->init_block.mode = cpu_to_le16(0x0000); - lp->init_block.filter[0] = 0x00000000; - lp->init_block.filter[1] = 0x00000000; + uc = lp->uc; + + uc->init_block.mode = cpu_to_le16(0x0000); + uc->init_block.filter[0] = 0x00000000; + uc->init_block.filter[1] = 0x00000000; /* * Initialize the Rx ring. */ lp->cur_rx = 0; for (i = 0; i < RX_RING_SIZE; i++) { - lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); - lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); - lp->rx_ring[i].status = cpu_to_le16(0x8000); + uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); + uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); + uc->rx_ring[i].status = cpu_to_le16(0x8000); PCNET_DEBUG1 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, - lp->rx_ring[i].base, lp->rx_ring[i].buf_length, - lp->rx_ring[i].status); + uc->rx_ring[i].base, uc->rx_ring[i].buf_length, + uc->rx_ring[i].status); } /* @@ -351,34 +363,34 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) */ lp->cur_tx = 0; for (i = 0; i < TX_RING_SIZE; i++) { - lp->tx_ring[i].base = 0; - lp->tx_ring[i].status = 0; + uc->tx_ring[i].base = 0; + uc->tx_ring[i].status = 0; } /* * Setup Init Block. */ - PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block); + PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block); for (i = 0; i < 6; i++) { - lp->init_block.phys_addr[i] = dev->enetaddr[i]; - PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]); + lp->uc->init_block.phys_addr[i] = dev->enetaddr[i]; + PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]); } - lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | + uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | RX_RING_LEN_BITS); - lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring); - lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring); - flush_dcache_range((unsigned long)lp, (unsigned long)&lp->rx_buf); + uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring); + uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring); PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", - lp->init_block.tlen_rlen, - lp->init_block.rx_ring, lp->init_block.tx_ring); + uc->init_block.tlen_rlen, + uc->init_block.rx_ring, uc->init_block.tx_ring); /* * Tell the controller where the Init Block is located. */ - addr = PCI_TO_MEM(dev, &lp->init_block); + barrier(); + addr = PCI_TO_MEM(dev, &lp->uc->init_block); pcnet_write_csr(dev, 1, addr & 0xffff); pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); @@ -408,7 +420,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) { int i, status; - struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; + struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx]; PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet); @@ -418,8 +430,6 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) /* Wait for completion by testing the OWN bit */ for (i = 1000; i > 0; i--) { - invalidate_dcache_range((unsigned long)entry, - (unsigned long)entry + sizeof(*entry)); status = le16_to_cpu(entry->status); if ((status & 0x8000) == 0) break; @@ -442,8 +452,6 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) entry->misc = 0x00000000; entry->base = PCI_TO_MEM_LE(dev, packet); entry->status = cpu_to_le16(status); - flush_dcache_range((unsigned long)entry, - (unsigned long)entry + sizeof(*entry)); /* Trigger an immediate send poll. */ pcnet_write_csr(dev, 0, 0x0008); @@ -463,9 +471,7 @@ static int pcnet_recv (struct eth_device *dev) u16 status; while (1) { - entry = &lp->rx_ring[lp->cur_rx]; - invalidate_dcache_range((unsigned long)entry, - (unsigned long)entry + sizeof(*entry)); + entry = &lp->uc->rx_ring[lp->cur_rx]; /* * If we own the next entry, it's a new packet. Send it up. */ @@ -505,8 +511,6 @@ static int pcnet_recv (struct eth_device *dev) } } entry->status |= cpu_to_le16(0x8000); - flush_dcache_range((unsigned long)entry, - (unsigned long)entry + sizeof(*entry)); if (++lp->cur_rx >= RX_RING_SIZE) lp->cur_rx = 0; -- cgit v1.3.1 From a354ddc3d7412c6d7cc702de60be32e580ccf348 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 7 Apr 2014 16:41:47 +0100 Subject: pcnet: align rx buffers for cache invalidation The RX buffers are invalidated when a packet is received, however they were not suitably cache-line aligned. Allocate them seperately to the pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure suitable alignment for the cache invalidation, preventing anything else being placed in the same lines & lost. Signed-off-by: Paul Burton --- drivers/net/pcnet.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 8c334c7abcc..2802411db19 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -80,7 +80,7 @@ struct pcnet_uncached_priv { typedef struct pcnet_priv { struct pcnet_uncached_priv *uc; /* Receive Buffer space */ - unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; + unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4]; int cur_rx; int cur_tx; } pcnet_priv_t; @@ -335,6 +335,10 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) flush_dcache_range(addr, addr + sizeof(*lp->uc)); addr = UNCACHED_SDRAM(addr); lp->uc = (struct pcnet_uncached_priv *)addr; + + addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf)); + flush_dcache_range(addr, addr + sizeof(*lp->rx_buf)); + lp->rx_buf = (void *)addr; } uc = lp->uc; @@ -348,7 +352,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) */ lp->cur_rx = 0; for (i = 0; i < RX_RING_SIZE; i++) { - uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); + uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]); uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); uc->rx_ring[i].status = cpu_to_le16(0x8000); PCNET_DEBUG1 @@ -467,6 +471,7 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) static int pcnet_recv (struct eth_device *dev) { struct pcnet_rx_head *entry; + unsigned char *buf; int pkt_len = 0; u16 status; @@ -500,14 +505,12 @@ static int pcnet_recv (struct eth_device *dev) printf("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); } else { - invalidate_dcache_range( - (unsigned long)lp->rx_buf[lp->cur_rx], - (unsigned long)lp->rx_buf[lp->cur_rx] + - pkt_len); - NetReceive(lp->rx_buf[lp->cur_rx], pkt_len); + buf = (*lp->rx_buf)[lp->cur_rx]; + invalidate_dcache_range((unsigned long)buf, + (unsigned long)buf + pkt_len); + NetReceive(buf, pkt_len); PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", - lp->cur_rx, pkt_len, - lp->rx_buf[lp->cur_rx]); + lp->cur_rx, pkt_len, buf); } } entry->status |= cpu_to_le16(0x8000); -- cgit v1.3.1 From 6fb49e4aa08e5d4f4081840b0b30160e98becf27 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 7 Apr 2014 16:41:48 +0100 Subject: pcnet: force ordering of descriptor accesses The ordering of accesses to the rx & tx descriptors is important, yet the send & recv functions accessed them via regular structure accesses. This leaves the compiler with the opportunity to reorder those accesses or to hoist them outside of loops. Prevent that from happening by using readl & writel to access the descriptors. As a nice bonus, this removes the need for the driver to care about endianness. Signed-off-by: Paul Burton --- drivers/net/pcnet.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 2802411db19..237fbba5137 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -434,7 +434,7 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) /* Wait for completion by testing the OWN bit */ for (i = 1000; i > 0; i--) { - status = le16_to_cpu(entry->status); + status = readw(&entry->status); if ((status & 0x8000) == 0) break; udelay(100); @@ -451,11 +451,10 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) * Setup Tx ring. Caution: the write order is important here, * set the status with the "ownership" bits last. */ - status = 0x8300; - entry->length = cpu_to_le16(-pkt_len); - entry->misc = 0x00000000; - entry->base = PCI_TO_MEM_LE(dev, packet); - entry->status = cpu_to_le16(status); + writew(-pkt_len, &entry->length); + writel(0, &entry->misc); + writel(PCI_TO_MEM(dev, packet), &entry->base); + writew(0x8300, &entry->status); /* Trigger an immediate send poll. */ pcnet_write_csr(dev, 0, 0x0008); @@ -473,34 +472,34 @@ static int pcnet_recv (struct eth_device *dev) struct pcnet_rx_head *entry; unsigned char *buf; int pkt_len = 0; - u16 status; + u16 status, err_status; while (1) { entry = &lp->uc->rx_ring[lp->cur_rx]; /* * If we own the next entry, it's a new packet. Send it up. */ - status = le16_to_cpu(entry->status); + status = readw(&entry->status); if ((status & 0x8000) != 0) break; - status >>= 8; + err_status = status >> 8; - if (status != 0x03) { /* There was an error. */ + if (err_status != 0x03) { /* There was an error. */ printf("%s: Rx%d", dev->name, lp->cur_rx); - PCNET_DEBUG1(" (status=0x%x)", status); - if (status & 0x20) + PCNET_DEBUG1(" (status=0x%x)", err_status); + if (err_status & 0x20) printf(" Frame"); - if (status & 0x10) + if (err_status & 0x10) printf(" Overflow"); - if (status & 0x08) + if (err_status & 0x08) printf(" CRC"); - if (status & 0x04) + if (err_status & 0x04) printf(" Fifo"); printf(" Error\n"); - entry->status &= le16_to_cpu(0x03ff); + status &= 0x03ff; } else { - pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4; + pkt_len = (readl(&entry->msg_length) & 0xfff) - 4; if (pkt_len < 60) { printf("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); @@ -513,7 +512,9 @@ static int pcnet_recv (struct eth_device *dev) lp->cur_rx, pkt_len, buf); } } - entry->status |= cpu_to_le16(0x8000); + + status |= 0x8000; + writew(status, &entry->status); if (++lp->cur_rx >= RX_RING_SIZE) lp->cur_rx = 0; -- cgit v1.3.1 From d2ff5e55c346f012129cbce8b373eafd5f00c9b2 Mon Sep 17 00:00:00 2001 From: "David Müller (ELSOFT AG)" Date: Wed, 16 Apr 2014 13:15:59 +0200 Subject: e1000: remove redundant assignment Signed-off-by: David Mueller Acked-by: Joe Hershberger --- drivers/net/e1000.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 9a66e68ae0d..9d9b259d644 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -4532,7 +4532,6 @@ static int e1000_set_phy_type (struct e1000_hw *hw) hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) { hw->phy_type = e1000_phy_igp; - hw->phy_type = e1000_phy_igp; break; } case IGP03E1000_E_PHY_ID: -- cgit v1.3.1 From 538cf92c8c2e8ea7f78c87b5bfb2f705b4b02fa8 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Thu, 10 Apr 2014 00:39:28 +0200 Subject: MIPS: drop incaip board This is dead hardware and no one is interested in making the necessary changes for upcoming features like generic board or driver model. Signed-off-by: Daniel Schwierzeck Cc: Wolfgang Denk --- MAKEALL | 4 - arch/mips/cpu/mips32/incaip/Makefile | 9 - arch/mips/cpu/mips32/incaip/asc_serial.c | 300 ---- arch/mips/cpu/mips32/incaip/asc_serial.h | 177 -- arch/mips/cpu/mips32/incaip/config.mk | 8 - arch/mips/cpu/mips32/incaip/incaip_clock.c | 100 -- arch/mips/cpu/mips32/incaip/incaip_wdt.S | 55 - arch/mips/include/asm/inca-ip.h | 2430 ---------------------------- arch/mips/include/asm/u-boot-mips.h | 2 - arch/mips/lib/board.c | 3 - board/incaip/Makefile | 9 - board/incaip/README | 57 - board/incaip/config.mk | 16 - board/incaip/flash.c | 655 -------- board/incaip/incaip.c | 110 -- board/incaip/lowlevel_init.S | 287 ---- boards.cfg | 4 - doc/README.scrapyard | 1 + drivers/net/Makefile | 1 - drivers/net/inca-ip_sw.c | 793 --------- include/common.h | 3 - include/configs/incaip.h | 177 -- include/netdev.h | 1 - 23 files changed, 1 insertion(+), 5201 deletions(-) delete mode 100644 arch/mips/cpu/mips32/incaip/Makefile delete mode 100644 arch/mips/cpu/mips32/incaip/asc_serial.c delete mode 100644 arch/mips/cpu/mips32/incaip/asc_serial.h delete mode 100644 arch/mips/cpu/mips32/incaip/config.mk delete mode 100644 arch/mips/cpu/mips32/incaip/incaip_clock.c delete mode 100644 arch/mips/cpu/mips32/incaip/incaip_wdt.S delete mode 100644 arch/mips/include/asm/inca-ip.h delete mode 100644 board/incaip/Makefile delete mode 100644 board/incaip/README delete mode 100644 board/incaip/config.mk delete mode 100644 board/incaip/flash.c delete mode 100644 board/incaip/incaip.c delete mode 100644 board/incaip/lowlevel_init.S delete mode 100644 drivers/net/inca-ip_sw.c delete mode 100644 include/configs/incaip.h (limited to 'drivers') diff --git a/MAKEALL b/MAKEALL index 705a0bb5e1a..c54240ced69 100755 --- a/MAKEALL +++ b/MAKEALL @@ -419,10 +419,6 @@ LIST_arm="$(targets_by_arch arm | \ ######################################################################### LIST_mips4kc=" \ - incaip \ - incaip_100MHz \ - incaip_133MHz \ - incaip_150MHz \ qemu_mips \ vct_platinum \ vct_platinum_small \ diff --git a/arch/mips/cpu/mips32/incaip/Makefile b/arch/mips/cpu/mips32/incaip/Makefile deleted file mode 100644 index 7341a4a3e88..00000000000 --- a/arch/mips/cpu/mips32/incaip/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2011 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = incaip_wdt.o -obj-y += incaip_clock.o asc_serial.o diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.c b/arch/mips/cpu/mips32/incaip/asc_serial.c deleted file mode 100644 index 6f0e4f25201..00000000000 --- a/arch/mips/cpu/mips32/incaip/asc_serial.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * (INCA) ASC UART support - */ - -#include -#include -#include -#include -#include -#include "asc_serial.h" - - -#define SET_BIT(reg, mask) reg |= (mask) -#define CLEAR_BIT(reg, mask) reg &= (~mask) -#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) -#define SET_BITS(reg, mask) SET_BIT(reg, mask) -#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} - -extern uint incaip_get_fpiclk(void); - -static int serial_setopt (void); - -/* pointer to ASC register base address */ -static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC; - -/****************************************************************************** -* -* serial_init - initialize a INCAASC channel -* -* This routine initializes the number of data bits, parity -* and set the selected baud rate. Interrupts are disabled. -* Set the modem control signals if the option is selected. -* -* RETURNS: N/A -*/ - -static int asc_serial_init(void) -{ - /* we have to set PMU.EN13 bit to enable an ASC device*/ - INCAASC_PMU_ENABLE(13); - - /* and we have to set CLC register*/ - CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS); - SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001); - - /* initialy we are in async mode */ - pAsc->asc_con = ASCCON_M_8ASYNC; - - /* select input port */ - pAsc->asc_pisel = (CONSOLE_TTY & 0x1); - - /* TXFIFO's filling level */ - SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK, - ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL); - /* enable TXFIFO */ - SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN); - - /* RXFIFO's filling level */ - SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK, - ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL); - /* enable RXFIFO */ - SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN); - - /* enable error signals */ - SET_BIT(pAsc->asc_con, ASCCON_FEN); - SET_BIT(pAsc->asc_con, ASCCON_OEN); - - /* acknowledge ASC interrupts */ - ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL); - - /* disable ASC interrupts */ - ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL); - - /* set FIFOs into the transparent mode */ - SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN); - SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN); - - /* set baud rate */ - serial_setbrg(); - - /* set the options */ - serial_setopt(); - - return 0; -} - -static void asc_serial_setbrg(void) -{ - ulong uiReloadValue, fdv; - ulong f_ASC; - - f_ASC = incaip_get_fpiclk(); - -#ifndef INCAASC_USE_FDV - fdv = 2; - uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1; -#else - fdv = INCAASC_FDV_HIGH_BAUDRATE; - uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1; -#endif /* INCAASC_USE_FDV */ - - if ( (uiReloadValue < 0) || (uiReloadValue > 8191) ) - { -#ifndef INCAASC_USE_FDV - fdv = 3; - uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1; -#else - fdv = INCAASC_FDV_LOW_BAUDRATE; - uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1; -#endif /* INCAASC_USE_FDV */ - - if ( (uiReloadValue < 0) || (uiReloadValue > 8191) ) - { - return; /* can't impossibly generate that baud rate */ - } - } - - /* Disable Baud Rate Generator; BG should only be written when R=0 */ - CLEAR_BIT(pAsc->asc_con, ASCCON_R); - -#ifndef INCAASC_USE_FDV - /* - * Disable Fractional Divider (FDE) - * Divide clock by reload-value + constant (BRS) - */ - /* FDE = 0 */ - CLEAR_BIT(pAsc->asc_con, ASCCON_FDE); - - if ( fdv == 2 ) - CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */ - else - SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */ - -#else /* INCAASC_USE_FDV */ - - /* Enable Fractional Divider */ - SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */ - - /* Set fractional divider value */ - pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK; - -#endif /* INCAASC_USE_FDV */ - - /* Set reload value in BG */ - pAsc->asc_bg = uiReloadValue; - - /* Enable Baud Rate Generator */ - SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */ -} - -/******************************************************************************* -* -* serial_setopt - set the serial options -* -* Set the channel operating mode to that specified. Following options -* are supported: CREAD, CSIZE, PARENB, and PARODD. -* -* Note, this routine disables the transmitter. The calling routine -* may have to re-enable it. -* -* RETURNS: -* Returns 0 to indicate success, otherwise -1 is returned -*/ - -static int serial_setopt (void) -{ - ulong con; - - switch ( ASC_OPTIONS & ASCOPT_CSIZE ) - { - /* 7-bit-data */ - case ASCOPT_CS7: - con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */ - break; - - /* 8-bit-data */ - case ASCOPT_CS8: - if ( ASC_OPTIONS & ASCOPT_PARENB ) - con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */ - else - con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */ - break; - - /* - * only 7 and 8-bit frames are supported - * if we don't use IOCTL extensions - */ - default: - return -1; - } - - if ( ASC_OPTIONS & ASCOPT_STOPB ) - SET_BIT(con, ASCCON_STP); /* 2 stop bits */ - else - CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */ - - if ( ASC_OPTIONS & ASCOPT_PARENB ) - SET_BIT(con, ASCCON_PEN); /* enable parity checking */ - else - CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */ - - if ( ASC_OPTIONS & ASCOPT_PARODD ) - SET_BIT(con, ASCCON_ODD); /* odd parity */ - else - CLEAR_BIT(con, ASCCON_ODD); /* even parity */ - - if ( ASC_OPTIONS & ASCOPT_CREAD ) - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */ - - pAsc->asc_con |= con; - - return 0; -} - -static void asc_serial_putc(const char c) -{ - uint txFl = 0; - - if (c == '\n') serial_putc ('\r'); - - /* check do we have a free space in the TX FIFO */ - /* get current filling level */ - do - { - txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; - } - while ( txFl == INCAASC_TXFIFO_FULL ); - - pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */ - - /* check for errors */ - if ( pAsc->asc_con & ASCCON_OE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); - return; - } -} - -static int asc_serial_getc(void) -{ - ulong symbol_mask; - char c; - - while (!serial_tstc()); - - symbol_mask = - ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff); - - c = (char)(pAsc->asc_rbuf & symbol_mask); - - return c; -} - -static int asc_serial_tstc(void) -{ - int res = 1; - - if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) - { - res = 0; - } - else if ( pAsc->asc_con & ASCCON_FE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE); - res = 0; - } - else if ( pAsc->asc_con & ASCCON_PE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE); - res = 0; - } - else if ( pAsc->asc_con & ASCCON_OE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); - res = 0; - } - - return res; -} - -static struct serial_device asc_serial_drv = { - .name = "asc_serial", - .start = asc_serial_init, - .stop = NULL, - .setbrg = asc_serial_setbrg, - .putc = asc_serial_putc, - .puts = default_serial_puts, - .getc = asc_serial_getc, - .tstc = asc_serial_tstc, -}; - -void asc_serial_initialize(void) -{ - serial_register(&asc_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &asc_serial_drv; -} diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.h b/arch/mips/cpu/mips32/incaip/asc_serial.h deleted file mode 100644 index 7ffdcfaf8b7..00000000000 --- a/arch/mips/cpu/mips32/incaip/asc_serial.h +++ /dev/null @@ -1,177 +0,0 @@ -/* incaAscSio.h - (INCA) ASC UART tty driver header */ - -#ifndef __INCincaAscSioh -#define __INCincaAscSioh - -#include - -/* channel operating modes */ -#define ASCOPT_CSIZE 0x00000003 -#define ASCOPT_CS7 0x00000001 -#define ASCOPT_CS8 0x00000002 -#define ASCOPT_PARENB 0x00000004 -#define ASCOPT_STOPB 0x00000008 -#define ASCOPT_PARODD 0x00000010 -#define ASCOPT_CREAD 0x00000020 - -#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) - -/* ASC input select (0 or 1) */ -#define CONSOLE_TTY 0 - -/* use fractional divider for baudrate settings */ -#define INCAASC_USE_FDV - -#ifdef INCAASC_USE_FDV - #define INCAASC_FDV_LOW_BAUDRATE 71 - #define INCAASC_FDV_HIGH_BAUDRATE 453 -#endif /*INCAASC_USE_FDV*/ - - -#define INCAASC_TXFIFO_FL 1 -#define INCAASC_RXFIFO_FL 1 -#define INCAASC_TXFIFO_FULL 16 - -/* interrupt lines masks for the ASC device interrupts*/ -/* change these macroses if it's necessary */ -#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */ - -#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */ -#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */ -#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */ -#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/ - -/* interrupt controller access macros */ -#define ASC_INTERRUPTS_ENABLE(X) \ - *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X; -#define ASC_INTERRUPTS_DISABLE(X) \ - *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X; -#define ASC_INTERRUPTS_CLEAR(X) \ - *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X; - -/* CLC register's bits and bitfields */ -#define ASCCLC_DISR 0x00000001 -#define ASCCLC_DISS 0x00000002 -#define ASCCLC_RMCMASK 0x0000FF00 -#define ASCCLC_RMCOFFSET 8 - -/* CON register's bits and bitfields */ -#define ASCCON_MODEMASK 0x0007 - #define ASCCON_M_8SYNC 0x0 - #define ASCCON_M_8ASYNC 0x1 - #define ASCCON_M_8IRDAASYNC 0x2 - #define ASCCON_M_7ASYNCPAR 0x3 - #define ASCCON_M_9ASYNC 0x4 - #define ASCCON_M_8WAKEUPASYNC 0x5 - #define ASCCON_M_8ASYNCPAR 0x7 -#define ASCCON_STP 0x0008 -#define ASCCON_REN 0x0010 -#define ASCCON_PEN 0x0020 -#define ASCCON_FEN 0x0040 -#define ASCCON_OEN 0x0080 -#define ASCCON_PE 0x0100 -#define ASCCON_FE 0x0200 -#define ASCCON_OE 0x0400 -#define ASCCON_FDE 0x0800 -#define ASCCON_ODD 0x1000 -#define ASCCON_BRS 0x2000 -#define ASCCON_LB 0x4000 -#define ASCCON_R 0x8000 - -/* WHBCON register's bits and bitfields */ -#define ASCWHBCON_CLRREN 0x0010 -#define ASCWHBCON_SETREN 0x0020 -#define ASCWHBCON_CLRPE 0x0100 -#define ASCWHBCON_CLRFE 0x0200 -#define ASCWHBCON_CLROE 0x0400 -#define ASCWHBCON_SETPE 0x0800 -#define ASCWHBCON_SETFE 0x1000 -#define ASCWHBCON_SETOE 0x2000 - -/* ABCON register's bits and bitfields */ -#define ASCABCON_ABEN 0x0001 -#define ASCABCON_AUREN 0x0002 -#define ASCABCON_ABSTEN 0x0004 -#define ASCABCON_ABDETEN 0x0008 -#define ASCABCON_FCDETEN 0x0010 -#define ASCABCON_EMMASK 0x0300 - #define ASCABCON_EMOFF 8 - #define ASCABCON_EM_DISAB 0x0 - #define ASCABCON_EM_DURAB 0x1 - #define ASCABCON_EM_ALWAYS 0x2 -#define ASCABCON_TXINV 0x0400 -#define ASCABCON_RXINV 0x0800 - -/* FDV register mask, offset and bitfields*/ -#define ASCFDV_VALUE_MASK 0x000001FF - -/* WHBABCON register's bits and bitfields */ -#define ASCWHBABCON_SETABEN 0x0001 -#define ASCWHBABCON_CLRABEN 0x0002 - -/* ABSTAT register's bits and bitfields */ -#define ASCABSTAT_FCSDET 0x0001 -#define ASCABSTAT_FCCDET 0x0002 -#define ASCABSTAT_SCSDET 0x0004 -#define ASCABSTAT_SCCDET 0x0008 -#define ASCABSTAT_DETWAIT 0x0010 - -/* WHBABSTAT register's bits and bitfields */ -#define ASCWHBABSTAT_CLRFCSDET 0x0001 -#define ASCWHBABSTAT_SETFCSDET 0x0002 -#define ASCWHBABSTAT_CLRFCCDET 0x0004 -#define ASCWHBABSTAT_SETFCCDET 0x0008 -#define ASCWHBABSTAT_CLRSCSDET 0x0010 -#define ASCWHBABSTAT_SETSCSDET 0x0020 -#define ASCWHBABSTAT_SETSCCDET 0x0040 -#define ASCWHBABSTAT_CLRSCCDET 0x0080 -#define ASCWHBABSTAT_CLRDETWAIT 0x0100 -#define ASCWHBABSTAT_SETDETWAIT 0x0200 - -/* TXFCON register's bits and bitfields */ -#define ASCTXFCON_TXFEN 0x0001 -#define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXTMEN 0x0004 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 - -/* RXFCON register's bits and bitfields */ -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXTMEN 0x0004 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 - -/* FSTAT register's bits and bitfields */ -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 - -#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT); - -typedef struct /* incaAsc_t */ -{ - volatile unsigned long asc_clc; /*0x0000*/ - volatile unsigned long asc_pisel; /*0x0004*/ - volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/ - volatile unsigned long asc_con; /*0x0010*/ - volatile unsigned long asc_bg; /*0x0014*/ - volatile unsigned long asc_fdv; /*0x0018*/ - volatile unsigned long asc_pmw; /* not used */ /*0x001C*/ - volatile unsigned long asc_tbuf; /*0x0020*/ - volatile unsigned long asc_rbuf; /*0x0024*/ - volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/ - volatile unsigned long asc_abcon; /*0x0030*/ - volatile unsigned long asc_abstat; /* not used */ /*0x0034*/ - volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/ - volatile unsigned long asc_rxfcon; /*0x0040*/ - volatile unsigned long asc_txfcon; /*0x0044*/ - volatile unsigned long asc_fstat; /*0x0048*/ - volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/ - volatile unsigned long asc_whbcon; /*0x0050*/ - volatile unsigned long asc_whbabcon; /*0x0054*/ - volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/ - -} incaAsc_t; - -#endif /* __INCincaAscSioh */ diff --git a/arch/mips/cpu/mips32/incaip/config.mk b/arch/mips/cpu/mips32/incaip/config.mk deleted file mode 100644 index 5c89129d8cf..00000000000 --- a/arch/mips/cpu/mips32/incaip/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2011 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mtune=4kc diff --git a/arch/mips/cpu/mips32/incaip/incaip_clock.c b/arch/mips/cpu/mips32/incaip/incaip_clock.c deleted file mode 100644 index efada9f6f8d..00000000000 --- a/arch/mips/cpu/mips32/incaip/incaip_clock.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - - -/******************************************************************************* -* -* get_cpuclk - returns the frequency of the CPU. -* -* Gets the value directly from the INCA-IP hardware. -* -* RETURNS: -* 150.000.000 for 150 MHz -* 133.333.333 for 133 MHz (= 400MHz/3) -* 100.000.000 for 100 MHz (= 400MHz/4) -* NOTE: -* This functions should be used by the hardware driver to get the correct -* frequency of the CPU. Don't use the macros, which are set to init the CPU -* frequency in the ROM code. -*/ -uint incaip_get_cpuclk (void) -{ - /*-------------------------------------------------------------------------*/ - /* CPU Clock Input Multiplexer (MUX I) */ - /* Multiplexer MUX I selects the maximum input clock to the CPU. */ - /*-------------------------------------------------------------------------*/ - if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) & - INCA_IP_CGU_CGU_MUXCR_MUXI) { - /* MUX I set to 150 MHz clock */ - return 150000000; - } else { - /* MUX I set to 100/133 MHz clock */ - if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) { - /* Division value is 1/3, maximum CPU operating */ - /* frequency is 133.3 MHz */ - return 133333333; - } else { - /* Division value is 1/4, maximum CPU operating */ - /* frequency is 100 MHz */ - return 100000000; - } - } -} - -/******************************************************************************* -* -* get_fpiclk - returns the frequency of the FPI bus. -* -* Gets the value directly from the INCA-IP hardware. -* -* RETURNS: Frquency in Hz -* -* NOTE: -* This functions should be used by the hardware driver to get the correct -* frequency of the CPU. Don't use the macros, which are set to init the CPU -* frequency in the ROM code. -* The calculation for the -*/ -uint incaip_get_fpiclk (void) -{ - uint clkCPU; - - clkCPU = incaip_get_cpuclk (); - - switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) { - case 0x4: - return clkCPU >> 1; /* devided by 2 */ - break; - case 0x8: - return clkCPU >> 2; /* devided by 4 */ - break; - default: - return clkCPU; - break; - } -} - -int incaip_set_cpuclk (void) -{ - extern void ebu_init(long); - extern void cgu_init(long); - extern void sdram_init(long); - char tmp[64]; - ulong cpuclk; - - if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) { - cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; - cgu_init (cpuclk); - ebu_init (cpuclk); - sdram_init (cpuclk); - } - - return 0; -} diff --git a/arch/mips/cpu/mips32/incaip/incaip_wdt.S b/arch/mips/cpu/mips32/incaip/incaip_wdt.S deleted file mode 100644 index b15320a57cf..00000000000 --- a/arch/mips/cpu/mips32/incaip/incaip_wdt.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * INCA-IP Watchdog timer management code. - * - * Copyright (c) 2003 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include - - -#define WD_BASE 0xb8000000 -#define WD_CON0(value) 0x0020(value) -#define WD_CON1(value) 0x0024(value) -#define WD_DISABLE 0x00000008 -#define WD_ENABLE 0x00000000 -#define WD_WRITE_PW 0xFFFC00F8 -#define WD_WRITE_ENDINIT 0xFFFC00F3 -#define WD_WRITE_INIT 0xFFFC00F2 - - - .globl disable_incaip_wdt -disable_incaip_wdt: - li t0, WD_BASE - - /* Calculate password. - */ - lw t2, WD_CON1(t0) - and t2, 0xC - - lw t3, WD_CON0(t0) - and t3, 0xFFFFFF01 - - or t3, t2 - or t3, 0xF0 - - sw t3, WD_CON0(t0) /* write password */ - - /* Clear ENDINIT. - */ - li t1, WD_WRITE_INIT - sw t1, WD_CON0(t0) - - - li t1, WD_DISABLE - sw t1, WD_CON1(t0) /* disable watchdog */ - li t1, WD_WRITE_PW - sw t1, WD_CON0(t0) /* write password */ - li t1, WD_WRITE_ENDINIT - sw t1, WD_CON0(t0) /* end command */ - - jr ra - nop diff --git a/arch/mips/include/asm/inca-ip.h b/arch/mips/include/asm/inca-ip.h deleted file mode 100644 index 5f03e2aa201..00000000000 --- a/arch/mips/include/asm/inca-ip.h +++ /dev/null @@ -1,2430 +0,0 @@ -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ - - -/***********************************************************************/ -/* Module : WDT register address and bits */ -/***********************************************************************/ - -#define INCA_IP_WDT (0xB8000000) -/***********************************************************************/ - - -/***Reset Status Register Power On***/ -#define INCA_IP_WDT_RST_SR ((volatile u32*)(INCA_IP_WDT+ 0x0014)) - -/***Reset Request Register***/ -#define INCA_IP_WDT_RST_REQ ((volatile u32*)(INCA_IP_WDT+ 0x0010)) -#define INCA_IP_WDT_RST_REQ_SWBOOT (1 << 24) -#define INCA_IP_WDT_RST_REQ_SWCFG (1 << 16) -#define INCA_IP_WDT_RST_REQ_RRPHY (1 << 5) -#define INCA_IP_WDT_RST_REQ_RRHSP (1 << 4) -#define INCA_IP_WDT_RST_REQ_RRFPI (1 << 3) -#define INCA_IP_WDT_RST_REQ_RREXT (1 << 2) -#define INCA_IP_WDT_RST_REQ_RRDSP (1 << 1) -#define INCA_IP_WDT_RST_REQ_RRCPU (1 << 0) - -/***NMI Status Register***/ -#define INCA_IP_WDT_NMISR ((volatile u32*)(INCA_IP_WDT+ 0x002C)) -#define INCA_IP_WDT_NMISR_NMIWDT (1 << 2) -#define INCA_IP_WDT_NMISR_NMIPLL (1 << 1) -#define INCA_IP_WDT_NMISR_NMIEXT (1 << 0) - -/***Manufacturer Identification Register***/ -#define INCA_IP_WDT_MANID ((volatile u32*)(INCA_IP_WDT+ 0x0070)) -#define INCA_IP_WDT_MANID_MANUF (value) (((( 1 << 11) - 1) & (value)) << 5) - -/***Chip Identification Register***/ -#define INCA_IP_WDT_CHIPID ((volatile u32*)(INCA_IP_WDT+ 0x0074)) -#define INCA_IP_WDT_CHIPID_VERSION (value) (((( 1 << 4) - 1) & (value)) << 28) -#define INCA_IP_WDT_CHIPID_PART_NUMBER (value) (((( 1 << 16) - 1) & (value)) << 12) -#define INCA_IP_WDT_CHIPID_MANID (value) (((( 1 << 11) - 1) & (value)) << 1) - -/***Redesign Tracing Identification Register***/ -#define INCA_IP_WDT_RTID ((volatile u32*)(INCA_IP_WDT+ 0x0078)) -#define INCA_IP_WDT_RTID_LC (1 << 15) -#define INCA_IP_WDT_RTID_RIX (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Watchdog Timer Control Register 0***/ -#define INCA_IP_WDT_WDT_CON0 ((volatile u32*)(INCA_IP_WDT+ 0x0020)) - -/***Watchdog Timer Control Register 1***/ -#define INCA_IP_WDT_WDT_CON1 ((volatile u32*)(INCA_IP_WDT+ 0x0024)) -#define INCA_IP_WDT_WDT_CON1_WDTDR (1 << 3) -#define INCA_IP_WDT_WDT_CON1_WDTIR (1 << 2) - -/***Watchdog Timer Status Register***/ -#define INCA_IP_WDT_WDT_SR ((volatile u32*)(INCA_IP_WDT+ 0x0028)) -#define INCA_IP_WDT_WDT_SR_WDTTIM (value) (((( 1 << 16) - 1) & (value)) << 16) -#define INCA_IP_WDT_WDT_SR_WDTPR (1 << 5) -#define INCA_IP_WDT_WDT_SR_WDTTO (1 << 4) -#define INCA_IP_WDT_WDT_SR_WDTDS (1 << 3) -#define INCA_IP_WDT_WDT_SR_WDTIS (1 << 2) -#define INCA_IP_WDT_WDT_SR_WDTOE (1 << 1) -#define INCA_IP_WDT_WDT_SR_WDTAE (1 << 0) - -/***********************************************************************/ -/* Module : CGU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_CGU (0xBF107000) -/***********************************************************************/ - - -/***CGU PLL1 Control Register***/ -#define INCA_IP_CGU_CGU_PLL1CR ((volatile u32*)(INCA_IP_CGU+ 0x0008)) -#define INCA_IP_CGU_CGU_PLL1CR_SWRST (1 << 31) -#define INCA_IP_CGU_CGU_PLL1CR_EN (1 << 30) -#define INCA_IP_CGU_CGU_PLL1CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_PLL1CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***CGU PLL0 Control Register***/ -#define INCA_IP_CGU_CGU_PLL0CR ((volatile u32*)(INCA_IP_CGU+ 0x0000)) -#define INCA_IP_CGU_CGU_PLL0CR_SWRST (1 << 31) -#define INCA_IP_CGU_CGU_PLL0CR_EN (1 << 30) -#define INCA_IP_CGU_CGU_PLL0CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_PLL0CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***CGU PLL0 Status Register***/ -#define INCA_IP_CGU_CGU_PLL0SR ((volatile u32*)(INCA_IP_CGU+ 0x0004)) -#define INCA_IP_CGU_CGU_PLL0SR_LOCK (1 << 31) -#define INCA_IP_CGU_CGU_PLL0SR_RCF (1 << 29) -#define INCA_IP_CGU_CGU_PLL0SR_PLLBYP (1 << 15) - -/***CGU PLL1 Status Register***/ -#define INCA_IP_CGU_CGU_PLL1SR ((volatile u32*)(INCA_IP_CGU+ 0x000C)) -#define INCA_IP_CGU_CGU_PLL1SR_LOCK (1 << 31) -#define INCA_IP_CGU_CGU_PLL1SR_RCF (1 << 29) -#define INCA_IP_CGU_CGU_PLL1SR_PLLBYP (1 << 15) - -/***CGU Divider Control Register***/ -#define INCA_IP_CGU_CGU_DIVCR ((volatile u32*)(INCA_IP_CGU+ 0x0010)) - -/***CGU Multiplexer Control Register***/ -#define INCA_IP_CGU_CGU_MUXCR ((volatile u32*)(INCA_IP_CGU+ 0x0014)) -#define INCA_IP_CGU_CGU_MUXCR_SWRST (1 << 31) -#define INCA_IP_CGU_CGU_MUXCR_MUXII (1 << 1) -#define INCA_IP_CGU_CGU_MUXCR_MUXI (1 << 0) - -/***CGU Fractional Divider Control Register***/ -#define INCA_IP_CGU_CGU_FDCR ((volatile u32*)(INCA_IP_CGU+ 0x0018)) -#define INCA_IP_CGU_CGU_FDCR_FDEN (1 << 31) -#define INCA_IP_CGU_CGU_FDCR_INTEGER (value) (((( 1 << 12) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_FDCR_FRACTION (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : PMU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_PMU (0xBF102000) -/***********************************************************************/ - - -/***PM Global Enable Register***/ -#define INCA_IP_PMU_PM_GEN ((volatile u32*)(INCA_IP_PMU+ 0x0000)) -#define INCA_IP_PMU_PM_GEN_EN16 (1 << 16) -#define INCA_IP_PMU_PM_GEN_EN15 (1 << 15) -#define INCA_IP_PMU_PM_GEN_EN14 (1 << 14) -#define INCA_IP_PMU_PM_GEN_EN13 (1 << 13) -#define INCA_IP_PMU_PM_GEN_EN12 (1 << 12) -#define INCA_IP_PMU_PM_GEN_EN11 (1 << 11) -#define INCA_IP_PMU_PM_GEN_EN10 (1 << 10) -#define INCA_IP_PMU_PM_GEN_EN9 (1 << 9) -#define INCA_IP_PMU_PM_GEN_EN8 (1 << 8) -#define INCA_IP_PMU_PM_GEN_EN7 (1 << 7) -#define INCA_IP_PMU_PM_GEN_EN6 (1 << 6) -#define INCA_IP_PMU_PM_GEN_EN5 (1 << 5) -#define INCA_IP_PMU_PM_GEN_EN4 (1 << 4) -#define INCA_IP_PMU_PM_GEN_EN3 (1 << 3) -#define INCA_IP_PMU_PM_GEN_EN2 (1 << 2) -#define INCA_IP_PMU_PM_GEN_EN0 (1 << 0) - -/***PM Power Down Enable Register***/ -#define INCA_IP_PMU_PM_PDEN ((volatile u32*)(INCA_IP_PMU+ 0x0008)) -#define INCA_IP_PMU_PM_PDEN_EN16 (1 << 16) -#define INCA_IP_PMU_PM_PDEN_EN15 (1 << 15) -#define INCA_IP_PMU_PM_PDEN_EN14 (1 << 14) -#define INCA_IP_PMU_PM_PDEN_EN13 (1 << 13) -#define INCA_IP_PMU_PM_PDEN_EN12 (1 << 12) -#define INCA_IP_PMU_PM_PDEN_EN11 (1 << 11) -#define INCA_IP_PMU_PM_PDEN_EN10 (1 << 10) -#define INCA_IP_PMU_PM_PDEN_EN9 (1 << 9) -#define INCA_IP_PMU_PM_PDEN_EN8 (1 << 8) -#define INCA_IP_PMU_PM_PDEN_EN7 (1 << 7) -#define INCA_IP_PMU_PM_PDEN_EN5 (1 << 5) -#define INCA_IP_PMU_PM_PDEN_EN4 (1 << 4) -#define INCA_IP_PMU_PM_PDEN_EN3 (1 << 3) -#define INCA_IP_PMU_PM_PDEN_EN2 (1 << 2) -#define INCA_IP_PMU_PM_PDEN_EN0 (1 << 0) - -/***PM Wake-Up from Power Down Register***/ -#define INCA_IP_PMU_PM_WUP ((volatile u32*)(INCA_IP_PMU+ 0x0010)) -#define INCA_IP_PMU_PM_WUP_WUP16 (1 << 16) -#define INCA_IP_PMU_PM_WUP_WUP15 (1 << 15) -#define INCA_IP_PMU_PM_WUP_WUP14 (1 << 14) -#define INCA_IP_PMU_PM_WUP_WUP13 (1 << 13) -#define INCA_IP_PMU_PM_WUP_WUP12 (1 << 12) -#define INCA_IP_PMU_PM_WUP_WUP11 (1 << 11) -#define INCA_IP_PMU_PM_WUP_WUP10 (1 << 10) -#define INCA_IP_PMU_PM_WUP_WUP9 (1 << 9) -#define INCA_IP_PMU_PM_WUP_WUP8 (1 << 8) -#define INCA_IP_PMU_PM_WUP_WUP7 (1 << 7) -#define INCA_IP_PMU_PM_WUP_WUP5 (1 << 5) -#define INCA_IP_PMU_PM_WUP_WUP4 (1 << 4) -#define INCA_IP_PMU_PM_WUP_WUP3 (1 << 3) -#define INCA_IP_PMU_PM_WUP_WUP2 (1 << 2) -#define INCA_IP_PMU_PM_WUP_WUP0 (1 << 0) - -/***PM Control Register***/ -#define INCA_IP_PMU_PM_CR ((volatile u32*)(INCA_IP_PMU+ 0x0014)) -#define INCA_IP_PMU_PM_CR_AWEN (1 << 31) -#define INCA_IP_PMU_PM_CR_SWRST (1 << 30) -#define INCA_IP_PMU_PM_CR_SWCR (1 << 2) -#define INCA_IP_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : BCU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_BCU (0xB8000100) -/***********************************************************************/ - - -/***BCU Control Register (0010H)***/ -#define INCA_IP_BCU_BCU_CON ((volatile u32*)(INCA_IP_BCU+ 0x0010)) -#define INCA_IP_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_BCU_BCU_CON_SPE (1 << 19) -#define INCA_IP_BCU_BCU_CON_PSE (1 << 18) -#define INCA_IP_BCU_BCU_CON_DBG (1 << 16) -#define INCA_IP_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***BCU Error Control Capture Register (0020H)***/ -#define INCA_IP_BCU_BCU_ECON ((volatile u32*)(INCA_IP_BCU+ 0x0020)) -#define INCA_IP_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24) -#define INCA_IP_BCU_BCU_ECON_RDN (1 << 23) -#define INCA_IP_BCU_BCU_ECON_WRN (1 << 22) -#define INCA_IP_BCU_BCU_ECON_SVM (1 << 21) -#define INCA_IP_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19) -#define INCA_IP_BCU_BCU_ECON_ABT (1 << 18) -#define INCA_IP_BCU_BCU_ECON_RDY (1 << 17) -#define INCA_IP_BCU_BCU_ECON_TOUT (1 << 16) -#define INCA_IP_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0) -#define INCA_IP_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28) - -/***BCU Error Address Capture Register (0024 H)***/ -#define INCA_IP_BCU_BCU_EADD ((volatile u32*)(INCA_IP_BCU+ 0x0024)) -#define INCA_IP_BCU_BCU_EADD_FPIADR - -/***BCU Error Data Capture Register (0028H)***/ -#define INCA_IP_BCU_BCU_EDAT ((volatile u32*)(INCA_IP_BCU+ 0x0028)) -#define INCA_IP_BCU_BCU_EDAT_FPIDAT - -/***********************************************************************/ -/* Module : MBC register address and bits */ -/***********************************************************************/ - -#define INCA_IP_MBC (0xBF103000) -/***********************************************************************/ - - -/***Mailbox CPU Configuration Register***/ -#define INCA_IP_MBC_MBC_CFG ((volatile u32*)(INCA_IP_MBC+ 0x0080)) -#define INCA_IP_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_MBC_MBC_CFG_RES (1 << 5) -#define INCA_IP_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1) -#define INCA_IP_MBC_MBC_CFG_SIZE (1 << 0) - -/***Mailbox CPU Interrupt Status Register***/ -#define INCA_IP_MBC_MBC_ISR ((volatile u32*)(INCA_IP_MBC+ 0x0084)) -#define INCA_IP_MBC_MBC_ISR_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_ISR_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_ISR_B1E (1 << 29) -#define INCA_IP_MBC_MBC_ISR_B0E (1 << 28) -#define INCA_IP_MBC_MBC_ISR_WDT (1 << 27) -#define INCA_IP_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask Register***/ -#define INCA_IP_MBC_MBC_MSK ((volatile u32*)(INCA_IP_MBC+ 0x0088)) -#define INCA_IP_MBC_MBC_MSK_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_MSK_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_MSK_B1E (1 << 29) -#define INCA_IP_MBC_MBC_MSK_B0E (1 << 28) -#define INCA_IP_MBC_MBC_MSK_WDT (1 << 27) -#define INCA_IP_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 01 Register***/ -#define INCA_IP_MBC_MBC_MSK01 ((volatile u32*)(INCA_IP_MBC+ 0x008C)) -#define INCA_IP_MBC_MBC_MSK01_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_MSK01_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_MSK01_B1E (1 << 29) -#define INCA_IP_MBC_MBC_MSK01_B0E (1 << 28) -#define INCA_IP_MBC_MBC_MSK01_WDT (1 << 27) -#define INCA_IP_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 10 Register***/ -#define INCA_IP_MBC_MBC_MSK10 ((volatile u32*)(INCA_IP_MBC+ 0x0090)) -#define INCA_IP_MBC_MBC_MSK10_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_MSK10_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_MSK10_B1E (1 << 29) -#define INCA_IP_MBC_MBC_MSK10_B0E (1 << 28) -#define INCA_IP_MBC_MBC_MSK10_WDT (1 << 27) -#define INCA_IP_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Short Command Register***/ -#define INCA_IP_MBC_MBC_CMD ((volatile u32*)(INCA_IP_MBC+ 0x0094)) -#define INCA_IP_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***Mailbox CPU Input Data of Buffer 0***/ -#define INCA_IP_MBC_MBC_ID0 ((volatile u32*)(INCA_IP_MBC+ 0x0000)) -#define INCA_IP_MBC_MBC_ID0_INDATA - -/***Mailbox CPU Input Data of Buffer 1***/ -#define INCA_IP_MBC_MBC_ID1 ((volatile u32*)(INCA_IP_MBC+ 0x0020)) -#define INCA_IP_MBC_MBC_ID1_INDATA - -/***Mailbox CPU Output Data of Buffer 2***/ -#define INCA_IP_MBC_MBC_OD2 ((volatile u32*)(INCA_IP_MBC+ 0x0040)) -#define INCA_IP_MBC_MBC_OD2_OUTDATA - -/***Mailbox CPU Output Data of Buffer 3***/ -#define INCA_IP_MBC_MBC_OD3 ((volatile u32*)(INCA_IP_MBC+ 0x0060)) -#define INCA_IP_MBC_MBC_OD3_OUTDATA - -/***Mailbox CPU Control Register of Buffer 0***/ -#define INCA_IP_MBC_MBC_CR0 ((volatile u32*)(INCA_IP_MBC+ 0x0004)) -#define INCA_IP_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 1***/ -#define INCA_IP_MBC_MBC_CR1 ((volatile u32*)(INCA_IP_MBC+ 0x0024)) -#define INCA_IP_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 2***/ -#define INCA_IP_MBC_MBC_CR2 ((volatile u32*)(INCA_IP_MBC+ 0x0044)) -#define INCA_IP_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 3***/ -#define INCA_IP_MBC_MBC_CR3 ((volatile u32*)(INCA_IP_MBC+ 0x0064)) -#define INCA_IP_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Free Space of Buffer 0***/ -#define INCA_IP_MBC_MBC_FS0 ((volatile u32*)(INCA_IP_MBC+ 0x0008)) -#define INCA_IP_MBC_MBC_FS0_FS - -/***Mailbox CPU Free Space of Buffer 1***/ -#define INCA_IP_MBC_MBC_FS1 ((volatile u32*)(INCA_IP_MBC+ 0x0028)) -#define INCA_IP_MBC_MBC_FS1_FS - -/***Mailbox CPU Free Space of Buffer 2***/ -#define INCA_IP_MBC_MBC_FS2 ((volatile u32*)(INCA_IP_MBC+ 0x0048)) -#define INCA_IP_MBC_MBC_FS2_FS - -/***Mailbox CPU Free Space of Buffer 3***/ -#define INCA_IP_MBC_MBC_FS3 ((volatile u32*)(INCA_IP_MBC+ 0x0068)) -#define INCA_IP_MBC_MBC_FS3_FS - -/***Mailbox CPU Data Available in Buffer 0***/ -#define INCA_IP_MBC_MBC_DA0 ((volatile u32*)(INCA_IP_MBC+ 0x000C)) -#define INCA_IP_MBC_MBC_DA0_DA - -/***Mailbox CPU Data Available in Buffer 1***/ -#define INCA_IP_MBC_MBC_DA1 ((volatile u32*)(INCA_IP_MBC+ 0x002C)) -#define INCA_IP_MBC_MBC_DA1_DA - -/***Mailbox CPU Data Available in Buffer 2***/ -#define INCA_IP_MBC_MBC_DA2 ((volatile u32*)(INCA_IP_MBC+ 0x004C)) -#define INCA_IP_MBC_MBC_DA2_DA - -/***Mailbox CPU Data Available in Buffer 3***/ -#define INCA_IP_MBC_MBC_DA3 ((volatile u32*)(INCA_IP_MBC+ 0x006C)) -#define INCA_IP_MBC_MBC_DA3_DA - -/***Mailbox CPU Input Absolute Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_IABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0010)) -#define INCA_IP_MBC_MBC_IABS0_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_IABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0030)) -#define INCA_IP_MBC_MBC_IABS1_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_IABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0050)) -#define INCA_IP_MBC_MBC_IABS2_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_IABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0070)) -#define INCA_IP_MBC_MBC_IABS3_IABS - -/***Mailbox CPU Input Temporary Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_ITMP0 ((volatile u32*)(INCA_IP_MBC+ 0x0014)) -#define INCA_IP_MBC_MBC_ITMP0_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_ITMP1 ((volatile u32*)(INCA_IP_MBC+ 0x0034)) -#define INCA_IP_MBC_MBC_ITMP1_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_ITMP2 ((volatile u32*)(INCA_IP_MBC+ 0x0054)) -#define INCA_IP_MBC_MBC_ITMP2_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_ITMP3 ((volatile u32*)(INCA_IP_MBC+ 0x0074)) -#define INCA_IP_MBC_MBC_ITMP3_ITMP - -/***Mailbox CPU Output Absolute Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_OABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0018)) -#define INCA_IP_MBC_MBC_OABS0_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_OABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0038)) -#define INCA_IP_MBC_MBC_OABS1_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_OABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0058)) -#define INCA_IP_MBC_MBC_OABS2_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_OABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0078)) -#define INCA_IP_MBC_MBC_OABS3_OABS - -/***Mailbox CPU Output Temporary Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_OTMP0 ((volatile u32*)(INCA_IP_MBC+ 0x001C)) -#define INCA_IP_MBC_MBC_OTMP0_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_OTMP1 ((volatile u32*)(INCA_IP_MBC+ 0x003C)) -#define INCA_IP_MBC_MBC_OTMP1_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_OTMP2 ((volatile u32*)(INCA_IP_MBC+ 0x005C)) -#define INCA_IP_MBC_MBC_OTMP2_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_OTMP3 ((volatile u32*)(INCA_IP_MBC+ 0x007C)) -#define INCA_IP_MBC_MBC_OTMP3_OTMP - -/***DSP Control Register***/ -#define INCA_IP_MBC_DCTRL ((volatile u32*)(INCA_IP_MBC+ 0x00A0)) -#define INCA_IP_MBC_DCTRL_BA (1 << 0) -#define INCA_IP_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1) -#define INCA_IP_MBC_DCTRL_IDL (1 << 4) -#define INCA_IP_MBC_DCTRL_RES (1 << 15) - -/***DSP Status Register***/ -#define INCA_IP_MBC_DSTA ((volatile u32*)(INCA_IP_MBC+ 0x00A4)) -#define INCA_IP_MBC_DSTA_IDLE (1 << 0) -#define INCA_IP_MBC_DSTA_PD (1 << 1) - -/***DSP Test 1 Register***/ -#define INCA_IP_MBC_DTST1 ((volatile u32*)(INCA_IP_MBC+ 0x00A8)) -#define INCA_IP_MBC_DTST1_ABORT (1 << 0) -#define INCA_IP_MBC_DTST1_HWF32 (1 << 1) -#define INCA_IP_MBC_DTST1_HWF4M (1 << 2) -#define INCA_IP_MBC_DTST1_HWFOP (1 << 3) - -/***********************************************************************/ -/* Module : Switch register address and bits */ -/***********************************************************************/ - -#define INCA_IP_Switch (0xBF104000) -/***********************************************************************/ - - -/***Unknown Destination Register***/ -#define INCA_IP_Switch_UN_DEST ((volatile u32*)(INCA_IP_Switch+ 0x0000)) -#define INCA_IP_Switch_UN_DEST_CB (1 << 8) -#define INCA_IP_Switch_UN_DEST_LB (1 << 7) -#define INCA_IP_Switch_UN_DEST_PB (1 << 6) -#define INCA_IP_Switch_UN_DEST_CM (1 << 5) -#define INCA_IP_Switch_UN_DEST_LM (1 << 4) -#define INCA_IP_Switch_UN_DEST_PM (1 << 3) -#define INCA_IP_Switch_UN_DEST_CU (1 << 2) -#define INCA_IP_Switch_UN_DEST_LU (1 << 1) -#define INCA_IP_Switch_UN_DEST_PU (1 << 0) - -/***VLAN Control Register***/ -#define INCA_IP_Switch_VLAN_CTRL ((volatile u32*)(INCA_IP_Switch+ 0x0004)) -#define INCA_IP_Switch_VLAN_CTRL_SC (1 << 6) -#define INCA_IP_Switch_VLAN_CTRL_SL (1 << 5) -#define INCA_IP_Switch_VLAN_CTRL_SP (1 << 4) -#define INCA_IP_Switch_VLAN_CTRL_TC (1 << 3) -#define INCA_IP_Switch_VLAN_CTRL_TL (1 << 2) -#define INCA_IP_Switch_VLAN_CTRL_TP (1 << 1) -#define INCA_IP_Switch_VLAN_CTRL_VA (1 << 0) - -/***PC VLAN Configuration Register***/ -#define INCA_IP_Switch_PC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0008)) -#define INCA_IP_Switch_PC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_Switch_PC_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***LAN VLAN Configuration Register***/ -#define INCA_IP_Switch_LAN_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x000C)) -#define INCA_IP_Switch_LAN_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_Switch_LAN_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***CPU VLAN Configuration Register***/ -#define INCA_IP_Switch_CPU_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0010)) -#define INCA_IP_Switch_CPU_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_Switch_CPU_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***Priority CoS Mapping Register***/ -#define INCA_IP_Switch_PRI_CoS ((volatile u32*)(INCA_IP_Switch+ 0x0014)) -#define INCA_IP_Switch_PRI_CoS_P7 (1 << 7) -#define INCA_IP_Switch_PRI_CoS_P6 (1 << 6) -#define INCA_IP_Switch_PRI_CoS_P5 (1 << 5) -#define INCA_IP_Switch_PRI_CoS_P4 (1 << 4) -#define INCA_IP_Switch_PRI_CoS_P3 (1 << 3) -#define INCA_IP_Switch_PRI_CoS_P2 (1 << 2) -#define INCA_IP_Switch_PRI_CoS_P1 (1 << 1) -#define INCA_IP_Switch_PRI_CoS_P0 (1 << 0) - -/***Spanning Tree Port Status Register***/ -#define INCA_IP_Switch_ST_PT ((volatile u32*)(INCA_IP_Switch+ 0x0018)) -#define INCA_IP_Switch_ST_PT_CPS (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_Switch_ST_PT_LPS (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_Switch_ST_PT_PPS (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***ARL Control Register***/ -#define INCA_IP_Switch_ARL_CTL ((volatile u32*)(INCA_IP_Switch+ 0x001C)) -#define INCA_IP_Switch_ARL_CTL_CHCC (1 << 15) -#define INCA_IP_Switch_ARL_CTL_CHCL (1 << 14) -#define INCA_IP_Switch_ARL_CTL_CHCP (1 << 13) -#define INCA_IP_Switch_ARL_CTL_CC (1 << 12) -#define INCA_IP_Switch_ARL_CTL_CL (1 << 11) -#define INCA_IP_Switch_ARL_CTL_CP (1 << 10) -#define INCA_IP_Switch_ARL_CTL_CG (1 << 9) -#define INCA_IP_Switch_ARL_CTL_PS (1 << 8) -#define INCA_IP_Switch_ARL_CTL_MRO (1 << 7) -#define INCA_IP_Switch_ARL_CTL_SRC (1 << 6) -#define INCA_IP_Switch_ARL_CTL_ATS (1 << 5) -#define INCA_IP_Switch_ARL_CTL_AGE_TICK_SEL (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_ARL_CTL_MAF (1 << 1) -#define INCA_IP_Switch_ARL_CTL_ENL (1 << 0) -#define INCA_IP_Switch_ARL_CTL_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - -/***CPU Access Control Register***/ -#define INCA_IP_Switch_CPU_ACTL ((volatile u32*)(INCA_IP_Switch+ 0x0020)) -#define INCA_IP_Switch_CPU_ACTL_RA (1 << 31) -#define INCA_IP_Switch_CPU_ACTL_RW (1 << 30) -#define INCA_IP_Switch_CPU_ACTL_Res (value) (((( 1 << 21) - 1) & (value)) << 9) -#define INCA_IP_Switch_CPU_ACTL_AVA (1 << 8) -#define INCA_IP_Switch_CPU_ACTL_IDX (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***CPU Access Data Register 1***/ -#define INCA_IP_Switch_DATA1 ((volatile u32*)(INCA_IP_Switch+ 0x0024)) -#define INCA_IP_Switch_DATA1_Data (value) (((( 1 << 24) - 1) & (value)) << 0) - -/***CPU Access Data Register 2***/ -#define INCA_IP_Switch_DATA2 ((volatile u32*)(INCA_IP_Switch+ 0x0028)) -#define INCA_IP_Switch_DATA2_Data - -/***CPU Port Control Register***/ -#define INCA_IP_Switch_CPU_PCTL ((volatile u32*)(INCA_IP_Switch+ 0x002C)) -#define INCA_IP_Switch_CPU_PCTL_DA_PORTS (value) (((( 1 << 3) - 1) & (value)) << 11) -#define INCA_IP_Switch_CPU_PCTL_DAC (1 << 10) -#define INCA_IP_Switch_CPU_PCTL_MA_STATE (value) (((( 1 << 3) - 1) & (value)) << 7) -#define INCA_IP_Switch_CPU_PCTL_MAM (1 << 6) -#define INCA_IP_Switch_CPU_PCTL_MA_Ports (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_Switch_CPU_PCTL_MAC (1 << 2) -#define INCA_IP_Switch_CPU_PCTL_EML (1 << 1) -#define INCA_IP_Switch_CPU_PCTL_EDL (1 << 0) -#define INCA_IP_Switch_CPU_PCTL_Res (value) (((( 1 << 18) - 1) & (value)) << 14) - -/***DSCP CoS Mapping Register 1***/ -#define INCA_IP_Switch_DSCP_COS1 ((volatile u32*)(INCA_IP_Switch+ 0x0030)) -#define INCA_IP_Switch_DSCP_COS1_DSCP - -/***DSCP CoS Mapping Register 1***/ -#define INCA_IP_Switch_DSCP_COS2 ((volatile u32*)(INCA_IP_Switch+ 0x0034)) -#define INCA_IP_Switch_DSCP_COS2_DSCP - -/***PC WFQ Control Register***/ -#define INCA_IP_Switch_PC_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0080)) -#define INCA_IP_Switch_PC_WFQ_CTL_P1 (1 << 9) -#define INCA_IP_Switch_PC_WFQ_CTL_P0 (1 << 8) -#define INCA_IP_Switch_PC_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) -#define INCA_IP_Switch_PC_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_PC_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***PC TX Control Register***/ -#define INCA_IP_Switch_PC_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0084)) -#define INCA_IP_Switch_PC_TX_CTL_ELR (1 << 1) -#define INCA_IP_Switch_PC_TX_CTL_EER (1 << 0) - -/***LAN WFQ Control Register***/ -#define INCA_IP_Switch_LAN_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0100)) -#define INCA_IP_Switch_LAN_WFQ_CTL_P1 (1 << 9) -#define INCA_IP_Switch_LAN_WFQ_CTL_P0 (1 << 8) -#define INCA_IP_Switch_LAN_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) -#define INCA_IP_Switch_LAN_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_LAN_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***LAN TX Control Register***/ -#define INCA_IP_Switch_LAN_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0104)) -#define INCA_IP_Switch_LAN_TX_CTL_ELR (1 << 1) -#define INCA_IP_Switch_LAN_TX_CTL_EER (1 << 0) - -/***CPU WFQ Control Register***/ -#define INCA_IP_Switch_CPU_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0180)) -#define INCA_IP_Switch_CPU_WFQ_CTL_P1 (1 << 9) -#define INCA_IP_Switch_CPU_WFQ_CTL_P0 (1 << 8) -#define INCA_IP_Switch_CPU_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) -#define INCA_IP_Switch_CPU_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_CPU_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***PM PC RX Watermark Register***/ -#define INCA_IP_Switch_PC_WM ((volatile u32*)(INCA_IP_Switch+ 0x0200)) -#define INCA_IP_Switch_PC_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_PC_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_PC_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_PC_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM LAN RX Watermark Register***/ -#define INCA_IP_Switch_LAN_WM ((volatile u32*)(INCA_IP_Switch+ 0x0204)) -#define INCA_IP_Switch_LAN_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_LAN_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_LAN_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_LAN_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM CPU RX Watermark Register***/ -#define INCA_IP_Switch_CPU_WM ((volatile u32*)(INCA_IP_Switch+ 0x0208)) -#define INCA_IP_Switch_CPU_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_CPU_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_CPU_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_CPU_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM CPU RX Watermark Register***/ -#define INCA_IP_Switch_GBL_WM ((volatile u32*)(INCA_IP_Switch+ 0x020C)) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM Control Register***/ -#define INCA_IP_Switch_PM_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0210)) -#define INCA_IP_Switch_PM_CTL_GDN (1 << 3) -#define INCA_IP_Switch_PM_CTL_CDN (1 << 2) -#define INCA_IP_Switch_PM_CTL_LDN (1 << 1) -#define INCA_IP_Switch_PM_CTL_PDN (1 << 0) - -/***PM Header Control Register***/ -#define INCA_IP_Switch_PMAC_HD_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0280)) -#define INCA_IP_Switch_PMAC_HD_CTL_RL2 (1 << 21) -#define INCA_IP_Switch_PMAC_HD_CTL_RC (1 << 20) -#define INCA_IP_Switch_PMAC_HD_CTL_CM (1 << 19) -#define INCA_IP_Switch_PMAC_HD_CTL_CV (1 << 18) -#define INCA_IP_Switch_PMAC_HD_CTL_TYPE_LEN (value) (((( 1 << 16) - 1) & (value)) << 2) -#define INCA_IP_Switch_PMAC_HD_CTL_TAG (1 << 1) -#define INCA_IP_Switch_PMAC_HD_CTL_ADD (1 << 0) - -/***PM Source Address Register 1***/ -#define INCA_IP_Switch_PMAC_SA1 ((volatile u32*)(INCA_IP_Switch+ 0x0284)) -#define INCA_IP_Switch_PMAC_SA1_SA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***PM Source Address Register 2***/ -#define INCA_IP_Switch_PMAC_SA2 ((volatile u32*)(INCA_IP_Switch+ 0x0288)) -#define INCA_IP_Switch_PMAC_SA2_SA_31_0 - -/***PM Dest Address Register 1***/ -#define INCA_IP_Switch_PMAC_DA1 ((volatile u32*)(INCA_IP_Switch+ 0x028C)) -#define INCA_IP_Switch_PMAC_DA1_DA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***PM Dest Address Register 2***/ -#define INCA_IP_Switch_PMAC_DA2 ((volatile u32*)(INCA_IP_Switch+ 0x0290)) -#define INCA_IP_Switch_PMAC_DA2_DA_31_0 - -/***PM VLAN Register***/ -#define INCA_IP_Switch_PMAC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0294)) -#define INCA_IP_Switch_PMAC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 13) -#define INCA_IP_Switch_PMAC_VLAN_CFI (1 << 12) -#define INCA_IP_Switch_PMAC_VLAN_VLANID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***PM TX IPG Counter Register***/ -#define INCA_IP_Switch_PMAC_TX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x0298)) -#define INCA_IP_Switch_PMAC_TX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM RX IPG Counter Register***/ -#define INCA_IP_Switch_PMAC_RX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x029C)) -#define INCA_IP_Switch_PMAC_RX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Mirror Register***/ -#define INCA_IP_Switch_MRR ((volatile u32*)(INCA_IP_Switch+ 0x0300)) -#define INCA_IP_Switch_MRR_MRR (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_Switch_MRR_EC (1 << 5) -#define INCA_IP_Switch_MRR_EL (1 << 4) -#define INCA_IP_Switch_MRR_EP (1 << 3) -#define INCA_IP_Switch_MRR_IC (1 << 2) -#define INCA_IP_Switch_MRR_IL (1 << 1) -#define INCA_IP_Switch_MRR_IP (1 << 0) - -/***Packet Length Register***/ -#define INCA_IP_Switch_PKT_LEN ((volatile u32*)(INCA_IP_Switch+ 0x0304)) -#define INCA_IP_Switch_PKT_LEN_ADD (1 << 11) -#define INCA_IP_Switch_PKT_LEN_MAX_PKT_LEN (value) (((( 1 << 11) - 1) & (value)) << 0) - -/***MDIO Access Register***/ -#define INCA_IP_Switch_MDIO_ACC ((volatile u32*)(INCA_IP_Switch+ 0x0480)) -#define INCA_IP_Switch_MDIO_ACC_RA (1 << 31) -#define INCA_IP_Switch_MDIO_ACC_RW (1 << 30) -#define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value) (((( 1 << 5) - 1) & (value)) << 21) -#define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value) (((( 1 << 5) - 1) & (value)) << 16) -#define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Ethernet PHY Register***/ -#define INCA_IP_Switch_EPHY ((volatile u32*)(INCA_IP_Switch+ 0x0484)) -#define INCA_IP_Switch_EPHY_SL (1 << 7) -#define INCA_IP_Switch_EPHY_SP (1 << 6) -#define INCA_IP_Switch_EPHY_LL (1 << 5) -#define INCA_IP_Switch_EPHY_LP (1 << 4) -#define INCA_IP_Switch_EPHY_DL (1 << 3) -#define INCA_IP_Switch_EPHY_DP (1 << 2) -#define INCA_IP_Switch_EPHY_PL (1 << 1) -#define INCA_IP_Switch_EPHY_PP (1 << 0) - -/***Pause Write Enable Register***/ -#define INCA_IP_Switch_PWR_EN ((volatile u32*)(INCA_IP_Switch+ 0x0488)) -#define INCA_IP_Switch_PWR_EN_PL (1 << 1) -#define INCA_IP_Switch_PWR_EN_PP (1 << 0) - -/***MDIO Configuration Register***/ -#define INCA_IP_Switch_MDIO_CFG ((volatile u32*)(INCA_IP_Switch+ 0x048C)) -#define INCA_IP_Switch_MDIO_CFG_MDS (value) (((( 1 << 2) - 1) & (value)) << 14) -#define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value) (((( 1 << 5) - 1) & (value)) << 9) -#define INCA_IP_Switch_MDIO_CFG_PHY_PC_ADDR (value) (((( 1 << 5) - 1) & (value)) << 4) -#define INCA_IP_Switch_MDIO_CFG_UEP (1 << 3) -#define INCA_IP_Switch_MDIO_CFG_PS (1 << 2) -#define INCA_IP_Switch_MDIO_CFG_PT (1 << 1) -#define INCA_IP_Switch_MDIO_CFG_UMM (1 << 0) - -/***Clock Configuration Register***/ -#define INCA_IP_Switch_CLK_CFG ((volatile u32*)(INCA_IP_Switch+ 0x0500)) -#define INCA_IP_Switch_CLK_CFG_ARL_ID (1 << 9) -#define INCA_IP_Switch_CLK_CFG_CPU_ID (1 << 8) -#define INCA_IP_Switch_CLK_CFG_LAN_ID (1 << 7) -#define INCA_IP_Switch_CLK_CFG_PC_ID (1 << 6) -#define INCA_IP_Switch_CLK_CFG_SE_ID (1 << 5) - -/***********************************************************************/ -/* Module : SSC1 register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SSC1 (0xB8000500) -/***********************************************************************/ - - -/***Control Register (Programming Mode)***/ -#define INCA_IP_SSC1_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) -#define INCA_IP_SSC1_SCC_CON_PRG_EN (1 << 15) -#define INCA_IP_SSC1_SCC_CON_PRG_MS (1 << 14) -#define INCA_IP_SSC1_SCC_CON_PRG_AREN (1 << 12) -#define INCA_IP_SSC1_SCC_CON_PRG_BEN (1 << 11) -#define INCA_IP_SSC1_SCC_CON_PRG_PEN (1 << 10) -#define INCA_IP_SSC1_SCC_CON_PRG_REN (1 << 9) -#define INCA_IP_SSC1_SCC_CON_PRG_TEN (1 << 8) -#define INCA_IP_SSC1_SCC_CON_PRG_LB (1 << 7) -#define INCA_IP_SSC1_SCC_CON_PRG_PO (1 << 6) -#define INCA_IP_SSC1_SCC_CON_PRG_PH (1 << 5) -#define INCA_IP_SSC1_SCC_CON_PRG_HB (1 << 4) -#define INCA_IP_SSC1_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SCC Control Register (Operating Mode)***/ -#define INCA_IP_SSC1_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) -#define INCA_IP_SSC1_SCC_CON_OPR_EN (1 << 15) -#define INCA_IP_SSC1_SCC_CON_OPR_MS (1 << 14) -#define INCA_IP_SSC1_SCC_CON_OPR_BSY (1 << 12) -#define INCA_IP_SSC1_SCC_CON_OPR_BE (1 << 11) -#define INCA_IP_SSC1_SCC_CON_OPR_PE (1 << 10) -#define INCA_IP_SSC1_SCC_CON_OPR_RE (1 << 9) -#define INCA_IP_SSC1_SCC_CON_OPR_TE (1 << 8) -#define INCA_IP_SSC1_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SSC Write Hardware Modified Control Register***/ -#define INCA_IP_SSC1_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC1+ 0x0040)) -#define INCA_IP_SSC1_SSC_WHBCON_SETBE (1 << 15) -#define INCA_IP_SSC1_SSC_WHBCON_SETPE (1 << 14) -#define INCA_IP_SSC1_SSC_WHBCON_SETRE (1 << 13) -#define INCA_IP_SSC1_SSC_WHBCON_SETTE (1 << 12) -#define INCA_IP_SSC1_SSC_WHBCON_CLRBE (1 << 11) -#define INCA_IP_SSC1_SSC_WHBCON_CLRPE (1 << 10) -#define INCA_IP_SSC1_SSC_WHBCON_CLRRE (1 << 9) -#define INCA_IP_SSC1_SSC_WHBCON_CLRTE (1 << 8) - -/***SSC Baudrate Timer Reload Register***/ -#define INCA_IP_SSC1_SSC_BR ((volatile u32*)(INCA_IP_SSC1+ 0x0014)) -#define INCA_IP_SSC1_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Transmitter Buffer Register***/ -#define INCA_IP_SSC1_SSC_TB ((volatile u32*)(INCA_IP_SSC1+ 0x0020)) -#define INCA_IP_SSC1_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receiver Buffer Register***/ -#define INCA_IP_SSC1_SSC_RB ((volatile u32*)(INCA_IP_SSC1+ 0x0024)) -#define INCA_IP_SSC1_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receive FIFO Control Register***/ -#define INCA_IP_SSC1_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0030)) -#define INCA_IP_SSC1_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_RXFCON_RXTMEN (1 << 2) -#define INCA_IP_SSC1_SSC_RXFCON_RXFLU (1 << 1) -#define INCA_IP_SSC1_SSC_RXFCON_RXFEN (1 << 0) - -/***SSC Transmit FIFO Control Register***/ -#define INCA_IP_SSC1_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0034)) -#define INCA_IP_SSC1_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_TXFCON_TXTMEN (1 << 2) -#define INCA_IP_SSC1_SSC_TXFCON_TXFLU (1 << 1) -#define INCA_IP_SSC1_SSC_TXFCON_TXFEN (1 << 0) - -/***SSC FIFO Status Register***/ -#define INCA_IP_SSC1_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC1+ 0x0038)) -#define INCA_IP_SSC1_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***SSC Clock Control Register***/ -#define INCA_IP_SSC1_SSC_CLC ((volatile u32*)(INCA_IP_SSC1+ 0x0000)) -#define INCA_IP_SSC1_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_CLC_DISS (1 << 1) -#define INCA_IP_SSC1_SSC_CLC_DISR (1 << 0) - -/***********************************************************************/ -/* Module : SSC2 register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SSC2 (0xB8000600) -/***********************************************************************/ - - -/***Control Register (Programming Mode)***/ -#define INCA_IP_SSC2_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) -#define INCA_IP_SSC2_SCC_CON_PRG_EN (1 << 15) -#define INCA_IP_SSC2_SCC_CON_PRG_MS (1 << 14) -#define INCA_IP_SSC2_SCC_CON_PRG_AREN (1 << 12) -#define INCA_IP_SSC2_SCC_CON_PRG_BEN (1 << 11) -#define INCA_IP_SSC2_SCC_CON_PRG_PEN (1 << 10) -#define INCA_IP_SSC2_SCC_CON_PRG_REN (1 << 9) -#define INCA_IP_SSC2_SCC_CON_PRG_TEN (1 << 8) -#define INCA_IP_SSC2_SCC_CON_PRG_LB (1 << 7) -#define INCA_IP_SSC2_SCC_CON_PRG_PO (1 << 6) -#define INCA_IP_SSC2_SCC_CON_PRG_PH (1 << 5) -#define INCA_IP_SSC2_SCC_CON_PRG_HB (1 << 4) -#define INCA_IP_SSC2_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SCC Control Register (Operating Mode)***/ -#define INCA_IP_SSC2_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) -#define INCA_IP_SSC2_SCC_CON_OPR_EN (1 << 15) -#define INCA_IP_SSC2_SCC_CON_OPR_MS (1 << 14) -#define INCA_IP_SSC2_SCC_CON_OPR_BSY (1 << 12) -#define INCA_IP_SSC2_SCC_CON_OPR_BE (1 << 11) -#define INCA_IP_SSC2_SCC_CON_OPR_PE (1 << 10) -#define INCA_IP_SSC2_SCC_CON_OPR_RE (1 << 9) -#define INCA_IP_SSC2_SCC_CON_OPR_TE (1 << 8) -#define INCA_IP_SSC2_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SSC Write Hardware Modified Control Register***/ -#define INCA_IP_SSC2_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC2+ 0x0040)) -#define INCA_IP_SSC2_SSC_WHBCON_SETBE (1 << 15) -#define INCA_IP_SSC2_SSC_WHBCON_SETPE (1 << 14) -#define INCA_IP_SSC2_SSC_WHBCON_SETRE (1 << 13) -#define INCA_IP_SSC2_SSC_WHBCON_SETTE (1 << 12) -#define INCA_IP_SSC2_SSC_WHBCON_CLRBE (1 << 11) -#define INCA_IP_SSC2_SSC_WHBCON_CLRPE (1 << 10) -#define INCA_IP_SSC2_SSC_WHBCON_CLRRE (1 << 9) -#define INCA_IP_SSC2_SSC_WHBCON_CLRTE (1 << 8) - -/***SSC Baudrate Timer Reload Register***/ -#define INCA_IP_SSC2_SSC_BR ((volatile u32*)(INCA_IP_SSC2+ 0x0014)) -#define INCA_IP_SSC2_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Transmitter Buffer Register***/ -#define INCA_IP_SSC2_SSC_TB ((volatile u32*)(INCA_IP_SSC2+ 0x0020)) -#define INCA_IP_SSC2_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receiver Buffer Register***/ -#define INCA_IP_SSC2_SSC_RB ((volatile u32*)(INCA_IP_SSC2+ 0x0024)) -#define INCA_IP_SSC2_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receive FIFO Control Register***/ -#define INCA_IP_SSC2_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0030)) -#define INCA_IP_SSC2_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_RXFCON_RXTMEN (1 << 2) -#define INCA_IP_SSC2_SSC_RXFCON_RXFLU (1 << 1) -#define INCA_IP_SSC2_SSC_RXFCON_RXFEN (1 << 0) - -/***SSC Transmit FIFO Control Register***/ -#define INCA_IP_SSC2_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0034)) -#define INCA_IP_SSC2_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_TXFCON_TXTMEN (1 << 2) -#define INCA_IP_SSC2_SSC_TXFCON_TXFLU (1 << 1) -#define INCA_IP_SSC2_SSC_TXFCON_TXFEN (1 << 0) - -/***SSC FIFO Status Register***/ -#define INCA_IP_SSC2_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC2+ 0x0038)) -#define INCA_IP_SSC2_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***SSC Clock Control Register***/ -#define INCA_IP_SSC2_SSC_CLC ((volatile u32*)(INCA_IP_SSC2+ 0x0000)) -#define INCA_IP_SSC2_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_CLC_DISS (1 << 1) -#define INCA_IP_SSC2_SSC_CLC_DISR (1 << 0) - -/***********************************************************************/ -/* Module : EBU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_EBU (0xB8000200) -/***********************************************************************/ - - -/***EBU Clock Control Register***/ -#define INCA_IP_EBU_EBU_CLC ((volatile u32*)(INCA_IP_EBU+ 0x0000)) -#define INCA_IP_EBU_EBU_CLC_DISS (1 << 1) -#define INCA_IP_EBU_EBU_CLC_DISR (1 << 0) - -/***EBU Global Control Register***/ -#define INCA_IP_EBU_EBU_CON ((volatile u32*)(INCA_IP_EBU+ 0x0010)) -#define INCA_IP_EBU_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_EBU_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_CON_ARBSYNC (1 << 5) -#define INCA_IP_EBU_EBU_CON_1 (1 << 3) - -/***EBU Address Select Register 0***/ -#define INCA_IP_EBU_EBU_ADDSEL0 ((volatile u32*)(INCA_IP_EBU+ 0x0020)) -#define INCA_IP_EBU_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define INCA_IP_EBU_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_ADDSEL0_MIRRORE (1 << 1) -#define INCA_IP_EBU_EBU_ADDSEL0_REGEN (1 << 0) - -/***EBU Address Select Register 1***/ -#define INCA_IP_EBU_EBU_ADDSEL1 ((volatile u32*)(INCA_IP_EBU+ 0x0024)) -#define INCA_IP_EBU_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define INCA_IP_EBU_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_ADDSEL1_MIRRORE (1 << 1) -#define INCA_IP_EBU_EBU_ADDSEL1_REGEN (1 << 0) - -/***EBU Address Select Register 2***/ -#define INCA_IP_EBU_EBU_ADDSEL2 ((volatile u32*)(INCA_IP_EBU+ 0x0028)) -#define INCA_IP_EBU_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define INCA_IP_EBU_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_ADDSEL2_MIRRORE (1 << 1) -#define INCA_IP_EBU_EBU_ADDSEL2_REGEN (1 << 0) - -/***EBU Bus Configuration Register 0***/ -#define INCA_IP_EBU_EBU_BUSCON0 ((volatile u32*)(INCA_IP_EBU+ 0x0060)) -#define INCA_IP_EBU_EBU_BUSCON0_WRDIS (1 << 31) -#define INCA_IP_EBU_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_EBU_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define INCA_IP_EBU_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_EBU_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define INCA_IP_EBU_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_BUSCON0_WAITINV (1 << 19) -#define INCA_IP_EBU_EBU_BUSCON0_SETUP (1 << 18) -#define INCA_IP_EBU_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define INCA_IP_EBU_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 1***/ -#define INCA_IP_EBU_EBU_BUSCON1 ((volatile u32*)(INCA_IP_EBU+ 0x0064)) -#define INCA_IP_EBU_EBU_BUSCON1_WRDIS (1 << 31) -#define INCA_IP_EBU_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_EBU_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define INCA_IP_EBU_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_EBU_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define INCA_IP_EBU_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_BUSCON1_WAITINV (1 << 19) -#define INCA_IP_EBU_EBU_BUSCON1_SETUP (1 << 18) -#define INCA_IP_EBU_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define INCA_IP_EBU_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 2***/ -#define INCA_IP_EBU_EBU_BUSCON2 ((volatile u32*)(INCA_IP_EBU+ 0x0068)) -#define INCA_IP_EBU_EBU_BUSCON2_WRDIS (1 << 31) -#define INCA_IP_EBU_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_EBU_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define INCA_IP_EBU_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_EBU_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define INCA_IP_EBU_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_BUSCON2_WAITINV (1 << 19) -#define INCA_IP_EBU_EBU_BUSCON2_SETUP (1 << 18) -#define INCA_IP_EBU_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define INCA_IP_EBU_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : SDRAM register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SDRAM (0xBF800000) -/***********************************************************************/ - - -/***MC Access Error Cause Register***/ -#define INCA_IP_SDRAM_MC_ERRCAUSE ((volatile u32*)(INCA_IP_SDRAM+ 0x0100)) -#define INCA_IP_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -#define INCA_IP_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***MC Access Error Address Register***/ -#define INCA_IP_SDRAM_MC_ERRADDR ((volatile u32*)(INCA_IP_SDRAM+ 0x0108)) -#define INCA_IP_SDRAM_MC_ERRADDR_ADDR - -/***MC I/O General Purpose Register***/ -#define INCA_IP_SDRAM_MC_IOGP ((volatile u32*)(INCA_IP_SDRAM+ 0x0800)) -#define INCA_IP_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28) -#define INCA_IP_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24) -#define INCA_IP_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20) -#define INCA_IP_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define INCA_IP_SDRAM_MC_IOGP_CPS (1 << 11) -#define INCA_IP_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***MC Self Refresh Register***/ -#define INCA_IP_SDRAM_MC_SELFRFSH ((volatile u32*)(INCA_IP_SDRAM+ 0x0A00)) -#define INCA_IP_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -#define INCA_IP_SDRAM_MC_SELFRFSH_PWD (1 << 0) -#define INCA_IP_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2) - -/***MC Enable Register***/ -#define INCA_IP_SDRAM_MC_CTRLENA ((volatile u32*)(INCA_IP_SDRAM+ 0x1000)) -#define INCA_IP_SDRAM_MC_CTRLENA_ENA (1 << 0) -#define INCA_IP_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1) - -/***MC Mode Register Setup Code***/ -#define INCA_IP_SDRAM_MC_MRSCODE ((volatile u32*)(INCA_IP_SDRAM+ 0x1008)) -#define INCA_IP_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7) -#define INCA_IP_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_MRSCODE_WT (1 << 3) -#define INCA_IP_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***MC Configuration Data-word Width Register***/ -#define INCA_IP_SDRAM_MC_CFGDW ((volatile u32*)(INCA_IP_SDRAM+ 0x1010)) -#define INCA_IP_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4) - -/***MC Configuration Physical Bank 0 Register***/ -#define INCA_IP_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP_SDRAM+ 0x1018)) -#define INCA_IP_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define INCA_IP_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8) -#define INCA_IP_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16) - -/***MC Latency Register***/ -#define INCA_IP_SDRAM_MC_LATENCY ((volatile u32*)(INCA_IP_SDRAM+ 0x1038)) -#define INCA_IP_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12) -#define INCA_IP_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8) -#define INCA_IP_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20) - -/***MC Refresh Cycle Time Register***/ -#define INCA_IP_SDRAM_MC_TREFRESH ((volatile u32*)(INCA_IP_SDRAM+ 0x1040)) -#define INCA_IP_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - -/***********************************************************************/ -/* Module : GPTU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_GPTU (0xB8000300) -/***********************************************************************/ - - -/***GPT Clock Control Register***/ -#define INCA_IP_GPTU_GPT_CLC ((volatile u32*)(INCA_IP_GPTU+ 0x0000)) -#define INCA_IP_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_GPTU_GPT_CLC_DISS (1 << 1) -#define INCA_IP_GPTU_GPT_CLC_DISR (1 << 0) - -/***GPT Timer 3 Control Register***/ -#define INCA_IP_GPTU_GPT_T3CON ((volatile u32*)(INCA_IP_GPTU+ 0x0014)) -#define INCA_IP_GPTU_GPT_T3CON_T3RDIR (1 << 15) -#define INCA_IP_GPTU_GPT_T3CON_T3CHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_T3CON_T3EDGE (1 << 13) -#define INCA_IP_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define INCA_IP_GPTU_GPT_T3CON_T3OTL (1 << 10) -#define INCA_IP_GPTU_GPT_T3CON_T3UD (1 << 7) -#define INCA_IP_GPTU_GPT_T3CON_T3R (1 << 6) -#define INCA_IP_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write Hardware Modified Timer 3 Control Register -If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT3CON ((volatile u32*)(INCA_IP_GPTU+ 0x004C)) -#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15) -#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13) -#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12) -#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11) -#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10) - -/***GPT Timer 2 Control Register***/ -#define INCA_IP_GPTU_GPT_T2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0010)) -#define INCA_IP_GPTU_GPT_T2CON_TxRDIR (1 << 15) -#define INCA_IP_GPTU_GPT_T2CON_TxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_T2CON_TxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_T2CON_TxIRDIS (1 << 12) -#define INCA_IP_GPTU_GPT_T2CON_TxRC (1 << 9) -#define INCA_IP_GPTU_GPT_T2CON_TxUD (1 << 7) -#define INCA_IP_GPTU_GPT_T2CON_TxR (1 << 6) -#define INCA_IP_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Timer 4 Control Register***/ -#define INCA_IP_GPTU_GPT_T4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0018)) -#define INCA_IP_GPTU_GPT_T4CON_TxRDIR (1 << 15) -#define INCA_IP_GPTU_GPT_T4CON_TxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_T4CON_TxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_T4CON_TxIRDIS (1 << 12) -#define INCA_IP_GPTU_GPT_T4CON_TxRC (1 << 9) -#define INCA_IP_GPTU_GPT_T4CON_TxUD (1 << 7) -#define INCA_IP_GPTU_GPT_T4CON_TxR (1 << 6) -#define INCA_IP_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 2 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0048)) -#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15) -#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12) - -/***GPT Write HW Modified Timer 4 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0050)) -#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15) -#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12) - -/***GPT Capture Reload Register***/ -#define INCA_IP_GPTU_GPT_CAPREL ((volatile u32*)(INCA_IP_GPTU+ 0x0030)) -#define INCA_IP_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 2 Register***/ -#define INCA_IP_GPTU_GPT_T2 ((volatile u32*)(INCA_IP_GPTU+ 0x0034)) -#define INCA_IP_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 3 Register***/ -#define INCA_IP_GPTU_GPT_T3 ((volatile u32*)(INCA_IP_GPTU+ 0x0038)) -#define INCA_IP_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 4 Register***/ -#define INCA_IP_GPTU_GPT_T4 ((volatile u32*)(INCA_IP_GPTU+ 0x003C)) -#define INCA_IP_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 5 Register***/ -#define INCA_IP_GPTU_GPT_T5 ((volatile u32*)(INCA_IP_GPTU+ 0x0040)) -#define INCA_IP_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Register***/ -#define INCA_IP_GPTU_GPT_T6 ((volatile u32*)(INCA_IP_GPTU+ 0x0044)) -#define INCA_IP_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Control Register***/ -#define INCA_IP_GPTU_GPT_T6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0020)) -#define INCA_IP_GPTU_GPT_T6CON_T6SR (1 << 15) -#define INCA_IP_GPTU_GPT_T6CON_T6CLR (1 << 14) -#define INCA_IP_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define INCA_IP_GPTU_GPT_T6CON_T6OTL (1 << 10) -#define INCA_IP_GPTU_GPT_T6CON_T6UD (1 << 7) -#define INCA_IP_GPTU_GPT_T6CON_T6R (1 << 6) -#define INCA_IP_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 6 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0054)) -#define INCA_IP_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11) -#define INCA_IP_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10) - -/***GPT Timer 5 Control Register***/ -#define INCA_IP_GPTU_GPT_T5CON ((volatile u32*)(INCA_IP_GPTU+ 0x001C)) -#define INCA_IP_GPTU_GPT_T5CON_T5SC (1 << 15) -#define INCA_IP_GPTU_GPT_T5CON_T5CLR (1 << 14) -#define INCA_IP_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12) -#define INCA_IP_GPTU_GPT_T5CON_T5CC (1 << 11) -#define INCA_IP_GPTU_GPT_T5CON_CT3 (1 << 10) -#define INCA_IP_GPTU_GPT_T5CON_T5RC (1 << 9) -#define INCA_IP_GPTU_GPT_T5CON_T5UDE (1 << 8) -#define INCA_IP_GPTU_GPT_T5CON_T5UD (1 << 7) -#define INCA_IP_GPTU_GPT_T5CON_T5R (1 << 6) -#define INCA_IP_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : IOM register address and bits */ -/***********************************************************************/ - -#define INCA_IP_IOM (0xBF105000) -/***********************************************************************/ - - -/***Receive FIFO***/ -#define INCA_IP_IOM_RFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) -#define INCA_IP_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Transmit FIFO***/ -#define INCA_IP_IOM_XFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) -#define INCA_IP_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Interrupt Status Register HDLC***/ -#define INCA_IP_IOM_ISTAH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) -#define INCA_IP_IOM_ISTAH_RME (1 << 7) -#define INCA_IP_IOM_ISTAH_RPF (1 << 6) -#define INCA_IP_IOM_ISTAH_RFO (1 << 5) -#define INCA_IP_IOM_ISTAH_XPR (1 << 4) -#define INCA_IP_IOM_ISTAH_XMR (1 << 3) -#define INCA_IP_IOM_ISTAH_XDU (1 << 2) - -/***Interrupt Mask Register HDLC***/ -#define INCA_IP_IOM_MASKH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) -#define INCA_IP_IOM_MASKH_RME (1 << 7) -#define INCA_IP_IOM_MASKH_RPF (1 << 6) -#define INCA_IP_IOM_MASKH_RFO (1 << 5) -#define INCA_IP_IOM_MASKH_XPR (1 << 4) -#define INCA_IP_IOM_MASKH_XMR (1 << 3) -#define INCA_IP_IOM_MASKH_XDU (1 << 2) - -/***Status Register***/ -#define INCA_IP_IOM_STAR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) -#define INCA_IP_IOM_STAR_XDOV (1 << 7) -#define INCA_IP_IOM_STAR_XFW (1 << 6) -#define INCA_IP_IOM_STAR_RACI (1 << 3) -#define INCA_IP_IOM_STAR_XACI (1 << 1) - -/***Command Register***/ -#define INCA_IP_IOM_CMDR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) -#define INCA_IP_IOM_CMDR_RMC (1 << 7) -#define INCA_IP_IOM_CMDR_RRES (1 << 6) -#define INCA_IP_IOM_CMDR_XTF (1 << 3) -#define INCA_IP_IOM_CMDR_XME (1 << 1) -#define INCA_IP_IOM_CMDR_XRES (1 << 0) - -/***Mode Register***/ -#define INCA_IP_IOM_MODEH ((volatile u32*)(INCA_IP_IOM+ 0x0088)) -#define INCA_IP_IOM_MODEH_MDS2 (1 << 7) -#define INCA_IP_IOM_MODEH_MDS1 (1 << 6) -#define INCA_IP_IOM_MODEH_MDS0 (1 << 5) -#define INCA_IP_IOM_MODEH_RAC (1 << 3) -#define INCA_IP_IOM_MODEH_DIM2 (1 << 2) -#define INCA_IP_IOM_MODEH_DIM1 (1 << 1) -#define INCA_IP_IOM_MODEH_DIM0 (1 << 0) - -/***Extended Mode Register***/ -#define INCA_IP_IOM_EXMR ((volatile u32*)(INCA_IP_IOM+ 0x008C)) -#define INCA_IP_IOM_EXMR_XFBS (1 << 7) -#define INCA_IP_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5) -#define INCA_IP_IOM_EXMR_SRA (1 << 4) -#define INCA_IP_IOM_EXMR_XCRC (1 << 3) -#define INCA_IP_IOM_EXMR_RCRC (1 << 2) -#define INCA_IP_IOM_EXMR_ITF (1 << 0) - -/***SAPI1 Register***/ -#define INCA_IP_IOM_SAP1 ((volatile u32*)(INCA_IP_IOM+ 0x0094)) -#define INCA_IP_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define INCA_IP_IOM_SAP1_MHA (1 << 0) - -/***Receive Frame Byte Count Low***/ -#define INCA_IP_IOM_RBCL ((volatile u32*)(INCA_IP_IOM+ 0x0098)) -#define INCA_IP_IOM_RBCL_RBC(value) (1 << value) - - -/***SAPI2 Register***/ -#define INCA_IP_IOM_SAP2 ((volatile u32*)(INCA_IP_IOM+ 0x0098)) -#define INCA_IP_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define INCA_IP_IOM_SAP2_MLA (1 << 0) - -/***Receive Frame Byte Count High***/ -#define INCA_IP_IOM_RBCH ((volatile u32*)(INCA_IP_IOM+ 0x009C)) -#define INCA_IP_IOM_RBCH_OV (1 << 4) -#define INCA_IP_IOM_RBCH_RBC11 (1 << 3) -#define INCA_IP_IOM_RBCH_RBC10 (1 << 2) -#define INCA_IP_IOM_RBCH_RBC9 (1 << 1) -#define INCA_IP_IOM_RBCH_RBC8 (1 << 0) - -/***TEI1 Register 1***/ -#define INCA_IP_IOM_TEI1 ((volatile u32*)(INCA_IP_IOM+ 0x009C)) -#define INCA_IP_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define INCA_IP_IOM_TEI1_EA (1 << 0) - -/***Receive Status Register***/ -#define INCA_IP_IOM_RSTA ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) -#define INCA_IP_IOM_RSTA_VFR (1 << 7) -#define INCA_IP_IOM_RSTA_RDO (1 << 6) -#define INCA_IP_IOM_RSTA_CRC (1 << 5) -#define INCA_IP_IOM_RSTA_RAB (1 << 4) -#define INCA_IP_IOM_RSTA_SA1 (1 << 3) -#define INCA_IP_IOM_RSTA_SA0 (1 << 2) -#define INCA_IP_IOM_RSTA_TA (1 << 0) -#define INCA_IP_IOM_RSTA_CR (1 << 1) - -/***TEI2 Register***/ -#define INCA_IP_IOM_TEI2 ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) -#define INCA_IP_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define INCA_IP_IOM_TEI2_EA (1 << 0) - -/***Test Mode Register HDLC***/ -#define INCA_IP_IOM_TMH ((volatile u32*)(INCA_IP_IOM+ 0x00A4)) -#define INCA_IP_IOM_TMH_TLP (1 << 0) - -/***Command/Indication Receive 0***/ -#define INCA_IP_IOM_CIR0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) -#define INCA_IP_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_IOM_CIR0_CIC0 (1 << 3) -#define INCA_IP_IOM_CIR0_CIC1 (1 << 2) -#define INCA_IP_IOM_CIR0_SG (1 << 1) -#define INCA_IP_IOM_CIR0_BAS (1 << 0) - -/***Command/Indication Transmit 0***/ -#define INCA_IP_IOM_CIX0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) -#define INCA_IP_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_IOM_CIX0_TBA2 (1 << 3) -#define INCA_IP_IOM_CIX0_TBA1 (1 << 2) -#define INCA_IP_IOM_CIX0_TBA0 (1 << 1) -#define INCA_IP_IOM_CIX0_BAC (1 << 0) - -/***Command/Indication Receive 1***/ -#define INCA_IP_IOM_CIR1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) -#define INCA_IP_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2) - -/***Command/Indication Transmit 1***/ -#define INCA_IP_IOM_CIX1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) -#define INCA_IP_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define INCA_IP_IOM_CIX1_CICW (1 << 1) -#define INCA_IP_IOM_CIX1_CI1E (1 << 0) - -/***Controller Data Access Reg. (CH10)***/ -#define INCA_IP_IOM_CDA10 ((volatile u32*)(INCA_IP_IOM+ 0x0100)) -#define INCA_IP_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH11)***/ -#define INCA_IP_IOM_CDA11 ((volatile u32*)(INCA_IP_IOM+ 0x0104)) -#define INCA_IP_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH20)***/ -#define INCA_IP_IOM_CDA20 ((volatile u32*)(INCA_IP_IOM+ 0x0108)) -#define INCA_IP_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH21)***/ -#define INCA_IP_IOM_CDA21 ((volatile u32*)(INCA_IP_IOM+ 0x010C)) -#define INCA_IP_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define INCA_IP_IOM_CDA_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0110)) -#define INCA_IP_IOM_CDA_TSDP10_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define INCA_IP_IOM_CDA_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0114)) -#define INCA_IP_IOM_CDA_TSDP11_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define INCA_IP_IOM_CDA_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0118)) -#define INCA_IP_IOM_CDA_TSDP20_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define INCA_IP_IOM_CDA_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x011C)) -#define INCA_IP_IOM_CDA_TSDP21_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define INCA_IP_IOM_CO_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0120)) -#define INCA_IP_IOM_CO_TSDP10_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define INCA_IP_IOM_CO_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0124)) -#define INCA_IP_IOM_CO_TSDP11_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define INCA_IP_IOM_CO_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0128)) -#define INCA_IP_IOM_CO_TSDP20_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define INCA_IP_IOM_CO_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x012C)) -#define INCA_IP_IOM_CO_TSDP21_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define INCA_IP_IOM_CDA1_CR ((volatile u32*)(INCA_IP_IOM+ 0x0138)) -#define INCA_IP_IOM_CDA1_CR_EN_TBM (1 << 5) -#define INCA_IP_IOM_CDA1_CR_EN_I1 (1 << 4) -#define INCA_IP_IOM_CDA1_CR_EN_I0 (1 << 3) -#define INCA_IP_IOM_CDA1_CR_EN_O1 (1 << 2) -#define INCA_IP_IOM_CDA1_CR_EN_O0 (1 << 1) -#define INCA_IP_IOM_CDA1_CR_SWAP (1 << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define INCA_IP_IOM_CDA2_CR ((volatile u32*)(INCA_IP_IOM+ 0x013C)) -#define INCA_IP_IOM_CDA2_CR_EN_TBM (1 << 5) -#define INCA_IP_IOM_CDA2_CR_EN_I1 (1 << 4) -#define INCA_IP_IOM_CDA2_CR_EN_I0 (1 << 3) -#define INCA_IP_IOM_CDA2_CR_EN_O1 (1 << 2) -#define INCA_IP_IOM_CDA2_CR_EN_O0 (1 << 1) -#define INCA_IP_IOM_CDA2_CR_SWAP (1 << 0) - -/***Control Register B-Channel Data***/ -#define INCA_IP_IOM_BCHA_CR ((volatile u32*)(INCA_IP_IOM+ 0x0144)) -#define INCA_IP_IOM_BCHA_CR_EN_BC2 (1 << 4) -#define INCA_IP_IOM_BCHA_CR_EN_BC1 (1 << 3) - -/***Control Register B-Channel Data***/ -#define INCA_IP_IOM_BCHB_CR ((volatile u32*)(INCA_IP_IOM+ 0x0148)) -#define INCA_IP_IOM_BCHB_CR_EN_BC2 (1 << 4) -#define INCA_IP_IOM_BCHB_CR_EN_BC1 (1 << 3) - -/***Control Reg. for HDLC and CI1 Data***/ -#define INCA_IP_IOM_DCI_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) -#define INCA_IP_IOM_DCI_CR_DPS_CI1 (1 << 7) -#define INCA_IP_IOM_DCI_CR_EN_CI1 (1 << 6) -#define INCA_IP_IOM_DCI_CR_EN_D (1 << 5) - -/***Control Reg. for HDLC and CI1 Data***/ -#define INCA_IP_IOM_DCIC_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) -#define INCA_IP_IOM_DCIC_CR_DPS_CI0 (1 << 7) -#define INCA_IP_IOM_DCIC_CR_EN_CI0 (1 << 6) -#define INCA_IP_IOM_DCIC_CR_DPS_D (1 << 5) - -/***Control Reg. Serial Data Strobe x***/ -#define INCA_IP_IOM_SDS_CR ((volatile u32*)(INCA_IP_IOM+ 0x0154)) -#define INCA_IP_IOM_SDS_CR_ENS_TSS (1 << 7) -#define INCA_IP_IOM_SDS_CR_ENS_TSS_1 (1 << 6) -#define INCA_IP_IOM_SDS_CR_ENS_TSS_3 (1 << 5) -#define INCA_IP_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Control Register IOM Data***/ -#define INCA_IP_IOM_IOM_CR ((volatile u32*)(INCA_IP_IOM+ 0x015C)) -#define INCA_IP_IOM_IOM_CR_SPU (1 << 7) -#define INCA_IP_IOM_IOM_CR_CI_CS (1 << 5) -#define INCA_IP_IOM_IOM_CR_TIC_DIS (1 << 4) -#define INCA_IP_IOM_IOM_CR_EN_BCL (1 << 3) -#define INCA_IP_IOM_IOM_CR_CLKM (1 << 2) -#define INCA_IP_IOM_IOM_CR_Res (1 << 1) -#define INCA_IP_IOM_IOM_CR_DIS_IOM (1 << 0) - -/***Synchronous Transfer Interrupt***/ -#define INCA_IP_IOM_STI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) -#define INCA_IP_IOM_STI_STOV21 (1 << 7) -#define INCA_IP_IOM_STI_STOV20 (1 << 6) -#define INCA_IP_IOM_STI_STOV11 (1 << 5) -#define INCA_IP_IOM_STI_STOV10 (1 << 4) -#define INCA_IP_IOM_STI_STI21 (1 << 3) -#define INCA_IP_IOM_STI_STI20 (1 << 2) -#define INCA_IP_IOM_STI_STI11 (1 << 1) -#define INCA_IP_IOM_STI_STI10 (1 << 0) - -/***Acknowledge Synchronous Transfer Interrupt***/ -#define INCA_IP_IOM_ASTI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) -#define INCA_IP_IOM_ASTI_ACK21 (1 << 3) -#define INCA_IP_IOM_ASTI_ACK20 (1 << 2) -#define INCA_IP_IOM_ASTI_ACK11 (1 << 1) -#define INCA_IP_IOM_ASTI_ACK10 (1 << 0) - -/***Mask Synchronous Transfer Interrupt***/ -#define INCA_IP_IOM_MSTI ((volatile u32*)(INCA_IP_IOM+ 0x0164)) -#define INCA_IP_IOM_MSTI_STOV21 (1 << 7) -#define INCA_IP_IOM_MSTI_STOV20 (1 << 6) -#define INCA_IP_IOM_MSTI_STOV11 (1 << 5) -#define INCA_IP_IOM_MSTI_STOV10 (1 << 4) -#define INCA_IP_IOM_MSTI_STI21 (1 << 3) -#define INCA_IP_IOM_MSTI_STI20 (1 << 2) -#define INCA_IP_IOM_MSTI_STI11 (1 << 1) -#define INCA_IP_IOM_MSTI_STI10 (1 << 0) - -/***Configuration Register for Serial Data Strobes***/ -#define INCA_IP_IOM_SDS_CONF ((volatile u32*)(INCA_IP_IOM+ 0x0168)) -#define INCA_IP_IOM_SDS_CONF_SDS_BCL (1 << 0) - -/***Monitoring CDA Bits***/ -#define INCA_IP_IOM_MCDA ((volatile u32*)(INCA_IP_IOM+ 0x016C)) -#define INCA_IP_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : ASC register address and bits */ -/***********************************************************************/ - -#define INCA_IP_ASC (0xB8000400) -/***********************************************************************/ - - -/***ASC Port Input Select Register***/ -#define INCA_IP_ASC_ASC_PISEL ((volatile u32*)(INCA_IP_ASC+ 0x0004)) -#define INCA_IP_ASC_ASC_PISEL_RIS (1 << 0) - -/***ASC Control Register***/ -#define INCA_IP_ASC_ASC_CON ((volatile u32*)(INCA_IP_ASC+ 0x0010)) -#define INCA_IP_ASC_ASC_CON_R (1 << 15) -#define INCA_IP_ASC_ASC_CON_LB (1 << 14) -#define INCA_IP_ASC_ASC_CON_BRS (1 << 13) -#define INCA_IP_ASC_ASC_CON_ODD (1 << 12) -#define INCA_IP_ASC_ASC_CON_FDE (1 << 11) -#define INCA_IP_ASC_ASC_CON_OE (1 << 10) -#define INCA_IP_ASC_ASC_CON_FE (1 << 9) -#define INCA_IP_ASC_ASC_CON_PE (1 << 8) -#define INCA_IP_ASC_ASC_CON_OEN (1 << 7) -#define INCA_IP_ASC_ASC_CON_FEN (1 << 6) -#define INCA_IP_ASC_ASC_CON_PENRXDI (1 << 5) -#define INCA_IP_ASC_ASC_CON_REN (1 << 4) -#define INCA_IP_ASC_ASC_CON_STP (1 << 3) -#define INCA_IP_ASC_ASC_CON_M (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***ASC Write Hardware Modified Control Register***/ -#define INCA_IP_ASC_ASC_WHBCON ((volatile u32*)(INCA_IP_ASC+ 0x0050)) -#define INCA_IP_ASC_ASC_WHBCON_SETOE (1 << 13) -#define INCA_IP_ASC_ASC_WHBCON_SETFE (1 << 12) -#define INCA_IP_ASC_ASC_WHBCON_SETPE (1 << 11) -#define INCA_IP_ASC_ASC_WHBCON_CLROE (1 << 10) -#define INCA_IP_ASC_ASC_WHBCON_CLRFE (1 << 9) -#define INCA_IP_ASC_ASC_WHBCON_CLRPE (1 << 8) -#define INCA_IP_ASC_ASC_WHBCON_SETREN (1 << 5) -#define INCA_IP_ASC_ASC_WHBCON_CLRREN (1 << 4) - -/***ASC Baudrate Timer/Reload Register***/ -#define INCA_IP_ASC_ASC_BTR ((volatile u32*)(INCA_IP_ASC+ 0x0014)) -#define INCA_IP_ASC_ASC_BTR_BR_VALUE (value) (((( 1 << 13) - 1) & (value)) << 0) - -/***ASC Fractional Divider Register***/ -#define INCA_IP_ASC_ASC_FDV ((volatile u32*)(INCA_IP_ASC+ 0x0018)) -#define INCA_IP_ASC_ASC_FDV_FD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC IrDA Pulse Mode/Width Register***/ -#define INCA_IP_ASC_ASC_PMW ((volatile u32*)(INCA_IP_ASC+ 0x001C)) -#define INCA_IP_ASC_ASC_PMW_IRPW (1 << 8) -#define INCA_IP_ASC_ASC_PMW_PW_VALUE (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***ASC Transmit Buffer Register***/ -#define INCA_IP_ASC_ASC_TBUF ((volatile u32*)(INCA_IP_ASC+ 0x0020)) -#define INCA_IP_ASC_ASC_TBUF_TD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Receive Buffer Register***/ -#define INCA_IP_ASC_ASC_RBUF ((volatile u32*)(INCA_IP_ASC+ 0x0024)) -#define INCA_IP_ASC_ASC_RBUF_RD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Autobaud Control Register***/ -#define INCA_IP_ASC_ASC_ABCON ((volatile u32*)(INCA_IP_ASC+ 0x0030)) -#define INCA_IP_ASC_ASC_ABCON_RXINV (1 << 11) -#define INCA_IP_ASC_ASC_ABCON_TXINV (1 << 10) -#define INCA_IP_ASC_ASC_ABCON_ABEM (value) (((( 1 << 2) - 1) & (value)) << 8) -#define INCA_IP_ASC_ASC_ABCON_FCDETEN (1 << 4) -#define INCA_IP_ASC_ASC_ABCON_ABDETEN (1 << 3) -#define INCA_IP_ASC_ASC_ABCON_ABSTEN (1 << 2) -#define INCA_IP_ASC_ASC_ABCON_AUREN (1 << 1) -#define INCA_IP_ASC_ASC_ABCON_ABEN (1 << 0) - -/***Receive FIFO Control Register***/ -#define INCA_IP_ASC_RXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0040)) -#define INCA_IP_ASC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_ASC_RXFCON_RXTMEN (1 << 2) -#define INCA_IP_ASC_RXFCON_RXFFLU (1 << 1) -#define INCA_IP_ASC_RXFCON_RXFEN (1 << 0) - -/***Transmit FIFO Control Register***/ -#define INCA_IP_ASC_TXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0044)) -#define INCA_IP_ASC_TXFCON_TXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_ASC_TXFCON_TXTMEN (1 << 2) -#define INCA_IP_ASC_TXFCON_TXFFLU (1 << 1) -#define INCA_IP_ASC_TXFCON_TXFEN (1 << 0) - -/***FIFO Status Register***/ -#define INCA_IP_ASC_FSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0048)) -#define INCA_IP_ASC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_ASC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***ASC Write HW Modified Autobaud Control Register***/ -#define INCA_IP_ASC_ASC_WHBABCON ((volatile u32*)(INCA_IP_ASC+ 0x0054)) -#define INCA_IP_ASC_ASC_WHBABCON_SETABEN (1 << 1) -#define INCA_IP_ASC_ASC_WHBABCON_CLRABEN (1 << 0) - -/***ASC Autobaud Status Register***/ -#define INCA_IP_ASC_ASC_ABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0034)) -#define INCA_IP_ASC_ASC_ABSTAT_DETWAIT (1 << 4) -#define INCA_IP_ASC_ASC_ABSTAT_SCCDET (1 << 3) -#define INCA_IP_ASC_ASC_ABSTAT_SCSDET (1 << 2) -#define INCA_IP_ASC_ASC_ABSTAT_FCCDET (1 << 1) -#define INCA_IP_ASC_ASC_ABSTAT_FCSDET (1 << 0) - -/***ASC Write HW Modified Autobaud Status Register***/ -#define INCA_IP_ASC_ASC_WHBABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0058)) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETDETWAIT (1 << 9) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRDETWAIT (1 << 8) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCCDET (1 << 7) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCCDET (1 << 6) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCSDET (1 << 5) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCSDET (1 << 4) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCCDET (1 << 3) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCCDET (1 << 2) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCSDET (1 << 1) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCSDET (1 << 0) - -/***ASC Clock Control Register***/ -#define INCA_IP_ASC_ASC_CLC ((volatile u32*)(INCA_IP_ASC+ 0x0000)) -#define INCA_IP_ASC_ASC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_ASC_ASC_CLC_DISS (1 << 1) -#define INCA_IP_ASC_ASC_CLC_DISR (1 << 0) - -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ - -#define INCA_IP_DMA (0xBF108000) -/***********************************************************************/ - - -/***DMA RX Channel 0 Command Register***/ -#define INCA_IP_DMA_DMA_RXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0800)) -#define INCA_IP_DMA_DMA_RXCCR0_LBE (1 << 31) -#define INCA_IP_DMA_DMA_RXCCR0_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_RXCCR0_INIT (1 << 2) -#define INCA_IP_DMA_DMA_RXCCR0_OFF (1 << 1) -#define INCA_IP_DMA_DMA_RXCCR0_HR (1 << 0) - -/***DMA RX Channel 1 Command Register***/ -#define INCA_IP_DMA_DMA_RXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0804)) -#define INCA_IP_DMA_DMA_RXCCR1_LBE (1 << 31) -#define INCA_IP_DMA_DMA_RXCCR1_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_RXCCR1_INIT (1 << 2) -#define INCA_IP_DMA_DMA_RXCCR1_OFF (1 << 1) -#define INCA_IP_DMA_DMA_RXCCR1_HR (1 << 0) - -/***DMA Receive Interrupt Status Register***/ -#define INCA_IP_DMA_DMA_RXISR ((volatile u32*)(INCA_IP_DMA+ 0x0808)) -#define INCA_IP_DMA_DMA_RXISR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) -#define INCA_IP_DMA_DMA_RXISR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_RXISR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_DMA_DMA_RXISR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_DMA_DMA_RXISR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA Receive Interrupt Mask Register***/ -#define INCA_IP_DMA_DMA_RXIMR ((volatile u32*)(INCA_IP_DMA+ 0x080C)) -#define INCA_IP_DMA_DMA_RXIMR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) -#define INCA_IP_DMA_DMA_RXIMR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_RXIMR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_DMA_DMA_RXIMR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_DMA_DMA_RXIMR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Rx Channel 0 -***/ -#define INCA_IP_DMA_DMA_RXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x0810)) -#define INCA_IP_DMA_DMA_RXFRDA0_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Rx Channel 1 -***/ -#define INCA_IP_DMA_DMA_RXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x0814)) -#define INCA_IP_DMA_DMA_RXFRDA1_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA Receive Channel Polling Time***/ -#define INCA_IP_DMA_DMA_RXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x0818)) -#define INCA_IP_DMA_DMA_RXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 30) -#define INCA_IP_DMA_DMA_RXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 28) -#define INCA_IP_DMA_DMA_RXPOLL_RXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***DMA TX Channel 0 Command Register (Voice Port)***/ -#define INCA_IP_DMA_DMA_TXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0880)) -#define INCA_IP_DMA_DMA_TXCCR0_LBE (1 << 31) -#define INCA_IP_DMA_DMA_TXCCR0_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_TXCCR0_HR (1 << 2) -#define INCA_IP_DMA_DMA_TXCCR0_OFF (1 << 1) -#define INCA_IP_DMA_DMA_TXCCR0_INIT (1 << 0) - -/***DMA TX Channel 1 Command Register (Mangmt Port)***/ -#define INCA_IP_DMA_DMA_TXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0884)) -#define INCA_IP_DMA_DMA_TXCCR1_LBE (1 << 31) -#define INCA_IP_DMA_DMA_TXCCR1_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_TXCCR1_HR (1 << 2) -#define INCA_IP_DMA_DMA_TXCCR1_OFF (1 << 1) -#define INCA_IP_DMA_DMA_TXCCR1_INIT (1 << 0) - -/***DMA TX Channel 2 Command Register (SSC Port)***/ -#define INCA_IP_DMA_DMA_TXCCR2 ((volatile u32*)(INCA_IP_DMA+ 0x0888)) -#define INCA_IP_DMA_DMA_TXCCR2_LBE (1 << 31) -#define INCA_IP_DMA_DMA_TXCCR2_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_TXCCR2_HBF (1 << 29) -#define INCA_IP_DMA_DMA_TXCCR2_HR (1 << 2) -#define INCA_IP_DMA_DMA_TXCCR2_OFF (1 << 1) -#define INCA_IP_DMA_DMA_TXCCR2_INIT (1 << 0) - -/***DMA First Receive Descriptor Addr. for Tx Channel 0 -***/ -#define INCA_IP_DMA_DMA_TXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x08A0)) -#define INCA_IP_DMA_DMA_TXFRDA0_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Tx Channel 1 -***/ -#define INCA_IP_DMA_DMA_TXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x08A4)) -#define INCA_IP_DMA_DMA_TXFRDA1_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Tx Channel 2 -***/ -#define INCA_IP_DMA_DMA_TXFRDA2 ((volatile u32*)(INCA_IP_DMA+ 0x08A8)) -#define INCA_IP_DMA_DMA_TXFRDA2_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA Transmit Channel Arbitration Register***/ -#define INCA_IP_DMA_DMA_TXWGT ((volatile u32*)(INCA_IP_DMA+ 0x08C0)) -#define INCA_IP_DMA_DMA_TXWGT_TX2PR (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_DMA_DMA_TXWGT_TX1PRI (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_DMA_DMA_TXWGT_TX0PRI (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA Transmit Channel Polling Time***/ -#define INCA_IP_DMA_DMA_TXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x08C4)) -#define INCA_IP_DMA_DMA_TXPOLL_BSZ2 (value) (((( 1 << 2) - 1) & (value)) << 30) -#define INCA_IP_DMA_DMA_TXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 28) -#define INCA_IP_DMA_DMA_TXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP_DMA_DMA_TXPOLL_TXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***DMA Transmit Interrupt Status Register***/ -#define INCA_IP_DMA_DMA_TXISR ((volatile u32*)(INCA_IP_DMA+ 0x08C8)) -#define INCA_IP_DMA_DMA_TXISR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_DMA_DMA_TXISR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) -#define INCA_IP_DMA_DMA_TXISR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_TXISR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_DMA_DMA_TXISR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***DMA Transmit Interrupt Mask Register***/ -#define INCA_IP_DMA_DMA_TXIMR ((volatile u32*)(INCA_IP_DMA+ 0x08CC)) -#define INCA_IP_DMA_DMA_TXIMR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_DMA_DMA_TXIMR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) -#define INCA_IP_DMA_DMA_TXIMR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_TXIMR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_DMA_DMA_TXIMR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : Debug register address and bits */ -/***********************************************************************/ - -#define INCA_IP_Debug (0xBF106000) -/***********************************************************************/ - - -/***MCD Break Bus Switch Register***/ -#define INCA_IP_Debug_MCD_BBS ((volatile u32*)(INCA_IP_Debug+ 0x0000)) -#define INCA_IP_Debug_MCD_BBS_BTP1 (1 << 19) -#define INCA_IP_Debug_MCD_BBS_BTP0 (1 << 18) -#define INCA_IP_Debug_MCD_BBS_BSP1 (1 << 17) -#define INCA_IP_Debug_MCD_BBS_BSP0 (1 << 16) -#define INCA_IP_Debug_MCD_BBS_BT5EN (1 << 15) -#define INCA_IP_Debug_MCD_BBS_BT4EN (1 << 14) -#define INCA_IP_Debug_MCD_BBS_BT5 (1 << 13) -#define INCA_IP_Debug_MCD_BBS_BT4 (1 << 12) -#define INCA_IP_Debug_MCD_BBS_BS5EN (1 << 7) -#define INCA_IP_Debug_MCD_BBS_BS4EN (1 << 6) -#define INCA_IP_Debug_MCD_BBS_BS5 (1 << 5) -#define INCA_IP_Debug_MCD_BBS_BS4 (1 << 4) - -/***MCD Multiplexer Control Register***/ -#define INCA_IP_Debug_MCD_MCR ((volatile u32*)(INCA_IP_Debug+ 0x0008)) -#define INCA_IP_Debug_MCD_MCR_MUX5 (1 << 4) -#define INCA_IP_Debug_MCD_MCR_MUX4 (1 << 3) -#define INCA_IP_Debug_MCD_MCR_MUX1 (1 << 0) - -/***********************************************************************/ -/* Module : TSF register address and bits */ -/***********************************************************************/ - -#define INCA_IP_TSF (0xB8000900) -/***********************************************************************/ - - -/***TSF Configuration Register (0000H)***/ -#define INCA_IP_TSF_TSF_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0000)) -#define INCA_IP_TSF_TSF_CONF_PWMEN (1 << 2) -#define INCA_IP_TSF_TSF_CONF_LEDEN (1 << 1) -#define INCA_IP_TSF_TSF_CONF_KEYEN (1 << 0) - -/***Key scan Configuration Register (0004H)***/ -#define INCA_IP_TSF_KEY_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0004)) -#define INCA_IP_TSF_KEY_CONF_SL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Scan Register Line 0 and 1 (0008H)***/ -#define INCA_IP_TSF_SREG01 ((volatile u32*)(INCA_IP_TSF+ 0x0008)) -#define INCA_IP_TSF_SREG01_RES1x (value) (((( 1 << 12) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG01_RES0x (value) (((( 1 << 13) - 1) & (value)) << 0) - -/***Scan Register Line 2 and 3 (000CH)***/ -#define INCA_IP_TSF_SREG23 ((volatile u32*)(INCA_IP_TSF+ 0x000C)) -#define INCA_IP_TSF_SREG23_RES3x (value) (((( 1 << 10) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG23_RES2x (value) (((( 1 << 11) - 1) & (value)) << 0) - -/***Scan Register Line 4, 5 and 6 (0010H)***/ -#define INCA_IP_TSF_SREG456 ((volatile u32*)(INCA_IP_TSF+ 0x0010)) -#define INCA_IP_TSF_SREG456_RES6x (value) (((( 1 << 7) - 1) & (value)) << 24) -#define INCA_IP_TSF_SREG456_RES5x (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG456_RES4x (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***Scan Register Line 7 to 12 (0014H)***/ -#define INCA_IP_TSF_SREG7to12 ((volatile u32*)(INCA_IP_TSF+ 0x0014)) -#define INCA_IP_TSF_SREG7to12_RES12x (1 << 28) -#define INCA_IP_TSF_SREG7to12_RES11x (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_TSF_SREG7to12_RES10x (value) (((( 1 << 3) - 1) & (value)) << 20) -#define INCA_IP_TSF_SREG7to12_RES9x (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG7to12_RES8x (value) (((( 1 << 5) - 1) & (value)) << 8) -#define INCA_IP_TSF_SREG7to12_RES7x (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***LEDMUX Configuration Register (0018H)***/ -#define INCA_IP_TSF_LEDMUX_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0018)) -#define INCA_IP_TSF_LEDMUX_CONF_ETL1 (1 << 25) -#define INCA_IP_TSF_LEDMUX_CONF_ESTA1 (1 << 24) -#define INCA_IP_TSF_LEDMUX_CONF_EDPX1 (1 << 23) -#define INCA_IP_TSF_LEDMUX_CONF_EACT1 (1 << 22) -#define INCA_IP_TSF_LEDMUX_CONF_ESPD1 (1 << 21) -#define INCA_IP_TSF_LEDMUX_CONF_ETL0 (1 << 20) -#define INCA_IP_TSF_LEDMUX_CONF_ESTA0 (1 << 19) -#define INCA_IP_TSF_LEDMUX_CONF_EDPX0 (1 << 18) -#define INCA_IP_TSF_LEDMUX_CONF_EACT0 (1 << 17) -#define INCA_IP_TSF_LEDMUX_CONF_ESPD0 (1 << 16) -#define INCA_IP_TSF_LEDMUX_CONF_INV (1 << 1) -#define INCA_IP_TSF_LEDMUX_CONF_NCOL (1 << 0) - -/***LED Register (001CH)***/ -#define INCA_IP_TSF_LED_REG ((volatile u32*)(INCA_IP_TSF+ 0x001C)) -#define INCA_IP_TSF_LED_REG_Lxy (value) (((( 1 << 24) - 1) & (value)) << 0) - -/***Pulse Width Modulator 1 and 2 Register (0020H)***/ -#define INCA_IP_TSF_PWM12 ((volatile u32*)(INCA_IP_TSF+ 0x0020)) -#define INCA_IP_TSF_PWM12_PW2PW1 (value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***********************************************************************/ -/* Module : Ports register address and bits */ -/***********************************************************************/ - -#define INCA_IP_Ports (0xB8000A00) -/***********************************************************************/ - - -/***Port 1 Data Output Register (0020H)***/ -#define INCA_IP_Ports_P1_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0020)) -#define INCA_IP_Ports_P1_OUT_P(value) (1 << value) - - -/***Port 2 Data Output Register (0040H)***/ -#define INCA_IP_Ports_P2_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0040)) -#define INCA_IP_Ports_P2_OUT_P(value) (1 << value) - - -/***Port 1 Data Input Register (0024H)***/ -#define INCA_IP_Ports_P1_IN ((volatile u32*)(INCA_IP_Ports+ 0x0024)) -#define INCA_IP_Ports_P1_IN_P(value) (1 << value) - - -/***Port 2 Data Input Register (0044H)***/ -#define INCA_IP_Ports_P2_IN ((volatile u32*)(INCA_IP_Ports+ 0x0044)) -#define INCA_IP_Ports_P2_IN_P(value) (1 << value) - - -/***Port 1 Direction Register (0028H)***/ -#define INCA_IP_Ports_P1_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0028)) -#define INCA_IP_Ports_P1_DIR_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P1_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Port 2 Direction Register (0048H)***/ -#define INCA_IP_Ports_P2_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0048)) -#define INCA_IP_Ports_P2_DIR_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P2_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Port 0 Alternate Function Select Register 0 (000C H) -***/ -#define INCA_IP_Ports_P0_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x000C)) -#define INCA_IP_Ports_P0_ALTSEL_Port0P(value) (1 << value) - - -/***Port 1 Alternate Function Select Register 0 (002C H) -***/ -#define INCA_IP_Ports_P1_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x002C)) -#define INCA_IP_Ports_P1_ALTSEL_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P1_ALTSEL_Port2P(value) (1 << value) - - -/***Port 2 Alternate Function Select Register 0 (004C H) -***/ -#define INCA_IP_Ports_P2_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x004C)) -#define INCA_IP_Ports_P2_ALTSEL_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P2_ALTSEL_Port2P(value) (1 << value) - - -/***Port 0 Input Schmitt-Trigger Off Register (0010 H) -***/ -#define INCA_IP_Ports_P0_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0010)) -#define INCA_IP_Ports_P0_STOFF_Port0P(value) (1 << value) - - -/***Port 1 Input Schmitt-Trigger Off Register (0030 H) -***/ -#define INCA_IP_Ports_P1_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0030)) -#define INCA_IP_Ports_P1_STOFF_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P1_STOFF_Port2P(value) (1 << value) - - -/***Port 2 Input Schmitt-Trigger Off Register (0050 H) -***/ -#define INCA_IP_Ports_P2_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0050)) -#define INCA_IP_Ports_P2_STOFF_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P2_STOFF_Port2P(value) (1 << value) - - -/***Port 2 Open Drain Control Register (0054H)***/ -#define INCA_IP_Ports_P2_OD ((volatile u32*)(INCA_IP_Ports+ 0x0054)) -#define INCA_IP_Ports_P2_OD_Port2P(value) (1 << value) - - -/***Port 0 Pull Up Device Enable Register (0018 H)***/ -#define INCA_IP_Ports_P0_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0018)) -#define INCA_IP_Ports_P0_PUDEN_Port0P(value) (1 << value) - - -/***Port 2 Pull Up Device Enable Register (0058 H)***/ -#define INCA_IP_Ports_P2_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0058)) -#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) - -#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) - - -/***Port 0 Pull Up/Pull Down Select Register (001C H)***/ -#define INCA_IP_Ports_P0_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x001C)) -#define INCA_IP_Ports_P0_PUDSEL_Port0P(value) (1 << value) - - -/***Port 2 Pull Up/Pull Down Select Register (005C H)***/ -#define INCA_IP_Ports_P2_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x005C)) -#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) - -#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) - - -/***********************************************************************/ -/* Module : DES/3DES register address and bits */ -/***********************************************************************/ - -#define INCA_IP_DES_3DES (0xB8000800) -/***********************************************************************/ - - -/***DES Input Data High Register***/ -#define INCA_IP_DES_3DES_DES_IHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0000)) -#define INCA_IP_DES_3DES_DES_IHR_IH(value) (1 << value) - - -/***DES Input Data Low Register***/ -#define INCA_IP_DES_3DES_DES_ILR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0004)) -#define INCA_IP_DES_3DES_DES_ILR_IL(value) (1 << value) - - -/***DES Key #1 High Register***/ -#define INCA_IP_DES_3DES_DES_K1HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0008)) -#define INCA_IP_DES_3DES_DES_K1HR_K1H(value) (1 << value) - - -/***DES Key #1 Low Register***/ -#define INCA_IP_DES_3DES_DES_K1LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x000C)) -#define INCA_IP_DES_3DES_DES_K1LR_K1L(value) (1 << value) - - -/***DES Key #2 High Register***/ -#define INCA_IP_DES_3DES_DES_K2HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0010)) -#define INCA_IP_DES_3DES_DES_K2HR_K2H(value) (1 << value) - - -/***DES Key #2 Low Register***/ -#define INCA_IP_DES_3DES_DES_K2LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0014)) -#define INCA_IP_DES_3DES_DES_K2LR_K2L(value) (1 << value) - - -/***DES Key #3 High Register***/ -#define INCA_IP_DES_3DES_DES_K3HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0018)) -#define INCA_IP_DES_3DES_DES_K3HR_K3H(value) (1 << value) - - -/***DES Key #3 Low Register***/ -#define INCA_IP_DES_3DES_DES_K3LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x001C)) -#define INCA_IP_DES_3DES_DES_K3LR_K3L(value) (1 << value) - - -/***DES Initialization Vector High Register***/ -#define INCA_IP_DES_3DES_DES_IVHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0020)) -#define INCA_IP_DES_3DES_DES_IVHR_IVH(value) (1 << value) - - -/***DES Initialization Vector Low Register***/ -#define INCA_IP_DES_3DES_DES_IVLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0024)) -#define INCA_IP_DES_3DES_DES_IVLR_IVL(value) (1 << value) - - -/***DES Control Register***/ -#define INCA_IP_DES_3DES_DES_CONTROLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0028)) -#define INCA_IP_DES_3DES_DES_CONTROLR_KRE (1 << 31) -#define INCA_IP_DES_3DES_DES_CONTROLR_DAU (1 << 16) -#define INCA_IP_DES_3DES_DES_CONTROLR_F(value) (1 << value) - -#define INCA_IP_DES_3DES_DES_CONTROLR_O(value) (1 << value) - -#define INCA_IP_DES_3DES_DES_CONTROLR_GO (1 << 8) -#define INCA_IP_DES_3DES_DES_CONTROLR_STP (1 << 7) -#define INCA_IP_DES_3DES_DES_CONTROLR_IEN (1 << 6) -#define INCA_IP_DES_3DES_DES_CONTROLR_BUS (1 << 5) -#define INCA_IP_DES_3DES_DES_CONTROLR_SM (1 << 4) -#define INCA_IP_DES_3DES_DES_CONTROLR_E_D (1 << 3) -#define INCA_IP_DES_3DES_DES_CONTROLR_M(value) (1 << value) - - -/***DES Output Data High Register***/ -#define INCA_IP_DES_3DES_DES_OHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x002C)) -#define INCA_IP_DES_3DES_DES_OHR_OH(value) (1 << value) - - -/***DES Output Data Low Register***/ -#define INCA_IP_DES_3DES_DES_OLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0030)) -#define INCA_IP_DES_3DES_DES_OLR_OL(value) (1 << value) - - -/***********************************************************************/ -/* Module : AES register address and bits */ -/***********************************************************************/ - -#define INCA_IP_AES (0xB8000880) -/***********************************************************************/ - - -/***AES Input Data 3 Register***/ -#define INCA_IP_AES_AES_ID3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID3R_I(value) (1 << value) - - -/***AES Input Data 2 Register***/ -#define INCA_IP_AES_AES_ID2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID2R_I(value) (1 << value) - - -/***AES Input Data 1 Register***/ -#define INCA_IP_AES_AES_ID1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID1R_I(value) (1 << value) - - -/***AES Input Data 0 Register***/ -#define INCA_IP_AES_AES_ID0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID0R_I(value) (1 << value) - - -/***AES Output Data 3 Register***/ -#define INCA_IP_AES_AES_OD3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD3R_O(value) (1 << value) - - -/***AES Output Data 2 Register***/ -#define INCA_IP_AES_AES_OD2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD2R_O(value) (1 << value) - - -/***AES Output Data 1 Register***/ -#define INCA_IP_AES_AES_OD1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD1R_O(value) (1 << value) - - -/***AES Output Data 0 Register***/ -#define INCA_IP_AES_AES_OD0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD0R_O(value) (1 << value) - - -/***AES Key 7 Register***/ -#define INCA_IP_AES_AES_K7R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K7R_K(value) (1 << value) - - -/***AES Key 6 Register***/ -#define INCA_IP_AES_AES_K6R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K6R_K(value) (1 << value) - - -/***AES Key 5 Register***/ -#define INCA_IP_AES_AES_K5R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K5R_K(value) (1 << value) - - -/***AES Key 4 Register***/ -#define INCA_IP_AES_AES_K4R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K4R_K(value) (1 << value) - - -/***AES Key 3 Register***/ -#define INCA_IP_AES_AES_K3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K3R_K(value) (1 << value) - - -/***AES Key 2 Register***/ -#define INCA_IP_AES_AES_K2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K2R_K(value) (1 << value) - - -/***AES Key 1 Register***/ -#define INCA_IP_AES_AES_K1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K1R_K(value) (1 << value) - - -/***AES Key 0 Register***/ -#define INCA_IP_AES_AES_K0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K0R_K(value) (1 << value) - - -/***AES Initialization Vector 3 Register***/ -#define INCA_IP_AES_AES_IV3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV3R_IV(value) (1 << value) - - -/***AES Initialization Vector 2 Register***/ -#define INCA_IP_AES_AES_IV2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV2R_IV(value) (1 << value) - - -/***AES Initialization Vector 1 Register***/ -#define INCA_IP_AES_AES_IV1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV1R_IV(value) (1 << value) - - -/***AES Initialization Vector 0 Register***/ -#define INCA_IP_AES_AES_IV0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV0R_IV (value) (((( 1 << 32) - 1) &(value)) << 0) - -/***AES Control Register***/ -#define INCA_IP_AES_AES_CONTROLR ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_CONTROLR_KRE (1 << 31) -#define INCA_IP_AES_AES_CONTROLR_DAU (1 << 16) -#define INCA_IP_AES_AES_CONTROLR_PNK (1 << 15) -#define INCA_IP_AES_AES_CONTROLR_F(value) (1 << value) - -#define INCA_IP_AES_AES_CONTROLR_O(value) (1 << value) - -#define INCA_IP_AES_AES_CONTROLR_GO (1 << 8) -#define INCA_IP_AES_AES_CONTROLR_STP (1 << 7) -#define INCA_IP_AES_AES_CONTROLR_IEN (1 << 6) -#define INCA_IP_AES_AES_CONTROLR_BUS (1 << 5) -#define INCA_IP_AES_AES_CONTROLR_SM (1 << 4) -#define INCA_IP_AES_AES_CONTROLR_E_D (1 << 3) -#define INCA_IP_AES_AES_CONTROLR_KV (1 << 2) -#define INCA_IP_AES_AES_CONTROLR_K(value) (1 << value) - - -/***********************************************************************/ -/* Module : I²C register address and bits */ -/***********************************************************************/ - -#define INCA_IP_IIC (0xB8000700) -/***********************************************************************/ - - -/***I²C Port Input Select Register***/ -#define INCA_IP_IIC_IIC_PISEL ((volatile u32*)(INCA_IP_IIC+ 0x0004)) -#define INCA_IP_IIC_IIC_PISEL_SDAIS(value) (1 << value) - -#define INCA_IP_IIC_IIC_PISEL_SCLIS(value) (1 << value) - - -/***I²C Clock Control Register***/ -#define INCA_IP_IIC_IIC_CLC ((volatile u32*)(INCA_IP_IIC+ 0x0000)) -#define INCA_IP_IIC_IIC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_CLC_DISS (1 << 1) -#define INCA_IP_IIC_IIC_CLC_DISR (1 << 0) - -/***I²C System Control Register***/ -#define INCA_IP_IIC_IIC_SYSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) -#define INCA_IP_IIC_IIC_SYSCON_0_WMEN (1 << 31) -#define INCA_IP_IIC_IIC_SYSCON_0_CI (value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP_IIC_IIC_SYSCON_0_STP (1 << 25) -#define INCA_IP_IIC_IIC_SYSCON_0_IGE (1 << 24) -#define INCA_IP_IIC_IIC_SYSCON_0_TRX (1 << 23) -#define INCA_IP_IIC_IIC_SYSCON_0_INT (1 << 22) -#define INCA_IP_IIC_IIC_SYSCON_0_ACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_SYSCON_0_BUM (1 << 20) -#define INCA_IP_IIC_IIC_SYSCON_0_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) -#define INCA_IP_IIC_IIC_SYSCON_0_RSC (1 << 17) -#define INCA_IP_IIC_IIC_SYSCON_0_M10 (1 << 16) -#define INCA_IP_IIC_IIC_SYSCON_0_RMEN (1 << 15) -#define INCA_IP_IIC_IIC_SYSCON_0_CO (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_SYSCON_0_IRQE (1 << 7) -#define INCA_IP_IIC_IIC_SYSCON_0_IRQP (1 << 6) -#define INCA_IP_IIC_IIC_SYSCON_0_IRQD (1 << 5) -#define INCA_IP_IIC_IIC_SYSCON_0_BB (1 << 4) -#define INCA_IP_IIC_IIC_SYSCON_0_LRB (1 << 3) -#define INCA_IP_IIC_IIC_SYSCON_0_SLA (1 << 2) -#define INCA_IP_IIC_IIC_SYSCON_0_AL (1 << 1) -#define INCA_IP_IIC_IIC_SYSCON_0_ADR (1 << 0) - -/***I²C System Control Register***/ -#define INCA_IP_IIC_IIC_SYSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) -#define INCA_IP_IIC_IIC_SYSCON_1_RM (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_IIC_IIC_SYSCON_1_TRX (1 << 23) -#define INCA_IP_IIC_IIC_SYSCON_1_INT (1 << 22) -#define INCA_IP_IIC_IIC_SYSCON_1_ACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_SYSCON_1_BUM (1 << 20) -#define INCA_IP_IIC_IIC_SYSCON_1_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) -#define INCA_IP_IIC_IIC_SYSCON_1_RSC (1 << 17) -#define INCA_IP_IIC_IIC_SYSCON_1_M10 (1 << 16) -#define INCA_IP_IIC_IIC_SYSCON_1_RMEN (1 << 15) -#define INCA_IP_IIC_IIC_SYSCON_1_CO (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_SYSCON_1_IRQE (1 << 7) -#define INCA_IP_IIC_IIC_SYSCON_1_IRQP (1 << 6) -#define INCA_IP_IIC_IIC_SYSCON_1_IRQD (1 << 5) -#define INCA_IP_IIC_IIC_SYSCON_1_BB (1 << 4) -#define INCA_IP_IIC_IIC_SYSCON_1_LRB (1 << 3) -#define INCA_IP_IIC_IIC_SYSCON_1_SLA (1 << 2) -#define INCA_IP_IIC_IIC_SYSCON_1_AL (1 << 1) -#define INCA_IP_IIC_IIC_SYSCON_1_ADR (1 << 0) - -/***I²C System Control Register***/ -#define INCA_IP_IIC_IIC_SYSCON_2 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) -#define INCA_IP_IIC_IIC_SYSCON_2_WMEN (1 << 31) -#define INCA_IP_IIC_IIC_SYSCON_2_CI (value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP_IIC_IIC_SYSCON_2_STP (1 << 25) -#define INCA_IP_IIC_IIC_SYSCON_2_IGE (1 << 24) -#define INCA_IP_IIC_IIC_SYSCON_2_TRX (1 << 23) -#define INCA_IP_IIC_IIC_SYSCON_2_INT (1 << 22) -#define INCA_IP_IIC_IIC_SYSCON_2_ACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_SYSCON_2_BUM (1 << 20) -#define INCA_IP_IIC_IIC_SYSCON_2_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) -#define INCA_IP_IIC_IIC_SYSCON_2_RSC (1 << 17) -#define INCA_IP_IIC_IIC_SYSCON_2_M10 (1 << 16) -#define INCA_IP_IIC_IIC_SYSCON_2_WM (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_SYSCON_2_IRQE (1 << 7) -#define INCA_IP_IIC_IIC_SYSCON_2_IRQP (1 << 6) -#define INCA_IP_IIC_IIC_SYSCON_2_IRQD (1 << 5) -#define INCA_IP_IIC_IIC_SYSCON_2_BB (1 << 4) -#define INCA_IP_IIC_IIC_SYSCON_2_LRB (1 << 3) -#define INCA_IP_IIC_IIC_SYSCON_2_SLA (1 << 2) -#define INCA_IP_IIC_IIC_SYSCON_2_AL (1 << 1) -#define INCA_IP_IIC_IIC_SYSCON_2_ADR (1 << 0) - -/***I²C Write Hardware Modified System Control Register -***/ -#define INCA_IP_IIC_IIC_WHBSYSCON ((volatile u32*)(INCA_IP_IIC+ 0x0020)) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRWMEN (1 << 31) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETWMEN (1 << 30) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETSTP (1 << 26) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRSTP (1 << 25) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETTRX (1 << 24) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRTRX (1 << 23) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETACKDIS (1 << 22) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETBUM (1 << 20) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRBUM (1 << 19) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETRSC (1 << 17) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRSC (1 << 16) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETRMEN (1 << 15) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRMEN (1 << 14) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQE (1 << 10) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQP (1 << 9) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQD (1 << 8) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQE (1 << 7) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQP (1 << 6) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQD (1 << 5) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETAL (1 << 2) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRAL (1 << 1) - -/***I²C Bus Control Register***/ -#define INCA_IP_IIC_IIC_BUSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0014)) -#define INCA_IP_IIC_IIC_BUSCON_0_BRPMOD (1 << 31) -#define INCA_IP_IIC_IIC_BUSCON_0_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_IIC_IIC_BUSCON_0_ICA9_0 (value) (((( 1 << 10) - 1) & (value)) << 16) -#define INCA_IP_IIC_IIC_BUSCON_0_BRP (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_BUSCON_0_SCLEN(value) (1 << value) - -#define INCA_IP_IIC_IIC_BUSCON_0_SDAEN(value) (1 << value) - - -/***I²C Bus Control Register***/ -#define INCA_IP_IIC_IIC_BUSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0014)) -#define INCA_IP_IIC_IIC_BUSCON_1_BRPMOD (1 << 31) -#define INCA_IP_IIC_IIC_BUSCON_1_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_IIC_IIC_BUSCON_1_ICA7_1 (value) (((( 1 << 7) - 1) & (value)) << 17) -#define INCA_IP_IIC_IIC_BUSCON_1_BRP (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_BUSCON_1_SCLEN(value) (1 << value) - -#define INCA_IP_IIC_IIC_BUSCON_1_SDAEN(value) (1 << value) - - -/***I²C Receive Transmit Buffer***/ -#define INCA_IP_IIC_IIC_RTB ((volatile u32*)(INCA_IP_IIC+ 0x0018)) -#define INCA_IP_IIC_IIC_RTB_RTB(value) (1 << value) - - -/***********************************************************************/ -/* Module : FB register address and bits */ -/***********************************************************************/ - -#define INCA_IP_FB (0xBF880000) -/***********************************************************************/ - - -/***FB Access Error Cause Register***/ -#define INCA_IP_FB_FB_ERRCAUSE ((volatile u32*)(INCA_IP_FB+ 0x0100)) -#define INCA_IP_FB_FB_ERRCAUSE_ERR (1 << 31) -#define INCA_IP_FB_FB_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_FB_FB_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***FB Access Error Address Register***/ -#define INCA_IP_FB_FB_ERRADDR ((volatile u32*)(INCA_IP_FB+ 0x0108)) -#define INCA_IP_FB_FB_ERRADDR_ADDR - -/***FB Configuration Register***/ -#define INCA_IP_FB_FB_CFG ((volatile u32*)(INCA_IP_FB+ 0x0800)) -#define INCA_IP_FB_FB_CFG_SVM (1 << 0) - -/***********************************************************************/ -/* Module : SRAM register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SRAM (0xBF980000) -/***********************************************************************/ - - -/***SRAM Size Register***/ -#define INCA_IP_SRAM_SRAM_SIZE ((volatile u32*)(INCA_IP_SRAM+ 0x0800)) -#define INCA_IP_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : BIU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_BIU (0xBFA80000) -/***********************************************************************/ - - -/***BIU Identification Register***/ -#define INCA_IP_BIU_BIU_ID ((volatile u32*)(INCA_IP_BIU+ 0x0000)) -#define INCA_IP_BIU_BIU_ID_ARCH (1 << 16) -#define INCA_IP_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***BIU Access Error Cause Register***/ -#define INCA_IP_BIU_BIU_ERRCAUSE ((volatile u32*)(INCA_IP_BIU+ 0x0100)) -#define INCA_IP_BIU_BIU_ERRCAUSE_ERR (1 << 31) -#define INCA_IP_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***BIU Access Error Address Register***/ -#define INCA_IP_BIU_BIU_ERRADDR ((volatile u32*)(INCA_IP_BIU+ 0x0108)) -#define INCA_IP_BIU_BIU_ERRADDR_ADDR - -/***********************************************************************/ -/* Module : ICU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_ICU (0xBF101000) -/***********************************************************************/ - - -/***IM0 Interrupt Status Register***/ -#define INCA_IP_ICU_IM0_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0000)) -#define INCA_IP_ICU_IM0_ISR_IR(value) (1 << value) - - -/***IM1 Interrupt Status Register***/ -#define INCA_IP_ICU_IM1_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0200)) -#define INCA_IP_ICU_IM1_ISR_IR(value) (1 << value) - - -/***IM2 Interrupt Status Register***/ -#define INCA_IP_ICU_IM2_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0400)) -#define INCA_IP_ICU_IM2_ISR_IR(value) (1 << value) - - -/***IM0 Interrupt Enable Register***/ -#define INCA_IP_ICU_IM0_IER ((volatile u32*)(INCA_IP_ICU+ 0x0008)) -#define INCA_IP_ICU_IM0_IER_IR(value) (1 << value) - - -/***IM1 Interrupt Enable Register***/ -#define INCA_IP_ICU_IM1_IER ((volatile u32*)(INCA_IP_ICU+ 0x0208)) -#define INCA_IP_ICU_IM1_IER_IR(value) (1 << value) - - -/***IM2 Interrupt Enable Register***/ -#define INCA_IP_ICU_IM2_IER ((volatile u32*)(INCA_IP_ICU+ 0x0408)) -#define INCA_IP_ICU_IM2_IER_IR(value) (1 << value) - - -/***IM0 Interrupt Output Status Register***/ -#define INCA_IP_ICU_IM0_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0010)) -#define INCA_IP_ICU_IM0_IOSR_IR(value) (1 << value) - - -/***IM1 Interrupt Output Status Register***/ -#define INCA_IP_ICU_IM1_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0210)) -#define INCA_IP_ICU_IM1_IOSR_IR(value) (1 << value) - - -/***IM2 Interrupt Output Status Register***/ -#define INCA_IP_ICU_IM2_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0410)) -#define INCA_IP_ICU_IM2_IOSR_IR(value) (1 << value) - - -/***IM0 Interrupt Request Set Register***/ -#define INCA_IP_ICU_IM0_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0018)) -#define INCA_IP_ICU_IM0_IRSR_IR(value) (1 << value) - - -/***IM1 Interrupt Request Set Register***/ -#define INCA_IP_ICU_IM1_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0218)) -#define INCA_IP_ICU_IM1_IRSR_IR(value) (1 << value) - - -/***IM2 Interrupt Request Set Register***/ -#define INCA_IP_ICU_IM2_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0418)) -#define INCA_IP_ICU_IM2_IRSR_IR(value) (1 << value) - - -/***External Interrupt Control Register***/ -#define INCA_IP_ICU_ICU_EICR ((volatile u32*)(INCA_IP_ICU+ 0x0B00)) -#define INCA_IP_ICU_ICU_EICR_EII5 (value) (((( 1 << 3) - 1) & (value)) << 20) -#define INCA_IP_ICU_ICU_EICR_EII4 (value) (((( 1 << 3) - 1) & (value)) << 16) -#define INCA_IP_ICU_ICU_EICR_EII3 (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_ICU_ICU_EICR_EII2 (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_ICU_ICU_EICR_EII1 (value) (((( 1 << 3) - 1) & (value)) << 4) -#define INCA_IP_ICU_ICU_EICR_EII0 (value) (((( 1 << 3) - 1) & (value)) << 0) diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h index 9f3cce9a628..a5b2fc08f87 100644 --- a/arch/mips/include/asm/u-boot-mips.h +++ b/arch/mips/include/asm/u-boot-mips.h @@ -21,5 +21,3 @@ static inline unsigned long image_copy_end(void) extern char __image_copy_end[]; return (unsigned long) &__image_copy_end; } - -extern int incaip_set_cpuclk(void); diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index 317c8258de9..3200d87e30a 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -103,9 +103,6 @@ init_fnc_t *init_sequence[] = { board_early_init_f, timer_init, env_init, /* initialize environment */ -#ifdef CONFIG_INCA_IP - incaip_set_cpuclk, /* set cpu clock according to env. variable */ -#endif init_baudrate, /* initialize baudrate settings */ serial_init, /* serial communications setup */ console_init_f, diff --git a/board/incaip/Makefile b/board/incaip/Makefile deleted file mode 100644 index 602d30ecee6..00000000000 --- a/board/incaip/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = incaip.o flash.o -obj-y += lowlevel_init.o diff --git a/board/incaip/README b/board/incaip/README deleted file mode 100644 index 132915292ea..00000000000 --- a/board/incaip/README +++ /dev/null @@ -1,57 +0,0 @@ - -Flash programming on the INCA-IP board is complicated because of the -EBU swapping unit. A BDI2000 can be used for flash programming only -if the EBU swapping unit is enabled; otherwise it will not detect the -flash memory. But the EBU swapping unit is disadbled after reset, so -if you program some code to flash with the swapping unit on, it will -not be runnable with the swapping unit off. - -The consequence is that you have to write a pre-swapped image to -flash using the BDI2000. A simple host-side tool "inca-swap-bytes" is -provided in the "tools/" directory. Use it as follows: - - bash$ ./inca-swap-bytes u-boot.bin.swp - -Note that the current BDI config file _disables_ the EBU swapping -unit for the flash bank 0. To enable it, (this is required for the -BDI flash commands to work) uncomment the following line in the -config file: - - ;WM32 0xb8000260 0x404161ff ; Swapping unit enabled - -and comment out - - WM32 0xb8000260 0x004161ff ; Swapping unit disabled - -Alternatively, you can use "mm 0xb8000260 " commands to -enable/disable the swapping unit manually. - -Just for reference, here is the complete sequence of actions we took -to install a U-Boot image into flash. - - 1. ./inca-swap-bytes u-boot.bin.swp - - 2. From BDI: - - mm 0xb8000260 0x404161ff - erase 0xb0000000 - erase 0xb0010000 - prog 0xb0000000 /tftpboot/INCA/u-boot.bin.swp bin - mm 0xb8000260 0x004161ff - go 0xb0000000 - - -Ethernet autonegotiation needs some time to complete. Instead of -delaying the boot process in all cases, we just start the -autonegotiation process when U-Boot comes up and that is all. Most -likely, it will complete by the time the network transfer is -attempted for the first time. In the worst case, if a transfer is -attempted before the autonegotiation is complete, just a single -packet would be lost resulting in a single timeout error, and then -the transfer would proceed normally. So the time that we would have -lost unconditionally waiting for the autonegotiation to complete, we -have to wait only if the file transfer is started immediately after -reset. We've verified that this works for all the clock -configurations. - -(C) 2003 Wolfgang Denk diff --git a/board/incaip/config.mk b/board/incaip/config.mk deleted file mode 100644 index e854f8e655b..00000000000 --- a/board/incaip/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# INCA-IP board with MIPS 4Kc CPU core -# - -# ROM version -CONFIG_SYS_TEXT_BASE = 0xB0000000 - -# RAM version -#CONFIG_SYS_TEXT_BASE = 0x80100000 diff --git a/board/incaip/flash.c b/board/incaip/flash.c deleted file mode 100644 index a786ac9327d..00000000000 --- a/board/incaip/flash.c +++ /dev/null @@ -1,655 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -#if 0 -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa -#else -#define FLASH_CYCLE1 0x0554 -#define FLASH_CYCLE2 0x02ab -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; - ulong * buscon = (ulong *) - ((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2); - - /* Disable write protection */ - *buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS; - -#if 1 - memset(&flash_info[i], 0, sizeof(flash_info_t)); -#endif - - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", - i, flash_info[i].size); - } - - size += flash_info[i].size; - } - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CONFIG_SYS_MONITOR_BASE)); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - flash_get_info(CONFIG_ENV_ADDR)); -#endif - - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base < info->start[0] + info->size) - break; - } - - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[1] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) { - - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - - return (res); -} diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c deleted file mode 100644 index 217b8afa347..00000000000 --- a/board/incaip/incaip.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -extern uint incaip_get_cpuclk(void); - -void _machine_restart(void) -{ - *INCA_IP_WDT_RST_REQ = 0x3f; -} - -static ulong max_sdram_size(void) -{ - /* The only supported SDRAM data width is 16bit. - */ -#define CONFIG_SYS_DW 2 - - /* The only supported number of SDRAM banks is 4. - */ -#define CONFIG_SYS_NB 4 - - ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; - int cols = cfgpb0 & 0xF; - int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB; - - return size; -} - -phys_size_t initdram(int board_type) -{ - int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0; - ulong size, max_size = 0; - ulong our_address; - - asm volatile ("move %0, $25" : "=r" (our_address) :); - - /* Can't probe for RAM size unless we are running from Flash. - */ - if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1)) - { - return max_sdram_size(); - } - - for (cols = 0x8; cols <= 0xC; cols++) - { - for (rows = 0xB; rows <= 0xD; rows++) - { - *INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) | - (rows << 4) | cols; - size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - max_sdram_size()); - - if (size > max_size) - { - best_val = *INCA_IP_SDRAM_MC_CFGPB0; - max_size = size; - } - } - } - - *INCA_IP_SDRAM_MC_CFGPB0 = best_val; - return max_size; -} - -int checkboard (void) -{ - unsigned long chipid = *INCA_IP_WDT_CHIPID; - int part_num; - - puts ("Board: INCA-IP "); - part_num = (chipid >> 12) & 0xffff; - switch (part_num) { - case 0xc0: - printf ("Standard Version, "); - break; - case 0xc1: - printf ("Basic Version, "); - break; - default: - printf ("Unknown Part Number 0x%x ", part_num); - break; - } - - printf ("Chip V1.%ld, ", (chipid >> 28)); - - printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000); - - set_io_port_base(0); - - return 0; -} - -#if defined(CONFIG_INCA_IP_SWITCH) -int board_eth_init(bd_t *bis) -{ - return inca_switch_initialize(bis); -} -#endif diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S deleted file mode 100644 index b6cf6a99600..00000000000 --- a/board/incaip/lowlevel_init.S +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Memory sub-system initialization code for INCA-IP development board. - * - * Copyright (c) 2003 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - - -#define EBU_MODUL_BASE 0xB8000200 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0100(value) -#define MC_ERRADDR(value) 0x0108(value) -#define MC_IOGP(value) 0x0800(value) -#define MC_SELFRFSH(value) 0x0A00(value) -#define MC_CTRLENA(value) 0x1000(value) -#define MC_MRSCODE(value) 0x1008(value) -#define MC_CFGDW(value) 0x1010(value) -#define MC_CFGPB0(value) 0x1018(value) -#define MC_LATENCY(value) 0x1038(value) -#define MC_TREFRESH(value) 0x1040(value) - -#define CGU_MODUL_BASE 0xBF107000 -#define CGU_PLL1CR(value) 0x0008(value) -#define CGU_DIVCR(value) 0x0010(value) -#define CGU_MUXCR(value) 0x0014(value) -#define CGU_PLL1SR(value) 0x000C(value) - - .set noreorder - - -/* - * void ebu_init(long) - * - * a0 has the clock value we are going to run at - */ - .globl ebu_init - .ent ebu_init -ebu_init: -__ebu_init: - - li t1, EBU_MODUL_BASE - li t2, 0xA0000041 - sw t2, EBU_ADDSEL0(t1) - li t2, 0xA0800041 - sw t2, EBU_ADDSEL2(t1) - li t2, 0xBE0000F1 - sw t2, EBU_ADDSEL1(t1) - - li t3, 100000000 - beq a0, t3, 1f - nop - li t3, 133000000 - beq a0, t3, 2f - nop - li t3, 150000000 - beq a0, t3, 2f - nop - b 3f - nop - - /* 100 MHz */ -1: - li t2, 0x8841417D - sw t2, EBU_BUSCON0(t1) - sw t2, EBU_BUSCON2(t1) - li t2, 0x684142BD - b 3f - sw t2, EBU_BUSCON1(t1) /* delay slot */ - - /* 133 or 150 MHz */ -2: - li t2, 0x8841417E - sw t2, EBU_BUSCON0(t1) - sw t2, EBU_BUSCON2(t1) - li t2, 0x684143FD - sw t2, EBU_BUSCON1(t1) -3: - jr ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: -__cgu_init: - - li t1, CGU_MODUL_BASE - - li t3, 100000000 - beq a0, t3, 1f - nop - li t3, 133000000 - beq a0, t3, 2f - nop - li t3, 150000000 - beq a0, t3, 3f - nop - b 5f - nop - - /* 100 MHz clock */ -1: - li t2, 0x80000014 - sw t2, CGU_DIVCR(t1) - li t2, 0x80000000 - sw t2, CGU_MUXCR(t1) - li t2, 0x800B0001 - b 5f - sw t2, CGU_PLL1CR(t1) /* delay slot */ - - /* 133 MHz clock */ -2: - li t2, 0x80000054 - sw t2, CGU_DIVCR(t1) - li t2, 0x80000000 - sw t2, CGU_MUXCR(t1) - li t2, 0x800B0001 - b 5f - sw t2, CGU_PLL1CR(t1) /* delay slot */ - - /* 150 MHz clock */ -3: - li t2, 0x80000017 - sw t2, CGU_DIVCR(t1) - li t2, 0xC00B0001 - sw t2, CGU_PLL1CR(t1) - li t3, 0x80000000 -4: - lw t2, CGU_PLL1SR(t1) - and t2, t2, t3 - beq t2, zero, 4b - nop - li t2, 0x80000001 - sw t2, CGU_MUXCR(t1) -5: - jr ra - nop - - .end cgu_init - - -/* - * void sdram_init(long) - * - * a0 has the clock value - */ - .globl sdram_init - .ent sdram_init -sdram_init: -__sdram_init: - - li t1, MC_MODUL_BASE - -#if 0 - /* Disable memory controller before changing any of its registers */ - sw zero, MC_CTRLENA(t1) -#endif - - li t2, 100000000 - beq a0, t2, 1f - nop - li t2, 133000000 - beq a0, t2, 2f - nop - li t2, 150000000 - beq a0, t2, 3f - nop - b 5f - nop - - /* 100 MHz clock */ -1: - /* Set clock ratio (clkrat=1:1, rddel=3) */ - li t2, 0x00000003 - sw t2, MC_IOGP(t1) - - /* Set sdram refresh rate (4K/64ms @ 100MHz) */ - li t2, 0x0000061A - b 4f - sw t2, MC_TREFRESH(t1) - - /* 133 MHz clock */ -2: - /* Set clock ratio (clkrat=1:1, rddel=3) */ - li t2, 0x00000003 - sw t2, MC_IOGP(t1) - - /* Set sdram refresh rate (4K/64ms @ 133MHz) */ - li t2, 0x00000822 - b 4f - sw t2, MC_TREFRESH(t1) - - /* 150 MHz clock */ -3: - /* Set clock ratio (clkrat=3:2, rddel=4) */ - li t2, 0x00000014 - sw t2, MC_IOGP(t1) - - /* Set sdram refresh rate (4K/64ms @ 150MHz) */ - li t2, 0x00000927 - sw t2, MC_TREFRESH(t1) - -4: - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Clear Power-down registers */ - sw zero, MC_SELFRFSH(t1) - - /* Set CAS Latency */ - li t2, 0x00000020 /* CL = 2 */ - sw t2, MC_MRSCODE(t1) - - /* Set word width to 16 bit */ - li t2, 0x2 - sw t2, MC_CFGDW(t1) - - /* Set CS0 to SDRAM parameters */ - li t2, 0x000014C9 - sw t2, MC_CFGPB0(t1) - - /* Set SDRAM latency parameters */ - li t2, 0x00026325 /* BC PC100 */ - sw t2, MC_LATENCY(t1) - -5: - /* Finally enable the controller */ - li t2, 0x00000001 - sw t2, MC_CTRLENA(t1) - - jr ra - nop - - .end sdram_init - - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - - /* Disable Watchdog. - */ - la t9, disable_incaip_wdt - jalr t9 - nop - - /* EBU, CGU and SDRAM Initialization. - */ - li a0, CONFIG_CPU_CLOCK_RATE - move t0, ra - - /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init() - * modify t0 and a0. - */ - bal __cgu_init - nop - bal __ebu_init - nop - bal __sdram_init - nop - move ra, t0 - - jr ra - nop - - .end lowlevel_init diff --git a/boards.cfg b/boards.cfg index c83aff3b141..f1f699458b7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -519,10 +519,6 @@ Active mips mips32 au1x00 - dbau1x00 Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 - -Active mips mips32 incaip - incaip incaip - Wolfgang Denk -Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk -Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk -Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 15c39e76758..f9742e7d494 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -125,3 +125,4 @@ MVS1 powerpc MPC823 306620b 2008-08-26 Andre Schwar adsvix ARM PXA27x 7610db1 2008-07-30 Adrian Filipi R5200 ColdFire - 48ead7a 2008-03-31 Zachary P. Landau CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs +incaip mips mips32 - 2014-04-17 Wolfgang Denk diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 7f9ce90a6d5..c25b3c93ce5 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GRETH) += greth.o -obj-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c deleted file mode 100644 index cdfbfa67d89..00000000000 --- a/drivers/net/inca-ip_sw.c +++ /dev/null @@ -1,793 +0,0 @@ -/* - * INCA-IP internal switch ethernet driver. - * - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include - -#include -#include -#include -#include -#include - - -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 3 -#define TOUT_LOOP 1000000 - - -#define DELAY udelay(10000) - /* Sometimes the store word instruction hangs while writing to one - * of the Switch registers. Moving the instruction into a separate - * function somehow makes the problem go away. - */ -static void SWORD(volatile u32 * reg, u32 value) -{ - *reg = value; -} - -#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value; -#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) -#define SW_WRITE_REG(reg, value) \ - SWORD(reg, value);\ - DELAY;\ - SWORD(reg, value); - -#define SW_READ_REG(reg, value) \ - value = (u32)*((volatile u32*)reg);\ - DELAY;\ - value = (u32)*((volatile u32*)reg); - -#define INCA_DMA_TX_POLLING_TIME 0x07 -#define INCA_DMA_RX_POLLING_TIME 0x07 - -#define INCA_DMA_TX_HOLD 0x80000000 -#define INCA_DMA_TX_EOP 0x40000000 -#define INCA_DMA_TX_SOP 0x20000000 -#define INCA_DMA_TX_ICPT 0x10000000 -#define INCA_DMA_TX_IEOP 0x08000000 - -#define INCA_DMA_RX_C 0x80000000 -#define INCA_DMA_RX_SOP 0x40000000 -#define INCA_DMA_RX_EOP 0x20000000 - -#define INCA_SWITCH_PHY_SPEED_10H 0x1 -#define INCA_SWITCH_PHY_SPEED_10F 0x5 -#define INCA_SWITCH_PHY_SPEED_100H 0x2 -#define INCA_SWITCH_PHY_SPEED_100F 0x6 - -/************************ Auto MDIX settings ************************/ -#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR -#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL -#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT -#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16 - -#define WAIT_SIGNAL_RETRIES 100 -#define WAIT_LINK_RETRIES 100 -#define LINK_RETRY_DELAY 2000 /* ms */ -/********************************************************************/ - -typedef struct -{ - union { - struct { - volatile u32 HOLD :1; - volatile u32 ICpt :1; - volatile u32 IEop :1; - volatile u32 offset :3; - volatile u32 reserved0 :4; - volatile u32 NFB :22; - }field; - - volatile u32 word; - }params; - - volatile u32 nextRxDescPtr; - - volatile u32 RxDataPtr; - - union { - struct { - volatile u32 C :1; - volatile u32 Sop :1; - volatile u32 Eop :1; - volatile u32 reserved3 :12; - volatile u32 NBT :17; - }field; - - volatile u32 word; - }status; - -} inca_rx_descriptor_t; - - -typedef struct -{ - union { - struct { - volatile u32 HOLD :1; - volatile u32 Eop :1; - volatile u32 Sop :1; - volatile u32 ICpt :1; - volatile u32 IEop :1; - volatile u32 reserved0 :5; - volatile u32 NBA :22; - }field; - - volatile u32 word; - }params; - - volatile u32 nextTxDescPtr; - - volatile u32 TxDataPtr; - - volatile u32 C :1; - volatile u32 reserved3 :31; - -} inca_tx_descriptor_t; - - -static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16))); -static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16))); - -static int tx_new, rx_new, tx_hold, rx_hold; -static int tx_old_hold = -1; -static int initialized = 0; - - -static int inca_switch_init(struct eth_device *dev, bd_t * bis); -static int inca_switch_send(struct eth_device *dev, void *packet, int length); -static int inca_switch_recv(struct eth_device *dev); -static void inca_switch_halt(struct eth_device *dev); -static void inca_init_switch_chip(void); -static void inca_dma_init(void); -static int inca_amdix(void); - - -int inca_switch_initialize(bd_t * bis) -{ - struct eth_device *dev; - -#if 0 - printf("Entered inca_switch_initialize()\n"); -#endif - - if (!(dev = (struct eth_device *) malloc (sizeof *dev))) { - printf("Failed to allocate memory\n"); - return 0; - } - memset(dev, 0, sizeof(*dev)); - - inca_dma_init(); - - inca_init_switch_chip(); - -#if defined(CONFIG_INCA_IP_SWITCH_AMDIX) - inca_amdix(); -#endif - - sprintf(dev->name, "INCA-IP Switch"); - dev->init = inca_switch_init; - dev->halt = inca_switch_halt; - dev->send = inca_switch_send; - dev->recv = inca_switch_recv; - - eth_register(dev); - -#if 0 - printf("Leaving inca_switch_initialize()\n"); -#endif - - return 0; -} - - -static int inca_switch_init(struct eth_device *dev, bd_t * bis) -{ - int i; - u32 v, regValue; - u16 wTmp; - -#if 0 - printf("Entering inca_switch_init()\n"); -#endif - - /* Set MAC address. - */ - wTmp = (u16)dev->enetaddr[0]; - regValue = (wTmp << 8) | dev->enetaddr[1]; - - SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue); - - wTmp = (u16)dev->enetaddr[2]; - regValue = (wTmp << 8) | dev->enetaddr[3]; - regValue = regValue << 16; - wTmp = (u16)dev->enetaddr[4]; - regValue |= (wTmp<<8) | dev->enetaddr[5]; - - SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue); - - /* Initialize the descriptor rings. - */ - for (i = 0; i < NUM_RX_DESC; i++) { - inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]); - memset(rx_desc, 0, sizeof(rx_ring[i])); - - /* Set maximum size of receive buffer. - */ - rx_desc->params.field.NFB = PKTSIZE_ALIGN; - - /* Set the offset of the receive buffer. Zero means - * that the offset mechanism is not used. - */ - rx_desc->params.field.offset = 0; - - /* Check if it is the last descriptor. - */ - if (i == (NUM_RX_DESC - 1)) { - /* Let the last descriptor point to the first - * one. - */ - rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring); - } else { - /* Set the address of the next descriptor. - */ - rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]); - } - - rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]); - } - -#if 0 - printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]); - printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]); -#endif - - for (i = 0; i < NUM_TX_DESC; i++) { - inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]); - - memset(tx_desc, 0, sizeof(tx_ring[i])); - - tx_desc->params.word = 0; - tx_desc->params.field.HOLD = 1; - tx_desc->C = 1; - - /* Check if it is the last descriptor. - */ - if (i == (NUM_TX_DESC - 1)) { - /* Let the last descriptor point to the - * first one. - */ - tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring); - } else { - /* Set the address of the next descriptor. - */ - tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]); - } - } - - /* Initialize RxDMA. - */ - DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v); - debug("RX status = 0x%08X\n", v); - - /* Writing to the FRDA of CHANNEL. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring); - - /* Writing to the COMMAND REG. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT); - - /* Initialize TxDMA. - */ - DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v); - debug("TX status = 0x%08X\n", v); - - /* Writing to the FRDA of CHANNEL. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring); - - tx_new = rx_new = 0; - - tx_hold = NUM_TX_DESC - 1; - rx_hold = NUM_RX_DESC - 1; - -#if 0 - rx_ring[rx_hold].params.field.HOLD = 1; -#endif - /* enable spanning tree forwarding, enable the CPU port */ - /* ST_PT: - * CPS (CPU port status) 0x3 (forwarding) - * LPS (LAN port status) 0x3 (forwarding) - * PPS (PC port status) 0x3 (forwarding) - */ - SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f); - -#if 0 - printf("Leaving inca_switch_init()\n"); -#endif - - return 0; -} - - -static int inca_switch_send(struct eth_device *dev, void *packet, int length) -{ - int i; - int res = -1; - u32 command; - u32 regValue; - inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]); - -#if 0 - printf("Entered inca_switch_send()\n"); -#endif - - if (length <= 0) { - printf ("%s: bad packet size: %d\n", dev->name, length); - goto Done; - } - - for(i = 0; tx_desc->C == 0; i++) { - if (i >= TOUT_LOOP) { - printf("%s: tx error buffer not ready\n", dev->name); - goto Done; - } - } - - if (tx_old_hold >= 0) { - ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1; - } - tx_old_hold = tx_hold; - - tx_desc->params.word = - (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD); - - tx_desc->C = 0; - tx_desc->TxDataPtr = (u32)packet; - tx_desc->params.field.NBA = length; - - ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0; - - tx_hold = tx_new; - tx_new = (tx_new + 1) % NUM_TX_DESC; - - - if (! initialized) { - command = INCA_IP_DMA_DMA_TXCCR0_INIT; - initialized = 1; - } else { - command = INCA_IP_DMA_DMA_TXCCR0_HR; - } - - DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); - regValue |= command; -#if 0 - printf("regValue = 0x%x\n", regValue); -#endif - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); - -#if 1 - for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) { - if (i >= TOUT_LOOP) { - printf("%s: tx buffer not ready\n", dev->name); - goto Done; - } - } -#endif - res = length; -Done: -#if 0 - printf("Leaving inca_switch_send()\n"); -#endif - return res; -} - - -static int inca_switch_recv(struct eth_device *dev) -{ - int length = 0; - inca_rx_descriptor_t * rx_desc; - -#if 0 - printf("Entered inca_switch_recv()\n"); -#endif - - for (;;) { - rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]); - - if (rx_desc->status.field.C == 0) { - break; - } - -#if 0 - rx_ring[rx_new].params.field.HOLD = 1; -#endif - - if (! rx_desc->status.field.Eop) { - printf("Partly received packet!!!\n"); - break; - } - - length = rx_desc->status.field.NBT; - rx_desc->status.word &= - ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C); -#if 0 -{ - int i; - for (i=0;iparams.field.HOLD = 0; - - rx_hold = rx_new; - - rx_new = (rx_new + 1) % NUM_RX_DESC; - } - -#if 0 - printf("Leaving inca_switch_recv()\n"); -#endif - - return length; -} - - -static void inca_switch_halt(struct eth_device *dev) -{ -#if 0 - printf("Entered inca_switch_halt()\n"); -#endif - -#if 1 - initialized = 0; -#endif -#if 1 - /* Disable forwarding to the CPU port. - */ - SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf); - - /* Close RxDMA channel. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); - - /* Close TxDMA channel. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF); - - -#endif -#if 0 - printf("Leaving inca_switch_halt()\n"); -#endif -} - - -static void inca_init_switch_chip(void) -{ - u32 regValue; - - /* To workaround a problem with collision counter - * (see Errata sheet). - */ - SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001); - SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001); - -#if 1 - /* init MDIO configuration: - * MDS (Poll speed): 0x01 (4ms) - * PHY_LAN_ADDR: 0x06 - * PHY_PC_ADDR: 0x05 - * UEP (Use External PHY): 0x00 (Internal PHY is used) - * PS (Port Select): 0x00 (PT/UMM for LAN) - * PT (PHY Test): 0x00 (no test mode) - * UMM (Use MDIO Mode): 0x00 (state machine is disabled) - */ - SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50); - - /* init PHY: - * SL (Auto Neg. Speed for LAN) - * SP (Auto Neg. Speed for PC) - * LL (Link Status for LAN) - * LP (Link Status for PC) - * DL (Duplex Status for LAN) - * DP (Duplex Status for PC) - * PL (Auto Neg. Pause Status for LAN) - * PP (Auto Neg. Pause Status for PC) - */ - SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff); - - /* MDIO_ACC: - * RA (Request/Ack) 0x01 (Request) - * RW (Read/Write) 0x01 (Write) - * PHY_ADDR 0x05 (PC) - * REG_ADDR 0x00 (PHY_BCR: basic control register) - * PHY_DATA 0x8000 - * Reset - software reset - * LB (loop back) - normal - * SS (speed select) - 10 Mbit/s - * ANE (auto neg. enable) - enable - * PD (power down) - normal - * ISO (isolate) - normal - * RAN (restart auto neg.) - normal - * DM (duplex mode) - half duplex - * CT (collision test) - enable - */ - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000); - - /* MDIO_ACC: - * RA (Request/Ack) 0x01 (Request) - * RW (Read/Write) 0x01 (Write) - * PHY_ADDR 0x06 (LAN) - * REG_ADDR 0x00 (PHY_BCR: basic control register) - * PHY_DATA 0x8000 - * Reset - software reset - * LB (loop back) - normal - * SS (speed select) - 10 Mbit/s - * ANE (auto neg. enable) - enable - * PD (power down) - normal - * ISO (isolate) - normal - * RAN (restart auto neg.) - normal - * DM (duplex mode) - half duplex - * CT (collision test) - enable - */ - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000); - -#endif - - /* Make sure the CPU port is disabled for now. We - * don't want packets to get stacked for us until - * we enable DMA and are prepared to receive them. - */ - SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf); - - SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue); - - /* CRC GEN is enabled. - */ - regValue |= 0x00000200; - SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue); - - /* ADD TAG is disabled. - */ - SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue); - regValue &= ~0x00000002; - SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue); -} - - -static void inca_dma_init(void) -{ - /* Switch off all DMA channels. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF); - - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF); - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF); - - /* Setup TX channel polling time. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME); - - /* Setup RX channel polling time. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME); - - /* ERRATA: write reset value into the DMA RX IMR register. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF); - - /* Just in case: disable all transmit interrupts also. - */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF); - - DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF); - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF); -} - -#if defined(CONFIG_INCA_IP_SWITCH_AMDIX) -static int inca_amdix(void) -{ - u32 phyReg1 = 0; - u32 phyReg4 = 0; - u32 phyReg5 = 0; - u32 phyReg6 = 0; - u32 phyReg31 = 0; - u32 regEphy = 0; - int mdi_flag; - int retries; - - /* Setup GPIO pins. - */ - *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - -#if 0 - /* Wait for signal. - */ - retries = WAIT_SIGNAL_RETRIES; - while (--retries) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (17 << 16)); /* PHY_MCSR */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); - } while (phyReg1 & (1 << 31)); - - if (phyReg1 & (1 << 1)) { - /* Signal detected */ - break; - } - } - - if (!retries) - goto Fail; -#endif - - /* Set MDI mode. - */ - *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - mdi_flag = 1; - - /* Wait for link. - */ - retries = WAIT_LINK_RETRIES; - while (--retries) { - udelay(LINK_RETRY_DELAY * 1000); - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (1 << 16)); /* PHY_BSR */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); - } while (phyReg1 & (1 << 31)); - - if (phyReg1 & (1 << 2)) { - /* Link is up */ - break; - } else if (mdi_flag) { - /* Set MDIX mode */ - *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - mdi_flag = 0; - } else { - /* Set MDI mode */ - *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); - mdi_flag = 1; - } - } - - if (!retries) { - goto Fail; - } else { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (1 << 16)); /* PHY_BSR */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); - } while (phyReg1 & (1 << 31)); - - /* Auto-negotiation / Parallel detection complete - */ - if (phyReg1 & (1 << 5)) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (31 << 16)); /* PHY_SCSR */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31); - } while (phyReg31 & (1 << 31)); - - switch ((phyReg31 >> 2) & 0x7) { - case INCA_SWITCH_PHY_SPEED_10H: - /* 10Base-T Half-duplex */ - regEphy = 0; - break; - case INCA_SWITCH_PHY_SPEED_10F: - /* 10Base-T Full-duplex */ - regEphy = INCA_IP_Switch_EPHY_DL; - break; - case INCA_SWITCH_PHY_SPEED_100H: - /* 100Base-TX Half-duplex */ - regEphy = INCA_IP_Switch_EPHY_SL; - break; - case INCA_SWITCH_PHY_SPEED_100F: - /* 100Base-TX Full-duplex */ - regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL; - break; - } - - /* In case of Auto-negotiation, - * update the negotiated PAUSE support status - */ - if (phyReg1 & (1 << 3)) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (6 << 16)); /* MII_EXPANSION */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6); - } while (phyReg6 & (1 << 31)); - - /* We are Autoneg-able. - * Is Link partner also able to autoneg? - */ - if (phyReg6 & (1 << 0)) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (4 << 16)); /* MII_ADVERTISE */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4); - } while (phyReg4 & (1 << 31)); - - /* We advertise PAUSE capab. - * Does link partner also advertise it? - */ - if (phyReg4 & (1 << 10)) { - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, - (0x1 << 31) | /* RA */ - (0x0 << 30) | /* Read */ - (0x6 << 21) | /* LAN */ - (5 << 16)); /* MII_LPA */ - do { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5); - } while (phyReg5 & (1 << 31)); - - /* Link partner is PAUSE capab. - */ - if (phyReg5 & (1 << 10)) { - regEphy |= INCA_IP_Switch_EPHY_PL; - } - } - } - - } - - /* Link is up */ - regEphy |= INCA_IP_Switch_EPHY_LL; - - SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy); - } - } - - return 0; - -Fail: - printf("No Link on LAN port\n"); - return -1; -} -#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */ diff --git a/include/common.h b/include/common.h index baf361b3e55..5fb0bb2d3d4 100644 --- a/include/common.h +++ b/include/common.h @@ -681,9 +681,6 @@ ulong get_UCLK (void); #if defined(CONFIG_LH7A40X) ulong get_PLLCLK (void); #endif -#if defined CONFIG_INCA_IP -uint incaip_get_cpuclk (void); -#endif #if defined(CONFIG_IMX) ulong get_systemPLLCLK(void); ulong get_FCLK(void); diff --git a/include/configs/incaip.h b/include/configs/incaip.h deleted file mode 100644 index e11d1843b9b..00000000000 --- a/include/configs/incaip.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file contains the configuration parameters for the INCA-IP board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */ - -#define CONFIG_XWAY_SWAP_BYTES - -/* - * Clock for the MIPS core (MHz) - * allowed values: 100000000, 133000000, and 150000000 (default) - */ -#ifndef CONFIG_CPU_CLOCK_RATE -#define CONFIG_CPU_CLOCK_RATE 150000000 -#endif - -#define CONFIG_SYS_XWAY_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "ethaddr=${ethaddr} " \ - "panic=1\0" \ - "flash_nfs=run nfsargs addip addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 80500000 ${bootfile};" \ - "run nfsargs addip addmisc;bootm\0" \ - "rootpath=/opt/eldk/mips_4KC\0" \ - "bootfile=/tftpboot/INCA/uImage\0" \ - "kernel_addr=B0040000\0" \ - "ramdisk_addr=B0100000\0" \ - "u-boot=/tftpboot/INCA/u-boot.bin\0" \ - "load=tftp 80500000 ${u-boot}\0" \ - "update=protect off 1:0-2;era 1:0-2;" \ - "cp.b 80500000 B0000000 ${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "INCA-IP # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ - -#define CONFIG_SYS_MALLOC_LEN 128*1024 - -#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 - -#define CONFIG_SYS_MIPS_TIMER_FREQ (incaip_get_cpuclk() / 2) - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -#define CONFIG_SYS_LOAD_ADDR 0x80100000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xb0800000 /* Flash Bank #2 */ - -/* The following #defines are needed to get flash environment right */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_ADDR 0xB0030000 -#define CONFIG_ENV_SIZE 0x10000 - -#define CONFIG_FLASH_16BIT - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_INCA_IP_SWITCH -#define CONFIG_INCA_IP_SWITCH_AMDIX - -/* - * JFFS2 partitions - */ -/* No command line, one static partition, use all space on the device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=INCA-IP Bank 0" -#define MTDPARTS_DEFAULT "mtdparts=INCA-IP Bank 0:192k(uboot)," \ - "64k(env)," \ - "768k(linux)," \ - "1m@3m(rootfs)," \ - "768k(linux2)," \ - "3m@5m(rootfs2)" -*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_DCACHE_SIZE 4096 -#define CONFIG_SYS_ICACHE_SIZE 4096 -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#endif /* __CONFIG_H */ diff --git a/include/netdev.h b/include/netdev.h index 32b5073ef02..e211f1841f6 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -54,7 +54,6 @@ int ftmac100_initialize(bd_t *bits); int ftmac110_initialize(bd_t *bits); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); -int inca_switch_initialize(bd_t *bis); int ks8695_eth_initialize(void); int ks8851_mll_initialize(u8 dev_num, int base_addr); int lan91c96_initialize(u8 dev_num, int base_addr); -- cgit v1.3.1 From 0ecb15c8e98edf6a4a120eefc43bcb1e8f48d97b Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Thu, 19 Dec 2013 11:08:46 +0530 Subject: fsl/usb: Fix phy type for Second USB controller Set correct phy_type value for second USB controller. This is required for supporting SOCs having 2 USB controllers working simultaneously, one with UTMI phy and other with ULPI phy Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- drivers/usb/host/ehci-fsl.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 1ca7cf5d9b7..3fd9e13af8a 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -41,11 +41,14 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct usb_ehci *ehci = NULL; const char *phy_type = NULL; size_t len; + char current_usb_controller[5]; #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY char usb_phy[5]; usb_phy[0] = '\0'; #endif + memset(current_usb_controller, '\0', 5); + snprintf(current_usb_controller, 4, "usb%d", index+1); switch (index) { case 0: @@ -70,8 +73,9 @@ int ehci_hcd_init(int index, enum usb_init_type init, out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); /* Init phy */ - if (hwconfig_sub("usb1", "phy_type")) - phy_type = hwconfig_subarg("usb1", "phy_type", &len); + if (hwconfig_sub(current_usb_controller, "phy_type")) + phy_type = hwconfig_subarg(current_usb_controller, + "phy_type", &len); else phy_type = getenv("usb_phy_type"); -- cgit v1.3.1 From dcf1d774bf5c2612538658eac01931895b7a805f Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 21 Mar 2014 16:21:44 +0800 Subject: QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- README | 9 +++++++-- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- drivers/net/fm/fm.c | 12 ++++++------ drivers/qe/qe.c | 2 +- include/configs/B4860QDS.h | 10 +++++----- include/configs/MPC8569MDS.h | 2 +- include/configs/P1023RDB.h | 2 +- include/configs/P1023RDS.h | 4 ++-- include/configs/P2041RDB.h | 10 +++++----- include/configs/T1040QDS.h | 8 ++++---- include/configs/T1040RDB.h | 8 ++++---- include/configs/T1042RDB_PI.h | 8 ++++---- include/configs/T208xQDS.h | 10 +++++----- include/configs/T208xRDB.h | 10 +++++----- include/configs/T4240EMU.h | 2 +- include/configs/T4240QDS.h | 10 +++++----- include/configs/corenet_ds.h | 10 +++++----- include/configs/km/km8309-common.h | 2 +- include/configs/km/kmp204x-common.h | 2 +- include/configs/p1_p2_rdb_pc.h | 2 +- include/configs/p1_twr.h | 2 +- 21 files changed, 66 insertions(+), 61 deletions(-) (limited to 'drivers') diff --git a/README b/README index 4715cfbc254..cb96322fb71 100644 --- a/README +++ b/README @@ -4502,8 +4502,13 @@ This firmware often needs to be loaded during U-Boot booting, so macros are used to identify the storage device (NOR flash, SPI, etc) and the address within that device. -- CONFIG_SYS_QE_FMAN_FW_ADDR - The address in the storage device where the firmware is located. The +- CONFIG_SYS_FMAN_FW_ADDR + The address in the storage device where the FMAN microcode is located. The + meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro + is also specified. + +- CONFIG_SYS_QE_FW_ADDR + The address in the storage device where the QE microcode is located. The meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro is also specified. diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 19df95fee29..0b4d8eaff85 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -818,7 +818,7 @@ void cpu_secondary_init_r(void) /* load QE firmware from NAND flash to DDR first */ ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, - &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); + &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); if (ret && ret == -EUCLEAN) { printf ("NAND read for QE firmware at offset %x failed %d\n", diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index bca20b33303..400e9dd5e24 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -350,16 +350,16 @@ int fm_init_common(int index, struct ccsr_fman *reg) { int rc; #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR) - void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND) size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); - rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR, + rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR, &fw_length, (u_char *)addr); if (rc == -EUCLEAN) { printf("NAND read of FMAN firmware at offset 0x%x failed %d\n", - CONFIG_SYS_QE_FMAN_FW_ADDR, rc); + CONFIG_SYS_FMAN_FW_ADDR, rc); } #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) struct spi_flash *ucode_flash; @@ -371,7 +371,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) if (!ucode_flash) printf("SF: probe for ucode failed\n"); else { - ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR, + ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR, CONFIG_SYS_QE_FMAN_FW_LENGTH, addr); if (ret) printf("SF: read for ucode failed\n"); @@ -381,7 +381,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) int dev = CONFIG_SYS_MMC_ENV_DEV; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; - u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512; + u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); if (!mmc) @@ -395,7 +395,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) flush_cache((ulong)addr, cnt * 512); } #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) - void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; + void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR; #else void *addr = NULL; #endif diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index b5ddc4b474d..b1da75ec4d9 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -165,7 +165,7 @@ void qe_init(uint qe_base) /* * Upload microcode to IRAM for those SOCs which do not have ROM in QE. */ - qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR); + qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); /* enable the microcode in IRAM */ out_be32(&qe_immr->iram.iready,QE_IRAM_READY); diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index b2483026870..b9ec9573db0 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -596,7 +596,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -604,10 +604,10 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -617,10 +617,10 @@ unsigned long get_board_ddr_clk(void); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 58b9c26e93d..5165a456aa1 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -493,7 +493,7 @@ extern unsigned long get_clock_freq(void); /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000 +#define CONFIG_SYS_QE_FW_ADDR 0xfff00000 /* * BOOTP options diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index b41cb4a13ef..d7274f1b684 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -360,7 +360,7 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index 2ffa3546de7..0ee75dc4b25 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -500,10 +500,10 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x1f00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b3880f190f9..f024c29dcd3 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -506,7 +506,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -514,10 +514,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -527,10 +527,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 993f9ae5336..84213b8eaf1 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -602,7 +602,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -610,13 +610,13 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 395845bd68d..7420db921e7 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -517,7 +517,7 @@ * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -525,13 +525,13 @@ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index 68656e6ef15..a2af6b02e10 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -525,7 +525,7 @@ * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -533,13 +533,13 @@ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 399ddbb791c..04527e3ec5c 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -552,7 +552,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -560,10 +560,10 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -573,10 +573,10 @@ unsigned long get_board_ddr_clk(void); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 743eee3161c..66f8a4ce8f2 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -510,7 +510,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #define CONFIG_CORTINA_FW_ADDR 0x120000 #elif defined(CONFIG_SDCARD) @@ -520,12 +520,12 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #define CONFIG_CORTINA_FW_ADDR (512 * 1808) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_CORTINA_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* @@ -536,11 +536,11 @@ unsigned long get_board_ddr_clk(void); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h index c81c4577e3a..ad5a9a6f0c8 100644 --- a/include/configs/T4240EMU.h +++ b/include/configs/T4240EMU.h @@ -98,7 +98,7 @@ #define CONFIG_SYS_INTERLAKEN #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 56e1293720c..1b98cfda3ec 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -375,7 +375,7 @@ unsigned long get_board_ddr_clk(void); * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -383,10 +383,10 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -396,10 +396,10 @@ unsigned long get_board_ddr_clk(void); * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 1e4bfc49fc9..ca14558357a 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -509,7 +509,7 @@ * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -517,10 +517,10 @@ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -530,10 +530,10 @@ * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h index 29c6f60971a..c8df23b534e 100644 --- a/include/configs/km/km8309-common.h +++ b/include/configs/km/km8309-common.h @@ -27,7 +27,7 @@ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR /* at end of uboot partition, before env */ -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xF00B0000 +#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 /* * System IO Config diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 582978afe20..418e3d12981 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -350,7 +350,7 @@ int get_scl(void); * ucode is stored after env, so we got 0x120000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x120000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x120000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 07b61795bb9..d3a792adf80 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -772,7 +772,7 @@ #ifdef CONFIG_QE /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 +#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index c296a075994..97ec593c207 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -348,7 +348,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #ifdef CONFIG_QE /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 +#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ -- cgit v1.3.1 From 2a44efeb217f1516052555bb66d7de962862bb51 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 21 Mar 2014 16:21:45 +0800 Subject: QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 16 +++++++++++++--- arch/powerpc/cpu/mpc85xx/qe_io.c | 2 +- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++++ arch/powerpc/cpu/mpc85xx/t1040_ids.c | 1 + arch/powerpc/include/asm/config_mpc85xx.h | 3 +++ arch/powerpc/include/asm/fsl_liodn.h | 4 ++++ arch/powerpc/include/asm/immap_85xx.h | 5 ++++- drivers/qe/qe.h | 2 ++ 8 files changed, 32 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 0b4d8eaff85..0a33e8dbc1f 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -33,6 +33,9 @@ #endif #include "../../../../drivers/block/fsl_sata.h" +#ifdef CONFIG_U_QE +#include "../../../../drivers/qe/qe.h" +#endif DECLARE_GLOBAL_DATA_PTR; @@ -84,7 +87,7 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) #endif -#ifdef CONFIG_QE +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); @@ -323,10 +326,12 @@ void cpu_init_f (void) #if defined(CONFIG_CPM2) m8560_cpm_reset(); #endif -#ifdef CONFIG_QE + +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) /* Config QE ioports */ config_qe_ioports(); #endif + #if defined(CONFIG_FSL_DMA) dma_init(); #endif @@ -810,8 +815,13 @@ int sata_initialize(void) void cpu_secondary_init_r(void) { -#ifdef CONFIG_QE +#ifdef CONFIG_U_QE + uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ +#elif defined CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ +#endif + +#ifdef CONFIG_QE #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND int ret; size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c index 76c60da4201..d2825ec36ec 100644 --- a/arch/powerpc/cpu/mpc85xx/qe_io.c +++ b/arch/powerpc/cpu/mpc85xx/qe_io.c @@ -12,7 +12,7 @@ #include "asm/io.h" #include "asm/immap_85xx.h" -#if defined(CONFIG_QE) +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) #define NUM_OF_PINS 32 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) { diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index adf09efa279..488fd5ea767 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -336,6 +336,10 @@ void get_sys_info(sys_info_t *sys_info) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ +#ifdef CONFIG_U_QE + sys_info->freq_qe = sys_info->freq_systembus / 2; +#endif + #else /* CONFIG_FSL_CORENET */ uint plat_ratio, e500_ratio, half_freq_systembus; int i; diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 68160a9512b..1034cd4852b 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -46,6 +46,7 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(2, 227), /* SET_NEXUS_LIODN(557), -- not yet implemented */ + SET_QE_LIODN(559), }; int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index e376783963c..39035b68acb 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -736,6 +736,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 44bc88dcecd..f658bcbc66a 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -99,6 +99,10 @@ extern void fdt_fixup_liodn(void *blob); SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\ CONFIG_SYS_MPC85xx_ESDHC_OFFSET) +#define SET_QE_LIODN(liodn) \ + SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\ + CONFIG_SYS_MPC85xx_QE_OFFSET) + #define SET_QMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \ CONFIG_SYS_FSL_QMAN_OFFSET, \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 4b6f9d018e9..4bda0f19344 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1889,7 +1889,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) u32 sata2liodnr; /* SATA 2 LIODN */ u32 sata3liodnr; /* SATA 3 LIODN */ u32 sata4liodnr; /* SATA 4 LIODN */ - u8 res22[32]; + u8 res22[24]; + u32 qeliodnr; /* QE LIODN */ + u8 res_57c[4]; u32 dma1liodnr; /* DMA 1 LIODN */ u32 dma2liodnr; /* DMA 2 LIODN */ u32 dma3liodnr; /* DMA 3 LIODN */ @@ -2877,6 +2879,7 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 +#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\ && !defined(CONFIG_PPC_B4420) diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index c82ac7b0710..ebb7c5f1246 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -282,5 +282,7 @@ int qe_set_mii_clk_src(int ucc_num); int qe_upload_firmware(const struct qe_firmware *firmware); struct qe_firmware_info *qe_get_firmware_info(void); void ft_qe_setup(void *blob); +void qe_init(uint qe_base); +void qe_reset(void); #endif /* __QE_H__ */ -- cgit v1.3.1 From e77224e2d8a2ec5accbedc70c87f171115a3e2b2 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 19 Mar 2014 13:52:34 -0700 Subject: driver/fsl_ifc: Add a function to finalize CS0 address binding For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded to higher address to support large space. Signed-off-by: York Sun CC: Prabhakar Kushwaha --- drivers/misc/fsl_ifc.c | 7 +++++++ include/fsl_ifc.h | 1 + 2 files changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index be619736674..3902e9ff53d 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -162,3 +162,10 @@ void init_early_memctl_regs(void) set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); #endif } + +void init_final_memctl_regs(void) +{ +#ifdef CONFIG_SYS_CSPR0_FINAL + set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL); +#endif +} diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 58a6efdfe05..630e4b4999b 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -784,6 +784,7 @@ enum ifc_nand_fir_opcodes { extern void print_ifc_regs(void); extern void init_early_memctl_regs(void); +void init_final_memctl_regs(void); #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) -- cgit v1.3.1 From 44afbbc0f0733381fefa159cc14931d7f711356e Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Wed, 26 Mar 2014 18:13:14 +0200 Subject: net/phy: Fix PHY id for VSC8514 In the current Datasheet for VSC8514 there is a mistake, saying that the PHY id is 0x70570. The real value in the identifier registers is 0x70670. Linux PHY driver uses 0x70670 also. Signed-off-by: Codrin Ciubotariu Cc: York Sun Reviewed-by: York Sun --- drivers/net/phy/vitesse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index c5559796611..3a55d271a53 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -296,7 +296,7 @@ static struct phy_driver VSC8574_driver = { static struct phy_driver VSC8514_driver = { .name = "Vitesse VSC8514", - .uid = 0x70570, + .uid = 0x70670, .mask = 0xffff0, .features = PHY_GBIT_FEATURES, .config = &vsc8514_config, -- cgit v1.3.1 From 34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 27 Mar 2014 17:54:47 -0700 Subject: driver/ddr/fsl: Add DDR4 support to Freescale DDR driver Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun --- README | 13 +- arch/powerpc/include/asm/config_mpc85xx.h | 17 +- common/ddr_spd.c | 45 +- drivers/ddr/fsl/Makefile | 19 +- drivers/ddr/fsl/ctrl_regs.c | 739 ++++++++++++++++++++++++++++-- drivers/ddr/fsl/ddr4_dimm_params.c | 300 ++++++++++++ drivers/ddr/fsl/fsl_ddr_gen4.c | 234 ++++++++++ drivers/ddr/fsl/interactive.c | 391 +++++++++++++++- drivers/ddr/fsl/lc_common_dimm_params.c | 407 ++++++++-------- drivers/ddr/fsl/main.c | 25 +- drivers/ddr/fsl/options.c | 34 +- drivers/ddr/fsl/util.c | 26 +- include/common_timing_params.h | 23 +- include/ddr_spd.h | 226 ++++++++- include/fsl_ddr.h | 7 +- include/fsl_ddr_dimm_params.h | 77 ++-- include/fsl_ddr_sdram.h | 63 ++- include/fsl_ddrc_version.h | 18 + include/fsl_immap.h | 35 +- 19 files changed, 2378 insertions(+), 321 deletions(-) create mode 100644 drivers/ddr/fsl/ddr4_dimm_params.c create mode 100644 drivers/ddr/fsl/fsl_ddr_gen4.c create mode 100644 include/fsl_ddrc_version.h (limited to 'drivers') diff --git a/README b/README index cb96322fb71..bbd7399f537 100644 --- a/README +++ b/README @@ -458,6 +458,9 @@ The following options need to be configured: CONFIG_SYS_FSL_DDRC_GEN3 Freescale DDR3 controller. + CONFIG_SYS_FSL_DDRC_GEN4 + Freescale DDR4 controller. + CONFIG_SYS_FSL_DDRC_ARM_GEN3 Freescale DDR3 controller for ARM-based SoCs. @@ -473,7 +476,15 @@ The following options need to be configured: CONFIG_SYS_FSL_DDR3 Board config to use DDR3. It can be enabled for SoCs with - Freescale DDR3 controllers. + Freescale DDR3 or DDR3L controllers. + + CONFIG_SYS_FSL_DDR3L + Board config to use DDR3L. It can be enabled for SoCs with + DDR3L controllers. + + CONFIG_SYS_FSL_DDR4 + Board config to use DDR4. It can be enabled for SoCs with + DDR4 controllers. CONFIG_SYS_FSL_IFC_BE Defines the IFC controller register space as Big Endian diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 39035b68acb..fe68e0e2808 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -19,8 +19,8 @@ */ #define CONFIG_PPC_SPINTABLE_COMPATIBLE -#define FSL_DDR_VER_4_7 47 -#define FSL_DDR_VER_5_0 50 +#include +#define CONFIG_SYS_FSL_DDR_BE /* IP endianness */ #define CONFIG_SYS_FSL_IFC_BE @@ -401,6 +401,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -442,6 +443,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -490,6 +492,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 @@ -527,6 +530,7 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -553,6 +557,7 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 @@ -571,6 +576,7 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 @@ -704,6 +710,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#endif #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) #define CONFIG_MAX_CPUS 4 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) @@ -796,6 +805,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_SEC_COMPAT 6 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_A005125 @@ -820,7 +830,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ - !defined(CONFIG_SYS_FSL_DDRC_GEN3) + !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ + !defined(CONFIG_SYS_FSL_DDRC_GEN4) #define CONFIG_SYS_FSL_DDRC_GEN3 #endif diff --git a/common/ddr_spd.c b/common/ddr_spd.c index 7a388bb9fa1..438e71afd20 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -116,3 +116,46 @@ ddr3_spd_check(const ddr3_spd_eeprom_t *spd) return 1; } } + +unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd) +{ + char *p = (char *)spd; + int csum16; + int len; + char crc_lsb; /* byte 126 */ + char crc_msb; /* byte 127 */ + + len = 126; + csum16 = crc16(p, len); + + crc_lsb = (char) (csum16 & 0xff); + crc_msb = (char) (csum16 >> 8); + + if (spd->crc[0] != crc_lsb || spd->crc[1] != crc_msb) { + printf("SPD checksum unexpected.\n" + "Checksum lsb in SPD = %02X, computed SPD = %02X\n" + "Checksum msb in SPD = %02X, computed SPD = %02X\n", + spd->crc[0], crc_lsb, spd->crc[1], crc_msb); + return 1; + } + + p = (char *)((ulong)spd + 128); + len = 126; + csum16 = crc16(p, len); + + crc_lsb = (char) (csum16 & 0xff); + crc_msb = (char) (csum16 >> 8); + + if (spd->mod_section.uc[126] != crc_lsb || + spd->mod_section.uc[127] != crc_msb) { + printf("SPD checksum unexpected.\n" + "Checksum lsb in SPD = %02X, computed SPD = %02X\n" + "Checksum msb in SPD = %02X, computed SPD = %02X\n", + spd->mod_section.uc[126], + crc_lsb, spd->mod_section.uc[127], + crc_msb); + return 1; + } + + return 0; +} diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile index 265204f3119..df66c07230f 100644 --- a/drivers/ddr/fsl/Makefile +++ b/drivers/ddr/fsl/Makefile @@ -1,19 +1,20 @@ # -# Copyright 2008-2011 Freescale Semiconductor, Inc. +# Copyright 2008-2014 Freescale Semiconductor, Inc. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License # Version 2 as published by the Free Software Foundation. # -obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \ - lc_common_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \ + lc_common_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \ + lc_common_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \ + lc_common_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR4) += main.o util.o ctrl_regs.o options.o \ + lc_common_dimm_params.o -obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \ - lc_common_dimm_params.o - -obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \ - lc_common_dimm_params.o ifdef CONFIG_DDR_SPD SPD := y endif @@ -24,6 +25,7 @@ ifdef SPD obj-$(CONFIG_SYS_FSL_DDR1) += ddr1_dimm_params.o obj-$(CONFIG_SYS_FSL_DDR2) += ddr2_dimm_params.o obj-$(CONFIG_SYS_FSL_DDR3) += ddr3_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR4) += ddr4_dimm_params.o endif obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o @@ -32,3 +34,4 @@ obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o +obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 0882932b070..d01eea05f37 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2012 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,20 +17,6 @@ #include #include -#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR - -static u32 fsl_ddr_get_version(void) -{ - struct ccsr_ddr __iomem *ddr; - u32 ver_major_minor_errata; - - ddr = (void *)_DDR_ADDR; - ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; - ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; - - return ver_major_minor_errata; -} - unsigned int picos_to_mclk(unsigned int picos); /* @@ -81,6 +67,39 @@ static inline int fsl_ddr_get_rtt(void) return rtt; } +#ifdef CONFIG_SYS_FSL_DDR4 +/* + * compute CAS write latency according to DDR4 spec + * CWL = 9 for <= 1600MT/s + * 10 for <= 1866MT/s + * 11 for <= 2133MT/s + * 12 for <= 2400MT/s + * 14 for <= 2667MT/s + * 16 for <= 2933MT/s + * 18 for higher + */ +static inline unsigned int compute_cas_write_latency(void) +{ + unsigned int cwl; + const unsigned int mclk_ps = get_memory_clk_period_ps(); + if (mclk_ps >= 1250) + cwl = 9; + else if (mclk_ps >= 1070) + cwl = 10; + else if (mclk_ps >= 935) + cwl = 11; + else if (mclk_ps >= 833) + cwl = 12; + else if (mclk_ps >= 750) + cwl = 14; + else if (mclk_ps >= 681) + cwl = 16; + else + cwl = 18; + + return cwl; +} +#else /* * compute the CAS write latency according to DDR3 spec * CWL = 5 if tCK >= 2.5ns @@ -119,6 +138,7 @@ static inline unsigned int compute_cas_write_latency(void) } return cwl; } +#endif /* Chip Select Configuration (CSn_CONFIG) */ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, @@ -135,6 +155,11 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ int go_config = 0; +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */ +#else + unsigned int n_banks_per_sdram_device; +#endif /* Compute CS_CONFIG only for existing ranks of each DIMM. */ switch (i) { @@ -178,14 +203,18 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, break; } if (go_config) { - unsigned int n_banks_per_sdram_device; cs_n_en = 1; ap_n_en = popts->cs_local_opts[i].auto_precharge; odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; +#ifdef CONFIG_SYS_FSL_DDR4 + ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits; + bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits; +#else n_banks_per_sdram_device = dimm_params[dimm_number].n_banks_per_sdram_device; ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; +#endif row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12; col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8; } @@ -203,6 +232,9 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, | ((ba_bits_cs_n & 0x3) << 14) | ((row_bits_cs_n & 0x7) << 8) +#ifdef CONFIG_SYS_FSL_DDR4 + | ((bg_bits_cs_n & 0x3) << 4) +#endif | ((col_bits_cs_n & 0x7) << 0) ); debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); @@ -262,11 +294,23 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, /* Precharge powerdown exit timing (tXP). */ unsigned char pre_pd_exit_mclk; /* ODT powerdown exit timing (tAXPD). */ - unsigned char taxpd_mclk; + unsigned char taxpd_mclk = 0; /* Mode register set cycle time (tMRD). */ unsigned char tmrd_mclk; -#ifdef CONFIG_SYS_FSL_DDR3 +#ifdef CONFIG_SYS_FSL_DDR4 + /* tXP=max(4nCK, 6ns) */ + int txp = max((get_memory_clk_period_ps() * 4), 6000); /* unit=ps */ + trwt_mclk = 2; + twrt_mclk = 1; + act_pd_exit_mclk = picos_to_mclk(txp); + pre_pd_exit_mclk = act_pd_exit_mclk; + /* + * MRS_CYC = max(tMRD, tMOD) + * tMRD = 8nCK, tMOD = max(24nCK, 15ns) + */ + tmrd_mclk = max(24, picos_to_mclk(15000)); +#elif defined(CONFIG_SYS_FSL_DDR3) /* * (tXARD and tXARDS). Empirical? * The DDR3 spec has not tXARD, @@ -275,7 +319,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, * spec has not the tAXPD, we use * tAXPD=1, need design to confirm. */ - int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ + int txp = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ unsigned int data_rate = get_ddr_freq(0); tmrd_mclk = 4; /* set the turnaround time */ @@ -300,7 +344,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, taxpd_mclk = 1; } else { /* act_pd_exit_mclk = tXARD, see above */ - act_pd_exit_mclk = picos_to_mclk(tXP); + act_pd_exit_mclk = picos_to_mclk(txp); /* Mode register MR0[A12] is '1' - fast exit */ pre_pd_exit_mclk = act_pd_exit_mclk; taxpd_mclk = 1; @@ -364,8 +408,12 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4; ext_caslat = (2 * cas_latency - 1) >> 4; ext_add_lat = additive_latency >> 4; +#ifdef CONFIG_SYS_FSL_DDR4 + ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4; +#else ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4; /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ +#endif ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) + (popts->otf_burst_chop_en ? 2 : 0)) >> 4; @@ -404,9 +452,19 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, unsigned char acttoact_mclk; /* Last write data pair to read command issue interval (tWTR) */ unsigned char wrtord_mclk; +#ifdef CONFIG_SYS_FSL_DDR4 + /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */ + static const u8 wrrec_table[] = { + 10, 10, 10, 10, 10, + 10, 10, 10, 10, 10, + 12, 12, 14, 14, 16, + 16, 18, 18, 20, 20, + 24, 24, 24, 24}; +#else /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ static const u8 wrrec_table[] = { 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; +#endif pretoact_mclk = picos_to_mclk(common_dimm->trp_ps); acttopre_mclk = picos_to_mclk(common_dimm->tras_ps); @@ -438,20 +496,34 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, * we need set extend bit for it at * TIMING_CFG_3[EXT_CASLAT] */ - caslat_ctrl = 2 * cas_latency - 1; + if (fsl_ddr_get_version() <= 0x40400) + caslat_ctrl = 2 * cas_latency - 1; + else + caslat_ctrl = (cas_latency - 1) << 1; #endif +#ifdef CONFIG_SYS_FSL_DDR4 + refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8; + wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); + acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4); + wrtord_mclk = max(2, picos_to_mclk(2500)); + if (wrrec_mclk > 24) + printf("Error: WRREC doesn't support more than 24 clocks\n"); + else + wrrec_mclk = wrrec_table[wrrec_mclk - 1]; +#else refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8; wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); - + acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); + wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); if (wrrec_mclk > 16) printf("Error: WRREC doesn't support more than 16 clocks\n"); else wrrec_mclk = wrrec_table[wrrec_mclk - 1]; +#endif if (popts->otf_burst_chop_en) wrrec_mclk += 2; - acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); /* * JEDEC has min requirement for tRRD */ @@ -459,7 +531,6 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, if (acttoact_mclk < 4) acttoact_mclk = 4; #endif - wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); /* * JEDEC has some min requirements for tWTR */ @@ -526,14 +597,18 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, wr_lat = compute_cas_write_latency(); #endif +#ifdef CONFIG_SYS_FSL_DDR4 + rd_to_pre = picos_to_mclk(7500); +#else rd_to_pre = picos_to_mclk(common_dimm->trtp_ps); +#endif /* * JEDEC has some min requirements for tRTP */ #if defined(CONFIG_SYS_FSL_DDR2) if (rd_to_pre < 2) rd_to_pre = 2; -#elif defined(CONFIG_SYS_FSL_DDR3) +#elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) if (rd_to_pre < 4) rd_to_pre = 4; #endif @@ -541,13 +616,20 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, rd_to_pre += 2; /* according to UM */ wr_data_delay = popts->write_data_delay; +#ifdef CONFIG_SYS_FSL_DDR4 + cpo = 0; + cke_pls = max(3, picos_to_mclk(5000)); +#else cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps); +#endif + four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps); ddr->timing_cfg_2 = (0 | ((add_lat_mclk & 0xf) << 28) | ((cpo & 0x1f) << 23) | ((wr_lat & 0xf) << 19) + | ((wr_lat & 0x10) << 14) | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) | ((cke_pls & 0x7) << 6) @@ -640,7 +722,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, * we must clear it when use the on-the-fly mode, * must set it when use the 32-bits bus mode. */ - if (sdram_type == SDRAM_TYPE_DDR3) { + if ((sdram_type == SDRAM_TYPE_DDR3) || + (sdram_type == SDRAM_TYPE_DDR4)) { if (popts->burst_length == DDR_BL8) eight_be = 1; if (popts->burst_length == DDR_OTF) @@ -682,8 +765,6 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, { unsigned int frc_sr = 0; /* Force self refresh */ unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ - unsigned int dll_rst_dis; /* DLL reset disable */ - unsigned int dqs_cfg; /* DQS configuration */ unsigned int odt_cfg = 0; /* ODT configuration */ unsigned int num_pr; /* Number of posted refreshes */ unsigned int slow = 0; /* DDR will be run less than 1250 */ @@ -695,9 +776,12 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, unsigned int md_en = 0; /* Mirrored DIMM Enable */ unsigned int qd_en = 0; /* quad-rank DIMM Enable */ int i; +#ifndef CONFIG_SYS_FSL_DDR4 + unsigned int dll_rst_dis = 1; /* DLL reset disable */ + unsigned int dqs_cfg; /* DQS configuration */ - dll_rst_dis = 1; /* Make this configurable */ dqs_cfg = popts->dqs_config; +#endif for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (popts->cs_local_opts[i].odt_rd_cfg || popts->cs_local_opts[i].odt_wr_cfg) { @@ -715,7 +799,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, * * ({EXT_REFREC || REFREC} + 8 + 2)]} * << DDR_SDRAM_INTERVAL[REFINT] */ -#if defined(CONFIG_SYS_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) obc_cfg = popts->otf_burst_chop_en; #else obc_cfg = 0; @@ -744,15 +828,17 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, d_init = 0; #endif -#if defined(CONFIG_SYS_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) md_en = popts->mirrored_dimm; #endif qd_en = popts->quad_rank_present ? 1 : 0; ddr->ddr_sdram_cfg_2 = (0 | ((frc_sr & 0x1) << 31) | ((sr_ie & 0x1) << 30) +#ifndef CONFIG_SYS_FSL_DDR4 | ((dll_rst_dis & 0x1) << 29) | ((dqs_cfg & 0x3) << 26) +#endif | ((odt_cfg & 0x3) << 21) | ((num_pr & 0xf) << 12) | ((slow & 1) << 11) @@ -768,6 +854,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); } +#ifdef CONFIG_SYS_FSL_DDR4 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, @@ -776,8 +863,93 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, { unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ + int i; + unsigned int wr_crc = 0; /* Disable */ + unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ + unsigned int srt = 0; /* self-refresh temerature, normal range */ + unsigned int cwl = compute_cas_write_latency() - 9; + unsigned int mpr = 0; /* serial */ + unsigned int wc_lat; + const unsigned int mclk_ps = get_memory_clk_period_ps(); -#if defined(CONFIG_SYS_FSL_DDR3) + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + else + rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; + + if (common_dimm->extended_op_srt) + srt = common_dimm->extended_op_srt; + + esdmode2 = (0 + | ((wr_crc & 0x1) << 12) + | ((rtt_wr & 0x3) << 9) + | ((srt & 0x3) << 6) + | ((cwl & 0x7) << 3)); + + if (mclk_ps >= 1250) + wc_lat = 0; + else if (mclk_ps >= 833) + wc_lat = 1; + else + wc_lat = 2; + + esdmode3 = (0 + | ((mpr & 0x3) << 11) + | ((wc_lat & 0x3) << 9)); + + ddr->ddr_sdram_mode_2 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); + + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + else + rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; + + esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ + esdmode2 |= (rtt_wr & 0x3) << 9; + switch (i) { + case 1: + ddr->ddr_sdram_mode_4 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_6 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_8 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", + ddr->ddr_sdram_mode_4); + debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", + ddr->ddr_sdram_mode_6); + debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", + ddr->ddr_sdram_mode_8); + } +} +#elif defined(CONFIG_SYS_FSL_DDR3) +/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ +static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + const unsigned int unq_mrs_en) +{ + unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ + unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ int i; unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ unsigned int srt = 0; /* self-refresh temerature, normal range */ @@ -799,14 +971,12 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, | ((asr & 0x1) << 6) | ((cwl & 0x7) << 3) | ((pasr & 0x7) << 0)); -#endif ddr->ddr_sdram_mode_2 = (0 | ((esdmode2 & 0xFFFF) << 16) | ((esdmode3 & 0xFFFF) << 0) ); debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); -#ifdef CONFIG_SYS_FSL_DDR3 if (unq_mrs_en) { /* unique mode registers are supported */ for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (popts->rtt_override) @@ -844,9 +1014,128 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", ddr->ddr_sdram_mode_8); } +} + +#else /* for DDR2 and DDR1 */ +/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ +static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + const unsigned int unq_mrs_en) +{ + unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ + unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ + + ddr->ddr_sdram_mode_2 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); +} #endif + +#ifdef CONFIG_SYS_FSL_DDR4 +/* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */ +static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + const unsigned int unq_mrs_en) +{ + int i; + unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */ + unsigned short esdmode5; /* Extended SDRAM mode 5 */ + + esdmode5 = 0x00000400; /* Data mask enabled */ + + ddr->ddr_sdram_mode_9 = (0 + | ((esdmode4 & 0xffff) << 16) + | ((esdmode5 & 0xffff) << 0) + ); + debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9); + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + switch (i) { + case 1: + ddr->ddr_sdram_mode_11 = (0 + | ((esdmode4 & 0xFFFF) << 16) + | ((esdmode5 & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_13 = (0 + | ((esdmode4 & 0xFFFF) << 16) + | ((esdmode5 & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_15 = (0 + | ((esdmode4 & 0xFFFF) << 16) + | ((esdmode5 & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n", + ddr->ddr_sdram_mode_11); + debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n", + ddr->ddr_sdram_mode_13); + debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n", + ddr->ddr_sdram_mode_15); + } +} + +/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */ +static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + const unsigned int unq_mrs_en) +{ + int i; + unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */ + unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */ + unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps); + + esdmode6 = ((tccdl_min - 4) & 0x7) << 10; + + ddr->ddr_sdram_mode_10 = (0 + | ((esdmode6 & 0xffff) << 16) + | ((esdmode7 & 0xffff) << 0) + ); + debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10); + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + switch (i) { + case 1: + ddr->ddr_sdram_mode_12 = (0 + | ((esdmode6 & 0xFFFF) << 16) + | ((esdmode7 & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_14 = (0 + | ((esdmode6 & 0xFFFF) << 16) + | ((esdmode7 & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_16 = (0 + | ((esdmode6 & 0xFFFF) << 16) + | ((esdmode7 & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n", + ddr->ddr_sdram_mode_12); + debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n", + ddr->ddr_sdram_mode_14); + debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n", + ddr->ddr_sdram_mode_16); + } } +#endif + /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, @@ -867,7 +1156,7 @@ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); } -#if defined(CONFIG_SYS_FSL_DDR3) +#ifdef CONFIG_SYS_FSL_DDR4 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, @@ -876,6 +1165,177 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, unsigned int additive_latency, const unsigned int unq_mrs_en) { + int i; + unsigned short esdmode; /* Extended SDRAM mode */ + unsigned short sdmode; /* SDRAM mode */ + + /* Mode Register - MR1 */ + unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ + unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ + unsigned int rtt; + unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ + unsigned int al = 0; /* Posted CAS# additive latency (AL) */ + unsigned int dic = 0; /* Output driver impedance, 40ohm */ + unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal), + 0=Disable (Test/Debug) */ + + /* Mode Register - MR0 */ + unsigned int wr = 0; /* Write Recovery */ + unsigned int dll_rst; /* DLL Reset */ + unsigned int mode; /* Normal=0 or Test=1 */ + unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ + /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ + unsigned int bt; + unsigned int bl; /* BL: Burst Length */ + + unsigned int wr_mclk; + /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */ + static const u8 wr_table[] = { + 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6}; + /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */ + static const u8 cas_latency_table[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, + 9, 9, 10, 10, 11, 11}; + + if (popts->rtt_override) + rtt = popts->rtt_override_value; + else + rtt = popts->cs_local_opts[0].odt_rtt_norm; + + if (additive_latency == (cas_latency - 1)) + al = 1; + if (additive_latency == (cas_latency - 2)) + al = 2; + + if (popts->quad_rank_present) + dic = 1; /* output driver impedance 240/7 ohm */ + + /* + * The esdmode value will also be used for writing + * MR1 during write leveling for DDR3, although the + * bits specifically related to the write leveling + * scheme will be handled automatically by the DDR + * controller. so we set the wrlvl_en = 0 here. + */ + esdmode = (0 + | ((qoff & 0x1) << 12) + | ((tdqs_en & 0x1) << 11) + | ((rtt & 0x7) << 8) + | ((wrlvl_en & 0x1) << 7) + | ((al & 0x3) << 3) + | ((dic & 0x3) << 1) /* DIC field is split */ + | ((dll_en & 0x1) << 0) + ); + + /* + * DLL control for precharge PD + * 0=slow exit DLL off (tXPDLL) + * 1=fast exit DLL on (tXP) + */ + + wr_mclk = picos_to_mclk(common_dimm->twr_ps); + if (wr_mclk <= 24) { + wr = wr_table[wr_mclk - 10]; + } else { + printf("Error: unsupported write recovery for mode register wr_mclk = %d\n", + wr_mclk); + } + + dll_rst = 0; /* dll no reset */ + mode = 0; /* normal mode */ + + /* look up table to get the cas latency bits */ + if (cas_latency >= 9 && cas_latency <= 24) + caslat = cas_latency_table[cas_latency - 9]; + else + printf("Error: unsupported cas latency for mode register\n"); + + bt = 0; /* Nibble sequential */ + + switch (popts->burst_length) { + case DDR_BL8: + bl = 0; + break; + case DDR_OTF: + bl = 1; + break; + case DDR_BC4: + bl = 2; + break; + default: + printf("Error: invalid burst length of %u specified. ", + popts->burst_length); + puts("Defaulting to on-the-fly BC4 or BL8 beats.\n"); + bl = 1; + break; + } + + sdmode = (0 + | ((wr & 0x7) << 9) + | ((dll_rst & 0x1) << 8) + | ((mode & 0x1) << 7) + | (((caslat >> 1) & 0x7) << 4) + | ((bt & 0x1) << 3) + | ((caslat & 1) << 2) + | ((bl & 0x3) << 0) + ); + + ddr->ddr_sdram_mode = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + + debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); + + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (popts->rtt_override) + rtt = popts->rtt_override_value; + else + rtt = popts->cs_local_opts[i].odt_rtt_norm; + + esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */ + esdmode |= (rtt & 0x7) << 8; + switch (i) { + case 1: + ddr->ddr_sdram_mode_3 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_5 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_7 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", + ddr->ddr_sdram_mode_3); + debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", + ddr->ddr_sdram_mode_5); + debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", + ddr->ddr_sdram_mode_5); + } +} + +#elif defined(CONFIG_SYS_FSL_DDR3) +/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ +static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency, + const unsigned int unq_mrs_en) +{ + int i; unsigned short esdmode; /* Extended SDRAM mode */ unsigned short sdmode; /* SDRAM mode */ @@ -907,9 +1367,6 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, */ static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0}; - const unsigned int mclk_ps = get_memory_clk_period_ps(); - int i; - if (popts->rtt_override) rtt = popts->rtt_override_value; else @@ -950,7 +1407,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, */ dll_on = 1; - wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps; + wr_mclk = picos_to_mclk(common_dimm->twr_ps); if (wr_mclk <= 16) { wr = wr_table[wr_mclk - 5]; } else { @@ -1109,9 +1566,6 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, unsigned int bt; unsigned int bl; /* BL: Burst Length */ -#if defined(CONFIG_SYS_FSL_DDR2) - const unsigned int mclk_ps = get_memory_clk_period_ps(); -#endif dqs_en = !popts->dqs_config; rtt = fsl_ddr_get_rtt(); @@ -1141,7 +1595,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_SYS_FSL_DDR1) wr = 0; /* Historical */ #elif defined(CONFIG_SYS_FSL_DDR2) - wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1; + wr = picos_to_mclk(common_dimm->twr_ps); #endif dll_res = 0; mode = 0; @@ -1255,7 +1709,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ -#if defined(CONFIG_SYS_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) if (popts->burst_length == DDR_BL8) { /* We set BL/2 for fixed BL8 */ rrt = 0; /* BL/2 clocks */ @@ -1265,6 +1719,11 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, rrt = 2; /* BL/2 + 2 clocks */ wwt = 2; /* BL/2 + 2 clocks */ } +#endif + +#ifdef CONFIG_SYS_FSL_DDR4 + dll_lock = 2; /* tDLLK = 1024 clocks */ +#elif defined(CONFIG_SYS_FSL_DDR3) dll_lock = 1; /* tDLLK = 512 clocks from spec */ #endif ddr->timing_cfg_4 = (0 @@ -1285,9 +1744,12 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) unsigned int wodt_on = 0; /* Write to ODT on */ unsigned int wodt_off = 0; /* Write to ODT off */ -#if defined(CONFIG_SYS_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + + ((ddr->timing_cfg_2 & 0x00040000) >> 14); /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */ - rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1; + if (cas_latency >= wr_lat) + rodt_on = cas_latency - wr_lat + 1; rodt_off = 4; /* 4 clocks */ wodt_on = 1; /* 1 clocks */ wodt_off = 4; /* 4 clocks */ @@ -1302,6 +1764,164 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); } +#ifdef CONFIG_SYS_FSL_DDR4 +static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int hs_caslat = 0; + unsigned int hs_wrlat = 0; + unsigned int hs_wrrec = 0; + unsigned int hs_clkadj = 0; + unsigned int hs_wrlvl_start = 0; + + ddr->timing_cfg_6 = (0 + | ((hs_caslat & 0x1f) << 24) + | ((hs_wrlat & 0x1f) << 19) + | ((hs_wrrec & 0x1f) << 12) + | ((hs_clkadj & 0x1f) << 6) + | ((hs_wrlvl_start & 0x1f) << 0) + ); + debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); +} + +static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm) +{ + unsigned int txpr, tcksre, tcksrx; + unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd; + + txpr = max(5, picos_to_mclk(common_dimm->trfc1_ps + 10000)); + tcksre = max(5, picos_to_mclk(10000)); + tcksrx = max(5, picos_to_mclk(10000)); + par_lat = 0; + cs_to_cmd = 0; + + if (txpr <= 200) + cke_rst = 0; + else if (txpr <= 256) + cke_rst = 1; + else if (txpr <= 512) + cke_rst = 2; + else + cke_rst = 3; + + if (tcksre <= 19) + cksre = tcksre - 5; + else + cksre = 15; + + if (tcksrx <= 19) + cksrx = tcksrx - 5; + else + cksrx = 15; + + ddr->timing_cfg_7 = (0 + | ((cke_rst & 0x3) << 28) + | ((cksre & 0xf) << 24) + | ((cksrx & 0xf) << 20) + | ((par_lat & 0xf) << 16) + | ((cs_to_cmd & 0xf) << 4) + ); + debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); +} + +static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency) +{ + unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg; + unsigned int acttoact_bg, wrtord_bg, pre_all_rec; + unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps); + unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + + ((ddr->timing_cfg_2 & 0x00040000) >> 14); + + rwt_bg = cas_latency + 2 + 4 - wr_lat; + if (rwt_bg < tccdl) + rwt_bg = tccdl - rwt_bg; + else + rwt_bg = 0; + + wrt_bg = wr_lat + 4 + 1 - cas_latency; + if (wrt_bg < tccdl) + wrt_bg = tccdl - wrt_bg; + else + wrt_bg = 0; + + if (popts->burst_length == DDR_BL8) { + rrt_bg = tccdl - 4; + wwt_bg = tccdl - 4; + } else { + rrt_bg = tccdl - 2; + wwt_bg = tccdl - 4; + } + + acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps); + wrtord_bg = max(4, picos_to_mclk(7500)); + pre_all_rec = 0; + + ddr->timing_cfg_8 = (0 + | ((rwt_bg & 0xf) << 28) + | ((wrt_bg & 0xf) << 24) + | ((rrt_bg & 0xf) << 20) + | ((wwt_bg & 0xf) << 16) + | ((acttoact_bg & 0xf) << 12) + | ((wrtord_bg & 0xf) << 8) + | ((pre_all_rec & 0x1f) << 0) + ); + + debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8); +} + +static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr) +{ + ddr->timing_cfg_9 = 0; + debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); +} + +static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr, + const dimm_params_t *dimm_params) +{ + ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) | + ((dimm_params->dq_mapping[1] & 0x3F) << 20) | + ((dimm_params->dq_mapping[2] & 0x3F) << 14) | + ((dimm_params->dq_mapping[3] & 0x3F) << 8) | + ((dimm_params->dq_mapping[4] & 0x3F) << 2); + + ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) | + ((dimm_params->dq_mapping[6] & 0x3F) << 20) | + ((dimm_params->dq_mapping[7] & 0x3F) << 14) | + ((dimm_params->dq_mapping[10] & 0x3F) << 8) | + ((dimm_params->dq_mapping[11] & 0x3F) << 2); + + ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) | + ((dimm_params->dq_mapping[13] & 0x3F) << 20) | + ((dimm_params->dq_mapping[14] & 0x3F) << 14) | + ((dimm_params->dq_mapping[15] & 0x3F) << 8) | + ((dimm_params->dq_mapping[16] & 0x3F) << 2); + + ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) | + ((dimm_params->dq_mapping[8] & 0x3F) << 20) | + ((dimm_params->dq_mapping[9] & 0x3F) << 14) | + dimm_params->dq_mapping_ors; + + debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0); + debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1); + debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2); + debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3); +} +static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) +{ + int rd_pre; + + rd_pre = popts->quad_rank_present ? 1 : 0; + + ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16; + + debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3); +} +#endif /* CONFIG_SYS_FSL_DDR4 */ + /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) { @@ -1310,11 +1930,21 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) unsigned int zqoper = 0; /* Normal Operation Short Calibration Time (tZQCS) */ unsigned int zqcs = 0; +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int zqcs_init; +#endif if (zq_en) { +#ifdef CONFIG_SYS_FSL_DDR4 + zqinit = 10; /* 1024 clocks */ + zqoper = 9; /* 512 clocks */ + zqcs = 7; /* 128 clocks */ + zqcs_init = 5; /* 1024 refresh sequences */ +#else zqinit = 9; /* 512 clocks */ zqoper = 8; /* 256 clocks */ zqcs = 6; /* 64 clocks */ +#endif } ddr->ddr_zq_cntl = (0 @@ -1322,6 +1952,9 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) | ((zqinit & 0xF) << 24) | ((zqoper & 0xF) << 16) | ((zqcs & 0xF) << 8) +#ifdef CONFIG_SYS_FSL_DDR4 + | ((zqcs_init & 0xF) << 0) +#endif ); debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); } @@ -1478,7 +2111,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, */ cas_latency = (popts->cas_latency_override) ? popts->cas_latency_override_value - : common_dimm->lowest_common_SPD_caslat; + : common_dimm->lowest_common_spd_caslat; additive_latency = (popts->additive_latency_override) ? popts->additive_latency_override_value @@ -1639,6 +2272,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_sdram_mode(ddr, popts, common_dimm, cas_latency, additive_latency, unq_mrs_en); set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en); +#ifdef CONFIG_SYS_FSL_DDR4 + set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en); + set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en); +#endif set_ddr_sdram_interval(ddr, popts, common_dimm); set_ddr_data_init(ddr); set_ddr_sdram_clk_cntl(ddr, popts); @@ -1646,6 +2283,14 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_init_ext_addr(ddr); set_timing_cfg_4(ddr, popts); set_timing_cfg_5(ddr, cas_latency); +#ifdef CONFIG_SYS_FSL_DDR4 + set_ddr_sdram_cfg_3(ddr, popts); + set_timing_cfg_6(ddr); + set_timing_cfg_7(ddr, common_dimm); + set_timing_cfg_8(ddr, popts, common_dimm, cas_latency); + set_timing_cfg_9(ddr); + set_ddr_dq_mapping(ddr, dimm_params); +#endif set_ddr_zq_cntl(ddr, zq_en); set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c new file mode 100644 index 00000000000..4745b7fb1bf --- /dev/null +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -0,0 +1,300 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * calculate the organization and timing parameter + * from ddr3 spd, please refer to the spec + * JEDEC standard No.21-C 4_01_02_12R23A.pdf + * + * + */ + +#include +#include + +#include + +/* + * Calculate the Density of each Physical Rank. + * Returned size is in bytes. + * + * Total DIMM size = + * sdram capacity(bit) / 8 * primary bus width / sdram width + * * Logical Ranks per DIMM + * + * where: sdram capacity = spd byte4[3:0] + * primary bus width = spd byte13[2:0] + * sdram width = spd byte12[2:0] + * Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP + * spd byte12{5:3] * spd byte6[6:4] for 3DS + * + * To simplify each rank size = total DIMM size / Number of Package Ranks + * where Number of Package Ranks = spd byte12[5:3] + * + * SPD byte4 - sdram density and banks + * bit[3:0] size(bit) size(byte) + * 0000 256Mb 32MB + * 0001 512Mb 64MB + * 0010 1Gb 128MB + * 0011 2Gb 256MB + * 0100 4Gb 512MB + * 0101 8Gb 1GB + * 0110 16Gb 2GB + * 0111 32Gb 4GB + * + * SPD byte13 - module memory bus width + * bit[2:0] primary bus width + * 000 8bits + * 001 16bits + * 010 32bits + * 011 64bits + * + * SPD byte12 - module organization + * bit[2:0] sdram device width + * 000 4bits + * 001 8bits + * 010 16bits + * 011 32bits + * + * SPD byte12 - module organization + * bit[5:3] number of package ranks per DIMM + * 000 1 + * 001 2 + * 010 3 + * 011 4 + * + * SPD byte6 - SDRAM package type + * bit[6:4] Die count + * 000 1 + * 001 2 + * 010 3 + * 011 4 + * 100 5 + * 101 6 + * 110 7 + * 111 8 + * + * SPD byte6 - SRAM package type + * bit[1:0] Signal loading + * 00 Not specified + * 01 Multi load stack + * 10 Sigle load stack (3DS) + * 11 Reserved + */ +static unsigned long long +compute_ranksize(const struct ddr4_spd_eeprom_s *spd) +{ + unsigned long long bsize; + + int nbit_sdram_cap_bsize = 0; + int nbit_primary_bus_width = 0; + int nbit_sdram_width = 0; + int die_count = 0; + bool package_3ds; + + if ((spd->density_banks & 0xf) <= 7) + nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; + if ((spd->bus_width & 0x7) < 4) + nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; + if ((spd->organization & 0x7) < 4) + nbit_sdram_width = (spd->organization & 0x7) + 2; + package_3ds = (spd->package_type & 0x3) == 0x2; + if (package_3ds) + die_count = (spd->package_type >> 4) & 0x7; + + bsize = 1ULL << (nbit_sdram_cap_bsize - 3 + + nbit_primary_bus_width - nbit_sdram_width + + die_count); + + debug("DDR: DDR III rank density = 0x%16llx\n", bsize); + + return bsize; +} + +#define spd_to_ps(mtb, ftb) \ + (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10) +/* + * ddr_compute_dimm_parameters for DDR3 SPD + * + * Compute DIMM parameters based upon the SPD information in spd. + * Writes the results to the dimm_params_t structure pointed by pdimm. + * + */ +unsigned int +ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) +{ + unsigned int retval; + int i; + + if (spd->mem_type) { + if (spd->mem_type != SPD_MEMTYPE_DDR4) { + printf("DIMM %u: is not a DDR4 SPD.\n", dimm_number); + return 1; + } + } else { + memset(pdimm, 0, sizeof(dimm_params_t)); + return 1; + } + + retval = ddr4_spd_check(spd); + if (retval) { + printf("DIMM %u: failed checksum\n", dimm_number); + return 2; + } + + /* + * The part name in ASCII in the SPD EEPROM is not null terminated. + * Guarantee null termination here by presetting all bytes to 0 + * and copying the part name in ASCII from the SPD onto it + */ + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + if ((spd->info_size_crc & 0xF) > 2) + memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); + + /* DIMM organization parameters */ + pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1; + pdimm->rank_density = compute_ranksize(spd); + pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; + pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); + if ((spd->bus_width >> 3) & 0x3) + pdimm->ec_sdram_width = 8; + else + pdimm->ec_sdram_width = 0; + pdimm->data_width = pdimm->primary_sdram_width + + pdimm->ec_sdram_width; + pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); + + /* These are the types defined by the JEDEC DDR3 SPD spec */ + pdimm->mirrored_dimm = 0; + pdimm->registered_dimm = 0; + switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { + case DDR3_SPD_MODULETYPE_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; + break; + + case DDR3_SPD_MODULETYPE_UDIMM: + case DDR3_SPD_MODULETYPE_SO_DIMM: + /* Unbuffered DIMMs */ + if (spd->mod_section.unbuffered.addr_mapping & 0x1) + pdimm->mirrored_dimm = 1; + break; + + default: + printf("unknown module_type 0x%02X\n", spd->module_type); + return 1; + } + + /* SDRAM device parameters */ + pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; + pdimm->n_col_addr = (spd->addressing & 0x7) + 9; + pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3; + pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3; + + /* + * The SPD spec has not the ECC bit, + * We consider the DIMM as ECC capability + * when the extension bus exist + */ + if (pdimm->ec_sdram_width) + pdimm->edc_config = 0x02; + else + pdimm->edc_config = 0x00; + + /* + * The SPD spec has not the burst length byte + * but DDR4 spec has nature BL8 and BC4, + * BL8 -bit3, BC4 -bit2 + */ + pdimm->burst_lengths_bitmask = 0x0c; + pdimm->row_density = __ilog2(pdimm->rank_density); + + /* MTB - medium timebase + * The MTB in the SPD spec is 125ps, + * + * FTB - fine timebase + * use 1/10th of ps as our unit to avoid floating point + * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps + */ + if ((spd->timebases & 0xf) == 0x0) { + pdimm->mtb_ps = 125; + pdimm->ftb_10th_ps = 10; + + } else { + printf("Unknown Timebases\n"); + } + + /* sdram minimum cycle time */ + pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min); + + /* sdram max cycle time */ + pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max); + + /* + * CAS latency supported + * bit0 - CL7 + * bit4 - CL11 + * bit8 - CL15 + * bit12- CL19 + * bit16- CL23 + */ + pdimm->caslat_x = (spd->caslat_b1 << 7) | + (spd->caslat_b2 << 15) | + (spd->caslat_b3 << 23); + + BUG_ON(spd->caslat_b4 != 0); + + /* + * min CAS latency time + */ + pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min); + + /* + * min RAS to CAS delay time + */ + pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min); + + /* + * Min Row Precharge Delay Time + */ + pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min); + + /* min active to precharge delay time */ + pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) + + spd->tras_min_lsb) * pdimm->mtb_ps; + + /* min active to actice/refresh delay time */ + pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) + + spd->trc_min_lsb), spd->fine_trc_min); + /* Min Refresh Recovery Delay Time */ + pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) * + pdimm->mtb_ps; + pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) * + pdimm->mtb_ps; + pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) * + pdimm->mtb_ps; + /* min four active window delay time */ + pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) * + pdimm->mtb_ps; + + /* min row active to row active delay time, different bank group */ + pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min); + /* min row active to row active delay time, same bank group */ + pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min); + /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */ + pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min); + + /* + * Average periodic refresh interval + * tREFI = 7.8 us at normal temperature range + */ + pdimm->refresh_rate_ps = 7800000; + + for (i = 0; i < 18; i++) + pdimm->dq_mapping[i] = spd->mapping[i]; + + pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0; + + return 0; +} diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c new file mode 100644 index 00000000000..7cd878aeecb --- /dev/null +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -0,0 +1,234 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) +#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL +#endif + +/* + * regs has the to-be-set values for DDR controller registers + * ctrl_num is the DDR controller number + * step: 0 goes through the initialization in one pass + * 1 sets registers and returns before enabling controller + * 2 resumes from step 1 and continues to initialize + * Dividing the initialization to two steps to deassert DDR reset signal + * to comply with JEDEC specs for RDIMMs. + */ +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step) +{ + unsigned int i, bus_width; + struct ccsr_ddr __iomem *ddr; + u32 temp_sdram_cfg; + u32 total_gb_size_per_controller; + int timeout; + + switch (ctrl_num) { + case 0: + ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + break; +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) + case 1: + ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; + break; +#endif + default: + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); + return; + } + + if (step == 2) + goto step2; + + if (regs->ddr_eor) + ddr_out32(&ddr->eor, regs->ddr_eor); + + ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs0_config, regs->cs[i].config); + ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); + + } else if (i == 1) { + ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs1_config, regs->cs[i].config); + ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); + + } else if (i == 2) { + ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs2_config, regs->cs[i].config); + ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); + + } else if (i == 3) { + ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs3_config, regs->cs[i].config); + ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); + } + } + + ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); + ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); + ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); + ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); + ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); + ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); + ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); + ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); + ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); + ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); + ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + ddr_out32(&ddr->dq_map_0, regs->dq_map_0); + ddr_out32(&ddr->dq_map_1, regs->dq_map_1); + ddr_out32(&ddr->dq_map_2, regs->dq_map_2); + ddr_out32(&ddr->dq_map_3, regs->dq_map_3); + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); + ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); + ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); + ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); + ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); + ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); + ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); + ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); + ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); + ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); + ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); + ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); + ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); + ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); + ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); + ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); + ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); + ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); + ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); + ddr_out32(&ddr->init_addr, regs->ddr_init_addr); + ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); +#ifndef CONFIG_SYS_FSL_DDR_EMU + /* + * Skip these two registers if running on emulator + * because emulator doesn't have skew between bytes. + */ + + if (regs->ddr_wrlvl_cntl_2) + ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); + if (regs->ddr_wrlvl_cntl_3) + ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); +#endif + + ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); + ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); + ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); + ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); + ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); + ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); + ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); + ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); + ddr_out32(&ddr->err_disable, regs->err_disable); + ddr_out32(&ddr->err_int_en, regs->err_int_en); + for (i = 0; i < 32; i++) { + if (regs->debug[i]) { + debug("Write to debug_%d as %08x\n", + i+1, regs->debug[i]); + ddr_out32(&ddr->debug[i], regs->debug[i]); + } + } + + /* + * For RDIMMs, JEDEC spec requires clocks to be stable before reset is + * deasserted. Clocks start when any chip select is enabled and clock + * control register is set. Because all DDR components are connected to + * one reset signal, this needs to be done in two steps. Step 1 is to + * get the clocks started. Step 2 resumes after reset signal is + * deasserted. + */ + if (step == 1) { + udelay(200); + return; + } + +step2: + /* Set, but do not enable the memory */ + temp_sdram_cfg = regs->ddr_sdram_cfg; + temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); + ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); + + /* + * 500 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + * DDR2 need 200 us, and DDR3 need 500 us from spec, + * we choose the max, that is 500 us for all of case. + */ + udelay(500); + asm volatile("sync;isync"); + + /* Let the controller go */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; + ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + asm volatile("sync;isync"); + + total_gb_size_per_controller = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (!(regs->cs[i].config & 0x80000000)) + continue; + total_gb_size_per_controller += 1 << ( + ((regs->cs[i].config >> 14) & 0x3) + 2 + + ((regs->cs[i].config >> 8) & 0x7) + 12 + + ((regs->cs[i].config >> 4) & 0x3) + 0 + + ((regs->cs[i].config >> 0) & 0x7) + 8 + + 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - + 26); /* minus 26 (count of 64M) */ + } + if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ + total_gb_size_per_controller *= 3; + else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ + total_gb_size_per_controller <<= 1; + /* + * total memory / bus width = transactions needed + * transactions needed / data rate = seconds + * to add plenty of buffer, double the time + * For example, 2GB on 666MT/s 64-bit bus takes about 402ms + * Let's wait for 800ms + */ + bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) + >> SDRAM_CFG_DBW_SHIFT); + timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / + (get_ddr_freq(0) >> 20)) << 2; + total_gb_size_per_controller >>= 4; /* shift down to gb size */ + debug("total %d GB\n", total_gb_size_per_controller); + debug("Need to wait up to %d * 10ms\n", timeout); + + /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ + while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + (timeout >= 0)) { + udelay(10000); /* throttle polling rate */ + timeout--; + } + + if (timeout <= 0) + printf("Waiting for D_INIT timeout. Memory may not work.\n"); + +} diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index ebf3ed6f388..cfe1e1f55aa 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2012 Freescale Semiconductor, Inc. + * Copyright 2010-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -153,25 +153,38 @@ static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo, static const struct options_string options[] = { COMMON_TIMING(tckmin_x_ps), COMMON_TIMING(tckmax_ps), - COMMON_TIMING(tckmax_max_ps), + COMMON_TIMING(taamin_ps), COMMON_TIMING(trcd_ps), COMMON_TIMING(trp_ps), COMMON_TIMING(tras_ps), - COMMON_TIMING(twr_ps), + +#ifdef CONFIG_SYS_FSL_DDR4 + COMMON_TIMING(trfc1_ps), + COMMON_TIMING(trfc2_ps), + COMMON_TIMING(trfc4_ps), + COMMON_TIMING(trrds_ps), + COMMON_TIMING(trrdl_ps), + COMMON_TIMING(tccdl_ps), +#else COMMON_TIMING(twtr_ps), COMMON_TIMING(trfc_ps), COMMON_TIMING(trrd_ps), + COMMON_TIMING(trtp_ps), +#endif + COMMON_TIMING(twr_ps), COMMON_TIMING(trc_ps), COMMON_TIMING(refresh_rate_ps), + COMMON_TIMING(extended_op_srt), +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) COMMON_TIMING(tis_ps), COMMON_TIMING(tih_ps), COMMON_TIMING(tds_ps), COMMON_TIMING(tdh_ps), - COMMON_TIMING(trtp_ps), COMMON_TIMING(tdqsq_max_ps), COMMON_TIMING(tqhs_ps), +#endif COMMON_TIMING(ndimms_present), - COMMON_TIMING(lowest_common_SPD_caslat), + COMMON_TIMING(lowest_common_spd_caslat), COMMON_TIMING(highest_common_derated_caslat), COMMON_TIMING(additive_latency), COMMON_TIMING(all_dimms_burst_lengths_bitmask), @@ -211,7 +224,12 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, DIMM_PARM(n_row_addr), DIMM_PARM(n_col_addr), DIMM_PARM(edc_config), +#ifdef CONFIG_SYS_FSL_DDR4 + DIMM_PARM(bank_addr_bits), + DIMM_PARM(bank_group_bits), +#else DIMM_PARM(n_banks_per_sdram_device), +#endif DIMM_PARM(burst_lengths_bitmask), DIMM_PARM(row_density), @@ -229,20 +247,32 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, DIMM_PARM(trcd_ps), DIMM_PARM(trp_ps), DIMM_PARM(tras_ps), +#ifdef CONFIG_SYS_FSL_DDR4 + DIMM_PARM(trfc1_ps), + DIMM_PARM(trfc2_ps), + DIMM_PARM(trfc4_ps), + DIMM_PARM(trrds_ps), + DIMM_PARM(trrdl_ps), + DIMM_PARM(tccdl_ps), +#else DIMM_PARM(twr_ps), DIMM_PARM(twtr_ps), DIMM_PARM(trfc_ps), DIMM_PARM(trrd_ps), + DIMM_PARM(trtp_ps), +#endif DIMM_PARM(trc_ps), DIMM_PARM(refresh_rate_ps), + DIMM_PARM(extended_op_srt), +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) DIMM_PARM(tis_ps), DIMM_PARM(tih_ps), DIMM_PARM(tds_ps), DIMM_PARM(tdh_ps), - DIMM_PARM(trtp_ps), DIMM_PARM(tdqsq_max_ps), DIMM_PARM(tqhs_ps), +#endif DIMM_PARM(rank_density), DIMM_PARM(capacity), @@ -270,7 +300,12 @@ static void print_dimm_parameters(const dimm_params_t *pdimm) DIMM_PARM(n_row_addr), DIMM_PARM(n_col_addr), DIMM_PARM(edc_config), +#ifdef CONFIG_SYS_FSL_DDR4 + DIMM_PARM(bank_addr_bits), + DIMM_PARM(bank_group_bits), +#else DIMM_PARM(n_banks_per_sdram_device), +#endif DIMM_PARM(tckmin_x_ps), DIMM_PARM(tckmin_x_minus_1_ps), @@ -286,20 +321,31 @@ static void print_dimm_parameters(const dimm_params_t *pdimm) DIMM_PARM(trcd_ps), DIMM_PARM(trp_ps), DIMM_PARM(tras_ps), +#ifdef CONFIG_SYS_FSL_DDR4 + DIMM_PARM(trfc1_ps), + DIMM_PARM(trfc2_ps), + DIMM_PARM(trfc4_ps), + DIMM_PARM(trrds_ps), + DIMM_PARM(trrdl_ps), + DIMM_PARM(tccdl_ps), +#else DIMM_PARM(twr_ps), DIMM_PARM(twtr_ps), DIMM_PARM(trfc_ps), DIMM_PARM(trrd_ps), + DIMM_PARM(trtp_ps), +#endif DIMM_PARM(trc_ps), DIMM_PARM(refresh_rate_ps), +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) DIMM_PARM(tis_ps), DIMM_PARM(tih_ps), DIMM_PARM(tds_ps), DIMM_PARM(tdh_ps), - DIMM_PARM(trtp_ps), DIMM_PARM(tdqsq_max_ps), DIMM_PARM(tqhs_ps), +#endif }; static const unsigned int n_opts = ARRAY_SIZE(options); @@ -326,23 +372,36 @@ static void print_lowest_common_dimm_parameters( const common_timing_params_t *plcd_dimm_params) { static const struct options_string options[] = { - COMMON_TIMING(tckmax_max_ps), + COMMON_TIMING(taamin_ps), COMMON_TIMING(trcd_ps), COMMON_TIMING(trp_ps), COMMON_TIMING(tras_ps), - COMMON_TIMING(twr_ps), +#ifdef CONFIG_SYS_FSL_DDR4 + COMMON_TIMING(trfc1_ps), + COMMON_TIMING(trfc2_ps), + COMMON_TIMING(trfc4_ps), + COMMON_TIMING(trrds_ps), + COMMON_TIMING(trrdl_ps), + COMMON_TIMING(tccdl_ps), +#else COMMON_TIMING(twtr_ps), COMMON_TIMING(trfc_ps), COMMON_TIMING(trrd_ps), + COMMON_TIMING(trtp_ps), +#endif + COMMON_TIMING(twr_ps), COMMON_TIMING(trc_ps), COMMON_TIMING(refresh_rate_ps), + COMMON_TIMING(extended_op_srt), +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) COMMON_TIMING(tis_ps), + COMMON_TIMING(tih_ps), COMMON_TIMING(tds_ps), COMMON_TIMING(tdh_ps), - COMMON_TIMING(trtp_ps), COMMON_TIMING(tdqsq_max_ps), COMMON_TIMING(tqhs_ps), - COMMON_TIMING(lowest_common_SPD_caslat), +#endif + COMMON_TIMING(lowest_common_spd_caslat), COMMON_TIMING(highest_common_derated_caslat), COMMON_TIMING(additive_latency), COMMON_TIMING(ndimms_present), @@ -460,6 +519,9 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, CTRL_OPTIONS(tfaw_window_four_activates_ps), CTRL_OPTIONS(trwt_override), CTRL_OPTIONS(trwt), + CTRL_OPTIONS(rtt_override), + CTRL_OPTIONS(rtt_override_value), + CTRL_OPTIONS(rtt_wr_override_value), }; static const unsigned int n_opts = ARRAY_SIZE(options); @@ -505,6 +567,7 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) CFG_REGS(timing_cfg_2), CFG_REGS(ddr_sdram_cfg), CFG_REGS(ddr_sdram_cfg_2), + CFG_REGS(ddr_sdram_cfg_3), CFG_REGS(ddr_sdram_mode), CFG_REGS(ddr_sdram_mode_2), CFG_REGS(ddr_sdram_mode_3), @@ -513,6 +576,16 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) CFG_REGS(ddr_sdram_mode_6), CFG_REGS(ddr_sdram_mode_7), CFG_REGS(ddr_sdram_mode_8), +#ifdef CONFIG_SYS_FSL_DDR4 + CFG_REGS(ddr_sdram_mode_9), + CFG_REGS(ddr_sdram_mode_10), + CFG_REGS(ddr_sdram_mode_11), + CFG_REGS(ddr_sdram_mode_12), + CFG_REGS(ddr_sdram_mode_13), + CFG_REGS(ddr_sdram_mode_14), + CFG_REGS(ddr_sdram_mode_15), + CFG_REGS(ddr_sdram_mode_16), +#endif CFG_REGS(ddr_sdram_interval), CFG_REGS(ddr_data_init), CFG_REGS(ddr_sdram_clk_cntl), @@ -520,6 +593,12 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) CFG_REGS(ddr_init_ext_addr), CFG_REGS(timing_cfg_4), CFG_REGS(timing_cfg_5), +#ifdef CONFIG_SYS_FSL_DDR4 + CFG_REGS(timing_cfg_6), + CFG_REGS(timing_cfg_7), + CFG_REGS(timing_cfg_8), + CFG_REGS(timing_cfg_9), +#endif CFG_REGS(ddr_zq_cntl), CFG_REGS(ddr_wrlvl_cntl), CFG_REGS(ddr_wrlvl_cntl_2), @@ -529,6 +608,10 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) CFG_REGS(ddr_sdram_rcw_2), CFG_REGS(ddr_cdr1), CFG_REGS(ddr_cdr2), + CFG_REGS(dq_map_0), + CFG_REGS(dq_map_1), + CFG_REGS(dq_map_2), + CFG_REGS(dq_map_3), CFG_REGS(err_disable), CFG_REGS(err_int_en), CFG_REGS(ddr_eor), @@ -574,6 +657,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, CFG_REGS(timing_cfg_2), CFG_REGS(ddr_sdram_cfg), CFG_REGS(ddr_sdram_cfg_2), + CFG_REGS(ddr_sdram_cfg_3), CFG_REGS(ddr_sdram_mode), CFG_REGS(ddr_sdram_mode_2), CFG_REGS(ddr_sdram_mode_3), @@ -582,6 +666,16 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, CFG_REGS(ddr_sdram_mode_6), CFG_REGS(ddr_sdram_mode_7), CFG_REGS(ddr_sdram_mode_8), +#ifdef CONFIG_SYS_FSL_DDR4 + CFG_REGS(ddr_sdram_mode_9), + CFG_REGS(ddr_sdram_mode_10), + CFG_REGS(ddr_sdram_mode_11), + CFG_REGS(ddr_sdram_mode_12), + CFG_REGS(ddr_sdram_mode_13), + CFG_REGS(ddr_sdram_mode_14), + CFG_REGS(ddr_sdram_mode_15), + CFG_REGS(ddr_sdram_mode_16), +#endif CFG_REGS(ddr_sdram_interval), CFG_REGS(ddr_data_init), CFG_REGS(ddr_sdram_clk_cntl), @@ -589,6 +683,12 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, CFG_REGS(ddr_init_ext_addr), CFG_REGS(timing_cfg_4), CFG_REGS(timing_cfg_5), +#ifdef CONFIG_SYS_FSL_DDR4 + CFG_REGS(timing_cfg_6), + CFG_REGS(timing_cfg_7), + CFG_REGS(timing_cfg_8), + CFG_REGS(timing_cfg_9), +#endif CFG_REGS(ddr_zq_cntl), CFG_REGS(ddr_wrlvl_cntl), CFG_REGS(ddr_wrlvl_cntl_2), @@ -598,6 +698,10 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, CFG_REGS(ddr_sdram_rcw_2), CFG_REGS(ddr_cdr1), CFG_REGS(ddr_cdr2), + CFG_REGS(dq_map_0), + CFG_REGS(dq_map_1), + CFG_REGS(dq_map_2), + CFG_REGS(dq_map_3), CFG_REGS(err_disable), CFG_REGS(err_int_en), CFG_REGS(ddr_sdram_rcw_2), @@ -705,6 +809,9 @@ static void print_memctl_options(const memctl_options_t *popts) CTRL_OPTIONS(tfaw_window_four_activates_ps), CTRL_OPTIONS(trwt_override), CTRL_OPTIONS(trwt), + CTRL_OPTIONS(rtt_override), + CTRL_OPTIONS(rtt_override_value), + CTRL_OPTIONS(rtt_wr_override_value), }; static const unsigned int n_opts = ARRAY_SIZE(options); @@ -1245,6 +1352,266 @@ void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd) } #endif +#ifdef CONFIG_SYS_FSL_DDR4 +void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd) +{ + unsigned int i; + + /* General Section: Bytes 0-127 */ + +#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y); +#define PRINT_NNXXS(n0, n1, x0, x1, s) \ + printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); + + PRINT_NXS(0, spd->info_size_crc, + "info_size_crc bytes written into serial memory, CRC coverage"); + PRINT_NXS(1, spd->spd_rev, + "spd_rev SPD Revision"); + PRINT_NXS(2, spd->mem_type, + "mem_type Key Byte / DRAM Device Type"); + PRINT_NXS(3, spd->module_type, + "module_type Key Byte / Module Type"); + PRINT_NXS(4, spd->density_banks, + "density_banks SDRAM Density and Banks"); + PRINT_NXS(5, spd->addressing, + "addressing SDRAM Addressing"); + PRINT_NXS(6, spd->package_type, + "package_type Package type"); + PRINT_NXS(7, spd->opt_feature, + "opt_feature Optional features"); + PRINT_NXS(8, spd->thermal_ref, + "thermal_ref Thermal and Refresh options"); + PRINT_NXS(9, spd->oth_opt_features, + "oth_opt_features Other SDRAM optional features"); + PRINT_NXS(10, spd->res_10, + "res_10 Reserved"); + PRINT_NXS(11, spd->module_vdd, + "module_vdd Module Nominal Voltage, VDD"); + PRINT_NXS(12, spd->organization, + "organization Module Organization"); + PRINT_NXS(13, spd->bus_width, + "bus_width Module Memory Bus Width"); + PRINT_NXS(14, spd->therm_sensor, + "therm_sensor Module Thermal Sensor"); + PRINT_NXS(15, spd->ext_type, + "ext_type Extended module type"); + PRINT_NXS(16, spd->res_16, + "res_16 Reserved"); + PRINT_NXS(17, spd->timebases, + "timebases MTb and FTB"); + PRINT_NXS(18, spd->tck_min, + "tck_min tCKAVGmin"); + PRINT_NXS(19, spd->tck_max, + "tck_max TCKAVGmax"); + PRINT_NXS(20, spd->caslat_b1, + "caslat_b1 CAS latencies, 1st byte"); + PRINT_NXS(21, spd->caslat_b2, + "caslat_b2 CAS latencies, 2nd byte"); + PRINT_NXS(22, spd->caslat_b3, + "caslat_b3 CAS latencies, 3rd byte "); + PRINT_NXS(23, spd->caslat_b4, + "caslat_b4 CAS latencies, 4th byte"); + PRINT_NXS(24, spd->taa_min, + "taa_min Min CAS Latency Time"); + PRINT_NXS(25, spd->trcd_min, + "trcd_min Min RAS# to CAS# Delay Time"); + PRINT_NXS(26, spd->trp_min, + "trp_min Min Row Precharge Delay Time"); + PRINT_NXS(27, spd->tras_trc_ext, + "tras_trc_ext Upper Nibbles for tRAS and tRC"); + PRINT_NXS(28, spd->tras_min_lsb, + "tras_min_lsb tRASmin, lsb"); + PRINT_NXS(29, spd->trc_min_lsb, + "trc_min_lsb tRCmin, lsb"); + PRINT_NXS(30, spd->trfc1_min_lsb, + "trfc1_min_lsb Min Refresh Recovery Delay Time, LSB"); + PRINT_NXS(31, spd->trfc1_min_msb, + "trfc1_min_msb Min Refresh Recovery Delay Time, MSB "); + PRINT_NXS(32, spd->trfc2_min_lsb, + "trfc2_min_lsb Min Refresh Recovery Delay Time, LSB"); + PRINT_NXS(33, spd->trfc2_min_msb, + "trfc2_min_msb Min Refresh Recovery Delay Time, MSB"); + PRINT_NXS(34, spd->trfc4_min_lsb, + "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB"); + PRINT_NXS(35, spd->trfc4_min_msb, + "trfc4_min_msb Min Refresh Recovery Delay Time, MSB"); + PRINT_NXS(36, spd->tfaw_msb, + "tfaw_msb Upper Nibble for tFAW"); + PRINT_NXS(37, spd->tfaw_min, + "tfaw_min tFAW, lsb"); + PRINT_NXS(38, spd->trrds_min, + "trrds_min tRRD_Smin, MTB"); + PRINT_NXS(39, spd->trrdl_min, + "trrdl_min tRRD_Lmin, MTB"); + PRINT_NXS(40, spd->tccdl_min, + "tccdl_min tCCS_Lmin, MTB"); + + printf("%-3d-%3d: ", 41, 59); /* Reserved, General Section */ + for (i = 41; i <= 59; i++) + printf("%02x ", spd->res_41[i - 41]); + + puts("\n"); + printf("%-3d-%3d: ", 60, 77); + for (i = 60; i <= 77; i++) + printf("%02x ", spd->mapping[i - 60]); + puts(" mapping[] Connector to SDRAM bit map\n"); + + PRINT_NXS(117, spd->fine_tccdl_min, + "fine_tccdl_min Fine offset for tCCD_Lmin"); + PRINT_NXS(118, spd->fine_trrdl_min, + "fine_trrdl_min Fine offset for tRRD_Lmin"); + PRINT_NXS(119, spd->fine_trrds_min, + "fine_trrds_min Fine offset for tRRD_Smin"); + PRINT_NXS(120, spd->fine_trc_min, + "fine_trc_min Fine offset for tRCmin"); + PRINT_NXS(121, spd->fine_trp_min, + "fine_trp_min Fine offset for tRPmin"); + PRINT_NXS(122, spd->fine_trcd_min, + "fine_trcd_min Fine offset for tRCDmin"); + PRINT_NXS(123, spd->fine_taa_min, + "fine_taa_min Fine offset for tAAmin"); + PRINT_NXS(124, spd->fine_tck_max, + "fine_tck_max Fine offset for tCKAVGmax"); + PRINT_NXS(125, spd->fine_tck_min, + "fine_tck_min Fine offset for tCKAVGmin"); + + /* CRC: Bytes 126-127 */ + PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC"); + + switch (spd->module_type) { + case 0x02: /* UDIMM */ + case 0x03: /* SO-DIMM */ + PRINT_NXS(128, spd->mod_section.unbuffered.mod_height, + "mod_height (Unbuffered) Module Nominal Height"); + PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness, + "mod_thickness (Unbuffered) Module Maximum Thickness"); + PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card, + "ref_raw_card (Unbuffered) Reference Raw Card Used"); + PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping, + "addr_mapping (Unbuffered) Address mapping from Edge Connector to DRAM"); + PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0], + spd->mod_section.unbuffered.crc[1], " Module CRC"); + break; + case 0x01: /* RDIMM */ + PRINT_NXS(128, spd->mod_section.registered.mod_height, + "mod_height (Registered) Module Nominal Height"); + PRINT_NXS(129, spd->mod_section.registered.mod_thickness, + "mod_thickness (Registered) Module Maximum Thickness"); + PRINT_NXS(130, spd->mod_section.registered.ref_raw_card, + "ref_raw_card (Registered) Reference Raw Card Used"); + PRINT_NXS(131, spd->mod_section.registered.modu_attr, + "modu_attr (Registered) DIMM Module Attributes"); + PRINT_NXS(132, spd->mod_section.registered.thermal, + "thermal (Registered) Thermal Heat Spreader Solution"); + PRINT_NXS(133, spd->mod_section.registered.reg_id_lo, + "reg_id_lo (Registered) Register Manufacturer ID Code, LSB"); + PRINT_NXS(134, spd->mod_section.registered.reg_id_hi, + "reg_id_hi (Registered) Register Manufacturer ID Code, MSB"); + PRINT_NXS(135, spd->mod_section.registered.reg_rev, + "reg_rev (Registered) Register Revision Number"); + PRINT_NXS(136, spd->mod_section.registered.reg_map, + "reg_map (Registered) Address mapping"); + PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0], + spd->mod_section.registered.crc[1], " Module CRC"); + break; + case 0x04: /* LRDIMM */ + PRINT_NXS(128, spd->mod_section.loadreduced.mod_height, + "mod_height (Loadreduced) Module Nominal Height"); + PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness, + "mod_thickness (Loadreduced) Module Maximum Thickness"); + PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card, + "ref_raw_card (Loadreduced) Reference Raw Card Used"); + PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr, + "modu_attr (Loadreduced) DIMM Module Attributes"); + PRINT_NXS(132, spd->mod_section.loadreduced.thermal, + "thermal (Loadreduced) Thermal Heat Spreader Solution"); + PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo, + "reg_id_lo (Loadreduced) Register Manufacturer ID Code, LSB"); + PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi, + "reg_id_hi (Loadreduced) Register Manufacturer ID Code, MSB"); + PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev, + "reg_rev (Loadreduced) Register Revision Number"); + PRINT_NXS(136, spd->mod_section.loadreduced.reg_map, + "reg_map (Loadreduced) Address mapping"); + PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv, + "reg_drv (Loadreduced) Reg output drive strength"); + PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck, + "reg_drv_ck (Loadreduced) Reg output drive strength for CK"); + PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev, + "data_buf_rev (Loadreduced) Data Buffer Revision Numbe"); + PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0, + "vrefqe_r0 (Loadreduced) DRAM VrefDQ for Package Rank 0"); + PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1, + "vrefqe_r1 (Loadreduced) DRAM VrefDQ for Package Rank 1"); + PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2, + "vrefqe_r2 (Loadreduced) DRAM VrefDQ for Package Rank 2"); + PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3, + "vrefqe_r3 (Loadreduced) DRAM VrefDQ for Package Rank 3"); + PRINT_NXS(144, spd->mod_section.loadreduced.data_intf, + "data_intf (Loadreduced) Data Buffer VrefDQ for DRAM Interface"); + PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866, + "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT"); + PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400, + "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT"); + PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200, + "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT"); + PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv, + "dram_drv (Loadreduced) DRAM Drive Strength"); + PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866, + "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)"); + PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400, + "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)"); + PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200, + "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)"); + PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866, + "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)"); + PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400, + "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)"); + PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200, + "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)"); + PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0], + spd->mod_section.loadreduced.crc[1], + " Module CRC"); + break; + default: + /* Module-specific Section, Unsupported Module Type */ + printf("%-3d-%3d: ", 128, 255); + + for (i = 128; i <= 255; i++) + printf("%02x", spd->mod_section.uc[i - 60]); + + break; + } + + /* Unique Module ID: Bytes 320-383 */ + PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106"); + PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106"); + PRINT_NXS(322, spd->mloc, "Mfg Location"); + PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date"); + + printf("%-3d-%3d: ", 325, 328); + + for (i = 325; i <= 328; i++) + printf("%02x ", spd->sernum[i - 325]); + printf(" Module Serial Number\n"); + + printf("%-3d-%3d: ", 329, 348); + for (i = 329; i <= 348; i++) + printf("%02x ", spd->mpart[i - 329]); + printf(" Mfg's Module Part Number\n"); + + PRINT_NXS(349, spd->mrev, "Module Revision code"); + PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106"); + PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106"); + PRINT_NXS(352, spd->stepping, "DRAM stepping"); + + printf("%-3d-%3d: ", 353, 381); + for (i = 353; i <= 381; i++) + printf("%02x ", spd->msd[i - 353]); + printf(" Mfg's Specific Data\n"); +} +#endif + static inline void generic_spd_dump(const generic_spd_eeprom_t *spd) { #if defined(CONFIG_SYS_FSL_DDR1) @@ -1253,6 +1620,8 @@ static inline void generic_spd_dump(const generic_spd_eeprom_t *spd) ddr2_spd_dump(spd); #elif defined(CONFIG_SYS_FSL_DDR3) ddr3_spd_dump(spd); +#elif defined(CONFIG_SYS_FSL_DDR4) + ddr4_spd_dump(spd); #endif } diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index 610318ad1e7..05a24dd6efd 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2012 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -11,20 +11,23 @@ #include -#if defined(CONFIG_SYS_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) static unsigned int -compute_cas_latency_ddr3(const dimm_params_t *dimm_params, - common_timing_params_t *outpdimm, - unsigned int number_of_dimms) +compute_cas_latency(const dimm_params_t *dimm_params, + common_timing_params_t *outpdimm, + unsigned int number_of_dimms) { unsigned int i; - unsigned int taamin_ps = 0; - unsigned int tckmin_x_ps = 0; unsigned int common_caslat; unsigned int caslat_actual; unsigned int retry = 16; unsigned int tmp; const unsigned int mclk_ps = get_memory_clk_period_ps(); +#ifdef CONFIG_SYS_FSL_DDR3 + const unsigned int taamax = 20000; +#else + const unsigned int taamax = 18000; +#endif /* compute the common CAS latency supported between slots */ tmp = dimm_params[0].caslat_x; @@ -34,19 +37,20 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params, } common_caslat = tmp; - /* compute the max tAAmin tCKmin between slots */ - for (i = 0; i < number_of_dimms; i++) { - taamin_ps = max(taamin_ps, dimm_params[i].taa_ps); - tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps); - } /* validate if the memory clk is in the range of dimms */ - if (mclk_ps < tckmin_x_ps) { + if (mclk_ps < outpdimm->tckmin_x_ps) { printf("DDR clock (MCLK cycle %u ps) is faster than " "the slowest DIMM(s) (tCKmin %u ps) can support.\n", - mclk_ps, tckmin_x_ps); + mclk_ps, outpdimm->tckmin_x_ps); + } +#ifdef CONFIG_SYS_FSL_DDR4 + if (mclk_ps > outpdimm->tckmax_ps) { + printf("DDR clock (MCLK cycle %u ps) is slower than DIMM(s) (tCKmax %u ps) can support.\n", + mclk_ps, outpdimm->tckmax_ps); } +#endif /* determine the acutal cas latency */ - caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps; + caslat_actual = (outpdimm->taamin_ps + mclk_ps - 1) / mclk_ps; /* check if the dimms support the CAS latency */ while (!(common_caslat & (1 << caslat_actual)) && retry > 0) { caslat_actual++; @@ -54,13 +58,147 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params, } /* once the caculation of caslat_actual is completed * we must verify that this CAS latency value does not - * exceed tAAmax, which is 20 ns for all DDR3 speed grades + * exceed tAAmax, which is 20 ns for all DDR3 speed grades, + * 18ns for all DDR4 speed grades. */ - if (caslat_actual * mclk_ps > 20000) { + if (caslat_actual * mclk_ps > taamax) { printf("The choosen cas latency %d is too large\n", caslat_actual); } - outpdimm->lowest_common_SPD_caslat = caslat_actual; + outpdimm->lowest_common_spd_caslat = caslat_actual; + debug("lowest_common_spd_caslat is 0x%x\n", caslat_actual); + + return 0; +} +#else /* for DDR1 and DDR2 */ +static unsigned int +compute_cas_latency(const dimm_params_t *dimm_params, + common_timing_params_t *outpdimm, + unsigned int number_of_dimms) +{ + int i; + const unsigned int mclk_ps = get_memory_clk_period_ps(); + unsigned int lowest_good_caslat; + unsigned int not_ok; + unsigned int temp1, temp2; + + debug("using mclk_ps = %u\n", mclk_ps); + if (mclk_ps > outpdimm->tckmax_ps) { + printf("Warning: DDR clock (%u ps) is slower than DIMM(s) (tCKmax %u ps)\n", + mclk_ps, outpdimm->tckmax_ps); + } + + /* + * Compute a CAS latency suitable for all DIMMs + * + * Strategy for SPD-defined latencies: compute only + * CAS latency defined by all DIMMs. + */ + + /* + * Step 1: find CAS latency common to all DIMMs using bitwise + * operation. + */ + temp1 = 0xFF; + for (i = 0; i < number_of_dimms; i++) { + if (dimm_params[i].n_ranks) { + temp2 = 0; + temp2 |= 1 << dimm_params[i].caslat_x; + temp2 |= 1 << dimm_params[i].caslat_x_minus_1; + temp2 |= 1 << dimm_params[i].caslat_x_minus_2; + /* + * If there was no entry for X-2 (X-1) in + * the SPD, then caslat_x_minus_2 + * (caslat_x_minus_1) contains either 255 or + * 0xFFFFFFFF because that's what the glorious + * __ilog2 function returns for an input of 0. + * On 32-bit PowerPC, left shift counts with bit + * 26 set (that the value of 255 or 0xFFFFFFFF + * will have), cause the destination register to + * be 0. That is why this works. + */ + temp1 &= temp2; + } + } + + /* + * Step 2: check each common CAS latency against tCK of each + * DIMM's SPD. + */ + lowest_good_caslat = 0; + temp2 = 0; + while (temp1) { + not_ok = 0; + temp2 = __ilog2(temp1); + debug("checking common caslat = %u\n", temp2); + + /* Check if this CAS latency will work on all DIMMs at tCK. */ + for (i = 0; i < number_of_dimms; i++) { + if (!dimm_params[i].n_ranks) + continue; + + if (dimm_params[i].caslat_x == temp2) { + if (mclk_ps >= dimm_params[i].tckmin_x_ps) { + debug("CL = %u ok on DIMM %u at tCK=%u ps with tCKmin_X_ps of %u\n", + temp2, i, mclk_ps, + dimm_params[i].tckmin_x_ps); + continue; + } else { + not_ok++; + } + } + + if (dimm_params[i].caslat_x_minus_1 == temp2) { + unsigned int tckmin_x_minus_1_ps + = dimm_params[i].tckmin_x_minus_1_ps; + if (mclk_ps >= tckmin_x_minus_1_ps) { + debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_1_ps of %u\n", + temp2, i, mclk_ps, + tckmin_x_minus_1_ps); + continue; + } else { + not_ok++; + } + } + + if (dimm_params[i].caslat_x_minus_2 == temp2) { + unsigned int tckmin_x_minus_2_ps + = dimm_params[i].tckmin_x_minus_2_ps; + if (mclk_ps >= tckmin_x_minus_2_ps) { + debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_2_ps of %u\n", + temp2, i, mclk_ps, + tckmin_x_minus_2_ps); + continue; + } else { + not_ok++; + } + } + } + + if (!not_ok) + lowest_good_caslat = temp2; + + temp1 &= ~(1 << temp2); + } + + debug("lowest common SPD-defined CAS latency = %u\n", + lowest_good_caslat); + outpdimm->lowest_common_spd_caslat = lowest_good_caslat; + + + /* + * Compute a common 'de-rated' CAS latency. + * + * The strategy here is to find the *highest* dereated cas latency + * with the assumption that all of the DIMMs will support a dereated + * CAS latency higher than or equal to their lowest dereated value. + */ + temp1 = 0; + for (i = 0; i < number_of_dimms; i++) + temp1 = max(temp1, dimm_params[i].caslat_lowest_derated); + + outpdimm->highest_common_derated_caslat = temp1; + debug("highest common dereated CAS latency = %u\n", temp1); return 0; } @@ -82,34 +220,40 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, unsigned int tckmin_x_ps = 0; unsigned int tckmax_ps = 0xFFFFFFFF; - unsigned int tckmax_max_ps = 0; unsigned int trcd_ps = 0; unsigned int trp_ps = 0; unsigned int tras_ps = 0; +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + unsigned int taamin_ps = 0; +#endif +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int twr_ps = 15000; + unsigned int trfc1_ps = 0; + unsigned int trfc2_ps = 0; + unsigned int trfc4_ps = 0; + unsigned int trrds_ps = 0; + unsigned int trrdl_ps = 0; + unsigned int tccdl_ps = 0; +#else unsigned int twr_ps = 0; unsigned int twtr_ps = 0; unsigned int trfc_ps = 0; unsigned int trrd_ps = 0; + unsigned int trtp_ps = 0; +#endif unsigned int trc_ps = 0; unsigned int refresh_rate_ps = 0; unsigned int extended_op_srt = 1; +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) unsigned int tis_ps = 0; unsigned int tih_ps = 0; unsigned int tds_ps = 0; unsigned int tdh_ps = 0; - unsigned int trtp_ps = 0; unsigned int tdqsq_max_ps = 0; unsigned int tqhs_ps = 0; - +#endif unsigned int temp1, temp2; unsigned int additive_latency = 0; -#if !defined(CONFIG_SYS_FSL_DDR3) - const unsigned int mclk_ps = get_memory_clk_period_ps(); - unsigned int lowest_good_caslat; - unsigned int not_ok; - - debug("using mclk_ps = %u\n", mclk_ps); -#endif temp1 = 0; for (i = 0; i < number_of_dimms; i++) { @@ -146,31 +290,34 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, * i.e., this is the slowest the whole system can go. */ tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps); - - /* Either find maximum value to determine slowest - * speed, delay, time, period, etc */ +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + taamin_ps = max(taamin_ps, dimm_params[i].taa_ps); +#endif tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps); - tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps); trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps); trp_ps = max(trp_ps, dimm_params[i].trp_ps); tras_ps = max(tras_ps, dimm_params[i].tras_ps); +#ifdef CONFIG_SYS_FSL_DDR4 + trfc1_ps = max(trfc1_ps, dimm_params[i].trfc1_ps); + trfc2_ps = max(trfc2_ps, dimm_params[i].trfc2_ps); + trfc4_ps = max(trfc4_ps, dimm_params[i].trfc4_ps); + trrds_ps = max(trrds_ps, dimm_params[i].trrds_ps); + trrdl_ps = max(trrdl_ps, dimm_params[i].trrdl_ps); + tccdl_ps = max(tccdl_ps, dimm_params[i].tccdl_ps); +#else twr_ps = max(twr_ps, dimm_params[i].twr_ps); twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps); trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps); trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps); + trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps); +#endif trc_ps = max(trc_ps, dimm_params[i].trc_ps); +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) tis_ps = max(tis_ps, dimm_params[i].tis_ps); tih_ps = max(tih_ps, dimm_params[i].tih_ps); tds_ps = max(tds_ps, dimm_params[i].tds_ps); tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps); - trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps); tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps); - refresh_rate_ps = max(refresh_rate_ps, - dimm_params[i].refresh_rate_ps); - /* extended_op_srt is either 0 or 1, 0 having priority */ - extended_op_srt = min(extended_op_srt, - dimm_params[i].extended_op_srt); - /* * Find maximum tdqsq_max_ps to find slowest. * @@ -178,6 +325,12 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, * strategy for this parameter? */ tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps); +#endif + refresh_rate_ps = max(refresh_rate_ps, + dimm_params[i].refresh_rate_ps); + /* extended_op_srt is either 0 or 1, 0 having priority */ + extended_op_srt = min(extended_op_srt, + dimm_params[i].extended_op_srt); } outpdimm->ndimms_present = number_of_dimms - temp1; @@ -189,24 +342,37 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, outpdimm->tckmin_x_ps = tckmin_x_ps; outpdimm->tckmax_ps = tckmax_ps; - outpdimm->tckmax_max_ps = tckmax_max_ps; +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + outpdimm->taamin_ps = taamin_ps; +#endif outpdimm->trcd_ps = trcd_ps; outpdimm->trp_ps = trp_ps; outpdimm->tras_ps = tras_ps; - outpdimm->twr_ps = twr_ps; +#ifdef CONFIG_SYS_FSL_DDR4 + outpdimm->trfc1_ps = trfc1_ps; + outpdimm->trfc2_ps = trfc2_ps; + outpdimm->trfc4_ps = trfc4_ps; + outpdimm->trrds_ps = trrds_ps; + outpdimm->trrdl_ps = trrdl_ps; + outpdimm->tccdl_ps = tccdl_ps; +#else outpdimm->twtr_ps = twtr_ps; outpdimm->trfc_ps = trfc_ps; outpdimm->trrd_ps = trrd_ps; + outpdimm->trtp_ps = trtp_ps; +#endif + outpdimm->twr_ps = twr_ps; outpdimm->trc_ps = trc_ps; outpdimm->refresh_rate_ps = refresh_rate_ps; outpdimm->extended_op_srt = extended_op_srt; +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) outpdimm->tis_ps = tis_ps; outpdimm->tih_ps = tih_ps; outpdimm->tds_ps = tds_ps; outpdimm->tdh_ps = tdh_ps; - outpdimm->trtp_ps = trtp_ps; outpdimm->tdqsq_max_ps = tdqsq_max_ps; outpdimm->tqhs_ps = tqhs_ps; +#endif /* Determine common burst length for all DIMMs. */ temp1 = 0xff; @@ -265,128 +431,9 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, if (temp1 != 0) printf("ERROR: Mix different RDIMM detected!\n"); -#if defined(CONFIG_SYS_FSL_DDR3) - if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms)) + /* calculate cas latency for all DDR types */ + if (compute_cas_latency(dimm_params, outpdimm, number_of_dimms)) return 1; -#else - /* - * Compute a CAS latency suitable for all DIMMs - * - * Strategy for SPD-defined latencies: compute only - * CAS latency defined by all DIMMs. - */ - - /* - * Step 1: find CAS latency common to all DIMMs using bitwise - * operation. - */ - temp1 = 0xFF; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) { - temp2 = 0; - temp2 |= 1 << dimm_params[i].caslat_x; - temp2 |= 1 << dimm_params[i].caslat_x_minus_1; - temp2 |= 1 << dimm_params[i].caslat_x_minus_2; - /* - * FIXME: If there was no entry for X-2 (X-1) in - * the SPD, then caslat_x_minus_2 - * (caslat_x_minus_1) contains either 255 or - * 0xFFFFFFFF because that's what the glorious - * __ilog2 function returns for an input of 0. - * On 32-bit PowerPC, left shift counts with bit - * 26 set (that the value of 255 or 0xFFFFFFFF - * will have), cause the destination register to - * be 0. That is why this works. - */ - temp1 &= temp2; - } - } - - /* - * Step 2: check each common CAS latency against tCK of each - * DIMM's SPD. - */ - lowest_good_caslat = 0; - temp2 = 0; - while (temp1) { - not_ok = 0; - temp2 = __ilog2(temp1); - debug("checking common caslat = %u\n", temp2); - - /* Check if this CAS latency will work on all DIMMs at tCK. */ - for (i = 0; i < number_of_dimms; i++) { - if (!dimm_params[i].n_ranks) { - continue; - } - if (dimm_params[i].caslat_x == temp2) { - if (mclk_ps >= dimm_params[i].tckmin_x_ps) { - debug("CL = %u ok on DIMM %u at tCK=%u" - " ps with its tCKmin_X_ps of %u\n", - temp2, i, mclk_ps, - dimm_params[i].tckmin_x_ps); - continue; - } else { - not_ok++; - } - } - - if (dimm_params[i].caslat_x_minus_1 == temp2) { - unsigned int tckmin_x_minus_1_ps - = dimm_params[i].tckmin_x_minus_1_ps; - if (mclk_ps >= tckmin_x_minus_1_ps) { - debug("CL = %u ok on DIMM %u at " - "tCK=%u ps with its " - "tckmin_x_minus_1_ps of %u\n", - temp2, i, mclk_ps, - tckmin_x_minus_1_ps); - continue; - } else { - not_ok++; - } - } - - if (dimm_params[i].caslat_x_minus_2 == temp2) { - unsigned int tckmin_x_minus_2_ps - = dimm_params[i].tckmin_x_minus_2_ps; - if (mclk_ps >= tckmin_x_minus_2_ps) { - debug("CL = %u ok on DIMM %u at " - "tCK=%u ps with its " - "tckmin_x_minus_2_ps of %u\n", - temp2, i, mclk_ps, - tckmin_x_minus_2_ps); - continue; - } else { - not_ok++; - } - } - } - - if (!not_ok) { - lowest_good_caslat = temp2; - } - - temp1 &= ~(1 << temp2); - } - - debug("lowest common SPD-defined CAS latency = %u\n", - lowest_good_caslat); - outpdimm->lowest_common_SPD_caslat = lowest_good_caslat; - - - /* - * Compute a common 'de-rated' CAS latency. - * - * The strategy here is to find the *highest* dereated cas latency - * with the assumption that all of the DIMMs will support a dereated - * CAS latency higher than or equal to their lowest dereated value. - */ - temp1 = 0; - for (i = 0; i < number_of_dimms; i++) { - temp1 = max(temp1, dimm_params[i].caslat_lowest_derated); - } - outpdimm->highest_common_derated_caslat = temp1; - debug("highest common dereated CAS latency = %u\n", temp1); -#endif /* #if defined(CONFIG_SYS_FSL_DDR3) */ /* Determine if all DIMMs ECC capable. */ temp1 = 1; @@ -404,14 +451,6 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, } outpdimm->all_dimms_ecc_capable = temp1; -#ifndef CONFIG_SYS_FSL_DDR3 - /* FIXME: move to somewhere else to validate. */ - if (mclk_ps > tckmax_max_ps) { - printf("Warning: some of the installed DIMMs " - "can not operate this slowly.\n"); - return 1; - } -#endif /* * Compute additive latency. * @@ -468,27 +507,20 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, additive_latency = 0; #if defined(CONFIG_SYS_FSL_DDR2) - if (lowest_good_caslat < 4) { - additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat) - ? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0; + if ((outpdimm->lowest_common_spd_caslat < 4) && + (picos_to_mclk(trcd_ps) > outpdimm->lowest_common_spd_caslat)) { + additive_latency = picos_to_mclk(trcd_ps) - + outpdimm->lowest_common_spd_caslat; if (mclk_to_picos(additive_latency) > trcd_ps) { additive_latency = picos_to_mclk(trcd_ps); debug("setting additive_latency to %u because it was " " greater than tRCD_ps\n", additive_latency); } } - -#elif defined(CONFIG_SYS_FSL_DDR3) - /* - * The system will not use the global auto-precharge mode. - * However, it uses the page mode, so we set AL=0 - */ - additive_latency = 0; #endif /* * Validate additive latency - * FIXME: move to somewhere else to validate * * AL <= tRCD(min) */ @@ -516,10 +548,19 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, debug("trcd_ps = %u\n", outpdimm->trcd_ps); debug("trp_ps = %u\n", outpdimm->trp_ps); debug("tras_ps = %u\n", outpdimm->tras_ps); - debug("twr_ps = %u\n", outpdimm->twr_ps); +#ifdef CONFIG_SYS_FSL_DDR4 + debug("trfc1_ps = %u\n", trfc1_ps); + debug("trfc2_ps = %u\n", trfc2_ps); + debug("trfc4_ps = %u\n", trfc4_ps); + debug("trrds_ps = %u\n", trrds_ps); + debug("trrdl_ps = %u\n", trrdl_ps); + debug("tccdl_ps = %u\n", tccdl_ps); +#else debug("twtr_ps = %u\n", outpdimm->twtr_ps); debug("trfc_ps = %u\n", outpdimm->trfc_ps); debug("trrd_ps = %u\n", outpdimm->trrd_ps); +#endif + debug("twr_ps = %u\n", outpdimm->twr_ps); debug("trc_ps = %u\n", outpdimm->trc_ps); return 0; diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index d62ca63c770..f95704f3dfd 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2012 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -81,14 +81,37 @@ u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { #endif +#define SPD_SPA0_ADDRESS 0x36 +#define SPD_SPA1_ADDRESS 0x37 + static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) { int ret; +#ifdef CONFIG_SYS_FSL_DDR4 + uint8_t dummy = 0; +#endif i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); +#ifdef CONFIG_SYS_FSL_DDR4 + /* + * DDR4 SPD has 384 to 512 bytes + * To access the lower 256 bytes, we need to set EE page address to 0 + * To access the upper 256 bytes, we need to set EE page address to 1 + * See Jedec standar No. 21-C for detail + */ + i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1); + ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256); + if (!ret) { + i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1); + ret = i2c_read(i2c_address, 0, 1, + (uchar *)((ulong)spd + 256), + min(256, sizeof(generic_spd_eeprom_t) - 256)); + } +#else ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(generic_spd_eeprom_t)); +#endif if (ret) { if (i2c_address == diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index b0cf046fdcd..bf0d1da7cfa 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -1,5 +1,5 @@ /* - * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc. + * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -29,7 +29,7 @@ struct dynamic_odt { unsigned int odt_rtt_wr; }; -#ifdef CONFIG_SYS_FSL_DDR3 +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) static const struct dynamic_odt single_Q[4] = { { /* cs0 */ FSL_DDR_ODT_NEVER, @@ -259,7 +259,7 @@ static const struct dynamic_odt odt_unknown[4] = { DDR3_RTT_OFF } }; -#else /* CONFIG_SYS_FSL_DDR3 */ +#else /* CONFIG_SYS_FSL_DDR3 || CONFIG_SYS_FSL_DDR4 */ static const struct dynamic_odt single_Q[4] = { {0, 0, 0, 0}, {0, 0, 0, 0}, @@ -507,7 +507,9 @@ unsigned int populate_memctl_options(int all_dimms_registered, unsigned int i; char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; -#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2) +#if defined(CONFIG_SYS_FSL_DDR3) || \ + defined(CONFIG_SYS_FSL_DDR2) || \ + defined(CONFIG_SYS_FSL_DDR4) const struct dynamic_odt *pdodt = odt_unknown; #endif ulong ddr_freq; @@ -519,7 +521,9 @@ unsigned int populate_memctl_options(int all_dimms_registered, if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; -#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2) +#if defined(CONFIG_SYS_FSL_DDR3) || \ + defined(CONFIG_SYS_FSL_DDR2) || \ + defined(CONFIG_SYS_FSL_DDR4) /* Chip select options. */ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { switch (pdimm[0].n_ranks) { @@ -585,7 +589,9 @@ unsigned int populate_memctl_options(int all_dimms_registered, /* Pick chip-select local options. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { -#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2) +#if defined(CONFIG_SYS_FSL_DDR3) || \ + defined(CONFIG_SYS_FSL_DDR2) || \ + defined(CONFIG_SYS_FSL_DDR4) popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg; popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg; popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm; @@ -703,7 +709,7 @@ unsigned int populate_memctl_options(int all_dimms_registered, popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0; /* Choose burst length. */ -#if defined(CONFIG_SYS_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) #if defined(CONFIG_E500MC) popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */ popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ @@ -722,7 +728,7 @@ unsigned int populate_memctl_options(int all_dimms_registered, #endif /* Choose ddr controller address mirror mode */ -#if defined(CONFIG_SYS_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) popts->mirrored_dimm = pdimm[0].mirrored_dimm; #endif @@ -766,11 +772,9 @@ unsigned int populate_memctl_options(int all_dimms_registered, * BSTTOPRE precharge interval * * Set this to 0 for global auto precharge - * - * FIXME: Should this be configured in picoseconds? - * Why it should be in ps: better understanding of this - * relative to actual DRAM timing parameters such as tRAS. - * e.g. tRAS(min) = 40 ns + * The value of 0x100 has been used for DDR1, DDR2, DDR3. + * It is not wrong. Any value should be OK. The performance depends on + * applications. There is no one good value for all. */ popts->bstopre = 0x100; @@ -795,12 +799,12 @@ unsigned int populate_memctl_options(int all_dimms_registered, */ popts->tfaw_window_four_activates_ps = 37500; -#elif defined(CONFIG_SYS_FSL_DDR3) +#else popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps; #endif popts->zq_en = 0; popts->wrlvl_en = 0; -#if defined(CONFIG_SYS_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) /* * due to ddr3 dimm is fly-by topology * we suggest to enable write leveling to diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index ad53658fc92..7a22aa39886 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2012 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -23,6 +23,18 @@ #define ULL_8FS 0xFFFFFFFFULL +u32 fsl_ddr_get_version(void) +{ + struct ccsr_ddr __iomem *ddr; + u32 ver_major_minor_errata; + + ddr = (void *)_DDR_ADDR; + ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; + ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; + + return ver_major_minor_errata; +} + /* * Round up mclk_ps to nearest 1 ps in memory controller code * if the error is 0.5ps or more. @@ -175,6 +187,9 @@ void board_add_ram_info(int use_default) case SDRAM_TYPE_DDR3: puts("3"); break; + case SDRAM_TYPE_DDR4: + puts("4"); + break; default: puts("?"); break; @@ -188,9 +203,12 @@ void board_add_ram_info(int use_default) puts(", 64-bit"); /* Calculate CAS latency based on timing cfg values */ - cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; - if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1) - cas_lat += (8 << 1); + cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); + if (fsl_ddr_get_version() <= 0x40400) + cas_lat += 1; + else + cas_lat += 2; + cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4; printf(", CL=%d", cas_lat >> 1); if (cas_lat & 0x1) puts(".5"); diff --git a/include/common_timing_params.h b/include/common_timing_params.h index 76338d4e6c1..821de21de73 100644 --- a/include/common_timing_params.h +++ b/include/common_timing_params.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -14,32 +14,45 @@ typedef struct { unsigned int tckmin_x_ps; unsigned int tckmax_ps; - unsigned int tckmax_max_ps; unsigned int trcd_ps; unsigned int trp_ps; unsigned int tras_ps; +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) + unsigned int taamin_ps; +#endif - unsigned int twr_ps; /* maximum = 63750 ps */ +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int trfc1_ps; + unsigned int trfc2_ps; + unsigned int trfc4_ps; + unsigned int trrds_ps; + unsigned int trrdl_ps; + unsigned int tccdl_ps; +#else unsigned int twtr_ps; /* maximum = 63750 ps */ unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns = 511750 ps */ unsigned int trrd_ps; /* maximum = 63750 ps */ + unsigned int trtp_ps; /* byte 38, spd->trtp */ +#endif + unsigned int twr_ps; /* maximum = 63750 ps */ unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ unsigned int refresh_rate_ps; unsigned int extended_op_srt; +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) unsigned int tis_ps; /* byte 32, spd->ca_setup */ unsigned int tih_ps; /* byte 33, spd->ca_hold */ unsigned int tds_ps; /* byte 34, spd->data_setup */ unsigned int tdh_ps; /* byte 35, spd->data_hold */ - unsigned int trtp_ps; /* byte 38, spd->trtp */ unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ unsigned int tqhs_ps; /* byte 45, spd->tqhs */ +#endif unsigned int ndimms_present; - unsigned int lowest_common_SPD_caslat; + unsigned int lowest_common_spd_caslat; unsigned int highest_common_derated_caslat; unsigned int additive_latency; unsigned int all_dimms_burst_lengths_bitmask; diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 15a3e8d3518..cf2aac6ae42 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -290,11 +290,220 @@ typedef struct ddr3_spd_eeprom_s { } ddr3_spd_eeprom_t; +/* From JEEC Standard No. 21-C release 23A */ +struct ddr4_spd_eeprom_s { + /* General Section: Bytes 0-127 */ + uint8_t info_size_crc; /* 0 # bytes */ + uint8_t spd_rev; /* 1 Total # bytes of SPD */ + uint8_t mem_type; /* 2 Key Byte / mem type */ + uint8_t module_type; /* 3 Key Byte / Module Type */ + uint8_t density_banks; /* 4 Density and Banks */ + uint8_t addressing; /* 5 Addressing */ + uint8_t package_type; /* 6 Package type */ + uint8_t opt_feature; /* 7 Optional features */ + uint8_t thermal_ref; /* 8 Thermal and refresh */ + uint8_t oth_opt_features; /* 9 Other optional features */ + uint8_t res_10; /* 10 Reserved */ + uint8_t module_vdd; /* 11 Module nominal voltage */ + uint8_t organization; /* 12 Module Organization */ + uint8_t bus_width; /* 13 Module Memory Bus Width */ + uint8_t therm_sensor; /* 14 Module Thermal Sensor */ + uint8_t ext_type; /* 15 Extended module type */ + uint8_t res_16; + uint8_t timebases; /* 17 MTb and FTB */ + uint8_t tck_min; /* 18 tCKAVGmin */ + uint8_t tck_max; /* 19 TCKAVGmax */ + uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */ + uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */ + uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */ + uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */ + uint8_t taa_min; /* 24 Min CAS Latency Time */ + uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */ + uint8_t trp_min; /* 26 Min Row Precharge Delay Time */ + uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */ + uint8_t tras_min_lsb; /* 28 tRASmin, lsb */ + uint8_t trc_min_lsb; /* 29 tRCmin, lsb */ + uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */ + uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */ + uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */ + uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */ + uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */ + uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */ + uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */ + uint8_t tfaw_min; /* 37 tFAW, lsb */ + uint8_t trrds_min; /* 38 tRRD_Smin, MTB */ + uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */ + uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */ + uint8_t res_41[60-41]; /* 41 Rserved */ + uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ + uint8_t res_78[117-78]; /* 78~116, Reserved */ + int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */ + int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */ + int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */ + int8_t fine_trc_min; /* 120 Fine offset for tRCmin */ + int8_t fine_trp_min; /* 121 Fine offset for tRPmin */ + int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */ + int8_t fine_taa_min; /* 123 Fine offset for tAAmin */ + int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */ + int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */ + /* CRC: Bytes 126-127 */ + uint8_t crc[2]; /* 126-127 SPD CRC */ + + /* Module-Specific Section: Bytes 128-255 */ + union { + struct { + /* 128 (Unbuffered) Module Nominal Height */ + uint8_t mod_height; + /* 129 (Unbuffered) Module Maximum Thickness */ + uint8_t mod_thickness; + /* 130 (Unbuffered) Reference Raw Card Used */ + uint8_t ref_raw_card; + /* 131 (Unbuffered) Address Mapping from + Edge Connector to DRAM */ + uint8_t addr_mapping; + /* 132~253 (Unbuffered) Reserved */ + uint8_t res_132[254-132]; + /* 254~255 CRC */ + uint8_t crc[2]; + } unbuffered; + struct { + /* 128 (Registered) Module Nominal Height */ + uint8_t mod_height; + /* 129 (Registered) Module Maximum Thickness */ + uint8_t mod_thickness; + /* 130 (Registered) Reference Raw Card Used */ + uint8_t ref_raw_card; + /* 131 DIMM Module Attributes */ + uint8_t modu_attr; + /* 132 RDIMM Thermal Heat Spreader Solution */ + uint8_t thermal; + /* 133 Register Manufacturer ID Code, LSB */ + uint8_t reg_id_lo; + /* 134 Register Manufacturer ID Code, MSB */ + uint8_t reg_id_hi; + /* 135 Register Revision Number */ + uint8_t reg_rev; + /* 136 Address mapping from register to DRAM */ + uint8_t reg_map; + /* 137~253 Reserved */ + uint8_t res_137[254-137]; + /* 254~255 CRC */ + uint8_t crc[2]; + } registered; + struct { + /* 128 (Loadreduced) Module Nominal Height */ + uint8_t mod_height; + /* 129 (Loadreduced) Module Maximum Thickness */ + uint8_t mod_thickness; + /* 130 (Loadreduced) Reference Raw Card Used */ + uint8_t ref_raw_card; + /* 131 DIMM Module Attributes */ + uint8_t modu_attr; + /* 132 RDIMM Thermal Heat Spreader Solution */ + uint8_t thermal; + /* 133 Register Manufacturer ID Code, LSB */ + uint8_t reg_id_lo; + /* 134 Register Manufacturer ID Code, MSB */ + uint8_t reg_id_hi; + /* 135 Register Revision Number */ + uint8_t reg_rev; + /* 136 Address mapping from register to DRAM */ + uint8_t reg_map; + /* 137 Register Output Drive Strength for CMD/Add*/ + uint8_t reg_drv; + /* 138 Register Output Drive Strength for CK */ + uint8_t reg_drv_ck; + /* 139 Data Buffer Revision Number */ + uint8_t data_buf_rev; + /* 140 DRAM VrefDQ for Package Rank 0 */ + uint8_t vrefqe_r0; + /* 141 DRAM VrefDQ for Package Rank 1 */ + uint8_t vrefqe_r1; + /* 142 DRAM VrefDQ for Package Rank 2 */ + uint8_t vrefqe_r2; + /* 143 DRAM VrefDQ for Package Rank 3 */ + uint8_t vrefqe_r3; + /* 144 Data Buffer VrefDQ for DRAM Interface */ + uint8_t data_intf; + /* + * 145 Data Buffer MDQ Drive Strength and RTT + * for data rate <= 1866 + */ + uint8_t data_drv_1866; + /* + * 146 Data Buffer MDQ Drive Strength and RTT + * for 1866 < data rate <= 2400 + */ + uint8_t data_drv_2400; + /* + * 147 Data Buffer MDQ Drive Strength and RTT + * for 2400 < data rate <= 3200 + */ + uint8_t data_drv_3200; + /* 148 DRAM Drive Strength */ + uint8_t dram_drv; + /* + * 149 DRAM ODT (RTT_WR, RTT_NOM) + * for data rate <= 1866 + */ + uint8_t dram_odt_1866; + /* + * 150 DRAM ODT (RTT_WR, RTT_NOM) + * for 1866 < data rate <= 2400 + */ + uint8_t dram_odt_2400; + /* + * 151 DRAM ODT (RTT_WR, RTT_NOM) + * for 2400 < data rate <= 3200 + */ + uint8_t dram_odt_3200; + /* + * 152 DRAM ODT (RTT_PARK) + * for data rate <= 1866 + */ + uint8_t dram_odt_park_1866; + /* + * 153 DRAM ODT (RTT_PARK) + * for 1866 < data rate <= 2400 + */ + uint8_t dram_odt_park_2400; + /* + * 154 DRAM ODT (RTT_PARK) + * for 2400 < data rate <= 3200 + */ + uint8_t dram_odt_park_3200; + uint8_t res_155[254-155]; /* Reserved */ + /* 254~255 CRC */ + uint8_t crc[2]; + } loadreduced; + uint8_t uc[128]; /* 128-255 Module-Specific Section */ + } mod_section; + + uint8_t res_256[320-256]; /* 256~319 Reserved */ + + /* Module supplier's data: Byte 320~383 */ + uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */ + uint8_t mmid_msb; /* 321 Module MfgID Code MSB */ + uint8_t mloc; /* 322 Mfg Location */ + uint8_t mdate[2]; /* 323~324 Mfg Date */ + uint8_t sernum[4]; /* 325~328 Module Serial Number */ + uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */ + uint8_t mrev; /* 349 Module Revision Code */ + uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */ + uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */ + uint8_t stepping; /* 352 DRAM stepping */ + uint8_t msd[29]; /* 353~381 Mfg's Specific Data */ + uint8_t res_382[2]; /* 382~383 Reserved */ + + uint8_t user[512-384]; /* 384~511 End User Programmable */ +}; + extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd); extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd); extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd); extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd); extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); +unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd); /* * Byte 2 Fundamental Memory Types. @@ -310,6 +519,7 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); #define SPD_MEMTYPE_DDR2_FBDIMM (0x09) #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) #define SPD_MEMTYPE_DDR3 (0x0B) +#define SPD_MEMTYPE_DDR4 (0x0C) /* DIMM Type for DDR2 SPD (according to v1.3) */ #define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00) @@ -338,4 +548,18 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); #define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C) #define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D) +/* DIMM Type for DDR4 SPD */ +#define DDR4_SPD_MODULETYPE_MASK (0x0f) +#define DDR4_SPD_MODULETYPE_EXT (0x00) +#define DDR4_SPD_MODULETYPE_RDIMM (0x01) +#define DDR4_SPD_MODULETYPE_UDIMM (0x02) +#define DDR4_SPD_MODULETYPE_SO_DIMM (0x03) +#define DDR4_SPD_MODULETYPE_LRDIMM (0x04) +#define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05) +#define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06) +#define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08) +#define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09) +#define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C) +#define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D) + #endif /* _DDR_SPD_H_ */ diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 72c0b2e94ed..5c49b229daf 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -9,6 +9,7 @@ #ifndef FSL_DDR_MAIN_H #define FSL_DDR_MAIN_H +#include #include #include @@ -22,6 +23,10 @@ #define ddr_out32(a, v) out_be32(a, v) #endif +#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR + +u32 fsl_ddr_get_version(void); + #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* * Bind the main DDR setup driver's generic names diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h index 99a72bc6e16..09a67a68029 100644 --- a/include/fsl_ddr_dimm_params.h +++ b/include/fsl_ddr_dimm_params.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -13,7 +13,7 @@ #define EDC_ECC 2 #define EDC_AC_PARITY 4 -/* Parameters for a DDR2 dimm computed from the SPD */ +/* Parameters for a DDR dimm computed from the SPD */ typedef struct dimm_params_s { /* DIMM organization parameters */ @@ -32,7 +32,12 @@ typedef struct dimm_params_s { unsigned int n_row_addr; unsigned int n_col_addr; unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int bank_addr_bits; + unsigned int bank_group_bits; +#else unsigned int n_banks_per_sdram_device; +#endif unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ unsigned int row_density; @@ -43,19 +48,19 @@ typedef struct dimm_params_s { /* DIMM timing parameters */ - unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ - unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ - unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */ - unsigned int tfaw_ps; /* four active window delay, only for ddr3 */ + int mtb_ps; /* medium timebase ps */ + int ftb_10th_ps; /* fine timebase, in 1/10 ps */ + int taa_ps; /* minimum CAS latency time */ + int tfaw_ps; /* four active window delay */ /* * SDRAM clock periods * The range for these are 1000-10000 so a short should be sufficient */ - unsigned int tckmin_x_ps; - unsigned int tckmin_x_minus_1_ps; - unsigned int tckmin_x_minus_2_ps; - unsigned int tckmax_ps; + int tckmin_x_ps; + int tckmin_x_minus_1_ps; + int tckmin_x_minus_2_ps; + int tckmax_ps; /* SPD-defined CAS latencies */ unsigned int caslat_x; @@ -65,32 +70,46 @@ typedef struct dimm_params_s { unsigned int caslat_lowest_derated; /* Derated CAS latency */ /* basic timing parameters */ - unsigned int trcd_ps; - unsigned int trp_ps; - unsigned int tras_ps; - - unsigned int twr_ps; /* maximum = 63750 ps */ - unsigned int twtr_ps; /* maximum = 63750 ps */ - unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns + int trcd_ps; + int trp_ps; + int tras_ps; + +#ifdef CONFIG_SYS_FSL_DDR4 + int trfc1_ps; + int trfc2_ps; + int trfc4_ps; + int trrds_ps; + int trrdl_ps; + int tccdl_ps; +#else + int twr_ps; /* maximum = 63750 ps */ + int trfc_ps; /* max = 255 ns + 256 ns + .75 ns = 511750 ps */ + int trrd_ps; /* maximum = 63750 ps */ + int twtr_ps; /* maximum = 63750 ps */ + int trtp_ps; /* byte 38, spd->trtp */ +#endif - unsigned int trrd_ps; /* maximum = 63750 ps */ - unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ - unsigned int refresh_rate_ps; - unsigned int extended_op_srt; + int refresh_rate_ps; + int extended_op_srt; - /* DDR3 doesn't need these as below */ - unsigned int tis_ps; /* byte 32, spd->ca_setup */ - unsigned int tih_ps; /* byte 33, spd->ca_hold */ - unsigned int tds_ps; /* byte 34, spd->data_setup */ - unsigned int tdh_ps; /* byte 35, spd->data_hold */ - unsigned int trtp_ps; /* byte 38, spd->trtp */ - unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tqhs_ps; /* byte 45, spd->tqhs */ +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + int tis_ps; /* byte 32, spd->ca_setup */ + int tih_ps; /* byte 33, spd->ca_hold */ + int tds_ps; /* byte 34, spd->data_setup */ + int tdh_ps; /* byte 35, spd->data_hold */ + int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + int tqhs_ps; /* byte 45, spd->tqhs */ +#endif /* DDR3 RDIMM */ unsigned char rcw[16]; /* Register Control Word 0-15 */ +#ifdef CONFIG_SYS_FSL_DDR4 + unsigned int dq_mapping[18]; + unsigned int dq_mapping_ors; +#endif } dimm_params_t; extern unsigned int ddr_compute_dimm_parameters( diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 2a36431146d..e39b716188f 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -13,11 +13,13 @@ * Pick a basic DDR Technology. */ #include +#include -#define SDRAM_TYPE_DDR1 2 -#define SDRAM_TYPE_DDR2 3 -#define SDRAM_TYPE_LPDDR1 6 -#define SDRAM_TYPE_DDR3 7 +#define SDRAM_TYPE_DDR1 2 +#define SDRAM_TYPE_DDR2 3 +#define SDRAM_TYPE_LPDDR1 6 +#define SDRAM_TYPE_DDR3 7 +#define SDRAM_TYPE_DDR4 5 #define DDR_BL4 4 /* burst length 4 */ #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ @@ -54,6 +56,12 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #ifndef CONFIG_FSL_SDRAM_TYPE #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 #endif +#elif defined(CONFIG_SYS_FSL_DDR4) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ +typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4 +#endif #endif /* #if defined(CONFIG_SYS_FSL_DDR1) */ #define FSL_DDR_ODT_NEVER 0x0 @@ -116,7 +124,8 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define TIMING_CFG_2_CPO_MASK 0x0F800000 -#if defined(CONFIG_P4080) +#if defined(CONFIG_SYS_FSL_DDR_VER) && \ + (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4) #define RD_TO_PRE_MASK 0xf #define RD_TO_PRE_SHIFT 13 #define WR_DATA_DELAY_MASK 0xf @@ -154,9 +163,27 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define DDR_CDR2_ODT_MASK 0x1 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) +#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) +#ifdef CONFIG_SYS_FSL_DDR3L +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_120ohm 0x1 +#define DDR_CDR_ODT_200ohm 0x2 +#define DDR_CDR_ODT_75ohm 0x3 +#define DDR_CDR_ODT_60ohm 0x5 +#define DDR_CDR_ODT_46ohm 0x7 +#elif defined(CONFIG_SYS_FSL_DDR4) +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_100ohm 0x1 +#define DDR_CDR_ODT_120OHM 0x2 +#define DDR_CDR_ODT_80ohm 0x3 +#define DDR_CDR_ODT_60ohm 0x4 +#define DDR_CDR_ODT_40ohm 0x5 +#define DDR_CDR_ODT_50ohm 0x6 +#define DDR_CDR_ODT_30ohm 0x7 +#else #define DDR_CDR_ODT_OFF 0x0 #define DDR_CDR_ODT_120ohm 0x1 #define DDR_CDR_ODT_180ohm 0x2 @@ -165,6 +192,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define DDR_CDR_ODT_60hm 0x5 #define DDR_CDR_ODT_70ohm 0x6 #define DDR_CDR_ODT_47ohm 0x7 +#endif /* DDR3L */ #else #define DDR_CDR_ODT_75ohm 0x0 #define DDR_CDR_ODT_55ohm 0x1 @@ -188,6 +216,7 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int timing_cfg_2; unsigned int ddr_sdram_cfg; unsigned int ddr_sdram_cfg_2; + unsigned int ddr_sdram_cfg_3; unsigned int ddr_sdram_mode; unsigned int ddr_sdram_mode_2; unsigned int ddr_sdram_mode_3; @@ -196,6 +225,14 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int ddr_sdram_mode_6; unsigned int ddr_sdram_mode_7; unsigned int ddr_sdram_mode_8; + unsigned int ddr_sdram_mode_9; + unsigned int ddr_sdram_mode_10; + unsigned int ddr_sdram_mode_11; + unsigned int ddr_sdram_mode_12; + unsigned int ddr_sdram_mode_13; + unsigned int ddr_sdram_mode_14; + unsigned int ddr_sdram_mode_15; + unsigned int ddr_sdram_mode_16; unsigned int ddr_sdram_md_cntl; unsigned int ddr_sdram_interval; unsigned int ddr_data_init; @@ -204,6 +241,10 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int ddr_init_ext_addr; unsigned int timing_cfg_4; unsigned int timing_cfg_5; + unsigned int timing_cfg_6; + unsigned int timing_cfg_7; + unsigned int timing_cfg_8; + unsigned int timing_cfg_9; unsigned int ddr_zq_cntl; unsigned int ddr_wrlvl_cntl; unsigned int ddr_wrlvl_cntl_2; @@ -211,6 +252,14 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int ddr_sr_cntr; unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; + unsigned int ddr_sdram_rcw_3; + unsigned int ddr_sdram_rcw_4; + unsigned int ddr_sdram_rcw_5; + unsigned int ddr_sdram_rcw_6; + unsigned int dq_map_0; + unsigned int dq_map_1; + unsigned int dq_map_2; + unsigned int dq_map_3; unsigned int ddr_eor; unsigned int ddr_cdr1; unsigned int ddr_cdr2; @@ -225,7 +274,7 @@ typedef struct memctl_options_partial_s { unsigned int all_dimms_burst_lengths_bitmask; unsigned int all_dimms_registered; unsigned int all_dimms_unbuffered; - /* unsigned int lowest_common_SPD_caslat; */ + /* unsigned int lowest_common_spd_caslat; */ unsigned int all_dimms_minimum_trcd_ps; } memctl_options_partial_t; diff --git a/include/fsl_ddrc_version.h b/include/fsl_ddrc_version.h new file mode 100644 index 00000000000..60ba98bf810 --- /dev/null +++ b/include/fsl_ddrc_version.h @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_DDRC_VER_H +#define __FSL_DDRC_VER_H + +/* + * Only the versions with distinct features or registers are listed here. + */ +#define FSL_DDR_VER_4_4 44 +#define FSL_DDR_VER_4_6 46 +#define FSL_DDR_VER_4_7 47 +#define FSL_DDR_VER_5_0 50 + +#endif /* __FSL_DDRC_VER_H */ diff --git a/include/fsl_immap.h b/include/fsl_immap.h index 00902cae080..d63cc19fa15 100644 --- a/include/fsl_immap.h +++ b/include/fsl_immap.h @@ -1,7 +1,7 @@ /* * Common internal memory map for some Freescale SoCs * - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -50,7 +50,8 @@ struct ccsr_ddr { u8 res_150[16]; u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ - u8 reg_168[8]; + u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */ + u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */ u32 ddr_zq_cntl; /* ZQ calibration control*/ u32 ddr_wrlvl_cntl; /* write leveling control*/ u8 reg_178[4]; @@ -60,14 +61,40 @@ struct ccsr_ddr { u8 reg_188[8]; u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ - u8 res_198[104]; + u8 res_198[0x1a0-0x198]; + u32 ddr_sdram_rcw_3; + u32 ddr_sdram_rcw_4; + u32 ddr_sdram_rcw_5; + u32 ddr_sdram_rcw_6; + u8 res_1b0[0x200-0x1b0]; u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ - u8 res_218[0x908]; + u8 res_218[0x220-0x218]; + u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */ + u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */ + u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */ + u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */ + u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */ + u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */ + u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */ + u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */ + u8 res_240[0x250-0x240]; + u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */ + u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ + u8 res_258[0x260-0x258]; + u32 sdram_cfg_3; + u8 res_264[0x2a0-0x264]; + u32 deskew_cntl; + u8 res_2a4[0x400-0x2a4]; + u32 dq_map_0; + u32 dq_map_1; + u32 dq_map_2; + u32 dq_map_3; + u8 res_410[0xb20-0x410]; u32 ddr_dsr1; /* Debug Status 1 */ u32 ddr_dsr2; /* Debug Status 2 */ u32 ddr_cdr1; /* Control Driver 1 */ -- cgit v1.3.1 From 11856919f267d00155f571c75dd68ba1bb98729b Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Wed, 26 Feb 2014 17:43:15 +0530 Subject: fsl/usb: Workaround for USB erratum-A007075 Put a delay of 5 millisecond after reset so that ULPI phy gets enough time to come out of reset. Erratum A007075 applies to following SOCs and their variants, if any P1010 rev 1.0 B4860 rev 1.0, 2.0 P4080 rev 2.0, 3.0 Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ arch/powerpc/include/asm/config_mpc85xx.h | 3 +++ arch/powerpc/include/asm/fsl_errata.h | 16 ++++++++++++++++ drivers/usb/host/ehci-fsl.c | 10 ++++++++++ 4 files changed, 33 insertions(+) (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 8b79c05b1f2..ee063fd8e94 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -268,6 +268,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A005125 puts("Work-around for Erratum A005125 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007075 + if (has_erratum_a007075()) + puts("Work-around for Erratum A007075 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index fe68e0e2808..502e7ccf25d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -154,6 +154,7 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 #define CONFIG_ESDHC_HC_BLK_ADDR @@ -478,6 +479,7 @@ #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 #define CONFIG_SYS_FSL_ERRATUM_A005812 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ @@ -674,6 +676,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006475 #define CONFIG_SYS_FSL_ERRATUM_A006384 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index c9982cc8ec4..4eba85cc347 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -60,4 +60,20 @@ static inline bool has_erratum_a006261(void) } #endif +static inline bool has_erratum_a007075(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_B4860: + case SVR_B4420: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0); + case SVR_P4080: + return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); + } + return false; +} #endif diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 3fd9e13af8a..1d012db92e6 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "ehci.h" @@ -47,6 +48,15 @@ int ehci_hcd_init(int index, enum usb_init_type init, usb_phy[0] = '\0'; #endif + if (has_erratum_a007075()) { + /* + * A 5ms delay is needed after applying soft-reset to the + * controller to let external ULPI phy come out of reset. + * This delay needs to be added before re-initializing + * the controller after soft-resetting completes + */ + mdelay(5); + } memset(current_usb_controller, '\0', 5); snprintf(current_usb_controller, 4, "usb%d", index+1); -- cgit v1.3.1 From 613ab32c4783fcd70bd13125bdd59ad6cb18c1cc Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 31 Mar 2014 15:32:03 +0530 Subject: driver/mmc: fix compile warnings Fix following compile warnings fsl_esdhc_spl.c: In function 'mmc_boot': fsl_esdhc_spl.c:35:10: warning: unused variable 'byte_num' [-Wunused-variable] fsl_esdhc_spl.c:35:7: warning: unused variable 'i' [-Wunused-variable] fsl_esdhc_spl.c:34:8: warning: unused variable 'val' [-Wunused-variable] fsl_esdhc_spl.c:33:6: warning: unused variable 'blklen' [-Wunused-variable] fsl_esdhc_spl.c:105:7: warning: 'tmp_buf' may be used uninitialized in this function [-Wuninitialized] Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- drivers/mmc/fsl_esdhc_spl.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 8fc263f4f40..e0bbf21b628 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -29,10 +29,12 @@ void __noreturn mmc_boot(void) { __attribute__((noreturn)) void (*uboot)(void); uint blk_start, blk_cnt, err; - u32 blklen; +#ifndef CONFIG_FSL_CORENET uchar *tmp_buf; + u32 blklen; uchar val; uint i, byte_num; +#endif u32 offset, code_len; struct mmc *mmc; @@ -102,7 +104,9 @@ void __noreturn mmc_boot(void) (uchar *)CONFIG_SYS_MMC_U_BOOT_DST); if (err != blk_cnt) { puts("spl: mmc read failed!!\n"); +#ifndef CONFIG_FSL_CORENET free(tmp_buf); +#endif hang(); } -- cgit v1.3.1 From 896720ceb2cededcd1f25fa5f5ff23822bea466d Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Mon, 7 Apr 2014 08:46:14 +0530 Subject: fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0 Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0. This decreases data burst rate with which data packets are posted from the TX latency FIFO to compensate for latencies in DDR pipeline during DMA. This avoids Tx buffer underruns and leads to successful usb writes Signed-off-by: Ramneek Mehresh Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- drivers/usb/host/ehci-fsl.c | 20 ++++++++++++++++++++ include/usb/ehci-fsl.h | 7 +++++++ 2 files changed, 27 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 1d012db92e6..6cb4d986685 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -18,6 +18,8 @@ #include "ehci.h" +static void set_txfifothresh(struct usb_ehci *, u32); + /* Check USB PHY clock valid */ static int usb_phy_clk_valid(struct usb_ehci *ehci) { @@ -123,6 +125,10 @@ int ehci_hcd_init(int index, enum usb_init_type init, in_le32(&ehci->usbmode); + if (SVR_SOC_VER(get_svr()) == SVR_T4240 && + IS_SVR_REV(get_svr(), 2, 0)) + set_txfifothresh(ehci, TXFIFOTHRESH); + return 0; } @@ -134,3 +140,17 @@ int ehci_hcd_stop(int index) { return 0; } + +/* + * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register + * to counter DDR latencies in writing data into Tx buffer. + * This prevents Tx buffer from getting underrun + */ +static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh) +{ + u32 cmd; + cmd = ehci_readl(&ehci->txfilltuning); + cmd &= ~TXFIFO_THRESH_MASK; + cmd |= TXFIFO_THRESH(txfifo_thresh); + ehci_writel(&ehci->txfilltuning, cmd); +} diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index 734305b9dba..c9ee1d5bf62 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -163,6 +163,13 @@ #define CONFIG_SYS_FSL_USB2_ADDR 0 #endif +/* + * Increasing TX FIFO threshold value from 2 to 4 decreases + * data burst rate with which data packets are posted from the TX + * latency FIFO to compensate for latencies in DDR pipeline during DMA + */ +#define TXFIFOTHRESH 4 + /* * USB Registers */ -- cgit v1.3.1 From 2ee6c52e229e1d0d1e78c3efbc67bc8bb868fb25 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Apr 2014 10:55:49 +0530 Subject: driver/net/fm/memac_phy: Initialize mdio_clock for SoCs wih FMANv3 MDIO clock needs to be initialized in u-boot code for SoCs having FMAN-v3(v3H or v3L) controller due to below reasons -On SoCs that have FMAN-v3H like B4860, default value of MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates mdio clock too high (much higher than 2.5MHz), violating the IEEE specs. -On SOCs that have FMAN-v3L like T1040, default value of MDIO_CLK_DIV bits is zero, so MDIO clock is disabled. So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to be properly initialized. Also this type of initialization is generally done in PBI(pre-bootloader) phase using rcw.But for chips like T1040 which support deep-sleep, such type of initialization cannot be done in PBI phase due to the limitation that during deep-sleep resume, FMAN (MDIO) registers are not accessible in PBI phase. So, mdio clock initailization must be done as part of u-boot. This initialization code is implemented in memac_phy.c which gets compiled only for SoCs having FMANv3, so no extra compilation flag is required. Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- drivers/net/fm/memac_phy.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers') diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 140e59b75c4..2f4bc11a6c2 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -133,5 +133,17 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info) bus->priv = info->regs; + /* + * On some platforms like B4860, default value of MDIO_CLK_DIV bits + * in mdio_stat(mdio_cfg) register generates MDIO clock too high + * (much higher than 2.5MHz), violating the IEEE specs. + * On other platforms like T1040, default value of MDIO_CLK_DIV bits + * is zero, so MDIO clock is disabled. + * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to + * be properly initialized. + */ + setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat, + MDIO_STAT_CLKDIV(258)); + return mdio_register(bus); } -- cgit v1.3.1 From 349689b8021f0a7d7923099bd8bbe5eab117d4fa Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 1 Apr 2014 14:20:49 -0700 Subject: drivers/ddr: Fix possible out of bounds error This is a theoretical possible out of bounds error in DDR driver. Adding check before using array index. Also change some runtime conditions to pre-compiling conditions. Signed-off-by: York Sun Reviewed-by: York Sun --- drivers/ddr/fsl/ctrl_regs.c | 8 ++-- drivers/ddr/fsl/main.c | 6 +++ drivers/ddr/fsl/options.c | 108 ++++++++++++++++++++++---------------------- 3 files changed, 64 insertions(+), 58 deletions(-) (limited to 'drivers') diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index d01eea05f37..78e82bba3d4 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -507,8 +507,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4); wrtord_mclk = max(2, picos_to_mclk(2500)); - if (wrrec_mclk > 24) - printf("Error: WRREC doesn't support more than 24 clocks\n"); + if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) + printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); else wrrec_mclk = wrrec_table[wrrec_mclk - 1]; #else @@ -516,8 +516,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); - if (wrrec_mclk > 16) - printf("Error: WRREC doesn't support more than 16 clocks\n"); + if ((wrrec_mclk < 1) || (wrrec_mclk > 16)) + printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); else wrrec_mclk = wrrec_table[wrrec_mclk - 1]; #endif diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index f95704f3dfd..5e001fcb994 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -220,6 +220,11 @@ const char * step_to_string(unsigned int step) { if ((1 << s) != step) return step_string_tbl[7]; + if (s >= ARRAY_SIZE(step_string_tbl)) { + printf("Error for the step in %s\n", __func__); + s = 0; + } + return step_string_tbl[s]; } @@ -520,6 +525,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, /* STEP 5: Assign addresses to chip selects */ check_interleaving_options(pinfo); total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); + debug("Total mem %llu assigned\n", total_mem); case STEP_COMPUTE_REGS: /* STEP 6: compute controller register values */ diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index bf0d1da7cfa..5986e1a0b9d 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -525,67 +525,66 @@ unsigned int populate_memctl_options(int all_dimms_registered, defined(CONFIG_SYS_FSL_DDR2) || \ defined(CONFIG_SYS_FSL_DDR4) /* Chip select options. */ - if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { - switch (pdimm[0].n_ranks) { - case 1: - pdodt = single_S; - break; +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) + switch (pdimm[0].n_ranks) { + case 1: + pdodt = single_S; + break; + case 2: + pdodt = single_D; + break; + case 4: + pdodt = single_Q; + break; + } +#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + switch (pdimm[0].n_ranks) { +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + case 4: + pdodt = single_Q; + if (pdimm[1].n_ranks) + printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n"); + break; +#endif + case 2: + switch (pdimm[1].n_ranks) { case 2: - pdodt = single_D; + pdodt = dual_DD; break; - case 4: - pdodt = single_Q; + case 1: + pdodt = dual_DS; break; - } - } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { - switch (pdimm[0].n_ranks) { -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - case 4: - pdodt = single_Q; - if (pdimm[1].n_ranks) - printf("Error: Quad- and Dual-rank DIMMs " - "cannot be used together\n"); + case 0: + pdodt = dual_D0; break; -#endif + } + break; + case 1: + switch (pdimm[1].n_ranks) { case 2: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_DD; - break; - case 1: - pdodt = dual_DS; - break; - case 0: - pdodt = dual_D0; - break; - } + pdodt = dual_SD; break; case 1: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_SD; - break; - case 1: - pdodt = dual_SS; - break; - case 0: - pdodt = dual_S0; - break; - } + pdodt = dual_SS; break; case 0: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_0D; - break; - case 1: - pdodt = dual_0S; - break; - } + pdodt = dual_S0; break; } + break; + case 0: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_0D; + break; + case 1: + pdodt = dual_0S; + break; + } + break; } -#endif +#endif /* CONFIG_DIMM_SLOTS_PER_CTLR */ +#endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */ /* Pick chip-select local options. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { @@ -847,8 +846,7 @@ unsigned int populate_memctl_options(int all_dimms_registered, popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING; popts->memctl_interleaving = 1; debug("256 Byte interleaving\n"); - goto done; -#endif +#else /* * test null first. if CONFIG_HWCONFIG is not defined * hwconfig_arg_cmp returns non-zero @@ -930,8 +928,9 @@ unsigned int populate_memctl_options(int all_dimms_registered, popts->memctl_interleaving = 0; printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); } +#endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */ done: -#endif +#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { /* test null first. if CONFIG_HWCONFIG is not defined, @@ -1106,10 +1105,11 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: case FSL_DDR_SUPERBANK_INTERLEAVING: - if (3 == CONFIG_NUM_DDR_CONTROLLERS) +#if (3 == CONFIG_NUM_DDR_CONTROLLERS) k = 2; - else +#else k = CONFIG_NUM_DDR_CONTROLLERS; +#endif break; case FSL_DDR_3WAY_1KB_INTERLEAVING: case FSL_DDR_3WAY_4KB_INTERLEAVING: -- cgit v1.3.1 From aade20046b7ab5bd9b2afe84ccb31f0adf0c5e1e Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Thu, 17 Apr 2014 15:33:46 +0800 Subject: mpc85xx/t104x: Add deep sleep framework support When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- README | 4 +++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 ++++++ arch/powerpc/lib/board.c | 16 ++++++++++++ drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 52 ++++++++++++++++++++++++++++++++++--- include/fsl_ddr_sdram.h | 4 +++ 5 files changed, 80 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/README b/README index bbd7399f537..017a13df4da 100644 --- a/README +++ b/README @@ -431,6 +431,10 @@ The following options need to be configured: This CONFIG is defined when the CPC is configured as SRAM at the time of U-boot entry and is required to be re-initialized. + CONFIG_DEEP_SLEEP + Inidcates this SoC supports deep sleep feature. If deep sleep is + supported, core will start to execute uboot when wakes up. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 941c20e00a5..867abb6cf73 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -350,6 +350,7 @@ void cpu_init_f (void) extern void m8560_cpm_reset (void); #ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); #endif #if defined(CONFIG_SECURE_BOOT) struct law_entry law; @@ -414,6 +415,13 @@ void cpu_init_f (void) in_be32(&gur->dcsrcr); #endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (in_be32(&gur->scrtsr[0]) & (1 << 3)) + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +#endif +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 fsl_erratum_a007212_workaround(); #endif diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index f86c6f3e8fa..8b03d3aa07b 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -343,6 +343,13 @@ void board_init_f(ulong bootflag) #ifdef CONFIG_PRAM ulong reg; #endif +#ifdef CONFIG_DEEP_SLEEP + const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + u32 start_addr; + typedef void (*func_t)(void); + func_t kernel_resume; +#endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -360,6 +367,15 @@ void board_init_f(ulong bootflag) if ((*init_fnc_ptr) () != 0) hang(); +#ifdef CONFIG_DEEP_SLEEP + /* Jump to kernel in deep sleep case */ + if (in_be32(&gur->scrtsr[0]) & (1 << 3)) { + start_addr = in_be32(&scfg->sparecr[1]); + kernel_resume = (func_t)start_addr; + kernel_resume(); + } +#endif + #ifdef CONFIG_POST post_bootmode_init(); post_run(NULL, POST_ROM | post_bootmode_get(NULL)); diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index c8050864163..4d5572ef21b 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -15,6 +15,7 @@ #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL #endif +DECLARE_GLOBAL_DATA_PTR; /* * regs has the to-be-set values for DDR controller registers @@ -43,6 +44,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 save1, save2; #endif +#ifdef CONFIG_DEEP_SLEEP + const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + bool sleep_flag = 0; +#endif + +#ifdef CONFIG_DEEP_SLEEP + if (in_be32(&gur->scrtsr[0]) & (1 << 3)) + sleep_flag = 1; +#endif + switch (ctrl_num) { case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; @@ -119,7 +130,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); +#ifdef CONFIG_DEEP_SLEEP + if (sleep_flag) + out_be32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); + else +#endif + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); @@ -132,8 +149,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); out_be32(&ddr->sdram_data_init, regs->ddr_data_init); out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); +#ifdef CONFIG_DEEP_SLEEP + if (sleep_flag) { + out_be32(&ddr->init_addr, 0); + out_be32(&ddr->init_ext_addr, (1 << 31)); + } else +#endif + { + out_be32(&ddr->init_addr, regs->ddr_init_addr); + out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + } out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); @@ -374,8 +399,22 @@ step2: udelay(500); asm volatile("sync;isync"); +#ifdef CONFIG_DEEP_SLEEP + if (sleep_flag) { + /* enter self-refresh */ + setbits_be32(&ddr->sdram_cfg_2, (1 << 31)); + /* do board specific memory setup */ + board_mem_sleep_setup(); + } +#endif + /* Let the controller go */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; +#ifdef CONFIG_DEEP_SLEEP + if (sleep_flag) + temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); + else +#endif + temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI); out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("sync;isync"); @@ -526,4 +565,9 @@ step2: clrbits_be32(&ddr->sdram_cfg, 0x2); } #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ +#ifdef CONFIG_DEEP_SLEEP + if (sleep_flag) + /* exit self-refresh */ + clrbits_be32(&ddr->sdram_cfg_2, (1 << 31)); +#endif } diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index e39b716188f..e8a2db91cb7 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -406,6 +406,10 @@ static int __board_need_mem_reset(void) int board_need_mem_reset(void) __attribute__((weak, alias("__board_need_mem_reset"))); +void __weak board_mem_sleep_setup(void) +{ +} + /* * The 85xx boards have a common prototype for fixed_sdram so put the * declaration here. -- cgit v1.3.1 From 5abed9c546be4a96db1443cd3abd5f82dfbe5903 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 8 Apr 2014 19:12:58 +0530 Subject: driver/ifc: define nand_spl_load_image() for SPL nand_spl_load_image() can also be used for non TPL framework. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- drivers/mtd/nand/fsl_ifc_spl.c | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index 2f82f7c5c61..510077282cd 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -88,11 +88,7 @@ static inline int bad_block(uchar *marker, int port_size) return __raw_readw((u16 *)marker) != 0xffff; } -#ifdef CONFIG_TPL_BUILD int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) -#else -static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) -#endif { struct fsl_ifc *ifc = IFC_BASE_ADDR; uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; @@ -217,15 +213,6 @@ static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) return 0; } -/* - * Defines a static function nand_load_image() here, because non-static makes - * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes) - */ -#ifndef CONFIG_TPL_BUILD -#define nand_spl_load_image(offs, uboot_size, vdst) \ - nand_load(offs, uboot_size, vdst) -#endif - /* * Main entrypoint for NAND Boot. It's necessary that SDRAM is already * configured and available since this code loads the main U-boot image -- cgit v1.3.1 From e278ddcd7fb6550b58030988467ef4b48d51bed8 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 8 Apr 2014 19:13:11 +0530 Subject: driver/mtd/spi:Read 8KB data chunk during u-boot load in SPL SPI driver perform its operation(read/write) on 64KB buffer chunk for data greater than 64KB. This buffer chunk is allocated from system heap. During SPL boot, 768KB of data is read from SPI flash. Here, heap size may not be sufficient enough to full-fill 64KB buffer requirement of SPI driver. So break down u-boot read operation at 8KB of chunk. Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- drivers/mtd/spi/fsl_espi_spl.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index e5ac79b9520..a55d741a370 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -20,8 +20,10 @@ void spi_boot(void) { void (*uboot)(void) __noreturn; - u32 offset, code_len; + u32 offset, code_len, copy_len = 0; +#ifndef CONFIG_FSL_CORENET unsigned char *buf = NULL; +#endif struct spi_flash *flash; flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, @@ -56,8 +58,15 @@ void spi_boot(void) code_len = code_len - CONFIG_SPL_MAX_SIZE; #endif /* copy code to DDR */ - spi_flash_read(flash, offset, code_len, - (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST); + printf("Loading second stage boot loader "); + while (copy_len <= code_len) { + spi_flash_read(flash, offset + copy_len, 0x2000, + (void *)(CONFIG_SYS_SPI_FLASH_U_BOOT_DST + + copy_len)); + copy_len = copy_len + 0x2000; + putc('.'); + } + /* * Jump to U-Boot image */ -- cgit v1.3.1 From 1eaa742d85a59ed3602a78445adf903f26d9b594 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 8 Apr 2014 19:13:22 +0530 Subject: driver: Add support of image load for MMC & SPI in SPL Add support of loading image, binary for MMC and SPI during SPL boot. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- drivers/mmc/fsl_esdhc_spl.c | 26 ++++++++++++++++++++++++++ drivers/mtd/spi/fsl_espi_spl.c | 14 ++++++++++++++ include/fsl_esdhc.h | 1 + include/spi_flash.h | 1 + 4 files changed, 42 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index e0bbf21b628..b1cb4b3534f 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -19,6 +19,32 @@ #define MBRDBR_BOOT_SIG_AA 0x1ff #define CONFIG_CFG_DATA_SECTOR 0 + +void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst) +{ + uint blk_start, blk_cnt, err; + + struct mmc *mmc = find_mmc_device(0); + if (!mmc) { + puts("spl: mmc device not found!!\n"); + hang(); + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + return; + } + + blk_start = ALIGN(offs, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; + + err = mmc->block_dev.block_read(0, blk_start, blk_cnt, vdst); + if (err != blk_cnt) { + puts("spl: mmc read failed!!\n"); + hang(); + } +} + /* * The main entry for mmc booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index a55d741a370..b915469b404 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -12,6 +12,20 @@ #define ESPI_BOOT_IMAGE_ADDR 0x50 #define CONFIG_CFG_DATA_SECTOR 0 +void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst) +{ + struct spi_flash *flash; + + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (flash == NULL) { + puts("\nspi_flash_probe failed"); + hang(); + } + + spi_flash_read(flash, offs, size, vdst); +} + /* * The main entry for SPI booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index a6e3a5dc9af..9814964937d 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -187,5 +187,6 @@ static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; } static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {} #endif /* CONFIG_FSL_ESDHC */ void __noreturn mmc_boot(void); +void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst); #endif /* __FSL_ESDHC_H__ */ diff --git a/include/spi_flash.h b/include/spi_flash.h index 1a112862240..2db53c74c88 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -158,5 +158,6 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, } void spi_boot(void) __noreturn; +void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst); #endif /* _SPI_FLASH_H_ */ -- cgit v1.3.1 From 08ad9b068afb8842df4cd559c327f54a42811a8d Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Mon, 21 Apr 2014 10:29:24 +0800 Subject: ar8031: modify the config func of ar8031 to ar8021_config ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- drivers/net/phy/atheros.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index b80980d5524..abd4e5b463e 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -53,7 +53,7 @@ static struct phy_driver AR8031_driver = { .uid = 0x4dd074, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = genphy_config, + .config = ar8021_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; -- cgit v1.3.1 From dec1861be90c948ea9fb771927d3d26a994d2e20 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Feb 2014 14:02:52 -0800 Subject: driver/mxc_i2c: Move static data structure to global_data This driver needs a data structure in SRAM before SDRAM is available. This is not alway the case using .data section. Moving this data structure to global_data guarantees it is writable. Signed-off-by: York Sun CC: Troy Kisky --- drivers/i2c/mxc_i2c.c | 18 ++++++++---------- include/asm-generic/global_data.h | 3 +++ 2 files changed, 11 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 595019b3b88..48468d74bdd 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -22,6 +22,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #ifdef I2C_QUIRK_REG struct mxc_i2c_regs { uint8_t iadr; @@ -411,12 +413,6 @@ struct sram_data { struct i2c_parms i2c_data[3]; }; -/* - * For SPL boot some boards need i2c before SDRAM is initialized so force - * variables to live in SRAM - */ -static struct sram_data __attribute__((section(".data"))) srdata; - static void * const i2c_bases[] = { #if defined(CONFIG_MX25) (void *)IMX_I2C_BASE, @@ -445,9 +441,10 @@ void *i2c_get_base(struct i2c_adapter *adap) static struct i2c_parms *i2c_get_parms(void *base) { + struct sram_data *srdata = (void *)gd->srdata; int i = 0; - struct i2c_parms *p = srdata.i2c_data; - while (i < ARRAY_SIZE(srdata.i2c_data)) { + struct i2c_parms *p = srdata->i2c_data; + while (i < ARRAY_SIZE(srdata->i2c_data)) { if (p->base == base) return p; p++; @@ -490,8 +487,9 @@ static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) void bus_i2c_init(void *base, int speed, int unused, int (*idle_bus_fn)(void *p), void *idle_bus_data) { + struct sram_data *srdata = (void *)gd->srdata; int i = 0; - struct i2c_parms *p = srdata.i2c_data; + struct i2c_parms *p = srdata->i2c_data; if (!base) return; for (;;) { @@ -505,7 +503,7 @@ void bus_i2c_init(void *base, int speed, int unused, } p++; i++; - if (i >= ARRAY_SIZE(srdata.i2c_data)) + if (i >= ARRAY_SIZE(srdata->i2c_data)) return; } bus_i2c_set_bus_speed(base, speed); diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 707400e8479..e98b661e358 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -79,6 +79,9 @@ typedef struct global_data { #endif #if defined(CONFIG_SYS_I2C) int cur_i2c_bus; /* current used i2c bus */ +#endif +#ifdef CONFIG_SYS_I2C_MXC + void *srdata[10]; #endif unsigned long timebase_h; unsigned long timebase_l; -- cgit v1.3.1 From a405764c1ec835a41ccda943b9156aee25e15d5e Mon Sep 17 00:00:00 2001 From: Shaveta Leekha Date: Thu, 24 Apr 2014 14:51:23 +0530 Subject: drivers/i2c/fsl_i2c: modify i2c_read to handle multi-byte write Most of the I2C slaves support accesses in the typical style that is : read/write series of bytes at particular address offset. These transactions look like:" (1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP" However there are certain devices which support accesses in terms of the transactions as follows: (2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching: RESTART:Address:Rx:data[0..n2]" Here Txdata is typically a command and some associated data, similarly Rxdata could be command status plus some data received as a response to the command sent. Type (1) transactions are currently supportd in the i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs, RTC, etc fall in this category. To handle type (2) along with type (1) transactions, i2c_read() function has been modified. Signed-off-by: Shaveta Leekha Signed-off-by: Poonam Aggrwal --- drivers/i2c/fsl_i2c.c | 41 ++++++++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 291ad946dba..aa159f8d41d 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -423,18 +423,45 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data, struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; int i = -1; /* signal error */ u8 *a = (u8*)&addr; + int len = alen * -1; if (i2c_wait4bus(adap) < 0) return -1; - if ((!length || alen > 0) - && i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 - && __i2c_write(adap, &a[4 - alen], alen) == alen) - i = 0; /* No error so far */ + /* To handle the need of I2C devices that require to write few bytes + * (more than 4 bytes of address as in the case of else part) + * of data before reading, Negative equivalent of length(bytes to write) + * is passed, but used the +ve part of len for writing data + */ + if (alen < 0) { + /* Generate a START and send the Address and + * the Tx Bytes to the slave. + * "START: Address: Write bytes data[len]" + * IF part supports writing any number of bytes in contrast + * to the else part, which supports writing address offset + * of upto 4 bytes only. + * bytes that need to be written are passed in + * "data", which will eventually keep the data READ, + * after writing the len bytes out of it + */ + if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0) + i = __i2c_write(adap, data, len); + + if (i != len) + return -1; - if (length && - i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0) - i = __i2c_read(adap, data, length); + if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0) + i = __i2c_read(adap, data, length); + } else { + if ((!length || alen > 0) && + i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 && + __i2c_write(adap, &a[4 - alen], alen) == alen) + i = 0; /* No error so far */ + + if (length && + i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0) + i = __i2c_read(adap, data, length); + } writeb(I2C_CR_MEN, &device->cr); -- cgit v1.3.1 From ede4d5e3872d04c75a30c5e234786b012f1c6d34 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 3 Apr 2014 13:55:54 +0900 Subject: usb: ehci: rmobile: Add support ehci host driver of rmobile SoCs The rmobile SoC has usb host controller. This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Marek Vasut --- arch/arm/include/asm/arch-rmobile/ehci-rmobile.h | 147 +++++++++++++++++++++++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-rmobile.c | 130 ++++++++++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 arch/arm/include/asm/arch-rmobile/ehci-rmobile.h create mode 100644 drivers/usb/host/ehci-rmobile.c (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h new file mode 100644 index 00000000000..463654efd33 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * Copyright (C) 2014 Nobuhiro Iwamatsu + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __EHCI_RMOBILE_H__ +#define __EHCI_RMOBILE_H__ + +/* Register offset */ +#define OHCI_OFFSET 0x00 +#define OHCI_SIZE 0x1000 +#define EHCI_OFFSET 0x1000 +#define EHCI_SIZE 0x1000 + +#define EHCI_USBCMD (EHCI_OFFSET + 0x0020) + +/* USBCTR */ +#define DIRPD (1 << 8) +#define PLL_RST (1 << 2) +#define PCICLK_MASK (1 << 1) +#define USBH_RST (1 << 0) + +/* CMND_STS */ +#define SERREN (1 << 8) +#define PERREN (1 << 6) +#define MASTEREN (1 << 2) +#define MEMEN (1 << 1) + +/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */ +#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0)) + +/* AHBPCI_WIN1_CTR */ +#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1)) +#define AHB_CFG_AHBPCI 0x40000000 +#define AHB_CFG_HOST 0x80000000 + +/* AHBPCI_WIN2_CTR */ +#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1)) + +/* PCI_INT_ENABLE */ +#define USBH_PMEEN (1 << 19) +#define USBH_INTBEN (1 << 17) +#define USBH_INTAEN (1 << 16) + +/* AHB_BUS_CTR */ +#define SMODE_READY_CTR (1 << 17) +#define SMODE_READ_BURST (1 << 16) +#define MMODE_HBUSREQ (1 << 7) +#define MMODE_BOUNDARY ((1 << 6)|(1 << 5)) +#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3)) +#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3)) +#define MMODE_WR_INCR (1 << 2) +#define MMODE_BYTE_BURST (1 << 1) +#define MMODE_HTRANS (1 << 0) + +/* PCI_ARBITER_CTR */ +#define PCIBUS_PARK_TIMER 0x00FF0000 +#define PCIBUS_PARK_TIMER_SET 0x00070000 +#define PCIBP_MODE (1 << 12) +#define PCIREQ7 (1 << 7) +#define PCIREQ6 (1 << 6) +#define PCIREQ5 (1 << 5) +#define PCIREQ4 (1 << 4) +#define PCIREQ3 (1 << 3) +#define PCIREQ2 (1 << 2) +#define PCIREQ1 (1 << 1) +#define PCIREQ0 (1 << 0) + +#define SMSTPCR7 0xE615014C +#define SMSTPCR703 (1 << 3) + +/* Init AHB master and slave functions of the host logic */ +#define AHB_BUS_CTR_INIT \ + (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \ + MMODE_BYTE_BURST | MMODE_HTRANS) + +#define USBCTR_WIN_SIZE_1GB 0x800 + +/* PCI Configuration Registers */ +#define PCI_CONF_OHCI_OFFSET 0x10000 +#define PCI_CONF_EHCI_OFFSET 0x10100 +struct ahb_pciconf { + u32 vid_did; + u32 cmnd_sts; + u32 rev; + u32 cache_line; + u32 basead; +}; + +/* PCI Configuration Registers for AHB-PCI Bridge Registers */ +#define PCI_CONF_AHBPCI_OFFSET 0x10000 +struct ahbconf_pci_bridge { + u32 vid_did; /* 0x00 */ + u32 cmnd_sts; + u32 revid_cc; + u32 cls_lt_ht_bist; + u32 basead; /* 0x10 */ + u32 win1_basead; + u32 win2_basead; + u32 dummy0[5]; + u32 ssvdi_ssid; /* 0x2C */ + u32 dummy1[4]; + u32 intr_line_pin; +}; + +/* AHB-PCI Bridge PCI Communication Registers */ +#define AHBPCI_OFFSET 0x10800 +struct ahbcom_pci_bridge { + u32 pciahb_win1_ctr; /* 0x00 */ + u32 pciahb_win2_ctr; + u32 pciahb_dct_ctr; + u32 dummy0; + u32 ahbpci_win1_ctr; /* 0x10 */ + u32 ahbpci_win2_ctr; + u32 dummy1; + u32 ahbpci_dct_ctr; + u32 pci_int_enable; /* 0x20 */ + u32 pci_int_status; + u32 dummy2[2]; + u32 ahb_bus_ctr; /* 0x30 */ + u32 usbctr; + u32 dummy3[2]; + u32 pci_arbiter_ctr; /* 0x40 */ + u32 dummy4; + u32 pci_unit_rev; /* 0x48 */ +}; + +struct rmobile_ehci_reg { + u32 hciversion; /* hciversion/caplength */ + u32 hcsparams; /* hcsparams */ + u32 hccparams; /* hccparams */ + u32 hcsp_portroute; /* hcsp_portroute */ + u32 usbcmd; /* usbcmd */ + u32 usbsts; /* usbsts */ + u32 usbintr; /* usbintr */ + u32 frindex; /* frindex */ + u32 ctrldssegment; /* ctrldssegment */ + u32 periodiclistbase; /* periodiclistbase */ + u32 asynclistaddr; /* asynclistaddr */ + u32 dummy[9]; + u32 configflag; /* configflag */ + u32 portsc; /* portsc */ +}; + +#endif /* __EHCI_RMOBILE_H__ */ diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 578b097fc95..b301e28252b 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o +obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o # xhci obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c new file mode 100644 index 00000000000..049e4c4e6b0 --- /dev/null +++ b/drivers/usb/host/ehci-rmobile.c @@ -0,0 +1,130 @@ +/* + * EHCI HCD (Host Controller Driver) for USB. + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * Copyright (C) 2014 Nobuhiro Iwamatsu + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include "ehci.h" + +#if defined(CONFIG_R8A7740) +static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { + 0xC6700000 +}; +#elif defined(CONFIG_R8A7790) +static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { + 0xEE080000, /* USB0 (EHCI) */ + 0xEE0A0000, /* USB1 */ + 0xEE0C0000, /* USB2 */ + 0xEE000000 /* USB3 (USB3.0 Host)*/ +}; +#elif defined(CONFIG_R8A7791) +static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { + 0xEE080000, /* USB0 (EHCI) */ + 0xEE0C0000, /* USB1 */ + 0xEE000000 /* USB3 (USB3.0 Host)*/ +}; +#else +#error rmobile EHCI USB driver not supported on this platform +#endif + +int ehci_hcd_stop(int index) +{ + int i; + u32 base; + struct ahbcom_pci_bridge *ahbcom_pci; + + base = usb_base_address[index]; + ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); + writel(0, &ahbcom_pci->ahb_bus_ctr); + + /* reset ehci */ + setbits_le32(base + EHCI_USBCMD, CMD_RESET); + for (i = 100; i > 0; i--) { + if (!(readl(base + EHCI_USBCMD) & CMD_RESET)) + break; + udelay(100); + } + + if (!i) + printf("error : ehci(%d) reset failed.\n", index); + + if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1)) + setbits_le32(SMSTPCR7, SMSTPCR703); + + return 0; +} + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + u32 base; + u32 phys_base; + struct rmobile_ehci_reg *rehci; + struct ahbcom_pci_bridge *ahbcom_pci; + struct ahbconf_pci_bridge *ahbconf_pci; + struct ahb_pciconf *ahb_pciconf_ohci; + struct ahb_pciconf *ahb_pciconf_ehci; + uint32_t cap_base; + + base = usb_base_address[index]; + phys_base = base; + if (index == 0) + clrbits_le32(SMSTPCR7, SMSTPCR703); + + rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET); + ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); + ahbconf_pci = + (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET); + ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET); + ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET); + + /* Clock & Reset & Direct Power Down */ + clrsetbits_le32(&ahbcom_pci->usbctr, + (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB); + clrbits_le32(&ahbcom_pci->usbctr, PLL_RST); + + /* AHB-PCI Bridge Communication Registers */ + writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr); + writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, + &ahbcom_pci->pciahb_win1_ctr); + writel(0xf0000000 | PCIAHB_WIN_PREFETCH, + &ahbcom_pci->pciahb_win2_ctr); + writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr); + + setbits_le32(&ahbcom_pci->pci_arbiter_ctr, + PCIBP_MODE | PCIREQ1 | PCIREQ0); + + /* PCI Configuration Registers for AHBPCI */ + writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI, + &ahbcom_pci->ahbpci_win1_ctr); + writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead); + writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); + writel(0xf0000000, &ahbconf_pci->win2_basead); + writel(SERREN | PERREN | MASTEREN | MEMEN, + &ahbconf_pci->cmnd_sts); + + /* PCI Configuration Registers for EHCI */ + writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr); + writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead); + writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead); + writel(SERREN | PERREN | MASTEREN | MEMEN, + &ahb_pciconf_ohci->cmnd_sts); + writel(SERREN | PERREN | MASTEREN | MEMEN, + &ahb_pciconf_ehci->cmnd_sts); + + /* Enable PCI interrupt */ + setbits_le32(&ahbcom_pci->pci_int_enable, + USBH_PMEEN | USBH_INTBEN | USBH_INTAEN); + + *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion); + cap_base = ehci_readl(&(*hccr)->cr_capbase); + *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base)); + + return 0; +} -- cgit v1.3.1 From ea427775677a4147147b64fce4d0ad1acac04e47 Mon Sep 17 00:00:00 2001 From: Adrian Cox Date: Thu, 10 Apr 2014 13:29:45 +0100 Subject: usb: Add endian support macros to interrupt transfers in the EHCI driver. Update the EHCI driver to support interrupt transfers on PowerPC. Signed-off-by: Adrian Cox --- drivers/usb/host/ehci-hcd.c | 56 +++++++++++++++++++++++++-------------------- 1 file changed, 31 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 6017090ebee..eaf59134cb0 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -998,8 +998,8 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) if (!ehcic[index].periodic_list) return -ENOMEM; for (i = 0; i < 1024; i++) { - ehcic[index].periodic_list[i] = (uint32_t)periodic - | QH_LINK_TYPE_QH; + ehcic[index].periodic_list[i] = cpu_to_hc32((uint32_t)periodic + | QH_LINK_TYPE_QH); } flush_dcache_range((uint32_t)ehcic[index].periodic_list, @@ -1089,7 +1089,7 @@ struct int_queue { struct qTD *tds; }; -#define NEXT_QH(qh) (struct QH *)((qh)->qh_link & ~0x1f) +#define NEXT_QH(qh) (struct QH *)(hc32_to_cpu((qh)->qh_link) & ~0x1f) static int enable_periodic(struct ehci_ctrl *ctrl) @@ -1184,41 +1184,47 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, struct qTD *td = result->tds + i; void **buf = &qh->buffer; - qh->qh_link = (uint32_t)(qh+1) | QH_LINK_TYPE_QH; + qh->qh_link = cpu_to_hc32((uint32_t)(qh+1) | QH_LINK_TYPE_QH); if (i == queuesize - 1) - qh->qh_link = QH_LINK_TERMINATE; + qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); - qh->qh_overlay.qt_next = (uint32_t)td; - qh->qh_overlay.qt_altnext = QT_NEXT_TERMINATE; - qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */ + qh->qh_overlay.qt_next = cpu_to_hc32((uint32_t)td); + qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + qh->qh_endpt1 = + cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */ (usb_maxpacket(dev, pipe) << 16) | /* MPS */ (1 << 14) | QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ - (usb_pipedevice(pipe) << 0); - qh->qh_endpt2 = (1 << 30) | /* 1 Tx per mframe */ - (1 << 0); /* S-mask: microframe 0 */ + (usb_pipedevice(pipe) << 0)); + qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */ + (1 << 0)); /* S-mask: microframe 0 */ if (dev->speed == USB_SPEED_LOW || dev->speed == USB_SPEED_FULL) { debug("TT: port: %d, hub address: %d\n", dev->portnr, dev->parent->devnum); - qh->qh_endpt2 |= (dev->portnr << 23) | + qh->qh_endpt2 |= cpu_to_hc32((dev->portnr << 23) | (dev->parent->devnum << 16) | - (0x1c << 8); /* C-mask: microframes 2-4 */ + (0x1c << 8)); /* C-mask: microframes 2-4 */ } - td->qt_next = QT_NEXT_TERMINATE; - td->qt_altnext = QT_NEXT_TERMINATE; + td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); debug("communication direction is '%s'\n", usb_pipein(pipe) ? "in" : "out"); - td->qt_token = (elementsize << 16) | + td->qt_token = cpu_to_hc32((elementsize << 16) | ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */ - 0x80; /* active */ - td->qt_buffer[0] = (uint32_t)buffer + i * elementsize; - td->qt_buffer[1] = (td->qt_buffer[0] + 0x1000) & ~0xfff; - td->qt_buffer[2] = (td->qt_buffer[0] + 0x2000) & ~0xfff; - td->qt_buffer[3] = (td->qt_buffer[0] + 0x3000) & ~0xfff; - td->qt_buffer[4] = (td->qt_buffer[0] + 0x4000) & ~0xfff; + 0x80); /* active */ + td->qt_buffer[0] = + cpu_to_hc32((uint32_t)buffer + i * elementsize); + td->qt_buffer[1] = + cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff); + td->qt_buffer[2] = + cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff); + td->qt_buffer[3] = + cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff); + td->qt_buffer[4] = + cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff); *buf = buffer + i * elementsize; } @@ -1241,7 +1247,7 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, /* hook up to periodic list */ struct QH *list = &ctrl->periodic_queue; result->last->qh_link = list->qh_link; - list->qh_link = (uint32_t)result->first | QH_LINK_TYPE_QH; + list->qh_link = cpu_to_hc32((uint32_t)result->first | QH_LINK_TYPE_QH); flush_dcache_range((uint32_t)result->last, ALIGN_END_ADDR(struct QH, result->last, 1)); @@ -1280,7 +1286,7 @@ void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) /* still active */ invalidate_dcache_range((uint32_t)cur, ALIGN_END_ADDR(struct QH, cur, 1)); - if (cur->qh_overlay.qt_token & 0x80) { + if (cur->qh_overlay.qt_token & cpu_to_hc32(0x80)) { debug("Exit poll_int_queue with no completed intr transfer. " "token is %x\n", cur->qh_overlay.qt_token); return NULL; @@ -1311,7 +1317,7 @@ destroy_int_queue(struct usb_device *dev, struct int_queue *queue) struct QH *cur = &ctrl->periodic_queue; timeout = get_timer(0) + 500; /* abort after 500ms */ - while (!(cur->qh_link & QH_LINK_TERMINATE)) { + while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) { debug("considering %p, with qh_link %x\n", cur, cur->qh_link); if (NEXT_QH(cur) == queue->first) { debug("found candidate. removing from chain\n"); -- cgit v1.3.1 From adfc17bf09ba67cff11472ffa58fc0208defa29c Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Fri, 18 Apr 2014 09:48:24 +0200 Subject: usb:gadget:f_thor: code cleanup in function download_tail() In thor's download_tail() function, dfu_get_entity() is called before each dfu_write() call and the returned entity pointers are the same. So dfu_get_entity() can be called just once and this patch changes this. Signed-off-by: Przemyslaw Marczak Cc: Lukasz Majewski Cc: Marek Vasut Cc: Heiko Schocher Cc: Tom Rini --- drivers/usb/gadget/f_thor.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index f5c0224f213..231f9c0ac7c 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -204,14 +204,14 @@ static long long int download_head(unsigned long long total, static int download_tail(long long int left, int cnt) { + struct dfu_entity *dfu_entity = dfu_get_entity(alt_setting_num); void *transfer_buffer = dfu_get_buf(); int ret; debug("%s: left: %llu cnt: %d\n", __func__, left, cnt); if (left) { - ret = dfu_write(dfu_get_entity(alt_setting_num), - transfer_buffer, left, cnt++); + ret = dfu_write(dfu_entity, transfer_buffer, left, cnt++); if (ret) { error("DFU write failed [%d]: left: %llu", ret, left); return ret; @@ -225,8 +225,7 @@ static int download_tail(long long int left, int cnt) * This also frees memory malloc'ed by dfu_get_buf(), so no explicit * need fo call dfu_free_buf() is needed. */ - ret = dfu_write(dfu_get_entity(alt_setting_num), - transfer_buffer, 0, cnt); + ret = dfu_write(dfu_entity, transfer_buffer, 0, cnt); if (ret) error("DFU write failed [%d] cnt: %d", ret, cnt); -- cgit v1.3.1 From fd2a89b20ba66d76929f672b03f392733fb1b2a6 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Fri, 18 Apr 2014 09:48:25 +0200 Subject: usb:gadget:f_thor: fix write to filesystem by add dfu_flush() Since dfu read/write operations needs to be flushed manually, writing to filesystem on MMC by thor was broken. MMC raw write actually is working fine because current dfu_flush() function writes filesystem only. This commit adds dfu_flush() to f_thor and now filesystem write is working. This change was tested on Trats2 board. Signed-off-by: Przemyslaw Marczak Cc: Lukasz Majewski Cc: Marek Vasut Cc: Heiko Schocher Cc: Tom Rini --- drivers/usb/gadget/f_thor.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index 231f9c0ac7c..ba479450073 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -229,6 +229,12 @@ static int download_tail(long long int left, int cnt) if (ret) error("DFU write failed [%d] cnt: %d", ret, cnt); + ret = dfu_flush(dfu_entity, transfer_buffer, 0, cnt); + if (ret) { + error("DFU flush failed!"); + return ret; + } + return ret; } -- cgit v1.3.1 From 52d45012ff66dee716b8dfcb7d67d3ab54a3208a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 18 Apr 2014 08:54:28 -0500 Subject: usb: handle NULL table in usb_gadget_get_string Allow a NULL table to be passed to usb_gadget_get_string for cases when a string table may not be populated. Signed-off-by: Rob Herring Reviewed-by: Tom Rini Acked-by: Marek Vasut Acked-by: Lukasz Majewski --- drivers/usb/gadget/usbstring.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c index de5fa3f6483..8c3ff64fe35 100644 --- a/drivers/usb/gadget/usbstring.c +++ b/drivers/usb/gadget/usbstring.c @@ -108,6 +108,9 @@ usb_gadget_get_string(struct usb_gadget_strings *table, int id, u8 *buf) struct usb_string *s; int len; + if (!table) + return -EINVAL; + /* descriptor 0 has the language id */ if (id == 0) { buf[0] = 4; -- cgit v1.3.1 From 078d7302ac9263e582d625c377c8289ae07436b7 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 18 Apr 2014 08:54:30 -0500 Subject: usb: musb: fill in usb_gadget_unregister_driver Add missing missing disconnect and unbind calls to the musb gadget driver's usb_gadget_unregister_driver function. Otherwise, any gadget drivers fail to uninitialize and run a 2nd time. Signed-off-by: Rob Herring --- drivers/usb/musb-new/musb_uboot.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c index 05126803c3f..0d7b89fcf6e 100644 --- a/drivers/usb/musb-new/musb_uboot.c +++ b/drivers/usb/musb-new/musb_uboot.c @@ -204,7 +204,10 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) { - /* TODO: implement me */ + if (driver->disconnect) + driver->disconnect(&gadget->g); + if (driver->unbind) + driver->unbind(&gadget->g); return 0; } #endif /* CONFIG_MUSB_GADGET */ -- cgit v1.3.1 From e6e493f341b0488843efe0c5b2c1274997fbbfe8 Mon Sep 17 00:00:00 2001 From: "andrey.konovalov@linaro.org" Date: Tue, 22 Apr 2014 21:23:49 +0400 Subject: exynos: usb: Fix data abort on boards w/o vbus-gpio node in the DT Commit 4a271cb1b4ff doesn't take into account that fdtdec_setup_gpio() returns success when the gpio passed to it is FDT_GPIO_NONE (no gpio node found in the fdtdec_decode_gpio() call). This results in calling gpio_direction_output() on invalid gpio. For this reason executing "usb start" command on Arndale causes data abort in the ehci-exynos driver. Add the fdt_gpio_isvalid() check to fix that problem. Signed-off-by: Andrey Konovalov Cc: Julius Werner Cc: Simon Glass Cc: Minkyu Kang Cc: Marek Vasut --- drivers/usb/host/ehci-exynos.c | 3 ++- drivers/usb/host/xhci-exynos5.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 9356878eb2e..edd91a84a7e 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -197,7 +197,8 @@ int ehci_hcd_init(int index, enum usb_init_type init, #ifdef CONFIG_OF_CONTROL /* setup the Vbus gpio here */ - if (!fdtdec_setup_gpio(&ctx->vbus_gpio)) + if (fdt_gpio_isvalid(&ctx->vbus_gpio) && + !fdtdec_setup_gpio(&ctx->vbus_gpio)) gpio_direction_output(ctx->vbus_gpio.gpio, 1); #endif diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c index 1146d101de4..b4946a3f1cf 100644 --- a/drivers/usb/host/xhci-exynos5.c +++ b/drivers/usb/host/xhci-exynos5.c @@ -298,7 +298,8 @@ int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) #ifdef CONFIG_OF_CONTROL /* setup the Vbus gpio here */ - if (!fdtdec_setup_gpio(&ctx->vbus_gpio)) + if (fdt_gpio_isvalid(&ctx->vbus_gpio) && + !fdtdec_setup_gpio(&ctx->vbus_gpio)) gpio_direction_output(ctx->vbus_gpio.gpio, 1); #endif -- cgit v1.3.1 From 672ad18c276e6c37e2e140294ec35ee96ae47d38 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 24 Apr 2014 10:24:53 +0200 Subject: dfu:fix: Replace wrong return value with proper one This patch remove always false (since we tested ret = 0) ternary operator with ret value returned. Signed-off-by: Lukasz Majewski --- drivers/dfu/dfu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 8a09aafbf24..51b10263b88 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -219,7 +219,7 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) ret = tret; } - return ret = 0 ? size : ret; + return ret; } static int dfu_read_buffer_fill(struct dfu_entity *dfu, void *buf, int size) -- cgit v1.3.1 From f5c03006dd1794362a2be7136fed9e664bc1775b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 24 Apr 2014 17:52:36 -0600 Subject: usb: ci_udc: Support larger packets ci_ep_queue() currently only fills in the page0/page1 fields in the queue item. If the buffer is larger than 4KiB (unaligned) or 8KiB (page-aligned), then this prevents the HW from knowing where to write the balance of the data. Fix this by initializing all 5 pageN pointers, which allows up to 16KiB (potentially non-page-aligned) buffers. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 14b1e9b8bf1..815ce7b262c 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -350,6 +350,9 @@ static int ci_ep_queue(struct usb_ep *ep, item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; item->page0 = (uint32_t)ci_ep->b_buf; item->page1 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x1000; + item->page2 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x2000; + item->page3 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x3000; + item->page4 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x4000; ci_flush_qtd(num); head->next = (unsigned) item; -- cgit v1.3.1 From 8aac6e9c537a2dd0c76acc3a0768ae7af5e166ab Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 24 Apr 2014 17:52:37 -0600 Subject: usb: ci_udc: set ep->req.actual after transfer At least drivers/usb/gadget/storage_common.c expects that ep->req.actual contain the number of bytes actually transferred. (At least in practice, I observed it failing to work correctly unless this was the case). However, ci_udc.c modifies ep->req.length instead. I assume that .length is supposed to represent the allocated buffer size, whereas .actual is supposed to represent the actual number of bytes transferred. In the OUT transaction case, this may happen simply because the host sends a smaller packet than the max possible size, which is quite legal. In the IN case, transferring fewer bytes than requested could presumably happen as an error. Modify handle_ep_complete() to write to .actual rather than modifying .length. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 815ce7b262c..832606f5e44 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -321,7 +321,7 @@ static void ci_debounce(struct ci_ep *ep, int in) if (addr == ba) return; /* not a bounce */ - memcpy(ep->req.buf, ep->b_buf, ep->req.length); + memcpy(ep->req.buf, ep->b_buf, ep->req.actual); free: /* Large payloads use allocated buffer, free it. */ if (ep->b_buf != ep->b_fast) @@ -388,7 +388,7 @@ static void handle_ep_complete(struct ci_ep *ep) num, in ? "in" : "out", item->info, item->page0); len = (item->info >> 16) & 0x7fff; - ep->req.length -= len; + ep->req.actual = ep->req.length - len; ci_debounce(ep, in); DBG("ept%d %s complete %x\n", -- cgit v1.3.1 From 0c51dc6db9ea0e3912d1d3e2d953bc22de433c60 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 24 Apr 2014 17:52:38 -0600 Subject: usb: ci_udc: make PHY initialization conditional usb_gadget_register_driver() currently unconditionally programs PORTSC to select a ULPI PHY. This is incorrect on at least the Tegra boards I am testing with, which use a UTMI PHY for the OTG ports. Make the PHY selection code conditional upon the specific EHCI controller that is in use. Ideally, I believe that the PHY initialization code should be part of ehci_hcd_init() in the relevant EHCI controller driver, or some board- specific function that ehci_hcd_init() calls. For MX6, I'm not sure this PHY initialization code is correct even before this patch, since ehci-mx6's ehci_hcd_init() already configures PORTSC to a board-specific value, and it seems likely that the code in ci_udc.c is incorrectly undoing this. Perhaps this is not an issue if the PHY selection register bits aren't implemented on this instance of the MX6 USB controller? ehci-mxs.c doens't appear to touch PORTSC, so this code is likely still required there. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 832606f5e44..fd751a24263 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -702,7 +702,6 @@ static int ci_udc_probe(void) int usb_gadget_register_driver(struct usb_gadget_driver *driver) { - struct ci_udc *udc; int ret; if (!driver) @@ -717,12 +716,18 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) return ret; ret = ci_udc_probe(); +#if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS) + /* + * FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all + * HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection + */ if (!ret) { - udc = (struct ci_udc *)controller.ctrl->hcor; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; /* select ULPI phy */ writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); } +#endif ret = driver->bind(&controller.gadget); if (ret) { -- cgit v1.3.1 From fcf2ede190e054edcb804ba7786dd024b388a160 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 24 Apr 2014 17:52:39 -0600 Subject: usb: ci_udc: support variants with hostpc register Tegra's USB controller appears to be a variant of the ChipIdea controller; perhaps derived from it, or simply a different version of the IP core to what U-Boot supports today. In this variant, at least the following difference are present: - Some registers are moved about. - Setup transaction completion is reported in a separate 'epsetupstat' register, rather than in 'epstat' (which still exists, perhaps for other transaction types). - USB connection speed is reported in a separate 'hostpc1_devlc' register, rather than 'portsc'. - The registers used by ci_udc.c begin at offset 0x130 from the USB register base, rather than offset 0x140. However, this is handled by the associated EHCI controller driver, since the register address is stored in controller.ctrl->hcor. Introduce define CONFIG_CI_UDC_HAS_HOSTPC to indicate which variant of the controller should be supported. The "HAS_HOSTPC" part of this name mirrors the similar "has_hostpc" field used by the Linux EHCI controller core to represent the presence/absence of the hostpc1_devlc register. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 15 +++++++++++ drivers/usb/gadget/ci_udc.h | 65 ++++++++++++++++++++++++++++++++------------- 2 files changed, 62 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index fd751a24263..02d3fdade86 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -416,7 +416,11 @@ static void handle_setup(void) ci_invalidate_qh(0); memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest)); +#ifdef CONFIG_CI_UDC_HAS_HOSTPC + writel(EPT_RX(0), &udc->epsetupstat); +#else writel(EPT_RX(0), &udc->epstat); +#endif DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), r.bRequestType, r.bRequest, r.wIndex, r.wValue); @@ -483,6 +487,9 @@ static void stop_activity(void) struct ept_queue_head *head; struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; writel(readl(&udc->epcomp), &udc->epcomp); +#ifdef CONFIG_CI_UDC_HAS_HOSTPC + writel(readl(&udc->epsetupstat), &udc->epsetupstat); +#endif writel(readl(&udc->epstat), &udc->epstat); writel(0xffffffff, &udc->epflush); @@ -524,7 +531,11 @@ void udc_irq(void) int max = 64; int speed = USB_SPEED_FULL; +#ifdef CONFIG_CI_UDC_HAS_HOSTPC + bit = (readl(&udc->hostpc1_devlc) >> 25) & 3; +#else bit = (readl(&udc->portsc) >> 26) & 3; +#endif DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full"); if (bit == 2) { speed = USB_SPEED_HIGH; @@ -541,7 +552,11 @@ void udc_irq(void) printf("\n", readl(&udc->epcomp)); if ((n & STS_UI) || (n & STS_UEI)) { +#ifdef CONFIG_CI_UDC_HAS_HOSTPC + n = readl(&udc->epsetupstat); +#else n = readl(&udc->epstat); +#endif if (n & EPT_RX(0)) handle_setup(); diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h index 42f6ef4ab30..4425fd93457 100644 --- a/drivers/usb/gadget/ci_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -8,45 +8,74 @@ #define NUM_ENDPOINTS 6 +#ifdef CONFIG_CI_UDC_HAS_HOSTPC +struct ci_udc { + u32 usbcmd; /* 0x130 */ + u32 usbsts; /* 0x134 */ + u32 pad1[3]; + u32 devaddr; /* 0x144 */ + u32 epinitaddr; /* 0x148 */ + u32 pad2[10]; + u32 portsc; /* 0x174 */ + u32 pad178[(0x1b4 - (0x174 + 4)) / 4]; + u32 hostpc1_devlc; /* 0x1b4 */ + u32 pad1b8[(0x1f8 - (0x1b4 + 4)) / 4]; + u32 usbmode; /* 0x1f8 */ + u32 pad1fc[(0x208 - (0x1f8 + 4)) / 4]; + u32 epsetupstat; /* 0x208 */ + u32 epprime; /* 0x20c */ + u32 epflush; /* 0x210 */ + u32 epstat; /* 0x214 */ + u32 epcomp; /* 0x218 */ + u32 epctrl[16]; /* 0x21c */ +}; +#else struct ci_udc { -#define MICRO_8FRAME 0x8 -#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) -#define USBCMD_FS2 (1 << 15) -#define USBCMD_RST (1 << 1) -#define USBCMD_RUN (1) u32 usbcmd; /* 0x140 */ -#define STS_SLI (1 << 8) -#define STS_URI (1 << 6) -#define STS_PCI (1 << 2) -#define STS_UEI (1 << 1) -#define STS_UI (1 << 0) u32 usbsts; /* 0x144 */ u32 pad1[3]; u32 devaddr; /* 0x154 */ u32 epinitaddr; /* 0x158 */ u32 pad2[10]; -#define PTS_ENABLE 2 -#define PTS(x) (((x) & 0x3) << 30) -#define PFSC (1 << 24) u32 portsc; /* 0x184 */ u32 pad3[8]; -#define USBMODE_DEVICE 2 u32 usbmode; /* 0x1a8 */ u32 epstat; /* 0x1ac */ -#define EPT_TX(x) (1 << (((x) & 0xffff) + 16)) -#define EPT_RX(x) (1 << ((x) & 0xffff)) u32 epprime; /* 0x1b0 */ u32 epflush; /* 0x1b4 */ u32 pad4; u32 epcomp; /* 0x1bc */ + u32 epctrl[16]; /* 0x1c0 */ +}; + +#define PTS_ENABLE 2 +#define PTS(x) (((x) & 0x3) << 30) +#define PFSC (1 << 24) +#endif + +#define MICRO_8FRAME 0x8 +#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) +#define USBCMD_FS2 (1 << 15) +#define USBCMD_RST (1 << 1) +#define USBCMD_RUN (1) + +#define STS_SLI (1 << 8) +#define STS_URI (1 << 6) +#define STS_PCI (1 << 2) +#define STS_UEI (1 << 1) +#define STS_UI (1 << 0) + +#define USBMODE_DEVICE 2 + +#define EPT_TX(x) (1 << (((x) & 0xffff) + 16)) +#define EPT_RX(x) (1 << ((x) & 0xffff)) + #define CTRL_TXE (1 << 23) #define CTRL_TXR (1 << 22) #define CTRL_RXE (1 << 7) #define CTRL_RXR (1 << 6) #define CTRL_TXT_BULK (2 << 18) #define CTRL_RXT_BULK (2 << 2) - u32 epctrl[16]; /* 0x1c0 */ -}; struct ci_ep { struct usb_ep ep; -- cgit v1.3.1 From a022c1e13c01d88edd3436c291630d4b8c642787 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 24 Apr 2014 17:52:40 -0600 Subject: usb: ums: use only 1 buffer for CI_UDC ci_udc.c allocates only a single buffer for each endpoint, which ci_ep_alloc_request() returns as a hard-coded value rather than dynamically allocating. Consequently, storage_common.c must limit itself to using a single buffer at a time. Add a special case to the definition of FSG_NUM_BUFFERS for this. Another option would be to fix ci_ep_alloc_request() to dynamically allocate the buffers like some/all(?) other device mode drivers do. However, I don't think that ci_ep_queue() supports queueing up multiple buffers either yet, and I'm not familiar enough with the controller yet to implement that. As such, any attempt to use multiple buffers simply results in data corruption and other errors. Signed-off-by: Stephen Warren --- drivers/usb/gadget/storage_common.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c index 02803df23c5..74300746b9d 100644 --- a/drivers/usb/gadget/storage_common.c +++ b/drivers/usb/gadget/storage_common.c @@ -311,7 +311,11 @@ static struct fsg_lun *fsg_lun_from_dev(struct device *dev) #define DELAYED_STATUS (EP0_BUFSIZE + 999) /* An impossibly large value */ /* Number of buffers we will use. 2 is enough for double-buffering */ +#ifndef CONFIG_CI_UDC #define FSG_NUM_BUFFERS 2 +#else +#define FSG_NUM_BUFFERS 1 /* ci_udc only allows 1 req per ep at present */ +#endif /* Default size of buffer length. */ #define FSG_BUFLEN ((u32)16384) -- cgit v1.3.1 From 2fc5dab2ed19b6e15ba0726905b6311793397806 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 28 Apr 2014 15:42:00 -0600 Subject: usb: gadget: allow ci_udc to build with new gadget framework Allow ci_udc.o to be built when using the new(?) USB gadget framework, as enabled by CONFIG_USB_GADGET. Note that this duplicates the Makefile entry for ci_udc.o, since it's also included inside #ifdef CONFIG_USB_ETHER. I'm not sure what that define means; perhaps an old style of Ethernet-specific USB gadget implementation? I wonder if the line that this patch adds shouldn't be outside all of the ifdefs, so it stands on its own, similar to how e.g. epautoconf.o is shared between the two? Signed-off-by: Stephen Warren --- drivers/usb/gadget/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 804a2bd412d..896c8d407e4 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -13,6 +13,7 @@ ifdef CONFIG_USB_GADGET obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o +obj-$(CONFIG_CI_UDC) += ci_udc.o obj-$(CONFIG_THOR_FUNCTION) += f_thor.o obj-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o obj-$(CONFIG_DFU_FUNCTION) += f_dfu.o -- cgit v1.3.1 From 75504e9592745021006cb8905b5ff5a51d9d1cb3 Mon Sep 17 00:00:00 2001 From: Mateusz Zalega Date: Wed, 30 Apr 2014 13:07:48 +0200 Subject: usb: dfu: fix boards wo USB cable detection Former usb_cable_connected() patch broke compilation of boards which do not support this feature. I've renamed usb_cable_connected() to g_dnl_usb_cable_connected() and added its default implementation to gadget downloader driver code. There's only one driver of this kind and it's unlikely there'll be another, so there's no point in keeping it in /common. Previously this function was declared in usb.h. I've moved it, since it's more appropriate to keep it in g_dnl.h - usb.h seems to be intended for USB host implementation. Existing code, confronted with default -EOPNOTSUPP return value, continues as if the cable was connected. CONFIG_USB_CABLE_CHECK was removed. Change-Id: Ib9198621adee2811b391c64512f14646cefd0369 Signed-off-by: Mateusz Zalega Acked-by: Marek Vasut Acked-by: Lukasz Majewski --- README | 7 ------- board/samsung/origen/origen.c | 7 ------- board/samsung/trats/trats.c | 4 +--- board/samsung/trats2/trats2.c | 4 +--- board/samsung/universal_c210/universal.c | 7 ------- common/cmd_usb_mass_storage.c | 8 ++++++-- drivers/usb/gadget/f_mass_storage.c | 8 ++++---- drivers/usb/gadget/g_dnl.c | 5 +++++ include/configs/exynos4-dt.h | 1 - include/g_dnl.h | 1 + include/usb.h | 10 ---------- 11 files changed, 18 insertions(+), 44 deletions(-) (limited to 'drivers') diff --git a/README b/README index 12758dc6e79..b973344184f 100644 --- a/README +++ b/README @@ -1484,13 +1484,6 @@ The following options need to be configured: for your device - CONFIG_USBD_PRODUCTID 0xFFFF - Some USB device drivers may need to check USB cable attachment. - In this case you can enable following config in BoardName.h: - CONFIG_USB_CABLE_CHECK - This enables function definition: - - usb_cable_connected() in include/usb.h - Implementation of this function is board-specific. - - ULPI Layer Support: The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via the generic ULPI layer. The generic layer accesses the ULPI PHY diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c index d502f02d3da..a539267a1ca 100644 --- a/board/samsung/origen/origen.c +++ b/board/samsung/origen/origen.c @@ -30,13 +30,6 @@ int board_usb_init(int index, enum usb_init_type init) return 0; } -#ifdef CONFIG_USB_CABLE_CHECK -int usb_cable_connected(void) -{ - return 0; -} -#endif - #ifdef CONFIG_BOARD_EARLY_INIT_F int exynos_early_init_f(void) { diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 7c79e7b73a7..ab0ad1d6505 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -430,8 +430,7 @@ int board_usb_init(int index, enum usb_init_type init) return s3c_udc_probe(&s5pc210_otg_data); } -#ifdef CONFIG_USB_CABLE_CHECK -int usb_cable_connected(void) +int g_dnl_board_usb_cable_connected(void) { struct pmic *muic = pmic_get("MAX8997_MUIC"); if (!muic) @@ -440,7 +439,6 @@ int usb_cable_connected(void) return !!muic->chrg->chrg_type(muic); } #endif -#endif static void pmic_reset(void) { diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index f558ef97a91..47095252a75 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -312,8 +312,7 @@ int board_usb_init(int index, enum usb_init_type init) return s3c_udc_probe(&s5pc210_otg_data); } -#ifdef CONFIG_USB_CABLE_CHECK -int usb_cable_connected(void) +int g_dnl_board_usb_cable_connected(void) { struct pmic *muic = pmic_get("MAX77693_MUIC"); if (!muic) @@ -322,7 +321,6 @@ int usb_cable_connected(void) return !!muic->chrg->chrg_type(muic); } #endif -#endif static int pmic_init_max77686(void) { diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index f9d71b617dd..8e49195fe1c 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -197,13 +197,6 @@ int board_usb_init(int index, enum usb_init_type init) return s3c_udc_probe(&s5pc210_otg_data); } -#ifdef CONFIG_USB_CABLE_CHECK -int usb_cable_connected(void) -{ - return 0; -} -#endif - int exynos_early_init_f(void) { wdt_stop(); diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c index 5f557d5f857..14a5b6ae5ea 100644 --- a/common/cmd_usb_mass_storage.c +++ b/common/cmd_usb_mass_storage.c @@ -45,10 +45,14 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, /* Timeout unit: seconds */ int cable_ready_timeout = UMS_CABLE_READY_TIMEOUT; - if (!usb_cable_connected()) { + if (!g_dnl_board_usb_cable_connected()) { + /* + * Won't execute if we don't know whether the cable is + * connected. + */ puts("Please connect USB cable.\n"); - while (!usb_cable_connected()) { + while (!g_dnl_board_usb_cable_connected()) { if (ctrlc()) { puts("\rCTRL+C - Operation aborted.\n"); goto exit; diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index f896169743c..4fae5cd3b1a 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -243,7 +243,7 @@ #include #include #include -#include +#include #include #include @@ -680,11 +680,11 @@ static int sleep_thread(struct fsg_common *common) /* Handle CTRL+C */ if (ctrlc()) return -EPIPE; -#ifdef CONFIG_USB_CABLE_CHECK + /* Check cable connection */ - if (!usb_cable_connected()) + if (!g_dnl_board_usb_cable_connected()) return -EIO; -#endif + k = 0; } diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index dd95afe86a5..973d7378b52 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -152,6 +152,11 @@ __weak int g_dnl_get_board_bcd_device_number(int gcnum) return gcnum; } +__weak int g_dnl_board_usb_cable_connected(void) +{ + return -EOPNOTSUPP; +} + static int g_dnl_get_bcd_device_number(struct usb_composite_dev *cdev) { struct usb_gadget *gadget = cdev->gadget; diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h index 2040bf7784d..cbd2d204cf9 100644 --- a/include/configs/exynos4-dt.h +++ b/include/configs/exynos4-dt.h @@ -127,7 +127,6 @@ #define CONFIG_USB_GADGET_S3C_UDC_OTG #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 -#define CONFIG_USB_CABLE_CHECK #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE diff --git a/include/g_dnl.h b/include/g_dnl.h index 8f813c21ee6..f4e8d1089e6 100644 --- a/include/g_dnl.h +++ b/include/g_dnl.h @@ -11,6 +11,7 @@ #include #include int g_dnl_bind_fixup(struct usb_device_descriptor *, const char *); +int g_dnl_board_usb_cable_connected(void); int g_dnl_register(const char *s); void g_dnl_unregister(void); void g_dnl_set_serialnumber(char *); diff --git a/include/usb.h b/include/usb.h index 736730e8964..d9fedeeff7d 100644 --- a/include/usb.h +++ b/include/usb.h @@ -197,16 +197,6 @@ int board_usb_init(int index, enum usb_init_type init); */ int board_usb_cleanup(int index, enum usb_init_type init); -/* - * If CONFIG_USB_CABLE_CHECK is set then this function - * should be defined in board file. - * - * @return 1 if cable is connected and 0 otherwise. - */ -#ifdef CONFIG_USB_CABLE_CHECK -int usb_cable_connected(void); -#endif - #ifdef CONFIG_USB_STORAGE #define USB_MAX_STOR_DEV 5 -- cgit v1.3.1 From 711b931f90e44ff1248cd73c15f64485470d86ff Mon Sep 17 00:00:00 2001 From: Mateusz Zalega Date: Mon, 28 Apr 2014 21:13:24 +0200 Subject: dfu: mmc: raw data write fix When user attempted to perform a raw write using DFU (vide dfu_fill_entity_mmc) with MMC interface not initialized before, get_mmc_blk_size() reported invalid (zero) block size - it wasn't possible to write ie. a new u-boot image. This commit fixes that by initializing MMC device before use in dfu_fill_entity_mmc(). While fixing initialization sequence, I had to change about half of dfu_fill_entity_mmc's body, so I refactored it on the way to make it, IMHO, considerably more comprehensible. Being left as dead code, get_mmc_blk_size() was removed. Tested on Samsung Goni. Signed-off-by: Mateusz Zalega Signed-off-by: Kyungmin Park Acked-by: Lukasz Majewski Acked-by: Tom Rini Cc: Minkyu Kang --- drivers/dfu/dfu_mmc.c | 105 +++++++++++++++++++++++++++++++------------------- include/dfu.h | 5 --- 2 files changed, 65 insertions(+), 45 deletions(-) (limited to 'drivers') diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 651cfff5b3b..b41785dfc71 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -184,66 +184,91 @@ int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, return ret; } +/* + * @param s Parameter string containing space-separated arguments: + * 1st: + * raw (raw read/write) + * fat (files) + * ext4 (^) + * part (partition image) + * 2nd and 3rd: + * lba_start and lba_size, for raw write + * mmc_dev and mmc_part, for filesystems and part + */ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) { - int dev, part; - struct mmc *mmc; - block_dev_desc_t *blk_dev; - disk_partition_t partinfo; - char *st; + const char *entity_type; + size_t second_arg; + size_t third_arg; - dfu->dev_type = DFU_DEV_MMC; - st = strsep(&s, " "); - if (!strcmp(st, "mmc")) { - dfu->layout = DFU_RAW_ADDR; - dfu->data.mmc.lba_start = simple_strtoul(s, &s, 16); - dfu->data.mmc.lba_size = simple_strtoul(++s, &s, 16); - dfu->data.mmc.lba_blk_size = get_mmc_blk_size(dfu->dev_num); - } else if (!strcmp(st, "fat")) { - dfu->layout = DFU_FS_FAT; - } else if (!strcmp(st, "ext4")) { - dfu->layout = DFU_FS_EXT4; - } else if (!strcmp(st, "part")) { - - dfu->layout = DFU_RAW_ADDR; + struct mmc *mmc; - dev = simple_strtoul(s, &s, 10); - s++; - part = simple_strtoul(s, &s, 10); + const char *argv[3]; + const char **parg = argv; - mmc = find_mmc_device(dev); - if (mmc == NULL || mmc_init(mmc)) { - printf("%s: could not find mmc device #%d!\n", - __func__, dev); + for (; parg < argv + sizeof(argv) / sizeof(*argv); ++parg) { + *parg = strsep(&s, " "); + if (*parg == NULL) { + error("Invalid number of arguments.\n"); return -ENODEV; } + } - blk_dev = &mmc->block_dev; - if (get_partition_info(blk_dev, part, &partinfo) != 0) { - printf("%s: could not find partition #%d on mmc device #%d!\n", - __func__, part, dev); + entity_type = argv[0]; + second_arg = simple_strtoul(argv[1], NULL, 16); + third_arg = simple_strtoul(argv[2], NULL, 16); + + mmc = find_mmc_device(dfu->dev_num); + if (mmc == NULL) { + error("Couldn't find MMC device no. %d.\n", dfu->dev_num); + return -ENODEV; + } + + if (mmc_init(mmc)) { + error("Couldn't init MMC device.\n"); + return -ENODEV; + } + + if (!strcmp(entity_type, "raw")) { + dfu->layout = DFU_RAW_ADDR; + dfu->data.mmc.lba_start = second_arg; + dfu->data.mmc.lba_size = third_arg; + dfu->data.mmc.lba_blk_size = mmc->read_bl_len; + } else if (!strcmp(entity_type, "part")) { + disk_partition_t partinfo; + block_dev_desc_t *blk_dev = &mmc->block_dev; + int mmcdev = second_arg; + int mmcpart = third_arg; + + if (get_partition_info(blk_dev, mmcpart, &partinfo) != 0) { + error("Couldn't find part #%d on mmc device #%d\n", + mmcpart, mmcdev); return -ENODEV; } - dfu->data.mmc.lba_start = partinfo.start; - dfu->data.mmc.lba_size = partinfo.size; - dfu->data.mmc.lba_blk_size = partinfo.blksz; - + dfu->layout = DFU_RAW_ADDR; + dfu->data.mmc.lba_start = partinfo.start; + dfu->data.mmc.lba_size = partinfo.size; + dfu->data.mmc.lba_blk_size = partinfo.blksz; + } else if (!strcmp(entity_type, "fat")) { + dfu->layout = DFU_FS_FAT; + } else if (!strcmp(entity_type, "ext4")) { + dfu->layout = DFU_FS_EXT4; } else { - printf("%s: Memory layout (%s) not supported!\n", __func__, st); + error("Memory layout (%s) not supported!\n", entity_type); return -ENODEV; } - if (dfu->layout == DFU_FS_EXT4 || dfu->layout == DFU_FS_FAT) { - dfu->data.mmc.dev = simple_strtoul(s, &s, 10); - dfu->data.mmc.part = simple_strtoul(++s, &s, 10); + /* if it's NOT a raw write */ + if (strcmp(entity_type, "raw")) { + dfu->data.mmc.dev = second_arg; + dfu->data.mmc.part = third_arg; } + dfu->dev_type = DFU_DEV_MMC; dfu->read_medium = dfu_read_medium_mmc; dfu->write_medium = dfu_write_medium_mmc; dfu->flush_medium = dfu_flush_medium_mmc; - - /* initial state */ dfu->inited = 0; return 0; diff --git a/include/dfu.h b/include/dfu.h index 6c71ecbe355..dcd3215d06b 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -64,11 +64,6 @@ struct ram_internal_data { unsigned int size; }; -static inline unsigned int get_mmc_blk_size(int dev) -{ - return find_mmc_device(dev)->read_bl_len; -} - #define DFU_NAME_SIZE 32 #define DFU_CMD_BUF_SIZE 128 #ifndef CONFIG_SYS_DFU_DATA_BUF_SIZE -- cgit v1.3.1 From b7d4259af298402b7d65c876d8e39e5b9e6c8934 Mon Sep 17 00:00:00 2001 From: Mateusz Zalega Date: Mon, 28 Apr 2014 21:13:25 +0200 Subject: dfu: mmc: change offset base handling Previously offsets handled by dfu_fill_entity_mmc(), defined in boards' CONFIG_DFU_ALT were treated as hexadecimal regardless of their prefix, which sometimes led to confusion. This patch forces usage of explicit numerical base prefixes. Signed-off-by: Mateusz Zalega Acked-by: Lukasz Majewski Cc: Tom Rini Cc: Minkyu Kang --- drivers/dfu/dfu_mmc.c | 8 ++++++-- include/configs/am335x_evm.h | 8 ++++---- include/configs/trats.h | 4 ++-- include/configs/trats2.h | 4 ++-- 4 files changed, 14 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index b41785dfc71..5e10ea7e664 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -215,8 +215,12 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) } entity_type = argv[0]; - second_arg = simple_strtoul(argv[1], NULL, 16); - third_arg = simple_strtoul(argv[2], NULL, 16); + /* + * Base 0 means we'll accept (prefixed with 0x or 0) base 16, 8, + * with default 10. + */ + second_arg = simple_strtoul(argv[1], NULL, 0); + third_arg = simple_strtoul(argv[2], NULL, 0); mmc = find_mmc_device(dfu->dev_num); if (mmc == NULL) { diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ea9e758a696..4147f9f3691 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -320,10 +320,10 @@ "boot part 0 1;" \ "rootfs part 0 2;" \ "MLO fat 0 1;" \ - "MLO.raw mmc 100 100;" \ - "u-boot.img.raw mmc 300 400;" \ - "spl-os-args.raw mmc 80 80;" \ - "spl-os-image.raw mmc 900 2000;" \ + "MLO.raw mmc 0x100 0x100;" \ + "u-boot.img.raw mmc 0x300 0x400;" \ + "spl-os-args.raw mmc 0x80 0x80;" \ + "spl-os-image.raw mmc 0x900 0x2000;" \ "spl-os-args fat 0 1;" \ "spl-os-image fat 0 1;" \ "u-boot.img fat 0 1;" \ diff --git a/include/configs/trats.h b/include/configs/trats.h index 5d8bd605836..c4afecf3dab 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -101,7 +101,7 @@ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ #define CONFIG_DFU_ALT \ - "u-boot mmc 80 400;" \ + "u-boot raw 0x80 0x400;" \ "uImage ext4 0 2;" \ "modem.bin ext4 0 2;" \ "exynos4210-trats.dtb ext4 0 2;" \ @@ -112,7 +112,7 @@ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ ""PARTS_UMS" part 0 7;" \ - "params.bin mmc 0x38 0x8\0" + "params.bin raw 0x38 0x8\0" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 53d449c291a..14def7d16e8 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -91,7 +91,7 @@ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ #define CONFIG_DFU_ALT \ - "u-boot mmc 80 800;" \ + "u-boot raw 0x80 0x800;" \ "uImage ext4 0 2;" \ "modem.bin ext4 0 2;" \ "exynos4412-trats2.dtb ext4 0 2;" \ @@ -102,7 +102,7 @@ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ ""PARTS_UMS" part 0 7;" \ - "params.bin mmc 0x38 0x8\0" + "params.bin raw 0x38 0x8\0" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ -- cgit v1.3.1 From c4d0e856047f2689278ffea63a562c4f22a35ee3 Mon Sep 17 00:00:00 2001 From: Mateusz Zalega Date: Mon, 28 Apr 2014 21:13:28 +0200 Subject: USB: gadget: added a saner gadget downloader registration API Preprocessor definitions and hardcoded implementation selection in g_dnl core were replaced by a linker list made of (usb_function_name, bind_callback) pairs. Signed-off-by: Mateusz Zalega Acked-by: Lukasz Majewski Acked-by: Marek Vasut --- common/cmd_dfu.c | 3 +- common/cmd_thordown.c | 3 +- common/cmd_usb_mass_storage.c | 2 +- drivers/usb/gadget/f_dfu.c | 3 ++ drivers/usb/gadget/f_mass_storage.c | 3 ++ drivers/usb/gadget/f_thor.c | 2 ++ drivers/usb/gadget/g_dnl.c | 64 ++++++++++++++++--------------------- include/dfu.h | 7 ---- include/g_dnl.h | 23 +++++++++++++ include/thor.h | 8 ----- include/usb_mass_storage.h | 8 ----- 11 files changed, 62 insertions(+), 64 deletions(-) (limited to 'drivers') diff --git a/common/cmd_dfu.c b/common/cmd_dfu.c index 5547678208a..a03538dabb3 100644 --- a/common/cmd_dfu.c +++ b/common/cmd_dfu.c @@ -22,7 +22,6 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char *interface = argv[2]; char *devstring = argv[3]; - char *s = "dfu"; int ret, i = 0; ret = dfu_init_env_entities(interface, simple_strtoul(devstring, @@ -38,7 +37,7 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int controller_index = simple_strtoul(usb_controller, NULL, 0); board_usb_init(controller_index, USB_INIT_DEVICE); - g_dnl_register(s); + g_dnl_register("usb_dnl_dfu"); while (1) { if (dfu_reset()) /* diff --git a/common/cmd_thordown.c b/common/cmd_thordown.c index c4b35114587..2dd750928e4 100644 --- a/common/cmd_thordown.c +++ b/common/cmd_thordown.c @@ -22,7 +22,6 @@ int do_thor_down(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char *interface = argv[2]; char *devstring = argv[3]; - const char *s = "thor"; int ret; puts("TIZEN \"THOR\" Downloader\n"); @@ -40,7 +39,7 @@ int do_thor_down(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) goto exit; } - g_dnl_register(s); + g_dnl_register("usb_dnl_thor"); ret = thor_init(); if (ret) { diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c index 14a5b6ae5ea..d8d9efd4f62 100644 --- a/common/cmd_usb_mass_storage.c +++ b/common/cmd_usb_mass_storage.c @@ -40,7 +40,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, return CMD_RET_FAILURE; } - g_dnl_register("ums"); + g_dnl_register("usb_dnl_ums"); /* Timeout unit: seconds */ int cable_ready_timeout = UMS_CABLE_READY_TIMEOUT; diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index de75ff13390..1b1e1793d92 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -24,6 +24,7 @@ #include #include +#include #include "f_dfu.h" struct f_dfu { @@ -817,3 +818,5 @@ int dfu_add(struct usb_configuration *c) return dfu_bind_config(c); } + +DECLARE_GADGET_BIND_CALLBACK(usb_dnl_dfu, dfu_add); diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index 4fae5cd3b1a..6374bb953a9 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -255,6 +255,7 @@ #include #include #include +#include /*------------------------------------------------------------------------*/ @@ -2778,3 +2779,5 @@ int fsg_init(struct ums *ums_dev) return 0; } + +DECLARE_GADGET_BIND_CALLBACK(usb_dnl_ums, fsg_add); diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index ba479450073..feef9e4619c 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -1004,3 +1004,5 @@ int thor_add(struct usb_configuration *c) debug("%s:\n", __func__); return thor_func_init(c); } + +DECLARE_GADGET_BIND_CALLBACK(usb_dnl_thor, thor_add); diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index 973d7378b52..743bae535ac 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -41,7 +41,6 @@ #define DRIVER_VERSION "usb_dnl 2.0" -static const char shortname[] = "usb_dnl_"; static const char product[] = "USB download gadget"; static char g_dnl_serial[MAX_STRING_SERIAL]; static const char manufacturer[] = CONFIG_G_DNL_MANUFACTURER; @@ -96,29 +95,36 @@ static int g_dnl_unbind(struct usb_composite_dev *cdev) free(cdev->config); cdev->config = NULL; debug("%s: calling usb_gadget_disconnect for " - "controller '%s'\n", shortname, gadget->name); + "controller '%s'\n", __func__, gadget->name); usb_gadget_disconnect(gadget); return 0; } +static inline struct g_dnl_bind_callback *g_dnl_bind_callback_first(void) +{ + return ll_entry_start(struct g_dnl_bind_callback, + g_dnl_bind_callbacks); +} + +static inline struct g_dnl_bind_callback *g_dnl_bind_callback_end(void) +{ + return ll_entry_end(struct g_dnl_bind_callback, + g_dnl_bind_callbacks); +} + static int g_dnl_do_config(struct usb_configuration *c) { const char *s = c->cdev->driver->name; - int ret = -1; + struct g_dnl_bind_callback *callback = g_dnl_bind_callback_first(); debug("%s: configuration: 0x%p composite dev: 0x%p\n", __func__, c, c->cdev); - printf("GADGET DRIVER: %s\n", s); - if (!strcmp(s, "usb_dnl_dfu")) - ret = dfu_add(c); - else if (!strcmp(s, "usb_dnl_ums")) - ret = fsg_add(c); - else if (!strcmp(s, "usb_dnl_thor")) - ret = thor_add(c); - - return ret; + for (; callback != g_dnl_bind_callback_end(); callback++) + if (!strcmp(s, callback->usb_function_name)) + return callback->fptr(c); + return -ENODEV; } static int g_dnl_config_register(struct usb_composite_dev *cdev) @@ -208,12 +214,12 @@ static int g_dnl_bind(struct usb_composite_dev *cdev) device_desc.bcdDevice = cpu_to_le16(gcnum); else { debug("%s: controller '%s' not recognized\n", - shortname, gadget->name); + __func__, gadget->name); device_desc.bcdDevice = __constant_cpu_to_le16(0x9999); } debug("%s: calling usb_gadget_connect for " - "controller '%s'\n", shortname, gadget->name); + "controller '%s'\n", __func__, gadget->name); usb_gadget_connect(gadget); return 0; @@ -232,36 +238,22 @@ static struct usb_composite_driver g_dnl_driver = { .unbind = g_dnl_unbind, }; -int g_dnl_register(const char *type) +/* + * NOTICE: + * Registering via USB function name won't be necessary after rewriting + * g_dnl to support multiple USB functions. + */ +int g_dnl_register(const char *name) { - /* The largest function name is 4 */ - static char name[sizeof(shortname) + 4]; - int ret; - - if (!strcmp(type, "dfu")) { - strcpy(name, shortname); - strcat(name, type); - } else if (!strcmp(type, "ums")) { - strcpy(name, shortname); - strcat(name, type); - } else if (!strcmp(type, "thor")) { - strcpy(name, shortname); - strcat(name, type); - } else { - printf("%s: unknown command: %s\n", __func__, type); - return -EINVAL; - } + int ret = usb_composite_register(&g_dnl_driver); + debug("%s: g_dnl_driver.name = %s\n", __func__, name); g_dnl_driver.name = name; - debug("%s: g_dnl_driver.name: %s\n", __func__, g_dnl_driver.name); - ret = usb_composite_register(&g_dnl_driver); - if (ret) { printf("%s: failed!, error: %d\n", __func__, ret); return ret; } - return 0; } diff --git a/include/dfu.h b/include/dfu.h index dcd3215d06b..240916854a1 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -168,12 +168,5 @@ static inline int dfu_fill_entity_ram(struct dfu_entity *dfu, char *s) } #endif -#ifdef CONFIG_DFU_FUNCTION int dfu_add(struct usb_configuration *c); -#else -int dfu_add(struct usb_configuration *c) -{ - return 0; -} -#endif #endif /* __DFU_ENTITY_H_ */ diff --git a/include/g_dnl.h b/include/g_dnl.h index f4e8d1089e6..1b1b35e0e1c 100644 --- a/include/g_dnl.h +++ b/include/g_dnl.h @@ -10,6 +10,29 @@ #include #include +#include +#include + +/* + * @usb_fname: unescaped USB function name + * @callback_ptr: bind callback, one per function name + */ +#define DECLARE_GADGET_BIND_CALLBACK(usb_fname, callback_ptr) \ + ll_entry_declare(struct g_dnl_bind_callback, \ + __usb_function_name_##usb_fname, \ + g_dnl_bind_callbacks) = { \ + .usb_function_name = #usb_fname, \ + .fptr = callback_ptr \ + } + +typedef int (*g_dnl_bind_callback_f)(struct usb_configuration *); + +/* used in Gadget downloader callback linker list */ +struct g_dnl_bind_callback { + const char *usb_function_name; + g_dnl_bind_callback_f fptr; +}; + int g_dnl_bind_fixup(struct usb_device_descriptor *, const char *); int g_dnl_board_usb_cable_connected(void); int g_dnl_register(const char *s); diff --git a/include/thor.h b/include/thor.h index afeade45646..5051be714bd 100644 --- a/include/thor.h +++ b/include/thor.h @@ -15,13 +15,5 @@ int thor_handle(void); int thor_init(void); - -#ifdef CONFIG_THOR_FUNCTION int thor_add(struct usb_configuration *c); -#else -int thor_add(struct usb_configuration *c) -{ - return 0; -} -#endif #endif /* __THOR_H_ */ diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h index 058dcf11740..ed460644c1f 100644 --- a/include/usb_mass_storage.h +++ b/include/usb_mass_storage.h @@ -40,13 +40,5 @@ int fsg_init(struct ums *); void fsg_cleanup(void); struct ums *ums_init(unsigned int); int fsg_main_thread(void *); - -#ifdef CONFIG_USB_GADGET_MASS_STORAGE int fsg_add(struct usb_configuration *c); -#else -int fsg_add(struct usb_configuration *c) -{ - return 0; -} -#endif #endif /* __USB_MASS_STORAGE_H__ */ -- cgit v1.3.1 From 25fbf96b24fd3fe0a5252c374b445be32f42b0c8 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 1 May 2014 15:45:16 -0600 Subject: USB: gadget: save driver name before registering it g_dnl_register() currently first attempts to register a composite driver by name, and then saves the driver name once it's registered. Internally to the registration code, g_dnl_do_config() is called and attempts to compare the composite device's name with the list of known device names. This fails since the composite device's name has not yet been stored. This means that the first time "ums 0 0" is run, it fails, but subsequent attempts succeed. Re-order the name-saving and registration code to solve this. Fixes: e5b834e07f51 ("USB: gadget: added a saner gadget downloader registration API") Signed-off-by: Stephen Warren --- drivers/usb/gadget/g_dnl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index 743bae535ac..25611acd607 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -245,11 +245,12 @@ static struct usb_composite_driver g_dnl_driver = { */ int g_dnl_register(const char *name) { - int ret = usb_composite_register(&g_dnl_driver); + int ret; debug("%s: g_dnl_driver.name = %s\n", __func__, name); g_dnl_driver.name = name; + ret = usb_composite_register(&g_dnl_driver); if (ret) { printf("%s: failed!, error: %d\n", __func__, ret); return ret; -- cgit v1.3.1 From c1a9fa4ba67971f45ee106250340963cef7d020a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 25 Feb 2014 10:25:38 +0100 Subject: net: zynq: Use predefined macros instead of hardcoded value MII is used by this driver. Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 101489c9947..08056a4bac1 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -338,7 +338,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) phy_detection(dev); /* interface - look at tsec */ - phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); + phydev = phy_connect(priv->bus, priv->phyaddr, dev, + PHY_INTERFACE_MODE_MII); phydev->supported = supported | ADVERTISED_Pause | ADVERTISED_Asym_Pause; -- cgit v1.3.1 From 2fd2489b7aa36478433ae2a1f4de9f66e0a80322 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 14:17:38 +0200 Subject: net: zynq: Fix sparse warnings in gem Add missing header. Warnings: drivers/net/zynq_gem.c:491:5: warning: symbol 'zynq_gem_initialize' was not declared. Should it be static? drivers/net/zynq_gem.c:542:5: warning: symbol 'zynq_gem_of_init' was not declared. Should it be static? Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 08056a4bac1..3cadd23bb46 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include -- cgit v1.3.1 From 6c4da359960bd15c1adbda2fc9639f2791f04e44 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 13:45:08 +0200 Subject: serial: zynq: Remove sparse warnings Warnings: drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_init' was not declared. Should it be static? drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_setbrg' was not declared. Should it be static? drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_getc' was not declared. Should it be static? drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_tstc' was not declared. Should it be static? drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_putc' was not declared. Should it be static? drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_puts' was not declared. Should it be static? drivers/serial/serial_zynq.c:182:22: warning: symbol 'uart_zynq_serial0_device' was not declared. Should it be static? drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_init' was not declared. Should it be static? drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_setbrg' was not declared. Should it be static? drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_getc' was not declared. Should it be static? drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_tstc' was not declared. Should it be static? drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_putc' was not declared. Should it be static? drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_puts' was not declared. Should it be static? drivers/serial/serial_zynq.c:185:22: warning: symbol 'uart_zynq_serial1_device' was not declared. Should it be static? Signed-off-by: Michal Simek --- drivers/serial/serial_zynq.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 53a8af02d64..3ce9a2731e9 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -153,17 +153,17 @@ static int uart_zynq_serial_getc(const int port) /* Multi serial device functions */ #define DECLARE_PSSERIAL_FUNCTIONS(port) \ - int uart_zynq##port##_init(void) \ + static int uart_zynq##port##_init(void) \ { return uart_zynq_serial_init(port); } \ - void uart_zynq##port##_setbrg(void) \ + static void uart_zynq##port##_setbrg(void) \ { return uart_zynq_serial_setbrg(port); } \ - int uart_zynq##port##_getc(void) \ + static int uart_zynq##port##_getc(void) \ { return uart_zynq_serial_getc(port); } \ - int uart_zynq##port##_tstc(void) \ + static int uart_zynq##port##_tstc(void) \ { return uart_zynq_serial_tstc(port); } \ - void uart_zynq##port##_putc(const char c) \ + static void uart_zynq##port##_putc(const char c) \ { uart_zynq_serial_putc(c, port); } \ - void uart_zynq##port##_puts(const char *s) \ + static void uart_zynq##port##_puts(const char *s) \ { uart_zynq_serial_puts(s, port); } /* Serial device descriptor */ @@ -179,10 +179,10 @@ static int uart_zynq_serial_getc(const int port) } DECLARE_PSSERIAL_FUNCTIONS(0); -struct serial_device uart_zynq_serial0_device = +static struct serial_device uart_zynq_serial0_device = INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); DECLARE_PSSERIAL_FUNCTIONS(1); -struct serial_device uart_zynq_serial1_device = +static struct serial_device uart_zynq_serial1_device = INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); #ifdef CONFIG_OF_CONTROL -- cgit v1.3.1 From 870e0bda43c9ea18a5f2fae5e48905c3b44ea18b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 13:46:28 +0200 Subject: serial: zynq: Fix typo in suffix function name 's/zynq_serial_initalize/zynq_serial_initialize/g' serial_initialize is used by all serial drivers. Signed-off-by: Michal Simek --- drivers/serial/serial.c | 4 ++-- drivers/serial/serial_zynq.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index df05bde4610..c4fb59cfb31 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -117,7 +117,7 @@ serial_initfunc(ns16550_serial_initialize); serial_initfunc(pxa_serial_initialize); serial_initfunc(s3c24xx_serial_initialize); serial_initfunc(s5p_serial_initialize); -serial_initfunc(zynq_serial_initalize); +serial_initfunc(zynq_serial_initialize); serial_initfunc(bfin_serial_initialize); serial_initfunc(bfin_jtag_initialize); serial_initfunc(mpc512x_serial_initialize); @@ -214,7 +214,7 @@ void serial_initialize(void) bfin_serial_initialize(); bfin_jtag_initialize(); uartlite_serial_initialize(); - zynq_serial_initalize(); + zynq_serial_initialize(); au1x00_serial_initialize(); asc_serial_initialize(); jz_serial_initialize(); diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 3ce9a2731e9..1ff27d5f488 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -223,7 +223,7 @@ __weak struct serial_device *default_serial_console(void) } #endif -void zynq_serial_initalize(void) +void zynq_serial_initialize(void) { serial_register(&uart_zynq_serial0_device); serial_register(&uart_zynq_serial1_device); -- cgit v1.3.1