From 75b6cd97dd41b11c212fccf545e346c38248f8a2 Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Mon, 13 Mar 2023 18:12:23 +0530 Subject: phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified It's possible that the Type-C plug orientation on the DIR line will be implemented through hardware design. In that situation, there won't be an external GPIO line available, but the driver still needs to address this since the DT won't use the typec-dir-gpios property. Add code to handle LN10 Type-C swap if typec-dir-gpios property is not specified in DT. Signed-off-by: Sinthu Raja --- drivers/phy/ti/phy-j721e-wiz.c | 38 +++++++++++++++++++++++++++++--------- 1 file changed, 29 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 6646b15d410..8e29f39cd8c 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -329,6 +329,7 @@ struct wiz { u32 num_lanes; struct gpio_desc *gpio_typec_dir; u32 lane_phy_type[WIZ_MAX_LANES]; + u32 master_lane_num[WIZ_MAX_LANES]; struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; unsigned int id; const struct wiz_data *data; @@ -586,14 +587,31 @@ static int wiz_reset_deassert(struct reset_ctl *reset_ctl) return ret; /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ - if (id == 0 && wiz->gpio_typec_dir) { - if (dm_gpio_get_value(wiz->gpio_typec_dir)) { - regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, - WIZ_SERDES_TYPEC_LN10_SWAP, - WIZ_SERDES_TYPEC_LN10_SWAP); - } else { - regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, - WIZ_SERDES_TYPEC_LN10_SWAP, 0); + if (id == 0) { + if (wiz->gpio_typec_dir) { + if (dm_gpio_get_value(wiz->gpio_typec_dir)) { + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN10_SWAP, + WIZ_SERDES_TYPEC_LN10_SWAP); + } else { + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN10_SWAP, 0); + } + } + } else { + /* if no typec-dir gpio was specified and PHY type is + * USB3 with master lane number is '0', set LN10 SWAP + * bit to '1' + */ + u32 num_lanes = wiz->num_lanes; + int i; + + for (i = 0; i < num_lanes; i++) { + if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) + if (wiz->master_lane_num[i] == 0) + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN10_SWAP, + WIZ_SERDES_TYPEC_LN10_SWAP); } } @@ -1100,8 +1118,10 @@ static int wiz_get_lane_phy_types(struct udevice *dev, struct wiz *wiz) dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, reg, reg + num_lanes - 1, phy_type); - for (i = reg; i < reg + num_lanes; i++) + for (i = reg; i < reg + num_lanes; i++) { wiz->lane_phy_type[i] = phy_type; + wiz->master_lane_num[i] = reg; + } } return 0; -- cgit v1.3.1 From 3d0f2e37c57b0d2f60e0b985d7006220d94bd9b0 Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Mon, 13 Mar 2023 18:12:24 +0530 Subject: phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the USB PHY that is integrated into the SerDes IP. The WIZ control register has to be configured to support this lane swap feature. The support for swapping lanes 2 and 3 is missing and therefore add support to configure the control register to swap between lanes 2 and 3 if PHY type is USB. Signed-off-by: Sinthu Raja --- drivers/phy/ti/phy-j721e-wiz.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 8e29f39cd8c..23397175d34 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -39,6 +39,7 @@ #define WIZ_DIV_NUM_CLOCKS_10G 1 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) +#define WIZ_SERDES_TYPEC_LN23_SWAP BIT(31) enum wiz_lane_standard_mode { LANE_MODE_GEN1, @@ -65,6 +66,14 @@ enum wiz_clock_input { WIZ_EXT_REFCLK1, }; +/* + * List of master lanes used for lane swapping + */ +enum wiz_typec_master_lane { + LANE0 = 0, + LANE2 = 2, +}; + static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); static const struct reg_field pll1_refclk_mux_sel = @@ -607,11 +616,22 @@ static int wiz_reset_deassert(struct reset_ctl *reset_ctl) int i; for (i = 0; i < num_lanes; i++) { - if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) - if (wiz->master_lane_num[i] == 0) + if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) { + switch (wiz->master_lane_num[i]) { + case LANE0: regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, WIZ_SERDES_TYPEC_LN10_SWAP, WIZ_SERDES_TYPEC_LN10_SWAP); + break; + case LANE2: + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN23_SWAP, + WIZ_SERDES_TYPEC_LN23_SWAP); + break; + default: + break; + } + } } } -- cgit v1.3.1 From 6ee2c8ad581b7fe14ba335b2412a28d1a77bb40e Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Mon, 13 Mar 2023 14:46:11 +0100 Subject: pci: apple: Initialize only enabled ports The Linux devicetrees for Apple silicon devices are after review feedback switching from deleting unused PCIe ports to disabling them. Link: https://lore.kernel.org/asahi/1ea2107a-bb86-8c22-0bbc-82c453ab08ce@linaro.org/ Signed-off-by: Janne Grunau Reviewed-by: Mark Kettenis --- drivers/pci/pcie_apple.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/pci/pcie_apple.c b/drivers/pci/pcie_apple.c index 9b08e1e5da8..b934fdbc35c 100644 --- a/drivers/pci/pcie_apple.c +++ b/drivers/pci/pcie_apple.c @@ -315,6 +315,8 @@ static int apple_pcie_probe(struct udevice *dev) for (of_port = ofnode_first_subnode(dev_ofnode(dev)); ofnode_valid(of_port); of_port = ofnode_next_subnode(of_port)) { + if (!ofnode_is_enabled(of_port)) + continue; ret = apple_pcie_setup_port(pcie, of_port); if (ret) { dev_err(pcie->dev, "Port %d setup fail: %d\n", i, ret); -- cgit v1.3.1