From 9f4f914d7f9e3188189bafd73d8cfa743de85fd2 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Wed, 7 Jun 2017 18:45:57 +0200 Subject: rockchip: pinctrl: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This change covers the pinctrl drivers for the Rockchip devices. Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass --- drivers/pinctrl/rockchip/pinctrl_rk3036.c | 3 +-- drivers/pinctrl/rockchip/pinctrl_rk3188.c | 3 +-- drivers/pinctrl/rockchip/pinctrl_rk3288.c | 3 +-- drivers/pinctrl/rockchip/pinctrl_rk3328.c | 3 +-- drivers/pinctrl/rockchip/pinctrl_rk3399.c | 3 +-- drivers/pinctrl/rockchip/pinctrl_rv1108.c | 3 +-- 6 files changed, 6 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c index 9215d6c96e2..94f6d7ad403 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c @@ -193,8 +193,7 @@ static int rk3036_pinctrl_get_periph_id(struct udevice *dev, u32 cell[3]; int ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); + ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); if (ret < 0) return -EINVAL; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3188.c b/drivers/pinctrl/rockchip/pinctrl_rk3188.c index 65c1f665ea9..692d8e298d0 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3188.c @@ -370,8 +370,7 @@ static int rk3188_pinctrl_get_periph_id(struct udevice *dev, u32 cell[3]; int ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); + ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); if (ret < 0) return -EINVAL; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c index cb13d30da8e..de5e8343e57 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c @@ -479,8 +479,7 @@ static int rk3288_pinctrl_get_periph_id(struct udevice *dev, u32 cell[3]; int ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); + ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); if (ret < 0) return -EINVAL; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c index d0ffeb1f044..efa5b3105ce 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c @@ -251,8 +251,7 @@ static int rk3328_pinctrl_get_periph_id(struct udevice *dev, u32 cell[3]; int ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); + ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); if (ret < 0) return -EINVAL; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index d93b90310b0..cab268c7d6c 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -350,8 +350,7 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev, u32 cell[3]; int ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); + ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); if (ret < 0) return -EINVAL; diff --git a/drivers/pinctrl/rockchip/pinctrl_rv1108.c b/drivers/pinctrl/rockchip/pinctrl_rv1108.c index bdf3910a885..cda94f49575 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl_rv1108.c @@ -108,8 +108,7 @@ static int rv1108_pinctrl_get_periph_id(struct udevice *dev, u32 cell[3]; int ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); + ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); if (ret < 0) return -EINVAL; -- cgit v1.3.1 From 6c65577ce6f3776638fd1d719bb5202acb2aa7ff Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Wed, 7 Jun 2017 18:45:58 +0200 Subject: rockchip: spi: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This change covers the rk_spi.c (SPI driver) used in Rockchip devices. Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass --- drivers/spi/rk_spi.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index a8f0eb0be6f..7921ea0d754 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -182,8 +182,6 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_spi_platdata *plat = dev_get_platdata(bus); struct rockchip_spi_priv *priv = dev_get_priv(bus); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(bus); int ret; plat->base = devfdt_get_addr(bus); @@ -195,12 +193,13 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) return ret; } - plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", - 50000000); - plat->deactivate_delay_us = fdtdec_get_int(blob, node, - "spi-deactivate-delay", 0); - plat->activate_delay_us = fdtdec_get_int(blob, node, - "spi-activate-delay", 0); + plat->frequency = + dev_read_u32_default(bus, "spi-max-frequency", 50000000); + plat->deactivate_delay_us = + dev_read_u32_default(bus, "spi-deactivate-delay", 0); + plat->activate_delay_us = + dev_read_u32_default(bus, "spi-activate-delay", 0); + debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", __func__, (uint)plat->base, plat->frequency, plat->deactivate_delay_us); -- cgit v1.3.1 From f2708c97c2ee213021a3d8ce484a6218ce4a5cf6 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Wed, 7 Jun 2017 18:45:59 +0200 Subject: rockchip: xhci: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This change covers the USB3 (xhci) driver for the Rockchip devices. Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass --- drivers/usb/host/xhci-rockchip.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c index c4ae55fc390..da21bc7ae84 100644 --- a/drivers/usb/host/xhci-rockchip.c +++ b/drivers/usb/host/xhci-rockchip.c @@ -86,18 +86,15 @@ static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, struct udevice *dev) { u32 reg; - const void *blob = gd->fdt_blob; u32 utmi_bits; /* Set dwc3 usb2 phy config */ reg = readl(&dwc3_reg->g_usb2phycfg[0]); - if (fdtdec_get_bool(blob, dev_of_offset(dev), - "snps,dis-enblslpm-quirk")) + if (dev_read_bool(dev, "snps,dis-enblslpm-quirk")) reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; - utmi_bits = fdtdec_get_int(blob, dev_of_offset(dev), - "snps,phyif-utmi-bits", -1); + utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1); if (utmi_bits == 16) { reg |= DWC3_GUSB2PHYCFG_PHYIF; reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; @@ -108,12 +105,10 @@ static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; } - if (fdtdec_get_bool(blob, dev_of_offset(dev), - "snps,dis-u2-freeclk-exists-quirk")) + if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk")) reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; - if (fdtdec_get_bool(blob, dev_of_offset(dev), - "snps,dis-u2-susphy-quirk")) + if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk")) reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; writel(reg, &dwc3_reg->g_usb2phycfg[0]); -- cgit v1.3.1 From fd1bf8df2507fb488febe4b5e4498adbef0fb43e Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Wed, 7 Jun 2017 18:46:00 +0200 Subject: rockchip: mmc: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the dw_mmc and sdhci wrapper drivers for Rockchip. Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass --- drivers/mmc/rockchip_dw_mmc.c | 18 +++++++----------- drivers/mmc/rockchip_sdhci.c | 3 +-- 2 files changed, 8 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 25a21e29d00..24754b7b120 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -59,32 +59,28 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) host->name = dev->name; host->ioaddr = (void *)devfdt_get_addr(dev); - host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "bus-width", 4); + host->buswidth = dev_read_u32_default(dev, "bus-width", 4); host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; host->priv = dev; /* use non-removeable as sdcard and emmc as judgement */ - if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "non-removable")) + if (dev_read_bool(dev, "non-removable")) host->dev_index = 0; else host->dev_index = 1; - priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "fifo-depth", 0); + priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); + if (priv->fifo_depth < 0) return -EINVAL; - priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), - "fifo-mode"); + priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); /* * 'clock-freq-min-max' is deprecated * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b) */ - if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), - "clock-freq-min-max", priv->minmax, 2)) { - int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "max-frequency", -EINVAL); + if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) { + int val = dev_read_u32_default(dev, "max-frequency", -EINVAL); if (val < 0) return val; diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 8985878d7e8..f31d329c81d 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -50,8 +50,7 @@ static int arasan_sdhci_probe(struct udevice *dev) max_frequency = dtplat->max_frequency; ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk); #else - max_frequency = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "max-frequency", 0); + max_frequency = dev_read_u32_default(dev, "max-frequency", 0); ret = clk_get_by_index(dev, 0, &clk); #endif if (!ret) { -- cgit v1.3.1 From 7ad326a905dac36939f9ea725835f809e1b7f432 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Wed, 7 Jun 2017 18:46:01 +0200 Subject: rockchip: net: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the Gigabit Ethernet MAC (i.e. common designware driver and rockchip-specific wrapper). Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass --- drivers/net/designware.c | 7 +++---- drivers/net/gmac_rockchip.c | 10 ++++------ 2 files changed, 7 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/net/designware.c b/drivers/net/designware.c index e8569e6fef5..521e4dde41f 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -760,15 +760,14 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev) pdata->max_speed = fdt32_to_cpu(*cell); #ifdef CONFIG_DM_GPIO - if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), - "snps,reset-active-low")) + if (dev_read_bool(dev, "snps,reset-active-low")) reset_flags |= GPIOD_ACTIVE_LOW; ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, &priv->reset_gpio, reset_flags); if (ret == 0) { - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), - "snps,reset-delays-us", dw_pdata->reset_delays, 3); + ret = dev_read_u32_array(dev, "snps,reset-delays-us", + dw_pdata->reset_delays, 3); } else if (ret == -ENOENT) { ret = 0; } diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 5e2ca763027..c9f9e839bad 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -43,18 +43,16 @@ struct rk_gmac_ops { static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); /* Check the new naming-style first... */ - pdata->tx_delay = fdtdec_get_int(blob, node, "tx_delay", -ENOENT); - pdata->rx_delay = fdtdec_get_int(blob, node, "rx_delay", -ENOENT); + pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); + pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); /* ... and fall back to the old naming style or default, if necessary */ if (pdata->tx_delay == -ENOENT) - pdata->tx_delay = fdtdec_get_int(blob, node, "tx-delay", 0x30); + pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); if (pdata->rx_delay == -ENOENT) - pdata->rx_delay = fdtdec_get_int(blob, node, "rx-delay", 0x10); + pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); return designware_eth_ofdata_to_platdata(dev); } -- cgit v1.3.1 From 3d40479f00c9406463b716d1874de0d2f4a31a02 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Wed, 7 Jun 2017 18:46:02 +0200 Subject: rockchip: ns16550: dm: convert fdt_get to dev_read With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This covers the serial driver (ns16550 and compatible) used for the Rockchip devices. Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass --- drivers/serial/ns16550.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 52c52c1ad14..e0e70244ce4 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -434,10 +434,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); #endif - plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "reg-offset", 0); - plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "reg-shift", 0); + plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); + plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); err = clk_get_by_index(dev, 0, &clk); if (!err) { @@ -450,9 +448,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) } if (!plat->clock) - plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "clock-frequency", - CONFIG_SYS_NS16550_CLK); + plat->clock = dev_read_u32_default(dev, "clock-frequency", + CONFIG_SYS_NS16550_CLK); if (!plat->clock) { debug("ns16550 clock not defined\n"); return -EINVAL; -- cgit v1.3.1 From 045029cbd16782031fceede2808b4905214f0921 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 23 Jun 2017 17:17:49 +0800 Subject: rockchip: rk322x: add clock driver Add clock driver init support for: - cpu, bus clock init; - emmc, sdmmc clock; - ddr clock; Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich Fixed format specified (%x -> %p) in clk_rk322x.c: Signed-off-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 215 ++++++++++++ drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rk322x.c | 413 ++++++++++++++++++++++++ 3 files changed, 629 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk322x.h create mode 100644 drivers/clk/rockchip/clk_rk322x.c (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h new file mode 100644 index 00000000000..2a2f804f675 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK322X_H +#define _ASM_ARCH_CRU_RK322X_H + +#include + +#define MHz 1000000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (594 * MHz) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk322x_clk_priv { + struct rk322x_cru *cru; + ulong rate; +}; + +struct rk322x_cru { + struct rk322x_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + } pll[4]; + unsigned int reserved0[4]; + unsigned int cru_mode_con; + unsigned int cru_clksel_con[35]; + unsigned int cru_clkgate_con[16]; + unsigned int cru_softrst_con[9]; + unsigned int cru_misc_con; + unsigned int reserved1[2]; + unsigned int cru_glb_cnt_th; + unsigned int reserved2[3]; + unsigned int cru_glb_rst_st; + unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1]; + unsigned int cru_sdmmc_con[2]; + unsigned int cru_sdio_con[2]; + unsigned int reserved4[2]; + unsigned int cru_emmc_con[2]; + unsigned int reserved5[4]; + unsigned int cru_glb_srst_fst_value; + unsigned int cru_glb_srst_snd_value; + unsigned int cru_pll_mask_con; +}; +check_member(rk322x_cru, cru_pll_mask_con, 0x01f8); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLLCON0*/ + PLL_BP_SHIFT = 15, + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLLCON1 */ + PLL_RST_SHIFT = 14, + PLL_PD_SHIFT = 13, + PLL_PD_MASK = 1 << PLL_PD_SHIFT, + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* CRU_MODE */ + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORM, + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORM, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORM, + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, + APLL_MODE_SLOW = 0, + APLL_MODE_NORM, + + /* CRU_CLK_SEL0_CON */ + BUS_ACLK_PLL_SEL_SHIFT = 13, + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, + BUS_ACLK_PLL_SEL_APLL = 0, + BUS_ACLK_PLL_SEL_GPLL, + BUS_ACLK_PLL_SEL_HDMIPLL, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, + CORE_CLK_PLL_SEL_SHIFT = 6, + CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL, + CORE_CLK_PLL_SEL_DPLL, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, + + /* CRU_CLK_SEL1_CON */ + BUS_PCLK_DIV_SHIFT = 12, + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 8, + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, + CORE_ACLK_DIV_SHIFT = 4, + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, + CORE_PERI_DIV_SHIFT = 0, + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, + + /* CRU_CLKSEL5_CON */ + GMAC_OUT_PLL_SHIFT = 15, + GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT, + GMAC_OUT_DIV_SHIFT = 8, + GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT, + MAC_PLL_SEL_SHIFT = 7, + MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, + RMII_EXTCLK_SLE_SHIFT = 5, + RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT, + RMII_EXTCLK_SEL_INT = 0, + RMII_EXTCLK_SEL_EXT, + CLK_MAC_DIV_SHIFT = 0, + CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT, + + /* CRU_CLKSEL10_CON */ + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT, + PERI_PLL_SEL_SHIFT = 10, + PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, + PERI_PLL_CPLL = 0, + PERI_PLL_GPLL, + PERI_PLL_HDMIPLL, + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + + /* CRU_CLKSEL11_CON */ + EMMC_PLL_SHIFT = 12, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, + EMMC_SEL_APLL = 0, + EMMC_SEL_DPLL, + EMMC_SEL_GPLL, + EMMC_SEL_24M, + SDIO_PLL_SHIFT = 10, + SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, + SDIO_SEL_APLL = 0, + SDIO_SEL_DPLL, + SDIO_SEL_GPLL, + SDIO_SEL_24M, + MMC0_PLL_SHIFT = 8, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, + MMC0_SEL_APLL = 0, + MMC0_SEL_DPLL, + MMC0_SEL_GPLL, + MMC0_SEL_24M, + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT, + + /* CRU_CLKSEL12_CON */ + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, + SDIO_DIV_SHIFT = 0, + SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT, + + /* CRU_CLKSEL26_CON */ + DDR_CLK_PLL_SEL_SHIFT = 8, + DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT, + DDR_CLK_SEL_DPLL = 0, + DDR_CLK_SEL_GPLL, + DDR_CLK_SEL_APLL, + DDR_DIV_SEL_SHIFT = 0, + DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT, + + /* CRU_CLKSEL27_CON */ + VOP_DCLK_DIV_SHIFT = 8, + VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT, + VOP_PLL_SEL_SHIFT = 1, + VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT, + + /* CRU_CLKSEL29_CON */ + GMAC_CLK_SRC_SHIFT = 12, + GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT, + + /* CRU_SOFTRST5_CON */ + DDRCTRL_PSRST_SHIFT = 11, + DDRCTRL_SRST_SHIFT = 10, + DDRPHY_PSRST_SHIFT = 9, + DDRPHY_SRST_SHIFT = 8, +}; +#endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index e404c0cdb90..c50aff2e93d 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o +obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c new file mode 100644 index 00000000000..fdeb816e231 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -0,0 +1,413 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + VCO_MAX_HZ = 3200U * 1000000, + VCO_MIN_HZ = 800 * 1000000, + OUTPUT_MAX_HZ = 3200U * 1000000, + OUTPUT_MIN_HZ = 24 * 1000000, +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ + .refdiv = _refdiv,\ + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ + _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \ + OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \ + #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)); + +/* use integer mode*/ +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); + +static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div) +{ + int pll_id = rk_pll_id(clk_id); + struct rk322x_pll *pll = &cru->pll[pll_id]; + + /* All PLLs have same VCO and output frequency range restrictions. */ + uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; + uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; + + debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", + pll, div->fbdiv, div->refdiv, div->postdiv1, + div->postdiv2, vco_hz, output_hz); + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); + + /* use integer mode */ + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + /* Power down */ + rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); + + rk_clrsetreg(&pll->con0, + PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, + (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, + (div->postdiv2 << PLL_POSTDIV2_SHIFT | + div->refdiv << PLL_REFDIV_SHIFT)); + + /* Power Up */ + rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); + + /* waiting for pll lock */ + while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) + udelay(1); + + return 0; +} + +static void rkclk_init(struct rk322x_cru *cru) +{ + u32 aclk_div; + u32 hclk_div; + u32 pclk_div; + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK | APLL_MODE_MASK, + GPLL_MODE_SLOW << GPLL_MODE_SHIFT | + APLL_MODE_SLOW << APLL_MODE_SHIFT); + + /* init pll */ + rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + + /* + * select apll as cpu/core clock pll source and + * set up dependent divisors for PERI and ACLK clocks. + * core hz : apll = 1:1 + */ + aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; + assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); + + pclk_div = APLL_HZ / CORE_PERI_HZ - 1; + assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, + CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | + 0 << CORE_DIV_CON_SHIFT); + + rk_clrsetreg(&cru->cru_clksel_con[1], + CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, + aclk_div << CORE_ACLK_DIV_SHIFT | + pclk_div << CORE_PERI_DIV_SHIFT); + + /* + * select apll as pd_bus bus clock source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; + assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); + + pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; + assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); + + hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; + assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); + + rk_clrsetreg(&cru->cru_clksel_con[0], + BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, + BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | + aclk_div << BUS_ACLK_DIV_SHIFT); + + rk_clrsetreg(&cru->cru_clksel_con[1], + BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, + pclk_div << BUS_PCLK_DIV_SHIFT | + hclk_div << BUS_HCLK_DIV_SHIFT); + + /* + * select gpll as pd_peri bus clock source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); + assert((1 << hclk_div) * PERI_HCLK_HZ == + PERI_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); + assert((1 << pclk_div) * PERI_PCLK_HZ == + PERI_ACLK_HZ && pclk_div < 0x8); + + rk_clrsetreg(&cru->cru_clksel_con[10], + PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | + PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, + PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | + pclk_div << PERI_PCLK_DIV_SHIFT | + hclk_div << PERI_HCLK_DIV_SHIFT | + aclk_div << PERI_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK | APLL_MODE_MASK, + GPLL_MODE_NORM << GPLL_MODE_SHIFT | + APLL_MODE_NORM << APLL_MODE_SHIFT); +} + +/* Get pll rate by id */ +static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru, + enum rk_clk_id clk_id) +{ + uint32_t refdiv, fbdiv, postdiv1, postdiv2; + uint32_t con; + int pll_id = rk_pll_id(clk_id); + struct rk322x_pll *pll = &cru->pll[pll_id]; + static u8 clk_shift[CLK_COUNT] = { + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, + GPLL_MODE_SHIFT, 0xff + }; + static u32 clk_mask[CLK_COUNT] = { + 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, + GPLL_MODE_MASK, 0xff + }; + uint shift; + uint mask; + + con = readl(&cru->cru_mode_con); + shift = clk_shift[clk_id]; + mask = clk_mask[clk_id]; + + switch ((con & mask) >> shift) { + case GPLL_MODE_SLOW: + return OSC_HZ; + case GPLL_MODE_NORM: + + /* normal mode */ + con = readl(&pll->con0); + postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; + fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; + con = readl(&pll->con1); + postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; + refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; + return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; + default: + return 32768; + } +} + +static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate, + int periph) +{ + uint src_rate; + uint div, mux; + u32 con; + + switch (periph) { + case HCLK_EMMC: + case SCLK_EMMC: + con = readl(&cru->cru_clksel_con[11]); + mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; + con = readl(&cru->cru_clksel_con[12]); + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; + break; + case HCLK_SDMMC: + case SCLK_SDMMC: + con = readl(&cru->cru_clksel_con[11]); + mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; + div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; + break; + default: + return -EINVAL; + } + + src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; + return DIV_TO_RATE(src_rate, div); +} + +static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, + int periph, uint freq) +{ + int src_clk_div; + int mux; + + debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); + + /* mmc clock auto divide 2 in internal */ + src_clk_div = (clk_general_rate / 2 + freq - 1) / freq; + + if (src_clk_div > 0x7f) { + src_clk_div = (OSC_HZ / 2 + freq - 1) / freq; + mux = EMMC_SEL_24M; + } else { + mux = EMMC_SEL_GPLL; + } + + switch (periph) { + case HCLK_EMMC: + case SCLK_EMMC: + rk_clrsetreg(&cru->cru_clksel_con[11], + EMMC_PLL_MASK, + mux << EMMC_PLL_SHIFT); + rk_clrsetreg(&cru->cru_clksel_con[12], + EMMC_DIV_MASK, + (src_clk_div - 1) << EMMC_DIV_SHIFT); + break; + case HCLK_SDMMC: + case SCLK_SDMMC: + rk_clrsetreg(&cru->cru_clksel_con[11], + MMC0_PLL_MASK | MMC0_DIV_MASK, + mux << MMC0_PLL_SHIFT | + (src_clk_div - 1) << MMC0_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_mmc_get_clk(cru, clk_general_rate, periph); +} + +static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate) +{ + struct pll_div dpll_cfg; + + /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ + switch (set_rate) { + case 400*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; + break; + case 600*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; + break; + case 800*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; + break; + } + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, + DPLL_MODE_SLOW << DPLL_MODE_SHIFT); + rkclk_set_pll(cru, CLK_DDR, &dpll_cfg); + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, + DPLL_MODE_NORM << DPLL_MODE_SHIFT); + + return set_rate; +} +static ulong rk322x_clk_get_rate(struct clk *clk) +{ + struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate, gclk_rate; + + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); + switch (clk->id) { + case 0 ... 63: + rate = rkclk_pll_get_rate(priv->cru, clk->id); + break; + case HCLK_EMMC: + case SCLK_EMMC: + case HCLK_SDMMC: + case SCLK_SDMMC: + rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate, gclk_rate; + + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); + switch (clk->id) { + case HCLK_EMMC: + case SCLK_EMMC: + case HCLK_SDMMC: + case SCLK_SDMMC: + new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, + clk->id, rate); + break; + case CLK_DDR: + new_rate = rk322x_ddr_set_clk(priv->cru, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static struct clk_ops rk322x_clk_ops = { + .get_rate = rk322x_clk_get_rate, + .set_rate = rk322x_clk_set_rate, +}; + +static int rk322x_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct rk322x_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev); + + return 0; +} + +static int rk322x_clk_probe(struct udevice *dev) +{ + struct rk322x_clk_priv *priv = dev_get_priv(dev); + + rkclk_init(priv->cru); + + return 0; +} + +static int rk322x_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev); + if (ret) + debug("Warning: No RK3036 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rk322x_clk_ids[] = { + { .compatible = "rockchip,rk3228-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk322x_cru) = { + .name = "clk_rk322x", + .id = UCLASS_CLK, + .of_match = rk322x_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk322x_clk_priv), + .ofdata_to_platdata = rk322x_clk_ofdata_to_platdata, + .ops = &rk322x_clk_ops, + .bind = rk322x_clk_bind, + .probe = rk322x_clk_probe, +}; -- cgit v1.3.1 From 5cc9d31a79fecfaacfdbc9c566b6df35765100f8 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 23 Jun 2017 17:17:50 +0800 Subject: rockchip: rk322x: add pinctrl driver Add init pinctrl driver support for: - i2c; - spi; - uart; - pwm; - emmc/sdmmc; Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 519 ++++++++++++++++++++++++ drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk322x.c | 294 ++++++++++++++ 4 files changed, 824 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk322x.h create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk322x.c (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h new file mode 100644 index 00000000000..26071c8ec8a --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h @@ -0,0 +1,519 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RK322X_H +#define _ASM_ARCH_GRF_RK322X_H + +#include + +struct rk322x_grf { + unsigned int gpio0a_iomux; + unsigned int gpio0b_iomux; + unsigned int gpio0c_iomux; + unsigned int gpio0d_iomux; + + unsigned int gpio1a_iomux; + unsigned int gpio1b_iomux; + unsigned int gpio1c_iomux; + unsigned int gpio1d_iomux; + + unsigned int gpio2a_iomux; + unsigned int gpio2b_iomux; + unsigned int gpio2c_iomux; + unsigned int gpio2d_iomux; + + unsigned int gpio3a_iomux; + unsigned int gpio3b_iomux; + unsigned int gpio3c_iomux; + unsigned int gpio3d_iomux; + + unsigned int reserved1[4]; + unsigned int con_iomux; + unsigned int reserved2[(0x100 - 0x50) / 4 - 1]; + unsigned int gpio0_p[4]; + unsigned int gpio1_p[4]; + unsigned int gpio2_p[4]; + unsigned int gpio3_p[4]; + unsigned int reserved3[(0x200 - 0x13c) / 4 - 1]; + unsigned int gpio0_e[4]; + unsigned int gpio1_e[4]; + unsigned int gpio2_e[4]; + unsigned int gpio3_e[4]; + unsigned int reserved4[(0x400 - 0x23c) / 4 - 1]; + unsigned int soc_con[7]; + unsigned int reserved5[(0x480 - 0x418) / 4 - 1]; + unsigned int soc_status[3]; + unsigned int chip_id; + unsigned int reserved6[(0x500 - 0x48c) / 4 - 1]; + unsigned int cpu_con[4]; + unsigned int reserved7[4]; + unsigned int cpu_status[2]; + unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1]; + unsigned int os_reg[8]; + unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1]; + unsigned int ddrc_stat; +}; +check_member(rk322x_grf, ddrc_stat, 0x604); + +struct rk322x_sgrf { + unsigned int soc_con[11]; + unsigned int busdmac_con[4]; +}; + +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A7_SHIFT = 14, + GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, + GPIO0A7_GPIO = 0, + GPIO0A7_I2C3_SDA, + GPIO0A7_HDMI_DDCSDA, + + GPIO0A6_SHIFT = 12, + GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, + GPIO0A6_GPIO = 0, + GPIO0A6_I2C3_SCL, + GPIO0A6_HDMI_DDCSCL, + + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, + GPIO0A3_GPIO = 0, + GPIO0A3_I2C1_SDA, + GPIO0A3_SDIO_CMD, + + GPIO0A2_SHIFT = 4, + GPIO0A2_MASK = 3 << GPIO0A2_SHIFT, + GPIO0A2_GPIO = 0, + GPIO0A2_I2C1_SCL, + + GPIO0A1_SHIFT = 2, + GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, + GPIO0A1_GPIO = 0, + GPIO0A1_I2C0_SDA, + + GPIO0A0_SHIFT = 0, + GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, + GPIO0A0_GPIO = 0, + GPIO0A0_I2C0_SCL, +}; + +/* GRF_GPIO0B_IOMUX */ +enum { + GPIO0B7_SHIFT = 14, + GPIO0B7_MASK = 3 << GPIO0B7_SHIFT, + GPIO0B7_GPIO = 0, + GPIO0B7_HDMI_HDP, + + GPIO0B6_SHIFT = 12, + GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, + GPIO0B6_GPIO = 0, + GPIO0B6_I2S_SDI, + GPIO0B6_SPI_CSN0, + + GPIO0B5_SHIFT = 10, + GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, + GPIO0B5_GPIO = 0, + GPIO0B5_I2S_SDO, + GPIO0B5_SPI_RXD, + + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, + GPIO0B3_GPIO = 0, + GPIO0B3_I2S1_LRCKRX, + GPIO0B3_SPI_TXD, + + GPIO0B1_SHIFT = 2, + GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, + GPIO0B1_GPIO = 0, + GPIO0B1_I2S_SCLK, + GPIO0B1_SPI_CLK, + + GPIO0B0_SHIFT = 0, + GPIO0B0_MASK = 3, + GPIO0B0_GPIO = 0, + GPIO0B0_I2S_MCLK, +}; + +/* GRF_GPIO0C_IOMUX */ +enum { + GPIO0C4_SHIFT = 8, + GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, + GPIO0C4_GPIO = 0, + GPIO0C4_HDMI_CECSDA, + + GPIO0C1_SHIFT = 2, + GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, + GPIO0C1_GPIO = 0, + GPIO0C1_UART0_RSTN, + GPIO0C1_CLK_OUT1, +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D6_SHIFT = 12, + GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, + GPIO0D6_GPIO = 0, + GPIO0D6_SDIO_PWREN, + GPIO0D6_PWM11, + + + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, + GPIO0D4_GPIO = 0, + GPIO0D4_PWM2, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, + GPIO0D3_GPIO = 0, + GPIO0D3_PWM1, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, + GPIO0D2_GPIO = 0, + GPIO0D2_PWM0, +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A7_SHIFT = 14, + GPIO1A7_MASK = 1, + GPIO1A7_GPIO = 0, + GPIO1A7_SDMMC_WRPRT, +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, + GPIO1B7_GPIO = 0, + GPIO1B7_SDMMC_CMD, + + GPIO1B6_SHIFT = 12, + GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, + GPIO1B6_GPIO = 0, + GPIO1B6_SDMMC_PWREN, + + GPIO1B4_SHIFT = 8, + GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, + GPIO1B4_GPIO = 0, + GPIO1B4_SPI_CSN1, + GPIO1B4_PWM12, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, + GPIO1B3_GPIO = 0, + GPIO1B3_UART1_RSTN, + GPIO1B3_PWM13, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_UART1_SIN, + GPIO1B2_UART21_SIN, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_UART1_SOUT, + GPIO1B1_UART21_SOUT, +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C7_SHIFT = 14, + GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, + GPIO1C7_GPIO = 0, + GPIO1C7_NAND_CS3, + GPIO1C7_EMMC_RSTNOUT, + + GPIO1C6_SHIFT = 12, + GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, + GPIO1C6_GPIO = 0, + GPIO1C6_NAND_CS2, + GPIO1C6_EMMC_CMD, + + + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, + GPIO1C5_GPIO = 0, + GPIO1C5_SDMMC_D3, + GPIO1C5_JTAG_TMS, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, + GPIO1C4_GPIO = 0, + GPIO1C4_SDMMC_D2, + GPIO1C4_JTAG_TCK, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_SDMMC_D1, + GPIO1C3_UART2_SIN, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , + GPIO1C2_GPIO = 0, + GPIO1C2_SDMMC_D0, + GPIO1C2_UART2_SOUT, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, + GPIO1C1_GPIO = 0, + GPIO1C1_SDMMC_DETN, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 3 << GPIO1C0_SHIFT, + GPIO1C0_GPIO = 0, + GPIO1C0_SDMMC_CLKOUT, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, + GPIO1D7_GPIO = 0, + GPIO1D7_NAND_D7, + GPIO1D7_EMMC_D7, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, + GPIO1D6_GPIO = 0, + GPIO1D6_NAND_D6, + GPIO1D6_EMMC_D6, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, + GPIO1D5_GPIO = 0, + GPIO1D5_NAND_D5, + GPIO1D5_EMMC_D5, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, + GPIO1D4_GPIO = 0, + GPIO1D4_NAND_D4, + GPIO1D4_EMMC_D4, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, + GPIO1D3_GPIO = 0, + GPIO1D3_NAND_D3, + GPIO1D3_EMMC_D3, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, + GPIO1D2_GPIO = 0, + GPIO1D2_NAND_D2, + GPIO1D2_EMMC_D2, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, + GPIO1D1_GPIO = 0, + GPIO1D1_NAND_D1, + GPIO1D1_EMMC_D1, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, + GPIO1D0_GPIO = 0, + GPIO1D0_NAND_D0, + GPIO1D0_EMMC_D0, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_NAND_DQS, + GPIO2A7_EMMC_CLKOUT, + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, + GPIO2A5_GPIO = 0, + GPIO2A5_NAND_WP, + GPIO2A5_EMMC_PWREN, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_NAND_RDY, + GPIO2A4_EMMC_CMD, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_NAND_RDN, + GPIO2A4_SPI1_CSN1, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_NAND_WRN, + GPIO2A4_SPI1_CSN0, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_NAND_CLE, + GPIO2A1_SPI1_TXD, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_NAND_ALE, + GPIO2A0_SPI1_RXD, +}; + +/* GRF_GPIO2B_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, + GPIO2B7_GPIO = 0, + GPIO2B7_GMAC_RXER, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, + GPIO2B6_GPIO = 0, + GPIO2B6_GMAC_CLK, + GPIO2B6_MAC_LINK, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, + GPIO2B5_GPIO = 0, + GPIO2B5_GMAC_TXEN, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, + GPIO2B4_GPIO = 0, + GPIO2B4_GMAC_MDIO, + + GPIO2B3_SHIFT = 6, + GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, + GPIO2B3_GPIO = 0, + GPIO2B3_GMAC_RXCLK, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, + GPIO2B2_GPIO = 0, + GPIO2B2_GMAC_CRS, + + GPIO2B1_SHIFT = 2, + GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, + GPIO2B1_GPIO = 0, + GPIO2B1_GMAC_TXCLK, + + + GPIO2B0_SHIFT = 0, + GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, + GPIO2B0_GPIO = 0, + GPIO2B0_GMAC_RXDV, + GPIO2B0_MAC_SPEED_IOUT, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C7_SHIFT = 14, + GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, + GPIO2C7_GPIO = 0, + GPIO2C7_GMAC_TXD3, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 3 << GPIO2C6_SHIFT, + GPIO2C6_GPIO = 0, + GPIO2C6_GMAC_TXD2, + + GPIO2C5_SHIFT = 10, + GPIO2C5_MASK = 3 << GPIO2C5_SHIFT, + GPIO2C5_GPIO = 0, + GPIO2C5_I2C2_SCL, + GPIO2C5_GMAC_RXD2, + + GPIO2C4_SHIFT = 8, + GPIO2C4_MASK = 3 << GPIO2C4_SHIFT, + GPIO2C4_GPIO = 0, + GPIO2C4_I2C2_SDA, + GPIO2C4_GMAC_RXD3, + + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, + GPIO2C3_GPIO = 0, + GPIO2C3_GMAC_TXD0, + + GPIO2C2_SHIFT = 4, + GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, + GPIO2C2_GPIO = 0, + GPIO2C2_GMAC_TXD1, + + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, + GPIO2C1_GPIO = 0, + GPIO2C1_GMAC_RXD0, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, + GPIO2C0_GPIO = 0, + GPIO2C0_GMAC_RXD1, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_GMAC_MDC, + + GPIO2D0_SHIFT = 0, + GPIO2D0_MASK = 3, + GPIO2D0_GPIO = 0, + GPIO2D0_GMAC_COL, +}; + +/* GRF_GPIO3C_IOMUX */ +enum { + GPIO3C6_SHIFT = 12, + GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, + GPIO3C6_GPIO = 0, + GPIO3C6_DRV_VBUS1, + + GPIO3C5_SHIFT = 10, + GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, + GPIO3C5_GPIO = 0, + GPIO3C5_PWM10, + + GPIO3C1_SHIFT = 2, + GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, + GPIO3C1_GPIO = 0, + GPIO3C1_DRV_VBUS, +}; + +/* GRF_GPIO3D_IOMUX */ +enum { + GPIO3D2_SHIFT = 4, + GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, + GPIO3D2_GPIO = 0, + GPIO3D2_PWM3, +}; + +/* GRF_CON_IOMUX */ +enum { + CON_IOMUX_GMAC_SHIFT = 15, + CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT, + CON_IOMUX_UART1SEL_SHIFT = 11, + CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT, + CON_IOMUX_UART2SEL_SHIFT = 8, + CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, + CON_IOMUX_UART2SEL_2 = 0, + CON_IOMUX_UART2SEL_21, + CON_IOMUX_EMMCSEL_SHIFT = 7, + CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT, + CON_IOMUX_PWM3SEL_SHIFT = 3, + CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT, + CON_IOMUX_PWM2SEL_SHIFT = 2, + CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT, + CON_IOMUX_PWM1SEL_SHIFT = 1, + CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT, + CON_IOMUX_PWM0SEL_SHIFT = 0, + CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT, +}; +#endif diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f948783170f..4ab0b3a5eba 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -178,6 +178,16 @@ config PINCTRL_ROCKCHIP_RK3188 the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_ROCKCHIP_RK322X + bool "Rockchip rk322x pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk322x SoCs. + + The driver is controlled by a device tree node which contains both + the GPIO definitions and pin control functions for each available + multiplex function. + config PINCTRL_ROCKCHIP_RK3288 bool "Rockchip rk3288 pin control driver" depends on DM diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index a1c655d537d..5251771a106 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o +obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3328) += pinctrl_rk3328.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3368) += pinctrl_rk3368.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c new file mode 100644 index 00000000000..7aaf4b5801a --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c @@ -0,0 +1,294 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct rk322x_pinctrl_priv { + struct rk322x_grf *grf; +}; + +static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id) +{ + u32 mux_con = readl(&grf->con_iomux); + + switch (pwm_id) { + case PERIPH_ID_PWM0: + if (mux_con & CON_IOMUX_PWM0SEL_MASK) + rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK, + GPIO3C5_PWM10 << GPIO3C5_SHIFT); + else + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK, + GPIO0D2_PWM0 << GPIO0D2_SHIFT); + break; + case PERIPH_ID_PWM1: + if (mux_con & CON_IOMUX_PWM1SEL_MASK) + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK, + GPIO0D6_PWM11 << GPIO0D6_SHIFT); + else + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK, + GPIO0D3_PWM1 << GPIO0D3_SHIFT); + break; + case PERIPH_ID_PWM2: + if (mux_con & CON_IOMUX_PWM2SEL_MASK) + rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK, + GPIO1B4_PWM12 << GPIO1B4_SHIFT); + else + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK, + GPIO0D4_PWM2 << GPIO0D4_SHIFT); + break; + case PERIPH_ID_PWM3: + if (mux_con & CON_IOMUX_PWM3SEL_MASK) + rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK, + GPIO1B3_PWM13 << GPIO1B3_SHIFT); + else + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK, + GPIO3D2_PWM3 << GPIO3D2_SHIFT); + break; + default: + debug("pwm id = %d iomux error!\n", pwm_id); + break; + } +} + +static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A1_MASK | GPIO0A0_MASK, + GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT | + GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT); + + break; + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A3_MASK | GPIO0A2_MASK, + GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT | + GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT); + break; + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C5_MASK | GPIO2C4_MASK, + GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT | + GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT); + break; + case PERIPH_ID_I2C3: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A7_MASK | GPIO0A6_MASK, + GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT | + GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT); + + break; + } +} + +static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs) +{ + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK, + GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK, + GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT); + break; + } + rk_clrsetreg(&grf->gpio0b_iomux, + GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK, + GPIO0B5_SPI_RXD << GPIO0B5_SHIFT | + GPIO0B3_SPI_TXD << GPIO0B3_SHIFT | + GPIO0B1_SPI_CLK << GPIO0B1_SHIFT); +} + +static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id) +{ + u32 mux_con = readl(&grf->con_iomux); + + switch (uart_id) { + case PERIPH_ID_UART1: + if (!(mux_con & CON_IOMUX_UART1SEL_MASK)) + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B2_MASK, + GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT | + GPIO1B2_UART1_SIN << GPIO1B2_SHIFT); + break; + case PERIPH_ID_UART2: + if (mux_con & CON_IOMUX_UART2SEL_MASK) + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B2_MASK, + GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT | + GPIO1B2_UART21_SIN << GPIO1B2_SHIFT); + else + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C3_MASK | GPIO1C2_MASK, + GPIO1C3_UART2_SIN << GPIO1C3_SHIFT | + GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT); + break; + } +} + +static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&grf->gpio1d_iomux, 0xffff, + GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT | + GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT | + GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT | + GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT | + GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT | + GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT | + GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT | + GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A5_MASK | GPIO2A7_MASK, + GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT | + GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT); + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C6_MASK | GPIO1C7_MASK, + GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT | + GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B6_MASK | GPIO1B7_MASK, + GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT | + GPIO1B7_SDMMC_CMD << GPIO1B6_SHIFT); + rk_clrsetreg(&grf->gpio1c_iomux, 0xfff, + GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT | + GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT | + GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT | + GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT | + GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT | + GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT); + break; + } +} + +static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk322x_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + pinctrl_rk322x_pwm_config(priv->grf, func); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + pinctrl_rk322x_i2c_config(priv->grf, func); + break; + case PERIPH_ID_SPI0: + pinctrl_rk322x_spi_config(priv->grf, flags); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + pinctrl_rk322x_uart_config(priv->grf, func); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + pinctrl_rk322x_sdmmc_config(priv->grf, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk322x_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 12: + return PERIPH_ID_SDCARD; + case 14: + return PERIPH_ID_EMMC; + case 36: + return PERIPH_ID_I2C0; + case 37: + return PERIPH_ID_I2C1; + case 38: + return PERIPH_ID_I2C2; + case 49: + return PERIPH_ID_SPI0; + case 50: + return PERIPH_ID_PWM0; + case 55: + return PERIPH_ID_UART0; + case 56: + return PERIPH_ID_UART1; + case 57: + return PERIPH_ID_UART2; + } + return -ENOENT; +} + +static int rk322x_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk322x_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + return rk322x_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops rk322x_pinctrl_ops = { + .set_state_simple = rk322x_pinctrl_set_state_simple, + .request = rk322x_pinctrl_request, + .get_periph_id = rk322x_pinctrl_get_periph_id, +}; + +static int rk322x_pinctrl_probe(struct udevice *dev) +{ + struct rk322x_pinctrl_priv *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + debug("%s: grf=%p\n", __func__, priv->grf); + return 0; +} + +static const struct udevice_id rk322x_pinctrl_ids[] = { + { .compatible = "rockchip,rk322x-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk322x) = { + .name = "pinctrl_rk322x", + .id = UCLASS_PINCTRL, + .of_match = rk322x_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv), + .ops = &rk322x_pinctrl_ops, + .bind = dm_scan_fdt_dev, + .probe = rk322x_pinctrl_probe, +}; -- cgit v1.3.1 From a21e132894f6a9acb73ed5e698144ba77a61f1a8 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 23 Jun 2017 17:17:53 +0800 Subject: rockchip: rk322x: add sysreset driver Rockchip rk322x sysreset is much like rk3036 and other Rockchip SoCs, only difference is that the target register address is different. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich --- drivers/sysreset/sysreset_rk322x.c | 45 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 drivers/sysreset/sysreset_rk322x.c (limited to 'drivers') diff --git a/drivers/sysreset/sysreset_rk322x.c b/drivers/sysreset/sysreset_rk322x.c new file mode 100644 index 00000000000..5fce79b685f --- /dev/null +++ b/drivers/sysreset/sysreset_rk322x.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rk322x_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case SYSRESET_WARM: + writel(0xeca8, &cru->cru_glb_srst_snd_value); + break; + case SYSRESET_COLD: + writel(0xfdb9, &cru->cru_glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rk322x_sysreset = { + .request = rk322x_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rk322x) = { + .name = "rk322x_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk322x_sysreset, +}; -- cgit v1.3.1 From 8093529809650621ba74ebfc9e317d7ba87489b6 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 14 Jun 2017 16:31:46 +0800 Subject: rockchip: dwmmc: use max-frequency when OF_PLATDATA enabled Since the 'clock-freq-min-max' is deprecated, we use max-frequency for all rockchip SoC dwmmc controller. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Reviewed-by: Philipp Tomsich --- drivers/mmc/rockchip_dw_mmc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 24754b7b120..d5b05b0b583 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -115,7 +115,8 @@ static int rockchip_dwmmc_probe(struct udevice *dev) host->dev_index = 0; priv->fifo_depth = dtplat->fifo_depth; priv->fifo_mode = 0; - memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax)); + priv->minmax[0] = 400000; /* 400 kHz */ + priv->minmax[1] = dtplat->max_frequency; ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); if (ret < 0) -- cgit v1.3.1 From 419b08012a09f2656c44c81d976ffa41926f5e6b Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 14 Jun 2017 16:31:49 +0800 Subject: Revert "mmc: dw_mmc: rockchip: select proper card clock" The origin patch get rockchip dwmmc by name 'ciu', which lead to the SPL not able to remove 'clock-names' node in dts. I'm not saying this is not correct, but I would prefer to handle this in dts or clock driver to save memory for SPL. For example the rk3288 SPL size has out of memory if not enable BACK_TO_BROM option, there are many other SoCs has less internal memory than rk3288. This reverts commit 480a9b834c661fc88217f50bdf780192c3018d66. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Reviewed-by: Philipp Tomsich --- drivers/mmc/rockchip_dw_mmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index d5b05b0b583..e7fcf89f734 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -44,7 +44,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) ret = clk_set_rate(&priv->clk, freq); if (ret < 0) { - printf("%s: err=%d\n", __func__, ret); + debug("%s: err=%d\n", __func__, ret); return ret; } @@ -122,7 +122,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev) if (ret < 0) return ret; #else - ret = clk_get_by_name(dev, "ciu", &priv->clk); + ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) return ret; #endif -- cgit v1.3.1 From 0c9eceb7af8961e945feaaa12c193f29ae65de3f Mon Sep 17 00:00:00 2001 From: "eric.gao@rock-chips.com" Date: Wed, 21 Jun 2017 11:12:50 +0800 Subject: rockchip: video: mipi: Modify variable type for arm32 compatibility Some address relevant varibable is defined originally as u64. To compatible with arm32, this patch change them to uintptr_t type. Signed-off-by: Eric Gao Reviewed-by: Simon Glass --- drivers/video/rockchip/rk_mipi.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index ad003970d68..1ccd24700bd 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR; * @txesc_clk: clock for tx esc mode */ struct rk_mipi_priv { - void __iomem *regs; + uintptr_t regs; struct rk3399_grf_regs *grf; struct udevice *panel; struct mipi_dsi *dsi; @@ -76,13 +76,13 @@ static int rk_mipi_read_timing(struct udevice *dev, * use define in rk_mipi.h directly for this parameter * @val: value that will be write to specified bits of register */ -static void rk_mipi_dsi_write(u32 regs, u32 reg, u32 val) +static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val) { u32 dat; u32 mask; u32 offset = (reg >> OFFSET_SHIFT) & 0xff; u32 bits = (reg >> BITS_SHIFT) & 0xff; - u64 addr = (reg >> ADDR_SHIFT) + regs; + uintptr_t addr = (reg >> ADDR_SHIFT) + regs; /* Mask for specifiled bits,the corresponding bits will be clear */ mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits))); @@ -108,7 +108,7 @@ static int rk_mipi_dsi_enable(struct udevice *dev, int node, timing_node; int val; struct rk_mipi_priv *priv = dev_get_priv(dev); - u64 regs = (u64)priv->regs; + uintptr_t regs = priv->regs; struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); u32 txbyte_clk = priv->txbyte_clk; u32 txesc_clk = priv->txesc_clk; @@ -224,7 +224,7 @@ static int rk_mipi_dsi_enable(struct udevice *dev, } /* rk mipi dphy write function. It is used to write test data to dphy */ -static void rk_mipi_phy_write(u32 regs, unsigned char test_code, +static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code, unsigned char *test_data, unsigned char size) { int i = 0; @@ -253,7 +253,7 @@ static int rk_mipi_phy_enable(struct udevice *dev) { int i; struct rk_mipi_priv *priv = dev_get_priv(dev); - u64 regs = (u64)priv->regs; + uintptr_t regs = priv->regs; u64 fbdiv; u64 prediv = 1; u32 max_fbdiv = 512; @@ -441,7 +441,7 @@ static int rk_mipi_ofdata_to_platdata(struct udevice *dev) __func__, (u64)priv->grf); return -ENXIO; } - priv->regs = (void *)devfdt_get_addr(dev); + priv->regs = devfdt_get_addr(dev); if (priv->regs <= 0) { debug("%s: Get MIPI dsi address failed (ret=%llu)\n", __func__, (u64)priv->regs); -- cgit v1.3.1 From 0c6d52bc4b78364500f817386af0b4eadc085fe6 Mon Sep 17 00:00:00 2001 From: "eric.gao@rock-chips.com" Date: Wed, 21 Jun 2017 11:15:57 +0800 Subject: rockchip: video: mipi: Modify format type for debug message Modify format type for debug message. Signed-off-by: Eric Gao --- drivers/video/rockchip/rk_mipi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index 1ccd24700bd..1199a30c1a5 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -437,14 +437,14 @@ static int rk_mipi_ofdata_to_platdata(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (priv->grf <= 0) { - debug("%s: Get syscon grf failed (ret=%llu)\n", - __func__, (u64)priv->grf); + debug("%s: Get syscon grf failed (ret=%p)\n", + __func__, priv->grf); return -ENXIO; } priv->regs = devfdt_get_addr(dev); if (priv->regs <= 0) { - debug("%s: Get MIPI dsi address failed (ret=%llu)\n", __func__, - (u64)priv->regs); + debug("%s: Get MIPI dsi address failed (ret=%lu)\n", __func__, + priv->regs); return -ENXIO; } -- cgit v1.3.1 From e85f00abdaf3d83dde6b4e62f65ff26ea6b1fd92 Mon Sep 17 00:00:00 2001 From: Meng Dongyang Date: Wed, 28 Jun 2017 19:22:39 +0800 Subject: usb: Kconfig: config USB_XHCI_ROCKCHIP depends on DM_REGULATOR and DM_USB The xhci-rockchip driver depends on DM_REGULATOR and DM_USB. So add dependent features for xhci-rockchip driver in Kconfig. Signed-off-by: Meng Dongyang Reviewed-by: Philipp Tomsich Acked-by: Philipp Tomsich --- drivers/usb/host/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index b824eec41d9..5e07a10e752 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -34,6 +34,8 @@ config USB_XHCI_MVEBU config USB_XHCI_ROCKCHIP bool "Support for Rockchip on-chip xHCI USB controller" depends on ARCH_ROCKCHIP + depends on DM_REGULATOR + depends on DM_USB default y help Enables support for the on-chip xHCI controller on Rockchip SoCs. -- cgit v1.3.1 From 26a8b80fac1736d50280c262078381b5eebc1216 Mon Sep 17 00:00:00 2001 From: Meng Dongyang Date: Wed, 28 Jun 2017 19:22:40 +0800 Subject: usb: host: xhci-rockchip: use fixed regulator to control vbus Use fixed regulator to control the voltage of vbus. Enable vbus supply when usb start and disable vbus supply when usb stop. Signed-off-by: Meng Dongyang Reviewed-by: Philipp Tomsich Acked-by: Philipp Tomsich --- drivers/usb/host/xhci-rockchip.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c index da21bc7ae84..ec55f4e59f7 100644 --- a/drivers/usb/host/xhci-rockchip.c +++ b/drivers/usb/host/xhci-rockchip.c @@ -48,7 +48,7 @@ static int xhci_usb_ofdata_to_platdata(struct udevice *dev) */ plat->hcd_base = devfdt_get_addr(dev); if (plat->hcd_base == FDT_ADDR_T_NONE) { - debug("Can't get the XHCI register base address\n"); + error("Can't get the XHCI register base address\n"); return -ENXIO; } @@ -62,17 +62,15 @@ static int xhci_usb_ofdata_to_platdata(struct udevice *dev) } if (plat->phy_base == FDT_ADDR_T_NONE) { - debug("Can't get the usbphy register address\n"); + error("Can't get the usbphy register address\n"); return -ENXIO; } -#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) /* Vbus regulator */ ret = device_get_supply_regulator(dev, "vbus-supply", &plat->vbus_supply); if (ret) - debug("Can't get vbus supply\n"); -#endif + debug("Can't get VBus regulator!\n"); return 0; } @@ -121,7 +119,7 @@ static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci, ret = dwc3_core_init(rkxhci->dwc3_reg); if (ret) { - debug("failed to initialize core\n"); + error("failed to initialize core\n"); return ret; } @@ -150,15 +148,17 @@ static int xhci_usb_probe(struct udevice *dev) hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd + HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); -#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) - ret = regulator_set_enable(plat->vbus_supply, true); - if (ret) - debug("XHCI: Failed to enable vbus supply\n"); -#endif + if (plat->vbus_supply) { + ret = regulator_set_enable(plat->vbus_supply, true); + if (ret) { + error("XHCI: failed to set VBus supply\n"); + return ret; + } + } ret = rockchip_xhci_core_init(ctx, dev); if (ret) { - debug("XHCI: failed to initialize controller\n"); + error("XHCI: failed to initialize controller\n"); return ret; } @@ -178,13 +178,13 @@ static int xhci_usb_remove(struct udevice *dev) if (ret) return ret; -#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) - ret = regulator_set_enable(plat->vbus_supply, false); - if (ret) - debug("XHCI: Failed to disable vbus supply\n"); -#endif + if (plat->vbus_supply) { + ret = regulator_set_enable(plat->vbus_supply, false); + if (ret) + error("XHCI: failed to set VBus supply\n"); + } - return 0; + return ret; } static const struct udevice_id xhci_usb_ids[] = { -- cgit v1.3.1 From 4ac72f5c5b751ad27515655bfd5aebc2231eadf9 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Mon, 3 Jul 2017 18:30:06 +0200 Subject: usb: Kconfig: migrate USB_DWC2 to Kconfig This change migrates the USB_DWC2 configuration item to Kconfig and runs moveconfig to adjust header files and defconfig. Signed-off-by: Meng Dongyang Split off into a separate patch: Ran moveconfig to migrate other boards: Signed-off-by: Philipp Tomsich --- configs/fennec-rk3288_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + configs/hikey_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 + configs/miqi-rk3288_defconfig | 1 + configs/popmetal-rk3288_defconfig | 1 + configs/rpi_2_defconfig | 1 + configs/rpi_3_32b_defconfig | 1 + configs/rpi_3_defconfig | 1 + configs/rpi_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/tinker-rk3288_defconfig | 1 + drivers/usb/host/Kconfig | 10 ++++++++++ include/configs/hikey.h | 1 - include/configs/rk3036_common.h | 1 - include/configs/rk3188_common.h | 1 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rpi.h | 1 - include/configs/socfpga_common.h | 3 --- scripts/config_whitelist.txt | 1 - 29 files changed, 30 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index aacf8082661..3a51da82745 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -62,6 +62,7 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 619002422d2..6f093f48cfe 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -65,6 +65,7 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index 20e3e98018f..88d5853d117 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -15,6 +15,7 @@ CONFIG_CMD_CACHE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_K3=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index edf9d082972..715e4b23589 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -33,6 +33,7 @@ CONFIG_PINCTRL_ROCKCHIP_RK3036=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index ffb68f73aca..c6bfa1e9f1e 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -62,6 +62,7 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 64d38b0112a..6d026756dac 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -62,6 +62,7 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 862203f0167..a6f3cd79658 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -19,6 +19,7 @@ CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index 95b16772887..1cbbb2c3575 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -21,6 +21,7 @@ CONFIG_DM_ETH=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index f91b53d4bf7..80e6681332f 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -21,6 +21,7 @@ CONFIG_DM_ETH=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index e2d81ab5a87..5d344fdc870 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -19,6 +19,7 @@ CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index a565384ea12..a3f9ef01ba3 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -57,6 +57,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 06fc82c2617..9e9f781da11 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -57,6 +57,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 0697e2ec373..f11570298cb 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -51,6 +51,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index cd64fb90c34..8f7e45961ec 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -49,6 +49,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index bba90bef28a..7b7909cb62b 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -48,6 +48,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y # CONFIG_EFI_LOADER is not set diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 627b90f7718..88618f8559e 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -50,6 +50,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index bf5d63db3cd..864ec5916ff 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -57,6 +57,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 5915fafbbb9..706ca72f93d 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -57,6 +57,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 18186e83db6..21754b4c5da 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -72,6 +72,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 35046a924bb..c46bacccf33 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -65,6 +65,7 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 5e07a10e752..bc2c1f17e58 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -201,3 +201,13 @@ config USB_UHCI_HCD if USB_UHCI_HCD endif # USB_UHCI_HCD + +config USB_DWC2 + bool "DesignWare USB2 Core support" + select USB_HOST + ---help--- + The DesignWare USB 2.0 controller is compliant with the + USB-Implementers Forum (USB-IF) USB 2.0 specifications. + Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) + operation is compliant to the controller Supplement. If you want to + enable this controller in host mode, say Y. diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 2b4fec4bd42..c7fb8a5f8e9 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -54,7 +54,6 @@ #define CONFIG_PL01X_SERIAL #ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 #define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000 /*#define CONFIG_DWC2_DFLT_SPEED_FULL*/ #define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 1f6b5a1669a..18b7dce94e6 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -72,7 +72,6 @@ /* usb host */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 7f57dd3141a..3ee9abd38d5 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -85,7 +85,6 @@ /* usb host support */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 56565b6ddb5..a145b7434a2 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -65,7 +65,6 @@ /* usb host */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 7d6ef413689..488d67924a0 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -81,7 +81,6 @@ /* usb host support */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/rpi.h b/include/configs/rpi.h index d715eaad14f..b31e2acce6a 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -71,7 +71,6 @@ #define CONFIG_VIDEO_BCM2835 #ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_TFTP_TSIZE diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c17814bf01b..1bed85e78b0 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -224,9 +224,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 -#endif /* * USB Gadget (DFU, UMS) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 54eee53572e..1ab6101ab75 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -5115,7 +5115,6 @@ CONFIG_USB_CABLE_CHECK CONFIG_USB_DEVICE CONFIG_USB_DEV_BASE CONFIG_USB_DEV_PULLUP_GPIO -CONFIG_USB_DWC2 CONFIG_USB_DWC2_REG_ADDR CONFIG_USB_EHCI_ARMADA100 CONFIG_USB_EHCI_BASE -- cgit v1.3.1 From dd22bace7a3fcd7ed6f83350234ecfe09a64bb68 Mon Sep 17 00:00:00 2001 From: Meng Dongyang Date: Wed, 28 Jun 2017 19:22:43 +0800 Subject: usb: dwc2: use dev_read_bool() instead of fdt_getprop() Use dev_read_bool() instead of fdt_getprop() to get the property from DTS. And add a comment for "hnp-srp-disable" property to fully describe its effect. Signed-off-by: Meng Dongyang Reviewed-by: Philipp Tomsich Acked-by: Philipp Tomsich --- drivers/usb/host/dwc2.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 841e596700c..64c42ac4715 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -43,6 +43,10 @@ struct dwc2_priv { struct dwc2_core_regs *regs; int root_hub_devnum; bool ext_vbus; + /* + * The hnp/srp capability must be disabled if the platform + * does't support hnp/srp. Otherwise the force mode can't work. + */ bool hnp_srp_disable; bool oc_disable; }; @@ -1239,7 +1243,6 @@ static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) { struct dwc2_priv *priv = dev_get_priv(dev); - const void *prop; fdt_addr_t addr; addr = devfdt_get_addr(dev); @@ -1247,15 +1250,8 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) return -EINVAL; priv->regs = (struct dwc2_core_regs *)addr; - prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), - "disable-over-current", NULL); - if (prop) - priv->oc_disable = true; - - prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), - "hnp-srp-disable", NULL); - if (prop) - priv->hnp_srp_disable = true; + priv->oc_disable = dev_read_bool(dev, "disable-over-current"); + priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable"); return 0; } -- cgit v1.3.1 From 8926c2f5841148ba0f1b67bb71314797e45229c2 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Mon, 19 Jun 2017 12:36:38 +0200 Subject: power: regulator: rk8xx: Build get_ldo_reg only for SPL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enabling CONFIG_SPL_POWER_SUPPORT will cause a compiler warning: ‘get_ldo_reg’ defined but not used [-Wunused-function] Let's wrap get_ldo_reg(), rk808_ldo and rk818_ldo with ENABLE_DRIVER which is only set for non SPL builds. Signed-off-by: Wadim Egorov Reviewed-by: Simon Glass Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- drivers/power/regulator/rk8xx.c | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index c1ece96b66f..d96a1f85e8f 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -45,6 +45,14 @@ static const struct rk8xx_reg_info rk808_buck[] = { { 1800000, 100000, REG_BUCK4_ON_VSEL, RK808_BUCK4_VSEL_MASK, }, }; +static const struct rk8xx_reg_info rk818_buck[] = { + { 712500, 12500, REG_BUCK1_ON_VSEL, RK818_BUCK_VSEL_MASK, }, + { 712500, 12500, REG_BUCK2_ON_VSEL, RK818_BUCK_VSEL_MASK, }, + { 712500, 12500, -1, RK818_BUCK_VSEL_MASK, }, + { 1800000, 100000, REG_BUCK4_ON_VSEL, RK818_BUCK4_VSEL_MASK, }, +}; + +#ifdef ENABLE_DRIVER static const struct rk8xx_reg_info rk808_ldo[] = { { 1800000, 100000, REG_LDO1_ON_VSEL, RK808_LDO_VSEL_MASK, }, { 1800000, 100000, REG_LDO2_ON_VSEL, RK808_LDO_VSEL_MASK, }, @@ -56,13 +64,6 @@ static const struct rk8xx_reg_info rk808_ldo[] = { { 1800000, 100000, REG_LDO8_ON_VSEL, RK808_LDO_VSEL_MASK, }, }; -static const struct rk8xx_reg_info rk818_buck[] = { - { 712500, 12500, REG_BUCK1_ON_VSEL, RK818_BUCK_VSEL_MASK, }, - { 712500, 12500, REG_BUCK2_ON_VSEL, RK818_BUCK_VSEL_MASK, }, - { 712500, 12500, -1, RK818_BUCK_VSEL_MASK, }, - { 1800000, 100000, REG_BUCK4_ON_VSEL, RK818_BUCK4_VSEL_MASK, }, -}; - static const struct rk8xx_reg_info rk818_ldo[] = { { 1800000, 100000, REG_LDO1_ON_VSEL, RK818_LDO_VSEL_MASK, }, { 1800000, 100000, REG_LDO2_ON_VSEL, RK818_LDO_VSEL_MASK, }, @@ -73,6 +74,7 @@ static const struct rk8xx_reg_info rk818_ldo[] = { { 800000, 100000, REG_LDO7_ON_VSEL, RK818_LDO_VSEL_MASK, }, { 1800000, 100000, REG_LDO8_ON_VSEL, RK818_LDO_VSEL_MASK, }, }; +#endif static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, int num) @@ -86,18 +88,6 @@ static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, } } -static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, - int num) -{ - struct rk8xx_priv *priv = dev_get_priv(pmic); - switch (priv->variant) { - case RK818_ID: - return &rk818_ldo[num]; - default: - return &rk808_ldo[num]; - } -} - static int _buck_set_value(struct udevice *pmic, int buck, int uvolt) { const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck - 1); @@ -133,6 +123,18 @@ static int _buck_set_enable(struct udevice *pmic, int buck, bool enable) } #ifdef ENABLE_DRIVER +static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, + int num) +{ + struct rk8xx_priv *priv = dev_get_priv(pmic); + switch (priv->variant) { + case RK818_ID: + return &rk818_ldo[num]; + default: + return &rk808_ldo[num]; + } +} + static int buck_get_value(struct udevice *dev) { int buck = dev->driver_data - 1; -- cgit v1.3.1 From ad98f882e86d3b7231b8c02bbdf8f7eee735aee6 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Mon, 19 Jun 2017 12:36:39 +0200 Subject: power: regulator: rk8xx: Allow input current/charger shutdown configuration The RK818 PMIC contains a charger. Add very basic charger functionality to be able to regulate the USB input current and charger shutdown limits. Signed-off-by: Wadim Egorov Reviewed-by: Simon Glass Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- drivers/power/regulator/rk8xx.c | 34 ++++++++++++++++++++++++++++++++++ include/power/rk8xx_pmic.h | 2 ++ 2 files changed, 36 insertions(+) (limited to 'drivers') diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index d96a1f85e8f..7c0a3aaa895 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -30,6 +30,9 @@ #define RK818_LDO_VSEL_MASK 0x1f #define RK818_LDO3_ON_VSEL_MASK 0xf #define RK818_BOOST_ON_VSEL_MASK 0xe0 +#define RK818_USB_ILIM_SEL_MASK 0x0f +#define RK818_USB_CHG_SD_VSEL_MASK 0x70 + struct rk8xx_reg_info { uint min_uv; @@ -76,6 +79,14 @@ static const struct rk8xx_reg_info rk818_ldo[] = { }; #endif +static const u16 rk818_chrg_cur_input_array[] = { + 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 +}; + +static const uint rk818_chrg_shutdown_vsel_array[] = { + 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000 +}; + static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, int num) { @@ -353,3 +364,26 @@ int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt) return _buck_set_enable(pmic, buck, true); } + +int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma) +{ + uint i; + + for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++) + if (current_ma <= rk818_chrg_cur_input_array[i]) + break; + + return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i); +} + +int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt) +{ + uint i; + + for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++) + if (uvolt <= rk818_chrg_shutdown_vsel_array[i]) + break; + + return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, + i); +} diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h index 589f8c4e1a9..47a6b36e7ea 100644 --- a/include/power/rk8xx_pmic.h +++ b/include/power/rk8xx_pmic.h @@ -189,5 +189,7 @@ struct rk8xx_priv { }; int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt); +int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma); +int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt); #endif -- cgit v1.3.1 From fe450895ff1a828d39bfd09082000149f2c8d9c3 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 8 Jun 2017 15:32:04 +0800 Subject: rockchip: pinctrl: rk3328: use gpio instead of sdmmc-pwren SDMMC-PWREN is a pin to control voltage for SDMMC IO, it may be high active or low active, the dwmmc driver always assume the sdmmc-pwren as high active. Kernel treat this pin as fixed regulator instead of a pin from controller, and then it can set in dts file upon board schematic, that's a good solution, we can also do this in u-boot. Signed-off-by: Kever Yang Acked-by: Simon Glass Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- drivers/pinctrl/rockchip/pinctrl_rk3328.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c index efa5b3105ce..c74163e026a 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c @@ -184,13 +184,11 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf, if (com_iomux & IOMUX_SEL_SDMMC_MASK) rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_SEL_MASK, - GPIO0D6_SDMMC0_PWRENM1 - << GPIO0D6_SEL_SHIFT); + GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT); else rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A7_SEL_MASK, - GPIO2A7_SDMMC0_PWRENM0 - << GPIO2A7_SEL_SHIFT); + GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT); rk_clrsetreg(&grf->gpio1a_iomux, GPIO1A0_SEL_MASK, GPIO1A0_CARD_DATA_CLK_CMD_DETN -- cgit v1.3.1 From 2454b719fb874120e06e4aa64bfb9450d091e56c Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 26 Jun 2017 10:01:46 +0200 Subject: rockchip: rk3288: Add pinctrl support for the gmac ethernet interface Add support for the gmac ethernet interface to pinctrl. This hardcodes the setup to match that of the firefly and Radxa Rock2 boards, using the RGMII phy mode for gmac interface and GPIO4B0 as the phy reset GPIO. Signed-off-by: Sjoerd Simons Signed-off-by: Romain Perier Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 178 ++++++++++++++++++++++++ drivers/pinctrl/rockchip/pinctrl_rk3288.c | 118 ++++++++++++++++ 2 files changed, 296 insertions(+) (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index fbc4a0d80f8..818e4c56661 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -283,6 +283,163 @@ enum { GPIO3C0_EMMC_CMD, }; +/* GRF_GPIO3DL_IOMUX */ +enum { + GPIO3D3_SHIFT = 12, + GPIO3D3_MASK = 7, + GPIO3D3_GPIO = 0, + GPIO3D3_FLASH1_DATA3, + GPIO3D3_HOST_DOUT3, + GPIO3D3_MAC_RXD3, + GPIO3D3_SDIO1_DATA3, + + GPIO3D2_SHIFT = 8, + GPIO3D2_MASK = 7, + GPIO3D2_GPIO = 0, + GPIO3D2_FLASH1_DATA2, + GPIO3D2_HOST_DOUT2, + GPIO3D2_MAC_RXD2, + GPIO3D2_SDIO1_DATA2, + + GPIO3D1_SHIFT = 4, + GPIO3D1_MASK = 7, + GPIO3D1_GPIO = 0, + GPIO3DL1_FLASH1_DATA1, + GPIO3D1_HOST_DOUT1, + GPIO3D1_MAC_TXD3, + GPIO3D1_SDIO1_DATA1, + + GPIO3D0_SHIFT = 0, + GPIO3D0_MASK = 7, + GPIO3D0_GPIO = 0, + GPIO3D0_FLASH1_DATA0, + GPIO3D0_HOST_DOUT0, + GPIO3D0_MAC_TXD2, + GPIO3D0_SDIO1_DATA0, +}; + +/* GRF_GPIO3HL_IOMUX */ +enum { + GPIO3D7_SHIFT = 12, + GPIO3D7_MASK = 7, + GPIO3D7_GPIO = 0, + GPIO3D7_FLASH1_DATA7, + GPIO3D7_HOST_DOUT7, + GPIO3D7_MAC_RXD1, + GPIO3D7_SDIO1_INTN, + + GPIO3D6_SHIFT = 8, + GPIO3D6_MASK = 7, + GPIO3D6_GPIO = 0, + GPIO3D6_FLASH1_DATA6, + GPIO3D6_HOST_DOUT6, + GPIO3D6_MAC_RXD0, + GPIO3D6_SDIO1_BKPWR, + + GPIO3D5_SHIFT = 4, + GPIO3D5_MASK = 7, + GPIO3D5_GPIO = 0, + GPIO3D5_FLASH1_DATA5, + GPIO3D5_HOST_DOUT5, + GPIO3D5_MAC_TXD1, + GPIO3D5_SDIO1_WRPRT, + + GPIO3D4_SHIFT = 0, + GPIO3D4_MASK = 7, + GPIO3D4_GPIO = 0, + GPIO3D4_FLASH1_DATA4, + GPIO3D4_HOST_DOUT4, + GPIO3D4_MAC_TXD0, + GPIO3D4_SDIO1_DETECTN, +}; + +/* GRF_GPIO4AL_IOMUX */ +enum { + GPIO4A3_SHIFT = 12, + GPIO4A3_MASK = 7, + GPIO4A3_GPIO = 0, + GPIO4A3_FLASH1_ALE, + GPIO4A3_HOST_DOUT9, + GPIO4A3_MAC_CLK, + GPIO4A3_FLASH0_CSN6, + + GPIO4A2_SHIFT = 8, + GPIO4A2_MASK = 7, + GPIO4A2_GPIO = 0, + GPIO4A2_FLASH1_RDN, + GPIO4A2_HOST_DOUT8, + GPIO4A2_MAC_RXER, + GPIO4A2_FLASH0_CSN5, + + GPIO4A1_SHIFT = 4, + GPIO4A1_MASK = 7, + GPIO4A1_GPIO = 0, + GPIO4A1_FLASH1_WP, + GPIO4A1_HOST_CKOUTN, + GPIO4A1_MAC_TXDV, + GPIO4A1_FLASH0_CSN4, + + GPIO4A0_SHIFT = 0, + GPIO4A0_MASK = 3, + GPIO4A0_GPIO = 0, + GPIO4A0_FLASH1_RDY, + GPIO4A0_HOST_CKOUTP, + GPIO4A0_MAC_MDC, +}; + +/* GRF_GPIO4AH_IOMUX */ +enum { + GPIO4A7_SHIFT = 12, + GPIO4A7_MASK = 7, + GPIO4A7_GPIO = 0, + GPIO4A7_FLASH1_CSN1, + GPIO4A7_HOST_DOUT13, + GPIO4A7_MAC_CSR, + GPIO4A7_SDIO1_CLKOUT, + + GPIO4A6_SHIFT = 8, + GPIO4A6_MASK = 7, + GPIO4A6_GPIO = 0, + GPIO4A6_FLASH1_CSN0, + GPIO4A6_HOST_DOUT12, + GPIO4A6_MAC_RXCLK, + GPIO4A6_SDIO1_CMD, + + GPIO4A5_SHIFT = 4, + GPIO4A5_MASK = 3, + GPIO4A5_GPIO = 0, + GPIO4A5_FLASH1_WRN, + GPIO4A5_HOST_DOUT11, + GPIO4A5_MAC_MDIO, + + GPIO4A4_SHIFT = 0, + GPIO4A4_MASK = 7, + GPIO4A4_GPIO = 0, + GPIO4A4_FLASH1_CLE, + GPIO4A4_HOST_DOUT10, + GPIO4A4_MAC_TXEN, + GPIO4A4_FLASH0_CSN7, +}; + +/* GRF_GPIO4BL_IOMUX */ +enum { + GPIO4B1_SHIFT = 4, + GPIO4B1_MASK = 7, + GPIO4B1_GPIO = 0, + GPIO4B1_FLASH1_CSN2, + GPIO4B1_HOST_DOUT15, + GPIO4B1_MAC_TXCLK, + GPIO4B1_SDIO1_PWREN, + + GPIO4B0_SHIFT = 0, + GPIO4B0_MASK = 7, + GPIO4B0_GPIO = 0, + GPIO4B0_FLASH1_DQS, + GPIO4B0_HOST_DOUT14, + GPIO4B0_MAC_COL, + GPIO4B0_FLASH1_CSN3, +}; + /* GRF_GPIO4C_IOMUX */ enum { GPIO4C7_SHIFT = 14, @@ -886,4 +1043,25 @@ enum GRF_SOC_CON8 { RK3288_DPHY_TX0_TURNREQUEST_DIS = 0, }; +/* GPIO Bias settings */ +enum GPIO_BIAS { + GPIO_BIAS_2MA = 0, + GPIO_BIAS_4MA, + GPIO_BIAS_8MA, + GPIO_BIAS_12MA, +}; + +#define GPIO_BIAS_MASK 0x3 +#define GPIO_BIAS_SHIFT(x) ((x) * 2) + +enum GPIO_PU_PD { + GPIO_PULL_NORMAL = 0, + GPIO_PULL_UP, + GPIO_PULL_DOWN, + GPIO_PULL_REPEAT, +}; + +#define GPIO_PULL_MASK 0x3 +#define GPIO_PULL_SHIFT(x) ((x) * 2) + #endif diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c index de5e8343e57..3c9ae974f47 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c @@ -402,6 +402,119 @@ static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id) } } +static void pinctrl_rk3288_gmac_config(struct rk3288_grf *grf, int gmac_id) +{ + switch (gmac_id) { + case PERIPH_ID_GMAC: + rk_clrsetreg(&grf->gpio3dl_iomux, + GPIO3D3_MASK << GPIO3D3_SHIFT | + GPIO3D2_MASK << GPIO3D2_SHIFT | + GPIO3D2_MASK << GPIO3D1_SHIFT | + GPIO3D0_MASK << GPIO3D0_SHIFT, + GPIO3D3_MAC_RXD3 << GPIO3D3_SHIFT | + GPIO3D2_MAC_RXD2 << GPIO3D2_SHIFT | + GPIO3D1_MAC_TXD3 << GPIO3D1_SHIFT | + GPIO3D0_MAC_TXD2 << GPIO3D0_SHIFT); + + rk_clrsetreg(&grf->gpio3dh_iomux, + GPIO3D7_MASK << GPIO3D7_SHIFT | + GPIO3D6_MASK << GPIO3D6_SHIFT | + GPIO3D5_MASK << GPIO3D5_SHIFT | + GPIO3D4_MASK << GPIO3D4_SHIFT, + GPIO3D7_MAC_RXD1 << GPIO3D7_SHIFT | + GPIO3D6_MAC_RXD0 << GPIO3D6_SHIFT | + GPIO3D5_MAC_TXD1 << GPIO3D5_SHIFT | + GPIO3D4_MAC_TXD0 << GPIO3D4_SHIFT); + + /* switch the Tx pins to 12ma drive-strength */ + rk_clrsetreg(&grf->gpio1_e[2][3], + GPIO_BIAS_MASK | + (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1)) | + (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4)) | + (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(5)), + (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(0)) | + (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1)) | + (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4)) | + (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(5))); + + /* Set normal pull for all GPIO3D pins */ + rk_clrsetreg(&grf->gpio1_p[2][3], + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)), + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7))); + + rk_clrsetreg(&grf->gpio4al_iomux, + GPIO4A3_MASK << GPIO4A3_SHIFT | + GPIO4A1_MASK << GPIO4A1_SHIFT | + GPIO4A0_MASK << GPIO4A0_SHIFT, + GPIO4A3_MAC_CLK << GPIO4A3_SHIFT | + GPIO4A1_MAC_TXDV << GPIO4A1_SHIFT | + GPIO4A0_MAC_MDC << GPIO4A0_SHIFT); + + rk_clrsetreg(&grf->gpio4ah_iomux, + GPIO4A6_MASK << GPIO4A6_SHIFT | + GPIO4A5_MASK << GPIO4A5_SHIFT | + GPIO4A4_MASK << GPIO4A4_SHIFT, + GPIO4A6_MAC_RXCLK << GPIO4A6_SHIFT | + GPIO4A5_MAC_MDIO << GPIO4A5_SHIFT | + GPIO4A4_MAC_TXEN << GPIO4A4_SHIFT); + + /* switch GPIO4A4 to 12ma drive-strength */ + rk_clrsetreg(&grf->gpio1_e[3][0], + GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4), + GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4)); + + /* Set normal pull for all GPIO4A pins */ + rk_clrsetreg(&grf->gpio1_p[3][0], + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)), + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7))); + + /* switch GPIO4B1 to 12ma drive-strength */ + rk_clrsetreg(&grf->gpio1_e[3][1], + GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1), + GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1)); + + /* Set pull normal for GPIO4B1, pull up for GPIO4B0 */ + rk_clrsetreg(&grf->gpio1_p[3][1], + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)), + (GPIO_PULL_UP << GPIO_PULL_SHIFT(0)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1))); + + break; + default: + printf("gmac id = %d iomux error!\n", gmac_id); + break; + } +} + #ifndef CONFIG_SPL_BUILD static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id) { @@ -465,6 +578,9 @@ static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk3288_sdmmc_config(priv->grf, func); break; + case PERIPH_ID_GMAC: + pinctrl_rk3288_gmac_config(priv->grf, func); + break; default: return -EINVAL; } @@ -484,6 +600,8 @@ static int rk3288_pinctrl_get_periph_id(struct udevice *dev, return -EINVAL; switch (cell[1]) { + case 27: + return PERIPH_ID_GMAC; case 44: return PERIPH_ID_SPI0; case 45: -- cgit v1.3.1