From 0c0a9cda1bde37106520476ed486bd67eb8d30ae Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 16 Jul 2007 00:31:07 +0200 Subject: [PATCH] Support for Xilinx EmacLite controller --- drivers/net/Makefile | 45 +++++ drivers/net/xilinx_emaclite.c | 378 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 423 insertions(+) create mode 100644 drivers/net/Makefile create mode 100644 drivers/net/xilinx_emaclite.c (limited to 'drivers') diff --git a/drivers/net/Makefile b/drivers/net/Makefile new file mode 100644 index 00000000000..a10d0819f98 --- /dev/null +++ b/drivers/net/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libnetdrv.a + +COBJS := xilinx_emaclite.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c new file mode 100644 index 00000000000..7e69211af94 --- /dev/null +++ b/drivers/net/xilinx_emaclite.c @@ -0,0 +1,378 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef XILINX_EMACLITE_BASEADDR + +//#define DEBUG + +#define ENET_MAX_MTU PKTSIZE +#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN +#define ENET_ADDR_LENGTH 6 + +/* EmacLite constants */ +#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ +#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ +#define XEL_TSR_OFFSET 0x07FC /* Tx status */ +#define XEL_RSR_OFFSET 0x17FC /* Rx status */ +#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ + +/* Xmit complete */ +#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL +/* Xmit interrupt enable bit */ +#define XEL_TSR_XMIT_IE_MASK 0x00000008UL +/* Buffer is active, SW bit only */ +#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL +/* Program the MAC address */ +#define XEL_TSR_PROGRAM_MASK 0x00000002UL +/* define for programming the MAC address into the EMAC Lite */ +#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) + +/* Transmit packet length upper byte */ +#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL +/* Transmit packet length lower byte */ +#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL + +/* Recv complete */ +#define XEL_RSR_RECV_DONE_MASK 0x00000001UL +/* Recv interrupt enable bit */ +#define XEL_RSR_RECV_IE_MASK 0x00000008UL + +typedef struct { + unsigned int BaseAddress; /* Base address for device (IPIF) */ + unsigned int NextTxBufferToUse; /* Next TX buffer to write to */ + unsigned int NextRxBufferToUse; /* Next RX buffer to read from */ + unsigned char DeviceId; /* Unique ID of device - for future */ +} XEmacLite; + +static XEmacLite EmacLite; + +static char etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ + +/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/ +#ifdef CFG_ENV_IS_NOWHERE +static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; +#endif + +void XEmacLite_AlignedRead (u32 * SrcPtr, void *DestPtr, unsigned ByteCount) +{ + unsigned i; + unsigned Length = ByteCount; + u32 AlignBuffer; + u32 *To32Ptr; + u32 *From32Ptr; + u8 *To8Ptr; + u8 *From8Ptr; + + From32Ptr = (u32 *) SrcPtr; + + /* Word aligned buffer, no correction needed. */ + To32Ptr = (u32 *) DestPtr; + while (Length > 3) { + *To32Ptr++ = *From32Ptr++; + Length -= 4; + } + To8Ptr = (u8 *) To32Ptr; + + AlignBuffer = *From32Ptr++; + From8Ptr = (u8 *) & AlignBuffer; + + for (i = 0; i < Length; i++) { + *To8Ptr++ = *From8Ptr++; + } +} + +void XEmacLite_AlignedWrite (void *SrcPtr, u32 * DestPtr, unsigned ByteCount) +{ + unsigned i; + unsigned Length = ByteCount; + u32 AlignBuffer; + u32 *To32Ptr; + u32 *From32Ptr; + u8 *To8Ptr; + u8 *From8Ptr; + To32Ptr = DestPtr; + + From32Ptr = (u32 *) SrcPtr; + while (Length > 3) { + + *To32Ptr++ = *From32Ptr++; + Length -= 4; + } + + AlignBuffer = 0; + To8Ptr = (u8 *) & AlignBuffer; + From8Ptr = (u8 *) From32Ptr; + + for (i = 0; i < Length; i++) { + *To8Ptr++ = *From8Ptr++; + } + + *To32Ptr++ = AlignBuffer; +} + +void eth_halt (void) +{ +#ifdef DEBUG + puts ("eth_halt\n"); +#endif +} + +int eth_init (bd_t * bis) +{ +#ifdef DEBUG + puts ("EmacLite Initialization Started\n"); +#endif + memset (&EmacLite, 0, sizeof (XEmacLite)); + EmacLite.BaseAddress = XILINX_EMACLITE_BASEADDR; + +#ifdef CFG_ENV_IS_NOWHERE + memcpy (bis->bi_enetaddr, EMACAddr, ENET_ADDR_LENGTH); +#endif +/* + * TX - TX_PING & TX_PONG initialization + */ + /* Restart PING TX */ + out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, 0); + /* Copy MAC address */ + XEmacLite_AlignedWrite (bis->bi_enetaddr, + EmacLite.BaseAddress, ENET_ADDR_LENGTH); + /* Set the length */ + out_be32 (EmacLite.BaseAddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + /* Update the MAC address in the EMAC Lite */ + out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); + /* Wait for EMAC Lite to finish with the MAC address update */ + while ((in_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET) & + XEL_TSR_PROG_MAC_ADDR) != 0) ; + +#ifdef XILINX_EMACLITE_TX_PING_PONG + /* The same operation with PONG TX */ + out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); + XEmacLite_AlignedWrite (bis->bi_enetaddr, + EmacLite.BaseAddress + XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); + out_be32 (EmacLite.BaseAddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, + XEL_TSR_PROG_MAC_ADDR); + while ((in_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + + XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ; +#endif + +/* + * RX - RX_PING & RX_PONG initialization + */ + /* Write out the value to flush the RX buffer */ + out_be32 (EmacLite.BaseAddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); +#ifdef XILINX_EMACLITE_RX_PING_PONG + out_be32 (EmacLite.BaseAddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, + XEL_RSR_RECV_IE_MASK); +#endif + +#ifdef DEBUG + puts ("EmacLite Initialization complete\n"); +#endif + return 0; +} + +int XEmacLite_TxBufferAvailable (XEmacLite * InstancePtr) +{ + u32 Register; + u32 TxPingBusy; + u32 TxPongBusy; + /* + * Read the other buffer register + * and determine if the other buffer is available + */ + Register = in_be32 (InstancePtr->BaseAddress + + InstancePtr->NextTxBufferToUse + 0); + TxPingBusy = ((Register & XEL_TSR_XMIT_BUSY_MASK) == + XEL_TSR_XMIT_BUSY_MASK); + + Register = in_be32 (InstancePtr->BaseAddress + + (InstancePtr->NextTxBufferToUse ^ XEL_TSR_OFFSET) + 0); + TxPongBusy = ((Register & XEL_TSR_XMIT_BUSY_MASK) == + XEL_TSR_XMIT_BUSY_MASK); + + return (!(TxPingBusy && TxPongBusy)); +} + +int eth_send (volatile void *ptr, int len) { + + unsigned int Register; + unsigned int BaseAddress; + + unsigned maxtry = 1000; + + if (len > ENET_MAX_MTU) + len = ENET_MAX_MTU; + + while (!XEmacLite_TxBufferAvailable (&EmacLite) && maxtry) { + udelay (10); + maxtry--; + } + + if (!maxtry) { + printf ("Error: Timeout waiting for ethernet TX buffer\n"); + /* Restart PING TX */ + out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, 0); +#ifdef XILINX_EMACLITE_TX_PING_PONG + out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + + XEL_BUFFER_OFFSET, 0); +#endif + return 0; + } + + /* Determine the expected TX buffer address */ + BaseAddress = (EmacLite.BaseAddress + EmacLite.NextTxBufferToUse); + + /* Determine if the expected buffer address is empty */ + Register = in_be32 (BaseAddress + XEL_TSR_OFFSET); + if (((Register & XEL_TSR_XMIT_BUSY_MASK) == 0) + && ((in_be32 ((BaseAddress) + XEL_TSR_OFFSET) + & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { + +#ifdef XILINX_EMACLITE_TX_PING_PONG + EmacLite.NextTxBufferToUse ^= XEL_BUFFER_OFFSET; +#endif +#ifdef DEBUG + printf ("Send packet from 0x%x\n", BaseAddress); +#endif + /* Write the frame to the buffer */ + XEmacLite_AlignedWrite (ptr, (u32 *) BaseAddress, len); + out_be32 (BaseAddress + XEL_TPLR_OFFSET,(len & + (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); + Register = in_be32 (BaseAddress + XEL_TSR_OFFSET); + Register |= XEL_TSR_XMIT_BUSY_MASK; + if ((Register & XEL_TSR_XMIT_IE_MASK) != 0) { + Register |= XEL_TSR_XMIT_ACTIVE_MASK; + } + out_be32 (BaseAddress + XEL_TSR_OFFSET, Register); + return 1; + } +#ifdef XILINX_EMACLITE_TX_PING_PONG + /* Switch to second buffer */ + BaseAddress ^= XEL_BUFFER_OFFSET; + /* Determine if the expected buffer address is empty */ + Register = in_be32 (BaseAddress + XEL_TSR_OFFSET); + if (((Register & XEL_TSR_XMIT_BUSY_MASK) == 0) + && ((in_be32 ((BaseAddress) + XEL_TSR_OFFSET) + & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { +#ifdef DEBUG + printf ("Send packet from 0x%x\n", BaseAddress); +#endif + /* Write the frame to the buffer */ + XEmacLite_AlignedWrite (ptr, (u32 *) BaseAddress, len); + out_be32 (BaseAddress + XEL_TPLR_OFFSET,(len & + (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); + Register = in_be32 (BaseAddress + XEL_TSR_OFFSET); + Register |= XEL_TSR_XMIT_BUSY_MASK; + if ((Register & XEL_TSR_XMIT_IE_MASK) != 0) { + Register |= XEL_TSR_XMIT_ACTIVE_MASK; + } + out_be32 (BaseAddress + XEL_TSR_OFFSET, Register); + return 1; + } +#endif + puts ("Error while sending frame\n"); + return 0; +} + +int eth_rx (void) +{ + unsigned int Length; + unsigned int Register; + unsigned int BaseAddress; + + BaseAddress = EmacLite.BaseAddress + EmacLite.NextRxBufferToUse; + Register = in_be32 (BaseAddress + XEL_RSR_OFFSET); +#ifdef DEBUG +// printf ("Testing data at address 0x%x\n", BaseAddress); +#endif + if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { +#ifdef XILINX_EMACLITE_RX_PING_PONG + EmacLite.NextRxBufferToUse ^= XEL_BUFFER_OFFSET; +#endif + } else { +#ifndef XILINX_EMACLITE_RX_PING_PONG +#ifdef DEBUG +// printf ("No data was available - address 0x%x\n", BaseAddress); +#endif + return 0; +#else + BaseAddress ^= XEL_BUFFER_OFFSET; + Register = in_be32 (BaseAddress + XEL_RSR_OFFSET); + if ((Register & XEL_RSR_RECV_DONE_MASK) != + XEL_RSR_RECV_DONE_MASK) { +#ifdef DEBUG +// printf ("No data was available - address 0x%x\n", +// BaseAddress); +#endif + return 0; + } +#endif + } + /* Get the length of the frame that arrived */ + switch(((in_be32(BaseAddress + XEL_RXBUFF_OFFSET + 0xC)) & + 0xFFFF0000 ) >> 16) { + case 0x806: + Length = 42 + 20; /* FIXME size of ARP */ +#ifdef DEBUG + puts ("ARP Packet\n"); +#endif + break; + case 0x800: + Length = 14 + 14 + + (((in_be32(BaseAddress + XEL_RXBUFF_OFFSET + 0x10)) & + 0xFFFF0000) >> 16); /* FIXME size of IP packet */ +#ifdef DEBUG + puts("IP Packet\n"); +#endif + break; + default: +#ifdef DEBUG + puts("Other Packet\n"); +#endif + Length = ENET_MAX_MTU; + break; + } + + XEmacLite_AlignedRead ((BaseAddress + XEL_RXBUFF_OFFSET), + etherrxbuff, Length); + + /* Acknowledge the frame */ + Register = in_be32 (BaseAddress + XEL_RSR_OFFSET); + Register &= ~XEL_RSR_RECV_DONE_MASK; + out_be32 (BaseAddress + XEL_RSR_OFFSET, Register); + +#ifdef DEBUG + printf ("Packet receive from 0x%x, length %dB\n", BaseAddress, Length); +#endif + NetReceive ((uchar *) etherrxbuff, Length); + return 1; + +} +#endif -- cgit v1.3.1 From 537091b4eed9302865d03fef3f7212b4fe5cf28f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sun, 5 Aug 2007 15:53:50 +0200 Subject: [PATCH] Added support for Xilinx Emac community driver --- drivers/net/Makefile | 2 +- drivers/net/xilinx_emac.c | 372 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/xilinx_emac.h | 128 ++++++++++++++++ 3 files changed, 501 insertions(+), 1 deletion(-) create mode 100644 drivers/net/xilinx_emac.c create mode 100644 drivers/net/xilinx_emac.h (limited to 'drivers') diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a10d0819f98..7342dc8ce6c 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libnetdrv.a -COBJS := xilinx_emaclite.o +COBJS := xilinx_emaclite.o xilinx_emac.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/net/xilinx_emac.c b/drivers/net/xilinx_emac.c new file mode 100644 index 00000000000..d44f31e8aff --- /dev/null +++ b/drivers/net/xilinx_emac.c @@ -0,0 +1,372 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on Xilinx drivers + * + */ + +#include +#include +#include +#include +#include +#include "xilinx_emac.h" + +#ifdef XILINX_EMAC + +#undef DEBUG + +#define ENET_MAX_MTU PKTSIZE +#define ENET_ADDR_LENGTH 6 + +static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ + +static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; + +static XEmac Emac; + +void eth_halt(void) +{ + return; +} + +int eth_init(bd_t * bis) +{ + u32 HelpReg; +#ifdef DEBUG + printf("EMAC Initialization Started\n\r"); +#endif + if (Emac.IsStarted) { + puts("Emac is started\n"); + return 0; + } + + memset (&Emac, 0, sizeof (XEmac)); + + Emac.BaseAddress = XILINX_EMAC_BASEADDR; + + /* Setting up FIFOs */ + Emac.RecvFifo.RegBaseAddress = Emac.BaseAddress + + XEM_PFIFO_RXREG_OFFSET; + Emac.RecvFifo.DataBaseAddress = Emac.BaseAddress + + XEM_PFIFO_RXDATA_OFFSET; + out_be32 (Emac.RecvFifo.RegBaseAddress, XPF_RESET_FIFO_MASK); + + Emac.SendFifo.RegBaseAddress = Emac.BaseAddress + + XEM_PFIFO_TXREG_OFFSET; + Emac.SendFifo.DataBaseAddress = Emac.BaseAddress + + XEM_PFIFO_TXDATA_OFFSET; + out_be32 (Emac.SendFifo.RegBaseAddress, XPF_RESET_FIFO_MASK); + + /* Reset the entire IPIF */ + out_be32 (Emac.BaseAddress + XIIF_V123B_RESETR_OFFSET, + XIIF_V123B_RESET_MASK); + + /* Stopping EMAC for setting up MAC */ + HelpReg = in_be32 (Emac.BaseAddress + XEM_ECR_OFFSET); + HelpReg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); + out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg); + + if (!getenv("ethaddr")) { + memcpy(bis->bi_enetaddr, EMACAddr, ENET_ADDR_LENGTH); + } + + /* Set the device station address high and low registers */ + HelpReg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1]; + out_be32 (Emac.BaseAddress + XEM_SAH_OFFSET, HelpReg); + HelpReg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) | + (bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5]; + out_be32 (Emac.BaseAddress + XEM_SAL_OFFSET, HelpReg); + + + HelpReg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK | + XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK | + XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK; + out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg); + + Emac.IsStarted = 1; + + /* Enable the transmitter, and receiver */ + HelpReg = in_be32 (Emac.BaseAddress + XEM_ECR_OFFSET); + HelpReg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); + HelpReg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); + out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg); + + printf("EMAC Initialization complete\n\r"); + return 0; +} + +int eth_send(volatile void *ptr, int len) +{ + u32 IntrStatus; + u32 XmitStatus; + u32 FifoCount; + u32 WordCount; + u32 ExtraByteCount; + u32 *WordBuffer = (u32 *) ptr; + + if (len > ENET_MAX_MTU) + len = ENET_MAX_MTU; + + /* + * Check for overruns and underruns for the transmit status and length + * FIFOs and make sure the send packet FIFO is not deadlocked. + * Any of these conditions is bad enough that we do not want to + * continue. The upper layer software should reset the device to resolve + * the error. + */ + IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET); + if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | + XEM_EIR_XMIT_LFIFO_OVER_MASK)) { +#ifdef DEBUG + puts ("Transmitting overrun error\n"); +#endif + return 0; + } else if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | + XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { +#ifdef DEBUG + puts ("Transmitting underrun error\n"); +#endif + return 0; + } else if (in_be32 (Emac.SendFifo.RegBaseAddress + + XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) { +#ifdef DEBUG + puts("Transmitting fifo error\n"); +#endif + return 0; + } + + /* + * Before writing to the data FIFO, make sure the length FIFO is not + * full. The data FIFO might not be full yet even though the length FIFO + * is. This avoids an overrun condition on the length FIFO and keeps the + * FIFOs in sync. + * + * Clear the latched LFIFO_FULL bit so next time around the most + * current status is represented + */ + if (IntrStatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) { + out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, IntrStatus + & XEM_EIR_XMIT_LFIFO_FULL_MASK); +#ifdef DEBUG + puts ("Fifo is full\n"); +#endif + return 0; + } + + /* get the count of how many words may be inserted into the FIFO */ + FifoCount = in_be32 (Emac.SendFifo.RegBaseAddress + + XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; + WordCount = len >> 2; + ExtraByteCount = len & 0x3; + + if (FifoCount < WordCount) { +#ifdef DEBUG + puts ("Sending packet is larger then size of FIFO\n"); +#endif + return 0; + } + + for (FifoCount = 0; FifoCount < WordCount; FifoCount++) { + out_be32 (Emac.SendFifo.DataBaseAddress, WordBuffer[FifoCount]); + } + if (ExtraByteCount > 0) { + u32 LastWord = 0; + u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount); + + if (ExtraByteCount == 1) { + LastWord = ExtraBytesBuffer[0] << 24; + } else if (ExtraByteCount == 2) { + LastWord = ExtraBytesBuffer[0] << 24 | + ExtraBytesBuffer[1] << 16; + } else if (ExtraByteCount == 3) { + LastWord = ExtraBytesBuffer[0] << 24 | + ExtraBytesBuffer[1] << 16 | + ExtraBytesBuffer[2] << 8; + } + out_be32 (Emac.SendFifo.DataBaseAddress, LastWord); + } + + /* Loop on the MAC's status to wait for any pause to complete */ + IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET); + while ((IntrStatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) { + IntrStatus = in_be32 ((Emac.BaseAddress) + + XIIF_V123B_IISR_OFFSET); + /* Clear the pause status from the transmit status register */ + out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, + IntrStatus & XEM_EIR_XMIT_PAUSE_MASK); + } + + /* + * Set the MAC's transmit packet length register to tell it to transmit + */ + out_be32 (Emac.BaseAddress + XEM_TPLR_OFFSET, len); + + /* + * Loop on the MAC's status to wait for the transmit to complete. + * The transmit status is in the FIFO when the XMIT_DONE bit is set. + */ + do { + IntrStatus = in_be32 ((Emac.BaseAddress) + + XIIF_V123B_IISR_OFFSET); + } + while ((IntrStatus & XEM_EIR_XMIT_DONE_MASK) == 0); + + XmitStatus = in_be32 (Emac.BaseAddress + XEM_TSR_OFFSET); + + if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | + XEM_EIR_XMIT_LFIFO_OVER_MASK)) { +#ifdef DEBUG + puts ("Transmitting overrun error\n"); +#endif + return 0; + } else if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | + XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { +#ifdef DEBUG + puts ("Transmitting underrun error\n"); +#endif + return 0; + } + + /* Clear the interrupt status register of transmit statuses */ + out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, + IntrStatus & XEM_EIR_XMIT_ALL_MASK); + + /* + * Collision errors are stored in the transmit status register + * instead of the interrupt status register + */ + if ((XmitStatus & XEM_TSR_EXCESS_DEFERRAL_MASK) || + (XmitStatus & XEM_TSR_LATE_COLLISION_MASK)) { +#ifdef DEBUG + puts ("Transmitting collision error\n"); +#endif + return 0; + } + return 1; +} + +int eth_rx(void) +{ + u32 PktLength; + u32 IntrStatus; + u32 FifoCount; + u32 WordCount; + u32 ExtraByteCount; + u32 LastWord; + u8 *ExtraBytesBuffer; + + if (in_be32 (Emac.RecvFifo.RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) + & XPF_DEADLOCK_MASK) { + out_be32 (Emac.RecvFifo.RegBaseAddress, XPF_RESET_FIFO_MASK); +#ifdef DEBUG + puts ("Receiving FIFO deadlock\n"); +#endif + return 0; + } + + /* + * Get the interrupt status to know what happened (whether an error occurred + * and/or whether frames have been received successfully). When clearing the + * intr status register, clear only statuses that pertain to receive. + */ + IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET); + /* + * Before reading from the length FIFO, make sure the length FIFO is not + * empty. We could cause an underrun error if we try to read from an + * empty FIFO. + */ + if (!(IntrStatus & XEM_EIR_RECV_DONE_MASK)) { +#ifdef DEBUG + /* puts("Receiving FIFO is empty\n"); */ +#endif + return 0; + } + + /* + * Determine, from the MAC, the length of the next packet available + * in the data FIFO (there should be a non-zero length here) + */ + PktLength = in_be32 (Emac.BaseAddress + XEM_RPLR_OFFSET); + if (!PktLength) { + return 0; + } + + /* + * Write the RECV_DONE bit in the status register to clear it. This bit + * indicates the RPLR is non-empty, and we know it's set at this point. + * We clear it so that subsequent entry into this routine will reflect + * the current status. This is done because the non-empty bit is latched + * in the IPIF, which means it may indicate a non-empty condition even + * though there is something in the FIFO. + */ + out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, + XEM_EIR_RECV_DONE_MASK); + + FifoCount = in_be32 (Emac.RecvFifo.RegBaseAddress + + XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; + + if ((FifoCount * 4) < PktLength) { +#ifdef DEBUG + puts ("Receiving FIFO is smaller than packet size.\n"); +#endif + return 0; + } + + WordCount = PktLength >> 2; + ExtraByteCount = PktLength & 0x3; + + for (FifoCount = 0; FifoCount < WordCount; FifoCount++) { + etherrxbuff[FifoCount] = + in_be32 (Emac.RecvFifo.DataBaseAddress); + } + + /* + * if there are extra bytes to handle, read the last word from the FIFO + * and insert the extra bytes into the buffer + */ + if (ExtraByteCount > 0) { + ExtraBytesBuffer = (u8 *) (etherrxbuff + WordCount); + + LastWord = in_be32 (Emac.RecvFifo.DataBaseAddress); + + /* + * one extra byte in the last word, put the byte into the next + * location of the buffer, bytes in a word of the FIFO are + * ordered from most significant byte to least + */ + if (ExtraByteCount == 1) { + ExtraBytesBuffer[0] = (u8) (LastWord >> 24); + } else if (ExtraByteCount == 2) { + ExtraBytesBuffer[0] = (u8) (LastWord >> 24); + ExtraBytesBuffer[1] = (u8) (LastWord >> 16); + } else if (ExtraByteCount == 3) { + ExtraBytesBuffer[0] = (u8) (LastWord >> 24); + ExtraBytesBuffer[1] = (u8) (LastWord >> 16); + ExtraBytesBuffer[2] = (u8) (LastWord >> 8); + } + } + NetReceive((uchar *)etherrxbuff, PktLength); + return 1; +} +#endif diff --git a/drivers/net/xilinx_emac.h b/drivers/net/xilinx_emac.h new file mode 100644 index 00000000000..ab4d2121f13 --- /dev/null +++ b/drivers/net/xilinx_emac.h @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on Xilinx drivers + * + */ + +typedef struct { + u32 RegBaseAddress; /* Base address of registers */ + u32 DataBaseAddress; /* Base address of data for FIFOs */ +} XPacketFifoV100b; + +typedef struct { + u32 BaseAddress; /* Base address (of IPIF) */ + u32 IsStarted; /* Device is currently started 0-no, 1-yes */ + XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */ + XPacketFifoV100b SendFifo; /* FIFO used to send frames */ + +} XEmac; + +#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ +#define XIIF_V123B_RESET_MASK 0xAUL +#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ + +/* This constant is used with the Reset Register */ +#define XPF_RESET_FIFO_MASK 0x0000000A +#define XPF_COUNT_STATUS_REG_OFFSET 4UL + +/* * These constants are used with the Occupancy/Vacancy Count Register. This + * register also contains FIFO status */ +#define XPF_COUNT_MASK 0x0000FFFF +#define XPF_DEADLOCK_MASK 0x20000000 + +/* Offset of the MAC registers from the IPIF base address */ +#define XEM_REG_OFFSET 0x1100UL + +/* + * Register offsets for the Ethernet MAC. Each register is 32 bits. + */ +#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */ +#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */ +#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */ +#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */ +#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */ +#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */ + + + +#define XEM_PFIFO_OFFSET 0x2000UL +#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) /* Tx registers */ +#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) /* Rx registers */ +#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) /* Tx keyhole */ +#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) /* Rx keyhole */ + + +/* + * EMAC Interrupt Registers (Status and Enable) masks. These registers are + * part of the IPIF IP Interrupt registers + */ +/* A mask for all transmit interrupts, used in polled mode */ +#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK | \ + XEM_EIR_XMIT_ERROR_MASK | \ + XEM_EIR_XMIT_SFIFO_EMPTY_MASK | \ + XEM_EIR_XMIT_LFIFO_FULL_MASK) + +#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */ +#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */ +#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */ +#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */ +#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */ +#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */ +#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */ +#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo + * overrun */ +#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo + * underrun */ +#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo + * overrun */ +#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo + * underrun */ +#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo + * overrun */ +#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo + * underrun */ +#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt + * received */ + +/* + * EMAC Control Register (ECR) + */ +#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL /* Full duplex mode */ +#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL /* Reset transmitter */ +#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL /* Enable transmitter */ +#define XEM_ECR_RECV_RESET_MASK 0x10000000UL /* Reset receiver */ +#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL /* Enable receiver */ +#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL /* Enable PHY */ +#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL /* Enable xmit pad + * insert */ +#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL /* Enable xmit FCS + * insert */ +#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL /* Enable unicast + * addr */ +#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL /* Enable broadcast + * addr */ + +/* Transmit Status Register (TSR) */ +#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */ +#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */ -- cgit v1.3.1 From af8377d4eb3a0ac5a831830d5ce63fbf65fecb7f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sun, 5 Aug 2007 16:13:31 +0200 Subject: [FIX] Xilinx Uartlite driver Because PPC405 can use UARTLITE serial interface and Microblaze can use Uart16550 serial interface not only Uartlite. --- drivers/serial_xuartlite.c | 2 +- include/configs/ml401.h | 1 + include/configs/suzaku.h | 1 + include/configs/xupv2p.h | 1 + 4 files changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial_xuartlite.c b/drivers/serial_xuartlite.c index ed59abea862..1f3aaae4034 100644 --- a/drivers/serial_xuartlite.c +++ b/drivers/serial_xuartlite.c @@ -24,7 +24,7 @@ #include -#ifdef CONFIG_MICROBLAZE +#ifdef XILINX_UARTLITE #include diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 3db287784da..a6026528b30 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -32,6 +32,7 @@ #define CONFIG_ML401 1 /* ML401 Board */ /* uart */ +#define XILINX_UARTLITE #define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR #define CONFIG_BAUDRATE XILINX_UART_BAUDRATE #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE } diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h index ca5c7519c61..9661726b2ba 100644 --- a/include/configs/suzaku.h +++ b/include/configs/suzaku.h @@ -48,6 +48,7 @@ #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - (1024 * 1024)) +#define XILINX_UARTLITE #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 115200 } diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h index 25fa4956412..bac31f476b0 100644 --- a/include/configs/xupv2p.h +++ b/include/configs/xupv2p.h @@ -32,6 +32,7 @@ /* uart */ #ifdef XILINX_UARTLITE_BASEADDR +#define XILINX_UARTLITE #define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR #define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE } -- cgit v1.3.1 From a274ca4f6d68830e7c916f897561cff8c4101c38 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sun, 5 Aug 2007 22:33:05 +0200 Subject: [FIX] Coding style cleanup --- drivers/net/xilinx_emac.h | 71 +++++++++++++++++++++---------------------- drivers/net/xilinx_emaclite.c | 10 +++--- include/configs/ml401.h | 10 +++--- 3 files changed, 45 insertions(+), 46 deletions(-) (limited to 'drivers') diff --git a/drivers/net/xilinx_emac.h b/drivers/net/xilinx_emac.h index ab4d2121f13..7c00eebf048 100644 --- a/drivers/net/xilinx_emac.h +++ b/drivers/net/xilinx_emac.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2007 Michal Simek * - * Michal SIMEK + * Michal SIMEK * * See file CREDITS for list of people who contributed to this * project. @@ -13,7 +13,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -35,34 +35,33 @@ typedef struct { u32 IsStarted; /* Device is currently started 0-no, 1-yes */ XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */ XPacketFifoV100b SendFifo; /* FIFO used to send frames */ - } XEmac; -#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ +#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ #define XIIF_V123B_RESET_MASK 0xAUL #define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ /* This constant is used with the Reset Register */ -#define XPF_RESET_FIFO_MASK 0x0000000A -#define XPF_COUNT_STATUS_REG_OFFSET 4UL +#define XPF_RESET_FIFO_MASK 0x0000000A +#define XPF_COUNT_STATUS_REG_OFFSET 4UL -/* * These constants are used with the Occupancy/Vacancy Count Register. This - * register also contains FIFO status */ -#define XPF_COUNT_MASK 0x0000FFFF -#define XPF_DEADLOCK_MASK 0x20000000 +/* These constants are used with the Occupancy/Vacancy Count Register. This + * register also contains FIFO status */ +#define XPF_COUNT_MASK 0x0000FFFF +#define XPF_DEADLOCK_MASK 0x20000000 /* Offset of the MAC registers from the IPIF base address */ -#define XEM_REG_OFFSET 0x1100UL +#define XEM_REG_OFFSET 0x1100UL /* * Register offsets for the Ethernet MAC. Each register is 32 bits. */ -#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */ -#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */ -#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */ -#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */ -#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */ -#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */ +#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */ +#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */ +#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */ +#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */ +#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */ +#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */ @@ -78,31 +77,31 @@ typedef struct { * part of the IPIF IP Interrupt registers */ /* A mask for all transmit interrupts, used in polled mode */ -#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK | \ - XEM_EIR_XMIT_ERROR_MASK | \ - XEM_EIR_XMIT_SFIFO_EMPTY_MASK | \ +#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK |\ + XEM_EIR_XMIT_ERROR_MASK | \ + XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\ XEM_EIR_XMIT_LFIFO_FULL_MASK) -#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */ -#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */ -#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */ -#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */ -#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */ -#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */ -#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */ -#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo +#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */ +#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */ +#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */ +#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */ +#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */ +#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */ +#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */ +#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo * overrun */ -#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo +#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo * underrun */ -#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo +#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo * overrun */ -#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo +#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo * underrun */ -#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo +#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo * overrun */ -#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo +#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo * underrun */ -#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt +#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt * received */ /* @@ -124,5 +123,5 @@ typedef struct { * addr */ /* Transmit Status Register (TSR) */ -#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */ -#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */ +#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */ +#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */ diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 7e69211af94..99e70354b61 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -29,7 +29,7 @@ #ifdef XILINX_EMACLITE_BASEADDR -//#define DEBUG +#undef DEBUG #define ENET_MAX_MTU PKTSIZE #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN @@ -310,7 +310,7 @@ int eth_rx (void) BaseAddress = EmacLite.BaseAddress + EmacLite.NextRxBufferToUse; Register = in_be32 (BaseAddress + XEL_RSR_OFFSET); #ifdef DEBUG -// printf ("Testing data at address 0x%x\n", BaseAddress); + printf ("Testing data at address 0x%x\n", BaseAddress); #endif if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { #ifdef XILINX_EMACLITE_RX_PING_PONG @@ -319,7 +319,7 @@ int eth_rx (void) } else { #ifndef XILINX_EMACLITE_RX_PING_PONG #ifdef DEBUG -// printf ("No data was available - address 0x%x\n", BaseAddress); + printf ("No data was available - address 0x%x\n", BaseAddress); #endif return 0; #else @@ -328,8 +328,8 @@ int eth_rx (void) if ((Register & XEL_RSR_RECV_DONE_MASK) != XEL_RSR_RECV_DONE_MASK) { #ifdef DEBUG -// printf ("No data was available - address 0x%x\n", -// BaseAddress); + printf ("No data was available - address 0x%x\n", + BaseAddress); #endif return 0; } diff --git a/include/configs/ml401.h b/include/configs/ml401.h index a6026528b30..8b74b7c686d 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -87,7 +87,7 @@ * 0x11FB_F000 CFG_MONITOR_BASE * MONITOR_CODE 256kB Env * 0x13FF_F000 CFG_GBL_DATA_OFFSET - * GLOBAL_DATA 4kB bd, gd + * GLOBAL_DATA 4kB bd, gd * 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE */ @@ -100,7 +100,7 @@ /* global pointer */ #define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */ /* start of global data */ -#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) +#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* monitor code */ #define SIZE 0x40000 @@ -243,10 +243,10 @@ #define CONFIG_BOOTDELAY 30 #define CONFIG_BOOTARGS "root=romfs" #define CONFIG_HOSTNAME "ml401" -#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" +#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" #define CONFIG_IPADDR 192.168.0.3 -#define CONFIG_SERVERIP 192.168.0.5 -#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.5 +#define CONFIG_GATEWAYIP 192.168.0.1 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD /* architecture dependent code */ -- cgit v1.3.1 From 706714d97a0d08d59eda4de2268c39f504688329 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 6 Aug 2007 23:41:53 +0200 Subject: [FIX] remove cute code --- drivers/net/xilinx_emac.c | 233 ++++++++++++++++++------------------- drivers/net/xilinx_emac.h | 121 ++++++++++++-------- drivers/net/xilinx_emaclite.c | 260 +++++++++++++++++++++--------------------- 3 files changed, 318 insertions(+), 296 deletions(-) (limited to 'drivers') diff --git a/drivers/net/xilinx_emac.c b/drivers/net/xilinx_emac.c index d44f31e8aff..23567cc40a0 100644 --- a/drivers/net/xilinx_emac.c +++ b/drivers/net/xilinx_emac.c @@ -41,76 +41,78 @@ static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ -static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; +static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; -static XEmac Emac; +static xemac emac; void eth_halt(void) { - return; +#ifdef DEBUG + puts ("eth_halt\n"); +#endif } int eth_init(bd_t * bis) { - u32 HelpReg; + u32 helpreg; #ifdef DEBUG printf("EMAC Initialization Started\n\r"); #endif - if (Emac.IsStarted) { + if (emac.isstarted) { puts("Emac is started\n"); return 0; } - memset (&Emac, 0, sizeof (XEmac)); + memset (&emac, 0, sizeof (xemac)); - Emac.BaseAddress = XILINX_EMAC_BASEADDR; + emac.baseaddress = XILINX_EMAC_BASEADDR; /* Setting up FIFOs */ - Emac.RecvFifo.RegBaseAddress = Emac.BaseAddress + + emac.recvfifo.regbaseaddress = emac.baseaddress + XEM_PFIFO_RXREG_OFFSET; - Emac.RecvFifo.DataBaseAddress = Emac.BaseAddress + + emac.recvfifo.databaseaddress = emac.baseaddress + XEM_PFIFO_RXDATA_OFFSET; - out_be32 (Emac.RecvFifo.RegBaseAddress, XPF_RESET_FIFO_MASK); + out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK); - Emac.SendFifo.RegBaseAddress = Emac.BaseAddress + + emac.sendfifo.regbaseaddress = emac.baseaddress + XEM_PFIFO_TXREG_OFFSET; - Emac.SendFifo.DataBaseAddress = Emac.BaseAddress + + emac.sendfifo.databaseaddress = emac.baseaddress + XEM_PFIFO_TXDATA_OFFSET; - out_be32 (Emac.SendFifo.RegBaseAddress, XPF_RESET_FIFO_MASK); + out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK); /* Reset the entire IPIF */ - out_be32 (Emac.BaseAddress + XIIF_V123B_RESETR_OFFSET, + out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET, XIIF_V123B_RESET_MASK); /* Stopping EMAC for setting up MAC */ - HelpReg = in_be32 (Emac.BaseAddress + XEM_ECR_OFFSET); - HelpReg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); - out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg); + helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET); + helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); + out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); if (!getenv("ethaddr")) { - memcpy(bis->bi_enetaddr, EMACAddr, ENET_ADDR_LENGTH); + memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH); } /* Set the device station address high and low registers */ - HelpReg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1]; - out_be32 (Emac.BaseAddress + XEM_SAH_OFFSET, HelpReg); - HelpReg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) | + helpreg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1]; + out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg); + helpreg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) | (bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5]; - out_be32 (Emac.BaseAddress + XEM_SAL_OFFSET, HelpReg); + out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg); - HelpReg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK | + helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK | XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK | XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK; - out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg); + out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); - Emac.IsStarted = 1; + emac.isstarted = 1; /* Enable the transmitter, and receiver */ - HelpReg = in_be32 (Emac.BaseAddress + XEM_ECR_OFFSET); - HelpReg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); - HelpReg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); - out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg); + helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET); + helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); + helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); + out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); printf("EMAC Initialization complete\n\r"); return 0; @@ -118,12 +120,12 @@ int eth_init(bd_t * bis) int eth_send(volatile void *ptr, int len) { - u32 IntrStatus; - u32 XmitStatus; - u32 FifoCount; - u32 WordCount; - u32 ExtraByteCount; - u32 *WordBuffer = (u32 *) ptr; + u32 intrstatus; + u32 xmitstatus; + u32 fifocount; + u32 wordcount; + u32 extrabytecount; + u32 *wordbuffer = (u32 *) ptr; if (len > ENET_MAX_MTU) len = ENET_MAX_MTU; @@ -135,20 +137,20 @@ int eth_send(volatile void *ptr, int len) * continue. The upper layer software should reset the device to resolve * the error. */ - IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET); - if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | + intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); + if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | XEM_EIR_XMIT_LFIFO_OVER_MASK)) { #ifdef DEBUG puts ("Transmitting overrun error\n"); #endif return 0; - } else if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | + } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { #ifdef DEBUG puts ("Transmitting underrun error\n"); #endif return 0; - } else if (in_be32 (Emac.SendFifo.RegBaseAddress + + } else if (in_be32 (emac.sendfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) { #ifdef DEBUG puts("Transmitting fifo error\n"); @@ -165,9 +167,9 @@ int eth_send(volatile void *ptr, int len) * Clear the latched LFIFO_FULL bit so next time around the most * current status is represented */ - if (IntrStatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) { - out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, IntrStatus - & XEM_EIR_XMIT_LFIFO_FULL_MASK); + if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) { + out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, + intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK); #ifdef DEBUG puts ("Fifo is full\n"); #endif @@ -175,72 +177,72 @@ int eth_send(volatile void *ptr, int len) } /* get the count of how many words may be inserted into the FIFO */ - FifoCount = in_be32 (Emac.SendFifo.RegBaseAddress + + fifocount = in_be32 (emac.sendfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; - WordCount = len >> 2; - ExtraByteCount = len & 0x3; + wordcount = len >> 2; + extrabytecount = len & 0x3; - if (FifoCount < WordCount) { + if (fifocount < wordcount) { #ifdef DEBUG puts ("Sending packet is larger then size of FIFO\n"); #endif return 0; } - for (FifoCount = 0; FifoCount < WordCount; FifoCount++) { - out_be32 (Emac.SendFifo.DataBaseAddress, WordBuffer[FifoCount]); + for (fifocount = 0; fifocount < wordcount; fifocount++) { + out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]); } - if (ExtraByteCount > 0) { - u32 LastWord = 0; - u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount); - - if (ExtraByteCount == 1) { - LastWord = ExtraBytesBuffer[0] << 24; - } else if (ExtraByteCount == 2) { - LastWord = ExtraBytesBuffer[0] << 24 | - ExtraBytesBuffer[1] << 16; - } else if (ExtraByteCount == 3) { - LastWord = ExtraBytesBuffer[0] << 24 | - ExtraBytesBuffer[1] << 16 | - ExtraBytesBuffer[2] << 8; + if (extrabytecount > 0) { + u32 lastword = 0; + u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount); + + if (extrabytecount == 1) { + lastword = extrabytesbuffer[0] << 24; + } else if (extrabytecount == 2) { + lastword = extrabytesbuffer[0] << 24 | + extrabytesbuffer[1] << 16; + } else if (extrabytecount == 3) { + lastword = extrabytesbuffer[0] << 24 | + extrabytesbuffer[1] << 16 | + extrabytesbuffer[2] << 8; } - out_be32 (Emac.SendFifo.DataBaseAddress, LastWord); + out_be32 (emac.sendfifo.databaseaddress, lastword); } /* Loop on the MAC's status to wait for any pause to complete */ - IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET); - while ((IntrStatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) { - IntrStatus = in_be32 ((Emac.BaseAddress) + + intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); + while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) { + intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); /* Clear the pause status from the transmit status register */ - out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, - IntrStatus & XEM_EIR_XMIT_PAUSE_MASK); + out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, + intrstatus & XEM_EIR_XMIT_PAUSE_MASK); } /* * Set the MAC's transmit packet length register to tell it to transmit */ - out_be32 (Emac.BaseAddress + XEM_TPLR_OFFSET, len); + out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len); /* * Loop on the MAC's status to wait for the transmit to complete. * The transmit status is in the FIFO when the XMIT_DONE bit is set. */ do { - IntrStatus = in_be32 ((Emac.BaseAddress) + + intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); } - while ((IntrStatus & XEM_EIR_XMIT_DONE_MASK) == 0); + while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0); - XmitStatus = in_be32 (Emac.BaseAddress + XEM_TSR_OFFSET); + xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET); - if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | + if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | XEM_EIR_XMIT_LFIFO_OVER_MASK)) { #ifdef DEBUG puts ("Transmitting overrun error\n"); #endif return 0; - } else if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | + } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { #ifdef DEBUG puts ("Transmitting underrun error\n"); @@ -249,15 +251,15 @@ int eth_send(volatile void *ptr, int len) } /* Clear the interrupt status register of transmit statuses */ - out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, - IntrStatus & XEM_EIR_XMIT_ALL_MASK); + out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, + intrstatus & XEM_EIR_XMIT_ALL_MASK); /* * Collision errors are stored in the transmit status register * instead of the interrupt status register */ - if ((XmitStatus & XEM_TSR_EXCESS_DEFERRAL_MASK) || - (XmitStatus & XEM_TSR_LATE_COLLISION_MASK)) { + if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) || + (xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) { #ifdef DEBUG puts ("Transmitting collision error\n"); #endif @@ -268,17 +270,17 @@ int eth_send(volatile void *ptr, int len) int eth_rx(void) { - u32 PktLength; - u32 IntrStatus; - u32 FifoCount; - u32 WordCount; - u32 ExtraByteCount; - u32 LastWord; - u8 *ExtraBytesBuffer; - - if (in_be32 (Emac.RecvFifo.RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) + u32 pktlength; + u32 intrstatus; + u32 fifocount; + u32 wordcount; + u32 extrabytecount; + u32 lastword; + u8 *extrabytesbuffer; + + if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) { - out_be32 (Emac.RecvFifo.RegBaseAddress, XPF_RESET_FIFO_MASK); + out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK); #ifdef DEBUG puts ("Receiving FIFO deadlock\n"); #endif @@ -286,17 +288,18 @@ int eth_rx(void) } /* - * Get the interrupt status to know what happened (whether an error occurred - * and/or whether frames have been received successfully). When clearing the - * intr status register, clear only statuses that pertain to receive. + * Get the interrupt status to know what happened (whether an error + * occurred and/or whether frames have been received successfully). + * When clearing the intr status register, clear only statuses that + * pertain to receive. */ - IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET); + intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); /* * Before reading from the length FIFO, make sure the length FIFO is not * empty. We could cause an underrun error if we try to read from an * empty FIFO. */ - if (!(IntrStatus & XEM_EIR_RECV_DONE_MASK)) { + if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) { #ifdef DEBUG /* puts("Receiving FIFO is empty\n"); */ #endif @@ -307,8 +310,8 @@ int eth_rx(void) * Determine, from the MAC, the length of the next packet available * in the data FIFO (there should be a non-zero length here) */ - PktLength = in_be32 (Emac.BaseAddress + XEM_RPLR_OFFSET); - if (!PktLength) { + pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET); + if (!pktlength) { return 0; } @@ -320,53 +323,53 @@ int eth_rx(void) * in the IPIF, which means it may indicate a non-empty condition even * though there is something in the FIFO. */ - out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, + out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, XEM_EIR_RECV_DONE_MASK); - FifoCount = in_be32 (Emac.RecvFifo.RegBaseAddress + + fifocount = in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; - if ((FifoCount * 4) < PktLength) { + if ((fifocount * 4) < pktlength) { #ifdef DEBUG puts ("Receiving FIFO is smaller than packet size.\n"); #endif return 0; } - WordCount = PktLength >> 2; - ExtraByteCount = PktLength & 0x3; + wordcount = pktlength >> 2; + extrabytecount = pktlength & 0x3; - for (FifoCount = 0; FifoCount < WordCount; FifoCount++) { - etherrxbuff[FifoCount] = - in_be32 (Emac.RecvFifo.DataBaseAddress); + for (fifocount = 0; fifocount < wordcount; fifocount++) { + etherrxbuff[fifocount] = + in_be32 (emac.recvfifo.databaseaddress); } /* * if there are extra bytes to handle, read the last word from the FIFO * and insert the extra bytes into the buffer */ - if (ExtraByteCount > 0) { - ExtraBytesBuffer = (u8 *) (etherrxbuff + WordCount); + if (extrabytecount > 0) { + extrabytesbuffer = (u8 *) (etherrxbuff + wordcount); - LastWord = in_be32 (Emac.RecvFifo.DataBaseAddress); + lastword = in_be32 (emac.recvfifo.databaseaddress); /* * one extra byte in the last word, put the byte into the next * location of the buffer, bytes in a word of the FIFO are * ordered from most significant byte to least */ - if (ExtraByteCount == 1) { - ExtraBytesBuffer[0] = (u8) (LastWord >> 24); - } else if (ExtraByteCount == 2) { - ExtraBytesBuffer[0] = (u8) (LastWord >> 24); - ExtraBytesBuffer[1] = (u8) (LastWord >> 16); - } else if (ExtraByteCount == 3) { - ExtraBytesBuffer[0] = (u8) (LastWord >> 24); - ExtraBytesBuffer[1] = (u8) (LastWord >> 16); - ExtraBytesBuffer[2] = (u8) (LastWord >> 8); + if (extrabytecount == 1) { + extrabytesbuffer[0] = (u8) (lastword >> 24); + } else if (extrabytecount == 2) { + extrabytesbuffer[0] = (u8) (lastword >> 24); + extrabytesbuffer[1] = (u8) (lastword >> 16); + } else if (extrabytecount == 3) { + extrabytesbuffer[0] = (u8) (lastword >> 24); + extrabytesbuffer[1] = (u8) (lastword >> 16); + extrabytesbuffer[2] = (u8) (lastword >> 8); } } - NetReceive((uchar *)etherrxbuff, PktLength); + NetReceive((uchar *)etherrxbuff, pktlength); return 1; } #endif diff --git a/drivers/net/xilinx_emac.h b/drivers/net/xilinx_emac.h index 7c00eebf048..966598e27a5 100644 --- a/drivers/net/xilinx_emac.h +++ b/drivers/net/xilinx_emac.h @@ -26,16 +26,16 @@ */ typedef struct { - u32 RegBaseAddress; /* Base address of registers */ - u32 DataBaseAddress; /* Base address of data for FIFOs */ -} XPacketFifoV100b; + u32 regbaseaddress; /* Base address of registers */ + u32 databaseaddress; /* Base address of data for FIFOs */ +} xpacketfifov100b; typedef struct { - u32 BaseAddress; /* Base address (of IPIF) */ - u32 IsStarted; /* Device is currently started 0-no, 1-yes */ - XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */ - XPacketFifoV100b SendFifo; /* FIFO used to send frames */ -} XEmac; + u32 baseaddress; /* Base address (of IPIF) */ + u32 isstarted; /* Device is currently started 0-no, 1-yes */ + xpacketfifov100b recvfifo; /* FIFO used to receive frames */ + xpacketfifov100b sendfifo; /* FIFO used to send frames */ +} xemac; #define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ #define XIIF_V123B_RESET_MASK 0xAUL @@ -66,10 +66,14 @@ typedef struct { #define XEM_PFIFO_OFFSET 0x2000UL -#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) /* Tx registers */ -#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) /* Rx registers */ -#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) /* Tx keyhole */ -#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) /* Rx keyhole */ +/* Tx registers */ +#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) +/* Rx registers */ +#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) +/* Tx keyhole */ +#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) +/* Rx keyhole */ +#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) /* @@ -82,46 +86,63 @@ typedef struct { XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\ XEM_EIR_XMIT_LFIFO_FULL_MASK) -#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */ -#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */ -#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */ -#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */ -#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */ -#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */ -#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */ -#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo - * overrun */ -#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo - * underrun */ -#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo - * overrun */ -#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo - * underrun */ -#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo - * overrun */ -#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo - * underrun */ -#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt - * received */ +/* Xmit complete */ +#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL +/* Recv complete */ +#define XEM_EIR_RECV_DONE_MASK 0x00000002UL +/* Xmit error */ +#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL +/* Recv error */ +#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL +/* Xmit status fifo empty */ +#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL +/* Recv length fifo empty */ +#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL +/* Xmit length fifo full */ +#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL +/* Recv length fifo overrun */ +#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL +/* Recv length fifo underrun */ +#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL +/* Xmit status fifo overrun */ +#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL +/* Transmit status fifo underrun */ +#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL +/* Transmit length fifo overrun */ +#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL +/* Transmit length fifo underrun */ +#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL +/* Transmit pause pkt received */ +#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* * EMAC Control Register (ECR) */ -#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL /* Full duplex mode */ -#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL /* Reset transmitter */ -#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL /* Enable transmitter */ -#define XEM_ECR_RECV_RESET_MASK 0x10000000UL /* Reset receiver */ -#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL /* Enable receiver */ -#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL /* Enable PHY */ -#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL /* Enable xmit pad - * insert */ -#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL /* Enable xmit FCS - * insert */ -#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL /* Enable unicast - * addr */ -#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL /* Enable broadcast - * addr */ +/* Full duplex mode */ +#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL +/* Reset transmitter */ +#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL +/* Enable transmitter */ +#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL +/* Reset receiver */ +#define XEM_ECR_RECV_RESET_MASK 0x10000000UL +/* Enable receiver */ +#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL +/* Enable PHY */ +#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL +/* Enable xmit pad insert */ +#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL +/* Enable xmit FCS insert */ +#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL +/* Enable unicast addr */ +#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL +/* Enable broadcast addr */ +#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL -/* Transmit Status Register (TSR) */ -#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */ -#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */ +/* + * Transmit Status Register (TSR) + */ +/* Transmit excess deferral */ +#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL +/* Transmit late collision */ +#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 99e70354b61..5d8eaa51823 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -64,76 +64,73 @@ #define XEL_RSR_RECV_IE_MASK 0x00000008UL typedef struct { - unsigned int BaseAddress; /* Base address for device (IPIF) */ - unsigned int NextTxBufferToUse; /* Next TX buffer to write to */ - unsigned int NextRxBufferToUse; /* Next RX buffer to read from */ - unsigned char DeviceId; /* Unique ID of device - for future */ -} XEmacLite; + unsigned int baseaddress; /* Base address for device (IPIF) */ + unsigned int nexttxbuffertouse; /* Next TX buffer to write to */ + unsigned int nextrxbuffertouse; /* Next RX buffer to read from */ + unsigned char deviceid; /* Unique ID of device - for future */ +} xemaclite; -static XEmacLite EmacLite; +static xemaclite emaclite; -static char etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ +static char etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ /* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/ #ifdef CFG_ENV_IS_NOWHERE -static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; +static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; #endif -void XEmacLite_AlignedRead (u32 * SrcPtr, void *DestPtr, unsigned ByteCount) +void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount) { - unsigned i; - unsigned Length = ByteCount; - u32 AlignBuffer; - u32 *To32Ptr; - u32 *From32Ptr; - u8 *To8Ptr; - u8 *From8Ptr; + unsigned int i; + u32 alignbuffer; + u32 *to32ptr; + u32 *from32ptr; + u8 *to8ptr; + u8 *from8ptr; - From32Ptr = (u32 *) SrcPtr; + from32ptr = (u32 *) srcptr; /* Word aligned buffer, no correction needed. */ - To32Ptr = (u32 *) DestPtr; - while (Length > 3) { - *To32Ptr++ = *From32Ptr++; - Length -= 4; + to32ptr = (u32 *) destptr; + while (bytecount > 3) { + *to32ptr++ = *from32ptr++; + bytecount -= 4; } - To8Ptr = (u8 *) To32Ptr; + to8ptr = (u8 *) to32ptr; - AlignBuffer = *From32Ptr++; - From8Ptr = (u8 *) & AlignBuffer; + alignbuffer = *from32ptr++; + from8ptr = (u8 *) & alignbuffer; - for (i = 0; i < Length; i++) { - *To8Ptr++ = *From8Ptr++; + for (i = 0; i < bytecount; i++) { + *to8ptr++ = *from8ptr++; } } -void XEmacLite_AlignedWrite (void *SrcPtr, u32 * DestPtr, unsigned ByteCount) +void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount) { unsigned i; - unsigned Length = ByteCount; - u32 AlignBuffer; - u32 *To32Ptr; - u32 *From32Ptr; - u8 *To8Ptr; - u8 *From8Ptr; - To32Ptr = DestPtr; - - From32Ptr = (u32 *) SrcPtr; - while (Length > 3) { - - *To32Ptr++ = *From32Ptr++; - Length -= 4; + u32 alignbuffer; + u32 *to32ptr = (u32 *) destptr; + u32 *from32ptr; + u8 *to8ptr; + u8 *from8ptr; + + from32ptr = (u32 *) srcptr; + while (bytecount > 3) { + + *to32ptr++ = *from32ptr++; + bytecount -= 4; } - AlignBuffer = 0; - To8Ptr = (u8 *) & AlignBuffer; - From8Ptr = (u8 *) From32Ptr; + alignbuffer = 0; + to8ptr = (u8 *) & alignbuffer; + from8ptr = (u8 *) from32ptr; - for (i = 0; i < Length; i++) { - *To8Ptr++ = *From8Ptr++; + for (i = 0; i < bytecount; i++) { + *to8ptr++ = *from8ptr++; } - *To32Ptr++ = AlignBuffer; + *to32ptr++ = alignbuffer; } void eth_halt (void) @@ -148,37 +145,38 @@ int eth_init (bd_t * bis) #ifdef DEBUG puts ("EmacLite Initialization Started\n"); #endif - memset (&EmacLite, 0, sizeof (XEmacLite)); - EmacLite.BaseAddress = XILINX_EMACLITE_BASEADDR; + memset (&emaclite, 0, sizeof (xemaclite)); + emaclite.baseaddress = XILINX_EMACLITE_BASEADDR; + + if (!getenv("ethaddr")) { + memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH); + } -#ifdef CFG_ENV_IS_NOWHERE - memcpy (bis->bi_enetaddr, EMACAddr, ENET_ADDR_LENGTH); -#endif /* * TX - TX_PING & TX_PONG initialization */ /* Restart PING TX */ - out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, 0); + out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0); /* Copy MAC address */ - XEmacLite_AlignedWrite (bis->bi_enetaddr, - EmacLite.BaseAddress, ENET_ADDR_LENGTH); + xemaclite_alignedwrite (bis->bi_enetaddr, + emaclite.baseaddress, ENET_ADDR_LENGTH); /* Set the length */ - out_be32 (EmacLite.BaseAddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); /* Update the MAC address in the EMAC Lite */ - out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); + out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); /* Wait for EMAC Lite to finish with the MAC address update */ - while ((in_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET) & + while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ; #ifdef XILINX_EMACLITE_TX_PING_PONG /* The same operation with PONG TX */ - out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); - XEmacLite_AlignedWrite (bis->bi_enetaddr, - EmacLite.BaseAddress + XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); - out_be32 (EmacLite.BaseAddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); - out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, + out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); + xemaclite_alignedwrite (bis->bi_enetaddr, emaclite.baseaddress + + XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); + out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, XEL_TSR_PROG_MAC_ADDR); - while ((in_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + + while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ; #endif @@ -186,9 +184,9 @@ int eth_init (bd_t * bis) * RX - RX_PING & RX_PONG initialization */ /* Write out the value to flush the RX buffer */ - out_be32 (EmacLite.BaseAddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); + out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); #ifdef XILINX_EMACLITE_RX_PING_PONG - out_be32 (EmacLite.BaseAddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, + out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, XEL_RSR_RECV_IE_MASK); #endif @@ -198,39 +196,39 @@ int eth_init (bd_t * bis) return 0; } -int XEmacLite_TxBufferAvailable (XEmacLite * InstancePtr) +int xemaclite_txbufferavailable (xemaclite * instanceptr) { - u32 Register; - u32 TxPingBusy; - u32 TxPongBusy; + u32 reg; + u32 txpingbusy; + u32 txpongbusy; /* * Read the other buffer register * and determine if the other buffer is available */ - Register = in_be32 (InstancePtr->BaseAddress + - InstancePtr->NextTxBufferToUse + 0); - TxPingBusy = ((Register & XEL_TSR_XMIT_BUSY_MASK) == + reg = in_be32 (instanceptr->baseaddress + + instanceptr->nexttxbuffertouse + 0); + txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == XEL_TSR_XMIT_BUSY_MASK); - Register = in_be32 (InstancePtr->BaseAddress + - (InstancePtr->NextTxBufferToUse ^ XEL_TSR_OFFSET) + 0); - TxPongBusy = ((Register & XEL_TSR_XMIT_BUSY_MASK) == + reg = in_be32 (instanceptr->baseaddress + + (instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0); + txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == XEL_TSR_XMIT_BUSY_MASK); - return (!(TxPingBusy && TxPongBusy)); + return (!(txpingbusy && txpongbusy)); } int eth_send (volatile void *ptr, int len) { - unsigned int Register; - unsigned int BaseAddress; + unsigned int reg; + unsigned int baseaddress; unsigned maxtry = 1000; if (len > ENET_MAX_MTU) len = ENET_MAX_MTU; - while (!XEmacLite_TxBufferAvailable (&EmacLite) && maxtry) { + while (!xemaclite_txbufferavailable (&emaclite) && maxtry) { udelay (10); maxtry--; } @@ -238,62 +236,62 @@ int eth_send (volatile void *ptr, int len) { if (!maxtry) { printf ("Error: Timeout waiting for ethernet TX buffer\n"); /* Restart PING TX */ - out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, 0); + out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0); #ifdef XILINX_EMACLITE_TX_PING_PONG - out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + + out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); #endif return 0; } /* Determine the expected TX buffer address */ - BaseAddress = (EmacLite.BaseAddress + EmacLite.NextTxBufferToUse); + baseaddress = (emaclite.baseaddress + emaclite.nexttxbuffertouse); /* Determine if the expected buffer address is empty */ - Register = in_be32 (BaseAddress + XEL_TSR_OFFSET); - if (((Register & XEL_TSR_XMIT_BUSY_MASK) == 0) - && ((in_be32 ((BaseAddress) + XEL_TSR_OFFSET) + reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) + && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { #ifdef XILINX_EMACLITE_TX_PING_PONG - EmacLite.NextTxBufferToUse ^= XEL_BUFFER_OFFSET; + emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET; #endif #ifdef DEBUG - printf ("Send packet from 0x%x\n", BaseAddress); + printf ("Send packet from 0x%x\n", baseaddress); #endif /* Write the frame to the buffer */ - XEmacLite_AlignedWrite (ptr, (u32 *) BaseAddress, len); - out_be32 (BaseAddress + XEL_TPLR_OFFSET,(len & + xemaclite_alignedwrite ((void *) ptr, baseaddress, len); + out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); - Register = in_be32 (BaseAddress + XEL_TSR_OFFSET); - Register |= XEL_TSR_XMIT_BUSY_MASK; - if ((Register & XEL_TSR_XMIT_IE_MASK) != 0) { - Register |= XEL_TSR_XMIT_ACTIVE_MASK; + reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + reg |= XEL_TSR_XMIT_BUSY_MASK; + if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) { + reg |= XEL_TSR_XMIT_ACTIVE_MASK; } - out_be32 (BaseAddress + XEL_TSR_OFFSET, Register); + out_be32 (baseaddress + XEL_TSR_OFFSET, reg); return 1; } #ifdef XILINX_EMACLITE_TX_PING_PONG /* Switch to second buffer */ - BaseAddress ^= XEL_BUFFER_OFFSET; + baseaddress ^= XEL_BUFFER_OFFSET; /* Determine if the expected buffer address is empty */ - Register = in_be32 (BaseAddress + XEL_TSR_OFFSET); - if (((Register & XEL_TSR_XMIT_BUSY_MASK) == 0) - && ((in_be32 ((BaseAddress) + XEL_TSR_OFFSET) + reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) + && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { #ifdef DEBUG - printf ("Send packet from 0x%x\n", BaseAddress); + printf ("Send packet from 0x%x\n", baseaddress); #endif /* Write the frame to the buffer */ - XEmacLite_AlignedWrite (ptr, (u32 *) BaseAddress, len); - out_be32 (BaseAddress + XEL_TPLR_OFFSET,(len & + xemaclite_alignedwrite ((void *) ptr, baseaddress, len); + out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); - Register = in_be32 (BaseAddress + XEL_TSR_OFFSET); - Register |= XEL_TSR_XMIT_BUSY_MASK; - if ((Register & XEL_TSR_XMIT_IE_MASK) != 0) { - Register |= XEL_TSR_XMIT_ACTIVE_MASK; + reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + reg |= XEL_TSR_XMIT_BUSY_MASK; + if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) { + reg |= XEL_TSR_XMIT_ACTIVE_MASK; } - out_be32 (BaseAddress + XEL_TSR_OFFSET, Register); + out_be32 (baseaddress + XEL_TSR_OFFSET, reg); return 1; } #endif @@ -303,50 +301,50 @@ int eth_send (volatile void *ptr, int len) { int eth_rx (void) { - unsigned int Length; - unsigned int Register; - unsigned int BaseAddress; + unsigned int length; + unsigned int reg; + unsigned int baseaddress; - BaseAddress = EmacLite.BaseAddress + EmacLite.NextRxBufferToUse; - Register = in_be32 (BaseAddress + XEL_RSR_OFFSET); + baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse; + reg = in_be32 (baseaddress + XEL_RSR_OFFSET); #ifdef DEBUG - printf ("Testing data at address 0x%x\n", BaseAddress); + printf ("Testing data at address 0x%x\n", baseaddress); #endif - if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { + if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { #ifdef XILINX_EMACLITE_RX_PING_PONG - EmacLite.NextRxBufferToUse ^= XEL_BUFFER_OFFSET; + emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET; #endif } else { #ifndef XILINX_EMACLITE_RX_PING_PONG #ifdef DEBUG - printf ("No data was available - address 0x%x\n", BaseAddress); + printf ("No data was available - address 0x%x\n", baseaddress); #endif return 0; #else - BaseAddress ^= XEL_BUFFER_OFFSET; - Register = in_be32 (BaseAddress + XEL_RSR_OFFSET); - if ((Register & XEL_RSR_RECV_DONE_MASK) != + baseaddress ^= XEL_BUFFER_OFFSET; + reg = in_be32 (baseaddress + XEL_RSR_OFFSET); + if ((reg & XEL_RSR_RECV_DONE_MASK) != XEL_RSR_RECV_DONE_MASK) { #ifdef DEBUG printf ("No data was available - address 0x%x\n", - BaseAddress); + baseaddress); #endif return 0; } #endif } /* Get the length of the frame that arrived */ - switch(((in_be32(BaseAddress + XEL_RXBUFF_OFFSET + 0xC)) & + switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) & 0xFFFF0000 ) >> 16) { case 0x806: - Length = 42 + 20; /* FIXME size of ARP */ + length = 42 + 20; /* FIXME size of ARP */ #ifdef DEBUG puts ("ARP Packet\n"); #endif break; case 0x800: - Length = 14 + 14 + - (((in_be32(BaseAddress + XEL_RXBUFF_OFFSET + 0x10)) & + length = 14 + 14 + + (((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) & 0xFFFF0000) >> 16); /* FIXME size of IP packet */ #ifdef DEBUG puts("IP Packet\n"); @@ -356,22 +354,22 @@ int eth_rx (void) #ifdef DEBUG puts("Other Packet\n"); #endif - Length = ENET_MAX_MTU; + length = ENET_MAX_MTU; break; } - XEmacLite_AlignedRead ((BaseAddress + XEL_RXBUFF_OFFSET), - etherrxbuff, Length); + xemaclite_alignedread ((u32 *) (baseaddress + XEL_RXBUFF_OFFSET), + etherrxbuff, length); /* Acknowledge the frame */ - Register = in_be32 (BaseAddress + XEL_RSR_OFFSET); - Register &= ~XEL_RSR_RECV_DONE_MASK; - out_be32 (BaseAddress + XEL_RSR_OFFSET, Register); + reg = in_be32 (baseaddress + XEL_RSR_OFFSET); + reg &= ~XEL_RSR_RECV_DONE_MASK; + out_be32 (baseaddress + XEL_RSR_OFFSET, reg); #ifdef DEBUG - printf ("Packet receive from 0x%x, length %dB\n", BaseAddress, Length); + printf ("Packet receive from 0x%x, length %dB\n", baseaddress, length); #endif - NetReceive ((uchar *) etherrxbuff, Length); + NetReceive ((uchar *) etherrxbuff, length); return 1; } -- cgit v1.3.1 From 5b4de9309d7a03aa1db2e5391ab696363391f460 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 15 Aug 2007 21:15:05 +0200 Subject: [FIX] Resolve problem with warnings microblaze toolchain don't support PRAGMA PACK. --- drivers/bios_emulator/besys.c | 3 ++- drivers/bios_emulator/bios.c | 3 ++- drivers/bios_emulator/biosemu.c | 3 ++- drivers/bios_emulator/x86emu/debug.c | 3 ++- drivers/bios_emulator/x86emu/decode.c | 4 ++-- drivers/bios_emulator/x86emu/ops.c | 4 ++-- drivers/bios_emulator/x86emu/ops2.c | 4 ++-- drivers/bios_emulator/x86emu/prim_ops.c | 3 ++- drivers/bios_emulator/x86emu/sys.c | 4 ++-- 9 files changed, 18 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c index 4c4bc8d7ba1..5751eeb2185 100644 --- a/drivers/bios_emulator/besys.c +++ b/drivers/bios_emulator/besys.c @@ -47,9 +47,10 @@ * ****************************************************************************/ +#if defined(CONFIG_BIOSEMU) + #include "biosemui.h" -#if defined(CONFIG_BIOSEMU) /*------------------------- Global Variables ------------------------------*/ #ifndef __i386__ diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c index 7aa1bfb2eb6..d9ccbf8cd04 100644 --- a/drivers/bios_emulator/bios.c +++ b/drivers/bios_emulator/bios.c @@ -41,9 +41,10 @@ * ****************************************************************************/ +#if defined(CONFIG_BIOSEMU) + #include "biosemui.h" -#if defined(CONFIG_BIOSEMU) /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c index 4c3aedf4130..5ab9e74c38c 100644 --- a/drivers/bios_emulator/biosemu.c +++ b/drivers/bios_emulator/biosemu.c @@ -45,11 +45,12 @@ * ****************************************************************************/ -#include "biosemui.h" #include #if defined(CONFIG_BIOSEMU) +#include "biosemui.h" + BE_sysEnv _BE_env = {{0}}; static X86EMU_memFuncs _BE_mem __attribute__((section(".got2"))) = { BE_rdb, diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index 915739c5b03..3acc7e5008b 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -37,11 +37,12 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" #include #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*----------------------------- Implementation ----------------------------*/ #ifdef DEBUG diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c index 879f0a06d17..915645c0835 100644 --- a/drivers/bios_emulator/x86emu/decode.c +++ b/drivers/bios_emulator/x86emu/decode.c @@ -37,10 +37,10 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" - #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index d334fb5b1cf..ff2f11963c7 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -75,10 +75,10 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" - #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*----------------------------- Implementation ----------------------------*/ /* constant arrays to do several instructions in just one function */ diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index 81c0d49a333..c8b85171928 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -44,10 +44,10 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" - #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*----------------------------- Implementation ----------------------------*/ /**************************************************************************** diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c index c1152eae341..b3d82bb0524 100644 --- a/drivers/bios_emulator/x86emu/prim_ops.c +++ b/drivers/bios_emulator/x86emu/prim_ops.c @@ -98,10 +98,11 @@ ****************************************************************************/ #define PRIM_OPS_NO_REDEFINE_ASM -#include "x86emu/x86emui.h" #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*------------------------- Global Variables ------------------------------*/ static u32 x86emu_parity_tab[8] = diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c index 566389f5862..6324cd34390 100644 --- a/drivers/bios_emulator/x86emu/sys.c +++ b/drivers/bios_emulator/x86emu/sys.c @@ -39,10 +39,10 @@ * ****************************************************************************/ -#include "x86emu/x86emui.h" - #if defined(CONFIG_BIOSEMU) +#include "x86emu/x86emui.h" + /*------------------------- Global Variables ------------------------------*/ X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ -- cgit v1.3.1 From 6e0e2253f039344f8ebd2787285fdba90e6714e8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 16 Aug 2007 10:45:09 +0200 Subject: [FIX] Remove unused include file --- drivers/net/xilinx_emac.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/xilinx_emac.c b/drivers/net/xilinx_emac.c index 23567cc40a0..36e627aae52 100644 --- a/drivers/net/xilinx_emac.c +++ b/drivers/net/xilinx_emac.c @@ -29,7 +29,6 @@ #include #include #include -#include #include "xilinx_emac.h" #ifdef XILINX_EMAC -- cgit v1.3.1 From 78cff50edba6b1508eb15c2f53ce966ac891eb9e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 16 Aug 2007 10:46:28 +0200 Subject: [FIX] Changes for bios_emulator code for others architecture --- drivers/bios_emulator/besys.c | 2 ++ drivers/bios_emulator/bios.c | 2 ++ drivers/bios_emulator/biosemu.c | 1 + drivers/bios_emulator/x86emu/debug.c | 1 + drivers/bios_emulator/x86emu/decode.c | 1 + drivers/bios_emulator/x86emu/ops.c | 2 ++ drivers/bios_emulator/x86emu/ops2.c | 2 ++ drivers/bios_emulator/x86emu/prim_ops.c | 2 ++ drivers/bios_emulator/x86emu/sys.c | 2 ++ 9 files changed, 15 insertions(+) (limited to 'drivers') diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c index 5751eeb2185..8f1d8b29d59 100644 --- a/drivers/bios_emulator/besys.c +++ b/drivers/bios_emulator/besys.c @@ -47,6 +47,8 @@ * ****************************************************************************/ +#include + #if defined(CONFIG_BIOSEMU) #include "biosemui.h" diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c index d9ccbf8cd04..70e9ce143b4 100644 --- a/drivers/bios_emulator/bios.c +++ b/drivers/bios_emulator/bios.c @@ -41,6 +41,8 @@ * ****************************************************************************/ +#include + #if defined(CONFIG_BIOSEMU) #include "biosemui.h" diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c index 5ab9e74c38c..ccfc872f788 100644 --- a/drivers/bios_emulator/biosemu.c +++ b/drivers/bios_emulator/biosemu.c @@ -46,6 +46,7 @@ ****************************************************************************/ #include +#include #if defined(CONFIG_BIOSEMU) diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index 3acc7e5008b..5cbcc950183 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -38,6 +38,7 @@ ****************************************************************************/ #include +#include #if defined(CONFIG_BIOSEMU) diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c index 915645c0835..7a9a1ddbff9 100644 --- a/drivers/bios_emulator/x86emu/decode.c +++ b/drivers/bios_emulator/x86emu/decode.c @@ -36,6 +36,7 @@ * instruction decoding and accessess of immediate data via IP. etc. * ****************************************************************************/ +#include #if defined(CONFIG_BIOSEMU) diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index ff2f11963c7..a77bd9b4924 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -75,6 +75,8 @@ * ****************************************************************************/ +#include + #if defined(CONFIG_BIOSEMU) #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index c8b85171928..d6a210c9736 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -44,6 +44,8 @@ * ****************************************************************************/ +#include + #if defined(CONFIG_BIOSEMU) #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c index b3d82bb0524..2a254a4e671 100644 --- a/drivers/bios_emulator/x86emu/prim_ops.c +++ b/drivers/bios_emulator/x86emu/prim_ops.c @@ -97,6 +97,8 @@ * ****************************************************************************/ +#include + #define PRIM_OPS_NO_REDEFINE_ASM #if defined(CONFIG_BIOSEMU) diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c index 6324cd34390..dd44ff1e738 100644 --- a/drivers/bios_emulator/x86emu/sys.c +++ b/drivers/bios_emulator/x86emu/sys.c @@ -39,6 +39,8 @@ * ****************************************************************************/ +#include + #if defined(CONFIG_BIOSEMU) #include "x86emu/x86emui.h" -- cgit v1.3.1 From 81b73dec16fd1227369a191e725e10044a9d56b8 Mon Sep 17 00:00:00 2001 From: Gary Jennejohn Date: Fri, 31 Aug 2007 15:21:46 +0200 Subject: ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese . o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese . o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn Signed-off-by: Stefan Roese --- board/amcc/sequoia/init.S | 3 +++ drivers/pci_auto.c | 8 +++++++- include/configs/sequoia.h | 3 ++- 3 files changed, 12 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 45bcd4bef75..5fe3af9a092 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -126,6 +126,9 @@ tlbtab: /* TLB-entry for peripherals */ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + /* TLB-entry PCI IO Space - from sr@denx.de */ + tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbtab_end #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 2378553be5a..acfda83ba50 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -28,6 +28,11 @@ #define PCIAUTO_IDE_MODE_MASK 0x05 +/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */ +#ifndef CFG_PCI_CACHE_LINE_SIZE +#define CFG_PCI_CACHE_LINE_SIZE 8 +#endif + /* * */ @@ -150,7 +155,8 @@ void pciauto_setup_device(struct pci_controller *hose, } pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, + CFG_PCI_CACHE_LINE_SIZE); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); } diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 824a81240cd..c2e1386217f 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -400,7 +400,8 @@ *----------------------------------------------------------------------*/ /* General PCI */ #define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ -- cgit v1.3.1 From 6e4bf9b24e57c15abc6542e685d06380bc64af27 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 4 Sep 2007 14:25:51 +0100 Subject: Ran Lindent on drivers/at45.c --- drivers/at45.c | 334 ++++++++++++++++++++++++++++----------------------------- 1 file changed, 162 insertions(+), 172 deletions(-) (limited to 'drivers') diff --git a/drivers/at45.c b/drivers/at45.c index 507ff36d478..f48d31776f2 100755 --- a/drivers/at45.c +++ b/drivers/at45.c @@ -27,50 +27,49 @@ /* * spi.c API */ -extern unsigned int AT91F_SpiWrite (AT91PS_DataflashDesc pDesc); -extern void AT91F_SpiEnable(int cs); +extern unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc); +extern void AT91F_SpiEnable(int cs); #define AT91C_TIMEOUT_WRDY 200000 - /*----------------------------------------------------------------------*/ /* \fn AT91F_DataFlashSendCommand */ /* \brief Generic function to send a command to the dataflash */ /*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashSendCommand( - AT91PS_DataFlash pDataFlash, - unsigned char OpCode, - unsigned int CmdSize, - unsigned int DataflashAddress) +AT91S_DataFlashStatus AT91F_DataFlashSendCommand(AT91PS_DataFlash pDataFlash, + unsigned char OpCode, + unsigned int CmdSize, + unsigned int DataflashAddress) { unsigned int adr; - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + if ((pDataFlash->pDataFlashDesc->state) != IDLE) return DATAFLASH_BUSY; /* process the address to obtain page address and byte address */ adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << - pDataFlash->pDevice->page_offset) + (DataflashAddress % - (pDataFlash->pDevice->pages_size)); + pDataFlash->pDevice->page_offset) + (DataflashAddress % + (pDataFlash->pDevice-> + pages_size)); /* fill the command buffer */ pDataFlash->pDataFlashDesc->command[0] = OpCode; if (pDataFlash->pDevice->pages_number >= 16384) { pDataFlash->pDataFlashDesc->command[1] = - (unsigned char)((adr & 0x0F000000) >> 24); + (unsigned char)((adr & 0x0F000000) >> 24); pDataFlash->pDataFlashDesc->command[2] = - (unsigned char)((adr & 0x00FF0000) >> 16); + (unsigned char)((adr & 0x00FF0000) >> 16); pDataFlash->pDataFlashDesc->command[3] = - (unsigned char)((adr & 0x0000FF00) >> 8); + (unsigned char)((adr & 0x0000FF00) >> 8); pDataFlash->pDataFlashDesc->command[4] = - (unsigned char)(adr & 0x000000FF); + (unsigned char)(adr & 0x000000FF); } else { pDataFlash->pDataFlashDesc->command[1] = - (unsigned char)((adr & 0x00FF0000) >> 16); + (unsigned char)((adr & 0x00FF0000) >> 16); pDataFlash->pDataFlashDesc->command[2] = - (unsigned char)((adr & 0x0000FF00) >> 8); + (unsigned char)((adr & 0x0000FF00) >> 8); pDataFlash->pDataFlashDesc->command[3] = - (unsigned char)(adr & 0x000000FF); + (unsigned char)(adr & 0x000000FF); pDataFlash->pDataFlashDesc->command[4] = 0; } pDataFlash->pDataFlashDesc->command[5] = 0; @@ -78,16 +77,16 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand( pDataFlash->pDataFlashDesc->command[7] = 0; /* Initialize the SpiData structure for the spi write fuction */ - pDataFlash->pDataFlashDesc->tx_cmd_pt = - pDataFlash->pDataFlashDesc->command; - pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize; - pDataFlash->pDataFlashDesc->rx_cmd_pt = - pDataFlash->pDataFlashDesc->command; - pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize; + pDataFlash->pDataFlashDesc->tx_cmd_pt = + pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize; + pDataFlash->pDataFlashDesc->rx_cmd_pt = + pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize; /* send the command and read the data */ - return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); } - + return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); +} /*----------------------------------------------------------------------*/ /* \fn AT91F_DataFlashGetStatus */ @@ -98,50 +97,49 @@ AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) AT91S_DataFlashStatus status; /* if a transfert is in progress ==> return 0 */ - if( (pDesc->state) != IDLE) + if ((pDesc->state) != IDLE) return DATAFLASH_BUSY; /* first send the read status command (D7H) */ pDesc->command[0] = DB_STATUS; pDesc->command[1] = 0; - pDesc->DataFlash_state = GET_STATUS; - pDesc->tx_data_size = 0; /* Transmit the command */ - /* and receive response */ - pDesc->tx_cmd_pt = pDesc->command; - pDesc->rx_cmd_pt = pDesc->command; - pDesc->rx_cmd_size = 2; - pDesc->tx_cmd_size = 2; - status = AT91F_SpiWrite (pDesc); + pDesc->DataFlash_state = GET_STATUS; + pDesc->tx_data_size = 0; /* Transmit the command */ + /* and receive response */ + pDesc->tx_cmd_pt = pDesc->command; + pDesc->rx_cmd_pt = pDesc->command; + pDesc->rx_cmd_size = 2; + pDesc->tx_cmd_size = 2; + status = AT91F_SpiWrite(pDesc); - pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); + pDesc->DataFlash_state = *((unsigned char *)(pDesc->rx_cmd_pt) + 1); return status; } - /*----------------------------------------------------------------------*/ /* \fn AT91F_DataFlashWaitReady */ /* \brief wait for dataflash ready (bit7 of the status register == 1) */ /*----------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc -pDataFlashDesc, unsigned int timeout) + pDataFlashDesc, + unsigned int timeout) { pDataFlashDesc->DataFlash_state = IDLE; do { AT91F_DataFlashGetStatus(pDataFlashDesc); timeout--; - } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && - (timeout > 0) ); + } while (((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && + (timeout > 0)); - if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) + if ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) return DATAFLASH_ERROR; return DATAFLASH_OK; } - /*--------------------------------------------------------------------------*/ /* Function Name : AT91F_DataFlashContinuousRead */ /* Object : Continuous stream Read */ @@ -151,17 +149,16 @@ pDataFlashDesc, unsigned int timeout) /* : = data buffer size */ /* Return value : State of the dataflash */ /*--------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( - AT91PS_DataFlash pDataFlash, - int src, - unsigned char *dataBuffer, - int sizeToRead ) +AT91S_DataFlashStatus AT91F_DataFlashContinuousRead(AT91PS_DataFlash pDataFlash, + int src, + unsigned char *dataBuffer, + int sizeToRead) { AT91S_DataFlashStatus status; /* Test the size to read in the device */ - if ( (src + sizeToRead) > - (pDataFlash->pDevice->pages_size * - (pDataFlash->pDevice->pages_number))) + if ((src + sizeToRead) > + (pDataFlash->pDevice->pages_size * + (pDataFlash->pDevice->pages_number))) return DATAFLASH_MEMORY_OVERFLOW; pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; @@ -170,12 +167,11 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; status = AT91F_DataFlashSendCommand - (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); + (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); /* Send the command to the dataflash */ - return(status); + return (status); } - /*---------------------------------------------------------------------------*/ /* Function Name : AT91F_DataFlashPagePgmBuf */ /* Object : Main memory page program thru buffer 1 or buffer 2 */ @@ -185,11 +181,10 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( /* : = data buffer size */ /* Return value : State of the dataflash */ /*---------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int SizeToWrite) +AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int SizeToWrite) { int cmdsize; pDataFlash->pDataFlashDesc->tx_data_pt = src; @@ -201,9 +196,9 @@ AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( /* Send the command to the dataflash */ if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, -cmdsize, dest)); } - + return (AT91F_DataFlashSendCommand(pDataFlash, DB_PAGE_PGM_BUF1, + cmdsize, dest)); +} /*---------------------------------------------------------------------------*/ /* Function Name : AT91F_MainMemoryToBufferTransfert */ @@ -213,15 +208,16 @@ cmdsize, dest)); } /* : */ /* Return value : State of the dataflash */ /*---------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int page) +AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(AT91PS_DataFlash + pDataFlash, + unsigned char + BufferCommand, + unsigned int page) { int cmdsize; /* Test if the buffer command is legal */ if ((BufferCommand != DB_PAGE_2_BUF1_TRF) - && (BufferCommand != DB_PAGE_2_BUF2_TRF)) + && (BufferCommand != DB_PAGE_2_BUF2_TRF)) return DATAFLASH_BAD_COMMAND; /* no data to transmit or receive */ @@ -229,11 +225,11 @@ AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, -page*pDataFlash->pDevice->pages_size)); + return (AT91F_DataFlashSendCommand(pDataFlash, BufferCommand, cmdsize, + page * + pDataFlash->pDevice->pages_size)); } - /*-------------------------------------------------------------------------- */ /* Function Name : AT91F_DataFlashWriteBuffer */ /* Object : Write data to the internal sram buffer 1 or 2 */ @@ -244,58 +240,59 @@ page*pDataFlash->pDevice->pages_size)); /* : = data buffer size */ /* Return value : State of the dataflash */ /*---------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned char *dataBuffer, - unsigned int bufferAddress, - int SizeToWrite ) +AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer(AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned char *dataBuffer, + unsigned int bufferAddress, + int SizeToWrite) { int cmdsize; /* Test if the buffer command is legal */ if ((BufferCommand != DB_BUF1_WRITE) - && (BufferCommand != DB_BUF2_WRITE)) + && (BufferCommand != DB_BUF2_WRITE)) return DATAFLASH_BAD_COMMAND; /* buffer address must be lower than page size */ if (bufferAddress > pDataFlash->pDevice->pages_size) return DATAFLASH_BAD_ADDRESS; - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + if ((pDataFlash->pDataFlashDesc->state) != IDLE) return DATAFLASH_BUSY; /* Send first Write Command */ pDataFlash->pDataFlashDesc->command[0] = BufferCommand; pDataFlash->pDataFlashDesc->command[1] = 0; if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[2] = 0; - pDataFlash->pDataFlashDesc->command[3] = - (unsigned char)(((unsigned int)(bufferAddress & - pDataFlash->pDevice->byte_mask)) >> 8); - pDataFlash->pDataFlashDesc->command[4] = - (unsigned char)((unsigned int)bufferAddress & 0x00FF); + pDataFlash->pDataFlashDesc->command[2] = 0; + pDataFlash->pDataFlashDesc->command[3] = + (unsigned char)(((unsigned int)(bufferAddress & + pDataFlash->pDevice-> + byte_mask)) >> 8); + pDataFlash->pDataFlashDesc->command[4] = + (unsigned char)((unsigned int)bufferAddress & 0x00FF); cmdsize = 5; } else { - pDataFlash->pDataFlashDesc->command[2] = - (unsigned char)(((unsigned int)(bufferAddress & - pDataFlash->pDevice->byte_mask)) >> 8); - pDataFlash->pDataFlashDesc->command[3] = - (unsigned char)((unsigned int)bufferAddress & 0x00FF); - pDataFlash->pDataFlashDesc->command[4] = 0; + pDataFlash->pDataFlashDesc->command[2] = + (unsigned char)(((unsigned int)(bufferAddress & + pDataFlash->pDevice-> + byte_mask)) >> 8); + pDataFlash->pDataFlashDesc->command[3] = + (unsigned char)((unsigned int)bufferAddress & 0x00FF); + pDataFlash->pDataFlashDesc->command[4] = 0; cmdsize = 4; } - pDataFlash->pDataFlashDesc->tx_cmd_pt = - pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->tx_cmd_pt = + pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize; - pDataFlash->pDataFlashDesc->rx_cmd_pt = - pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->rx_cmd_pt = + pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize; - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite; + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite; return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); } @@ -308,23 +305,22 @@ AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( /* : */ /* Return value : State of the dataflash */ /*---------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PageErase( - AT91PS_DataFlash pDataFlash, - unsigned int page) +AT91S_DataFlashStatus AT91F_PageErase(AT91PS_DataFlash pDataFlash, + unsigned int page) { int cmdsize; /* Test if the buffer command is legal */ /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; + pDataFlash->pDataFlashDesc->tx_data_size = 0; cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, -page*pDataFlash->pDevice->pages_size)); + return (AT91F_DataFlashSendCommand(pDataFlash, DB_PAGE_ERASE, cmdsize, + page * + pDataFlash->pDevice->pages_size)); } - /*---------------------------------------------------------------------------*/ /* Function Name : AT91F_BlockErase */ /* Object : Erase a Block */ @@ -333,19 +329,19 @@ page*pDataFlash->pDevice->pages_size)); /* : */ /* Return value : State of the dataflash */ /*---------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_BlockErase( - AT91PS_DataFlash pDataFlash, - unsigned int block) +AT91S_DataFlashStatus AT91F_BlockErase(AT91PS_DataFlash pDataFlash, + unsigned int block) { int cmdsize; /* Test if the buffer command is legal */ /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; + pDataFlash->pDataFlashDesc->tx_data_size = 0; cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, -block*8*pDataFlash->pDevice->pages_size)); + return (AT91F_DataFlashSendCommand(pDataFlash, DB_BLOCK_ERASE, cmdsize, + block * 8 * + pDataFlash->pDevice->pages_size)); } /*---------------------------------------------------------------------------*/ @@ -356,17 +352,16 @@ block*8*pDataFlash->pDevice->pages_size)); /* : = main memory address */ /* Return value : State of the dataflash */ /*---------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_WriteBufferToMain ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int dest ) +AT91S_DataFlashStatus AT91F_WriteBufferToMain(AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int dest) { int cmdsize; /* Test if the buffer command is correct */ if ((BufferCommand != DB_BUF1_PAGE_PGM) && (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && (BufferCommand != DB_BUF2_PAGE_PGM) && - (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) + (BufferCommand != DB_BUF2_PAGE_ERASE_PGM)) return DATAFLASH_BAD_COMMAND; /* no data to transmit or receive */ @@ -376,9 +371,9 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain ( if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; /* Send the command to the dataflash */ - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, - dest)); } - + return (AT91F_DataFlashSendCommand(pDataFlash, BufferCommand, cmdsize, + dest)); +} /*---------------------------------------------------------------------------*/ /* Function Name : AT91F_PartialPageWrite */ @@ -387,11 +382,10 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain ( /* : = adr to begin the fading */ /* : = Number of bytes to erase */ /*---------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PartialPageWrite ( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int size) +AT91S_DataFlashStatus AT91F_PartialPageWrite(AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int size) { unsigned int page; unsigned int AdrInPage; @@ -400,28 +394,28 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite ( AdrInPage = dest % (pDataFlash->pDevice->pages_size); /* Read the contents of the page in the Sram Buffer */ - AT91F_MainMemoryToBufferTransfert(pDataFlash, - DB_PAGE_2_BUF1_TRF, page); + AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY); + AT91C_TIMEOUT_WRDY); /*Update the SRAM buffer */ AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, - AdrInPage, size); + AdrInPage, size); AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY); + AT91C_TIMEOUT_WRDY); /* Erase page if a 128 Mbits device */ if (pDataFlash->pDevice->pages_number >= 16384) { AT91F_PageErase(pDataFlash, page); /* Rewrite the modified Sram Buffer in the main memory */ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY); + AT91C_TIMEOUT_WRDY); } /* Rewrite the modified Sram Buffer in the main memory */ - return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, - (page*pDataFlash->pDevice->pages_size))); + return (AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, + (page * + pDataFlash->pDevice->pages_size))); } /*---------------------------------------------------------------------------*/ @@ -431,11 +425,9 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite ( /* : = dataflash adress */ /* : = data buffer size */ /*---------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWrite( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ) +AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash pDataFlash, + unsigned char *src, + int dest, int size) { unsigned int length; unsigned int page; @@ -443,26 +435,24 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite( AT91F_SpiEnable(pDataFlash->pDevice->cs); - if ( (dest + size) > (pDataFlash->pDevice->pages_size * - (pDataFlash->pDevice->pages_number))) + if ((dest + size) > (pDataFlash->pDevice->pages_size * + (pDataFlash->pDevice->pages_number))) return DATAFLASH_MEMORY_OVERFLOW; /* If destination does not fit a page start address */ - if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) - { + if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0) { length = pDataFlash->pDevice->pages_size - - (dest % - ((unsigned int) - (pDataFlash->pDevice->pages_size))); + (dest % ((unsigned int) + (pDataFlash->pDevice->pages_size))); if (size < length) length = size; - if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) + if (!AT91F_PartialPageWrite(pDataFlash, src, dest, length)) return DATAFLASH_ERROR; AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY); + AT91C_TIMEOUT_WRDY); /* Update size, source and destination pointers */ size -= length; @@ -470,78 +460,77 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite( src += length; } - while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { + while ((size - pDataFlash->pDevice->pages_size) >= 0) { /* program dataflash page */ page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); status = AT91F_DataFlashWriteBuffer(pDataFlash, - DB_BUF1_WRITE, src, 0, - pDataFlash->pDevice->pages_size); + DB_BUF1_WRITE, src, 0, + pDataFlash->pDevice-> + pages_size); AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY); + AT91C_TIMEOUT_WRDY); status = AT91F_PageErase(pDataFlash, page); AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY); + AT91C_TIMEOUT_WRDY); if (!status) return DATAFLASH_ERROR; - status = AT91F_WriteBufferToMain (pDataFlash, - DB_BUF1_PAGE_PGM, dest); - if(!status) + status = AT91F_WriteBufferToMain(pDataFlash, + DB_BUF1_PAGE_PGM, dest); + if (!status) return DATAFLASH_ERROR; AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY); + AT91C_TIMEOUT_WRDY); /* Update size, source and destination pointers */ size -= pDataFlash->pDevice->pages_size; dest += pDataFlash->pDevice->pages_size; - src += pDataFlash->pDevice->pages_size; + src += pDataFlash->pDevice->pages_size; } /* If still some bytes to read */ - if ( size > 0 ) { + if (size > 0) { /* program dataflash page */ - if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) + if (!AT91F_PartialPageWrite(pDataFlash, src, dest, size)) return DATAFLASH_ERROR; AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY); + AT91C_TIMEOUT_WRDY); } return DATAFLASH_OK; } - /*---------------------------------------------------------------------------*/ /* Function Name : AT91F_DataFlashRead */ /* Object : Read a block in dataflash */ /* Input Parameters : */ /* Return value : */ /*---------------------------------------------------------------------------*/ -int AT91F_DataFlashRead( - AT91PS_DataFlash pDataFlash, - unsigned long addr, - unsigned long size, - char *buffer) +int AT91F_DataFlashRead(AT91PS_DataFlash pDataFlash, + unsigned long addr, unsigned long size, char *buffer) { unsigned long SizeToRead; AT91F_SpiEnable(pDataFlash->pDevice->cs); - if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, + AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) return -1; while (size) { - SizeToRead = (size < 0x8000)? size:0x8000; + SizeToRead = (size < 0x8000) ? size : 0x8000; if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + AT91C_TIMEOUT_WRDY) != + DATAFLASH_OK) return -1; - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, - (uchar *) buffer, SizeToRead) != DATAFLASH_OK) + if (AT91F_DataFlashContinuousRead(pDataFlash, addr, + (uchar *) buffer, + SizeToRead) != DATAFLASH_OK) return -1; size -= SizeToRead; @@ -558,9 +547,10 @@ int AT91F_DataFlashRead( /* Input Parameters : */ /* Return value : Dataflash status register */ /*---------------------------------------------------------------------------*/ -int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) { +int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) +{ AT91F_SpiEnable(cs); AT91F_DataFlashGetStatus(pDesc); - return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); + return ((pDesc->command[1] == 0xFF) ? 0 : pDesc->command[1] & 0x3C); } #endif -- cgit v1.3.1 From 041a2554ad619e80dce520c1a33210affcb6a3f2 Mon Sep 17 00:00:00 2001 From: Gary Jennejohn Date: Fri, 31 Aug 2007 14:29:04 +0200 Subject: Add support for Sil680 IDE controller. o add drivers/sil680.c to support the Sil680 IDE-controller. o drivers/Makefile: add sil680.o. Signed-off-by: Gary Jennejohn --- drivers/Makefile | 2 +- drivers/sil680.c | 110 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 drivers/sil680.c (limited to 'drivers') diff --git a/drivers/Makefile b/drivers/Makefile index 3ee6312e9db..6bf05ccad19 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -43,7 +43,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \ sed13806.o sed156x.o \ serial.o serial_max3100.o \ serial_pl010.o serial_pl011.o serial_xuartlite.o \ - sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ + sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ status_led.o sym53c8xx.o systemace.o ahci.o \ ti_pci1410a.o tigon3.o tsec.o \ tsi108_eth.o tsi108_i2c.o tsi108_pci.o \ diff --git a/drivers/sil680.c b/drivers/sil680.c new file mode 100644 index 00000000000..a6143df4c06 --- /dev/null +++ b/drivers/sil680.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2007 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* sil680.c - ide support functions for the Sil0680A controller */ + +/* + * The following parameters must be defined in the configuration file + * of the target board: + * + * #define CFG_IDE_SIL680 + * + * #define CONFIG_PCI_PNP + * NOTE it may also be necessary to define this if the default of 8 is + * incorrect for the target board (e.g. the sequoia board requires 0). + * #define CFG_PCI_CACHE_LINE_SIZE 0 + * + * #define CONFIG_CMD_IDE + * #undef CONFIG_IDE_8xx_DIRECT + * #undef CONFIG_IDE_LED + * #undef CONFIG_IDE_RESET + * #define CONFIG_IDE_PREINIT + * #define CFG_IDE_MAXBUS 2 - modify to suit + * #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) - modify to suit + * #define CFG_ATA_BASE_ADDR 0 + * #define CFG_ATA_IDE0_OFFSET 0 + * #define CFG_ATA_IDE1_OFFSET 0 + * #define CFG_ATA_DATA_OFFSET 0 + * #define CFG_ATA_REG_OFFSET 0 + * #define CFG_ATA_ALT_OFFSET 0x0004 + * + * The mapping for PCI IO-space. + * NOTE this is the value for the sequoia board. Modify to suit. + * #define CFG_PCI0_IO_SPACE 0xE8000000 + */ + +#include +#if defined(CFG_IDE_SIL680) +#include +#include +#include + +extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; + +int ide_preinit (void) +{ + int status; + pci_dev_t devbusfn; + int l; + + status = 1; + for (l = 0; l < CFG_IDE_MAXBUS; l++) { + ide_bus_offset[l] = -ATA_STATUS; + } + devbusfn = pci_find_device (0x1095, 0x0680, 0); + if (devbusfn != -1) { + status = 0; + + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, + (u32 *) &ide_bus_offset[0]); + ide_bus_offset[0] &= 0xfffffff8; + ide_bus_offset[0] += CFG_PCI0_IO_SPACE; + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, + (u32 *) &ide_bus_offset[1]); + ide_bus_offset[1] &= 0xfffffff8; + ide_bus_offset[1] += CFG_PCI0_IO_SPACE; + /* init various things - taken from the Linux driver */ + /* set PIO mode */ + pci_write_config_byte(devbusfn, 0x80, 0x00); + pci_write_config_byte(devbusfn, 0x84, 0x00); + /* IDE0 */ + pci_write_config_byte(devbusfn, 0xA1, 0x02); + pci_write_config_word(devbusfn, 0xA2, 0x328A); + pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD); + pci_write_config_dword(devbusfn, 0xA8, 0x43924392); + pci_write_config_dword(devbusfn, 0xAC, 0x40094009); + /* IDE1 */ + pci_write_config_byte(devbusfn, 0xB1, 0x02); + pci_write_config_word(devbusfn, 0xB2, 0x328A); + pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD); + pci_write_config_dword(devbusfn, 0xB8, 0x43924392); + pci_write_config_dword(devbusfn, 0xBC, 0x40094009); + } + return (status); +} + +void ide_set_reset (int flag) { + return; +} + +#endif /* CFG_IDE_SIL680 */ -- cgit v1.3.1 From 1d2ca446e1a731df420206d04fe278c27ea6b8e8 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Thu, 30 Aug 2007 18:19:05 +0800 Subject: Add BUILD_DIR support for bios emulator. Signed-off-by: Jason Jin --- drivers/bios_emulator/Makefile | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index 586e83be8f2..90c64dad602 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -2,9 +2,11 @@ include $(TOPDIR)/config.mk LIB := $(obj)libatibiosemu.a -X86DIR = ./x86emu +X86DIR = x86emu -OBJS = atibios.o biosemu.o besys.o bios.o \ +$(shell mkdir -p $(obj)$(X86DIR)) + +COBJS = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/decode.o \ $(X86DIR)/ops2.o \ $(X86DIR)/ops.o \ @@ -12,19 +14,24 @@ OBJS = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/sys.o \ $(X86DIR)/debug.o -CFLAGS += -I. -I./include -I$(X86DIR) -I$(TOPDIR)/include \ +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \ -D__PPC__ -D__BIG_ENDIAN__ +CFLAGS += $(EXTRA_CFLAGS) +HOST_CFLAGS += $(EXTRA_CFLAGS) + all: $(LIB) -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) ######################################################################### -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude $(obj).depend ######################################################################### -- cgit v1.3.1 From 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3 Mon Sep 17 00:00:00 2001 From: stefano babic Date: Thu, 30 Aug 2007 23:01:49 +0200 Subject: PXA270: Added support for TrizepsIV board. This patch add support for the Trizeps IV module (520Mhz). Signed-off-by: Stefano Babic --- Makefile | 3 + board/trizepsiv/Makefile | 51 ++++ board/trizepsiv/config.mk | 3 + board/trizepsiv/conxs.c | 146 ++++++++++++ board/trizepsiv/eeprom.c | 85 +++++++ board/trizepsiv/lowlevel_init.S | 503 ++++++++++++++++++++++++++++++++++++++++ board/trizepsiv/pxavoltage.S | 31 +++ board/trizepsiv/u-boot.lds | 56 +++++ drivers/dm9000x.c | 16 +- include/configs/trizepsiv.h | 325 ++++++++++++++++++++++++++ 10 files changed, 1217 insertions(+), 2 deletions(-) create mode 100644 board/trizepsiv/Makefile create mode 100644 board/trizepsiv/config.mk create mode 100644 board/trizepsiv/conxs.c create mode 100644 board/trizepsiv/eeprom.c create mode 100644 board/trizepsiv/lowlevel_init.S create mode 100644 board/trizepsiv/pxavoltage.S create mode 100644 board/trizepsiv/u-boot.lds create mode 100644 include/configs/trizepsiv.h (limited to 'drivers') diff --git a/Makefile b/Makefile index 0477cd3dc2e..0371d4619d4 100644 --- a/Makefile +++ b/Makefile @@ -2334,6 +2334,9 @@ scpu_config: unconfig pxa255_idp_config: unconfig @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp +trizepsiv_config : unconfig + @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv + wepep250_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa wepep250 diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile new file mode 100644 index 00000000000..115e17ded92 --- /dev/null +++ b/board/trizepsiv/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := conxs.o eeprom.o +SOBJS := lowlevel_init.o pxavoltage.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/trizepsiv/config.mk b/board/trizepsiv/config.mk new file mode 100644 index 00000000000..4486f6b96db --- /dev/null +++ b/board/trizepsiv/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE =0xa1f00000 +# 0xa1700000 +#TEXT_BASE = 0 diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c new file mode 100644 index 00000000000..7c6c8550074 --- /dev/null +++ b/board/trizepsiv/conxs.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ + +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +void usb_board_init(void) +{ + UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + UHCHR |= UHCHR_FSBIR; + + while (UHCHR & UHCHR_FSBIR); + + UHCHR &= ~UHCHR_SSE; + UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + + /* Clear any OTG Pin Hold */ + if (PSSR & PSSR_OTGPH) + PSSR |= PSSR_OTGPH; + + UHCRHDA &= ~(RH_A_NPS); + UHCRHDA |= RH_A_PSM; + + /* Set port power control mask bits, only 3 ports. */ + UHCRHDB |= (0x7<<17); +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + UHCHR |= UHCHR_FHR; + udelay(11); + UHCHR &= ~UHCHR_FHR; + + UHCCOMS |= 1; + udelay(10); + + CKEN &= ~CKEN10_USBHOST; + + puts("Called USB STOP\n"); + return; +} + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of ConXS Board */ + gd->bd->bi_arch_number = 776; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa000003c; + + return 0; +} + +int board_late_init(void) +{ +#if defined(CONFIG_SERIAL_MULTI) + char *console=getenv("boot_console"); + + if ((strcmp(console,"serial_btuart") == 0) || + (strcmp(console,"serial_stuart") == 0) || + (strcmp(console,"serial_ffuart") == 0)) { + setenv("stdout",console); + setenv("stdin", console); + setenv("stderr",console); + } else { + setenv("stdout", "serial"); + setenv("stdin", "serial"); + setenv("stderr", "serial"); + } +#endif + return 0; +} + +struct serial_device *default_serial_console (void) +{ + return &serial_ffuart_device; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c new file mode 100644 index 00000000000..3d3bc00221b --- /dev/null +++ b/board/trizepsiv/eeprom.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +static unsigned char srom[128]; +extern u16 read_srom_word(int); +extern void write_srom_word(int offset, u16 val); + +static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int i; + + for (i=0; i < 0x40; i++) { + if (!(i % 0x10)) + printf("\n%08lx:", i); + printf(" %04x", read_srom_word(i)); + } + printf ("\n"); + return (0); +} + +static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int offset,value; + + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + offset=simple_strtoul(argv[2],NULL,16); + value=simple_strtoul(argv[3],NULL,16); + if (offset > 0x40) { + printf("Wrong offset : 0x%x\n",offset); + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + write_srom_word(offset, value); + return (0); +} + +int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp (argv[1],"read") == 0) { + return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else if (strcmp (argv[1],"write") == 0) { + return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } +} + +U_BOOT_CMD( + dm9000ee,4,1,do_dm9000_eeprom, + "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n", + "\ndm9000ee write \n" + "\tdm9000ee read \n" + "\tword:\t\t00-02 : MAC Address\n" + "\t\t\t03-07 : DM9000 Configuration\n" + "\t\t\t08-63 : User data\n"); diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S new file mode 100644 index 00000000000..d8869381acc --- /dev/null +++ b/board/trizepsiv/lowlevel_init.S @@ -0,0 +1,503 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CFG_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CFG_GPCR3_VAL + str r1, [r0] + + ldr r0, =GRER0 + ldr r1, =CFG_GRER0_VAL + str r1, [r0] + + ldr r0, =GRER1 + ldr r1, =CFG_GRER1_VAL + str r1, [r0] + + ldr r0, =GRER2 + ldr r1, =CFG_GRER2_VAL + str r1, [r0] + + ldr r0, =GRER3 + ldr r1, =CFG_GRER3_VAL + str r1, [r0] + + ldr r0, =GFER0 + ldr r1, =CFG_GFER0_VAL + str r1, [r0] + + ldr r0, =GFER1 + ldr r1, =CFG_GFER1_VAL + str r1, [r0] + + ldr r0, =GFER2 + ldr r1, =CFG_GFER2_VAL + str r1, [r0] + + ldr r0, =GFER3 + ldr r1, =CFG_GFER3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CFG_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CFG_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CFG_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + ldr r2, =CFG_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CFG_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + bic r4, r4, #MDREFR_K2FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + ldr r2, =CFG_SXCNFG_VAL + str r2, [r1, #SXCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ + + +setvoltage: + + mov r10, lr + bl initPXAvoltage /* In case the board is rebooting with a */ + mov lr, r10 /* low voltage raise it up to a good one. */ + +#if 1 + b initirqs +#endif + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CFG_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CFG_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MEMC_BASE + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#else +#error "RTC not defined" +#endif + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/trizepsiv/pxavoltage.S b/board/trizepsiv/pxavoltage.S new file mode 100644 index 00000000000..5e411321f30 --- /dev/null +++ b/board/trizepsiv/pxavoltage.S @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + + .global initPXAvoltage + +initPXAvoltage: + mov pc, lr + diff --git a/board/trizepsiv/u-boot.lds b/board/trizepsiv/u-boot.lds new file mode 100644 index 00000000000..f0102391b34 --- /dev/null +++ b/board/trizepsiv/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c index e0d531bd917..6131b5c3570 100644 --- a/drivers/dm9000x.c +++ b/drivers/dm9000x.c @@ -99,7 +99,7 @@ void eth_halt(void); static int dm9000_probe(void); static u16 phy_read(int); static void phy_write(int, u16); -static u16 read_srom_word(int); +u16 read_srom_word(int); static u8 DM9000_ior(int); static void DM9000_iow(int reg, u8 value); @@ -537,7 +537,7 @@ eth_rx(void) /* Read a word data from SROM */ -static u16 +u16 read_srom_word(int offset) { DM9000_iow(DM9000_EPAR, offset); @@ -547,6 +547,18 @@ read_srom_word(int offset) return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); } +void +write_srom_word(int offset, u16 val) +{ + DM9000_iow(DM9000_EPAR, offset); + DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); + DM9000_iow(DM9000_EPDRL, (val & 0xff)); + DM9000_iow(DM9000_EPCR, 0x12); + udelay(8000); + DM9000_iow(DM9000_EPCR, 0); +} + + /* Read a byte from I/O port */ diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h new file mode 100644 index 00000000000..84998d4392a --- /dev/null +++ b/include/configs/trizepsiv.h @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the LUBBOCK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ + +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ + +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define RTC + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_FFUART 1 /* we use FFUART on Conxs */ +#define CONFIG_BTUART 1 /* we use BTUART on Conxs */ +#define CONFIG_STUART 1 /* we use STUART on Conxs */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IMLS +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SERVERIP 192.168.1.99 +#define CONFIG_BOOTCOMMAND "run boot_flash" +#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ + " rw root=/dev/ram initrd=0xa0800000,5m" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "program_boot_mmc=" \ + "mw.b 0xa0010000 0xff 0x20000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x1ffff; " \ + "erase 0x0 0x1ffff; " \ + "cp.b 0xa0010000 0x0 0x20000; " \ + "fi\0" \ + "program_uzImage_mmc=" \ + "mw.b 0xa0010000 0xff 0x180000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 uzImage; " \ + "then " \ + "protect off 0x40000 0x1bffff; " \ + "erase 0x40000 0x1bffff; " \ + "cp.b 0xa0010000 0x40000 0x180000; " \ + "fi\0" \ + "program_ramdisk_mmc=" \ + "mw.b 0xa0010000 0xff 0x500000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 ramdisk.gz; " \ + "then " \ + "protect off 0x1c0000 0x6bffff; " \ + "erase 0x1c0000 0x6bffff; " \ + "cp.b 0xa0010000 0x1c0000 0x500000; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmcinit && " \ + "fatload mmc 0 0xa0030000 uzImage && " \ + "fatload mmc 0 0xa0800000 ramdisk.gz; " \ + "then " \ + "bootm 0xa0030000; " \ + "fi\0" \ + "boot_flash=" \ + "cp.b 0x1c0000 0xa0800000 0x500000; " \ + "bootm 0x40000\0" \ + +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +/* #define CONFIG_INITRD_TAG 1 */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MMC_BASE 0xF0000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00018000 +#define CFG_GPSR1_VAL 0x00000000 +#define CFG_GPSR2_VAL 0x400dc000 +#define CFG_GPSR3_VAL 0x00000000 +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPCR3_VAL 0x00000000 +#define CFG_GPDR0_VAL 0x00018000 +#define CFG_GPDR1_VAL 0x00028801 +#define CFG_GPDR2_VAL 0x520dc000 +#define CFG_GPDR3_VAL 0x0001E000 +#define CFG_GAFR0_L_VAL 0x801c0000 +#define CFG_GAFR0_U_VAL 0x00000013 +#define CFG_GAFR1_L_VAL 0x6990100A +#define CFG_GAFR1_U_VAL 0x00000008 +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x010900F2 +#define CFG_GAFR3_L_VAL 0x54000003 +#define CFG_GAFR3_U_VAL 0x00002401 +#define CFG_GRER0_VAL 0x00000000 +#define CFG_GRER1_VAL 0x00000000 +#define CFG_GRER2_VAL 0x00000000 +#define CFG_GRER3_VAL 0x00000000 +#define CFG_GFER0_VAL 0x00000000 +#define CFG_GFER1_VAL 0x00000000 +#define CFG_GFER2_VAL 0x00000000 +#define CFG_GFER3_VAL 0x00000020 + + +#define CFG_PSSR_VAL 0x20 /* CHECK */ + +/* + * Clock settings + */ +#define CFG_CKEN 0x01FFFFFF /* CHECK */ +#define CFG_CCCR 0x02000290 /* 520Mhz */ + +/* + * Memory settings + */ + +#define CFG_MSC0_VAL 0x4df84df0 +#define CFG_MSC1_VAL 0x7ff87ff4 +#define CFG_MSC2_VAL 0xa26936d4 +#define CFG_MDCNFG_VAL 0x880009C9 +#define CFG_MDREFR_VAL 0x20ca201e +#define CFG_MDMRS_VAL 0x00220022 + +#define CFG_FLYCNFG_VAL 0x00000000 +#define CFG_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000001 +#define CFG_MCMEM0_VAL 0x00004204 +#define CFG_MCMEM1_VAL 0x00010204 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00008407 +#define CFG_MCIO1_VAL 0x0000c108 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x08000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) +/* #define CONFIG_DM9000_USE_8BIT */ +/* #define CONFIG_DM9000_USE_16BIT */ +#define CONFIG_DM9000_USE_32BIT + +#define CONFIG_USB_OHCI_NEW 1 +#define CFG_USB_OHCI_BOARD_INIT 1 +#define CFG_USB_OHCI_MAX_ROOT_PORTS 3 +#define CFG_USB_OHCI_REGS_BASE 0x4C000000 +#define CFG_USB_OHCI_SLOT_NAME "trizepsiv" +#define CONFIG_USB_STORAGE 1 +#define CFG_USB_OHCI_CPU_INIT 1 + +/* + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_MONITOR_BASE 0 +#define CFG_MONITOR_LEN 0x40000 + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* write flash less slowly */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* Flash environment locations */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 1218abf1b5817a39a82399b4b928b00750575bda Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 15 Sep 2007 20:48:41 +0200 Subject: Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as global Signed-off-by: Wolfgang Denk --- board/amcc/katmai/katmai.c | 4 ++-- board/amcc/taishan/taishan.c | 4 ++-- board/amcc/yucca/yucca.c | 4 ++-- board/bf533-ezkit/bf533-ezkit.c | 3 ++- board/bf533-stamp/bf533-stamp.c | 3 ++- board/bf537-stamp/bf537-stamp.c | 3 ++- board/bf561-ezkit/bf561-ezkit.c | 3 ++- board/freescale/mpc8313erdb/sdram.c | 3 ++- board/lpc2292sodimm/lpc2292sodimm.c | 7 +------ board/mpc7448hpc2/mpc7448hpc2.c | 4 ++-- board/mpc7448hpc2/tsi108_init.c | 4 ++-- board/mpl/vcma9/cmd_vcma9.c | 4 ++-- board/sbc2410x/sbc2410x.c | 5 +---- board/siemens/SMN42/smn42.c | 7 +------ board/tqm5200/tqm5200.c | 4 ++-- cpu/arm720t/serial.c | 2 -- cpu/bf533/serial.c | 1 - cpu/bf537/i2c.c | 3 ++- cpu/bf537/serial.c | 3 ++- cpu/bf561/serial.c | 3 ++- cpu/mcf532x/cpu.c | 4 ++-- cpu/mcf532x/speed.c | 4 ++-- cpu/mpc86xx/cpu_init.c | 3 ++- cpu/mpc86xx/speed.c | 2 +- cpu/mpc86xx/traps.c | 4 ++-- drivers/qe/qe.c | 7 ++----- drivers/usbdcore_mpc8xx.c | 3 ++- include/configs/atstk1002.h | 3 +-- lib_blackfin/board.c | 7 ++----- lib_blackfin/post.c | 10 ++-------- 30 files changed, 51 insertions(+), 70 deletions(-) (limited to 'drivers') diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index afd60ece624..a49066fcc94 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -34,6 +34,8 @@ #undef PCIE_ENDPOINT /* #define PCIE_ENDPOINT 1 */ +DECLARE_GLOBAL_DATA_PTR; + int ppc440spe_init_pcie_rootport(int port); void ppc440spe_setup_pcie(struct pci_controller *hose, int port); @@ -322,8 +324,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index bc976c75261..f00397ed197 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -32,6 +32,8 @@ void show_reset_reg(void); #endif +DECLARE_GLOBAL_DATA_PTR; + int lcd_init(void); int board_early_init_f (void) @@ -266,8 +268,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 397b01873f4..d7cc384ba0b 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -34,6 +34,8 @@ #include "yucca.h" #include "../cpu/ppc4xx/440spe_pcie.h" +DECLARE_GLOBAL_DATA_PTR; + #undef PCIE_ENDPOINT /* #define PCIE_ENDPOINT 1 */ @@ -668,8 +670,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 1dd4a3fe2e0..98ed6f81d2b 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -30,6 +30,8 @@ #include "psd4256.h" #endif +DECLARE_GLOBAL_DATA_PTR; + int checkboard(void) { #if (BFIN_CPU == ADSP_BF531) @@ -46,7 +48,6 @@ int checkboard(void) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG int brate; char *tmp = getenv("baudrate"); diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index b9dff99171a..69e425bf974 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -30,6 +30,8 @@ #include #include "bf533-stamp.h" +DECLARE_GLOBAL_DATA_PTR; + #define STATUS_LED_OFF 0 #define STATUS_LED_ON 1 @@ -55,7 +57,6 @@ int checkboard(void) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG printf("SDRAM attributes:\n"); printf diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 919cef688db..b3d8bda9bf6 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -32,6 +32,8 @@ #include #include "ether_bf537.h" +DECLARE_GLOBAL_DATA_PTR; + #define POST_WORD_ADDR 0xFF903FFC /* @@ -132,7 +134,6 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG int brate; char *tmp = getenv("baudrate"); diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 989b0194c1e..2ff44a7152a 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -29,6 +29,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + int checkboard(void) { printf("CPU: ADSP BF561\n"); @@ -39,7 +41,6 @@ int checkboard(void) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG int brate; char *tmp = getenv("baudrate"); diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index e6e84107eb2..16ec4bbf546 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -33,10 +33,11 @@ #include +DECLARE_GLOBAL_DATA_PTR; + #ifndef CFG_8313ERDB_BROKEN_PMC static void resume_from_sleep(void) { - DECLARE_GLOBAL_DATA_PTR; u32 magic = *(u32 *)0; typedef void (*func_t)(void); diff --git a/board/lpc2292sodimm/lpc2292sodimm.c b/board/lpc2292sodimm/lpc2292sodimm.c index d212c63328b..9c2d1af2fcb 100644 --- a/board/lpc2292sodimm/lpc2292sodimm.c +++ b/board/lpc2292sodimm/lpc2292sodimm.c @@ -28,8 +28,7 @@ #include #include -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -37,8 +36,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* Activate LED flasher */ IO_LEDFLSH = 0x40; @@ -53,8 +50,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/mpc7448hpc2/mpc7448hpc2.c index 63c99de1756..81846eba77d 100644 --- a/board/mpc7448hpc2/mpc7448hpc2.c +++ b/board/mpc7448hpc2/mpc7448hpc2.c @@ -38,6 +38,8 @@ extern void ft_cpu_setup (void *blob, bd_t *bd); #undef DEBUG +DECLARE_GLOBAL_DATA_PTR; + extern void flush_data_cache (void); extern void invalidate_l1_instruction_cache (void); extern void tsi108_init_f (void); @@ -46,8 +48,6 @@ int display_mem_map (void); void after_reloc (ulong dest_addr) { - DECLARE_GLOBAL_DATA_PTR; - /* * Jump to the main U-Boot board init code */ diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c index 8a7efef7723..30ae17d8729 100644 --- a/board/mpc7448hpc2/tsi108_init.c +++ b/board/mpc7448hpc2/tsi108_init.c @@ -33,6 +33,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + extern void mpicInit (int verbose); /* @@ -141,7 +143,6 @@ unsigned long get_board_bus_clk (void) int board_early_init_f (void) { - DECLARE_GLOBAL_DATA_PTR; ulong i; gd->mem_clk = 0; @@ -583,7 +584,6 @@ unsigned long get_l2cr (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; #ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ ulong i; diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index 44b41125546..227c49272ce 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -40,6 +40,8 @@ static uchar cs8900_chksum(ushort data) #endif +DECLARE_GLOBAL_DATA_PTR; + extern void print_vcma9_info(void); extern int vcma9_cantest(int); extern int vcma9_nandtest(void); @@ -53,8 +55,6 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - DECLARE_GLOBAL_DATA_PTR; - if (strcmp(argv[1], "info") == 0) { print_vcma9_info(); diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index b4865e1229c..6c894a3869e 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -35,7 +35,7 @@ #include #endif -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; #define FCLK_SPEED 1 @@ -74,7 +74,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); @@ -128,8 +127,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/siemens/SMN42/smn42.c b/board/siemens/SMN42/smn42.c index cbfc76c4639..52d1d7e5f38 100644 --- a/board/siemens/SMN42/smn42.c +++ b/board/siemens/SMN42/smn42.c @@ -31,8 +31,7 @@ #include #include -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscellaneous platform dependent initialisations @@ -40,8 +39,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number MACH_TYPE_ARMADILLO - not official*/ gd->bd->bi_arch_number = 83; @@ -53,8 +50,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 21f67aa4e53..29d6f00427f 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -43,6 +43,8 @@ #include "mt48lc16m16a2-75.h" #endif +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_PS2MULT void ps2mult_early_init(void); #endif @@ -477,8 +479,6 @@ int silent_boot (void) int board_early_init_f (void) { - DECLARE_GLOBAL_DATA_PTR; - if (silent_boot()) gd->flags |= GD_FLG_SILENT; diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c index 15c54af08b7..27eb73ad889 100644 --- a/cpu/arm720t/serial.c +++ b/cpu/arm720t/serial.c @@ -129,8 +129,6 @@ serial_puts (const char *s) void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - unsigned short divisor = 0; switch (gd->baudrate) { diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c index 6cab5daac79..8ac6e3ff64e 100644 --- a/cpu/bf533/serial.c +++ b/cpu/bf533/serial.c @@ -76,7 +76,6 @@ void calc_baud(void) void serial_setbrg(void) { int i; - DECLARE_GLOBAL_DATA_PTR; calc_baud(); diff --git a/cpu/bf537/i2c.c b/cpu/bf537/i2c.c index 3b0d026e0dc..0daba63b68a 100644 --- a/cpu/bf537/i2c.c +++ b/cpu/bf537/i2c.c @@ -22,6 +22,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #define bfin_read16(addr) ({ unsigned __v; \ __asm__ __volatile__ (\ "%0 = w[%1] (z);\n\t"\ @@ -68,7 +70,6 @@ #ifdef DEBUG_I2C #define PRINTD(fmt,args...) do { \ - DECLARE_GLOBAL_DATA_PTR; \ if (gd->have_console) \ printf(fmt ,##args); \ } while (0) diff --git a/cpu/bf537/serial.c b/cpu/bf537/serial.c index e04d08a0e77..f7a2483ffbe 100644 --- a/cpu/bf537/serial.c +++ b/cpu/bf537/serial.c @@ -52,6 +52,8 @@ #include #include "serial.h" +DECLARE_GLOBAL_DATA_PTR; + unsigned long pll_div_fact; void calc_baud(void) @@ -74,7 +76,6 @@ void calc_baud(void) void serial_setbrg(void) { int i; - DECLARE_GLOBAL_DATA_PTR; calc_baud(); diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c index 7f5c6953618..bc5a4f57260 100644 --- a/cpu/bf561/serial.c +++ b/cpu/bf561/serial.c @@ -52,6 +52,8 @@ #include "serial.h" #include +DECLARE_GLOBAL_DATA_PTR; + unsigned long pll_div_fact; void calc_baud(void) @@ -74,7 +76,6 @@ void calc_baud(void) void serial_setbrg(void) { int i; - DECLARE_GLOBAL_DATA_PTR; calc_baud(); diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c index 520f5d69397..2f62e956cca 100644 --- a/cpu/mcf532x/cpu.c +++ b/cpu/mcf532x/cpu.c @@ -31,6 +31,8 @@ #include +DECLARE_GLOBAL_DATA_PTR; + int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) { volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); @@ -48,8 +50,6 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) int checkcpu(void) { - DECLARE_GLOBAL_DATA_PTR; - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; u16 msk; u16 id = 0; diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c index cf72609b42f..001b9f42d64 100644 --- a/cpu/mcf532x/speed.c +++ b/cpu/mcf532x/speed.c @@ -30,6 +30,8 @@ #include +DECLARE_GLOBAL_DATA_PTR; + /* PLL min/max specifications */ #define MAX_FVCO 500000 /* KHz */ #define MAX_FSYS 80000 /* KHz */ @@ -208,8 +210,6 @@ int clock_pll(int fsys, int flags) */ int get_clocks(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000; gd->cpu_clk = (gd->bus_clk * 3); return (0); diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index c8e46666949..4f8956e0afe 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -29,6 +29,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + /* * Breathe some life into the CPU... * @@ -38,7 +40,6 @@ void cpu_init_f(void) { - DECLARE_GLOBAL_DATA_PTR; volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 312ca128277..23161ca8cbe 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -29,6 +29,7 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; void get_sys_info(sys_info_t *sysInfo) { @@ -96,7 +97,6 @@ void get_sys_info(sys_info_t *sysInfo) int get_clocks(void) { - DECLARE_GLOBAL_DATA_PTR; sys_info_t sys_info; get_sys_info(&sys_info); diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index c84bfbf6aaa..04c2e1331b6 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -34,6 +34,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -50,8 +52,6 @@ extern unsigned long search_exception_table(unsigned long); void print_backtrace(unsigned long *sp) { - DECLARE_GLOBAL_DATA_PTR; - int cnt = 0; unsigned long i; diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 0f5232a72af..7559e922272 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -30,6 +30,8 @@ qe_map_t *qe_immr = NULL; static qe_snum_t snums[QE_NUM_OF_SNUM]; +DECLARE_GLOBAL_DATA_PTR; + void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) { u32 cecr; @@ -51,8 +53,6 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) uint qe_muram_alloc(uint size, uint align) { - DECLARE_GLOBAL_DATA_PTR; - uint retloc; uint align_mask, off; uint savebase; @@ -158,8 +158,6 @@ void qe_put_snum(u8 snum) void qe_init(uint qe_base) { - DECLARE_GLOBAL_DATA_PTR; - /* Init the QE IMMR base */ qe_immr = (qe_map_t *)qe_base; @@ -204,7 +202,6 @@ void qe_assign_page(uint snum, uint para_ram_base) int qe_set_brg(uint brg, uint rate) { - DECLARE_GLOBAL_DATA_PTR; volatile uint *bp; u32 divisor; int div16 = 0; diff --git a/drivers/usbdcore_mpc8xx.c b/drivers/usbdcore_mpc8xx.c index e87284b1787..d4c40965656 100644 --- a/drivers/usbdcore_mpc8xx.c +++ b/drivers/usbdcore_mpc8xx.c @@ -64,6 +64,8 @@ #include "usbdcore_mpc8xx.h" #include "usbdcore_ep0.h" +DECLARE_GLOBAL_DATA_PTR; + #define ERR(fmt, args...)\ serial_printf("ERROR : [%s] %s:%d: "fmt,\ __FILE__,__FUNCTION__,__LINE__, ##args) @@ -1216,7 +1218,6 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr, #elif defined(CFG_USB_BRGCLK) /* This has been tested with brgclk == 50MHz */ - DECLARE_GLOBAL_DATA_PTR; int divisor = 0; if (gd->cpu_clk < 48000000L) { diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index e1d8f74c5ec..75b153e4a85 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -183,10 +183,9 @@ #define CFG_LONGHELP 1 #define CFG_MEMTEST_START \ - ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; }) + ({ gd->bd->bi_dram[0].start; }) #define CFG_MEMTEST_END \ ({ \ - DECLARE_GLOBAL_DATA_PTR; \ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \ }) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index 36a969e7318..7c9990f8e0d 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -42,6 +42,8 @@ int post_flag; #endif +DECLARE_GLOBAL_DATA_PTR; + #ifndef CFG_NO_FLASH extern flash_info_t flash_info[]; #endif @@ -126,8 +128,6 @@ static void display_flash_config(ulong size) static int init_baudrate(void) { - DECLARE_GLOBAL_DATA_PTR; - char tmp[64]; int i = getenv_r("baudrate", tmp, sizeof(tmp)); gd->bd->bi_baudrate = gd->baudrate = (i > 0) @@ -139,7 +139,6 @@ static int init_baudrate(void) #ifdef DEBUG static void display_global_data(void) { - DECLARE_GLOBAL_DATA_PTR; bd_t *bd; bd = gd->bd; printf("--flags:%x\n", gd->flags); @@ -256,7 +255,6 @@ void init_cplbtables(void) void board_init_f(ulong bootflag) { - DECLARE_GLOBAL_DATA_PTR; ulong addr; bd_t *bd; int i; @@ -325,7 +323,6 @@ static int init_func_i2c(void) void board_init_r(gd_t * id, ulong dest_addr) { - DECLARE_GLOBAL_DATA_PTR; ulong size; extern void malloc_bin_reloc(void); char *s, *e; diff --git a/lib_blackfin/post.c b/lib_blackfin/post.c index 7c9478def5c..3c4d5c51dda 100644 --- a/lib_blackfin/post.c +++ b/lib_blackfin/post.c @@ -32,14 +32,14 @@ #ifdef CONFIG_POST +DECLARE_GLOBAL_DATA_PTR; + #define POST_MAX_NUMBER 32 #define BOOTMODE_MAGIC 0xDEAD0000 int post_init_f(void) { - DECLARE_GLOBAL_DATA_PTR; - int res = 0; unsigned int i; @@ -62,7 +62,6 @@ int post_init_f(void) void post_bootmode_init(void) { - DECLARE_GLOBAL_DATA_PTR; int bootmode = post_bootmode_get(0); int newword; @@ -109,20 +108,17 @@ int post_bootmode_get(unsigned int *last_test) /* POST tests run before relocation only mark status bits .... */ static void post_log_mark_start(unsigned long testid) { - DECLARE_GLOBAL_DATA_PTR; gd->post_log_word |= (testid) << 16; } static void post_log_mark_succ(unsigned long testid) { - DECLARE_GLOBAL_DATA_PTR; gd->post_log_word |= testid; } /* ... and the messages are output once we are relocated */ void post_output_backlog(void) { - DECLARE_GLOBAL_DATA_PTR; int j; for (j = 0; j < post_list_size; j++) { @@ -372,8 +368,6 @@ int post_log(char *format, ...) void post_reloc(void) { - DECLARE_GLOBAL_DATA_PTR; - unsigned int i; /* -- cgit v1.3.1 From 5bd7fe9aeb76906371f40b8fd07613f10922e3e7 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Tue, 11 Sep 2007 17:04:00 +0200 Subject: Fix do_div() usage in nand process output Fix usage of do_div() in nand erase|read|write process output. The last patch to nand_util.c introduced do_div() instead of libgcc's implementation. But do_div() returns the quotient in its first macro parameter and not as result. Signed-off-by: Matthias Fuchs --- common/cmd_nand.c | 2 +- drivers/nand/nand_util.c | 21 ++++++++++++++++----- 2 files changed, 17 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/common/cmd_nand.c b/common/cmd_nand.c index aeb76e5fb71..1fdd7a67f60 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -456,7 +456,7 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" "nand read[.jffs2] - addr off|partition size\n" - "nand write[.jffs2] - addr off|partiton size - read/write `size' bytes starting\n" + "nand write[.jffs2] - addr off|partition size - read/write `size' bytes starting\n" " at offset `off' to/from memory address `addr'\n" "nand erase [clean] [off size] - erase `size' bytes from\n" " offset `off' (entire device if not specified)\n" diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c index cf05043c0af..4fd4e166e6a 100644 --- a/drivers/nand/nand_util.c +++ b/drivers/nand/nand_util.c @@ -210,9 +210,12 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) if (!opts->quiet) { unsigned long long n =(unsigned long long) - (erase.addr+meminfo->erasesize-opts->offset) - * 100; - int percent = (int)do_div(n, erase_length); + (erase.addr + meminfo->erasesize - opts->offset) + * 100; + int percent; + + do_div(n, erase_length); + percent = (int)n; /* output progress message only at whole percent * steps to reduce the number of messages printed @@ -478,7 +481,11 @@ int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts) if (!opts->quiet) { unsigned long long n = (unsigned long long) (opts->length-imglen) * 100; - int percent = (int)do_div(n, opts->length); + int percent; + + do_div(n, opts->length); + percent = (int)n; + /* output progress message only at whole percent * steps to reduce the number of messages printed * on (slow) serial consoles @@ -653,7 +660,11 @@ int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts) if (!opts->quiet) { unsigned long long n = (unsigned long long) (opts->length-imglen) * 100; - int percent = (int)do_div(n ,opts->length); + int percent; + + do_div(n, opts->length); + percent = (int)n; + /* output progress message only at whole percent * steps to reduce the number of messages printed * on (slow) serial consoles -- cgit v1.3.1 From cd2d1602c54cc6957bdef3872272a4b264893960 Mon Sep 17 00:00:00 2001 From: "urwithsughosh@gmail.com" Date: Mon, 10 Sep 2007 14:54:56 -0400 Subject: Typo fix in tsec.c Fixup for the break statement in wrong place. [Patch by urwithsughosh@gmail.com] Acked-by: Andy Fleming Signed-off-by: Wolfgang Denk --- drivers/tsec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/tsec.c b/drivers/tsec.c index 6bca4dc0f33..4ff3339c7de 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -1262,10 +1262,10 @@ uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) case MIIM_LXT971_SR2_100HDX: priv->speed = 100; priv->duplexity = 0; + break; default: priv->speed = 100; priv->duplexity = 1; - break; } } else { priv->speed = 0; -- cgit v1.3.1 From 916527f4809a7bcd811f1f1daf34af184e31dd8c Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Mon, 10 Sep 2007 17:13:49 +0900 Subject: OneNAND support (take #2) [PATCH 1/3] OneNAND support (take #2) OneNAND support at U-Boot Signed-off-by: Kyungmin Park --- drivers/onenand/onenand_base.c | 1294 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1294 insertions(+) create mode 100644 drivers/onenand/onenand_base.c (limited to 'drivers') diff --git a/drivers/onenand/onenand_base.c b/drivers/onenand/onenand_base.c new file mode 100644 index 00000000000..7983a4a0d82 --- /dev/null +++ b/drivers/onenand/onenand_base.c @@ -0,0 +1,1294 @@ +/* + * linux/drivers/mtd/onenand/onenand_base.c + * + * Copyright (C) 2005-2007 Samsung Electronics + * Kyungmin Park + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#ifdef CONFIG_CMD_ONENAND + +#include +#include +#include + +#include +#include + +static const unsigned char ffchars[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */ +}; + +/** + * onenand_readw - [OneNAND Interface] Read OneNAND register + * @param addr address to read + * + * Read OneNAND register + */ +static unsigned short onenand_readw(void __iomem * addr) +{ + return readw(addr); +} + +/** + * onenand_writew - [OneNAND Interface] Write OneNAND register with value + * @param value value to write + * @param addr address to write + * + * Write OneNAND register with value + */ +static void onenand_writew(unsigned short value, void __iomem * addr) +{ + writew(value, addr); +} + +/** + * onenand_block_address - [DEFAULT] Get block address + * @param device the device id + * @param block the block + * @return translated block address if DDP, otherwise same + * + * Setup Start Address 1 Register (F100h) + */ +static int onenand_block_address(int device, int block) +{ + if (device & ONENAND_DEVICE_IS_DDP) { + /* Device Flash Core select, NAND Flash Block Address */ + int dfs = 0, density, mask; + + density = device >> ONENAND_DEVICE_DENSITY_SHIFT; + mask = (1 << (density + 6)); + + if (block & mask) + dfs = 1; + + return (dfs << ONENAND_DDP_SHIFT) | (block & (mask - 1)); + } + + return block; +} + +/** + * onenand_bufferram_address - [DEFAULT] Get bufferram address + * @param device the device id + * @param block the block + * @return set DBS value if DDP, otherwise 0 + * + * Setup Start Address 2 Register (F101h) for DDP + */ +static int onenand_bufferram_address(int device, int block) +{ + if (device & ONENAND_DEVICE_IS_DDP) { + /* Device BufferRAM Select */ + int dbs = 0, density, mask; + + density = device >> ONENAND_DEVICE_DENSITY_SHIFT; + mask = (1 << (density + 6)); + + if (block & mask) + dbs = 1; + + return (dbs << ONENAND_DDP_SHIFT); + } + + return 0; +} + +/** + * onenand_page_address - [DEFAULT] Get page address + * @param page the page address + * @param sector the sector address + * @return combined page and sector address + * + * Setup Start Address 8 Register (F107h) + */ +static int onenand_page_address(int page, int sector) +{ + /* Flash Page Address, Flash Sector Address */ + int fpa, fsa; + + fpa = page & ONENAND_FPA_MASK; + fsa = sector & ONENAND_FSA_MASK; + + return ((fpa << ONENAND_FPA_SHIFT) | fsa); +} + +/** + * onenand_buffer_address - [DEFAULT] Get buffer address + * @param dataram1 DataRAM index + * @param sectors the sector address + * @param count the number of sectors + * @return the start buffer value + * + * Setup Start Buffer Register (F200h) + */ +static int onenand_buffer_address(int dataram1, int sectors, int count) +{ + int bsa, bsc; + + /* BufferRAM Sector Address */ + bsa = sectors & ONENAND_BSA_MASK; + + if (dataram1) + bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */ + else + bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */ + + /* BufferRAM Sector Count */ + bsc = count & ONENAND_BSC_MASK; + + return ((bsa << ONENAND_BSA_SHIFT) | bsc); +} + +/** + * onenand_command - [DEFAULT] Send command to OneNAND device + * @param mtd MTD device structure + * @param cmd the command to be sent + * @param addr offset to read from or write to + * @param len number of bytes to read or write + * + * Send command to OneNAND device. This function is used for middle/large page + * devices (1KB/2KB Bytes per page) + */ +static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, + size_t len) +{ + struct onenand_chip *this = mtd->priv; + int value, readcmd = 0; + int block, page; + /* Now we use page size operation */ + int sectors = 4, count = 4; + + /* Address translation */ + switch (cmd) { + case ONENAND_CMD_UNLOCK: + case ONENAND_CMD_LOCK: + case ONENAND_CMD_LOCK_TIGHT: + block = -1; + page = -1; + break; + + case ONENAND_CMD_ERASE: + case ONENAND_CMD_BUFFERRAM: + block = (int)(addr >> this->erase_shift); + page = -1; + break; + + default: + block = (int)(addr >> this->erase_shift); + page = (int)(addr >> this->page_shift); + page &= this->page_mask; + break; + } + + /* NOTE: The setting order of the registers is very important! */ + if (cmd == ONENAND_CMD_BUFFERRAM) { + /* Select DataRAM for DDP */ + value = onenand_bufferram_address(this->device_id, block); + this->write_word(value, + this->base + ONENAND_REG_START_ADDRESS2); + + /* Switch to the next data buffer */ + ONENAND_SET_NEXT_BUFFERRAM(this); + + return 0; + } + + if (block != -1) { + /* Write 'DFS, FBA' of Flash */ + value = onenand_block_address(this->device_id, block); + this->write_word(value, + this->base + ONENAND_REG_START_ADDRESS1); + } + + if (page != -1) { + int dataram; + + switch (cmd) { + case ONENAND_CMD_READ: + case ONENAND_CMD_READOOB: + dataram = ONENAND_SET_NEXT_BUFFERRAM(this); + readcmd = 1; + break; + + default: + dataram = ONENAND_CURRENT_BUFFERRAM(this); + break; + } + + /* Write 'FPA, FSA' of Flash */ + value = onenand_page_address(page, sectors); + this->write_word(value, + this->base + ONENAND_REG_START_ADDRESS8); + + /* Write 'BSA, BSC' of DataRAM */ + value = onenand_buffer_address(dataram, sectors, count); + this->write_word(value, this->base + ONENAND_REG_START_BUFFER); + + if (readcmd) { + /* Select DataRAM for DDP */ + value = + onenand_bufferram_address(this->device_id, block); + this->write_word(value, + this->base + + ONENAND_REG_START_ADDRESS2); + } + } + + /* Interrupt clear */ + this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT); + /* Write command */ + this->write_word(cmd, this->base + ONENAND_REG_COMMAND); + + return 0; +} + +/** + * onenand_wait - [DEFAULT] wait until the command is done + * @param mtd MTD device structure + * @param state state to select the max. timeout value + * + * Wait for command done. This applies to all OneNAND command + * Read can take up to 30us, erase up to 2ms and program up to 350us + * according to general OneNAND specs + */ +static int onenand_wait(struct mtd_info *mtd, int state) +{ + struct onenand_chip *this = mtd->priv; + unsigned int flags = ONENAND_INT_MASTER; + unsigned int interrupt = 0; + unsigned int ctrl, ecc; + + while (1) { + interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); + if (interrupt & flags) + break; + } + + ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); + + if (ctrl & ONENAND_CTRL_ERROR) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_wait: controller error = 0x%04x\n", ctrl); + return -EAGAIN; + } + + if (ctrl & ONENAND_CTRL_LOCK) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_wait: it's locked error = 0x%04x\n", ctrl); + return -EIO; + } + + if (interrupt & ONENAND_INT_READ) { + ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); + if (ecc & ONENAND_ECC_2BIT_ALL) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_wait: ECC error = 0x%04x\n", ecc); + return -EBADMSG; + } + } + + return 0; +} + +/** + * onenand_bufferram_offset - [DEFAULT] BufferRAM offset + * @param mtd MTD data structure + * @param area BufferRAM area + * @return offset given area + * + * Return BufferRAM offset given area + */ +static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) +{ + struct onenand_chip *this = mtd->priv; + + if (ONENAND_CURRENT_BUFFERRAM(this)) { + if (area == ONENAND_DATARAM) + return mtd->oobblock; + if (area == ONENAND_SPARERAM) + return mtd->oobsize; + } + + return 0; +} + +/** + * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area + * @param mtd MTD data structure + * @param area BufferRAM area + * @param buffer the databuffer to put/get data + * @param offset offset to read from or write to + * @param count number of bytes to read/write + * + * Read the BufferRAM area + */ +static int onenand_read_bufferram(struct mtd_info *mtd, int area, + unsigned char *buffer, int offset, + size_t count) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *bufferram; + + bufferram = this->base + area; + bufferram += onenand_bufferram_offset(mtd, area); + + memcpy(buffer, bufferram + offset, count); + + return 0; +} + +/** + * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode + * @param mtd MTD data structure + * @param area BufferRAM area + * @param buffer the databuffer to put/get data + * @param offset offset to read from or write to + * @param count number of bytes to read/write + * + * Read the BufferRAM area with Sync. Burst Mode + */ +static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area, + unsigned char *buffer, int offset, + size_t count) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *bufferram; + + bufferram = this->base + area; + bufferram += onenand_bufferram_offset(mtd, area); + + this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ); + + memcpy(buffer, bufferram + offset, count); + + this->mmcontrol(mtd, 0); + + return 0; +} + +/** + * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area + * @param mtd MTD data structure + * @param area BufferRAM area + * @param buffer the databuffer to put/get data + * @param offset offset to read from or write to + * @param count number of bytes to read/write + * + * Write the BufferRAM area + */ +static int onenand_write_bufferram(struct mtd_info *mtd, int area, + const unsigned char *buffer, int offset, + size_t count) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *bufferram; + + bufferram = this->base + area; + bufferram += onenand_bufferram_offset(mtd, area); + + memcpy(bufferram + offset, buffer, count); + + return 0; +} + +/** + * onenand_check_bufferram - [GENERIC] Check BufferRAM information + * @param mtd MTD data structure + * @param addr address to check + * @return 1 if there are valid data, otherwise 0 + * + * Check bufferram if there is data we required + */ +static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) +{ + struct onenand_chip *this = mtd->priv; + int block, page; + int i; + + block = (int)(addr >> this->erase_shift); + page = (int)(addr >> this->page_shift); + page &= this->page_mask; + + i = ONENAND_CURRENT_BUFFERRAM(this); + + /* Is there valid data? */ + if (this->bufferram[i].block == block && + this->bufferram[i].page == page && this->bufferram[i].valid) + return 1; + + return 0; +} + +/** + * onenand_update_bufferram - [GENERIC] Update BufferRAM information + * @param mtd MTD data structure + * @param addr address to update + * @param valid valid flag + * + * Update BufferRAM information + */ +static int onenand_update_bufferram(struct mtd_info *mtd, loff_t addr, + int valid) +{ + struct onenand_chip *this = mtd->priv; + int block, page; + int i; + + block = (int)(addr >> this->erase_shift); + page = (int)(addr >> this->page_shift); + page &= this->page_mask; + + /* Invalidate BufferRAM */ + for (i = 0; i < MAX_BUFFERRAM; i++) { + if (this->bufferram[i].block == block && + this->bufferram[i].page == page) + this->bufferram[i].valid = 0; + } + + /* Update BufferRAM */ + i = ONENAND_CURRENT_BUFFERRAM(this); + this->bufferram[i].block = block; + this->bufferram[i].page = page; + this->bufferram[i].valid = valid; + + return 0; +} + +/** + * onenand_get_device - [GENERIC] Get chip for selected access + * @param mtd MTD device structure + * @param new_state the state which is requested + * + * Get the device and lock it for exclusive access + */ +static void onenand_get_device(struct mtd_info *mtd, int new_state) +{ + /* Do nothing */ +} + +/** + * onenand_release_device - [GENERIC] release chip + * @param mtd MTD device structure + * + * Deselect, release chip lock and wake up anyone waiting on the device + */ +static void onenand_release_device(struct mtd_info *mtd) +{ + /* Do nothing */ +} + +/** + * onenand_read_ecc - [MTD Interface] Read data with ECC + * @param mtd MTD device structure + * @param from offset to read from + * @param len number of bytes to read + * @param retlen pointer to variable to store the number of read bytes + * @param buf the databuffer to put data + * @param oob_buf filesystem supplied oob data buffer + * @param oobsel oob selection structure + * + * OneNAND read with ECC + */ +static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len, + size_t * retlen, u_char * buf, + u_char * oob_buf, struct nand_oobinfo *oobsel) +{ + struct onenand_chip *this = mtd->priv; + int read = 0, column; + int thislen; + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ecc: from = 0x%08x, len = %i\n", + (unsigned int)from, (int)len); + + /* Do not allow reads past end of device */ + if ((from + len) > mtd->size) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_read_ecc: Attempt read beyond end of device\n"); + *retlen = 0; + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + onenand_get_device(mtd, FL_READING); + + while (read < len) { + thislen = min_t(int, mtd->oobblock, len - read); + + column = from & (mtd->oobblock - 1); + if (column + thislen > mtd->oobblock) + thislen = mtd->oobblock - column; + + if (!onenand_check_bufferram(mtd, from)) { + this->command(mtd, ONENAND_CMD_READ, from, + mtd->oobblock); + ret = this->wait(mtd, FL_READING); + /* First copy data and check return value for ECC handling */ + onenand_update_bufferram(mtd, from, 1); + } + + this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, + thislen); + + read += thislen; + if (read == len) + break; + + if (ret) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_read_ecc: read failed = %d\n", ret); + break; + } + + from += thislen; + buf += thislen; + } + + /* Deselect and wake up anyone waiting on the device */ + onenand_release_device(mtd); + + /* + * Return success, if no ECC failures, else -EBADMSG + * fs driver will take care of that, because + * retlen == desired len and result == -EBADMSG + */ + *retlen = read; + return ret; +} + +/** + * onenand_read - [MTD Interface] MTD compability function for onenand_read_ecc + * @param mtd MTD device structure + * @param from offset to read from + * @param len number of bytes to read + * @param retlen pointer to variable to store the number of read bytes + * @param buf the databuffer to put data + * + * This function simply calls onenand_read_ecc with oob buffer and oobsel = NULL +*/ +int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, + size_t * retlen, u_char * buf) +{ + return onenand_read_ecc(mtd, from, len, retlen, buf, NULL, NULL); +} + +/** + * onenand_read_oob - [MTD Interface] OneNAND read out-of-band + * @param mtd MTD device structure + * @param from offset to read from + * @param len number of bytes to read + * @param retlen pointer to variable to store the number of read bytes + * @param buf the databuffer to put data + * + * OneNAND read out-of-band data from the spare area + */ +int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, + size_t * retlen, u_char * buf) +{ + struct onenand_chip *this = mtd->priv; + int read = 0, thislen, column; + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", + (unsigned int)from, (int)len); + + /* Initialize return length value */ + *retlen = 0; + + /* Do not allow reads past end of device */ + if (unlikely((from + len) > mtd->size)) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_read_oob: Attempt read beyond end of device\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + onenand_get_device(mtd, FL_READING); + + column = from & (mtd->oobsize - 1); + + while (read < len) { + thislen = mtd->oobsize - column; + thislen = min_t(int, thislen, len); + + this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); + + onenand_update_bufferram(mtd, from, 0); + + ret = this->wait(mtd, FL_READING); + /* First copy data and check return value for ECC handling */ + + this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, + thislen); + + read += thislen; + if (read == len) + break; + + if (ret) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_read_oob: read failed = %d\n", ret); + break; + } + + buf += thislen; + /* Read more? */ + if (read < len) { + /* Page size */ + from += mtd->oobblock; + column = 0; + } + } + + /* Deselect and wake up anyone waiting on the device */ + onenand_release_device(mtd); + + *retlen = read; + return ret; +} + +#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE +/** + * onenand_verify_page - [GENERIC] verify the chip contents after a write + * @param mtd MTD device structure + * @param buf the databuffer to verify + * @param block block address + * @param page page address + * + * Check DataRAM area directly + */ +static int onenand_verify_page(struct mtd_info *mtd, u_char * buf, + loff_t addr, int block, int page) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *dataram0, *dataram1; + int ret = 0; + + this->command(mtd, ONENAND_CMD_READ, addr, mtd->oobblock); + + ret = this->wait(mtd, FL_READING); + if (ret) + return ret; + + onenand_update_bufferram(mtd, addr, 1); + + /* Check, if the two dataram areas are same */ + dataram0 = this->base + ONENAND_DATARAM; + dataram1 = dataram0 + mtd->oobblock; + + if (memcmp(dataram0, dataram1, mtd->oobblock)) + return -EBADMSG; + + return 0; +} +#else +#define onenand_verify_page(...) (0) +#endif + +#define NOTALIGNED(x) ((x & (mtd->oobblock - 1)) != 0) + +/** + * onenand_write_ecc - [MTD Interface] OneNAND write with ECC + * @param mtd MTD device structure + * @param to offset to write to + * @param len number of bytes to write + * @param retlen pointer to variable to store the number of written bytes + * @param buf the data to write + * @param eccbuf filesystem supplied oob data buffer + * @param oobsel oob selection structure + * + * OneNAND write with ECC + */ +static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len, + size_t * retlen, const u_char * buf, + u_char * eccbuf, struct nand_oobinfo *oobsel) +{ + struct onenand_chip *this = mtd->priv; + int written = 0; + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ecc: to = 0x%08x, len = %i\n", + (unsigned int)to, (int)len); + + /* Initialize retlen, in case of early exit */ + *retlen = 0; + + /* Do not allow writes past end of device */ + if (unlikely((to + len) > mtd->size)) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_write_ecc: Attempt write to past end of device\n"); + return -EINVAL; + } + + /* Reject writes, which are not page aligned */ + if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_write_ecc: Attempt to write not page aligned data\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + onenand_get_device(mtd, FL_WRITING); + + /* Loop until all data write */ + while (written < len) { + int thislen = min_t(int, mtd->oobblock, len - written); + + this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobblock); + + this->write_bufferram(mtd, ONENAND_DATARAM, buf, 0, thislen); + this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, + mtd->oobsize); + + this->command(mtd, ONENAND_CMD_PROG, to, mtd->oobblock); + + onenand_update_bufferram(mtd, to, 1); + + ret = this->wait(mtd, FL_WRITING); + if (ret) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_write_ecc: write filaed %d\n", ret); + break; + } + + written += thislen; + + /* Only check verify write turn on */ + ret = onenand_verify_page(mtd, (u_char *) buf, to, block, page); + if (ret) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_write_ecc: verify failed %d\n", ret); + break; + } + + if (written == len) + break; + + to += thislen; + buf += thislen; + } + + /* Deselect and wake up anyone waiting on the device */ + onenand_release_device(mtd); + + *retlen = written; + + return ret; +} + +/** + * onenand_write - [MTD Interface] compability function for onenand_write_ecc + * @param mtd MTD device structure + * @param to offset to write to + * @param len number of bytes to write + * @param retlen pointer to variable to store the number of written bytes + * @param buf the data to write + * + * This function simply calls onenand_write_ecc + * with oob buffer and oobsel = NULL + */ +int onenand_write(struct mtd_info *mtd, loff_t to, size_t len, + size_t * retlen, const u_char * buf) +{ + return onenand_write_ecc(mtd, to, len, retlen, buf, NULL, NULL); +} + +/** + * onenand_write_oob - [MTD Interface] OneNAND write out-of-band + * @param mtd MTD device structure + * @param to offset to write to + * @param len number of bytes to write + * @param retlen pointer to variable to store the number of written bytes + * @param buf the data to write + * + * OneNAND write out-of-band + */ +int onenand_write_oob(struct mtd_info *mtd, loff_t to, size_t len, + size_t * retlen, const u_char * buf) +{ + struct onenand_chip *this = mtd->priv; + int column, status; + int written = 0; + + DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", + (unsigned int)to, (int)len); + + /* Initialize retlen, in case of early exit */ + *retlen = 0; + + /* Do not allow writes past end of device */ + if (unlikely((to + len) > mtd->size)) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_write_oob: Attempt write to past end of device\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + onenand_get_device(mtd, FL_WRITING); + + /* Loop until all data write */ + while (written < len) { + int thislen = min_t(int, mtd->oobsize, len - written); + + column = to & (mtd->oobsize - 1); + + this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize); + + this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, + mtd->oobsize); + this->write_bufferram(mtd, ONENAND_SPARERAM, buf, column, + thislen); + + this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); + + onenand_update_bufferram(mtd, to, 0); + + status = this->wait(mtd, FL_WRITING); + if (status) + break; + + written += thislen; + if (written == len) + break; + + to += thislen; + buf += thislen; + } + + /* Deselect and wake up anyone waiting on the device */ + onenand_release_device(mtd); + + *retlen = written; + + return 0; +} + +/** + * onenand_erase - [MTD Interface] erase block(s) + * @param mtd MTD device structure + * @param instr erase instruction + * + * Erase one ore more blocks + */ +int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) +{ + struct onenand_chip *this = mtd->priv; + unsigned int block_size; + loff_t addr; + int len; + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", + (unsigned int)instr->addr, (unsigned int)instr->len); + + block_size = (1 << this->erase_shift); + + /* Start address must align on block boundary */ + if (unlikely(instr->addr & (block_size - 1))) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n"); + return -EINVAL; + } + + /* Length must align on block boundary */ + if (unlikely(instr->len & (block_size - 1))) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_erase: Length not block aligned\n"); + return -EINVAL; + } + + /* Do not allow erase past end of device */ + if (unlikely((instr->len + instr->addr) > mtd->size)) { + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_erase: Erase past end of device\n"); + return -EINVAL; + } + + instr->fail_addr = 0xffffffff; + + /* Grab the lock and see if the device is available */ + onenand_get_device(mtd, FL_ERASING); + + /* Loop throught the pages */ + len = instr->len; + addr = instr->addr; + + instr->state = MTD_ERASING; + + while (len) { + + /* TODO Check badblock */ + + this->command(mtd, ONENAND_CMD_ERASE, addr, block_size); + + ret = this->wait(mtd, FL_ERASING); + /* Check, if it is write protected */ + if (ret) { + if (ret == -EPERM) + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_erase: Device is write protected!!!\n"); + else + DEBUG(MTD_DEBUG_LEVEL0, + "onenand_erase: Failed erase, block %d\n", + (unsigned)(addr >> this->erase_shift)); + instr->state = MTD_ERASE_FAILED; + instr->fail_addr = addr; + goto erase_exit; + } + + len -= block_size; + addr += block_size; + } + + instr->state = MTD_ERASE_DONE; + + erase_exit: + + ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; + /* Do call back function */ + if (!ret) + mtd_erase_callback(instr); + + /* Deselect and wake up anyone waiting on the device */ + onenand_release_device(mtd); + + return ret; +} + +/** + * onenand_sync - [MTD Interface] sync + * @param mtd MTD device structure + * + * Sync is actually a wait for chip ready function + */ +void onenand_sync(struct mtd_info *mtd) +{ + DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); + + /* Grab the lock and see if the device is available */ + onenand_get_device(mtd, FL_SYNCING); + + /* Release it and go back */ + onenand_release_device(mtd); +} + +/** + * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad + * @param mtd MTD device structure + * @param ofs offset relative to mtd start + */ +int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs) +{ + /* + * TODO + * 1. Bad block table (BBT) + * -> using NAND BBT to support JFFS2 + * 2. Bad block management (BBM) + * -> bad block replace scheme + * + * Currently we do nothing + */ + return 0; +} + +/** + * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad + * @param mtd MTD device structure + * @param ofs offset relative to mtd start + */ +int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs) +{ + /* see above */ + return 0; +} + +/** + * onenand_unlock - [MTD Interface] Unlock block(s) + * @param mtd MTD device structure + * @param ofs offset relative to mtd start + * @param len number of bytes to unlock + * + * Unlock one or more blocks + */ +int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) +{ + struct onenand_chip *this = mtd->priv; + int start, end, block, value, status; + + start = ofs >> this->erase_shift; + end = len >> this->erase_shift; + + /* Continuous lock scheme */ + if (this->options & ONENAND_CONT_LOCK) { + /* Set start block address */ + this->write_word(start, + this->base + ONENAND_REG_START_BLOCK_ADDRESS); + /* Set end block address */ + this->write_word(end - 1, + this->base + ONENAND_REG_END_BLOCK_ADDRESS); + /* Write unlock command */ + this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0); + + /* There's no return value */ + this->wait(mtd, FL_UNLOCKING); + + /* Sanity check */ + while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) + & ONENAND_CTRL_ONGO) + continue; + + /* Check lock status */ + status = this->read_word(this->base + ONENAND_REG_WP_STATUS); + if (!(status & ONENAND_WP_US)) + printk(KERN_ERR "wp status = 0x%x\n", status); + + return 0; + } + + /* Block lock scheme */ + for (block = start; block < end; block++) { + /* Set start block address */ + this->write_word(block, + this->base + ONENAND_REG_START_BLOCK_ADDRESS); + /* Write unlock command */ + this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0); + + /* There's no return value */ + this->wait(mtd, FL_UNLOCKING); + + /* Sanity check */ + while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) + & ONENAND_CTRL_ONGO) + continue; + + /* Set block address for read block status */ + value = onenand_block_address(this->device_id, block); + this->write_word(value, + this->base + ONENAND_REG_START_ADDRESS1); + + /* Check lock status */ + status = this->read_word(this->base + ONENAND_REG_WP_STATUS); + if (!(status & ONENAND_WP_US)) + printk(KERN_ERR "block = %d, wp status = 0x%x\n", + block, status); + } + + return 0; +} + +/** + * onenand_print_device_info - Print device ID + * @param device device ID + * + * Print device ID + */ +void onenand_print_device_info(int device, int verbose) +{ + int vcc, demuxed, ddp, density; + + if (!verbose) + return; + + vcc = device & ONENAND_DEVICE_VCC_MASK; + demuxed = device & ONENAND_DEVICE_IS_DEMUX; + ddp = device & ONENAND_DEVICE_IS_DDP; + density = device >> ONENAND_DEVICE_DENSITY_SHIFT; + printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n", + demuxed ? "" : "Muxed ", + ddp ? "(DDP)" : "", + (16 << density), vcc ? "2.65/3.3" : "1.8", device); +} + +static const struct onenand_manufacturers onenand_manuf_ids[] = { + {ONENAND_MFR_SAMSUNG, "Samsung"}, + {ONENAND_MFR_UNKNOWN, "Unknown"} +}; + +/** + * onenand_check_maf - Check manufacturer ID + * @param manuf manufacturer ID + * + * Check manufacturer ID + */ +static int onenand_check_maf(int manuf) +{ + int i; + + for (i = 0; onenand_manuf_ids[i].id; i++) { + if (manuf == onenand_manuf_ids[i].id) + break; + } + +#ifdef ONENAND_DEBUG + printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", + onenand_manuf_ids[i].name, manuf); +#endif + + return (i != ONENAND_MFR_UNKNOWN); +} + +/** + * onenand_probe - [OneNAND Interface] Probe the OneNAND device + * @param mtd MTD device structure + * + * OneNAND detection method: + * Compare the the values from command with ones from register + */ +static int onenand_probe(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + int bram_maf_id, bram_dev_id, maf_id, dev_id; + int version_id; + int density; + + /* Send the command for reading device ID from BootRAM */ + this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM); + + /* Read manufacturer and device IDs from BootRAM */ + bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0); + bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2); + + /* Check manufacturer ID */ + if (onenand_check_maf(bram_maf_id)) + return -ENXIO; + + /* Reset OneNAND to read default register values */ + this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM); + + { + int i; + for (i = 0; i < 10000; i++) ; + } + + /* Read manufacturer and device IDs from Register */ + maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID); + dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID); + + /* Check OneNAND device */ + if (maf_id != bram_maf_id || dev_id != bram_dev_id) + return -ENXIO; + + /* Flash device information */ + onenand_print_device_info(dev_id, 0); + this->device_id = dev_id; + + density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; + this->chipsize = (16 << density) << 20; + + /* OneNAND page size & block size */ + /* The data buffer size is equal to page size */ + mtd->oobblock = + this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE); + mtd->oobsize = mtd->oobblock >> 5; + /* Pagers per block is always 64 in OneNAND */ + mtd->erasesize = mtd->oobblock << 6; + + this->erase_shift = ffs(mtd->erasesize) - 1; + this->page_shift = ffs(mtd->oobblock) - 1; + this->ppb_shift = (this->erase_shift - this->page_shift); + this->page_mask = (mtd->erasesize / mtd->oobblock) - 1; + + /* REVIST: Multichip handling */ + + mtd->size = this->chipsize; + + /* Version ID */ + version_id = this->read_word(this->base + ONENAND_REG_VERSION_ID); +#ifdef ONENAND_DEBUG + printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version_id); +#endif + + /* Lock scheme */ + if (density <= ONENAND_DEVICE_DENSITY_512Mb && + !(version_id >> ONENAND_VERSION_PROCESS_SHIFT)) { + printk(KERN_INFO "Lock scheme is Continues Lock\n"); + this->options |= ONENAND_CONT_LOCK; + } + + return 0; +} + +/** + * onenand_scan - [OneNAND Interface] Scan for the OneNAND device + * @param mtd MTD device structure + * @param maxchips Number of chips to scan for + * + * This fills out all the not initialized function pointers + * with the defaults. + * The flash ID is read and the mtd/chip structures are + * filled with the appropriate values. + */ +int onenand_scan(struct mtd_info *mtd, int maxchips) +{ + struct onenand_chip *this = mtd->priv; + + if (!this->read_word) + this->read_word = onenand_readw; + if (!this->write_word) + this->write_word = onenand_writew; + + if (!this->command) + this->command = onenand_command; + if (!this->wait) + this->wait = onenand_wait; + + if (!this->read_bufferram) + this->read_bufferram = onenand_read_bufferram; + if (!this->write_bufferram) + this->write_bufferram = onenand_write_bufferram; + + if (onenand_probe(mtd)) + return -ENXIO; + + /* Set Sync. Burst Read after probing */ + if (this->mmcontrol) { + printk(KERN_INFO "OneNAND Sync. Burst Read support\n"); + this->read_bufferram = onenand_sync_read_bufferram; + } + + onenand_unlock(mtd, 0, mtd->size); + + return onenand_default_bbt(mtd); +} + +/** + * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device + * @param mtd MTD device structure + */ +void onenand_release(struct mtd_info *mtd) +{ +} + +/* + * OneNAND initialization at U-Boot + */ +struct mtd_info onenand_mtd; +struct onenand_chip onenand_chip; + +void onenand_init(void) +{ + memset(&onenand_mtd, 0, sizeof(struct mtd_info)); + memset(&onenand_chip, 0, sizeof(struct onenand_chip)); + + onenand_chip.base = (void *)CFG_ONENAND_BASE; + onenand_mtd.priv = &onenand_chip; + + onenand_scan(&onenand_mtd, 1); + + puts("OneNAND: "); + print_size(onenand_mtd.size, "\n"); +} + +#endif /* CONFIG_CMD_ONENAND */ -- cgit v1.3.1 From 17aa2800457df0c06b41516f46f126712c196219 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Mon, 10 Sep 2007 17:14:34 +0900 Subject: OneNAND support (take #2) [PATCH 2/3] OneNAND support (take #2) OneNAND support at U-Boot Signed-off-by: Kyungmin Park --- drivers/onenand/Makefile | 44 +++++++ drivers/onenand/onenand_bbt.c | 265 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 309 insertions(+) create mode 100644 drivers/onenand/Makefile create mode 100644 drivers/onenand/onenand_bbt.c (limited to 'drivers') diff --git a/drivers/onenand/Makefile b/drivers/onenand/Makefile new file mode 100644 index 00000000000..5d7a471d837 --- /dev/null +++ b/drivers/onenand/Makefile @@ -0,0 +1,44 @@ +# +# Copyright (C) 2005-2007 Samsung Electronics. +# Kyungmin Park +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libonenand.a + +COBJS := onenand_base.o onenand_bbt.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/onenand/onenand_bbt.c b/drivers/onenand/onenand_bbt.c new file mode 100644 index 00000000000..5a610ee5ea8 --- /dev/null +++ b/drivers/onenand/onenand_bbt.c @@ -0,0 +1,265 @@ +/* + * linux/drivers/mtd/onenand/onenand_bbt.c + * + * Bad Block Table support for the OneNAND driver + * + * Copyright(c) 2005-2007 Samsung Electronics + * Kyungmin Park + * + * TODO: + * Split BBT core and chip specific BBT. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#ifdef CONFIG_CMD_ONENAND + +#include +#include +#include +#include + +#include + +/** + * check_short_pattern - [GENERIC] check if a pattern is in the buffer + * @param buf the buffer to search + * @param len the length of buffer to search + * @param paglen the pagelength + * @param td search pattern descriptor + * + * Check for a pattern at the given place. Used to search bad block + * tables and good / bad block identifiers. Same as check_pattern, but + * no optional empty check and the pattern is expected to start + * at offset 0. + */ +static int check_short_pattern(uint8_t * buf, int len, int paglen, + struct nand_bbt_descr *td) +{ + int i; + uint8_t *p = buf; + + /* Compare the pattern */ + for (i = 0; i < td->len; i++) { + if (p[i] != td->pattern[i]) + return -1; + } + return 0; +} + +/** + * create_bbt - [GENERIC] Create a bad block table by scanning the device + * @param mtd MTD device structure + * @param buf temporary buffer + * @param bd descriptor for the good/bad block search pattern + * @param chip create the table for a specific chip, -1 read all chips. + * Applies only if NAND_BBT_PERCHIP option is set + * + * Create a bad block table by scanning the device + * for the given good/bad block identify pattern + */ +static int create_bbt(struct mtd_info *mtd, uint8_t * buf, + struct nand_bbt_descr *bd, int chip) +{ + struct onenand_chip *this = mtd->priv; + struct bbm_info *bbm = this->bbm; + int i, j, numblocks, len, scanlen; + int startblock; + loff_t from; + size_t readlen, ooblen; + + printk(KERN_INFO "Scanning device for bad blocks\n"); + + len = 1; + + /* We need only read few bytes from the OOB area */ + scanlen = ooblen = 0; + readlen = bd->len; + + /* chip == -1 case only */ + /* Note that numblocks is 2 * (real numblocks) here; + * see i += 2 below as it makses shifting and masking less painful + */ + numblocks = mtd->size >> (bbm->bbt_erase_shift - 1); + startblock = 0; + from = 0; + + for (i = startblock; i < numblocks;) { + int ret; + + for (j = 0; j < len; j++) { + size_t retlen; + + /* No need to read pages fully, + * just read required OOB bytes */ + ret = onenand_read_oob(mtd, + from + j * mtd->oobblock + + bd->offs, readlen, &retlen, + &buf[0]); + + if (ret && ret != -EAGAIN) { + printk("ret = %d\n", ret); + return ret; + } + + if (check_short_pattern + (&buf[j * scanlen], scanlen, mtd->oobblock, bd)) { + bbm->bbt[i >> 3] |= 0x03 << (i & 0x6); + printk(KERN_WARNING + "Bad eraseblock %d at 0x%08x\n", i >> 1, + (unsigned int)from); + break; + } + } + i += 2; + from += (1 << bbm->bbt_erase_shift); + } + + return 0; +} + +/** + * onenand_memory_bbt - [GENERIC] create a memory based bad block table + * @param mtd MTD device structure + * @param bd descriptor for the good/bad block search pattern + * + * The function creates a memory based bbt by scanning the device + * for manufacturer / software marked good / bad blocks + */ +static inline int onenand_memory_bbt(struct mtd_info *mtd, + struct nand_bbt_descr *bd) +{ + unsigned char data_buf[MAX_ONENAND_PAGESIZE]; + + bd->options &= ~NAND_BBT_SCANEMPTY; + return create_bbt(mtd, data_buf, bd, -1); +} + +/** + * onenand_isbad_bbt - [OneNAND Interface] Check if a block is bad + * @param mtd MTD device structure + * @param offs offset in the device + * @param allowbbt allow access to bad block table region + */ +static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) +{ + struct onenand_chip *this = mtd->priv; + struct bbm_info *bbm = this->bbm; + int block; + uint8_t res; + + /* Get block number * 2 */ + block = (int)(offs >> (bbm->bbt_erase_shift - 1)); + res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03; + + DEBUG(MTD_DEBUG_LEVEL2, + "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n", + (unsigned int)offs, block >> 1, res); + + switch ((int)res) { + case 0x00: + return 0; + case 0x01: + return 1; + case 0x02: + return allowbbt ? 0 : 1; + } + + return 1; +} + +/** + * onenand_scan_bbt - [OneNAND Interface] scan, find, read and maybe create bad block table(s) + * @param mtd MTD device structure + * @param bd descriptor for the good/bad block search pattern + * + * The function checks, if a bad block table(s) is/are already + * available. If not it scans the device for manufacturer + * marked good / bad blocks and writes the bad block table(s) to + * the selected place. + * + * The bad block table memory is allocated here. It must be freed + * by calling the onenand_free_bbt function. + * + */ +int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) +{ + struct onenand_chip *this = mtd->priv; + struct bbm_info *bbm = this->bbm; + int len, ret = 0; + + len = mtd->size >> (this->erase_shift + 2); + /* Allocate memory (2bit per block) */ + bbm->bbt = malloc(len); + if (!bbm->bbt) { + printk(KERN_ERR "onenand_scan_bbt: Out of memory\n"); + return -ENOMEM; + } + /* Clear the memory bad block table */ + memset(bbm->bbt, 0x00, len); + + /* Set the bad block position */ + bbm->badblockpos = ONENAND_BADBLOCK_POS; + + /* Set erase shift */ + bbm->bbt_erase_shift = this->erase_shift; + + if (!bbm->isbad_bbt) + bbm->isbad_bbt = onenand_isbad_bbt; + + /* Scan the device to build a memory based bad block table */ + if ((ret = onenand_memory_bbt(mtd, bd))) { + printk(KERN_ERR + "onenand_scan_bbt: Can't scan flash and build the RAM-based BBT\n"); + free(bbm->bbt); + bbm->bbt = NULL; + } + + return ret; +} + +/* + * Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks. + */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr largepage_memorybased = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern, +}; + +/** + * onenand_default_bbt - [OneNAND Interface] Select a default bad block table for the device + * @param mtd MTD device structure + * + * This function selects the default bad block table + * support for the device and calls the onenand_scan_bbt function + */ +int onenand_default_bbt(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + struct bbm_info *bbm; + + this->bbm = malloc(sizeof(struct bbm_info)); + if (!this->bbm) + return -ENOMEM; + + bbm = this->bbm; + + memset(bbm, 0, sizeof(struct bbm_info)); + + /* 1KB page has same configuration as 2KB page */ + if (!bbm->badblock_pattern) + bbm->badblock_pattern = &largepage_memorybased; + + return onenand_scan_bbt(mtd, bbm->badblock_pattern); +} + +#endif /* CFG_CMD_ONENAND */ -- cgit v1.3.1 From 30363e98fa470fbecea5e8bc0f1443352754f303 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 17 Sep 2007 08:20:47 +0200 Subject: Small whitespace cleanup of OneNAND patch Signed-off-by: Stefan Roese --- drivers/onenand/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/onenand/Makefile b/drivers/onenand/Makefile index 5d7a471d837..20494133270 100644 --- a/drivers/onenand/Makefile +++ b/drivers/onenand/Makefile @@ -1,6 +1,6 @@ # -# Copyright (C) 2005-2007 Samsung Electronics. -# Kyungmin Park +# Copyright (C) 2005-2007 Samsung Electronics. +# Kyungmin Park # # See file CREDITS for list of people who contributed to this # project. -- cgit v1.3.1 From 97213f32416ead885deafea86774e912ffd60ad0 Mon Sep 17 00:00:00 2001 From: David Saada Date: Mon, 17 Sep 2007 17:04:47 +0200 Subject: Description: Add NEC's PCI OHCI module ID to the USB OHCI driver Signed-off-by: David Saada --- drivers/usb_ohci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index d6b745fadd6..388827fd001 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -93,6 +93,7 @@ #ifdef CONFIG_PCI_OHCI static struct pci_device_id ohci_pci_ids[] = { {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ + {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ /* Please add supported PCI OHCI controller ids here */ {0, 0} }; -- cgit v1.3.1 From bd86220f58b99d6896198c385fda132f0c980915 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 18 Sep 2007 13:07:54 +0100 Subject: Move coloured led API to status_led.h Improve indentation in drivers/at45.c --- cpu/arm920t/start.S | 2 +- drivers/at45.c | 180 +++++++++++++++++++++-------------------- include/asm-arm/coloured_led.h | 45 ----------- include/status_led.h | 21 +++++ 4 files changed, 114 insertions(+), 134 deletions(-) mode change 100755 => 100644 drivers/at45.c delete mode 100644 include/asm-arm/coloured_led.h (limited to 'drivers') diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index df2ee20cbe9..aefcdd1552f 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -27,7 +27,7 @@ #include #include -#include +#include /* ************************************************************************* diff --git a/drivers/at45.c b/drivers/at45.c old mode 100755 new mode 100644 index f48d31776f2..a075ebd5d74 --- a/drivers/at45.c +++ b/drivers/at45.c @@ -48,28 +48,27 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand(AT91PS_DataFlash pDataFlash, /* process the address to obtain page address and byte address */ adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << - pDataFlash->pDevice->page_offset) + (DataflashAddress % - (pDataFlash->pDevice-> - pages_size)); + pDataFlash->pDevice->page_offset) + + (DataflashAddress % (pDataFlash->pDevice->pages_size)); - /* fill the command buffer */ + /* fill the command buffer */ pDataFlash->pDataFlashDesc->command[0] = OpCode; if (pDataFlash->pDevice->pages_number >= 16384) { pDataFlash->pDataFlashDesc->command[1] = - (unsigned char)((adr & 0x0F000000) >> 24); + (unsigned char)((adr & 0x0F000000) >> 24); pDataFlash->pDataFlashDesc->command[2] = - (unsigned char)((adr & 0x00FF0000) >> 16); + (unsigned char)((adr & 0x00FF0000) >> 16); pDataFlash->pDataFlashDesc->command[3] = - (unsigned char)((adr & 0x0000FF00) >> 8); + (unsigned char)((adr & 0x0000FF00) >> 8); pDataFlash->pDataFlashDesc->command[4] = - (unsigned char)(adr & 0x000000FF); + (unsigned char)(adr & 0x000000FF); } else { pDataFlash->pDataFlashDesc->command[1] = - (unsigned char)((adr & 0x00FF0000) >> 16); + (unsigned char)((adr & 0x00FF0000) >> 16); pDataFlash->pDataFlashDesc->command[2] = - (unsigned char)((adr & 0x0000FF00) >> 8); + (unsigned char)((adr & 0x0000FF00) >> 8); pDataFlash->pDataFlashDesc->command[3] = - (unsigned char)(adr & 0x000000FF); + (unsigned char)(adr & 0x000000FF); pDataFlash->pDataFlashDesc->command[4] = 0; } pDataFlash->pDataFlashDesc->command[5] = 0; @@ -78,10 +77,10 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand(AT91PS_DataFlash pDataFlash, /* Initialize the SpiData structure for the spi write fuction */ pDataFlash->pDataFlashDesc->tx_cmd_pt = - pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize; pDataFlash->pDataFlashDesc->rx_cmd_pt = - pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize; /* send the command and read the data */ @@ -123,8 +122,8 @@ AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) /* \brief wait for dataflash ready (bit7 of the status register == 1) */ /*----------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc - pDataFlashDesc, - unsigned int timeout) + pDataFlashDesc, + unsigned int timeout) { pDataFlashDesc->DataFlash_state = IDLE; @@ -149,16 +148,17 @@ AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc /* : = data buffer size */ /* Return value : State of the dataflash */ /*--------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashContinuousRead(AT91PS_DataFlash pDataFlash, - int src, - unsigned char *dataBuffer, - int sizeToRead) +AT91S_DataFlashStatus AT91F_DataFlashContinuousRead( + AT91PS_DataFlash pDataFlash, + int src, + unsigned char *dataBuffer, + int sizeToRead) { AT91S_DataFlashStatus status; /* Test the size to read in the device */ if ((src + sizeToRead) > - (pDataFlash->pDevice->pages_size * - (pDataFlash->pDevice->pages_number))) + (pDataFlash->pDevice->pages_size * + (pDataFlash->pDevice->pages_number))) return DATAFLASH_MEMORY_OVERFLOW; pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; @@ -166,8 +166,8 @@ AT91S_DataFlashStatus AT91F_DataFlashContinuousRead(AT91PS_DataFlash pDataFlash, pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; - status = AT91F_DataFlashSendCommand - (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); + status = AT91F_DataFlashSendCommand( + pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); /* Send the command to the dataflash */ return (status); } @@ -196,8 +196,8 @@ AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(AT91PS_DataFlash pDataFlash, /* Send the command to the dataflash */ if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return (AT91F_DataFlashSendCommand(pDataFlash, DB_PAGE_PGM_BUF1, - cmdsize, dest)); + return (AT91F_DataFlashSendCommand( + pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); } /*---------------------------------------------------------------------------*/ @@ -208,16 +208,17 @@ AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(AT91PS_DataFlash pDataFlash, /* : */ /* Return value : State of the dataflash */ /*---------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(AT91PS_DataFlash - pDataFlash, - unsigned char - BufferCommand, - unsigned int page) +AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( + AT91PS_DataFlash + pDataFlash, + unsigned char + BufferCommand, + unsigned int page) { int cmdsize; /* Test if the buffer command is legal */ - if ((BufferCommand != DB_PAGE_2_BUF1_TRF) - && (BufferCommand != DB_PAGE_2_BUF2_TRF)) + if ((BufferCommand != DB_PAGE_2_BUF1_TRF)&& + (BufferCommand != DB_PAGE_2_BUF2_TRF)) return DATAFLASH_BAD_COMMAND; /* no data to transmit or receive */ @@ -225,9 +226,9 @@ AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(AT91PS_DataFlash cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return (AT91F_DataFlashSendCommand(pDataFlash, BufferCommand, cmdsize, - page * - pDataFlash->pDevice->pages_size)); + return (AT91F_DataFlashSendCommand( + pDataFlash, BufferCommand, cmdsize, + page * pDataFlash->pDevice->pages_size)); } /*-------------------------------------------------------------------------- */ @@ -240,16 +241,17 @@ AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(AT91PS_DataFlash /* : = data buffer size */ /* Return value : State of the dataflash */ /*---------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer(AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned char *dataBuffer, - unsigned int bufferAddress, - int SizeToWrite) +AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned char *dataBuffer, + unsigned int bufferAddress, + int SizeToWrite) { int cmdsize; /* Test if the buffer command is legal */ - if ((BufferCommand != DB_BUF1_WRITE) - && (BufferCommand != DB_BUF2_WRITE)) + if ((BufferCommand != DB_BUF1_WRITE) && + (BufferCommand != DB_BUF2_WRITE)) return DATAFLASH_BAD_COMMAND; /* buffer address must be lower than page size */ @@ -265,28 +267,28 @@ AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer(AT91PS_DataFlash pDataFlash, if (pDataFlash->pDevice->pages_number >= 16384) { pDataFlash->pDataFlashDesc->command[2] = 0; pDataFlash->pDataFlashDesc->command[3] = - (unsigned char)(((unsigned int)(bufferAddress & - pDataFlash->pDevice-> - byte_mask)) >> 8); + (unsigned char)(((unsigned int)(bufferAddress & + pDataFlash->pDevice-> + byte_mask)) >> 8); pDataFlash->pDataFlashDesc->command[4] = - (unsigned char)((unsigned int)bufferAddress & 0x00FF); + (unsigned char)((unsigned int)bufferAddress & 0x00FF); cmdsize = 5; } else { pDataFlash->pDataFlashDesc->command[2] = - (unsigned char)(((unsigned int)(bufferAddress & - pDataFlash->pDevice-> - byte_mask)) >> 8); + (unsigned char)(((unsigned int)(bufferAddress & + pDataFlash->pDevice-> + byte_mask)) >> 8); pDataFlash->pDataFlashDesc->command[3] = - (unsigned char)((unsigned int)bufferAddress & 0x00FF); + (unsigned char)((unsigned int)bufferAddress & 0x00FF); pDataFlash->pDataFlashDesc->command[4] = 0; cmdsize = 4; } pDataFlash->pDataFlashDesc->tx_cmd_pt = - pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize; pDataFlash->pDataFlashDesc->rx_cmd_pt = - pDataFlash->pDataFlashDesc->command; + pDataFlash->pDataFlashDesc->command; pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize; pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; @@ -305,8 +307,9 @@ AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer(AT91PS_DataFlash pDataFlash, /* : */ /* Return value : State of the dataflash */ /*---------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PageErase(AT91PS_DataFlash pDataFlash, - unsigned int page) +AT91S_DataFlashStatus AT91F_PageErase( + AT91PS_DataFlash pDataFlash, + unsigned int page) { int cmdsize; /* Test if the buffer command is legal */ @@ -316,9 +319,9 @@ AT91S_DataFlashStatus AT91F_PageErase(AT91PS_DataFlash pDataFlash, cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return (AT91F_DataFlashSendCommand(pDataFlash, DB_PAGE_ERASE, cmdsize, - page * - pDataFlash->pDevice->pages_size)); + return (AT91F_DataFlashSendCommand(pDataFlash, + DB_PAGE_ERASE, cmdsize, + page * pDataFlash->pDevice->pages_size)); } /*---------------------------------------------------------------------------*/ @@ -329,8 +332,9 @@ AT91S_DataFlashStatus AT91F_PageErase(AT91PS_DataFlash pDataFlash, /* : */ /* Return value : State of the dataflash */ /*---------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_BlockErase(AT91PS_DataFlash pDataFlash, - unsigned int block) +AT91S_DataFlashStatus AT91F_BlockErase( + AT91PS_DataFlash pDataFlash, + unsigned int block) { int cmdsize; /* Test if the buffer command is legal */ @@ -340,8 +344,8 @@ AT91S_DataFlashStatus AT91F_BlockErase(AT91PS_DataFlash pDataFlash, if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; return (AT91F_DataFlashSendCommand(pDataFlash, DB_BLOCK_ERASE, cmdsize, - block * 8 * - pDataFlash->pDevice->pages_size)); + block * 8 * + pDataFlash->pDevice->pages_size)); } /*---------------------------------------------------------------------------*/ @@ -353,15 +357,15 @@ AT91S_DataFlashStatus AT91F_BlockErase(AT91PS_DataFlash pDataFlash, /* Return value : State of the dataflash */ /*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_WriteBufferToMain(AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int dest) + unsigned char BufferCommand, + unsigned int dest) { int cmdsize; /* Test if the buffer command is correct */ if ((BufferCommand != DB_BUF1_PAGE_PGM) && - (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && - (BufferCommand != DB_BUF2_PAGE_PGM) && - (BufferCommand != DB_BUF2_PAGE_ERASE_PGM)) + (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && + (BufferCommand != DB_BUF2_PAGE_PGM) && + (BufferCommand != DB_BUF2_PAGE_ERASE_PGM)) return DATAFLASH_BAD_COMMAND; /* no data to transmit or receive */ @@ -371,8 +375,8 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain(AT91PS_DataFlash pDataFlash, if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; /* Send the command to the dataflash */ - return (AT91F_DataFlashSendCommand(pDataFlash, BufferCommand, cmdsize, - dest)); + return (AT91F_DataFlashSendCommand(pDataFlash, BufferCommand, + cmdsize, dest)); } /*---------------------------------------------------------------------------*/ @@ -383,9 +387,9 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain(AT91PS_DataFlash pDataFlash, /* : = Number of bytes to erase */ /*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_PartialPageWrite(AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int size) + unsigned char *src, + unsigned int dest, + unsigned int size) { unsigned int page; unsigned int AdrInPage; @@ -399,10 +403,10 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite(AT91PS_DataFlash pDataFlash, AT91C_TIMEOUT_WRDY); /*Update the SRAM buffer */ AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, - AdrInPage, size); + AdrInPage, size); AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY); + AT91C_TIMEOUT_WRDY); /* Erase page if a 128 Mbits device */ if (pDataFlash->pDevice->pages_number >= 16384) { @@ -426,8 +430,8 @@ AT91S_DataFlashStatus AT91F_PartialPageWrite(AT91PS_DataFlash pDataFlash, /* : = data buffer size */ /*---------------------------------------------------------------------------*/ AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, int size) + unsigned char *src, + int dest, int size) { unsigned int length; unsigned int page; @@ -436,14 +440,14 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash pDataFlash, AT91F_SpiEnable(pDataFlash->pDevice->cs); if ((dest + size) > (pDataFlash->pDevice->pages_size * - (pDataFlash->pDevice->pages_number))) + (pDataFlash->pDevice->pages_number))) return DATAFLASH_MEMORY_OVERFLOW; /* If destination does not fit a page start address */ if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0) { - length = pDataFlash->pDevice->pages_size - - (dest % ((unsigned int) - (pDataFlash->pDevice->pages_size))); + length = + pDataFlash->pDevice->pages_size - + (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); if (size < length) length = size; @@ -465,9 +469,9 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash pDataFlash, page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); status = AT91F_DataFlashWriteBuffer(pDataFlash, - DB_BUF1_WRITE, src, 0, - pDataFlash->pDevice-> - pages_size); + DB_BUF1_WRITE, src, 0, + pDataFlash->pDevice-> + pages_size); AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); @@ -478,7 +482,7 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash pDataFlash, return DATAFLASH_ERROR; status = AT91F_WriteBufferToMain(pDataFlash, - DB_BUF1_PAGE_PGM, dest); + DB_BUF1_PAGE_PGM, dest); if (!status) return DATAFLASH_ERROR; @@ -517,20 +521,20 @@ int AT91F_DataFlashRead(AT91PS_DataFlash pDataFlash, AT91F_SpiEnable(pDataFlash->pDevice->cs); if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) return -1; while (size) { SizeToRead = (size < 0x8000) ? size : 0x8000; if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, - AT91C_TIMEOUT_WRDY) != - DATAFLASH_OK) + AT91C_TIMEOUT_WRDY) != + DATAFLASH_OK) return -1; if (AT91F_DataFlashContinuousRead(pDataFlash, addr, - (uchar *) buffer, - SizeToRead) != DATAFLASH_OK) + (uchar *) buffer, + SizeToRead) != DATAFLASH_OK) return -1; size -= SizeToRead; diff --git a/include/asm-arm/coloured_led.h b/include/asm-arm/coloured_led.h deleted file mode 100644 index f78a4b10041..00000000000 --- a/include/asm-arm/coloured_led.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * (C) Copyright 2006 - * Atmel Nordic AB - * Ulf Samuelsson - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __LED_H -#define __LED_H - -#ifndef __ASSEMBLY__ -extern void coloured_LED_init (void); -extern void red_LED_on(void); -extern void red_LED_off(void); -extern void green_LED_on(void); -extern void green_LED_off(void); -extern void yellow_LED_on(void); -extern void yellow_LED_off(void); -#else - .extern LED_init - .extern red_LED_on - .extern red_LED_off - .extern yellow_LED_on - .extern yellow_LED_off - .extern green_LED_on - .extern green_LED_off -#endif -#endif diff --git a/include/status_led.h b/include/status_led.h index a6468142557..74e2147cf92 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -383,6 +383,27 @@ extern void __led_set (led_id_t mask, int state); # include #endif +/* + * Coloured LEDs API + */ +#ifndef __ASSEMBLY__ +extern void coloured_LED_init (void); +extern void red_LED_on(void); +extern void red_LED_off(void); +extern void green_LED_on(void); +extern void green_LED_off(void); +extern void yellow_LED_on(void); +extern void yellow_LED_off(void); +#else + .extern LED_init + .extern red_LED_on + .extern red_LED_off + .extern yellow_LED_on + .extern yellow_LED_off + .extern green_LED_on + .extern green_LED_off +#endif + #endif /* CONFIG_STATUS_LED */ #endif /* _STATUS_LED_H_ */ -- cgit v1.3.1 From b90c045f035c3cc9b5d2edaed6048dfb74e40763 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 24 Sep 2007 00:08:37 +0200 Subject: synchronizition with mainline --- Makefile | 11 +- board/xilinx/xupv2p/Makefile | 21 ++- board/xilinx/xupv2p/config.mk | 6 +- board/xilinx/xupv2p/xparameters.h | 27 ++- common/cmd_jffs2.c | 36 +--- common/cmd_mfsl.c | 11 +- cpu/microblaze/cache.c | 2 +- cpu/microblaze/start.S | 6 +- cpu/microblaze/timer.c | 7 - drivers/net/Makefile | 3 +- drivers/net/xilinx_emac.c | 374 ------------------------------------- drivers/net/xilinx_emac.h | 148 --------------- drivers/net/xilinx_emaclite.c | 376 -------------------------------------- drivers/serial_xuartlite.c | 2 +- fs/Makefile | 2 +- fs/romfs/Makefile | 49 ----- fs/romfs/romfs.c | 240 ------------------------ include/configs/ml401.h | 50 ++--- include/configs/suzaku.h | 18 +- include/configs/xupv2p.h | 63 +++---- lib_microblaze/time.c | 8 - 21 files changed, 119 insertions(+), 1341 deletions(-) delete mode 100644 drivers/net/xilinx_emac.c delete mode 100644 drivers/net/xilinx_emac.h delete mode 100644 drivers/net/xilinx_emaclite.c delete mode 100644 fs/romfs/Makefile delete mode 100644 fs/romfs/romfs.c (limited to 'drivers') diff --git a/Makefile b/Makefile index 63e7dcb01dd..8d500f53495 100644 --- a/Makefile +++ b/Makefile @@ -144,7 +144,7 @@ ifeq ($(ARCH),m68k) CROSS_COMPILE = m68k-elf- endif ifeq ($(ARCH),microblaze) -CROSS_COMPILE = microblaze-uclinux- +CROSS_COMPILE = mb- endif ifeq ($(ARCH),blackfin) CROSS_COMPILE = bfin-uclinux- @@ -201,9 +201,8 @@ ifeq ($(CPU),ixp) LIBS += cpu/ixp/npe/libnpe.a endif LIBS += lib_$(ARCH)/lib$(ARCH).a -LIBS += fs/cramfs/libcramfs.a fs/ext2/libext2fs.a fs/fat/libfat.a \ - fs/fdos/libfdos.a fs/jffs2/libjffs2.a fs/reiserfs/libreiserfs.a \ - fs/romfs/libromfs.a +LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \ + fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a LIBS += net/libnet.a LIBS += disk/libdisk.a LIBS += rtc/librtc.a @@ -326,14 +325,14 @@ depend dep: version tags ctags: ctags -w -o $(OBJTREE)/ctags `find $(SUBDIRS) include \ lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \ - fs/cramfs fs/fat fs/fdos fs/jffs2 fs/romfs\ + fs/cramfs fs/fat fs/fdos fs/jffs2 \ net disk rtc dtt drivers drivers/sk98lin common \ \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)` etags: etags -a -o $(OBJTREE)/etags `find $(SUBDIRS) include \ lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \ - fs/cramfs fs/fat fs/fdos fs/jffs2 fs/romfs\ + fs/cramfs fs/fat fs/fdos fs/jffs2 \ net disk rtc dtt drivers drivers/sk98lin common \ \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)` diff --git a/board/xilinx/xupv2p/Makefile b/board/xilinx/xupv2p/Makefile index 99e7047350f..9ab5633626e 100644 --- a/board/xilinx/xupv2p/Makefile +++ b/board/xilinx/xupv2p/Makefile @@ -22,17 +22,32 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +$(shell mkdir -p $(obj)../xilinx_enet) +endif + +INCS := -I../common -I../xilinx_enet +CFLAGS += $(INCS) +HOST_CFLAGS += $(INCS) LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o +COBJS = $(BOARD).o \ + ../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \ + ../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \ + ../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \ + ../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \ + ../common/xbasic_types.o ../common/xdma_channel.o \ + ../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \ + ../common/xversion.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $^ clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/xilinx/xupv2p/config.mk b/board/xilinx/xupv2p/config.mk index eedfb24d4f3..c07b0b35b18 100644 --- a/board/xilinx/xupv2p/config.mk +++ b/board/xilinx/xupv2p/config.mk @@ -25,8 +25,8 @@ # Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 # -TEXT_BASE = 0x30000000 +TEXT_BASE = 0x38000000 -PLATFORM_CPPFLAGS += -mxl-pattern-compare PLATFORM_CPPFLAGS += -mno-xl-soft-mul -PLATFORM_CPPFLAGS += -mcpu=v5.00.c +PLATFORM_CPPFLAGS += -mno-xl-soft-div +PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/xilinx/xupv2p/xparameters.h b/board/xilinx/xupv2p/xparameters.h index 0bb7a805f4a..a96c693c551 100644 --- a/board/xilinx/xupv2p/xparameters.h +++ b/board/xilinx/xupv2p/xparameters.h @@ -28,24 +28,17 @@ /* System Clock Frequency */ #define XILINX_CLOCK_FREQ 100000000 -/* Microblaze is microblaze_0 */ -#define XILINX_USE_MSR_INSTR 1 -#define XILINX_PVR 0 -#define XILINX_FSL_NUMBER 0 - /* Interrupt controller is opb_intc_0 */ #define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 7 +#define XILINX_INTC_NUM_INTR_INPUTS 11 /* Timer pheriphery is opb_timer_1 */ #define XILINX_TIMER_BASEADDR 0x41c00000 -#define XILINX_TIMER_IRQ 0 +#define XILINX_TIMER_IRQ 1 /* Uart pheriphery is RS232_Uart_1 */ -#define XILINX_UARTLITE_BASEADDR 0x40600000 -#define XILINX_UARTLITE_BAUDRATE 115200 - -/* IIC doesn't exist */ +#define XILINX_UART_BASEADDR 0x40600000 +#define XILINX_UART_BAUDRATE 115200 /* GPIO is LEDs_4Bit*/ #define XILINX_GPIO_BASEADDR 0x40000000 @@ -58,10 +51,14 @@ /* Sysace Controller is SysACE_CompactFlash */ #define XILINX_SYSACE_BASEADDR 0x41800000 +#define XILINX_SYSACE_HIGHADDR 0x4180ffff #define XILINX_SYSACE_MEM_WIDTH 16 /* Ethernet controller is Ethernet_MAC */ -#define XILINX_EMAC_BASEADDR 0x40c00000 -#define XILINX_EMAC_DMA_PRESENT 3 -#define XILINX_EMAC_HALF_DUPLEX_EXIST 1 -#define XILINX_EMAC_MII_EXIST 1 +#define XPAR_XEMAC_NUM_INSTANCES 1 +#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 +#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000 +#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff +#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 +#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 +#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c index 3e6061a5202..513a226c431 100644 --- a/common/cmd_jffs2.c +++ b/common/cmd_jffs2.c @@ -85,7 +85,7 @@ */ /* - * JFFS2/CRAMFS/ROMFS support + * JFFS2/CRAMFS support */ #include #include @@ -175,11 +175,6 @@ extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename extern int cramfs_ls (struct part_info *info, char *filename); extern int cramfs_info (struct part_info *info); -extern int romfs_check (struct part_info *info); -extern int romfs_load (char *loadoffset, struct part_info *info, char *filename); -extern int romfs_ls (struct part_info *info, char *filename); -extern int romfs_info (struct part_info *info); - static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int part_num); /* command line only routines */ @@ -1879,22 +1874,14 @@ int do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if ((part = jffs2_part_info(current_dev, current_partnum))){ - /* check partition type for JFFS2, cramfs, romfs */ - if (cramfs_check(part)) { - fsname = "CRAMFS"; - } else if (romfs_check(part)) { - fsname = "ROMFS"; - } else { - fsname = "JFFS2"; - } + /* check partition type for cramfs */ + fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2"); printf("### %s loading '%s' to 0x%lx\n", fsname, filename, offset); if (cramfs_check(part)) { size = cramfs_load ((char *) offset, part, filename); - } else if (romfs_check(part)){ - size = romfs_load ((char *) offset, part, filename); } else { - /* if this is not cramfs or romfs assume jffs2 */ + /* if this is not cramfs assume jffs2 */ size = jffs2_1pass_load((char *)offset, part, filename); } @@ -1941,10 +1928,8 @@ int do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* check partition type for cramfs */ if (cramfs_check(part)) { ret = cramfs_ls (part, filename); - } else if (romfs_check(part)) { - ret = romfs_ls (part, filename); } else { - /* if this is not cramfs or romfs assume jffs2 */ + /* if this is not cramfs assume jffs2 */ ret = jffs2_1pass_ls(part, filename); } @@ -1966,6 +1951,7 @@ int do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { struct part_info *part; + char *fsname; int ret; /* make sure we are in sync with env variables */ @@ -1975,17 +1961,13 @@ int do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if ((part = jffs2_part_info(current_dev, current_partnum))){ /* check partition type for cramfs */ - puts("### filesystem type is "); + fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2"); + printf("### filesystem type is %s\n", fsname); if (cramfs_check(part)) { - puts("CRAMFS\n"); ret = cramfs_info (part); - } else if (romfs_check(part)) { - puts("ROMFS\n"); - ret = romfs_info (part); } else { - /* if this is not cramfs or romfs assume jffs2 */ - puts("JFFS2\n"); + /* if this is not cramfs assume jffs2 */ ret = jffs2_1pass_info(part); } diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c index 93cc873b05a..8d4c1a38d7f 100644 --- a/common/cmd_mfsl.c +++ b/common/cmd_mfsl.c @@ -357,7 +357,7 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) reg = (unsigned int)simple_strtoul (argv[1], NULL, 16); val = (unsigned int)simple_strtoul (argv[2], NULL, 16); - if (argc < 2) { + if (argc < 1) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } @@ -382,7 +382,6 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) puts ("ESR"); break; default: - puts ("Unsupported register\n"); return 1; } printf (": 0x%08lx\n", val); @@ -409,10 +408,10 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr, " 3 - blocking control write\n"); U_BOOT_CMD (rspr, 3, 1, do_rspr, - "rspr - read/write special purpose register\n", + "rmsr - read/write special purpose register\n", "- reg_num [write value] read/write special purpose register\n" - " 1 - MSR - Machine status register\n" - " 3 - EAR - Exception address register\n" - " 5 - ESR - Exception status register\n"); + " 0 - MSR - Machine status register\n" + " 1 - EAR - Exception address register\n" + " 2 - ESR - Exception status register\n"); #endif diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c index 4b7866fae50..6ce0b55b243 100644 --- a/cpu/microblaze/cache.c +++ b/cpu/microblaze/cache.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2007 Michal Simek * - * Michal SIMEK + * Michal SIMEK * * See file CREDITS for list of people who contributed to this * project. diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S index 8740284ad84..3c027ff9bb1 100644 --- a/cpu/microblaze/start.S +++ b/cpu/microblaze/start.S @@ -33,13 +33,15 @@ _start: addi r1, r0, CFG_INIT_SP_OFFSET addi r1, r1, -4 /* Decrement SP to top of memory */ /* add opcode instruction for 32bit jump - 2 instruction imm & brai*/ - addi r6, r0, 0xb0000000 /* hex b000 opcode imm */ + addi r6, r0, 0xb000 /* hex b000 opcode imm */ + bslli r6, r6, 16 /* shift */ swi r6, r0, 0x0 /* reset address */ swi r6, r0, 0x8 /* user vector exception */ swi r6, r0, 0x10 /* interrupt */ swi r6, r0, 0x20 /* hardware exception */ - addi r6, r0, 0xb8080000 /* hew b808 opcode brai*/ + addi r6, r0, 0xb808 /* hew b808 opcode brai*/ + bslli r6, r6, 16 swi r6, r0, 0x4 /* reset address */ swi r6, r0, 0xC /* user vector exception */ swi r6, r0, 0x14 /* interrupt */ diff --git a/cpu/microblaze/timer.c b/cpu/microblaze/timer.c index b350453443e..ab1cb127492 100644 --- a/cpu/microblaze/timer.c +++ b/cpu/microblaze/timer.c @@ -33,17 +33,10 @@ void reset_timer (void) timestamp = 0; } -#ifdef CFG_TIMER_0 ulong get_timer (ulong base) { return (timestamp - base); } -#else -ulong get_timer (ulong base) -{ - return (timestamp++ - base); -} -#endif void set_timer (ulong t) { diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 063985984eb..37d69b9949b 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -24,7 +24,8 @@ include $(TOPDIR)/config.mk LIB := $(obj)libnet.a -COBJS := mcffec.o xilinx_emac.o xilinx_emaclite.o + +COBJS := mcffec.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/net/xilinx_emac.c b/drivers/net/xilinx_emac.c deleted file mode 100644 index 36e627aae52..00000000000 --- a/drivers/net/xilinx_emac.c +++ /dev/null @@ -1,374 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Based on Xilinx drivers - * - */ - -#include -#include -#include -#include -#include "xilinx_emac.h" - -#ifdef XILINX_EMAC - -#undef DEBUG - -#define ENET_MAX_MTU PKTSIZE -#define ENET_ADDR_LENGTH 6 - -static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ - -static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; - -static xemac emac; - -void eth_halt(void) -{ -#ifdef DEBUG - puts ("eth_halt\n"); -#endif -} - -int eth_init(bd_t * bis) -{ - u32 helpreg; -#ifdef DEBUG - printf("EMAC Initialization Started\n\r"); -#endif - if (emac.isstarted) { - puts("Emac is started\n"); - return 0; - } - - memset (&emac, 0, sizeof (xemac)); - - emac.baseaddress = XILINX_EMAC_BASEADDR; - - /* Setting up FIFOs */ - emac.recvfifo.regbaseaddress = emac.baseaddress + - XEM_PFIFO_RXREG_OFFSET; - emac.recvfifo.databaseaddress = emac.baseaddress + - XEM_PFIFO_RXDATA_OFFSET; - out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK); - - emac.sendfifo.regbaseaddress = emac.baseaddress + - XEM_PFIFO_TXREG_OFFSET; - emac.sendfifo.databaseaddress = emac.baseaddress + - XEM_PFIFO_TXDATA_OFFSET; - out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK); - - /* Reset the entire IPIF */ - out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET, - XIIF_V123B_RESET_MASK); - - /* Stopping EMAC for setting up MAC */ - helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET); - helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); - out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); - - if (!getenv("ethaddr")) { - memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH); - } - - /* Set the device station address high and low registers */ - helpreg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1]; - out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg); - helpreg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) | - (bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5]; - out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg); - - - helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK | - XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK | - XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK; - out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); - - emac.isstarted = 1; - - /* Enable the transmitter, and receiver */ - helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET); - helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); - helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); - out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); - - printf("EMAC Initialization complete\n\r"); - return 0; -} - -int eth_send(volatile void *ptr, int len) -{ - u32 intrstatus; - u32 xmitstatus; - u32 fifocount; - u32 wordcount; - u32 extrabytecount; - u32 *wordbuffer = (u32 *) ptr; - - if (len > ENET_MAX_MTU) - len = ENET_MAX_MTU; - - /* - * Check for overruns and underruns for the transmit status and length - * FIFOs and make sure the send packet FIFO is not deadlocked. - * Any of these conditions is bad enough that we do not want to - * continue. The upper layer software should reset the device to resolve - * the error. - */ - intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); - if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | - XEM_EIR_XMIT_LFIFO_OVER_MASK)) { -#ifdef DEBUG - puts ("Transmitting overrun error\n"); -#endif - return 0; - } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | - XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { -#ifdef DEBUG - puts ("Transmitting underrun error\n"); -#endif - return 0; - } else if (in_be32 (emac.sendfifo.regbaseaddress + - XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) { -#ifdef DEBUG - puts("Transmitting fifo error\n"); -#endif - return 0; - } - - /* - * Before writing to the data FIFO, make sure the length FIFO is not - * full. The data FIFO might not be full yet even though the length FIFO - * is. This avoids an overrun condition on the length FIFO and keeps the - * FIFOs in sync. - * - * Clear the latched LFIFO_FULL bit so next time around the most - * current status is represented - */ - if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) { - out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, - intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK); -#ifdef DEBUG - puts ("Fifo is full\n"); -#endif - return 0; - } - - /* get the count of how many words may be inserted into the FIFO */ - fifocount = in_be32 (emac.sendfifo.regbaseaddress + - XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; - wordcount = len >> 2; - extrabytecount = len & 0x3; - - if (fifocount < wordcount) { -#ifdef DEBUG - puts ("Sending packet is larger then size of FIFO\n"); -#endif - return 0; - } - - for (fifocount = 0; fifocount < wordcount; fifocount++) { - out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]); - } - if (extrabytecount > 0) { - u32 lastword = 0; - u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount); - - if (extrabytecount == 1) { - lastword = extrabytesbuffer[0] << 24; - } else if (extrabytecount == 2) { - lastword = extrabytesbuffer[0] << 24 | - extrabytesbuffer[1] << 16; - } else if (extrabytecount == 3) { - lastword = extrabytesbuffer[0] << 24 | - extrabytesbuffer[1] << 16 | - extrabytesbuffer[2] << 8; - } - out_be32 (emac.sendfifo.databaseaddress, lastword); - } - - /* Loop on the MAC's status to wait for any pause to complete */ - intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); - while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) { - intrstatus = in_be32 ((emac.baseaddress) + - XIIF_V123B_IISR_OFFSET); - /* Clear the pause status from the transmit status register */ - out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, - intrstatus & XEM_EIR_XMIT_PAUSE_MASK); - } - - /* - * Set the MAC's transmit packet length register to tell it to transmit - */ - out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len); - - /* - * Loop on the MAC's status to wait for the transmit to complete. - * The transmit status is in the FIFO when the XMIT_DONE bit is set. - */ - do { - intrstatus = in_be32 ((emac.baseaddress) + - XIIF_V123B_IISR_OFFSET); - } - while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0); - - xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET); - - if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | - XEM_EIR_XMIT_LFIFO_OVER_MASK)) { -#ifdef DEBUG - puts ("Transmitting overrun error\n"); -#endif - return 0; - } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | - XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { -#ifdef DEBUG - puts ("Transmitting underrun error\n"); -#endif - return 0; - } - - /* Clear the interrupt status register of transmit statuses */ - out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, - intrstatus & XEM_EIR_XMIT_ALL_MASK); - - /* - * Collision errors are stored in the transmit status register - * instead of the interrupt status register - */ - if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) || - (xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) { -#ifdef DEBUG - puts ("Transmitting collision error\n"); -#endif - return 0; - } - return 1; -} - -int eth_rx(void) -{ - u32 pktlength; - u32 intrstatus; - u32 fifocount; - u32 wordcount; - u32 extrabytecount; - u32 lastword; - u8 *extrabytesbuffer; - - if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET) - & XPF_DEADLOCK_MASK) { - out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK); -#ifdef DEBUG - puts ("Receiving FIFO deadlock\n"); -#endif - return 0; - } - - /* - * Get the interrupt status to know what happened (whether an error - * occurred and/or whether frames have been received successfully). - * When clearing the intr status register, clear only statuses that - * pertain to receive. - */ - intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); - /* - * Before reading from the length FIFO, make sure the length FIFO is not - * empty. We could cause an underrun error if we try to read from an - * empty FIFO. - */ - if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) { -#ifdef DEBUG - /* puts("Receiving FIFO is empty\n"); */ -#endif - return 0; - } - - /* - * Determine, from the MAC, the length of the next packet available - * in the data FIFO (there should be a non-zero length here) - */ - pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET); - if (!pktlength) { - return 0; - } - - /* - * Write the RECV_DONE bit in the status register to clear it. This bit - * indicates the RPLR is non-empty, and we know it's set at this point. - * We clear it so that subsequent entry into this routine will reflect - * the current status. This is done because the non-empty bit is latched - * in the IPIF, which means it may indicate a non-empty condition even - * though there is something in the FIFO. - */ - out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, - XEM_EIR_RECV_DONE_MASK); - - fifocount = in_be32 (emac.recvfifo.regbaseaddress + - XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; - - if ((fifocount * 4) < pktlength) { -#ifdef DEBUG - puts ("Receiving FIFO is smaller than packet size.\n"); -#endif - return 0; - } - - wordcount = pktlength >> 2; - extrabytecount = pktlength & 0x3; - - for (fifocount = 0; fifocount < wordcount; fifocount++) { - etherrxbuff[fifocount] = - in_be32 (emac.recvfifo.databaseaddress); - } - - /* - * if there are extra bytes to handle, read the last word from the FIFO - * and insert the extra bytes into the buffer - */ - if (extrabytecount > 0) { - extrabytesbuffer = (u8 *) (etherrxbuff + wordcount); - - lastword = in_be32 (emac.recvfifo.databaseaddress); - - /* - * one extra byte in the last word, put the byte into the next - * location of the buffer, bytes in a word of the FIFO are - * ordered from most significant byte to least - */ - if (extrabytecount == 1) { - extrabytesbuffer[0] = (u8) (lastword >> 24); - } else if (extrabytecount == 2) { - extrabytesbuffer[0] = (u8) (lastword >> 24); - extrabytesbuffer[1] = (u8) (lastword >> 16); - } else if (extrabytecount == 3) { - extrabytesbuffer[0] = (u8) (lastword >> 24); - extrabytesbuffer[1] = (u8) (lastword >> 16); - extrabytesbuffer[2] = (u8) (lastword >> 8); - } - } - NetReceive((uchar *)etherrxbuff, pktlength); - return 1; -} -#endif diff --git a/drivers/net/xilinx_emac.h b/drivers/net/xilinx_emac.h deleted file mode 100644 index 966598e27a5..00000000000 --- a/drivers/net/xilinx_emac.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Based on Xilinx drivers - * - */ - -typedef struct { - u32 regbaseaddress; /* Base address of registers */ - u32 databaseaddress; /* Base address of data for FIFOs */ -} xpacketfifov100b; - -typedef struct { - u32 baseaddress; /* Base address (of IPIF) */ - u32 isstarted; /* Device is currently started 0-no, 1-yes */ - xpacketfifov100b recvfifo; /* FIFO used to receive frames */ - xpacketfifov100b sendfifo; /* FIFO used to send frames */ -} xemac; - -#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ -#define XIIF_V123B_RESET_MASK 0xAUL -#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ - -/* This constant is used with the Reset Register */ -#define XPF_RESET_FIFO_MASK 0x0000000A -#define XPF_COUNT_STATUS_REG_OFFSET 4UL - -/* These constants are used with the Occupancy/Vacancy Count Register. This - * register also contains FIFO status */ -#define XPF_COUNT_MASK 0x0000FFFF -#define XPF_DEADLOCK_MASK 0x20000000 - -/* Offset of the MAC registers from the IPIF base address */ -#define XEM_REG_OFFSET 0x1100UL - -/* - * Register offsets for the Ethernet MAC. Each register is 32 bits. - */ -#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */ -#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */ -#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */ -#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */ -#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */ -#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */ - - - -#define XEM_PFIFO_OFFSET 0x2000UL -/* Tx registers */ -#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) -/* Rx registers */ -#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) -/* Tx keyhole */ -#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) -/* Rx keyhole */ -#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) - - -/* - * EMAC Interrupt Registers (Status and Enable) masks. These registers are - * part of the IPIF IP Interrupt registers - */ -/* A mask for all transmit interrupts, used in polled mode */ -#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK |\ - XEM_EIR_XMIT_ERROR_MASK | \ - XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\ - XEM_EIR_XMIT_LFIFO_FULL_MASK) - -/* Xmit complete */ -#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL -/* Recv complete */ -#define XEM_EIR_RECV_DONE_MASK 0x00000002UL -/* Xmit error */ -#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL -/* Recv error */ -#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL -/* Xmit status fifo empty */ -#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL -/* Recv length fifo empty */ -#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL -/* Xmit length fifo full */ -#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL -/* Recv length fifo overrun */ -#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL -/* Recv length fifo underrun */ -#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL -/* Xmit status fifo overrun */ -#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL -/* Transmit status fifo underrun */ -#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL -/* Transmit length fifo overrun */ -#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL -/* Transmit length fifo underrun */ -#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL -/* Transmit pause pkt received */ -#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL - -/* - * EMAC Control Register (ECR) - */ -/* Full duplex mode */ -#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL -/* Reset transmitter */ -#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL -/* Enable transmitter */ -#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL -/* Reset receiver */ -#define XEM_ECR_RECV_RESET_MASK 0x10000000UL -/* Enable receiver */ -#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL -/* Enable PHY */ -#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL -/* Enable xmit pad insert */ -#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL -/* Enable xmit FCS insert */ -#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL -/* Enable unicast addr */ -#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL -/* Enable broadcast addr */ -#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL - -/* - * Transmit Status Register (TSR) - */ -/* Transmit excess deferral */ -#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL -/* Transmit late collision */ -#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c deleted file mode 100644 index 5d8eaa51823..00000000000 --- a/drivers/net/xilinx_emaclite.c +++ /dev/null @@ -1,376 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#ifdef XILINX_EMACLITE_BASEADDR - -#undef DEBUG - -#define ENET_MAX_MTU PKTSIZE -#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN -#define ENET_ADDR_LENGTH 6 - -/* EmacLite constants */ -#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ -#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ -#define XEL_TSR_OFFSET 0x07FC /* Tx status */ -#define XEL_RSR_OFFSET 0x17FC /* Rx status */ -#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ - -/* Xmit complete */ -#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL -/* Xmit interrupt enable bit */ -#define XEL_TSR_XMIT_IE_MASK 0x00000008UL -/* Buffer is active, SW bit only */ -#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL -/* Program the MAC address */ -#define XEL_TSR_PROGRAM_MASK 0x00000002UL -/* define for programming the MAC address into the EMAC Lite */ -#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) - -/* Transmit packet length upper byte */ -#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL -/* Transmit packet length lower byte */ -#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL - -/* Recv complete */ -#define XEL_RSR_RECV_DONE_MASK 0x00000001UL -/* Recv interrupt enable bit */ -#define XEL_RSR_RECV_IE_MASK 0x00000008UL - -typedef struct { - unsigned int baseaddress; /* Base address for device (IPIF) */ - unsigned int nexttxbuffertouse; /* Next TX buffer to write to */ - unsigned int nextrxbuffertouse; /* Next RX buffer to read from */ - unsigned char deviceid; /* Unique ID of device - for future */ -} xemaclite; - -static xemaclite emaclite; - -static char etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ - -/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/ -#ifdef CFG_ENV_IS_NOWHERE -static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; -#endif - -void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount) -{ - unsigned int i; - u32 alignbuffer; - u32 *to32ptr; - u32 *from32ptr; - u8 *to8ptr; - u8 *from8ptr; - - from32ptr = (u32 *) srcptr; - - /* Word aligned buffer, no correction needed. */ - to32ptr = (u32 *) destptr; - while (bytecount > 3) { - *to32ptr++ = *from32ptr++; - bytecount -= 4; - } - to8ptr = (u8 *) to32ptr; - - alignbuffer = *from32ptr++; - from8ptr = (u8 *) & alignbuffer; - - for (i = 0; i < bytecount; i++) { - *to8ptr++ = *from8ptr++; - } -} - -void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount) -{ - unsigned i; - u32 alignbuffer; - u32 *to32ptr = (u32 *) destptr; - u32 *from32ptr; - u8 *to8ptr; - u8 *from8ptr; - - from32ptr = (u32 *) srcptr; - while (bytecount > 3) { - - *to32ptr++ = *from32ptr++; - bytecount -= 4; - } - - alignbuffer = 0; - to8ptr = (u8 *) & alignbuffer; - from8ptr = (u8 *) from32ptr; - - for (i = 0; i < bytecount; i++) { - *to8ptr++ = *from8ptr++; - } - - *to32ptr++ = alignbuffer; -} - -void eth_halt (void) -{ -#ifdef DEBUG - puts ("eth_halt\n"); -#endif -} - -int eth_init (bd_t * bis) -{ -#ifdef DEBUG - puts ("EmacLite Initialization Started\n"); -#endif - memset (&emaclite, 0, sizeof (xemaclite)); - emaclite.baseaddress = XILINX_EMACLITE_BASEADDR; - - if (!getenv("ethaddr")) { - memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH); - } - -/* - * TX - TX_PING & TX_PONG initialization - */ - /* Restart PING TX */ - out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0); - /* Copy MAC address */ - xemaclite_alignedwrite (bis->bi_enetaddr, - emaclite.baseaddress, ENET_ADDR_LENGTH); - /* Set the length */ - out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); - /* Update the MAC address in the EMAC Lite */ - out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); - /* Wait for EMAC Lite to finish with the MAC address update */ - while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET) & - XEL_TSR_PROG_MAC_ADDR) != 0) ; - -#ifdef XILINX_EMACLITE_TX_PING_PONG - /* The same operation with PONG TX */ - out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); - xemaclite_alignedwrite (bis->bi_enetaddr, emaclite.baseaddress + - XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); - out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); - out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, - XEL_TSR_PROG_MAC_ADDR); - while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + - XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ; -#endif - -/* - * RX - RX_PING & RX_PONG initialization - */ - /* Write out the value to flush the RX buffer */ - out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); -#ifdef XILINX_EMACLITE_RX_PING_PONG - out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, - XEL_RSR_RECV_IE_MASK); -#endif - -#ifdef DEBUG - puts ("EmacLite Initialization complete\n"); -#endif - return 0; -} - -int xemaclite_txbufferavailable (xemaclite * instanceptr) -{ - u32 reg; - u32 txpingbusy; - u32 txpongbusy; - /* - * Read the other buffer register - * and determine if the other buffer is available - */ - reg = in_be32 (instanceptr->baseaddress + - instanceptr->nexttxbuffertouse + 0); - txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == - XEL_TSR_XMIT_BUSY_MASK); - - reg = in_be32 (instanceptr->baseaddress + - (instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0); - txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == - XEL_TSR_XMIT_BUSY_MASK); - - return (!(txpingbusy && txpongbusy)); -} - -int eth_send (volatile void *ptr, int len) { - - unsigned int reg; - unsigned int baseaddress; - - unsigned maxtry = 1000; - - if (len > ENET_MAX_MTU) - len = ENET_MAX_MTU; - - while (!xemaclite_txbufferavailable (&emaclite) && maxtry) { - udelay (10); - maxtry--; - } - - if (!maxtry) { - printf ("Error: Timeout waiting for ethernet TX buffer\n"); - /* Restart PING TX */ - out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0); -#ifdef XILINX_EMACLITE_TX_PING_PONG - out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + - XEL_BUFFER_OFFSET, 0); -#endif - return 0; - } - - /* Determine the expected TX buffer address */ - baseaddress = (emaclite.baseaddress + emaclite.nexttxbuffertouse); - - /* Determine if the expected buffer address is empty */ - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); - if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) - && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) - & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { - -#ifdef XILINX_EMACLITE_TX_PING_PONG - emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET; -#endif -#ifdef DEBUG - printf ("Send packet from 0x%x\n", baseaddress); -#endif - /* Write the frame to the buffer */ - xemaclite_alignedwrite ((void *) ptr, baseaddress, len); - out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & - (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); - reg |= XEL_TSR_XMIT_BUSY_MASK; - if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) { - reg |= XEL_TSR_XMIT_ACTIVE_MASK; - } - out_be32 (baseaddress + XEL_TSR_OFFSET, reg); - return 1; - } -#ifdef XILINX_EMACLITE_TX_PING_PONG - /* Switch to second buffer */ - baseaddress ^= XEL_BUFFER_OFFSET; - /* Determine if the expected buffer address is empty */ - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); - if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) - && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) - & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { -#ifdef DEBUG - printf ("Send packet from 0x%x\n", baseaddress); -#endif - /* Write the frame to the buffer */ - xemaclite_alignedwrite ((void *) ptr, baseaddress, len); - out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & - (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); - reg |= XEL_TSR_XMIT_BUSY_MASK; - if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) { - reg |= XEL_TSR_XMIT_ACTIVE_MASK; - } - out_be32 (baseaddress + XEL_TSR_OFFSET, reg); - return 1; - } -#endif - puts ("Error while sending frame\n"); - return 0; -} - -int eth_rx (void) -{ - unsigned int length; - unsigned int reg; - unsigned int baseaddress; - - baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse; - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); -#ifdef DEBUG - printf ("Testing data at address 0x%x\n", baseaddress); -#endif - if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { -#ifdef XILINX_EMACLITE_RX_PING_PONG - emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET; -#endif - } else { -#ifndef XILINX_EMACLITE_RX_PING_PONG -#ifdef DEBUG - printf ("No data was available - address 0x%x\n", baseaddress); -#endif - return 0; -#else - baseaddress ^= XEL_BUFFER_OFFSET; - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); - if ((reg & XEL_RSR_RECV_DONE_MASK) != - XEL_RSR_RECV_DONE_MASK) { -#ifdef DEBUG - printf ("No data was available - address 0x%x\n", - baseaddress); -#endif - return 0; - } -#endif - } - /* Get the length of the frame that arrived */ - switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) & - 0xFFFF0000 ) >> 16) { - case 0x806: - length = 42 + 20; /* FIXME size of ARP */ -#ifdef DEBUG - puts ("ARP Packet\n"); -#endif - break; - case 0x800: - length = 14 + 14 + - (((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) & - 0xFFFF0000) >> 16); /* FIXME size of IP packet */ -#ifdef DEBUG - puts("IP Packet\n"); -#endif - break; - default: -#ifdef DEBUG - puts("Other Packet\n"); -#endif - length = ENET_MAX_MTU; - break; - } - - xemaclite_alignedread ((u32 *) (baseaddress + XEL_RXBUFF_OFFSET), - etherrxbuff, length); - - /* Acknowledge the frame */ - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); - reg &= ~XEL_RSR_RECV_DONE_MASK; - out_be32 (baseaddress + XEL_RSR_OFFSET, reg); - -#ifdef DEBUG - printf ("Packet receive from 0x%x, length %dB\n", baseaddress, length); -#endif - NetReceive ((uchar *) etherrxbuff, length); - return 1; - -} -#endif diff --git a/drivers/serial_xuartlite.c b/drivers/serial_xuartlite.c index 1f3aaae4034..ed59abea862 100644 --- a/drivers/serial_xuartlite.c +++ b/drivers/serial_xuartlite.c @@ -24,7 +24,7 @@ #include -#ifdef XILINX_UARTLITE +#ifdef CONFIG_MICROBLAZE #include diff --git a/fs/Makefile b/fs/Makefile index 118ae78f2d3..273d90e011b 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -22,7 +22,7 @@ # # -SUBDIRS := romfs jffs2 cramfs fdos fat reiserfs ext2 +SUBDIRS := jffs2 cramfs fdos fat reiserfs ext2 $(obj).depend all: @for dir in $(SUBDIRS) ; do \ diff --git a/fs/romfs/Makefile b/fs/romfs/Makefile deleted file mode 100644 index 937d755940d..00000000000 --- a/fs/romfs/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)libromfs.a - -AOBJS = -COBJS = romfs.o - -SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) - -#CPPFLAGS += - -all: $(LIB) $(AOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/fs/romfs/romfs.c b/fs/romfs/romfs.c deleted file mode 100644 index 15de3e18ff0..00000000000 --- a/fs/romfs/romfs.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_CMD_JFFS2) - -#include -#include -#include -#include - -#undef DEBUG_ROMFS - -/* ROMFS superblock */ -struct romfs_super { - u32 word0; - u32 word1; - u32 size; - u32 checksum; - char name[0]; -}; - -struct romfs_inode { - u32 next; - u32 spec; - u32 size; - u32 checksum; - char name[0]; -}; - -extern flash_info_t flash_info[]; -#define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0]) -#define ALIGN(x) (((x) & 0xfffffff0)) -#define HEADERSIZE(name) (0x20 + ALIGN(strlen(name))) - -static unsigned long romfs_resolve (unsigned long begin, unsigned long offset, - unsigned long size, int raw, char *filename) -{ - unsigned long inodeoffset = 0, nextoffset; - struct romfs_inode *inode; -#ifdef DEBUG_ROMFS - printf ("ROMFS_resolve: begin 0x%x, offset 0x%x, size 0x%x, raw 0x%x, \ - filename %s\n", begin, offset, size, raw, filename); -#endif - - while (inodeoffset < size) { - inode = (struct romfs_inode *)(begin + offset + inodeoffset); - offset = 0; - nextoffset = ALIGN (inode->next); -#ifdef DEBUG_ROMFS - printf("inode 0x%x, name %s - len 0x%x, next inode 0x%x, \ - compare names 0x%x\n", - inode, inode->name, strlen (inode->name), nextoffset, - strncmp (filename, inode->name, strlen (filename))); -#endif - if (!strncmp (filename, inode->name, strlen (inode->name))) { - char *p = strtok (NULL, "/"); - if (raw && (p == NULL || *p == '\0')) { - return offset + inodeoffset; - } - return romfs_resolve (begin, - inodeoffset + HEADERSIZE (inode->name), - size, raw, p); - } - inodeoffset = nextoffset; - } - - printf ("can't find corresponding entry\n"); - return 0; -} - -int romfs_load (char *loadoffset, struct part_info *info, char *filename) -{ - struct romfs_inode *inode; - struct romfs_super *sb; - char *data; - int pocet; - sb = (struct romfs_super *) PART_OFFSET (info); - - unsigned long offset; - - offset = romfs_resolve (PART_OFFSET (info), HEADERSIZE (sb->name), - sb->size, 1, strtok (filename, "/")); - if (offset <= 0) - return offset; - - inode = (struct romfs_inode *)(PART_OFFSET (info) + offset); - data = (char *)((int)inode + HEADERSIZE (inode->name)); - pocet = inode->size; - while (pocet--) { - *loadoffset++ = *data++; - } - return inode->size; -} - -static int romfs_list_inode (struct part_info *info, unsigned long offset) -{ - struct romfs_inode *inode = - (struct romfs_inode *)(PART_OFFSET (info) + offset); - struct romfs_inode *hardlink = NULL; - char str[3], *data; - -/* - * mapping spec.info means - * 0 hard link link destination [file header] - * 1 directory first file's header - * 2 regular file unused, must be zero [MBZ] - * 3 symbolic link unused, MBZ (file data is the link content) - * 4 block device 16/16 bits major/minor number - * 5 char device - " - - * 6 socket unused, MBZ - * 7 fifo unused, MBZ - */ - char attributes[] = "hdflbcsp"; - str[0] = attributes[inode->next & 0x7]; - str[1] = (inode->next & 0x8) ? 'x' : '-'; - str[2] = '\0'; - - if ((str[0] == 'b') || (str[0] == 'c')) { -#ifdef DEBUG_ROMFS - printf (" %s %3d,%3d %12s 0x%08x 0x%08x", str, - (inode->spec & 0xffff0000) >> 16, - inode->spec & 0x0000ffff, inode->name, inode, - inode->spec); -#else - printf (" %s %3d,%3d %12s", str, - (inode->spec & 0xffff0000) >> 16, - inode->spec & 0x0000ffff); -#endif - } else { -#ifdef DEBUG_ROMFS - printf (" %s %7d %12s 0x%08x 0x%08x", str, inode->size, - inode->name, inode, inode->spec); -#else - printf (" %s %7d %12s", str, inode->size, inode->name); -#endif - if (str[0] == 'l') { - data = (char *)((int)inode + HEADERSIZE (inode->name)); - puts (" -> "); - puts (data); - } - if (str[0] == 'h') { - hardlink = (struct romfs_inode *)(PART_OFFSET (info) + - inode->spec); - puts (" -> "); - puts (hardlink->name); - } - } - puts ("\n"); - return ALIGN (inode->next); -} - -int romfs_ls (struct part_info *info, char *filename) -{ - struct romfs_inode *inode; - unsigned long inodeoffset = 0, nextoffset; - unsigned long offset, size; - struct romfs_super *sb; - sb = (struct romfs_super *)PART_OFFSET (info); - - if (strlen (filename) == 0 || !strcmp (filename, "/")) { - offset = HEADERSIZE (sb->name); - size = sb->size; - } else { - offset = romfs_resolve (PART_OFFSET (info), - HEADERSIZE (sb->name), sb->size, 1, - strtok (filename, "/")); - - if (offset == 0) { - return offset; - } - inode = (struct romfs_inode *)(PART_OFFSET (info) + offset); - if ((inode->next & 0x7) != 1) { - return (romfs_list_inode (info, offset) > 0); - } - - size = sb->size; - offset = offset + HEADERSIZE (inode->name); - } - - inodeoffset = offset + inodeoffset; - while (inodeoffset < size) { - nextoffset = romfs_list_inode (info, inodeoffset); - if (nextoffset == 0) - break; - inodeoffset = nextoffset; - } - return 1; -} - -int romfs_info (struct part_info *info) -{ - struct romfs_super *sb; - sb = (struct romfs_super *)PART_OFFSET (info); - - printf ("name: \t\t%s, len %d B\n", sb->name, strlen (sb->name)); - printf ("size of SB:\t%d B\n", HEADERSIZE (sb->name)); - printf ("full size:\t%d B\n", sb->size); - printf ("checksum:\t0x%x\n", sb->checksum); - return 0; -} - -int romfs_check (struct part_info *info) -{ - struct romfs_super *sb; - if (info->dev->id->type != MTD_DEV_TYPE_NOR) - return 0; - - sb = (struct romfs_super *)PART_OFFSET (info); - if ((sb->word0 != 0x2D726F6D) || (sb->word1 != 0x3166732D)) { - return 0; - } - return 1; -} - -#endif diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 74fe88867ea..7eeae708a72 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2007 Czech Technical University. * - * Michal SIMEK + * Michal SIMEK * * See file CREDITS for list of people who contributed to this * project. @@ -32,7 +32,6 @@ #define CONFIG_ML401 1 /* ML401 Board */ /* uart */ -#define XILINX_UARTLITE #define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR #define CONFIG_BAUDRATE XILINX_UART_BAUDRATE #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE } @@ -87,7 +86,7 @@ * 0x11FB_F000 CFG_MONITOR_BASE * MONITOR_CODE 256kB Env * 0x13FF_F000 CFG_GBL_DATA_OFFSET - * GLOBAL_DATA 4kB bd, gd + * GLOBAL_DATA 4kB bd, gd * 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE */ @@ -100,7 +99,7 @@ /* global pointer */ #define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */ /* start of global data */ -#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) +#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* monitor code */ #define SIZE 0x40000 @@ -146,16 +145,6 @@ #define CFG_FLASH_PROTECTION /* hardware flash protection */ #endif /* !FLASH */ -/* system ace */ -#ifdef XILINX_SYSACE_BASEADDR - #define CONFIG_SYSTEMACE - /* #define DEBUG_SYSTEMACE */ - #define SYSTEMACE_CONFIG_FPGA - #define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR - #define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH - #define CONFIG_DOS_PARTITION -#endif - /* * BOOTP options */ @@ -164,21 +153,28 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME + /* * Command line configuration. */ #include #define CONFIG_CMD_ASKENV +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_BDI #define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IMI #define CONFIG_CMD_IRQ +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC #define CONFIG_CMD_MFSL +#define CONFIG_CMD_NET #define CONFIG_CMD_PING - -#if defined(CONFIG_SYSTEMACE) - #define CONFIG_CMD_EXT2 - #define CONFIG_CMD_FAT -#endif +#define CONFIG_CMD_RUN #if defined(FLASH) #define CONFIG_CMD_ECHO @@ -190,8 +186,6 @@ #define CONFIG_CMD_ENV #define CONFIG_CMD_SAVES #endif -#else - #undef CONFIG_CMD_FLASH #endif #if defined(CONFIG_CMD_JFFS2) @@ -216,16 +210,24 @@ #define CONFIG_BOOTDELAY 30 #define CONFIG_BOOTARGS "root=romfs" #define CONFIG_HOSTNAME "ml401" -#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" +#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" #define CONFIG_IPADDR 192.168.0.3 -#define CONFIG_SERVERIP 192.168.0.5 -#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.5 +#define CONFIG_GATEWAYIP 192.168.0.1 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD /* architecture dependent code */ #define CFG_USR_EXCEP /* user exception */ #define CFG_HZ 1000 +/* system ace */ +#define CONFIG_SYSTEMACE +/* #define DEBUG_SYSTEMACE */ +#define SYSTEMACE_CONFIG_FPGA +#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR +#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH +#define CONFIG_DOS_PARTITION + #define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo" #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\ diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h index 9a2eec1bb2a..08ac9cbd58b 100644 --- a/include/configs/suzaku.h +++ b/include/configs/suzaku.h @@ -48,7 +48,6 @@ #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - (1024 * 1024)) -#define XILINX_UARTLITE #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 115200 } @@ -56,16 +55,21 @@ #define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000 #define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0) + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ #include -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_ENV -#undef CONFIG_CMD_MEMORY -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_MISC #define CFG_UART1_BASE (0xFFFF2000) #define CONFIG_SERIAL_BASE CFG_UART1_BASE @@ -104,6 +108,4 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define XILINX_CLOCK_FREQ 50000000 - #endif /* __CONFIG_H */ diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h index 006a132881d..35001d7ada3 100644 --- a/include/configs/xupv2p.h +++ b/include/configs/xupv2p.h @@ -31,34 +31,13 @@ #define CONFIG_XUPV2P 1 /* uart */ -#ifdef XILINX_UARTLITE_BASEADDR -#define XILINX_UARTLITE -#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR -#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE +#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR +#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE } -#else -#ifdef XILINX_UART16550_BASEADDR -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 4 -#define CONFIG_CONS_INDEX 1 -#define CFG_NS16550_COM1 XILINX_UART16550_BASEADDR -#define CFG_NS16550_CLK XILINX_UART16550_CLOCK_HZ - -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 115200 } -#endif -#endif /* ethernet */ -#ifdef XILINX_EMAC_BASEADDR -#define XILINX_EMAC 1 -#else -#ifdef XILINX_EMACLITE_BASEADDR -#define XILINX_EMACLITE 1 -#endif -#endif -#undef ET_DEBUG +#define CONFIG_EMAC 1 +#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES /* * setting reset address @@ -69,13 +48,11 @@ * U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze * jump to CFG_RESET_ADDRESS where is the original U-BOOT code. */ -/* #define CFG_RESET_ADDRESS 0x36000000 */ +#define CFG_RESET_ADDRESS 0x36000000 /* gpio */ -#ifdef XILINX_GPIO_BASEADDR #define CFG_GPIO_0 1 #define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR -#endif /* interrupt controller */ #define CFG_INTC_0 1 @@ -142,6 +119,7 @@ #define CFG_ENV_SIZE 0x1000 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE) + /* * BOOTP options */ @@ -150,24 +128,29 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME + /* * Command line configuration. */ #include -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE +#define CONFIG_CMD_MEMORY #define CONFIG_CMD_IRQ -#define CONFIG_CMD_MFSL +#define CONFIG_CMD_BDI +#define CONFIG_CMD_NET +#define CONFIG_CMD_IMI +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_RUN +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MISC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_PING -#ifdef XILINX_SYSACE_BASEADDR -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#endif /* Miscellaneous configurable options */ #define CFG_PROMPT "U-Boot-mONStR> " @@ -179,7 +162,7 @@ #define CONFIG_BOOTDELAY 30 #define CONFIG_BOOTARGS "root=romfs" -#define CONFIG_HOSTNAME "xupv2p" +#define CONFIG_HOSTNAME "ml401" #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" #define CONFIG_IPADDR 192.168.0.3 #define CONFIG_SERVERIP 192.168.0.5 @@ -195,13 +178,11 @@ "echo" /* system ace */ -#ifdef XILINX_SYSACE_BASEADDR #define CONFIG_SYSTEMACE /* #define DEBUG_SYSTEMACE */ #define SYSTEMACE_CONFIG_FPGA #define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR #define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH #define CONFIG_DOS_PARTITION -#endif #endif /* __CONFIG_H */ diff --git a/lib_microblaze/time.c b/lib_microblaze/time.c index 0fef834992a..3fa1b112627 100644 --- a/lib_microblaze/time.c +++ b/lib_microblaze/time.c @@ -26,17 +26,9 @@ #include -#ifdef CFG_TIMER_0 void udelay (unsigned long usec) { int i; i = get_timer (0); while ((get_timer (0) - i) < (usec / 1000)) ; } -#else -void udelay (unsigned long usec) -{ - unsigned int i; - for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 10000000); i++); -} -#endif -- cgit v1.3.1 From 0731cbae6c2feab93b244d83fd6a43f5cc9bf852 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 24 Sep 2007 00:25:11 +0200 Subject: [PATCH] Change macro name for UartLite because PowerPC 405 can use UartLite as console --- drivers/serial_xuartlite.c | 2 +- include/configs/ml401.h | 1 + include/configs/suzaku.h | 1 + include/configs/xupv2p.h | 1 + 4 files changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial_xuartlite.c b/drivers/serial_xuartlite.c index ed59abea862..d678ab6b766 100644 --- a/drivers/serial_xuartlite.c +++ b/drivers/serial_xuartlite.c @@ -24,7 +24,7 @@ #include -#ifdef CONFIG_MICROBLAZE +#ifdef CONFIG_XILINX_UARTLITE #include diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 7eeae708a72..2cf09495773 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -32,6 +32,7 @@ #define CONFIG_ML401 1 /* ML401 Board */ /* uart */ +#define CONFIG_XILINX_UARTLITE #define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR #define CONFIG_BAUDRATE XILINX_UART_BAUDRATE #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE } diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h index 08ac9cbd58b..2353b63f5da 100644 --- a/include/configs/suzaku.h +++ b/include/configs/suzaku.h @@ -48,6 +48,7 @@ #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - (1024 * 1024)) +#define CONFIG_XILINX_UARTLITE #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 115200 } diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h index 35001d7ada3..8ab0b49cd00 100644 --- a/include/configs/xupv2p.h +++ b/include/configs/xupv2p.h @@ -31,6 +31,7 @@ #define CONFIG_XUPV2P 1 /* uart */ +#define CONFIG_XILINX_UARTLITE #define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR #define CONFIG_BAUDRATE XILINX_UART_BAUDRATE #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE } -- cgit v1.3.1 From 785c13477b77dcd2e6c5128fffcdb4e1943f4818 Mon Sep 17 00:00:00 2001 From: Timo Ketola Date: Mon, 24 Sep 2007 14:50:32 +0300 Subject: Bugfix: Use only one PTD for one endpoint Original isp116x-hcd code prepared multiple PTDs for longer than 16 byte transfers for one endpoint. That is unnecessary because the ISP116x is able to split long data from one PTD into multiple transactions based on the buffer size of the endpoint. It also caused serious problems if the endpoint NAKed some of the transactions. In that case ISP116x wouldn't notice that the other PTDs were for the same endpoint and would try the other PTDs possibly out of order. That would break the whole transfer. This patch makes isp116x_submit_job to use one PTD for one transfer. Signed-off-by: Timo Ketola Signed-off-by: Markus Klotzbuecher --- drivers/isp116x-hcd.c | 112 ++++++++++++++++++++++++++++++++------------------ 1 file changed, 72 insertions(+), 40 deletions(-) (limited to 'drivers') diff --git a/drivers/isp116x-hcd.c b/drivers/isp116x-hcd.c index 8e2bc7adcc9..b21af10d0ba 100644 --- a/drivers/isp116x-hcd.c +++ b/drivers/isp116x-hcd.c @@ -113,9 +113,9 @@ static const char hcd_name[] = "isp116x-hcd"; struct isp116x isp116x_dev; struct isp116x_platform_data isp116x_board; -int got_rhsc = 0; /* root hub status change */ +static int got_rhsc; /* root hub status change */ struct usb_device *devgone; /* device which was disconnected */ -int rh_devnum = 0; /* address of Root Hub endpoint */ +static int rh_devnum; /* address of Root Hub endpoint */ /* ------------------------------------------------------------------------- */ @@ -522,11 +522,13 @@ static int unpack_fifo(struct isp116x *isp116x, struct usb_device *dev, done += PTD_GET_LEN(&ptd[i]); cc = PTD_GET_CC(&ptd[i]); - if (cc == TD_DATAUNDERRUN) { /* underrun is no error... */ - DBG("allowed data underrun"); - cc = TD_CC_NOERROR; - } - if (cc != TD_CC_NOERROR && ret == TD_CC_NOERROR) + + /* Data underrun means basically that we had more buffer space than + * the function had data. It is perfectly normal but upper levels have + * to know how much we actually transferred. + */ + if (cc == TD_NOTACCESSED || + (cc != TD_CC_NOERROR && (ret == TD_CC_NOERROR || ret == TD_DATAUNDERRUN))) ret = cc; } @@ -592,11 +594,19 @@ static int isp116x_interrupt(struct isp116x *isp116x) return ret; } -#define PTD_NUM 64 /* it should be enougth... */ -struct ptd ptd[PTD_NUM]; +/* With one PTD we can transfer almost 1K in one go; + * HC does the splitting into endpoint digestible transactions + */ +struct ptd ptd[1]; + static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe) { - return min(PTD_NUM * usb_maxpacket(dev, pipe), PTD_NUM * 16); + unsigned mpck = usb_maxpacket(dev, pipe); + + /* One PTD can transfer 1023 bytes but try to always + * transfer multiples of endpoint buffer size + */ + return 1023 / mpck * mpck; } /* Do an USB transfer @@ -610,13 +620,21 @@ static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe, int max = usb_maxpacket(dev, pipe); int dir_out = usb_pipeout(pipe); int speed_low = usb_pipeslow(pipe); - int i, done, stat, timeout, cc; - int retries = 10; + int i, done = 0, stat, timeout, cc; + + /* 500 frames or 0.5s timeout when function is busy and NAKs transactions for a while */ + int retries = 500; DBG("------------------------------------------------"); dump_msg(dev, pipe, buffer, len, "SUBMIT"); DBG("------------------------------------------------"); + if (len >= 1024) { + ERR("Too big job"); + dev->status = USB_ST_CRC_ERR; + return -1; + } + if (isp116x->disabled) { ERR("EPIPE"); dev->status = USB_ST_CRC_ERR; @@ -653,29 +671,15 @@ static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe, isp116x_write_reg32(isp116x, HCINTSTAT, 0xff); /* Prepare the PTD data */ - done = 0; - i = 0; - do { - ptd[i].count = PTD_CC_MSK | PTD_ACTIVE_MSK | - PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out)); - ptd[i].mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum); - ptd[i].len = PTD_LEN(max > len - done ? len - done : max) | - PTD_DIR(dir); - ptd[i].faddr = PTD_FA(usb_pipedevice(pipe)); - - usb_dotoggle(dev, epnum, dir_out); - done += PTD_GET_LEN(&ptd[i]); - i++; - if (i >= PTD_NUM) { - ERR("****** Cannot pack buffer! ******"); - dev->status = USB_ST_BUF_ERR; - return -1; - } - } while (done < len); - ptd[i - 1].mps |= PTD_LAST_MSK; + ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK | + PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out)); + ptd->mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum) | PTD_LAST_MSK; + ptd->len = PTD_LEN(len) | PTD_DIR(dir); + ptd->faddr = PTD_FA(usb_pipedevice(pipe)); +retry_same: /* Pack data into FIFO ram */ - pack_fifo(isp116x, dev, pipe, ptd, i, buffer, len); + pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len); #ifdef EXTRA_DELAY wait_ms(EXTRA_DELAY); #endif @@ -738,17 +742,42 @@ static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe, } /* Unpack data from FIFO ram */ - cc = unpack_fifo(isp116x, dev, pipe, ptd, i, buffer, len); + cc = unpack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len); + + i = PTD_GET_COUNT(ptd); + done += i; + buffer += i; + len -= i; - /* Mmm... sometime we get 0x0f as cc which is a non sense! - * Just retry the transfer... + /* There was some kind of real problem; Prepare the PTD again + * and retry from the failed transaction on */ - if (cc == 0x0f && retries-- > 0) { - usb_dotoggle(dev, epnum, dir_out); - goto retry; + if (cc && cc != TD_NOTACCESSED && cc != TD_DATAUNDERRUN) { + if (retries >= 100) { + retries -= 100; + /* The chip will have toggled the toggle bit for the failed + * transaction too. We have to toggle it back. + */ + usb_settoggle(dev, epnum, dir_out, !PTD_GET_TOGGLE(ptd)); + goto retry; + } + } + /* "Normal" errors; TD_NOTACCESSED would mean in effect that the function have NAKed + * the transactions from the first on for the whole frame. It may be busy and we retry + * with the same PTD. PTD_ACTIVE (and not TD_NOTACCESSED) would mean that some of the + * PTD didn't make it because the function was busy or the frame ended before the PTD + * finished. We prepare the rest of the data and try again. + */ + else if (cc == TD_NOTACCESSED || PTD_GET_ACTIVE(ptd) || (cc != TD_DATAUNDERRUN && PTD_GET_COUNT(ptd) < PTD_GET_LEN(ptd))) { + if (retries) { + --retries; + if (cc == TD_NOTACCESSED && PTD_GET_ACTIVE(ptd) && !PTD_GET_COUNT(ptd)) goto retry_same; + usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd)); + goto retry; + } } - if (cc != TD_CC_NOERROR) { + if (cc != TD_CC_NOERROR && cc != TD_DATAUNDERRUN) { DBG("****** completition code error %x ******", cc); switch (cc) { case TD_CC_BITSTUFFING: @@ -766,6 +795,7 @@ static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe, } return -cc; } + else usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd)); dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)"); @@ -1369,6 +1399,8 @@ int usb_lowlevel_init(void) DBG(""); + got_rhsc = rh_devnum = 0; + /* Init device registers addr */ isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR; isp116x->data_reg = (u16 *) ISP116X_HCD_DATA; -- cgit v1.3.1 From de74b9eeacccaf0a42e5ecc9ae79a88f7a311296 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 13 Oct 2007 21:15:39 +0200 Subject: Coding Style cleanup. Signed-off-by: Wolfgang Denk --- CHANGELOG | 175 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/at45.c | 18 ++--- include/configs/ads5121.h | 2 +- include/status_led.h | 4 +- lib_arm/board.c | 17 ++--- 5 files changed, 194 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/CHANGELOG b/CHANGELOG index 82b3145357d..66fa2e1e0e9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,98 @@ +commit e1893815b0999410d7a327589611c7b38e95299e +Author: Wolfgang Denk +Date: Fri Oct 12 15:49:39 2007 +0200 + + GP3 SSA: enable RTC + + Signed-off-by: Wolfgang Denk + +commit 8002012041f1ff9f997a5727abe5015f70cd2e46 +Author: Grzegorz Bernacki +Date: Tue Oct 9 13:58:24 2007 +0200 + + [ads5121] EEPROM support added. + + Signed-off-by: Grzegorz Bernacki + +commit 2b2a587d6d3076387d22ac740f44044bf46e2cb8 +Author: Marian Balakowicz +Date: Fri Oct 5 10:40:54 2007 +0200 + + tqm5200: Fix CONFIG_CMD_PCI typo in board config file. + + Signed-off-by: Marian Balakowicz + +commit 92869195ef8210758d2176230c0a36897afd50ed +Author: Bartlomiej Sieka +Date: Fri Oct 5 09:46:06 2007 +0200 + + CM5200: Fix missing null-termination in hostname manipulation code + + Signed-off-by: Bartlomiej Sieka + +commit 738815c0cc44aa329097f868dc1efc49ede9c5ba +Author: Stefan Roese +Date: Tue Oct 2 11:44:46 2007 +0200 + + ppc4xx: Coding style cleanup + + Signed-off-by: Stefan Roese + +commit 87c1833a39e944db66385286fd5e28f9b3fcdd50 +Author: Stefan Roese +Date: Tue Oct 2 11:44:19 2007 +0200 + + ppc4xx: lwmon5: Remove watchdog for now, since not fully tested yet + + Signed-off-by: Stefan Roese + +commit 2db64784061bfc34f4ba70ef1d2fbe7133b55670 +Author: Grzegorz Bernacki +Date: Mon Oct 1 09:51:50 2007 +0200 + + Program EPLD to force full duplex mode for PHY. + + EPLD forces modes of PHY operation. By default full duplex is turned off. + This fix turns it on. + + Signed-off-by: Grzegorz Bernacki + +commit 86ec86c04326c3913178a7679aa910de071da75d +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Thu Sep 27 23:27:47 2007 +0200 + + Fix missing DECLARE_GLOBAL_DATA_PTR on CONFIG_LPC2292 in serial + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 3e954beb614b5b190d7f4f4c3b641437a0132e35 +Author: Stefan Roese +Date: Tue Sep 11 14:12:55 2007 +0200 + + ppc4xx: lwmon5: Change GPIO 58 to default to low (watchdog test) + + Signed-off-by: Stefan Roese + +commit 0d38effc6e359e6b1b0c78d66e8bc1a4dc15a2ae +Author: Grant Likely +Date: Tue Sep 25 15:48:05 2007 -0600 + + Fpga: fix incorrect test of CFG_FPGA_XILINX macro + + CFG_FPGA_XILINX is a bit value used to test against the value in + CONFIG_FPGA. Testing for a value will always return TRUE. I don't + think that is the intention in this code. + + Signed-off-by: Grant Likely + +commit 66dcad3a9a53e0766d90e0084123bd8529522fb0 +Author: Wolfgang Denk +Date: Thu Sep 20 00:04:14 2007 +0200 + + v1.3.0-rc2 + + Signed-off-by: Wolfgang Denk + commit 135e19bc2773ebca487e9a8371f67e1ba202313a Author: Wolfgang Denk Date: Tue Sep 18 21:36:35 2007 +0200 @@ -38,6 +133,21 @@ Date: Tue Sep 18 17:40:27 2007 +0200 Signed-off-by: Wolfgang Denk +commit bd86220f58b99d6896198c385fda132f0c980915 +Author: Peter Pearse +Date: Tue Sep 18 13:07:54 2007 +0100 + + Move coloured led API to status_led.h + Improve indentation in drivers/at45.c + +commit 97213f32416ead885deafea86774e912ffd60ad0 +Author: David Saada +Date: Mon Sep 17 17:04:47 2007 +0200 + + Description: Add NEC's PCI OHCI module ID to the USB OHCI driver + + Signed-off-by: David Saada + commit 67c31036acaaaa992fc346cc89db0909a7e733c4 Author: Wolfgang Denk Date: Sun Sep 16 17:10:04 2007 +0200 @@ -193,6 +303,18 @@ Date: Thu Sep 13 18:21:48 2007 +0200 Signed-off-by: Marian Balakowicz +commit e1f601b572db5de9aa81a0b77c68a86994fe24c4 +Author: Bartlomiej Sieka +Date: Thu Sep 13 16:33:59 2007 +0200 + + tqm5200: Restore customary env. variable boot commands for powerpc kernels + + - update default definitions of kernel_addr and fdt_addr env. variables + - make arch/powerpc booting the default scenario + - update MTD partition layout to match the above + + Signed-off-by: Bartlomiej Sieka + commit f34024d4a328e6edd906456da98d2c537155c4f7 Author: Wolfgang Denk Date: Wed Sep 12 00:48:57 2007 +0200 @@ -201,6 +323,12 @@ Date: Wed Sep 12 00:48:57 2007 +0200 Signed-off-by: Wolfgang Denk +commit d94c79e47011af5e8dd10ed6163c09b4cfc743cc +Author: Peter Pearse +Date: Tue Sep 11 15:35:01 2007 +0100 + + Final tidy + commit 38ad82da0c1180ecdeb212a8f4245e945bcc546e Author: Grzegorz Bernacki Date: Tue Sep 11 15:42:11 2007 +0200 @@ -507,6 +635,14 @@ Date: Thu Sep 6 09:46:17 2007 -0600 Signed-off-by: Grant Likely +commit 80767a6cead9990d9e77e62be947843c2c72f469 +Author: Peter Pearse +Date: Wed Sep 5 16:04:41 2007 +0100 + + Changed API name to coloured_led.h + Removed code using deprecated ifdef CONFIG_BOOTBINFUNC + Tidied other cpu/arm920t/start.S code + commit 56a9270521baaa00e12639a978302a67f61ef060 Author: Kumar Gala Date: Thu Aug 30 16:18:18 2007 -0500 @@ -532,6 +668,31 @@ Date: Thu Aug 30 01:58:48 2007 -0500 Signed-off-by: Ed Swarthout +commit 9f5c3d3720e777a572dcdc8af2008b44c7243885 +Author: Peter Pearse +Date: Tue Sep 4 16:18:38 2007 +0100 + + Add coloured led interface for ARM boards. + Use it in cpu/arm920t/start.S to indicate U-Boot code has been entered. + +commit 7462fe0d5a9d40cde083fb1a3cd73911996b5ecb +Author: Peter Pearse +Date: Tue Sep 4 14:49:28 2007 +0100 + + Move include/led.h to board/at91rm9200dk + +commit 6e4bf9b24e57c15abc6542e685d06380bc64af27 +Author: Peter Pearse +Date: Tue Sep 4 14:25:51 2007 +0100 + + Ran Lindent on drivers/at45.c + +commit 557ab89d294f08dd532f21d19861b40093200a33 +Author: Peter Pearse +Date: Tue Sep 4 14:23:50 2007 +0100 + + Rename CONFIG_CMD_MUX to CONFIG_CMD_AT91_SPIMUX + commit 81b73dec16fd1227369a191e725e10044a9d56b8 Author: Gary Jennejohn Date: Fri Aug 31 15:21:46 2007 +0200 @@ -607,6 +768,20 @@ Date: Wed Aug 29 18:26:24 2007 -0600 Signed-off-by: Grant Likely +commit 04625764cc93ce8a61625ac19d7fe2a2ceee8143 +Author: Stefan Roese +Date: Wed Aug 29 16:31:18 2007 +0200 + + ppc4xx: Change lwmon5 default environment to support Linux RTC + + The Linux PCF8563 RTC driver doesn't do autoprobing, so we need + to supply the RTC I2C address as bootline parameter. This patch + adds support for this rtc probing parameter to the bootargs: + + "rtc-pcf8563.probe=0,0x51" + + Signed-off-by: Stefan Roese + commit 2602a5c40ae37ab965a4e240854fdaffb51328a4 Author: Kim Phillips Date: Wed Aug 29 09:06:05 2007 -0500 diff --git a/drivers/at45.c b/drivers/at45.c index a075ebd5d74..dac987a43a5 100644 --- a/drivers/at45.c +++ b/drivers/at45.c @@ -48,7 +48,7 @@ AT91S_DataFlashStatus AT91F_DataFlashSendCommand(AT91PS_DataFlash pDataFlash, /* process the address to obtain page address and byte address */ adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << - pDataFlash->pDevice->page_offset) + + pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); /* fill the command buffer */ @@ -217,9 +217,10 @@ AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( { int cmdsize; /* Test if the buffer command is legal */ - if ((BufferCommand != DB_PAGE_2_BUF1_TRF)&& - (BufferCommand != DB_PAGE_2_BUF2_TRF)) + if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && + (BufferCommand != DB_PAGE_2_BUF2_TRF)) { return DATAFLASH_BAD_COMMAND; + } /* no data to transmit or receive */ pDataFlash->pDataFlashDesc->tx_data_size = 0; @@ -250,9 +251,10 @@ AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer( { int cmdsize; /* Test if the buffer command is legal */ - if ((BufferCommand != DB_BUF1_WRITE) && - (BufferCommand != DB_BUF2_WRITE)) + if ((BufferCommand != DB_BUF1_WRITE) && + (BufferCommand != DB_BUF2_WRITE)) { return DATAFLASH_BAD_COMMAND; + } /* buffer address must be lower than page size */ if (bufferAddress > pDataFlash->pDevice->pages_size) @@ -319,7 +321,7 @@ AT91S_DataFlashStatus AT91F_PageErase( cmdsize = 4; if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; - return (AT91F_DataFlashSendCommand(pDataFlash, + return (AT91F_DataFlashSendCommand(pDataFlash, DB_PAGE_ERASE, cmdsize, page * pDataFlash->pDevice->pages_size)); } @@ -375,7 +377,7 @@ AT91S_DataFlashStatus AT91F_WriteBufferToMain(AT91PS_DataFlash pDataFlash, if (pDataFlash->pDevice->pages_number >= 16384) cmdsize = 5; /* Send the command to the dataflash */ - return (AT91F_DataFlashSendCommand(pDataFlash, BufferCommand, + return (AT91F_DataFlashSendCommand(pDataFlash, BufferCommand, cmdsize, dest)); } @@ -445,7 +447,7 @@ AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash pDataFlash, /* If destination does not fit a page start address */ if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0) { - length = + length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index ee9cfd6768c..bb1efdf6dea 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -239,7 +239,7 @@ */ #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ #define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ /* diff --git a/include/status_led.h b/include/status_led.h index 74e2147cf92..d12bb67c2c8 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -383,9 +383,9 @@ extern void __led_set (led_id_t mask, int state); # include #endif -/* +/* * Coloured LEDs API - */ + */ #ifndef __ASSEMBLY__ extern void coloured_LED_init (void); extern void red_LED_on(void); diff --git a/lib_arm/board.c b/lib_arm/board.c index 87848d94c04..af0233a6201 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -117,23 +117,19 @@ void *sbrk (ptrdiff_t increment) * May be supplied by boards if desired */ void inline __coloured_LED_init (void) {} -void inline coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init"))); +void inline coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init"))); void inline __red_LED_on (void) {} void inline red_LED_on (void) __attribute__((weak, alias("__red_LED_on"))); void inline __red_LED_off(void) {} -void inline red_LED_off(void) __attribute__((weak, alias("__red_LED_off"))); +void inline red_LED_off(void) __attribute__((weak, alias("__red_LED_off"))); void inline __green_LED_on(void) {} -void inline green_LED_on(void) __attribute__((weak, alias("__green_LED_on"))); +void inline green_LED_on(void) __attribute__((weak, alias("__green_LED_on"))); void inline __green_LED_off(void) {} -void inline green_LED_off(void)__attribute__((weak, alias("__green_LED_off"))); +void inline green_LED_off(void)__attribute__((weak, alias("__green_LED_off"))); void inline __yellow_LED_on(void) {} -void inline yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on"))); +void inline yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on"))); void inline __yellow_LED_off(void) {} -void inline yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off"))); - - - - +void inline yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off"))); /************************************************************************ * Init Utilities * @@ -209,7 +205,6 @@ static void display_flash_config (ulong size) } #endif /* CFG_NO_FLASH */ - /* * Breathe some life into the board... * -- cgit v1.3.1