From 1727e216987a2d4e3e220f8c09e4bb54a611d21e Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Mon, 27 Sep 2010 15:43:52 +0900 Subject: s5p_mmc: support 8-bit bus width This Patch do support 8-bit bus width for s5p So we add parameter for bus_width (in s5p_mmc_init(), s5p_mmc_initialize()) If want to use 8-bit bus width, only change (0, 8) instead of (0, 4). Signed-off-by: Jaehoon Chung Signed-off-by: Minkyu Kang Signed-off-by: Kyungmin Park --- drivers/mmc/s5p_mmc.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/s5p_mmc.c b/drivers/mmc/s5p_mmc.c index 1fd425cbb67..195b5be39ea 100644 --- a/drivers/mmc/s5p_mmc.c +++ b/drivers/mmc/s5p_mmc.c @@ -352,11 +352,16 @@ static void mmc_set_ios(struct mmc *mmc) ctrl = readb(&host->reg->hostctl); /* + * WIDE8[5] + * 0 = Depend on WIDE4 + * 1 = 8-bit mode * WIDE4[1] * 1 = 4-bit mode * 0 = 1-bit mode */ - if (mmc->bus_width == 4) + if (mmc->bus_width == 8) + ctrl |= (1 << 5); + else if (mmc->bus_width == 4) ctrl |= (1 << 1); else ctrl &= ~(1 << 1); @@ -437,7 +442,7 @@ static int mmc_core_init(struct mmc *mmc) return 0; } -static int s5p_mmc_initialize(int dev_index) +static int s5p_mmc_initialize(int dev_index, int bus_width) { struct mmc *mmc; @@ -450,7 +455,11 @@ static int s5p_mmc_initialize(int dev_index) mmc->init = mmc_core_init; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; + if (bus_width == 8) + mmc->host_caps = MMC_MODE_8BIT; + else + mmc->host_caps = MMC_MODE_4BIT; + mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; mmc->f_min = 400000; mmc->f_max = 52000000; @@ -462,7 +471,7 @@ static int s5p_mmc_initialize(int dev_index) return 0; } -int s5p_mmc_init(int dev_index) +int s5p_mmc_init(int dev_index, int bus_width) { - return s5p_mmc_initialize(dev_index); + return s5p_mmc_initialize(dev_index, bus_width); } -- cgit v1.3.1 From 1628cfc4fe4b2c3caa7e9d5622f0665c54e8ba6e Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Tue, 28 Sep 2010 14:35:02 +0900 Subject: ARMV7: S5P: serial: support the s5pc210 This patch is for s5pc210 support. Due to the resigter of baudrate is changed from slot to value, add both of them to uart structure. Signed-off-by: Minkyu Kang Signed-off-by: Kyungmin Park --- arch/arm/include/asm/arch-s5pc1xx/uart.h | 14 +++++++++++--- drivers/serial/serial_s5p.c | 6 +++++- 2 files changed, 16 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-s5pc1xx/uart.h b/arch/arm/include/asm/arch-s5pc1xx/uart.h index 2d7ad7ec987..f6eeab45cdc 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/uart.h +++ b/arch/arm/include/asm/arch-s5pc1xx/uart.h @@ -24,6 +24,12 @@ #define __ASM_ARCH_UART_H_ #ifndef __ASSEMBLY__ +/* baudrate rest value */ +union br_rest { + unsigned short slot; /* udivslot */ + unsigned char value; /* ufracval */ +}; + struct s5p_uart { unsigned int ulcon; unsigned int ucon; @@ -38,10 +44,12 @@ struct s5p_uart { unsigned char urxh; unsigned char res2[3]; unsigned int ubrdiv; - unsigned short udivslot; - unsigned char res3[2]; - unsigned char res4[0x3d0]; + union br_rest rest; + unsigned char res3[0x3d0]; }; + +static int use_divslot = 1; + #endif /* __ASSEMBLY__ */ #endif diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 77096643f1f..36333c3d49a 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -70,7 +70,11 @@ void serial_setbrg_dev(const int dev_index) val = uclk / baudrate; writel(val / 16 - 1, &uart->ubrdiv); - writew(udivslot[val % 16], &uart->udivslot); + + if (use_divslot) + writew(udivslot[val % 16], &uart->rest.slot); + else + writeb(val % 16, &uart->rest.value); } /* -- cgit v1.3.1 From 0284816e985ab8509371170f39501da0cdee75e4 Mon Sep 17 00:00:00 2001 From: Macpaul Lin Date: Tue, 19 Oct 2010 20:14:36 +0800 Subject: ftrtc010.c : enhance code according to original datasheet Add missing codes according to original datasheet. This patch also makes ftrtc010 could be adapted to PCLK and EXT_CLK. Signed-off-by: Macpaul Lin --- drivers/rtc/ftrtc010.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c index 7738a7acaa0..25e4a7bcdb8 100644 --- a/drivers/rtc/ftrtc010.c +++ b/drivers/rtc/ftrtc010.c @@ -34,6 +34,13 @@ struct ftrtc010 { unsigned int alarm_hour; /* 0x18 */ unsigned int record; /* 0x1c */ unsigned int cr; /* 0x20 */ + unsigned int wsec; /* 0x24 */ + unsigned int wmin; /* 0x28 */ + unsigned int whour; /* 0x2c */ + unsigned int wday; /* 0x30 */ + unsigned int intr; /* 0x34 */ + unsigned int div; /* 0x38 */ + unsigned int rev; /* 0x3c */ }; /* @@ -85,7 +92,11 @@ int rtc_get(struct rtc_time *tmp) debug("%s(): record register: %x\n", __func__, readl(&rtc->record)); +#ifdef CONFIG_FTRTC010_PCLK + now = (ftrtc010_time() + readl(&rtc->record)) / RTC_DIV_COUNT; +#else /* CONFIG_FTRTC010_EXTCLK */ now = ftrtc010_time() + readl(&rtc->record); +#endif to_tm(now, tmp); -- cgit v1.3.1 From 575001e40c9d10e63f2924649098e7c07d3985c7 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 13 Oct 2010 12:16:35 +0200 Subject: MX51: Add IPU driver for video support The patch is a porting of the IPU Linux driver developed by Freescale to have framebuffer functionalities in u-boot. The port is based on kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f, as delivered by Freescale [i.MX BSP]. Most features are dropped from the original driver and only LCD support is the goal of this porting. Signed-off-by: Stefano Babic --- arch/arm/include/asm/arch-mx5/crm_regs.h | 11 + drivers/video/ipu.h | 321 +++++++ drivers/video/ipu_common.c | 1183 ++++++++++++++++++++++++++ drivers/video/ipu_disp.c | 1359 ++++++++++++++++++++++++++++++ drivers/video/ipu_regs.h | 418 +++++++++ 5 files changed, 3292 insertions(+) create mode 100644 drivers/video/ipu.h create mode 100644 drivers/video/ipu_common.c create mode 100644 drivers/video/ipu_disp.c create mode 100644 drivers/video/ipu_regs.h (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index 14aa231a5b0..4ed8eb31c8a 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -189,4 +189,15 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 +/* Define the bits in register CCDR */ +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) + +/* Define the bits in register CCGRx */ +#define MXC_CCM_CCGR_CG_MASK 0x3 + +#define MXC_CCM_CCGR5_CG5_OFFSET 10 + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) + #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/drivers/video/ipu.h b/drivers/video/ipu.h new file mode 100644 index 00000000000..d8bc287d841 --- /dev/null +++ b/drivers/video/ipu.h @@ -0,0 +1,321 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * Linux IPU driver for MX51: + * + * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_IPU_H__ +#define __ASM_ARCH_IPU_H__ + +#include + +#define IDMA_CHAN_INVALID 0xFF +#define HIGH_RESOLUTION_WIDTH 1024 + +struct clk { + const char *name; + int id; + /* Source clock this clk depends on */ + struct clk *parent; + /* Secondary clock to enable/disable with this clock */ + struct clk *secondary; + /* Current clock rate */ + unsigned long rate; + /* Reference count of clock enable/disable */ + __s8 usecount; + /* Register bit position for clock's enable/disable control. */ + u8 enable_shift; + /* Register address for clock's enable/disable control. */ + void *enable_reg; + u32 flags; + /* + * Function ptr to recalculate the clock's rate based on parent + * clock's rate + */ + void (*recalc) (struct clk *); + /* + * Function ptr to set the clock to a new rate. The rate must match a + * supported rate returned from round_rate. Leave blank if clock is not + * programmable + */ + int (*set_rate) (struct clk *, unsigned long); + /* + * Function ptr to round the requested clock rate to the nearest + * supported rate that is less than or equal to the requested rate. + */ + unsigned long (*round_rate) (struct clk *, unsigned long); + /* + * Function ptr to enable the clock. Leave blank if clock can not + * be gated. + */ + int (*enable) (struct clk *); + /* + * Function ptr to disable the clock. Leave blank if clock can not + * be gated. + */ + void (*disable) (struct clk *); + /* Function ptr to set the parent clock of the clock. */ + int (*set_parent) (struct clk *, struct clk *); +}; + +/* + * Enumeration of Synchronous (Memory-less) panel types + */ +typedef enum { + IPU_PANEL_SHARP_TFT, + IPU_PANEL_TFT, +} ipu_panel_t; + +/* IPU Pixel format definitions */ +#define fourcc(a, b, c, d)\ + (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) + +/* + * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are + * the same used by V4L2 API. + */ + +#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0') +#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1') +#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6') +#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8') + +#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */ +#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */ +#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */ +#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */ +#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */ +#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */ +#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */ +#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*< 32 BGR-8-8-8-8 */ +#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*< 32 BGR-8-8-8-8 */ +#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*< 32 RGB-8-8-8-8 */ +#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*< 32 RGB-8-8-8-8 */ +#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*< 32 ABGR-8-8-8-8 */ + +/* YUV Interleaved Formats */ +#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*< 16 YUV 4:2:2 */ +#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*< 16 YUV 4:2:2 */ +#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*< 12 YUV 4:1:1 */ +#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*< 24 YUV 4:4:4 */ + +/* two planes -- one Y, one Cb + Cr interleaved */ +#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ + +#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*< 8 Greyscale */ +#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*< 9 YVU 4:1:0 */ +#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*< 9 YUV 4:1:0 */ +#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*< 12 YVU 4:2:0 */ +#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*< 12 YUV 4:2:0 */ +#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*< 12 YUV 4:2:0 */ +#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */ +#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */ + +/* + * IPU Driver channels definitions. + * Note these are different from IDMA channels + */ +#define IPU_MAX_CH 32 +#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \ + ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out) +#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24)) +#define IPU_CHAN_ID(ch) (ch >> 24) +#define IPU_CHAN_ALT(ch) (ch & 0x02000000) +#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F) +#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F) +#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F) +#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F)) +#define NO_DMA 0x3F +#define ALT 1 + +/* + * Enumeration of IPU logical channels. An IPU logical channel is defined as a + * combination of an input (memory to IPU), output (IPU to memory), and/or + * secondary input IDMA channels and in some cases an Image Converter task. + * Some channels consist of only an input or output. + */ +typedef enum { + CHAN_NONE = -1, + + MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA), + MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA), + MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA), + MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA), + + MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA), + MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA), + MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0), + MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0), + + DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + +} ipu_channel_t; + +/* + * Enumeration of types of buffers for a logical channel. + */ +typedef enum { + IPU_OUTPUT_BUFFER = 0, /*< Buffer for output from IPU */ + IPU_ALPHA_IN_BUFFER = 1, /*< Buffer for input to IPU */ + IPU_GRAPH_IN_BUFFER = 2, /*< Buffer for input to IPU */ + IPU_VIDEO_IN_BUFFER = 3, /*< Buffer for input to IPU */ + IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER, + IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, +} ipu_buffer_t; + +#define IPU_PANEL_SERIAL 1 +#define IPU_PANEL_PARALLEL 2 + +struct ipu_channel { + u8 video_in_dma; + u8 alpha_in_dma; + u8 graph_in_dma; + u8 out_dma; +}; + +enum ipu_dmfc_type { + DMFC_NORMAL = 0, + DMFC_HIGH_RESOLUTION_DC, + DMFC_HIGH_RESOLUTION_DP, + DMFC_HIGH_RESOLUTION_ONLY_DP, +}; + + +/* + * Union of initialization parameters for a logical channel. + */ +typedef union { + struct { + uint32_t di; + unsigned char interlaced; + } mem_dc_sync; + struct { + uint32_t temp; + } mem_sdc_fg; + struct { + uint32_t di; + unsigned char interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + unsigned char alpha_chan_en; + } mem_dp_bg_sync; + struct { + uint32_t temp; + } mem_sdc_bg; + struct { + uint32_t di; + unsigned char interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + unsigned char alpha_chan_en; + } mem_dp_fg_sync; +} ipu_channel_params_t; + +/* + * Bitfield of Display Interface signal polarities. + */ +typedef struct { + unsigned datamask_en:1; + unsigned ext_clk:1; + unsigned interlaced:1; + unsigned odd_field_first:1; + unsigned clksel_en:1; + unsigned clkidle_en:1; + unsigned data_pol:1; /* true = inverted */ + unsigned clk_pol:1; /* true = rising edge */ + unsigned enable_pol:1; + unsigned Hsync_pol:1; /* true = active high */ + unsigned Vsync_pol:1; +} ipu_di_signal_cfg_t; + +typedef enum { + RGB, + YCbCr, + YUV +} ipu_color_space_t; + +/* Common IPU API */ +int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params); +void ipu_uninit_channel(ipu_channel_t channel); + +int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + uint32_t u_offset, uint32_t v_offset); + +int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum, dma_addr_t phyaddr); + +int32_t ipu_is_channel_busy(ipu_channel_t channel); +void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +int32_t ipu_enable_channel(ipu_channel_t channel); +int32_t ipu_disable_channel(ipu_channel_t channel); + +int32_t ipu_init_sync_panel(int disp, + uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig); + +int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, + uint8_t alpha); +int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, + uint32_t colorKey); + +uint32_t bytes_per_pixel(uint32_t fmt); + +void clk_enable(struct clk *clk); +void clk_disable(struct clk *clk); +u32 clk_get_rate(struct clk *clk); +int clk_set_rate(struct clk *clk, unsigned long rate); +long clk_round_rate(struct clk *clk, unsigned long rate); +int clk_set_parent(struct clk *clk, struct clk *parent); +int clk_get_usecount(struct clk *clk); +struct clk *clk_get_parent(struct clk *clk); + +void ipu_dump_registers(void); +int ipu_probe(void); + +void ipu_dmfc_init(int dmfc_type, int first); +void ipu_init_dc_mappings(void); +void ipu_dmfc_set_wait4eot(int dma_chan, int width); +void ipu_dc_init(int dc_chan, int di, unsigned char interlaced); +void ipu_dc_uninit(int dc_chan); +void ipu_dp_dc_enable(ipu_channel_t channel); +int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, + uint32_t out_pixel_fmt); +void ipu_dp_uninit(ipu_channel_t channel); +void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap); +ipu_color_space_t format_to_colorspace(uint32_t fmt); + +#endif diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c new file mode 100644 index 00000000000..9d20c864bac --- /dev/null +++ b/drivers/video/ipu_common.c @@ -0,0 +1,1183 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * Linux IPU driver for MX51: + * + * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ +#include +#include +#include +#include +#include +#include +#include +#include "ipu.h" +#include "ipu_regs.h" + +extern struct mxc_ccm_reg *mxc_ccm; +extern u32 *ipu_cpmem_base; + +struct ipu_ch_param_word { + uint32_t data[5]; + uint32_t res[3]; +}; + +struct ipu_ch_param { + struct ipu_ch_param_word word[2]; +}; + +#define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch)) + +#define _param_word(base, w) \ + (((struct ipu_ch_param *)(base))->word[(w)].data) + +#define ipu_ch_param_set_field(base, w, bit, size, v) { \ + int i = (bit) / 32; \ + int off = (bit) % 32; \ + _param_word(base, w)[i] |= (v) << off; \ + if (((bit) + (size) - 1) / 32 > i) { \ + _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \ + } \ +} + +#define ipu_ch_param_mod_field(base, w, bit, size, v) { \ + int i = (bit) / 32; \ + int off = (bit) % 32; \ + u32 mask = (1UL << size) - 1; \ + u32 temp = _param_word(base, w)[i]; \ + temp &= ~(mask << off); \ + _param_word(base, w)[i] = temp | (v) << off; \ + if (((bit) + (size) - 1) / 32 > i) { \ + temp = _param_word(base, w)[i + 1]; \ + temp &= ~(mask >> (32 - off)); \ + _param_word(base, w)[i + 1] = \ + temp | ((v) >> (off ? (32 - off) : 0)); \ + } \ +} + +#define ipu_ch_param_read_field(base, w, bit, size) ({ \ + u32 temp2; \ + int i = (bit) / 32; \ + int off = (bit) % 32; \ + u32 mask = (1UL << size) - 1; \ + u32 temp1 = _param_word(base, w)[i]; \ + temp1 = mask & (temp1 >> off); \ + if (((bit)+(size) - 1) / 32 > i) { \ + temp2 = _param_word(base, w)[i + 1]; \ + temp2 &= mask >> (off ? (32 - off) : 0); \ + temp1 |= temp2 << (off ? (32 - off) : 0); \ + } \ + temp1; \ +}) + + +void clk_enable(struct clk *clk) +{ + if (clk) { + if (clk->usecount++ == 0) { + clk->enable(clk); + } + } +} + +void clk_disable(struct clk *clk) +{ + if (clk) { + if (!(--clk->usecount)) { + if (clk->disable) + clk->disable(clk); + } + } +} + +int clk_get_usecount(struct clk *clk) +{ + if (clk == NULL) + return 0; + + return clk->usecount; +} + +u32 clk_get_rate(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->rate; +} + +struct clk *clk_get_parent(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->parent; +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + if (clk && clk->set_rate) + clk->set_rate(clk, rate); + return clk->rate; +} + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || !clk->round_rate) + return 0; + + return clk->round_rate(clk, rate); +} + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + clk->parent = parent; + if (clk->set_parent) + return clk->set_parent(clk, parent); + return 0; +} + +static int clk_ipu_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + /* Handshake with IPU when certain clock rates are changed. */ + reg = __raw_readl(&mxc_ccm->ccdr); + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, &mxc_ccm->ccdr); + + /* Handshake with IPU when LPM is entered as its enabled. */ + reg = __raw_readl(&mxc_ccm->clpcr); + reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, &mxc_ccm->clpcr); + + return 0; +} + +static void clk_ipu_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + + /* + * No handshake with IPU whe dividers are changed + * as its not enabled. + */ + reg = __raw_readl(&mxc_ccm->ccdr); + reg |= MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, &mxc_ccm->ccdr); + + /* No handshake with IPU when LPM is entered as its not enabled. */ + reg = __raw_readl(&mxc_ccm->clpcr); + reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, &mxc_ccm->clpcr); +} + + +static struct clk ipu_clk = { + .name = "ipu_clk", + .rate = 133000000, + .enable_reg = (u32 *)(MXC_CCM_BASE + + offsetof(struct mxc_ccm_reg, CCGR5)), + .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET, + .enable = clk_ipu_enable, + .disable = clk_ipu_disable, + .usecount = 0, +}; + +/* Globals */ +struct clk *g_ipu_clk; +unsigned char g_ipu_clk_enabled; +struct clk *g_di_clk[2]; +struct clk *g_pixel_clk[2]; +unsigned char g_dc_di_assignment[10]; +uint32_t g_channel_init_mask; +uint32_t g_channel_enable_mask; + +static int ipu_dc_use_count; +static int ipu_dp_use_count; +static int ipu_dmfc_use_count; +static int ipu_di_use_count[2]; + +u32 *ipu_cpmem_base; +u32 *ipu_dc_tmpl_reg; + +/* Static functions */ + +static inline void ipu_ch_param_set_high_priority(uint32_t ch) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1); +}; + +static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type) +{ + return ((uint32_t) ch >> (6 * type)) & 0x3F; +}; + +/* Either DP BG or DP FG can be graphic window */ +static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan) +{ + return (dma_chan == 23 || dma_chan == 27); +} + +static inline int ipu_is_dmfc_chan(uint32_t dma_chan) +{ + return ((dma_chan >= 23) && (dma_chan <= 29)); +} + + +static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum, + dma_addr_t phyaddr) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29, + phyaddr / 8); +}; + +#define idma_is_valid(ch) (ch != NO_DMA) +#define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0) +#define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma)) + +static void ipu_pixel_clk_recalc(struct clk *clk) +{ + u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id)); + if (div == 0) + clk->rate = 0; + else + clk->rate = (clk->parent->rate * 16) / div; +} + +static unsigned long ipu_pixel_clk_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div, div1; + u32 tmp; + /* + * Calculate divider + * Fractional part is 4 bits, + * so simply multiply by 2^4 to get fractional part. + */ + tmp = (clk->parent->rate * 16); + div = tmp / rate; + + if (div < 0x10) /* Min DI disp clock divider is 1 */ + div = 0x10; + if (div & ~0xFEF) + div &= 0xFF8; + else { + div1 = div & 0xFE0; + if ((tmp/div1 - tmp/div) < rate / 4) + div = div1; + else + div &= 0xFF8; + } + return (clk->parent->rate * 16) / div; +} + +static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate) +{ + u32 div = (clk->parent->rate * 16) / rate; + + __raw_writel(div, DI_BS_CLKGEN0(clk->id)); + + /* Setup pixel clock timing */ + __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); + + clk->rate = (clk->parent->rate * 16) / div; + return 0; +} + +static int ipu_pixel_clk_enable(struct clk *clk) +{ + u32 disp_gen = __raw_readl(IPU_DISP_GEN); + disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE; + __raw_writel(disp_gen, IPU_DISP_GEN); + + return 0; +} + +static void ipu_pixel_clk_disable(struct clk *clk) +{ + u32 disp_gen = __raw_readl(IPU_DISP_GEN); + disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE; + __raw_writel(disp_gen, IPU_DISP_GEN); + +} + +static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) +{ + u32 di_gen = __raw_readl(DI_GENERAL(clk->id)); + + if (parent == g_ipu_clk) + di_gen &= ~DI_GEN_DI_CLK_EXT; + else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id]) + di_gen |= DI_GEN_DI_CLK_EXT; + else + return -EINVAL; + + __raw_writel(di_gen, DI_GENERAL(clk->id)); + ipu_pixel_clk_recalc(clk); + return 0; +} + +static struct clk pixel_clk[] = { + { + .name = "pixel_clk", + .id = 0, + .recalc = ipu_pixel_clk_recalc, + .set_rate = ipu_pixel_clk_set_rate, + .round_rate = ipu_pixel_clk_round_rate, + .set_parent = ipu_pixel_clk_set_parent, + .enable = ipu_pixel_clk_enable, + .disable = ipu_pixel_clk_disable, + .usecount = 0, + }, + { + .name = "pixel_clk", + .id = 1, + .recalc = ipu_pixel_clk_recalc, + .set_rate = ipu_pixel_clk_set_rate, + .round_rate = ipu_pixel_clk_round_rate, + .set_parent = ipu_pixel_clk_set_parent, + .enable = ipu_pixel_clk_enable, + .disable = ipu_pixel_clk_disable, + .usecount = 0, + }, +}; + +/* + * This function resets IPU + */ +void ipu_reset(void) +{ + u32 *reg; + u32 value; + + reg = (u32 *)SRC_BASE_ADDR; + value = __raw_readl(reg); + value = value | SW_IPU_RST; + __raw_writel(value, reg); +} + +/* + * This function is called by the driver framework to initialize the IPU + * hardware. + * + * @param dev The device structure for the IPU passed in by the + * driver framework. + * + * @return Returns 0 on success or negative error code on error + */ +int ipu_probe(void) +{ + unsigned long ipu_base; + u32 temp; + + u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR; + u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800); + + __raw_writel(0xF00, reg_hsc_mcd); + + /* CSI mode reserved*/ + temp = __raw_readl(reg_hsc_mxt_conf); + __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf); + + temp = __raw_readl(reg_hsc_mxt_conf); + __raw_writel(temp | 0x10000, reg_hsc_mxt_conf); + + ipu_base = IPU_CTRL_BASE_ADDR; + ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE); + ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE); + + g_pixel_clk[0] = &pixel_clk[0]; + g_pixel_clk[1] = &pixel_clk[1]; + + g_ipu_clk = &ipu_clk; + debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk)); + + ipu_reset(); + + clk_set_parent(g_pixel_clk[0], g_ipu_clk); + clk_set_parent(g_pixel_clk[1], g_ipu_clk); + clk_enable(g_ipu_clk); + + g_di_clk[0] = NULL; + g_di_clk[1] = NULL; + + __raw_writel(0x807FFFFF, IPU_MEM_RST); + while (__raw_readl(IPU_MEM_RST) & 0x80000000) + ; + + ipu_init_dc_mappings(); + + __raw_writel(0, IPU_INT_CTRL(5)); + __raw_writel(0, IPU_INT_CTRL(6)); + __raw_writel(0, IPU_INT_CTRL(9)); + __raw_writel(0, IPU_INT_CTRL(10)); + + /* DMFC Init */ + ipu_dmfc_init(DMFC_NORMAL, 1); + + /* Set sync refresh channels as high priority */ + __raw_writel(0x18800000L, IDMAC_CHA_PRI(0)); + + /* Set MCU_T to divide MCU access window into 2 */ + __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN); + + clk_disable(g_ipu_clk); + + return 0; +} + +void ipu_dump_registers(void) +{ + debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF)); + debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF)); + debug("IDMAC_CHA_EN1 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_EN(0))); + debug("IDMAC_CHA_EN2 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_EN(32))); + debug("IDMAC_CHA_PRI1 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_PRI(0))); + debug("IDMAC_CHA_PRI2 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_PRI(32))); + debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", + __raw_readl(IPU_CHA_DB_MODE_SEL(0))); + debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", + __raw_readl(IPU_CHA_DB_MODE_SEL(32))); + debug("DMFC_WR_CHAN = \t0x%08X\n", + __raw_readl(DMFC_WR_CHAN)); + debug("DMFC_WR_CHAN_DEF = \t0x%08X\n", + __raw_readl(DMFC_WR_CHAN_DEF)); + debug("DMFC_DP_CHAN = \t0x%08X\n", + __raw_readl(DMFC_DP_CHAN)); + debug("DMFC_DP_CHAN_DEF = \t0x%08X\n", + __raw_readl(DMFC_DP_CHAN_DEF)); + debug("DMFC_IC_CTRL = \t0x%08X\n", + __raw_readl(DMFC_IC_CTRL)); + debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n", + __raw_readl(IPU_FS_PROC_FLOW1)); + debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n", + __raw_readl(IPU_FS_PROC_FLOW2)); + debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n", + __raw_readl(IPU_FS_PROC_FLOW3)); + debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n", + __raw_readl(IPU_FS_DISP_FLOW1)); +} + +/* + * This function is called to initialize a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID to init. + * + * @param params Input parameter containing union of channel + * initialization parameters. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params) +{ + int ret = 0; + uint32_t ipu_conf; + + debug("init channel = %d\n", IPU_CHAN_ID(channel)); + + if (g_ipu_clk_enabled == 0) { + g_ipu_clk_enabled = 1; + clk_enable(g_ipu_clk); + } + + + if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) { + printf("Warning: channel already initialized %d\n", + IPU_CHAN_ID(channel)); + } + + ipu_conf = __raw_readl(IPU_CONF); + + switch (channel) { + case MEM_DC_SYNC: + if (params->mem_dc_sync.di > 1) { + ret = -EINVAL; + goto err; + } + + g_dc_di_assignment[1] = params->mem_dc_sync.di; + ipu_dc_init(1, params->mem_dc_sync.di, + params->mem_dc_sync.interlaced); + ipu_di_use_count[params->mem_dc_sync.di]++; + ipu_dc_use_count++; + ipu_dmfc_use_count++; + break; + case MEM_BG_SYNC: + if (params->mem_dp_bg_sync.di > 1) { + ret = -EINVAL; + goto err; + } + + g_dc_di_assignment[5] = params->mem_dp_bg_sync.di; + ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt, + params->mem_dp_bg_sync.out_pixel_fmt); + ipu_dc_init(5, params->mem_dp_bg_sync.di, + params->mem_dp_bg_sync.interlaced); + ipu_di_use_count[params->mem_dp_bg_sync.di]++; + ipu_dc_use_count++; + ipu_dp_use_count++; + ipu_dmfc_use_count++; + break; + case MEM_FG_SYNC: + ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt, + params->mem_dp_fg_sync.out_pixel_fmt); + + ipu_dc_use_count++; + ipu_dp_use_count++; + ipu_dmfc_use_count++; + break; + default: + printf("Missing channel initialization\n"); + break; + } + + /* Enable IPU sub module */ + g_channel_init_mask |= 1L << IPU_CHAN_ID(channel); + if (ipu_dc_use_count == 1) + ipu_conf |= IPU_CONF_DC_EN; + if (ipu_dp_use_count == 1) + ipu_conf |= IPU_CONF_DP_EN; + if (ipu_dmfc_use_count == 1) + ipu_conf |= IPU_CONF_DMFC_EN; + if (ipu_di_use_count[0] == 1) { + ipu_conf |= IPU_CONF_DI0_EN; + } + if (ipu_di_use_count[1] == 1) { + ipu_conf |= IPU_CONF_DI1_EN; + } + + __raw_writel(ipu_conf, IPU_CONF); + +err: + return ret; +} + +/* + * This function is called to uninitialize a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID to uninit. + */ +void ipu_uninit_channel(ipu_channel_t channel) +{ + uint32_t reg; + uint32_t in_dma, out_dma = 0; + uint32_t ipu_conf; + + if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) { + debug("Channel already uninitialized %d\n", + IPU_CHAN_ID(channel)); + return; + } + + /* + * Make sure channel is disabled + * Get input and output dma channels + */ + in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + if (idma_is_set(IDMAC_CHA_EN, in_dma) || + idma_is_set(IDMAC_CHA_EN, out_dma)) { + printf( + "Channel %d is not disabled, disable first\n", + IPU_CHAN_ID(channel)); + return; + } + + ipu_conf = __raw_readl(IPU_CONF); + + /* Reset the double buffer */ + reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma)); + __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma)); + reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma)); + __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma)); + + switch (channel) { + case MEM_DC_SYNC: + ipu_dc_uninit(1); + ipu_di_use_count[g_dc_di_assignment[1]]--; + ipu_dc_use_count--; + ipu_dmfc_use_count--; + break; + case MEM_BG_SYNC: + ipu_dp_uninit(channel); + ipu_dc_uninit(5); + ipu_di_use_count[g_dc_di_assignment[5]]--; + ipu_dc_use_count--; + ipu_dp_use_count--; + ipu_dmfc_use_count--; + break; + case MEM_FG_SYNC: + ipu_dp_uninit(channel); + ipu_dc_use_count--; + ipu_dp_use_count--; + ipu_dmfc_use_count--; + break; + default: + break; + } + + g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel)); + + if (ipu_dc_use_count == 0) + ipu_conf &= ~IPU_CONF_DC_EN; + if (ipu_dp_use_count == 0) + ipu_conf &= ~IPU_CONF_DP_EN; + if (ipu_dmfc_use_count == 0) + ipu_conf &= ~IPU_CONF_DMFC_EN; + if (ipu_di_use_count[0] == 0) { + ipu_conf &= ~IPU_CONF_DI0_EN; + } + if (ipu_di_use_count[1] == 0) { + ipu_conf &= ~IPU_CONF_DI1_EN; + } + + __raw_writel(ipu_conf, IPU_CONF); + + if (ipu_conf == 0) { + clk_disable(g_ipu_clk); + g_ipu_clk_enabled = 0; + } + +} + +static inline void ipu_ch_param_dump(int ch) +{ +#ifdef DEBUG + struct ipu_ch_param *p = ipu_ch_param_addr(ch); + debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch, + p->word[0].data[0], p->word[0].data[1], p->word[0].data[2], + p->word[0].data[3], p->word[0].data[4]); + debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch, + p->word[1].data[0], p->word[1].data[1], p->word[1].data[2], + p->word[1].data[3], p->word[1].data[4]); + debug("PFS 0x%x, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4)); + debug("BPP 0x%x, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3)); + debug("NPB 0x%x\n", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7)); + + debug("FW %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13)); + debug("FH %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12)); + debug("Stride %d\n", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14)); + + debug("Width0 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3)); + debug("Width1 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3)); + debug("Width2 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3)); + debug("Width3 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3)); + debug("Offset0 %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5)); + debug("Offset1 %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5)); + debug("Offset2 %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5)); + debug("Offset3 %d\n", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5)); +#endif +} + +static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p, + int red_width, int red_offset, + int green_width, int green_offset, + int blue_width, int blue_offset, + int alpha_width, int alpha_offset) +{ + /* Setup red width and offset */ + ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1); + ipu_ch_param_set_field(p, 1, 128, 5, red_offset); + /* Setup green width and offset */ + ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1); + ipu_ch_param_set_field(p, 1, 133, 5, green_offset); + /* Setup blue width and offset */ + ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1); + ipu_ch_param_set_field(p, 1, 138, 5, blue_offset); + /* Setup alpha width and offset */ + ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1); + ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset); +} + +static void ipu_ch_param_init(int ch, + uint32_t pixel_fmt, uint32_t width, + uint32_t height, uint32_t stride, + uint32_t u, uint32_t v, + uint32_t uv_stride, dma_addr_t addr0, + dma_addr_t addr1) +{ + uint32_t u_offset = 0; + uint32_t v_offset = 0; + struct ipu_ch_param params; + + memset(¶ms, 0, sizeof(params)); + + ipu_ch_param_set_field(¶ms, 0, 125, 13, width - 1); + + if ((ch == 8) || (ch == 9) || (ch == 10)) { + ipu_ch_param_set_field(¶ms, 0, 138, 12, (height / 2) - 1); + ipu_ch_param_set_field(¶ms, 1, 102, 14, (stride * 2) - 1); + } else { + ipu_ch_param_set_field(¶ms, 0, 138, 12, height - 1); + ipu_ch_param_set_field(¶ms, 1, 102, 14, stride - 1); + } + + ipu_ch_param_set_field(¶ms, 1, 0, 29, addr0 >> 3); + ipu_ch_param_set_field(¶ms, 1, 29, 29, addr1 >> 3); + + switch (pixel_fmt) { + case IPU_PIX_FMT_GENERIC: + /*Represents 8-bit Generic data */ + ipu_ch_param_set_field(¶ms, 0, 107, 3, 5); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 6); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 63); /* burst size */ + + break; + case IPU_PIX_FMT_GENERIC_32: + /*Represents 32-bit Generic data */ + break; + case IPU_PIX_FMT_RGB565: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + ipu_ch_params_set_packing(¶ms, 5, 0, 6, 5, 5, 11, 8, 16); + break; + case IPU_PIX_FMT_BGR24: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */ + + ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24); + break; + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_YUV444: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */ + + ipu_ch_params_set_packing(¶ms, 8, 16, 8, 8, 8, 0, 8, 24); + break; + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_BGR32: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + ipu_ch_params_set_packing(¶ms, 8, 8, 8, 16, 8, 24, 8, 0); + break; + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_RGB32: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + ipu_ch_params_set_packing(¶ms, 8, 24, 8, 16, 8, 8, 8, 0); + break; + case IPU_PIX_FMT_ABGR32: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + + ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24); + break; + case IPU_PIX_FMT_UYVY: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 0xA); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + break; + case IPU_PIX_FMT_YUYV: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 0x8); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + break; + case IPU_PIX_FMT_YUV420P2: + case IPU_PIX_FMT_YUV420P: + ipu_ch_param_set_field(¶ms, 1, 85, 4, 2); /* pix format */ + + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + u_offset = stride * height; + v_offset = u_offset + (uv_stride * height / 2); + /* burst size */ + if ((ch == 8) || (ch == 9) || (ch == 10)) { + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); + uv_stride = uv_stride*2; + } else { + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); + } + break; + case IPU_PIX_FMT_YVU422P: + /* BPP & pixel format */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + v_offset = (v == 0) ? stride * height : v; + u_offset = (u == 0) ? v_offset + v_offset / 2 : u; + break; + case IPU_PIX_FMT_YUV422P: + /* BPP & pixel format */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + u_offset = (u == 0) ? stride * height : u; + v_offset = (v == 0) ? u_offset + u_offset / 2 : v; + break; + case IPU_PIX_FMT_NV12: + /* BPP & pixel format */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 4); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + uv_stride = stride; + u_offset = (u == 0) ? stride * height : u; + break; + default: + puts("mxc ipu: unimplemented pixel format\n"); + break; + } + + + if (uv_stride) + ipu_ch_param_set_field(¶ms, 1, 128, 14, uv_stride - 1); + + /* Get the uv offset from user when need cropping */ + if (u || v) { + u_offset = u; + v_offset = v; + } + + /* UBO and VBO are 22-bit */ + if (u_offset/8 > 0x3fffff) + puts("The value of U offset exceeds IPU limitation\n"); + if (v_offset/8 > 0x3fffff) + puts("The value of V offset exceeds IPU limitation\n"); + + ipu_ch_param_set_field(¶ms, 0, 46, 22, u_offset / 8); + ipu_ch_param_set_field(¶ms, 0, 68, 22, v_offset / 8); + + debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch)); + memcpy(ipu_ch_param_addr(ch), ¶ms, sizeof(params)); +}; + +/* + * This function is called to initialize a buffer for logical IPU channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param pixel_fmt Input parameter for pixel format of buffer. + * Pixel format is a FOURCC ASCII code. + * + * @param width Input parameter for width of buffer in pixels. + * + * @param height Input parameter for height of buffer in pixels. + * + * @param stride Input parameter for stride length of buffer + * in pixels. + * + * @param phyaddr_0 Input parameter buffer 0 physical address. + * + * @param phyaddr_1 Input parameter buffer 1 physical address. + * Setting this to a value other than NULL enables + * double buffering mode. + * + * @param u private u offset for additional cropping, + * zero if not used. + * + * @param v private v offset for additional cropping, + * zero if not used. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + uint32_t u, uint32_t v) +{ + uint32_t reg; + uint32_t dma_chan; + + dma_chan = channel_2_dma(channel, type); + if (!idma_is_valid(dma_chan)) + return -EINVAL; + + if (stride < width * bytes_per_pixel(pixel_fmt)) + stride = width * bytes_per_pixel(pixel_fmt); + + if (stride % 4) { + printf( + "Stride not 32-bit aligned, stride = %d\n", stride); + return -EINVAL; + } + /* Build parameter memory data for DMA channel */ + ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0, + phyaddr_0, phyaddr_1); + + if (ipu_is_dmfc_chan(dma_chan)) { + ipu_dmfc_set_wait4eot(dma_chan, width); + } + + if (idma_is_set(IDMAC_CHA_PRI, dma_chan)) + ipu_ch_param_set_high_priority(dma_chan); + + ipu_ch_param_dump(dma_chan); + + reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan)); + if (phyaddr_1) + reg |= idma_mask(dma_chan); + else + reg &= ~idma_mask(dma_chan); + __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan)); + + /* Reset to buffer 0 */ + __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan)); + + return 0; +} + +/* + * This function enables a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_enable_channel(ipu_channel_t channel) +{ + uint32_t reg; + uint32_t in_dma; + uint32_t out_dma; + + if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) { + printf("Warning: channel already enabled %d\n", + IPU_CHAN_ID(channel)); + } + + /* Get input and output dma channels */ + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + if (idma_is_valid(in_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(in_dma)); + __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma)); + } + if (idma_is_valid(out_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(out_dma)); + __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma)); + } + + if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) || + (channel == MEM_FG_SYNC)) + ipu_dp_dc_enable(channel); + + g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel); + + return 0; +} + +/* + * This function clear buffer ready for a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to clear. + * + * @param bufNum Input parameter for which buffer number clear + * ready state. + * + */ +void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum) +{ + uint32_t dma_ch = channel_2_dma(channel, type); + + if (!idma_is_valid(dma_ch)) + return; + + __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */ + if (bufNum == 0) { + if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) { + __raw_writel(idma_mask(dma_ch), + IPU_CHA_BUF0_RDY(dma_ch)); + } + } else { + if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) { + __raw_writel(idma_mask(dma_ch), + IPU_CHA_BUF1_RDY(dma_ch)); + } + } + __raw_writel(0x0, IPU_GPR); /* write one to set */ +} + +/* + * This function disables a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param wait_for_stop Flag to set whether to wait for channel end + * of frame or return immediately. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_disable_channel(ipu_channel_t channel) +{ + uint32_t reg; + uint32_t in_dma; + uint32_t out_dma; + + if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) { + debug("Channel already disabled %d\n", + IPU_CHAN_ID(channel)); + return 0; + } + + /* Get input and output dma channels */ + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + if ((idma_is_valid(in_dma) && + !idma_is_set(IDMAC_CHA_EN, in_dma)) + && (idma_is_valid(out_dma) && + !idma_is_set(IDMAC_CHA_EN, out_dma))) + return -EINVAL; + + if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) || + (channel == MEM_DC_SYNC)) { + ipu_dp_dc_disable(channel, 0); + } + + /* Disable DMA channel(s) */ + if (idma_is_valid(in_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(in_dma)); + __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma)); + __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma)); + } + if (idma_is_valid(out_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(out_dma)); + __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma)); + __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma)); + } + + g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel)); + + /* Set channel buffers NOT to be ready */ + if (idma_is_valid(in_dma)) { + ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0); + ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1); + } + if (idma_is_valid(out_dma)) { + ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0); + ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1); + } + + return 0; +} + +uint32_t bytes_per_pixel(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_GENERIC: /*generic data */ + case IPU_PIX_FMT_RGB332: + case IPU_PIX_FMT_YUV420P: + case IPU_PIX_FMT_YUV422P: + return 1; + break; + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_YUYV: + case IPU_PIX_FMT_UYVY: + return 2; + break; + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + return 3; + break; + case IPU_PIX_FMT_GENERIC_32: /*generic data */ + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_RGB32: + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_ABGR32: + return 4; + break; + default: + return 1; + break; + } + return 0; +} + +ipu_color_space_t format_to_colorspace(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_RGB666: + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_RGB32: + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_ABGR32: + case IPU_PIX_FMT_LVDS666: + case IPU_PIX_FMT_LVDS888: + return RGB; + break; + + default: + return YCbCr; + break; + } + return RGB; +} diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c new file mode 100644 index 00000000000..11cf98d3d5a --- /dev/null +++ b/drivers/video/ipu_disp.c @@ -0,0 +1,1359 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * Linux IPU driver for MX51: + * + * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include +#include +#include +#include +#include +#include "ipu.h" +#include "ipu_regs.h" + +enum csc_type_t { + RGB2YUV = 0, + YUV2RGB, + RGB2RGB, + YUV2YUV, + CSC_NONE, + CSC_NUM +}; + +struct dp_csc_param_t { + int mode; + void *coeff; +}; + +#define SYNC_WAVE 0 + +/* DC display ID assignments */ +#define DC_DISP_ID_SYNC(di) (di) +#define DC_DISP_ID_SERIAL 2 +#define DC_DISP_ID_ASYNC 3 + +int dmfc_type_setup; +static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23; +int g_di1_tvout; + +extern struct clk *g_ipu_clk; +extern struct clk *g_di_clk[2]; +extern struct clk *g_pixel_clk[2]; + +extern unsigned char g_ipu_clk_enabled; +extern unsigned char g_dc_di_assignment[]; + +void ipu_dmfc_init(int dmfc_type, int first) +{ + u32 dmfc_wr_chan, dmfc_dp_chan; + + if (first) { + if (dmfc_type_setup > dmfc_type) + dmfc_type = dmfc_type_setup; + else + dmfc_type_setup = dmfc_type; + + /* disable DMFC-IC channel*/ + __raw_writel(0x2, DMFC_IC_CTRL); + } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) { + printf("DMFC high resolution has set, will not change\n"); + return; + } else + dmfc_type_setup = dmfc_type; + + if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) { + /* 1 - segment 0~3; + * 5B - segement 4, 5; + * 5F - segement 6, 7; + * 1C, 2C and 6B, 6F unused; + */ + debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n"); + dmfc_wr_chan = 0x00000088; + dmfc_dp_chan = 0x00009694; + dmfc_size_28 = 256 * 4; + dmfc_size_29 = 0; + dmfc_size_24 = 0; + dmfc_size_27 = 128 * 4; + dmfc_size_23 = 128 * 4; + } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) { + /* 1 - segment 0, 1; + * 5B - segement 2~5; + * 5F - segement 6,7; + * 1C, 2C and 6B, 6F unused; + */ + debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n"); + dmfc_wr_chan = 0x00000090; + dmfc_dp_chan = 0x0000968a; + dmfc_size_28 = 128 * 4; + dmfc_size_29 = 0; + dmfc_size_24 = 0; + dmfc_size_27 = 128 * 4; + dmfc_size_23 = 256 * 4; + } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) { + /* 5B - segement 0~3; + * 5F - segement 4~7; + * 1, 1C, 2C and 6B, 6F unused; + */ + debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n"); + dmfc_wr_chan = 0x00000000; + dmfc_dp_chan = 0x00008c88; + dmfc_size_28 = 0; + dmfc_size_29 = 0; + dmfc_size_24 = 0; + dmfc_size_27 = 256 * 4; + dmfc_size_23 = 256 * 4; + } else { + /* 1 - segment 0, 1; + * 5B - segement 4, 5; + * 5F - segement 6, 7; + * 1C, 2C and 6B, 6F unused; + */ + debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n"); + dmfc_wr_chan = 0x00000090; + dmfc_dp_chan = 0x00009694; + dmfc_size_28 = 128 * 4; + dmfc_size_29 = 0; + dmfc_size_24 = 0; + dmfc_size_27 = 128 * 4; + dmfc_size_23 = 128 * 4; + } + __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN); + __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF); + __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN); + /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */ + __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF); +} + +void ipu_dmfc_set_wait4eot(int dma_chan, int width) +{ + u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1); + + if (width >= HIGH_RESOLUTION_WIDTH) { + if (dma_chan == 23) + ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0); + else if (dma_chan == 28) + ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0); + } + + if (dma_chan == 23) { /*5B*/ + if (dmfc_size_23 / width > 3) + dmfc_gen1 |= 1UL << 20; + else + dmfc_gen1 &= ~(1UL << 20); + } else if (dma_chan == 24) { /*6B*/ + if (dmfc_size_24 / width > 1) + dmfc_gen1 |= 1UL << 22; + else + dmfc_gen1 &= ~(1UL << 22); + } else if (dma_chan == 27) { /*5F*/ + if (dmfc_size_27 / width > 2) + dmfc_gen1 |= 1UL << 21; + else + dmfc_gen1 &= ~(1UL << 21); + } else if (dma_chan == 28) { /*1*/ + if (dmfc_size_28 / width > 2) + dmfc_gen1 |= 1UL << 16; + else + dmfc_gen1 &= ~(1UL << 16); + } else if (dma_chan == 29) { /*6F*/ + if (dmfc_size_29 / width > 1) + dmfc_gen1 |= 1UL << 23; + else + dmfc_gen1 &= ~(1UL << 23); + } + + __raw_writel(dmfc_gen1, DMFC_GENERAL1); +} + +static void ipu_di_data_wave_config(int di, + int wave_gen, + int access_size, int component_size) +{ + u32 reg; + reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | + (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET); + __raw_writel(reg, DI_DW_GEN(di, wave_gen)); +} + +static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set, + int up, int down) +{ + u32 reg; + + reg = __raw_readl(DI_DW_GEN(di, wave_gen)); + reg &= ~(0x3 << (di_pin * 2)); + reg |= set << (di_pin * 2); + __raw_writel(reg, DI_DW_GEN(di, wave_gen)); + + __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set)); +} + +static void ipu_di_sync_config(int di, int wave_gen, + int run_count, int run_src, + int offset_count, int offset_src, + int repeat_count, int cnt_clr_src, + int cnt_polarity_gen_en, + int cnt_polarity_clr_src, + int cnt_polarity_trigger_src, + int cnt_up, int cnt_down) +{ + u32 reg; + + if ((run_count >= 0x1000) || (offset_count >= 0x1000) || + (repeat_count >= 0x1000) || + (cnt_up >= 0x400) || (cnt_down >= 0x400)) { + printf("DI%d counters out of range.\n", di); + return; + } + + reg = (run_count << 19) | (++run_src << 16) | + (offset_count << 3) | ++offset_src; + __raw_writel(reg, DI_SW_GEN0(di, wave_gen)); + reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) | + (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9); + reg |= (cnt_down << 16) | cnt_up; + if (repeat_count == 0) { + /* Enable auto reload */ + reg |= 0x10000000; + } + __raw_writel(reg, DI_SW_GEN1(di, wave_gen)); + reg = __raw_readl(DI_STP_REP(di, wave_gen)); + reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1))); + reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1)); + __raw_writel(reg, DI_STP_REP(di, wave_gen)); +} + +static void ipu_dc_map_config(int map, int byte_num, int offset, int mask) +{ + int ptr = map * 3 + byte_num; + u32 reg; + + reg = __raw_readl(DC_MAP_CONF_VAL(ptr)); + reg &= ~(0xFFFF << (16 * (ptr & 0x1))); + reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1)); + __raw_writel(reg, DC_MAP_CONF_VAL(ptr)); + + reg = __raw_readl(DC_MAP_CONF_PTR(map)); + reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num))); + reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num)); + __raw_writel(reg, DC_MAP_CONF_PTR(map)); +} + +static void ipu_dc_map_clear(int map) +{ + u32 reg = __raw_readl(DC_MAP_CONF_PTR(map)); + __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))), + DC_MAP_CONF_PTR(map)); +} + +static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map, + int wave, int glue, int sync) +{ + u32 reg; + int stop = 1; + + reg = sync; + reg |= (glue << 4); + reg |= (++wave << 11); + reg |= (++map << 15); + reg |= (operand << 20) & 0xFFF00000; + __raw_writel(reg, ipu_dc_tmpl_reg + word * 2); + + reg = (operand >> 12); + reg |= opcode << 4; + reg |= (stop << 9); + __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1); +} + +static void ipu_dc_link_event(int chan, int event, int addr, int priority) +{ + u32 reg; + + reg = __raw_readl(DC_RL_CH(chan, event)); + reg &= ~(0xFFFF << (16 * (event & 0x1))); + reg |= ((addr << 8) | priority) << (16 * (event & 0x1)); + __raw_writel(reg, DC_RL_CH(chan, event)); +} + +/* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250; + * U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.; + * V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.; + */ +static const int rgb2ycbcr_coeff[5][3] = { + {0x4D, 0x96, 0x1D}, + {0x3D5, 0x3AB, 0x80}, + {0x80, 0x395, 0x3EB}, + {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */ + {0x2, 0x2, 0x2}, /* S0, S1, S2 */ +}; + +/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128)); + * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); + * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); + */ +static const int ycbcr2rgb_coeff[5][3] = { + {0x095, 0x000, 0x0CC}, + {0x095, 0x3CE, 0x398}, + {0x095, 0x0FF, 0x000}, + {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */ + {0x1, 0x1, 0x1}, /*S0,S1,S2 */ +}; + +#define mask_a(a) ((u32)(a) & 0x3FF) +#define mask_b(b) ((u32)(b) & 0x3FFF) + +/* Pls keep S0, S1 and S2 as 0x2 by using this convertion */ +static int rgb_to_yuv(int n, int red, int green, int blue) +{ + int c; + c = red * rgb2ycbcr_coeff[n][0]; + c += green * rgb2ycbcr_coeff[n][1]; + c += blue * rgb2ycbcr_coeff[n][2]; + c /= 16; + c += rgb2ycbcr_coeff[3][n] * 4; + c += 8; + c /= 16; + if (c < 0) + c = 0; + if (c > 255) + c = 255; + return c; +} + +/* + * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE + * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE + */ +static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = { + { + {DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, + {0, 0}, + {0, 0}, + {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, + {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} + }, + { + {0, 0}, + {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, + {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, + {0, 0}, + {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} + }, + { + {0, 0}, + {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, + {0, 0}, + {0, 0}, + {0, 0} + }, + { + {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0} + }, + { + {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, + {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, + {0, 0}, + {0, 0}, + {0, 0} + } +}; + +static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE; +static int color_key_4rgb = 1; + +void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param, + unsigned char srm_mode_update) +{ + u32 reg; + const int (*coeff)[5][3]; + + if (dp_csc_param.mode >= 0) { + reg = __raw_readl(DP_COM_CONF(dp)); + reg &= ~DP_COM_CONF_CSC_DEF_MASK; + reg |= dp_csc_param.mode; + __raw_writel(reg, DP_COM_CONF(dp)); + } + + coeff = dp_csc_param.coeff; + + if (coeff) { + __raw_writel(mask_a((*coeff)[0][0]) | + (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp)); + __raw_writel(mask_a((*coeff)[0][2]) | + (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp)); + __raw_writel(mask_a((*coeff)[1][1]) | + (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp)); + __raw_writel(mask_a((*coeff)[2][0]) | + (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp)); + __raw_writel(mask_a((*coeff)[2][2]) | + (mask_b((*coeff)[3][0]) << 16) | + ((*coeff)[4][0] << 30), DP_CSC_0(dp)); + __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) | + (mask_b((*coeff)[3][2]) << 16) | + ((*coeff)[4][2] << 30), DP_CSC_1(dp)); + } + + if (srm_mode_update) { + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + } +} + +int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, + uint32_t out_pixel_fmt) +{ + int in_fmt, out_fmt; + int dp; + int partial = 0; + uint32_t reg; + + if (channel == MEM_FG_SYNC) { + dp = DP_SYNC; + partial = 1; + } else if (channel == MEM_BG_SYNC) { + dp = DP_SYNC; + partial = 0; + } else if (channel == MEM_BG_ASYNC0) { + dp = DP_ASYNC0; + partial = 0; + } else { + return -EINVAL; + } + + in_fmt = format_to_colorspace(in_pixel_fmt); + out_fmt = format_to_colorspace(out_pixel_fmt); + + if (partial) { + if (in_fmt == RGB) { + if (out_fmt == RGB) + fg_csc_type = RGB2RGB; + else + fg_csc_type = RGB2YUV; + } else { + if (out_fmt == RGB) + fg_csc_type = YUV2RGB; + else + fg_csc_type = YUV2YUV; + } + } else { + if (in_fmt == RGB) { + if (out_fmt == RGB) + bg_csc_type = RGB2RGB; + else + bg_csc_type = RGB2YUV; + } else { + if (out_fmt == RGB) + bg_csc_type = YUV2RGB; + else + bg_csc_type = YUV2YUV; + } + } + + /* Transform color key from rgb to yuv if CSC is enabled */ + reg = __raw_readl(DP_COM_CONF(dp)); + if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) && + (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) || + ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) || + ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) || + ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) { + int red, green, blue; + int y, u, v; + uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) & + 0xFFFFFFL; + + debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n", + color_key); + + red = (color_key >> 16) & 0xFF; + green = (color_key >> 8) & 0xFF; + blue = color_key & 0xFF; + + y = rgb_to_yuv(0, red, green, blue); + u = rgb_to_yuv(1, red, green, blue); + v = rgb_to_yuv(2, red, green, blue); + color_key = (y << 16) | (u << 8) | v; + + reg = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L; + __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(dp)); + color_key_4rgb = 0; + + debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n", + color_key); + } + + ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1); + + return 0; +} + +void ipu_dp_uninit(ipu_channel_t channel) +{ + int dp; + int partial = 0; + + if (channel == MEM_FG_SYNC) { + dp = DP_SYNC; + partial = 1; + } else if (channel == MEM_BG_SYNC) { + dp = DP_SYNC; + partial = 0; + } else if (channel == MEM_BG_ASYNC0) { + dp = DP_ASYNC0; + partial = 0; + } else { + return; + } + + if (partial) + fg_csc_type = CSC_NONE; + else + bg_csc_type = CSC_NONE; + + ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0); +} + +void ipu_dc_init(int dc_chan, int di, unsigned char interlaced) +{ + u32 reg = 0; + + if ((dc_chan == 1) || (dc_chan == 5)) { + if (interlaced) { + ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3); + ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1); + } else { + if (di) { + ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3); + ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, + 4, 1); + } else { + ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3); + ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, + 7, 1); + } + } + ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0); + + reg = 0x2; + reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; + reg |= di << 2; + if (interlaced) + reg |= DC_WR_CH_CONF_FIELD_MODE; + } else if ((dc_chan == 8) || (dc_chan == 9)) { + /* async channels */ + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1); + + reg = 0x3; + reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; + } + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + + __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan)); + + __raw_writel(0x00000084, DC_GEN); +} + +void ipu_dc_uninit(int dc_chan) +{ + if ((dc_chan == 1) || (dc_chan == 5)) { + ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0); + } else if ((dc_chan == 8) || (dc_chan == 9)) { + ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0); + } +} + +int ipu_chan_is_interlaced(ipu_channel_t channel) +{ + if (channel == MEM_DC_SYNC) + return !!(__raw_readl(DC_WR_CH_CONF_1) & + DC_WR_CH_CONF_FIELD_MODE); + else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC)) + return !!(__raw_readl(DC_WR_CH_CONF_5) & + DC_WR_CH_CONF_FIELD_MODE); + return 0; +} + +void ipu_dp_dc_enable(ipu_channel_t channel) +{ + int di; + uint32_t reg; + uint32_t dc_chan; + + if (channel == MEM_FG_SYNC) + dc_chan = 5; + if (channel == MEM_DC_SYNC) + dc_chan = 1; + else if (channel == MEM_BG_SYNC) + dc_chan = 5; + else + return; + + if (channel == MEM_FG_SYNC) { + /* Enable FG channel */ + reg = __raw_readl(DP_COM_CONF(DP_SYNC)); + __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC)); + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + return; + } + + di = g_dc_di_assignment[dc_chan]; + + /* Make sure other DC sync channel is not assigned same DI */ + reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan)); + if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) { + reg &= ~DC_WR_CH_CONF_PROG_DI_ID; + reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID; + __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); + } + + reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); + reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET; + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + + clk_enable(g_pixel_clk[di]); +} + +static unsigned char dc_swap; + +void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) +{ + uint32_t reg; + uint32_t csc; + uint32_t dc_chan = 0; + int timeout = 50; + + dc_swap = swap; + + if (channel == MEM_DC_SYNC) { + dc_chan = 1; + } else if (channel == MEM_BG_SYNC) { + dc_chan = 5; + } else if (channel == MEM_FG_SYNC) { + /* Disable FG channel */ + dc_chan = 5; + + reg = __raw_readl(DP_COM_CONF(DP_SYNC)); + csc = reg & DP_COM_CONF_CSC_DEF_MASK; + if (csc == DP_COM_CONF_CSC_DEF_FG) + reg &= ~DP_COM_CONF_CSC_DEF_MASK; + + reg &= ~DP_COM_CONF_FG_EN; + __raw_writel(reg, DP_COM_CONF(DP_SYNC)); + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + timeout = 50; + + /* + * Wait for DC triple buffer to empty, + * this check is useful for tv overlay. + */ + if (g_dc_di_assignment[dc_chan] == 0) + while ((__raw_readl(DC_STAT) & 0x00000002) + != 0x00000002) { + udelay(2000); + timeout -= 2; + if (timeout <= 0) + break; + } + else if (g_dc_di_assignment[dc_chan] == 1) + while ((__raw_readl(DC_STAT) & 0x00000020) + != 0x00000020) { + udelay(2000); + timeout -= 2; + if (timeout <= 0) + break; + } + return; + } else { + return; + } + + if (dc_swap) { + /* Swap DC channel 1 and 5 settings, and disable old dc chan */ + reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); + __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); + reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; + reg ^= DC_WR_CH_CONF_PROG_DI_ID; + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + } else { + timeout = 50; + + /* Wait for DC triple buffer to empty */ + if (g_dc_di_assignment[dc_chan] == 0) + while ((__raw_readl(DC_STAT) & 0x00000002) + != 0x00000002) { + udelay(2000); + timeout -= 2; + if (timeout <= 0) + break; + } + else if (g_dc_di_assignment[dc_chan] == 1) + while ((__raw_readl(DC_STAT) & 0x00000020) + != 0x00000020) { + udelay(2000); + timeout -= 2; + if (timeout <= 0) + break; + } + + reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); + reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + + reg = __raw_readl(IPU_DISP_GEN); + if (g_dc_di_assignment[dc_chan]) + reg &= ~DI1_COUNTER_RELEASE; + else + reg &= ~DI0_COUNTER_RELEASE; + __raw_writel(reg, IPU_DISP_GEN); + + /* Clock is already off because it must be done quickly, but + we need to fix the ref count */ + clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]); + } +} + +void ipu_init_dc_mappings(void) +{ + /* IPU_PIX_FMT_RGB24 */ + ipu_dc_map_clear(0); + ipu_dc_map_config(0, 0, 7, 0xFF); + ipu_dc_map_config(0, 1, 15, 0xFF); + ipu_dc_map_config(0, 2, 23, 0xFF); + + /* IPU_PIX_FMT_RGB666 */ + ipu_dc_map_clear(1); + ipu_dc_map_config(1, 0, 5, 0xFC); + ipu_dc_map_config(1, 1, 11, 0xFC); + ipu_dc_map_config(1, 2, 17, 0xFC); + + /* IPU_PIX_FMT_YUV444 */ + ipu_dc_map_clear(2); + ipu_dc_map_config(2, 0, 15, 0xFF); + ipu_dc_map_config(2, 1, 23, 0xFF); + ipu_dc_map_config(2, 2, 7, 0xFF); + + /* IPU_PIX_FMT_RGB565 */ + ipu_dc_map_clear(3); + ipu_dc_map_config(3, 0, 4, 0xF8); + ipu_dc_map_config(3, 1, 10, 0xFC); + ipu_dc_map_config(3, 2, 15, 0xF8); + + /* IPU_PIX_FMT_LVDS666 */ + ipu_dc_map_clear(4); + ipu_dc_map_config(4, 0, 5, 0xFC); + ipu_dc_map_config(4, 1, 13, 0xFC); + ipu_dc_map_config(4, 2, 21, 0xFC); +} + +int ipu_pixfmt_to_map(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_GENERIC: + case IPU_PIX_FMT_RGB24: + return 0; + case IPU_PIX_FMT_RGB666: + return 1; + case IPU_PIX_FMT_YUV444: + return 2; + case IPU_PIX_FMT_RGB565: + return 3; + case IPU_PIX_FMT_LVDS666: + return 4; + } + + return -1; +} + +/* + * This function is called to adapt synchronous LCD panel to IPU restriction. + */ +void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk, + uint16_t width, uint16_t height, + uint16_t h_start_width, + uint16_t h_end_width, + uint16_t v_start_width, + uint16_t *v_end_width) +{ + if (*v_end_width < 2) { + uint16_t total_width = width + h_start_width + h_end_width; + uint16_t total_height_old = height + v_start_width + + (*v_end_width); + uint16_t total_height_new = height + v_start_width + 2; + *v_end_width = 2; + *pixel_clk = (*pixel_clk) * total_width * total_height_new / + (total_width * total_height_old); + printf("WARNING: adapt panel end blank lines\n"); + } +} + +/* + * This function is called to initialize a synchronous LCD panel. + * + * @param disp The DI the panel is attached to. + * + * @param pixel_clk Desired pixel clock frequency in Hz. + * + * @param pixel_fmt Input parameter for pixel format of buffer. + * Pixel format is a FOURCC ASCII code. + * + * @param width The width of panel in pixels. + * + * @param height The height of panel in pixels. + * + * @param hStartWidth The number of pixel clocks between the HSYNC + * signal pulse and the start of valid data. + * + * @param hSyncWidth The width of the HSYNC signal in units of pixel + * clocks. + * + * @param hEndWidth The number of pixel clocks between the end of + * valid data and the HSYNC signal for next line. + * + * @param vStartWidth The number of lines between the VSYNC + * signal pulse and the start of valid data. + * + * @param vSyncWidth The width of the VSYNC signal in units of lines + * + * @param vEndWidth The number of lines between the end of valid + * data and the VSYNC signal for next frame. + * + * @param sig Bitfield of signal polarities for LCD interface. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ + +int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig) +{ + uint32_t reg; + uint32_t di_gen, vsync_cnt; + uint32_t div, rounded_pixel_clk; + uint32_t h_total, v_total; + int map; + struct clk *di_parent; + + debug("panel size = %d x %d\n", width, height); + + if ((v_sync_width == 0) || (h_sync_width == 0)) + return EINVAL; + + adapt_panel_to_ipu_restricitions(&pixel_clk, width, height, + h_start_width, h_end_width, + v_start_width, &v_end_width); + h_total = width + h_sync_width + h_start_width + h_end_width; + v_total = height + v_sync_width + v_start_width + v_end_width; + + /* Init clocking */ + debug("pixel clk = %d\n", pixel_clk); + + if (sig.ext_clk) { + if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/ + /* + * Set the PLL to be an even multiple + * of the pixel clock. + */ + if ((clk_get_usecount(g_pixel_clk[0]) == 0) && + (clk_get_usecount(g_pixel_clk[1]) == 0)) { + di_parent = clk_get_parent(g_di_clk[disp]); + rounded_pixel_clk = + clk_round_rate(g_pixel_clk[disp], + pixel_clk); + div = clk_get_rate(di_parent) / + rounded_pixel_clk; + if (div % 2) + div++; + if (clk_get_rate(di_parent) != div * + rounded_pixel_clk) + clk_set_rate(di_parent, + div * rounded_pixel_clk); + udelay(10000); + clk_set_rate(g_di_clk[disp], + 2 * rounded_pixel_clk); + udelay(10000); + } + } + clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]); + } else { + if (clk_get_usecount(g_pixel_clk[disp]) != 0) + clk_set_parent(g_pixel_clk[disp], g_ipu_clk); + } + rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk); + clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk); + udelay(5000); + /* Get integer portion of divider */ + div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) / + rounded_pixel_clk; + + ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1); + ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); + + map = ipu_pixfmt_to_map(pixel_fmt); + if (map < 0) { + debug("IPU_DISP: No MAP\n"); + return -EINVAL; + } + + di_gen = __raw_readl(DI_GENERAL(disp)); + + if (sig.interlaced) { + /* Setup internal HSYNC waveform */ + ipu_di_sync_config( + disp, /* display */ + 1, /* counter */ + h_total / 2 - 1,/* run count */ + DI_SYNC_CLK, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Field 1 VSYNC waveform */ + ipu_di_sync_config( + disp, /* display */ + 2, /* counter */ + h_total - 1, /* run count */ + DI_SYNC_CLK, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 4 /* COUNT DOWN */ + ); + + /* Setup internal HSYNC waveform */ + ipu_di_sync_config( + disp, /* display */ + 3, /* counter */ + v_total * 2 - 1,/* run count */ + DI_SYNC_INT_HSYNC, /* run_resolution */ + 1, /* offset */ + DI_SYNC_INT_HSYNC, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 4 /* COUNT DOWN */ + ); + + /* Active Field ? */ + ipu_di_sync_config( + disp, /* display */ + 4, /* counter */ + v_total / 2 - 1,/* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + v_start_width, /* offset */ + DI_SYNC_HSYNC, /* offset resolution */ + 2, /* repeat count */ + DI_SYNC_VSYNC, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Active Line */ + ipu_di_sync_config( + disp, /* display */ + 5, /* counter */ + 0, /* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + height / 2, /* repeat count */ + 4, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Field 0 VSYNC waveform */ + ipu_di_sync_config( + disp, /* display */ + 6, /* counter */ + v_total - 1, /* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* DC VSYNC waveform */ + vsync_cnt = 7; + ipu_di_sync_config( + disp, /* display */ + 7, /* counter */ + v_total / 2 - 1,/* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + 9, /* offset */ + DI_SYNC_HSYNC, /* offset resolution */ + 2, /* repeat count */ + DI_SYNC_VSYNC, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* active pixel waveform */ + ipu_di_sync_config( + disp, /* display */ + 8, /* counter */ + 0, /* run count */ + DI_SYNC_CLK, /* run_resolution */ + h_start_width, /* offset */ + DI_SYNC_CLK, /* offset resolution */ + width, /* repeat count */ + 5, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + ipu_di_sync_config( + disp, /* display */ + 9, /* counter */ + v_total - 1, /* run count */ + DI_SYNC_INT_HSYNC,/* run_resolution */ + v_total / 2, /* offset */ + DI_SYNC_INT_HSYNC,/* offset resolution */ + 0, /* repeat count */ + DI_SYNC_HSYNC, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 4 /* COUNT DOWN */ + ); + + /* set gentime select and tag sel */ + reg = __raw_readl(DI_SW_GEN1(disp, 9)); + reg &= 0x1FFFFFFF; + reg |= (3 - 1)<<29 | 0x00008000; + __raw_writel(reg, DI_SW_GEN1(disp, 9)); + + __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp)); + + /* set y_sel = 1 */ + di_gen |= 0x10000000; + di_gen |= DI_GEN_POLARITY_5; + di_gen |= DI_GEN_POLARITY_8; + } else { + /* Setup internal HSYNC waveform */ + ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, + 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + + /* Setup external (delayed) HSYNC waveform */ + ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1, + DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, + DI_SYNC_CLK, 0, h_sync_width * 2); + /* Setup VSYNC waveform */ + vsync_cnt = DI_SYNC_VSYNC; + ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1, + DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0, + DI_SYNC_NONE, 1, DI_SYNC_NONE, + DI_SYNC_INT_HSYNC, 0, v_sync_width * 2); + __raw_writel(v_total - 1, DI_SCR_CONF(disp)); + + /* Setup active data waveform to sync with DC */ + ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC, + v_sync_width + v_start_width, DI_SYNC_HSYNC, + height, + DI_SYNC_VSYNC, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK, + h_sync_width + h_start_width, DI_SYNC_CLK, + width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, + 0); + + /* reset all unused counters */ + __raw_writel(0, DI_SW_GEN0(disp, 6)); + __raw_writel(0, DI_SW_GEN1(disp, 6)); + __raw_writel(0, DI_SW_GEN0(disp, 7)); + __raw_writel(0, DI_SW_GEN1(disp, 7)); + __raw_writel(0, DI_SW_GEN0(disp, 8)); + __raw_writel(0, DI_SW_GEN1(disp, 8)); + __raw_writel(0, DI_SW_GEN0(disp, 9)); + __raw_writel(0, DI_SW_GEN1(disp, 9)); + + reg = __raw_readl(DI_STP_REP(disp, 6)); + reg &= 0x0000FFFF; + __raw_writel(reg, DI_STP_REP(disp, 6)); + __raw_writel(0, DI_STP_REP(disp, 7)); + __raw_writel(0, DI_STP_REP(disp, 9)); + + /* Init template microcode */ + if (disp) { + ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5); + ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5); + ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5); + } else { + ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5); + ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5); + ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5); + } + + if (sig.Hsync_pol) + di_gen |= DI_GEN_POLARITY_2; + if (sig.Vsync_pol) + di_gen |= DI_GEN_POLARITY_3; + + if (sig.clk_pol) + di_gen |= DI_GEN_POL_CLK; + + } + + __raw_writel(di_gen, DI_GENERAL(disp)); + + __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | + 0x00000002, DI_SYNC_AS_GEN(disp)); + + reg = __raw_readl(DI_POL(disp)); + reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); + if (sig.enable_pol) + reg |= DI_POL_DRDY_POLARITY_15; + if (sig.data_pol) + reg |= DI_POL_DRDY_DATA_POLARITY; + __raw_writel(reg, DI_POL(disp)); + + __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp))); + + return 0; +} + +/* + * This function sets the foreground and background plane global alpha blending + * modes. This function also sets the DP graphic plane according to the + * parameter of IPUv3 DP channel. + * + * @param channel IPUv3 DP channel + * + * @param enable Boolean to enable or disable global alpha + * blending. If disabled, local blending is used. + * + * @param alpha Global alpha value. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, + uint8_t alpha) +{ + uint32_t reg; + uint32_t flow; + + unsigned char bg_chan; + + if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) + flow = DP_SYNC; + else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) + flow = DP_ASYNC0; + else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1) + flow = DP_ASYNC1; + else + return -EINVAL; + + if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 || + channel == MEM_BG_ASYNC1) + bg_chan = 1; + else + bg_chan = 0; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + if (bg_chan) { + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow)); + } else { + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow)); + } + + if (enable) { + reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL; + __raw_writel(reg | ((uint32_t) alpha << 24), + DP_GRAPH_WIND_CTRL(flow)); + + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow)); + } else { + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow)); + } + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + return 0; +} + +/* + * This function sets the transparent color key for SDC graphic plane. + * + * @param channel Input parameter for the logical channel ID. + * + * @param enable Boolean to enable or disable color key + * + * @param colorKey 24-bit RGB color for transparent color key. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, + uint32_t color_key) +{ + uint32_t reg, flow; + int y, u, v; + int red, green, blue; + + if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) + flow = DP_SYNC; + else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) + flow = DP_ASYNC0; + else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1) + flow = DP_ASYNC1; + else + return -EINVAL; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + color_key_4rgb = 1; + /* Transform color key from rgb to yuv if CSC is enabled */ + if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) || + ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) || + ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) || + ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) { + + debug("color key 0x%x need change to yuv fmt\n", color_key); + + red = (color_key >> 16) & 0xFF; + green = (color_key >> 8) & 0xFF; + blue = color_key & 0xFF; + + y = rgb_to_yuv(0, red, green, blue); + u = rgb_to_yuv(1, red, green, blue); + v = rgb_to_yuv(2, red, green, blue); + color_key = (y << 16) | (u << 8) | v; + + color_key_4rgb = 0; + + debug("color key change to yuv fmt 0x%x\n", color_key); + } + + if (enable) { + reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L; + __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(flow)); + + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow)); + } else { + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow)); + } + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + return 0; +} diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h new file mode 100644 index 00000000000..36f07bbee33 --- /dev/null +++ b/drivers/video/ipu_regs.h @@ -0,0 +1,418 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * Linux IPU driver for MX51: + * + * (C) Copyright 2005-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IPU_REGS_INCLUDED__ +#define __IPU_REGS_INCLUDED__ + +#define IPU_DISP0_BASE 0x00000000 +#define IPU_MCU_T_DEFAULT 8 +#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25) +#define IPU_CM_REG_BASE 0x1E000000 +#define IPU_STAT_REG_BASE 0x1E000200 +#define IPU_IDMAC_REG_BASE 0x1E008000 +#define IPU_ISP_REG_BASE 0x1E010000 +#define IPU_DP_REG_BASE 0x1E018000 +#define IPU_IC_REG_BASE 0x1E020000 +#define IPU_IRT_REG_BASE 0x1E028000 +#define IPU_CSI0_REG_BASE 0x1E030000 +#define IPU_CSI1_REG_BASE 0x1E038000 +#define IPU_DI0_REG_BASE 0x1E040000 +#define IPU_DI1_REG_BASE 0x1E048000 +#define IPU_SMFC_REG_BASE 0x1E050000 +#define IPU_DC_REG_BASE 0x1E058000 +#define IPU_DMFC_REG_BASE 0x1E060000 +#define IPU_CPMEM_REG_BASE 0x1F000000 +#define IPU_LUT_REG_BASE 0x1F020000 +#define IPU_SRM_REG_BASE 0x1F040000 +#define IPU_TPM_REG_BASE 0x1F060000 +#define IPU_DC_TMPL_REG_BASE 0x1F080000 +#define IPU_ISP_TBPR_REG_BASE 0x1F0C0000 +#define IPU_VDI_REG_BASE 0x1E068000 + + +extern u32 *ipu_dc_tmpl_reg; + +#define DC_EVT_NF 0 +#define DC_EVT_NL 1 +#define DC_EVT_EOF 2 +#define DC_EVT_NFIELD 3 +#define DC_EVT_EOL 4 +#define DC_EVT_EOFIELD 5 +#define DC_EVT_NEW_ADDR 6 +#define DC_EVT_NEW_CHAN 7 +#define DC_EVT_NEW_DATA 8 + +#define DC_EVT_NEW_ADDR_W_0 0 +#define DC_EVT_NEW_ADDR_W_1 1 +#define DC_EVT_NEW_CHAN_W_0 2 +#define DC_EVT_NEW_CHAN_W_1 3 +#define DC_EVT_NEW_DATA_W_0 4 +#define DC_EVT_NEW_DATA_W_1 5 +#define DC_EVT_NEW_ADDR_R_0 6 +#define DC_EVT_NEW_ADDR_R_1 7 +#define DC_EVT_NEW_CHAN_R_0 8 +#define DC_EVT_NEW_CHAN_R_1 9 +#define DC_EVT_NEW_DATA_R_0 10 +#define DC_EVT_NEW_DATA_R_1 11 + +/* Software reset for ipu */ +#define SW_IPU_RST 8 + +enum { + IPU_CONF_DP_EN = 0x00000020, + IPU_CONF_DI0_EN = 0x00000040, + IPU_CONF_DI1_EN = 0x00000080, + IPU_CONF_DMFC_EN = 0x00000400, + IPU_CONF_DC_EN = 0x00000200, + + DI0_COUNTER_RELEASE = 0x01000000, + DI1_COUNTER_RELEASE = 0x02000000, + + DI_DW_GEN_ACCESS_SIZE_OFFSET = 24, + DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16, + + DI_GEN_DI_CLK_EXT = 0x100000, + DI_GEN_POLARITY_1 = 0x00000001, + DI_GEN_POLARITY_2 = 0x00000002, + DI_GEN_POLARITY_3 = 0x00000004, + DI_GEN_POLARITY_4 = 0x00000008, + DI_GEN_POLARITY_5 = 0x00000010, + DI_GEN_POLARITY_6 = 0x00000020, + DI_GEN_POLARITY_7 = 0x00000040, + DI_GEN_POLARITY_8 = 0x00000080, + DI_GEN_POL_CLK = 0x20000, + + DI_POL_DRDY_DATA_POLARITY = 0x00000080, + DI_POL_DRDY_POLARITY_15 = 0x00000010, + DI_VSYNC_SEL_OFFSET = 13, + + DC_WR_CH_CONF_FIELD_MODE = 0x00000200, + DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5, + DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0, + DC_WR_CH_CONF_PROG_DI_ID = 0x00000004, + DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3, + DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018, + + DP_COM_CONF_FG_EN = 0x00000001, + DP_COM_CONF_GWSEL = 0x00000002, + DP_COM_CONF_GWAM = 0x00000004, + DP_COM_CONF_GWCKE = 0x00000008, + DP_COM_CONF_CSC_DEF_MASK = 0x00000300, + DP_COM_CONF_CSC_DEF_OFFSET = 8, + DP_COM_CONF_CSC_DEF_FG = 0x00000300, + DP_COM_CONF_CSC_DEF_BG = 0x00000200, + DP_COM_CONF_CSC_DEF_BOTH = 0x00000100, + DP_COM_CONF_GAMMA_EN = 0x00001000, + DP_COM_CONF_GAMMA_YUV_EN = 0x00002000, +}; + +enum di_pins { + DI_PIN11 = 0, + DI_PIN12 = 1, + DI_PIN13 = 2, + DI_PIN14 = 3, + DI_PIN15 = 4, + DI_PIN16 = 5, + DI_PIN17 = 6, + DI_PIN_CS = 7, + + DI_PIN_SER_CLK = 0, + DI_PIN_SER_RS = 1, +}; + +enum di_sync_wave { + DI_SYNC_NONE = -1, + DI_SYNC_CLK = 0, + DI_SYNC_INT_HSYNC = 1, + DI_SYNC_HSYNC = 2, + DI_SYNC_VSYNC = 3, + DI_SYNC_DE = 5, +}; + +struct ipu_cm { + u32 conf; + u32 sisg_ctrl0; + u32 sisg_ctrl1; + u32 sisg_set[6]; + u32 sisg_clear[6]; + u32 int_ctrl[15]; + u32 sdma_event[10]; + u32 srm_pri1; + u32 srm_pri2; + u32 fs_proc_flow[3]; + u32 fs_disp_flow[2]; + u32 skip; + u32 disp_alt_conf; + u32 disp_gen; + u32 disp_alt[4]; + u32 snoop; + u32 mem_rst; + u32 pm; + u32 gpr; + u32 reserved0[26]; + u32 ch_db_mode_sel[2]; + u32 reserved1[16]; + u32 alt_ch_db_mode_sel[2]; + u32 reserved2[2]; + u32 ch_trb_mode_sel[2]; +}; + +struct ipu_idmac { + u32 conf; + u32 ch_en[2]; + u32 sep_alpha; + u32 alt_sep_alpha; + u32 ch_pri[2]; + u32 wm_en[2]; + u32 lock_en[2]; + u32 sub_addr[5]; + u32 bndm_en[2]; + u32 sc_cord[2]; + u32 reserved[45]; + u32 ch_busy[2]; +}; + +struct ipu_com_async { + u32 com_conf_async; + u32 graph_wind_ctrl_async; + u32 fg_pos_async; + u32 cur_pos_async; + u32 cur_map_async; + u32 gamma_c_async[8]; + u32 gamma_s_async[4]; + u32 dp_csca_async[4]; + u32 dp_csc_async[2]; +}; + +struct ipu_dp { + u32 com_conf_sync; + u32 graph_wind_ctrl_sync; + u32 fg_pos_sync; + u32 cur_pos_sync; + u32 cur_map_sync; + u32 gamma_c_sync[8]; + u32 gamma_s_sync[4]; + u32 csca_sync[4]; + u32 csc_sync[2]; + u32 cur_pos_alt; + struct ipu_com_async async[2]; +}; + +struct ipu_di { + u32 general; + u32 bs_clkgen0; + u32 bs_clkgen1; + u32 sw_gen0[9]; + u32 sw_gen1[9]; + u32 sync_as; + u32 dw_gen[12]; + u32 dw_set[48]; + u32 stp_rep[4]; + u32 stp_rep9; + u32 ser_conf; + u32 ssc; + u32 pol; + u32 aw0; + u32 aw1; + u32 scr_conf; + u32 stat; +}; + +struct ipu_stat { + u32 int_stat[15]; + u32 cur_buf[2]; + u32 alt_cur_buf_0; + u32 alt_cur_buf_1; + u32 srm_stat; + u32 proc_task_stat; + u32 disp_task_stat; + u32 triple_cur_buf[4]; + u32 ch_buf0_rdy[2]; + u32 ch_buf1_rdy[2]; + u32 alt_ch_buf0_rdy[2]; + u32 alt_ch_buf1_rdy[2]; + u32 ch_buf2_rdy[2]; +}; + +struct ipu_dc_ch { + u32 wr_ch_conf; + u32 wr_ch_addr; + u32 rl[5]; +}; + +struct ipu_dc { + struct ipu_dc_ch dc_ch0_1_2[3]; + u32 cmd_ch_conf_3; + u32 cmd_ch_conf_4; + struct ipu_dc_ch dc_ch5_6[2]; + struct ipu_dc_ch dc_ch8; + u32 rl6_ch_8; + struct ipu_dc_ch dc_ch9; + u32 rl6_ch_9; + u32 gen; + u32 disp_conf1[4]; + u32 disp_conf2[4]; + u32 di0_conf[2]; + u32 di1_conf[2]; + u32 dc_map_ptr[15]; + u32 dc_map_val[12]; + u32 udge[16]; + u32 lla[2]; + u32 r_lla[2]; + u32 wr_ch_addr_5_alt; + u32 stat; +}; + +struct ipu_dmfc { + u32 rd_chan; + u32 wr_chan; + u32 wr_chan_def; + u32 dp_chan; + u32 dp_chan_def; + u32 general[2]; + u32 ic_ctrl; + u32 wr_chan_alt; + u32 wr_chan_def_alt; + u32 general1_alt; + u32 stat; +}; + +#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \ + IPU_CM_REG_BASE)) +#define IPU_CONF (&IPU_CM_REG->conf) +#define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1) +#define IPU_SRM_PRI2 (&IPU_CM_REG->srm_pri2) +#define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0]) +#define IPU_FS_PROC_FLOW2 (&IPU_CM_REG->fs_proc_flow[1]) +#define IPU_FS_PROC_FLOW3 (&IPU_CM_REG->fs_proc_flow[2]) +#define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0]) +#define IPU_DISP_GEN (&IPU_CM_REG->disp_gen) +#define IPU_MEM_RST (&IPU_CM_REG->mem_rst) +#define IPU_GPR (&IPU_CM_REG->gpr) +#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32]) + +#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \ + IPU_STAT_REG_BASE)) +#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32]) +#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32]) +#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32]) + +#define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1]) + +#define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \ + IPU_IDMAC_REG_BASE)) +#define IDMAC_CONF (&IDMAC_REG->conf) +#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32]) +#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32]) + +#define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \ + ((di == 1) ? IPU_DI1_REG_BASE : \ + IPU_DI0_REG_BASE))) +#define DI_GENERAL(di) (&DI_REG(di)->general) +#define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0) +#define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1) + +#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1]) +#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1]) +#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2]) +#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as) +#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen]) +#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set]) +#define DI_POL(di) (&DI_REG(di)->pol) +#define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf) + +#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \ + IPU_DMFC_REG_BASE)) +#define DMFC_WR_CHAN (&DMFC_REG->wr_chan) +#define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def) +#define DMFC_DP_CHAN (&DMFC_REG->dp_chan) +#define DMFC_DP_CHAN_DEF (&DMFC_REG->dp_chan_def) +#define DMFC_GENERAL1 (&DMFC_REG->general[0]) +#define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl) + + +#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \ + IPU_DC_REG_BASE)) +#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2]) +#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2]) + + +static inline struct ipu_dc_ch *dc_ch_offset(int ch) +{ + switch (ch) { + case 0: + case 1: + case 2: + return &DC_REG->dc_ch0_1_2[ch]; + case 5: + case 6: + return &DC_REG->dc_ch5_6[ch - 5]; + case 8: + return &DC_REG->dc_ch8; + case 9: + return &DC_REG->dc_ch9; + default: + printf("%s: invalid channel %d\n", __func__, ch); + return NULL; + } + +} + +#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2]) + +#define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf) +#define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr) + +#define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1) +#define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5) + +#define DC_GEN (&DC_REG->gen) +#define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp]) +#define DC_STAT (&DC_REG->stat) + +#define DP_SYNC 0 +#define DP_ASYNC0 0x60 +#define DP_ASYNC1 0xBC + +#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \ + IPU_DP_REG_BASE)) +#define DP_COM_CONF(flow) (&DP_REG->com_conf_sync) +#define DP_GRAPH_WIND_CTRL(flow) (&DP_REG->graph_wind_ctrl_sync) +#define DP_CSC_A_0(flow) (&DP_REG->csca_sync[0]) +#define DP_CSC_A_1(flow) (&DP_REG->csca_sync[1]) +#define DP_CSC_A_2(flow) (&DP_REG->csca_sync[2]) +#define DP_CSC_A_3(flow) (&DP_REG->csca_sync[3]) + +#define DP_CSC_0(flow) (&DP_REG->csc_sync[0]) +#define DP_CSC_1(flow) (&DP_REG->csc_sync[1]) + +/* DC template opcodes */ +#define WROD(lf) (0x18 | (lf << 1)) + +#endif -- cgit v1.3.1 From 5dda7945d18077db81eb0cfdc2f9d4525e6b77b1 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 13 Oct 2010 12:17:14 +0200 Subject: MX51: Add video support Add framebuffer driver for the MX51 processor working on the IPUv3 internal graphic processor. The port is based on the driver found in the kernel delivered by Freescale as part of i.MX BSP: [kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f] [agust@denx.de: some style fixes and dead code removal] Signed-off-by: Stefano Babic Signed-off-by: Anatolij Gustschin --- drivers/video/Makefile | 1 + drivers/video/mxc_ipuv3_fb.c | 642 +++++++++++++++++++++++++++++++++++++++++++ drivers/video/mxcfb.h | 68 +++++ 3 files changed, 711 insertions(+) create mode 100644 drivers/video/mxc_ipuv3_fb.c create mode 100644 drivers/video/mxcfb.h (limited to 'drivers') diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 4be82e73960..5b7b2612686 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o +COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o COBJS-$(CONFIG_SED156X) += sed156x.o COBJS-$(CONFIG_VIDEO_SM501) += sm501.o diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c new file mode 100644 index 00000000000..a66981c27c9 --- /dev/null +++ b/drivers/video/mxc_ipuv3_fb.c @@ -0,0 +1,642 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * MX51 Linux framebuffer: + * + * (C) Copyright 2004-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "videomodes.h" +#include "ipu.h" +#include "mxcfb.h" + +DECLARE_GLOBAL_DATA_PTR; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +short console_col; +short console_row; + +vidinfo_t panel_info; + +static int mxcfb_map_video_memory(struct fb_info *fbi); +static int mxcfb_unmap_video_memory(struct fb_info *fbi); + +void lcd_initcolregs(void) +{ +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +void lcd_disable(void) +{ +} + +void lcd_panel_disable(void) +{ +} + +void fb_videomode_to_var(struct fb_var_screeninfo *var, + const struct fb_videomode *mode) +{ + var->xres = mode->xres; + var->yres = mode->yres; + var->xres_virtual = mode->xres; + var->yres_virtual = mode->yres; + var->xoffset = 0; + var->yoffset = 0; + var->pixclock = mode->pixclock; + var->left_margin = mode->left_margin; + var->right_margin = mode->right_margin; + var->upper_margin = mode->upper_margin; + var->lower_margin = mode->lower_margin; + var->hsync_len = mode->hsync_len; + var->vsync_len = mode->vsync_len; + var->sync = mode->sync; + var->vmode = mode->vmode & FB_VMODE_MASK; +} + +/* + * Structure containing the MXC specific framebuffer information. + */ +struct mxcfb_info { + int blank; + ipu_channel_t ipu_ch; + int ipu_di; + u32 ipu_di_pix_fmt; + unsigned char overlay; + unsigned char alpha_chan_en; + dma_addr_t alpha_phy_addr0; + dma_addr_t alpha_phy_addr1; + void *alpha_virt_addr0; + void *alpha_virt_addr1; + uint32_t alpha_mem_len; + uint32_t cur_ipu_buf; + uint32_t cur_ipu_alpha_buf; + + u32 pseudo_palette[16]; +}; + +enum { + BOTH_ON, + SRC_ON, + TGT_ON, + BOTH_OFF +}; + +static unsigned long default_bpp = 16; +static unsigned char g_dp_in_use; +static struct fb_info *mxcfb_info[3]; +static int ext_clk_used; + +static uint32_t bpp_to_pixfmt(struct fb_info *fbi) +{ + uint32_t pixfmt = 0; + + debug("bpp_to_pixfmt: %d\n", fbi->var.bits_per_pixel); + + if (fbi->var.nonstd) + return fbi->var.nonstd; + + switch (fbi->var.bits_per_pixel) { + case 24: + pixfmt = IPU_PIX_FMT_BGR24; + break; + case 32: + pixfmt = IPU_PIX_FMT_BGR32; + break; + case 16: + pixfmt = IPU_PIX_FMT_RGB565; + break; + } + return pixfmt; +} + +/* + * Set fixed framebuffer parameters based on variable settings. + * + * @param info framebuffer information pointer + */ +static int mxcfb_set_fix(struct fb_info *info) +{ + struct fb_fix_screeninfo *fix = &info->fix; + struct fb_var_screeninfo *var = &info->var; + + fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; + + fix->type = FB_TYPE_PACKED_PIXELS; + fix->accel = FB_ACCEL_NONE; + fix->visual = FB_VISUAL_TRUECOLOR; + fix->xpanstep = 1; + fix->ypanstep = 1; + + return 0; +} + +static int setup_disp_channel1(struct fb_info *fbi) +{ + ipu_channel_params_t params; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + + memset(¶ms, 0, sizeof(params)); + params.mem_dp_bg_sync.di = mxc_fbi->ipu_di; + + debug("%s called\n", __func__); + /* + * Assuming interlaced means yuv output, below setting also + * valid for mem_dc_sync. FG should have the same vmode as BG. + */ + if (fbi->var.vmode & FB_VMODE_INTERLACED) { + params.mem_dp_bg_sync.interlaced = 1; + params.mem_dp_bg_sync.out_pixel_fmt = + IPU_PIX_FMT_YUV444; + } else { + if (mxc_fbi->ipu_di_pix_fmt) { + params.mem_dp_bg_sync.out_pixel_fmt = + mxc_fbi->ipu_di_pix_fmt; + } else { + params.mem_dp_bg_sync.out_pixel_fmt = + IPU_PIX_FMT_RGB666; + } + } + params.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi); + if (mxc_fbi->alpha_chan_en) + params.mem_dp_bg_sync.alpha_chan_en = 1; + + ipu_init_channel(mxc_fbi->ipu_ch, ¶ms); + + return 0; +} + +static int setup_disp_channel2(struct fb_info *fbi) +{ + int retval = 0; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + + mxc_fbi->cur_ipu_buf = 1; + if (mxc_fbi->alpha_chan_en) + mxc_fbi->cur_ipu_alpha_buf = 1; + + fbi->var.xoffset = fbi->var.yoffset = 0; + + debug("%s: %x %d %d %d %lx %lx\n", + __func__, + mxc_fbi->ipu_ch, + fbi->var.xres, + fbi->var.yres, + fbi->fix.line_length, + fbi->fix.smem_start, + fbi->fix.smem_start + + (fbi->fix.line_length * fbi->var.yres)); + + retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER, + bpp_to_pixfmt(fbi), + fbi->var.xres, fbi->var.yres, + fbi->fix.line_length, + fbi->fix.smem_start + + (fbi->fix.line_length * fbi->var.yres), + fbi->fix.smem_start, + 0, 0); + if (retval) + printf("ipu_init_channel_buffer error %d\n", retval); + + return retval; +} + +/* + * Set framebuffer parameters and change the operating mode. + * + * @param info framebuffer information pointer + */ +static int mxcfb_set_par(struct fb_info *fbi) +{ + int retval = 0; + u32 mem_len; + ipu_di_signal_cfg_t sig_cfg; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + uint32_t out_pixel_fmt; + + ipu_disable_channel(mxc_fbi->ipu_ch); + ipu_uninit_channel(mxc_fbi->ipu_ch); + mxcfb_set_fix(fbi); + + mem_len = fbi->var.yres_virtual * fbi->fix.line_length; + if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) { + if (fbi->fix.smem_start) + mxcfb_unmap_video_memory(fbi); + + if (mxcfb_map_video_memory(fbi) < 0) + return -ENOMEM; + } + + setup_disp_channel1(fbi); + + memset(&sig_cfg, 0, sizeof(sig_cfg)); + if (fbi->var.vmode & FB_VMODE_INTERLACED) { + sig_cfg.interlaced = 1; + out_pixel_fmt = IPU_PIX_FMT_YUV444; + } else { + if (mxc_fbi->ipu_di_pix_fmt) + out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt; + else + out_pixel_fmt = IPU_PIX_FMT_RGB666; + } + if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */ + sig_cfg.odd_field_first = 1; + if ((fbi->var.sync & FB_SYNC_EXT) || ext_clk_used) + sig_cfg.ext_clk = 1; + if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT) + sig_cfg.Hsync_pol = 1; + if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) + sig_cfg.Vsync_pol = 1; + if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL)) + sig_cfg.clk_pol = 1; + if (fbi->var.sync & FB_SYNC_DATA_INVERT) + sig_cfg.data_pol = 1; + if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT)) + sig_cfg.enable_pol = 1; + if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN) + sig_cfg.clkidle_en = 1; + + debug("pixclock = %ul Hz\n", + (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); + + if (ipu_init_sync_panel(mxc_fbi->ipu_di, + (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, + fbi->var.xres, fbi->var.yres, + out_pixel_fmt, + fbi->var.left_margin, + fbi->var.hsync_len, + fbi->var.right_margin, + fbi->var.upper_margin, + fbi->var.vsync_len, + fbi->var.lower_margin, + 0, sig_cfg) != 0) { + puts("mxcfb: Error initializing panel.\n"); + return -EINVAL; + } + + retval = setup_disp_channel2(fbi); + if (retval) + return retval; + + if (mxc_fbi->blank == FB_BLANK_UNBLANK) + ipu_enable_channel(mxc_fbi->ipu_ch); + + return retval; +} + +/* + * Check framebuffer variable parameters and adjust to valid values. + * + * @param var framebuffer variable parameters + * + * @param info framebuffer information pointer + */ +static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + u32 vtotal; + u32 htotal; + + if (var->xres_virtual < var->xres) + var->xres_virtual = var->xres; + if (var->yres_virtual < var->yres) + var->yres_virtual = var->yres; + + if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && + (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8)) + var->bits_per_pixel = default_bpp; + + switch (var->bits_per_pixel) { + case 8: + var->red.length = 3; + var->red.offset = 5; + var->red.msb_right = 0; + + var->green.length = 3; + var->green.offset = 2; + var->green.msb_right = 0; + + var->blue.length = 2; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 16: + var->red.length = 5; + var->red.offset = 11; + var->red.msb_right = 0; + + var->green.length = 6; + var->green.offset = 5; + var->green.msb_right = 0; + + var->blue.length = 5; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 24: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 32: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 8; + var->transp.offset = 24; + var->transp.msb_right = 0; + break; + } + + if (var->pixclock < 1000) { + htotal = var->xres + var->right_margin + var->hsync_len + + var->left_margin; + vtotal = var->yres + var->lower_margin + var->vsync_len + + var->upper_margin; + var->pixclock = (vtotal * htotal * 6UL) / 100UL; + var->pixclock = KHZ2PICOS(var->pixclock); + printf("pixclock set for 60Hz refresh = %u ps\n", + var->pixclock); + } + + var->height = -1; + var->width = -1; + var->grayscale = 0; + + return 0; +} + +static int mxcfb_map_video_memory(struct fb_info *fbi) +{ + if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) { + fbi->fix.smem_len = fbi->var.yres_virtual * + fbi->fix.line_length; + } + + fbi->screen_base = (char *)lcd_base; + fbi->fix.smem_start = (unsigned long)lcd_base; + if (fbi->screen_base == 0) { + puts("Unable to allocate framebuffer memory\n"); + fbi->fix.smem_len = 0; + fbi->fix.smem_start = 0; + return -EBUSY; + } + + debug("allocated fb @ paddr=0x%08X, size=%d.\n", + (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len); + + fbi->screen_size = fbi->fix.smem_len; + + /* Clear the screen */ + memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); + + return 0; +} + +static int mxcfb_unmap_video_memory(struct fb_info *fbi) +{ + fbi->screen_base = 0; + fbi->fix.smem_start = 0; + fbi->fix.smem_len = 0; + return 0; +} + +/* + * Initializes the framebuffer information pointer. After allocating + * sufficient memory for the framebuffer structure, the fields are + * filled with custom information passed in from the configurable + * structures. This includes information such as bits per pixel, + * color maps, screen width/height and RGBA offsets. + * + * @return Framebuffer structure initialized with our information + */ +static struct fb_info *mxcfb_init_fbinfo(void) +{ +#define BYTES_PER_LONG 4 +#define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG)) + struct fb_info *fbi; + struct mxcfb_info *mxcfbi; + char *p; + int size = sizeof(struct mxcfb_info) + PADDING + + sizeof(struct fb_info); + + debug("%s: %d %d %d %d\n", + __func__, + PADDING, + size, + sizeof(struct mxcfb_info), + sizeof(struct fb_info)); + /* + * Allocate sufficient memory for the fb structure + */ + + p = malloc(size); + if (!p) + return NULL; + + memset(p, 0, size); + + fbi = (struct fb_info *)p; + fbi->par = p + sizeof(struct fb_info) + PADDING; + + mxcfbi = (struct mxcfb_info *)fbi->par; + debug("Framebuffer structures at: fbi=0x%x mxcfbi=0x%x\n", + (unsigned int)fbi, (unsigned int)mxcfbi); + + fbi->var.activate = FB_ACTIVATE_NOW; + + fbi->flags = FBINFO_FLAG_DEFAULT; + fbi->pseudo_palette = mxcfbi->pseudo_palette; + + return fbi; +} + +/* + * Probe routine for the framebuffer driver. It is called during the + * driver binding process. The following functions are performed in + * this routine: Framebuffer initialization, Memory allocation and + * mapping, Framebuffer registration, IPU initialization. + * + * @return Appropriate error code to the kernel common code + */ +static int mxcfb_probe(u32 interface_pix_fmt, struct fb_videomode *mode) +{ + struct fb_info *fbi; + struct mxcfb_info *mxcfbi; + int ret = 0; + + /* + * Initialize FB structures + */ + fbi = mxcfb_init_fbinfo(); + if (!fbi) { + ret = -ENOMEM; + goto err0; + } + mxcfbi = (struct mxcfb_info *)fbi->par; + + if (!g_dp_in_use) { + mxcfbi->ipu_ch = MEM_BG_SYNC; + mxcfbi->blank = FB_BLANK_UNBLANK; + } else { + mxcfbi->ipu_ch = MEM_DC_SYNC; + mxcfbi->blank = FB_BLANK_POWERDOWN; + } + + mxcfbi->ipu_di = 0; + + ipu_disp_set_global_alpha(mxcfbi->ipu_ch, 1, 0x80); + ipu_disp_set_color_key(mxcfbi->ipu_ch, 0, 0); + strcpy(fbi->fix.id, "DISP3 BG"); + + g_dp_in_use = 1; + + mxcfb_info[mxcfbi->ipu_di] = fbi; + + /* Need dummy values until real panel is configured */ + fbi->var.xres = 640; + fbi->var.yres = 480; + fbi->var.bits_per_pixel = 16; + + mxcfbi->ipu_di_pix_fmt = interface_pix_fmt; + fb_videomode_to_var(&fbi->var, mode); + + mxcfb_check_var(&fbi->var, fbi); + + /* Default Y virtual size is 2x panel size */ + fbi->var.yres_virtual = fbi->var.yres * 2; + + mxcfb_set_fix(fbi); + + /* alocate fb first */ + if (mxcfb_map_video_memory(fbi) < 0) + return -ENOMEM; + + mxcfb_set_par(fbi); + + /* Setting panel_info for lcd */ + panel_info.cmap = NULL; + panel_info.vl_col = fbi->var.xres; + panel_info.vl_row = fbi->var.yres; + panel_info.vl_bpix = LCD_BPP; + + lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; + + debug("MXC IPUV3 configured\n" + "XRES = %d YRES = %d BitsXpixel = %d\n", + panel_info.vl_col, + panel_info.vl_row, + panel_info.vl_bpix); + + ipu_dump_registers(); + + return 0; + +err0: + return ret; +} + +int overwrite_console(void) +{ + /* Keep stdout / stderr on serial, our LCD is for splashscreen only */ + return 1; +} + +void lcd_ctrl_init(void *lcdbase) +{ + u32 mem_len = panel_info.vl_col * + panel_info.vl_row * + NBITS(panel_info.vl_bpix) / 8; + + /* + * We rely on lcdbase being a physical address, i.e., either MMU off, + * or 1-to-1 mapping. Might want to add some virt2phys here. + */ + if (!lcdbase) + return; + + memset(lcdbase, 0, mem_len); +} + +int mx51_fb_init(struct fb_videomode *mode) +{ + int ret; + + ret = ipu_probe(); + if (ret) + puts("Error initializing IPU\n"); + + lcd_base += 56; + + debug("Framebuffer at 0x%x\n", (unsigned int)lcd_base); + ret = mxcfb_probe(IPU_PIX_FMT_RGB666, mode); + + return ret; +} diff --git a/drivers/video/mxcfb.h b/drivers/video/mxcfb.h new file mode 100644 index 00000000000..d508196603b --- /dev/null +++ b/drivers/video/mxcfb.h @@ -0,0 +1,68 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * Linux IPU driver for MX51: + * + * (C) Copyright 2004-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MXCFB_H__ +#define __ASM_ARCH_MXCFB_H__ + +#define FB_SYNC_OE_LOW_ACT 0x80000000 +#define FB_SYNC_CLK_LAT_FALL 0x40000000 +#define FB_SYNC_DATA_INVERT 0x20000000 +#define FB_SYNC_CLK_IDLE_EN 0x10000000 +#define FB_SYNC_SHARP_MODE 0x08000000 +#define FB_SYNC_SWAP_RGB 0x04000000 + +struct mxcfb_gbl_alpha { + int enable; + int alpha; +}; + +struct mxcfb_loc_alpha { + int enable; + int alpha_in_pixel; + unsigned long alpha_phy_addr0; + unsigned long alpha_phy_addr1; +}; + +struct mxcfb_color_key { + int enable; + __u32 color_key; +}; + +struct mxcfb_pos { + __u16 x; + __u16 y; +}; + +struct mxcfb_gamma { + int enable; + int constk[16]; + int slopek[16]; +}; + +#endif -- cgit v1.3.1 From 96d6160324c49c81df10b6b4c75d2470cb30dce4 Mon Sep 17 00:00:00 2001 From: John Schmoller Date: Fri, 22 Oct 2010 00:20:23 -0500 Subject: pci: Add ability to re-enumerate PCI buses Add a new 'pci enum' command which re-enumerates the PCI buses. This command is enabled via the CONFIG_CMD_PCI_ENUM define and can be useful in boards with FPGAs connected via PCI/PCIe, boards that support PCI hot-plugging, or during PCI debug. Also enable the 'pci enum' command for X-ES's Freescale-based boards. Signed-off-by: John Schmoller Signed-off-by: Peter Tyser Acked-by: Kumar Gala Acked-by: Wolfgang Denk --- common/cmd_pci.c | 13 +++++++++++++ drivers/pci/fsl_pci_init.c | 3 +++ drivers/pci/pci.c | 4 +++- include/configs/XPEDITE5170.h | 1 + include/configs/XPEDITE5200.h | 1 + include/configs/XPEDITE5370.h | 1 + 6 files changed, 22 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/common/cmd_pci.c b/common/cmd_pci.c index 4bde0599118..ccf5adaaad6 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -497,6 +497,10 @@ int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((bdf = get_pci_dev(argv[2])) == -1) return 1; break; +#ifdef CONFIG_CMD_PCI_ENUM + case 'e': + break; +#endif default: /* scan bus */ value = 1; /* short listing */ bdf = 0; /* bus number */ @@ -518,6 +522,11 @@ int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; case 'd': /* display */ return pci_cfg_display(bdf, addr, size, value); +#ifdef CONFIG_CMD_PCI_ENUM + case 'e': + pci_init(); + return 0; +#endif case 'n': /* next */ if (argc < 4) goto usage; @@ -545,6 +554,10 @@ U_BOOT_CMD( "list and access PCI Configuration Space", "[bus] [long]\n" " - short or long list of PCI devices on bus 'bus'\n" +#ifdef CONFIG_CMD_PCI_ENUM + "pci enum\n" + " - re-enumerate PCI buses\n" +#endif "pci header b.d.f\n" " - show header of PCI device 'bus.device.function'\n" "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n" diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 001e6eb9007..1f021036e5f 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -91,6 +91,9 @@ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr; + /* Reset hose to make sure its in a clean state */ + memset(hose, 0, sizeof(struct pci_controller)); + pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); return fsl_is_pci_agent(hose); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index cd64a87fc6d..848746f1ed2 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -139,7 +139,7 @@ void *pci_map_bar(pci_dev_t pdev, int bar, int flags) * */ -static struct pci_controller* hose_head = NULL; +static struct pci_controller* hose_head; void pci_register_hose(struct pci_controller* hose) { @@ -640,6 +640,8 @@ void pci_init(void) } #endif /* CONFIG_PCI_BOOTDELAY */ + hose_head = NULL; + /* now call board specific pci_init()... */ pci_init_board(); } diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h index 9ff28a29132..ab6d4b4ecb3 100644 --- a/include/configs/XPEDITE5170.h +++ b/include/configs/XPEDITE5170.h @@ -545,6 +545,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_PCA953X #define CONFIG_CMD_PCA953X_INFO #define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SNTP diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index db03777a79d..00cd5162812 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -339,6 +339,7 @@ #define CONFIG_CMD_PCA953X #define CONFIG_CMD_PCA953X_INFO #define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM #define CONFIG_CMD_PING #define CONFIG_CMD_SNTP #define CONFIG_CMD_REGINFO diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 01047c85eee..73e3d52e835 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -396,6 +396,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_PCA953X #define CONFIG_CMD_PCA953X_INFO #define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI_ENUM #define CONFIG_CMD_PING #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SNTP -- cgit v1.3.1 From af68c066709f20fcfd0ce6cd955bfbe4642d0a15 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 15 Oct 2010 15:53:45 +0200 Subject: ehci-pci: print hccr, hcor and hc_lenght It is useful to know the EHCI-PCI hccr, hcor and hc_lenght to make sure it was successfully registered, and at the correct location. Signed-off-by: Florian Fainelli --- drivers/usb/host/ehci-pci.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 047902a0c1c..cff34389295 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -53,6 +53,10 @@ int ehci_hcd_init(void) hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", + (uint32_t)hccr, (uint32_t)hcor, + (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + return 0; } -- cgit v1.3.1 From 8b675fe18e03d31f1c2a2ad576eab7e57c404751 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 20 Oct 2010 21:08:17 +0200 Subject: USB: fix Queue Element Transfer Descriptor changes Commit 3ed1607 "USB: sync Queue Element Transfer Descriptor against EHCI spec" added an "__attribute__ ((aligned (32)))" to the declaration of struct qTD, as used for example in the Linux kernel as well. However, it turns out that this attribute causes errors in "usb start" (like "ERROR: NOT USB_CONFIG_DESC 7b" and similar). Drop the attribute again. Signed-off-by: Wolfgang Denk Cc: Dan Lykowski Cc: Remy Bohmer Cc: Stefano Babic --- drivers/usb/host/ehci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index d3aa55b4a6c..945ab64f951 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -175,7 +175,7 @@ struct qTD { uint32_t qt_buffer_hi[5]; /* Appendix B */ /* pad struct for 32 byte alignment */ uint32_t unused[3]; -} __attribute__ ((aligned (32))); +}; /* Queue Head (QH). */ struct QH { -- cgit v1.3.1 From 0228348e9c0361dcb1c7e2678a3d899aca15f258 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 20 Oct 2010 07:15:35 -0400 Subject: usb: musb: constify a bit These ep and root hub structures need not be writable. Signed-off-by: Mike Frysinger --- drivers/usb/musb/musb_core.c | 2 +- drivers/usb/musb/musb_core.h | 2 +- drivers/usb/musb/musb_hcd.c | 36 +++++++++++++++++++----------------- 3 files changed, 21 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index 6fe2c39bce8..545ebf4b502 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -76,7 +76,7 @@ void musb_start(void) * epinfo - Pointer to EP configuration table * cnt - Number of entries in the EP conf table. */ -void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt) +void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt) { u16 csr; u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */ diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index 8f73876f806..a8adcce00fa 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -357,7 +357,7 @@ extern struct musb_regs *musbr; /* exported functions */ extern void musb_start(void); -extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt); +extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt); extern void write_fifo(u8 ep, u32 length, void *fifo_data); extern void read_fifo(u8 ep, u32 length, void *fifo_data); diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c index f38b279096c..8b0c61d6426 100644 --- a/drivers/usb/musb/musb_hcd.c +++ b/drivers/usb/musb/musb_hcd.c @@ -29,7 +29,7 @@ #define USB_MSC_BBB_GET_MAX_LUN 0xFE /* Endpoint configuration information */ -static struct musb_epinfo epinfo[3] = { +static const struct musb_epinfo epinfo[3] = { {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */ {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */ {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */ @@ -41,7 +41,7 @@ static int rh_devnum; static u32 port_status; /* Device descriptor */ -static u8 root_hub_dev_des[] = { +static const u8 root_hub_dev_des[] = { 0x12, /* __u8 bLength; */ 0x01, /* __u8 bDescriptorType; Device */ 0x00, /* __u16 bcdUSB; v1.1 */ @@ -63,7 +63,7 @@ static u8 root_hub_dev_des[] = { }; /* Configuration descriptor */ -static u8 root_hub_config_des[] = { +static const u8 root_hub_config_des[] = { 0x09, /* __u8 bLength; */ 0x02, /* __u8 bDescriptorType; Configuration */ 0x19, /* __u16 wTotalLength; */ @@ -96,14 +96,14 @@ static u8 root_hub_config_des[] = { 0xff /* __u8 ep_bInterval; 255 ms */ }; -static unsigned char root_hub_str_index0[] = { +static const unsigned char root_hub_str_index0[] = { 0x04, /* __u8 bLength; */ 0x03, /* __u8 bDescriptorType; String-descriptor */ 0x09, /* __u8 lang ID */ 0x04, /* __u8 lang ID */ }; -static unsigned char root_hub_str_index1[] = { +static const unsigned char root_hub_str_index1[] = { 0x1c, /* __u8 bLength; */ 0x03, /* __u8 bDescriptorType; String-descriptor */ 'M', /* __u8 Unicode */ @@ -557,7 +557,7 @@ static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe, int len = 0; int stat = 0; u32 datab[4]; - u8 *data_buf = (u8 *) datab; + const u8 *data_buf = (u8 *) datab; u16 bmRType_bReq; u16 wValue; u16 wIndex; @@ -778,25 +778,27 @@ static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe, break; - case RH_GET_DESCRIPTOR | RH_CLASS: + case RH_GET_DESCRIPTOR | RH_CLASS: { + u8 *_data_buf = (u8 *) datab; debug("RH_GET_DESCRIPTOR | RH_CLASS\n"); - data_buf[0] = 0x09; /* min length; */ - data_buf[1] = 0x29; - data_buf[2] = 0x1; /* 1 port */ - data_buf[3] = 0x01; /* per-port power switching */ - data_buf[3] |= 0x10; /* no overcurrent reporting */ + _data_buf[0] = 0x09; /* min length; */ + _data_buf[1] = 0x29; + _data_buf[2] = 0x1; /* 1 port */ + _data_buf[3] = 0x01; /* per-port power switching */ + _data_buf[3] |= 0x10; /* no overcurrent reporting */ /* Corresponds to data_buf[4-7] */ - data_buf[4] = 0; - data_buf[5] = 5; - data_buf[6] = 0; - data_buf[7] = 0x02; - data_buf[8] = 0xff; + _data_buf[4] = 0; + _data_buf[5] = 5; + _data_buf[6] = 0; + _data_buf[7] = 0x02; + _data_buf[8] = 0xff; len = min_t(unsigned int, leni, min_t(unsigned int, data_buf[0], wLength)); break; + } case RH_GET_CONFIGURATION: debug("RH_GET_CONFIGURATION\n"); -- cgit v1.3.1 From 09c83a45b797aefbb41115af1b348494740460ce Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 22 Oct 2010 14:23:00 +0200 Subject: ehci-hcd.c: fix hanging under higher load This patch solves a problem with USB hanging under higher load on a i.MX31 board. It falls into class of typical USB problems and fixes: if you don't understand the real cause, add a delay somewhere. The problem appeared after introduction of ELF relocation, which results in smaller code, which appears to run faster (probably because it fits better in the cache); turning off the instruction cache, adding debug printf()s and increasing the delay have all been found to make the problem go away. Moving the original "udelay(1)" up in the code to it's new place made the problem appear much less frequently. Increasing the delay to 2 microseconds then made the code run reliably in all (hour-long) tests. To be on the safe side, we set it to 5 microseconds here. Signed-off-by: Heiko schocher Signed-off-by: Wolfgang Denk Cc: Remy Bohmer Cc: Stefano Babic --- drivers/usb/host/ehci-hcd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index f44fc4e3c4b..982f96e8b8f 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -205,12 +205,12 @@ static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) uint32_t result; do { result = ehci_readl(ptr); + udelay(5); if (result == ~(uint32_t)0) return -1; result &= mask; if (result == done) return 0; - udelay(1); usec--; } while (usec > 0); return -1; -- cgit v1.3.1 From ec50a8e389863ac35bfd9d9a2e8b30187318e59e Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Thu, 21 Oct 2010 17:20:12 +0200 Subject: cfi_flash: handle 'chip size exceeds address window' situation On some boards we have flash mapped high in the address space with considerably small window (say 0xFE000000 and 32MB). When we install bigger chip (say 64MB) on such a board strange things happen (flash_write() doesn't work at all, for ex). That's because cfi_flash driver doesn't care about window size at all. Of course, cleanest solution would probably be to just extend address window to be able to map the whole flash but for legacy/compatibility reasons some people prefer just truncate the flash size and never use the upper part. This patch adds an option for cfi_flash driver to handle this situation properly. To achieve this we add the new function cfi_flash_bank_size() which can be provided by the board code and weak-aliased to default implementation that returns value from the CONFIG_SYS_FLASH_BANKS_SIZES array if it's defined or 0 otherwise (the last case is added for compatibility). If non-zero flash bank size is provided and detected chip size is bigger than provided address window size the warning will be displayed and flash chip will be truncated. Signed-off-by: Ilya Yanok Changed cfi_flash_bank_size() return type to unsigned long to match caller function. Signed-off-by: Wolfgang Denk --- drivers/mtd/cfi_flash.c | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 798902f3376..c92c7a7a490 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -85,6 +85,17 @@ static phys_addr_t __cfi_flash_bank_addr(int i) phys_addr_t cfi_flash_bank_addr(int i) __attribute__((weak, alias("__cfi_flash_bank_addr"))); +static unsigned long __cfi_flash_bank_size(int i) +{ +#ifdef CONFIG_SYS_FLASH_BANKS_SIZES + return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; +#else + return 0; +#endif +} +unsigned long cfi_flash_bank_size(int i) + __attribute__((weak, alias("__cfi_flash_bank_size"))); + static void __flash_write8(u8 value, void *addr) { __raw_writeb(value, addr); @@ -1826,7 +1837,7 @@ static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) * The following code cannot be run from FLASH! * */ -ulong flash_get_size (phys_addr_t base, int banknum) +ulong flash_get_size (phys_addr_t base, int banknum, unsigned long max_size) { flash_info_t *info = &flash_info[banknum]; int i, j; @@ -1915,6 +1926,13 @@ ulong flash_get_size (phys_addr_t base, int banknum) debug ("size_ratio %d port %d bits chip %d bits\n", size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + info->size = 1 << qry.dev_size; + /* multiply the size by the number of chips */ + info->size *= size_ratio; + if (max_size && (info->size > max_size)) { + debug("[truncated from %ldMiB]", info->size >> 20); + info->size = max_size; + } debug ("found %d erase regions\n", num_erase_regions); sect_cnt = 0; sector = base; @@ -1935,6 +1953,8 @@ ulong flash_get_size (phys_addr_t base, int banknum) debug ("erase_region_count = %d erase_region_size = %d\n", erase_region_count, erase_region_size); for (j = 0; j < erase_region_count; j++) { + if (sector - base >= info->size) + break; if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { printf("ERROR: too many flash sectors\n"); break; @@ -1968,9 +1988,6 @@ ulong flash_get_size (phys_addr_t base, int banknum) } info->sector_count = sect_cnt; - info->size = 1 << qry.dev_size; - /* multiply the size by the number of chips */ - info->size *= size_ratio; info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); tmp = 1 << qry.block_erase_timeout_typ; info->erase_blk_tout = tmp * @@ -2026,7 +2043,8 @@ unsigned long flash_init (void) flash_info[i].flash_id = FLASH_UNKNOWN; if (!flash_detect_legacy(cfi_flash_bank_addr(i), i)) - flash_get_size(cfi_flash_bank_addr(i), i); + flash_get_size(cfi_flash_bank_addr(i), i, + cfi_flash_bank_size(i)); size += flash_info[i].size; if (flash_info[i].flash_id == FLASH_UNKNOWN) { #ifndef CONFIG_SYS_FLASH_QUIET_TEST -- cgit v1.3.1 From 4df66894954ec6411d22e3a86070014d74bafb5c Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Fri, 22 Oct 2010 13:48:00 -0700 Subject: ARMV7: OMAP: I2C driver: Fix bug found in 37XX testing On OMAP36/37XX the standard on chip pullups are not sufficient to ensure proper i2c operation without external pullups or switching to high speed mode and enabling special on chip pullups. This is an issue for Beagle xM, which does not have external pullups on the expansion board i2c lines. The issue manifests itself as an AL (arbitration lost) error when probing for a non-existent device (i.e. on a Beagle xM with no expansion boards attached). This issue does not occur on expansion boards that include pullups or on Overo 37XX COM's since they include pull-ups. This patch fixes the issue by checking for the AL bit in the i2c_probe function. Signed-off-by: Steve Sakoman --- drivers/i2c/omap24xx_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index a72d1a12570..fab49fd969e 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -329,7 +329,7 @@ int i2c_probe (uchar chip) while (1) { status = wait_for_pin(); - if (status == 0) { + if (status == 0 || status & I2C_STAT_AL) { res = 1; goto probe_exit; } -- cgit v1.3.1 From 0158126e252b6860e7a7d8408d0872278a3483cf Mon Sep 17 00:00:00 2001 From: Lei Wen Date: Thu, 14 Oct 2010 13:38:11 +0800 Subject: mmc: seperate block number into small parts for multi-write cmd Constraint the mmc framework to only send no more than 65535 blocks in one go during the multi-write command. This constraint comes due to the limitation of 16bit width block counter register at some hardware. Signed-off-by: Lei Wen Cc: Reinhard Meyer --- drivers/mmc/mmc.c | 54 +++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 39 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c543d837dc7..eb7bfb39e92 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -78,17 +78,11 @@ struct mmc *find_mmc_device(int dev_num) } static ulong -mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src) +mmc_write_blocks(struct mmc *mmc, ulong start, lbaint_t blkcnt, const void*src) { struct mmc_cmd cmd; struct mmc_data data; - int err; - int stoperr = 0; - struct mmc *mmc = find_mmc_device(dev_num); - int blklen; - - if (!mmc) - return -1; + int blklen, err; blklen = mmc->write_bl_len; @@ -97,12 +91,6 @@ mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src) start + blkcnt, mmc->block_dev.lba); return 0; } - err = mmc_set_blocklen(mmc, mmc->write_bl_len); - - if (err) { - printf("set write bl len failed\n\r"); - return err; - } if (blkcnt > 1) cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK; @@ -134,9 +122,45 @@ mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src) cmd.cmdarg = 0; cmd.resp_type = MMC_RSP_R1b; cmd.flags = 0; - stoperr = mmc_send_cmd(mmc, &cmd, NULL); + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) { + printf("mmc fail to send stop cmd\n\r"); + return err; + } + } + + return blkcnt; +} + +static ulong +mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src) +{ + int err; + struct mmc *mmc = find_mmc_device(dev_num); + lbaint_t cur, blocks_todo = blkcnt; + + if (!mmc) + return -1; + + err = mmc_set_blocklen(mmc, mmc->write_bl_len); + if (err) { + printf("set write bl len failed\n\r"); + return err; } + do { + /* + * The 65535 constraint comes from some hardware has + * only 16 bit width block number counter + */ + cur = (blocks_todo > 65535) ? 65535 : blocks_todo; + if(mmc_write_blocks(mmc, start, cur, src) != cur) + return -1; + blocks_todo -= cur; + start += cur; + src += cur * mmc->write_bl_len; + } while (blocks_todo > 0); + return blkcnt; } -- cgit v1.3.1 From 071bc923308832bbc541a887fece767d79a6dc7a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 27 Oct 2010 22:48:30 +0200 Subject: Coding Style cleanup Signed-off-by: Wolfgang Denk --- MAKEALL | 2 +- README | 10 +-- arch/arm/cpu/arm926ejs/kirkwood/dram.c | 1 - arch/arm/cpu/pxa/cpu.c | 2 +- arch/microblaze/cpu/start.S | 2 +- arch/sh/lib/bootm.c | 2 +- board/bct-brettl2/cled.c | 2 +- board/davedenx/qong/fpga.c | 1 - board/isee/igep0030/config.mk | 1 - board/xes/common/fsl_8xxx_misc.c | 10 ++- board/xes/xpedite550x/ddr.c | 21 +++--- doc/README.arm-relocation | 14 ++-- drivers/fpga/lattice.c | 2 - drivers/mmc/omap_hsmmc.c | 1 - drivers/serial/atmel_usart.h | 2 +- drivers/usb/gadget/config.c | 1 - drivers/usb/gadget/epautoconf.c | 1 - drivers/usb/gadget/ether.c | 1 - drivers/usb/gadget/usbstring.c | 1 - include/configs/a4m072.h | 2 +- include/configs/bct-brettl2.h | 24 +++---- include/configs/blackvme.h | 4 +- include/configs/mx1ads.h | 5 -- include/configs/mx1fs2.h | 5 -- include/configs/scb9328.h | 15 ----- include/lattice.h | 1 - include/linux/fb.h | 120 ++++++++++++++++----------------- include/linux/kbuild.h | 2 +- include/linux/usb/cdc.h | 4 -- lib/hashtable.c | 12 ++-- lib/qsort.c | 6 +- post/board/lwmon5/fpga.c | 2 - 32 files changed, 117 insertions(+), 162 deletions(-) (limited to 'drivers') diff --git a/MAKEALL b/MAKEALL index db11f134b8b..c54c6e8cf95 100755 --- a/MAKEALL +++ b/MAKEALL @@ -56,7 +56,7 @@ LONG_OPTS="arch:,cpu:,vendor:,soc:" # Option processing based on util-linux-2.13/getopt-parse.bash -# Note that we use `"$@"' to let each command-line parameter expand to a +# Note that we use `"$@"' to let each command-line parameter expand to a # separate word. The quotes around `$@' are essential! # We need TEMP as the `eval set --' would nuke the return value of # getopt. diff --git a/README b/README index 3d8742386c0..f559811278d 100644 --- a/README +++ b/README @@ -2364,11 +2364,11 @@ Configuration Settings: - CONFIG_ENV_MAX_ENTRIES - Maximum number of entries in the hash table that is used - internally to store the environment settings. The default - setting is supposed to be generous and should work in most - cases. This setting can be used to tune behaviour; see - lib/hashtable.c for details. + Maximum number of entries in the hash table that is used + internally to store the environment settings. The default + setting is supposed to be generous and should work in most + cases. This setting can be used to tune behaviour; see + lib/hashtable.c for details. The following definitions that deal with the placement and management of environment data (variable area); in general, we support the diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c index 7439c87f681..342afe9cd06 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c @@ -93,4 +93,3 @@ void dram_init_banksize(void) dram_init(); } #endif /* CONFIG_SYS_BOARD_DRAM_INIT */ - diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c index 3ea34582e7a..7d49cbb4fd9 100644 --- a/arch/arm/cpu/pxa/cpu.c +++ b/arch/arm/cpu/pxa/cpu.c @@ -312,7 +312,7 @@ void pxa_wakeup(void) int arch_cpu_init(void) { pxa_gpio_setup(); -// pxa_wait_ticks(0x8000); +/* pxa_wait_ticks(0x8000); */ pxa_wakeup(); pxa_interrupt_setup(); pxa_clock_setup(); diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index d44903b2b8f..93a9efdf106 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -98,7 +98,7 @@ _start: * 0xC: 0xB808XXXX * * then it is necessary to count address for storing the most significant - * 16bits from _exception_handler address and copy it to + * 16bits from _exception_handler address and copy it to * 0xa address. Big endian use offset in r10=0 that's why is it just * 0xa address. The same is done for the least significant 16 bits * for 0xe address. diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index f38d0b0e8e3..19b3a94023c 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -109,7 +109,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima ramdisk_flags |= RD_PROMPT; else ramdisk_flags &= ~RD_PROMPT; - + val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10); if (val == 1) ramdisk_flags |= RD_DOLOAD; diff --git a/board/bct-brettl2/cled.c b/board/bct-brettl2/cled.c index 9e73c57b878..dcb91bdffad 100644 --- a/board/bct-brettl2/cled.c +++ b/board/bct-brettl2/cled.c @@ -13,7 +13,7 @@ int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - ulong addr = 0x20000000 + 0x200000; // AMS2 + ulong addr = 0x20000000 + 0x200000; /* AMS2 */ uchar data; if (argc < 2) diff --git a/board/davedenx/qong/fpga.c b/board/davedenx/qong/fpga.c index f865eb42256..656d5cde95a 100644 --- a/board/davedenx/qong/fpga.c +++ b/board/davedenx/qong/fpga.c @@ -92,4 +92,3 @@ int qong_fpga_init(void) } #endif - diff --git a/board/isee/igep0030/config.mk b/board/isee/igep0030/config.mk index 35865e06a49..019f93f2007 100644 --- a/board/isee/igep0030/config.mk +++ b/board/isee/igep0030/config.mk @@ -31,4 +31,3 @@ # For use with external or internal boots. TEXT_BASE = 0x80008000 - diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c index b7fa6950b07..36e9146654c 100644 --- a/board/xes/common/fsl_8xxx_misc.c +++ b/board/xes/common/fsl_8xxx_misc.c @@ -52,11 +52,9 @@ uint get_board_derivative(void) #endif /* - * The top 4 lines of the local bus address are pulled low/high and - * can be read to determine the least significant digit of a board's - * model number. - */ + * The top 4 lines of the local bus address are pulled low/high and + * can be read to determine the least significant digit of a board's + * model number. + */ return gur->gpporcr >> 28; } - - diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c index 718cd989bbf..38a459715fd 100644 --- a/board/xes/xpedite550x/ddr.c +++ b/board/xes/xpedite550x/ddr.c @@ -55,16 +55,16 @@ unsigned int fsl_ddr_get_mem_data_rate(void) * There are traditionally three board-specific SDRAM timing parameters * which must be calculated based on the particular PCB artwork. These are: * 1.) CPO (Read Capture Delay) - * - TIMING_CFG_2 register - * Source: Calculation based on board trace lengths and - * chip-specific internal delays. + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths and + * chip-specific internal delays. * 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control) - * - DDR_SDRAM_CLK_CNTL register - * Source: Signal Integrity Simulations + * - DDR_SDRAM_CLK_CNTL register + * Source: Signal Integrity Simulations * 3.) 2T Timing on Addr/Ctl - * - TIMING_CFG_2 register - * Source: Signal Integrity Simulations - * Usually only needed with heavy load/very high speed (>DDR2-800) + * - TIMING_CFG_2 register + * Source: Signal Integrity Simulations + * Usually only needed with heavy load/very high speed (>DDR2-800) * * ====== XPedite550x DDR3-800 read delay calculations ====== * @@ -82,14 +82,14 @@ typedef struct { const board_specific_parameters_t board_specific_parameters[][20] = { { /* Controller 0 */ - { + { /* DDR3-600/667 */ .datarate_mhz_low = 500, .datarate_mhz_high = 750, .clk_adjust = 5, .cpo = 31, }, - { + { /* DDR3-800 */ .datarate_mhz_low = 750, .datarate_mhz_high = 850, @@ -162,4 +162,3 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->rtt_override = 1; popts->rtt_override_value = 3; } - diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation index 3856633e9d9..dc7be7e42e4 100644 --- a/doc/README.arm-relocation +++ b/doc/README.arm-relocation @@ -93,7 +93,7 @@ Relocation with NAND_SPL (example for the tx25): and start with code execution on this address. - The First page contains u-boot code from u-boot:nand_spl/nand_boot_fsl_nfc.c - which inits the dram, cpu registers, reloacte itself to CONFIG_SYS_TEXT_BASE and loads + which inits the dram, cpu registers, reloacte itself to CONFIG_SYS_TEXT_BASE and loads the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution @CONFIG_SYS_NAND_U_BOOT_START @@ -162,7 +162,7 @@ e) load new symbol table: (gdb) add-symbol-file u-boot 0x8ff08000 add symbol table from file "u-boot" at - .text_addr = 0x8ff08000 + .text_addr = 0x8ff08000 (y or n) y Reading symbols from /home/hs/celf/u-boot/u-boot...done. (gdb) c @@ -170,12 +170,12 @@ Continuing. ^C Program received signal SIGSTOP, Stopped (signal). 0x8ff17f18 in serial_getc () at serial_mxc.c:192 -192 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); +192 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); (gdb) add-symbol-file u-boot 0x8ff08000 - ^^^^^^^^^^ - get this address from u-boot debug printfs + ^^^^^^^^^^ + get this address from u-boot debug printfs U-Boot 2010.06-rc2-00009-gf77b8b8-dirty (Jun 22 2010 - 09:43:46) @@ -187,7 +187,7 @@ Top of RAM usable for U-Boot at: 90000000 LCD panel info: 640 x 480, 16 bit/pix Reserving 600k for LCD Framebuffer at: 8ff6a000 Reserving 391k for U-Boot at: 8ff08000 - ^^^^^^^^ + ^^^^^^^^ Reserving 1280k for malloc() at: 8fdc8000 Reserving 24 Bytes for Board Info at: 8fdc7fe8 Reserving 52 Bytes for Global Data at: 8fdc7fb4 @@ -197,6 +197,6 @@ Bank #0: 80000000 256 MiB relocation Offset is: eff08000 mon: 00058BAC gd->monLen: 00061F10 Now running in RAM - U-Boot at: 8ff08000 - ^^^^^^^^ + ^^^^^^^^ Now you can use gdb as usual :-) diff --git a/drivers/fpga/lattice.c b/drivers/fpga/lattice.c index a0e78231024..c3b2355f941 100644 --- a/drivers/fpga/lattice.c +++ b/drivers/fpga/lattice.c @@ -395,5 +395,3 @@ int lattice_info(Lattice_desc *desc) return ret_val; } - - diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 9271470e368..c7f76209f33 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -412,4 +412,3 @@ int omap_mmc_init(int dev_index) return 0; } - diff --git a/drivers/serial/atmel_usart.h b/drivers/serial/atmel_usart.h index 7cfc2d500cb..7e4b2c9c69e 100644 --- a/drivers/serial/atmel_usart.h +++ b/drivers/serial/atmel_usart.h @@ -42,7 +42,7 @@ typedef struct atmel_usart3 { u32 reserved1; u32 ifr; u32 man; - u32 reserved2[54]; // version and PDC not needed + u32 reserved2[54]; /* version and PDC not needed */ } atmel_usart3_t; /* Bitfields in CR */ diff --git a/drivers/usb/gadget/config.c b/drivers/usb/gadget/config.c index cf22629b971..f9163a80ed1 100644 --- a/drivers/usb/gadget/config.c +++ b/drivers/usb/gadget/config.c @@ -116,4 +116,3 @@ int usb_gadget_config_buf( cp->bmAttributes |= USB_CONFIG_ATT_ONE; return len; } - diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c index 7cf3c673ddd..18964894215 100644 --- a/drivers/usb/gadget/epautoconf.c +++ b/drivers/usb/gadget/epautoconf.c @@ -302,4 +302,3 @@ void usb_ep_autoconfig_reset(struct usb_gadget *gadget) #endif epnum = 0; } - diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index b22ca90fc68..5a18e035b6e 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -1968,4 +1968,3 @@ fail: error("%s failed. error = %d", __func__, status); return status; } - diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c index 6e9d1bf0f29..95555cf96b9 100644 --- a/drivers/usb/gadget/usbstring.c +++ b/drivers/usb/gadget/usbstring.c @@ -137,4 +137,3 @@ usb_gadget_get_string(struct usb_gadget_strings *table, int id, u8 *buf) buf[1] = USB_DT_STRING; return buf[0]; } - diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index 20c119aede1..b5d20bd7b25 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -79,7 +79,7 @@ #define CONFIG_SYS_XLB_PIPELINING 1 #undef CONFIG_NET_MULTI -#undef CONFIG_EEPRO100 +#undef CONFIG_EEPRO100 /* Partitions */ #define CONFIG_MAC_PARTITION diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h index 09691d37377..608ab9f41a4 100644 --- a/include/configs/bct-brettl2.h +++ b/include/configs/bct-brettl2.h @@ -11,7 +11,7 @@ /* * Processor Settings */ -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS /* @@ -21,11 +21,11 @@ */ /* CONFIG_CLKIN_HZ is any value in Hz */ #define CONFIG_CLKIN_HZ 16384000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ #define CONFIG_CLKIN_HALF 0 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ +/* 1 = bypass PLL */ #define CONFIG_PLL_BYPASS 0 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ /* Values can range from 0-63 (where 0 means 64) */ @@ -36,7 +36,7 @@ /* SCLK_DIV controls the system clock divider */ /* Values can range from 1-15 */ #define CONFIG_SCLK_DIV 3 -#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) +#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) /* @@ -111,13 +111,13 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/cpu/traps.o (.text .text.*); \ - arch/blackfin/cpu/interrupt.o (.text .text.*); \ - arch/blackfin/cpu/serial.o (.text .text.*); \ - common/dlmalloc.o (.text .text.*); \ - lib/crc32.o (.text .text.*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text .text.*); + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); #endif diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h index 8b2bdc715d6..e4688a27b4a 100644 --- a/include/configs/blackvme.h +++ b/include/configs/blackvme.h @@ -126,9 +126,9 @@ * AX88180 WEN = 5 clocks REN 6 clocks @ SCLK = 100 MHz * One extra clock needed because AX88180 is asynchronous to CPU. */ - /* bank 1 0 */ + /* bank 1 0 */ #define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2 - /* bank 3 2 */ + /* bank 3 2 */ #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2 /* memory layout */ diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h index 21b7ec7e1b2..166da6ca7fd 100644 --- a/include/configs/mx1ads.h +++ b/include/configs/mx1ads.h @@ -60,8 +60,6 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - - /* * CS8900 Ethernet drivers */ @@ -79,7 +77,6 @@ #define CONFIG_BAUDRATE 115200 - /* * BOOTP options */ @@ -88,7 +85,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -98,7 +94,6 @@ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_ELF - #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "root=/dev/msdk mem=48M" #define CONFIG_BOOTFILE "mx1ads" diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h index 0641befeb17..1632ce82ba3 100644 --- a/include/configs/mx1fs2.h +++ b/include/configs/mx1fs2.h @@ -34,7 +34,6 @@ #undef _CONFIG_UART4 /* internal uart 4 */ #undef CONFIG_SILENT_CONSOLE /* use this to disable output */ - /* * BOOTP options */ @@ -43,7 +42,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -58,7 +56,6 @@ #undef CONFIG_CMD_PING #undef CONFIG_CMD_SOURCE - /* * Boot options. Setting delay to -1 stops autostart count down. */ @@ -98,8 +95,6 @@ */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) - - #define CONFIG_STACKSIZE (120<<10) /* stack size */ #ifdef CONFIG_USE_IRQ diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index c0ae2d9d240..3da214e99dd 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -35,7 +35,6 @@ * Select serial console configuration */ - /* * BOOTP options */ @@ -44,7 +43,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -58,7 +56,6 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_SOURCE - /* * Boot options. Setting delay to -1 stops autostart count down. * NOTE: Sending parameters to kernel depends on kernel version and @@ -100,14 +97,11 @@ #define CONFIG_INITRD_TAG 1 /* send initrd params */ #undef CONFIG_VFD /* do not send framebuffer setup */ - /* * Malloc pool need to host env + 128 Kb reserve for other allocations. */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) - - #define CONFIG_STACKSIZE (120<<10) /* stack size */ #ifdef CONFIG_USE_IRQ @@ -133,15 +127,6 @@ #define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ #define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ -/* - * Flash Controller settings - */ - -/* - * Hardware drivers - */ - - /* * Configuration for FLASH memory for the Synertronixx board */ diff --git a/include/lattice.h b/include/lattice.h index 75729b605ab..e965663579e 100755 --- a/include/lattice.h +++ b/include/lattice.h @@ -317,4 +317,3 @@ void writePort(unsigned char pins, unsigned char value); unsigned char readPort(void); void sclock(void); #endif - diff --git a/include/linux/fb.h b/include/linux/fb.h index f4ac4bf90e8..3858f8f80f6 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -26,13 +26,13 @@ struct fb_fix_screeninfo { __u32 type; /* see FB_TYPE_* */ __u32 type_aux; /* Interleave for interleaved Planes */ __u32 visual; /* see FB_VISUAL_* */ - __u16 xpanstep; /* zero if no hardware panning */ - __u16 ypanstep; /* zero if no hardware panning */ - __u16 ywrapstep; /* zero if no hardware ywrap */ - __u32 line_length; /* length of a line in bytes */ - unsigned long mmio_start; /* Start of Memory Mapped I/O */ + __u16 xpanstep; /* zero if no hardware panning */ + __u16 ypanstep; /* zero if no hardware panning */ + __u16 ywrapstep; /* zero if no hardware ywrap */ + __u32 line_length; /* length of a line in bytes */ + unsigned long mmio_start; /* Start of Memory Mapped I/O */ /* (physical address) */ - __u32 mmio_len; /* Length of Memory Mapped I/O */ + __u32 mmio_len; /* Length of Memory Mapped I/O */ __u32 accel; /* Indicate to driver which */ /* specific chip/card we have */ __u16 reserved[3]; /* Reserved for future compatibility */ @@ -56,7 +56,7 @@ struct fb_bitfield { }; -#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ +#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ #define FB_NONSTD_REV_PIX_IN_B 2 /* order of pixels in each byte is reversed */ #define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/ @@ -64,38 +64,38 @@ struct fb_bitfield { #define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */ #define FB_ACTIVATE_MASK 15 /* values */ -#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */ +#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */ #define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */ #define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */ #define FB_ACTIVATE_FORCE 128 /* force apply even when no change*/ -#define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */ +#define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */ #define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ #define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ #define FB_SYNC_EXT 4 /* external sync */ -#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ -#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ /* vtotal = 144d/288n/576i => PAL */ /* vtotal = 121d/242n/484i => NTSC */ #define FB_SYNC_ON_GREEN 32 /* sync on green */ -#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ +#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ #define FB_VMODE_INTERLACED 1 /* interlaced */ #define FB_VMODE_DOUBLE 2 /* double scan */ #define FB_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */ #define FB_VMODE_MASK 255 -#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ #define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ #define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ /* * Display rotation support */ -#define FB_ROTATE_UR 0 -#define FB_ROTATE_CW 1 -#define FB_ROTATE_UD 2 -#define FB_ROTATE_CCW 3 +#define FB_ROTATE_UR 0 +#define FB_ROTATE_CW 1 +#define FB_ROTATE_UD 2 +#define FB_ROTATE_CCW 3 #define PICOS2KHZ(a) (1000000000UL/(a)) #define KHZ2PICOS(a) (1000000000UL/(a)) @@ -154,10 +154,10 @@ struct fb_con2fbmap { }; /* VESA Blanking Levels */ -#define VESA_NO_BLANKING 0 -#define VESA_VSYNC_SUSPEND 1 -#define VESA_HSYNC_SUSPEND 2 -#define VESA_POWERDOWN 3 +#define VESA_NO_BLANKING 0 +#define VESA_VSYNC_SUSPEND 1 +#define VESA_HSYNC_SUSPEND 2 +#define VESA_POWERDOWN 3 enum { @@ -234,12 +234,12 @@ struct fb_image { */ #define FB_CUR_SETIMAGE 0x01 -#define FB_CUR_SETPOS 0x02 -#define FB_CUR_SETHOT 0x04 -#define FB_CUR_SETCMAP 0x08 +#define FB_CUR_SETPOS 0x02 +#define FB_CUR_SETHOT 0x04 +#define FB_CUR_SETCMAP 0x08 #define FB_CUR_SETSHAPE 0x10 #define FB_CUR_SETSIZE 0x20 -#define FB_CUR_SETALL 0xFF +#define FB_CUR_SETALL 0xFF struct fbcurpos { __u16 x, y; @@ -377,29 +377,29 @@ struct fb_cursor_user { * if you own it */ #define FB_EVENT_RESUME 0x03 -/* An entry from the modelist was removed */ -#define FB_EVENT_MODE_DELETE 0x04 -/* A driver registered itself */ -#define FB_EVENT_FB_REGISTERED 0x05 -/* A driver unregistered itself */ -#define FB_EVENT_FB_UNREGISTERED 0x06 -/* CONSOLE-SPECIFIC: get console to framebuffer mapping */ -#define FB_EVENT_GET_CONSOLE_MAP 0x07 -/* CONSOLE-SPECIFIC: set console to framebuffer mapping */ -#define FB_EVENT_SET_CONSOLE_MAP 0x08 -/* A hardware display blank change occured */ -#define FB_EVENT_BLANK 0x09 -/* Private modelist is to be replaced */ -#define FB_EVENT_NEW_MODELIST 0x0A +/* An entry from the modelist was removed */ +#define FB_EVENT_MODE_DELETE 0x04 +/* A driver registered itself */ +#define FB_EVENT_FB_REGISTERED 0x05 +/* A driver unregistered itself */ +#define FB_EVENT_FB_UNREGISTERED 0x06 +/* CONSOLE-SPECIFIC: get console to framebuffer mapping */ +#define FB_EVENT_GET_CONSOLE_MAP 0x07 +/* CONSOLE-SPECIFIC: set console to framebuffer mapping */ +#define FB_EVENT_SET_CONSOLE_MAP 0x08 +/* A hardware display blank change occured */ +#define FB_EVENT_BLANK 0x09 +/* Private modelist is to be replaced */ +#define FB_EVENT_NEW_MODELIST 0x0A /* The resolution of the passed in fb_info about to change and - all vc's should be changed */ + all vc's should be changed */ #define FB_EVENT_MODE_CHANGE_ALL 0x0B /* A software display blank change occured */ -#define FB_EVENT_CONBLANK 0x0C -/* Get drawing requirements */ -#define FB_EVENT_GET_REQ 0x0D -/* Unbind from the console if possible */ -#define FB_EVENT_FB_UNBIND 0x0E +#define FB_EVENT_CONBLANK 0x0C +/* Get drawing requirements */ +#define FB_EVENT_GET_REQ 0x0D +/* Unbind from the console if possible */ +#define FB_EVENT_FB_UNBIND 0x0E struct fb_event { struct fb_info *info; @@ -421,10 +421,10 @@ struct fb_blit_caps { * format the hardware needs. */ -#define FB_PIXMAP_DEFAULT 1 /* used internally by fbcon */ -#define FB_PIXMAP_SYSTEM 2 /* memory is in system RAM */ -#define FB_PIXMAP_IO 4 /* memory is iomapped */ -#define FB_PIXMAP_SYNC 256 /* set if GPU can DMA */ +#define FB_PIXMAP_DEFAULT 1 /* used internally by fbcon */ +#define FB_PIXMAP_SYSTEM 2 /* memory is in system RAM */ +#define FB_PIXMAP_IO 4 /* memory is iomapped */ +#define FB_PIXMAP_SYNC 256 /* set if GPU can DMA */ struct fb_pixmap { u8 *addr; /* pointer to memory */ @@ -434,10 +434,10 @@ struct fb_pixmap { u32 scan_align; /* alignment per scanline */ u32 access_align; /* alignment per read/write (bits) */ u32 flags; /* see FB_PIXMAP_* */ - u32 blit_x; /* supported bit block dimensions (1-32)*/ - u32 blit_y; /* Format: blit_x = 1 << (width - 1) */ - /* blit_y = 1 << (height - 1) */ - /* if 0, will be set to 0xffffffff (all)*/ + u32 blit_x; /* supported bit block dimensions (1-32)*/ + u32 blit_y; /* Format: blit_x = 1 << (width - 1) */ + /* blit_y = 1 << (height - 1) */ + /* if 0, will be set to 0xffffffff (all)*/ /* access methods */ void (*writeio)(struct fb_info *info, void *dst, void *src, unsigned int size); void (*readio) (struct fb_info *info, void *dst, void *src, unsigned int size); @@ -488,7 +488,7 @@ struct fb_deferred_io { * meaning, it is set by the fb subsystem depending FOREIGN_ENDIAN flag * and host endianness. Drivers should not use this flag. */ -#define FBINFO_BE_MATH 0x100000 +#define FBINFO_BE_MATH 0x100000 struct fb_info { int node; @@ -499,7 +499,7 @@ struct fb_info { struct fb_pixmap pixmap; /* Image hardware mapper */ struct fb_pixmap sprite; /* Cursor hardware mapper */ struct fb_cmap cmap; /* Current cmap */ - struct list_head modelist; /* mode list */ + struct list_head modelist; /* mode list */ struct fb_videomode *mode; /* current mode */ char *screen_base; /* Virtual address */ @@ -508,7 +508,7 @@ struct fb_info { #define FBINFO_STATE_RUNNING 0 #define FBINFO_STATE_SUSPENDED 1 u32 state; /* Hardware state i.e suspend */ - void *fbcon_par; /* fbcon use-only private area */ + void *fbcon_par; /* fbcon use-only private area */ /* From here on everything is device dependent */ void *par; }; @@ -518,14 +518,14 @@ struct fb_info { #define FBINFO_FLAG_MODULE FBINFO_MODULE #define FBINFO_FLAG_DEFAULT FBINFO_DEFAULT -// This will go away +/* This will go away */ #if defined(__sparc__) /* We map all of our framebuffers such that big-endian accesses * are what we want, so the following is sufficient. */ -// This will go away +/* This will go away */ #define fb_readb sbus_readb #define fb_readw sbus_readw #define fb_readl sbus_readl @@ -562,7 +562,7 @@ struct fb_info { #endif -#define FB_LEFT_POS(p, bpp) (fb_be_math(p) ? (32 - (bpp)) : 0) +#define FB_LEFT_POS(p, bpp) (fb_be_math(p) ? (32 - (bpp)) : 0) #define FB_SHIFT_HIGH(p, val, bits) (fb_be_math(p) ? (val) >> (bits) : \ (val) << (bits)) #define FB_SHIFT_LOW(p, val, bits) (fb_be_math(p) ? (val) << (bits) : \ @@ -580,7 +580,7 @@ struct fb_info { #define FB_MODE_IS_VESA 4 #define FB_MODE_IS_CALCULATED 8 #define FB_MODE_IS_FIRST 16 -#define FB_MODE_IS_FROM_VAR 32 +#define FB_MODE_IS_FROM_VAR 32 /* drivers/video/fbcmap.c */ diff --git a/include/linux/kbuild.h b/include/linux/kbuild.h index be763842c0b..ab7805a3b44 100644 --- a/include/linux/kbuild.h +++ b/include/linux/kbuild.h @@ -7,7 +7,7 @@ #define __LINUX_KBUILD_H #define DEFINE(sym, val) \ - asm volatile("\n->" #sym " %0 " #val : : "i" (val)) + asm volatile("\n->" #sym " %0 " #val : : "i" (val)) #define BLANK() asm volatile("\n->" : : ) diff --git a/include/linux/usb/cdc.h b/include/linux/usb/cdc.h index 03541cbf219..29672842749 100644 --- a/include/linux/usb/cdc.h +++ b/include/linux/usb/cdc.h @@ -9,8 +9,6 @@ * Remy Bohmer */ - - #define USB_CDC_SUBCLASS_ACM 0x02 #define USB_CDC_SUBCLASS_ETHERNET 0x06 #define USB_CDC_SUBCLASS_WHCM 0x08 @@ -199,7 +197,6 @@ struct usb_cdc_line_coding { #define USB_CDC_PACKET_TYPE_BROADCAST (1 << 3) #define USB_CDC_PACKET_TYPE_MULTICAST (1 << 4) /* filtered */ - /*-------------------------------------------------------------------------*/ /* @@ -221,4 +218,3 @@ struct usb_cdc_notification { __le16 wIndex; __le16 wLength; } __attribute__ ((packed)); - diff --git a/lib/hashtable.c b/lib/hashtable.c index 57802cfb6de..7ac3dddda69 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -56,7 +56,7 @@ /* * [Aho,Sethi,Ullman] Compilers: Principles, Techniques and Tools, 1986 - * [Knuth] The Art of Computer Programming, part 3 (6.4) + * [Knuth] The Art of Computer Programming, part 3 (6.4) */ /* @@ -252,7 +252,7 @@ int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval, if (htab->table[idx].used) { /* - * Further action might be required according to the + * Further action might be required according to the * action value. */ unsigned hval2; @@ -283,8 +283,8 @@ int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval, do { /* - * Because SIZE is prime this guarantees to - * step through all available indices. + * Because SIZE is prime this guarantees to + * step through all available indices. */ if (idx <= hval2) idx = htab->size + idx - hval2; @@ -323,8 +323,8 @@ int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval, /* An empty bucket has been found. */ if (action == ENTER) { /* - * If table is full and another entry should be - * entered return with error. + * If table is full and another entry should be + * entered return with error. */ if (htab->filled == htab->size) { __set_errno(ENOMEM); diff --git a/lib/qsort.c b/lib/qsort.c index bb47319f8ba..e771dcfcf27 100644 --- a/lib/qsort.c +++ b/lib/qsort.c @@ -23,9 +23,9 @@ #endif void qsort(void *base, - size_t nel, - size_t width, - int (*comp)(const void *, const void *)) + size_t nel, + size_t width, + int (*comp)(const void *, const void *)) { size_t wgap, i, j, k; char tmp; diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c index 30675484839..501369b6a1c 100644 --- a/post/board/lwmon5/fpga.c +++ b/post/board/lwmon5/fpga.c @@ -227,8 +227,6 @@ static int fpga_mem_test(void) return ret; } - - /* Verify FPGA addresslines */ static int fpga_post_addrline(ulong *address, ulong *base, ulong size) { -- cgit v1.3.1 From d9abba8254c3e6b9a1d5c2e52c2d8088bbeb520f Mon Sep 17 00:00:00 2001 From: C Nauman Date: Tue, 26 Oct 2010 23:04:31 +0900 Subject: Add generic support for samsung s3c2440 This patch adds generic support for the Samsung s3c2440 processor. Global s3c24x0 changes to struct members converting from upper case to lower case. Signed-off-by: Craig Nauman Cc: kevin.morfitt@fearnside-systems.co.uk Signed-off-by: Minkyu Kang --- arch/arm/cpu/arm920t/s3c24x0/speed.c | 30 +- arch/arm/cpu/arm920t/s3c24x0/timer.c | 23 +- arch/arm/cpu/arm920t/s3c24x0/usb.c | 10 +- arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c | 12 +- arch/arm/include/asm/arch-s3c24x0/s3c2440.h | 161 ++++++ arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 672 +++++++++++++----------- arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h | 2 + board/mpl/vcma9/vcma9.c | 41 +- board/samsung/smdk2400/smdk2400.c | 28 +- board/samsung/smdk2410/smdk2410.c | 36 +- board/sbc2410x/sbc2410x.c | 44 +- board/trab/cmd_trab.c | 28 +- board/trab/rs485.c | 40 +- board/trab/trab.c | 67 +-- board/trab/trab_fkt.c | 142 ++--- board/trab/tsc2000.c | 39 +- board/trab/tsc2000.h | 86 +-- board/trab/vfd.c | 90 ++-- drivers/i2c/s3c24x0_i2c.c | 102 ++-- drivers/mtd/nand/s3c2410_nand.c | 25 +- drivers/rtc/s3c24x0_rtc.c | 52 +- drivers/serial/serial_s3c24x0.c | 26 +- 22 files changed, 1016 insertions(+), 740 deletions(-) create mode 100644 arch/arm/include/asm/arch-s3c24x0/s3c2440.h (limited to 'drivers') diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c index b13283a798e..3ae558dd628 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/speed.c +++ b/arch/arm/cpu/arm920t/s3c24x0/speed.c @@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg) ulong r, m, p, s; if (pllreg == MPLL) - r = readl(&clk_power->MPLLCON); + r = readl(&clk_power->mpllcon); else if (pllreg == UPLL) - r = readl(&clk_power->UPLLCON); + r = readl(&clk_power->upllcon); else hang(); @@ -64,7 +64,12 @@ static ulong get_PLLCLK(int pllreg) p = ((r & 0x003F0) >> 4) + 2; s = r & 0x3; +#if defined(CONFIG_S3C2440) + if (pllreg == MPLL) + return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s)); +#endif return (CONFIG_SYS_CLK_FREQ * m) / (p << s); + } /* return FCLK frequency */ @@ -77,8 +82,23 @@ ulong get_FCLK(void) ulong get_HCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - - return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK(); +#ifdef CONFIG_S3C2440 + switch (readl(&clk_power->clkdivn) & 0x6) { + default: + case 0: + return get_FCLK(); + case 2: + return get_FCLK() / 2; + case 4: + return (readl(&clk_power->camdivn) & (1 << 9)) ? + get_FCLK() / 8 : get_FCLK() / 4; + case 6: + return (readl(&clk_power->camdivn) & (1 << 8)) ? + get_FCLK() / 6 : get_FCLK() / 3; + } +#else + return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK(); +#endif } /* return PCLK frequency */ @@ -86,7 +106,7 @@ ulong get_PCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK(); + return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK(); } /* return UCLK frequency */ diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c index 7d47354381c..8cf9ff6be00 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/timer.c +++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c @@ -43,7 +43,7 @@ static inline ulong READ_TIMER(void) { struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); - return readl(&timers->TCNTO4) & 0xffff; + return readl(&timers->tcnto4) & 0xffff; } static ulong timestamp; @@ -56,7 +56,7 @@ int timer_init(void) /* use PWM Timer 4 because it has no output */ /* prescaler for Timer 4 is 16 */ - writel(0x0f00, &timers->TCFG0); + writel(0x0f00, &timers->tcfg0); if (timer_load_val == 0) { /* * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 @@ -68,13 +68,13 @@ int timer_init(void) } /* load value for 10 ms timeout */ lastdec = timer_load_val; - writel(timer_load_val, &timers->TCNTB4); - /* auto load, manual update of Timer 4 */ - tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000; - writel(tmr, &timers->TCON); - /* auto load, start Timer 4 */ + writel(timer_load_val, &timers->tcntb4); + /* auto load, manual update of timer 4 */ + tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000; + writel(tmr, &timers->tcon); + /* auto load, start timer 4 */ tmr = (tmr & ~0x0700000) | 0x0500000; - writel(tmr, &timers->TCON); + writel(tmr, &timers->tcon); timestamp = 0; return (0); @@ -181,6 +181,7 @@ ulong get_tbclk(void) tbclk = timer_load_val * 100; #elif defined(CONFIG_SBC2410X) || \ defined(CONFIG_SMDK2410) || \ + defined(CONFIG_S3C2440) || \ defined(CONFIG_VCMA9) tbclk = CONFIG_SYS_HZ; #else @@ -206,13 +207,13 @@ void reset_cpu(ulong ignored) watchdog = s3c24x0_get_base_watchdog(); /* Disable watchdog */ - writel(0x0000, &watchdog->WTCON); + writel(0x0000, &watchdog->wtcon); /* Initialize watchdog timer count register */ - writel(0x0001, &watchdog->WTCNT); + writel(0x0001, &watchdog->wtcnt); /* Enable watchdog timer; assert reset at timer timeout */ - writel(0x0021, &watchdog->WTCON); + writel(0x0021, &watchdog->wtcon); while (1) /* loop forever and wait for reset to happen */; diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb.c b/arch/arm/cpu/arm920t/s3c24x0/usb.c index e468ed08fc4..226a3f6c90c 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/usb.c +++ b/arch/arm/cpu/arm920t/s3c24x0/usb.c @@ -39,14 +39,14 @@ int usb_cpu_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */ - writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON); + writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); /* 1 = use pads related USB for USB host */ - writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR); + writel(readl(&gpio->misccr) | 0x8, &gpio->misccr); /* * Enable USB host clock. */ - writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); return 0; } @@ -55,14 +55,14 @@ int usb_cpu_stop(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); /* may not want to do this */ - writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; } int usb_cpu_init_fail(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; } diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c index 5aa8d64a55c..ccc97384f33 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c @@ -1666,13 +1666,13 @@ int usb_lowlevel_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */ - clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2); - gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */ + clk_power->upllcon = ((40 << 12) + (1 << 4) + 2); + gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */ /* * Enable USB host clock. */ - clk_power->CLKCON |= (1 << 4); + clk_power->clkcon |= (1 << 4); memset(&gohci, 0, sizeof(struct ohci)); memset(&urb_priv, 0, sizeof(struct urb_priv)); @@ -1709,7 +1709,7 @@ int usb_lowlevel_init(void) if (hc_reset(&gohci) < 0) { hc_release_ohci(&gohci); /* Initialization failed */ - clk_power->CLKCON &= ~(1 << 4); + clk_power->clkcon &= ~(1 << 4); return -1; } @@ -1722,7 +1722,7 @@ int usb_lowlevel_init(void) err("can't start usb-%s", gohci.slot_name); hc_release_ohci(&gohci); /* Initialization failed */ - clk_power->CLKCON &= ~(1 << 4); + clk_power->clkcon &= ~(1 << 4); return -1; } #ifdef DEBUG @@ -1748,7 +1748,7 @@ int usb_lowlevel_stop(void) /* call hc_release_ohci() here ? */ hc_reset(&gohci); /* may not want to do this */ - clk_power->CLKCON &= ~(1 << 4); + clk_power->clkcon &= ~(1 << 4); return 0; } diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h new file mode 100644 index 00000000000..8c606e3995a --- /dev/null +++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2003 + * David Mueller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c2440.h + * Version : 31.3.2003 + * + * Based on S3C2440 User's manual Rev x.x + ************************************************/ + +#ifndef __S3C2440_H__ +#define __S3C2440_H__ + +#define S3C24X0_UART_CHANNELS 3 +#define S3C24X0_SPI_CHANNELS 2 + +/* S3C2440 only supports 512 Byte HW ECC */ +#define S3C2440_ECCSIZE 512 +#define S3C2440_ECCBYTES 3 + +enum s3c24x0_uarts_nr { + S3C24X0_UART0, + S3C24X0_UART1, + S3C24X0_UART2 +}; + +/* S3C2440 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x48000000 +#define S3C24X0_USB_HOST_BASE 0x49000000 +#define S3C24X0_INTERRUPT_BASE 0x4A000000 +#define S3C24X0_DMA_BASE 0x4B000000 +#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 +#define S3C24X0_LCD_BASE 0x4D000000 +#define S3C2440_NAND_BASE 0x4E000000 +#define S3C24X0_UART_BASE 0x50000000 +#define S3C24X0_TIMER_BASE 0x51000000 +#define S3C24X0_USB_DEVICE_BASE 0x52000140 +#define S3C24X0_WATCHDOG_BASE 0x53000000 +#define S3C24X0_I2C_BASE 0x54000000 +#define S3C24X0_I2S_BASE 0x55000000 +#define S3C24X0_GPIO_BASE 0x56000000 +#define S3C24X0_RTC_BASE 0x57000000 +#define S3C2440_ADC_BASE 0x58000000 +#define S3C24X0_SPI_BASE 0x59000000 +#define S3C2440_SDI_BASE 0x5A000000 + +/* include common stuff */ +#include + +static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) +{ + return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; +} + +static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) +{ + return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; +} + +static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) +{ + return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; +} + +static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) +{ + return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; +} + +static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) +{ + return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; +} + +static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) +{ + return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; +} + +static inline struct s3c2440_nand *s3c2440_get_base_nand(void) +{ + return (struct s3c2440_nand *)S3C2440_NAND_BASE; +} + +static inline struct s3c24x0_uart + *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) +{ + return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); +} + +static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) +{ + return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; +} + +static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) +{ + return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; +} + +static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) +{ + return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; +} + +static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) +{ + return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; +} + +static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) +{ + return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; +} + +static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) +{ + return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; +} + +static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) +{ + return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; +} + +static inline struct s3c2440_adc *s3c2440_get_base_adc(void) +{ + return (struct s3c2440_adc *)S3C2440_ADC_BASE; +} + +static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) +{ + return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; +} + +static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void) +{ + return (struct s3c2440_sdi *)S3C2440_SDI_BASE; +} + +#endif /*__S3C2440_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h index 15f53dd35be..f634d112964 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h @@ -33,12 +33,12 @@ /* Memory controller (see manual chapter 5) */ struct s3c24x0_memctl { - u32 BWSCON; - u32 BANKCON[8]; - u32 REFRESH; - u32 BANKSIZE; - u32 MRSRB6; - u32 MRSRB7; + u32 bwscon; + u32 bankcon[8]; + u32 refresh; + u32 banksize; + u32 mrsrb6; + u32 mrsrb7; }; @@ -72,40 +72,38 @@ struct s3c24x0_usb_host { /* INTERRUPT (see manual chapter 14) */ struct s3c24x0_interrupt { - u32 SRCPND; - u32 INTMOD; - u32 INTMSK; - u32 PRIORITY; - u32 INTPND; - u32 INTOFFSET; -#ifdef CONFIG_S3C2410 - u32 SUBSRCPND; - u32 INTSUBMSK; + u32 srcpnd; + u32 intmod; + u32 intmsk; + u32 priority; + u32 intpnd; + u32 intoffset; +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + u32 subsrcpnd; + u32 intsubmsk; #endif }; /* DMAS (see manual chapter 8) */ struct s3c24x0_dma { - u32 DISRC; -#ifdef CONFIG_S3C2410 - u32 DISRCC; + u32 disrc; +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + u32 disrcc; #endif - u32 DIDST; -#ifdef CONFIG_S3C2410 - u32 DIDSTC; + u32 didst; +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + u32 didstc; #endif - u32 DCON; - u32 DSTAT; - u32 DCSRC; - u32 DCDST; - u32 DMASKTRIG; -#ifdef CONFIG_S3C2400 + u32 dcon; + u32 dstat; + u32 dcsrc; + u32 dcdst; + u32 dmasktrig; +#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \ + || defined(CONFIG_S3C2440) u32 res[1]; #endif -#ifdef CONFIG_S3C2410 - u32 res[7]; -#endif }; struct s3c24x0_dmas { @@ -116,90 +114,111 @@ struct s3c24x0_dmas { /* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ /* (see S3C2410 manual chapter 7) */ struct s3c24x0_clock_power { - u32 LOCKTIME; - u32 MPLLCON; - u32 UPLLCON; - u32 CLKCON; - u32 CLKSLOW; - u32 CLKDIVN; + u32 locktime; + u32 mpllcon; + u32 upllcon; + u32 clkcon; + u32 clkslow; + u32 clkdivn; +#if defined(CONFIG_S3C2440) + u32 camdivn; +#endif }; /* LCD CONTROLLER (see manual chapter 15) */ struct s3c24x0_lcd { - u32 LCDCON1; - u32 LCDCON2; - u32 LCDCON3; - u32 LCDCON4; - u32 LCDCON5; - u32 LCDSADDR1; - u32 LCDSADDR2; - u32 LCDSADDR3; - u32 REDLUT; - u32 GREENLUT; - u32 BLUELUT; + u32 lcdcon1; + u32 lcdcon2; + u32 lcdcon3; + u32 lcdcon4; + u32 lcdcon5; + u32 lcdsaddr1; + u32 lcdsaddr2; + u32 lcdsaddr3; + u32 redlut; + u32 greenlut; + u32 bluelut; u32 res[8]; - u32 DITHMODE; - u32 TPAL; -#ifdef CONFIG_S3C2410 - u32 LCDINTPND; - u32 LCDSRCPND; - u32 LCDINTMSK; - u32 LPCSEL; + u32 dithmode; + u32 tpal; +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + u32 lcdintpnd; + u32 lcdsrcpnd; + u32 lcdintmsk; + u32 lpcsel; #endif }; +#ifdef CONFIG_S3C2410 /* NAND FLASH (see S3C2410 manual chapter 6) */ struct s3c2410_nand { - u32 NFCONF; - u32 NFCMD; - u32 NFADDR; - u32 NFDATA; - u32 NFSTAT; - u32 NFECC; + u32 nfconf; + u32 nfcmd; + u32 nfaddr; + u32 nfdata; + u32 nfstat; + u32 nfecc; +}; +#endif +#ifdef CONFIG_S3C2440 +/* NAND FLASH (see S3C2440 manual chapter 6) */ +struct s3c2440_nand { + u32 nfconf; + u32 nfcont; + u32 nfcmd; + u32 nfaddr; + u32 nfdata; + u32 nfeccd0; + u32 nfeccd1; + u32 nfeccd; + u32 nfstat; + u32 nfstat0; + u32 nfstat1; }; +#endif /* UART (see manual chapter 11) */ struct s3c24x0_uart { - u32 ULCON; - u32 UCON; - u32 UFCON; - u32 UMCON; - u32 UTRSTAT; - u32 UERSTAT; - u32 UFSTAT; - u32 UMSTAT; + u32 ulcon; + u32 ucon; + u32 ufcon; + u32 umcon; + u32 utrstat; + u32 uerstat; + u32 ufstat; + u32 umstat; #ifdef __BIG_ENDIAN u8 res1[3]; - u8 UTXH; + u8 utxh; u8 res2[3]; - u8 URXH; + u8 urxh; #else /* Little Endian */ - u8 UTXH; + u8 utxh; u8 res1[3]; - u8 URXH; + u8 urxh; u8 res2[3]; #endif - u32 UBRDIV; + u32 ubrdiv; }; /* PWM TIMER (see manual chapter 10) */ struct s3c24x0_timer { - u32 TCNTB; - u32 TCMPB; - u32 TCNTO; + u32 tcntb; + u32 tcmpb; + u32 tcnto; }; struct s3c24x0_timers { - u32 TCFG0; - u32 TCFG1; - u32 TCON; + u32 tcfg0; + u32 tcfg1; + u32 tcon; struct s3c24x0_timer ch[4]; - u32 TCNTB4; - u32 TCNTO4; + u32 tcntb4; + u32 tcnto4; }; @@ -207,9 +226,9 @@ struct s3c24x0_timers { struct s3c24x0_usb_dev_fifos { #ifdef __BIG_ENDIAN u8 res[3]; - u8 EP_FIFO_REG; + u8 ep_fifo_reg; #else /* little endian */ - u8 EP_FIFO_REG; + u8 ep_fifo_reg; u8 res[3]; #endif }; @@ -217,29 +236,29 @@ struct s3c24x0_usb_dev_fifos { struct s3c24x0_usb_dev_dmas { #ifdef __BIG_ENDIAN u8 res1[3]; - u8 EP_DMA_CON; + u8 ep_dma_con; u8 res2[3]; - u8 EP_DMA_UNIT; + u8 ep_dma_unit; u8 res3[3]; - u8 EP_DMA_FIFO; + u8 ep_dma_fifo; u8 res4[3]; - u8 EP_DMA_TTC_L; + u8 ep_dma_ttc_l; u8 res5[3]; - u8 EP_DMA_TTC_M; + u8 ep_dma_ttc_m; u8 res6[3]; - u8 EP_DMA_TTC_H; + u8 ep_dma_ttc_h; #else /* little endian */ - u8 EP_DMA_CON; + u8 ep_dma_con; u8 res1[3]; - u8 EP_DMA_UNIT; + u8 ep_dma_unit; u8 res2[3]; - u8 EP_DMA_FIFO; + u8 ep_dma_fifo; u8 res3[3]; - u8 EP_DMA_TTC_L; + u8 ep_dma_ttc_l; u8 res4[3]; - u8 EP_DMA_TTC_M; + u8 ep_dma_ttc_m; u8 res5[3]; - u8 EP_DMA_TTC_H; + u8 ep_dma_ttc_h; u8 res6[3]; #endif }; @@ -247,69 +266,69 @@ struct s3c24x0_usb_dev_dmas { struct s3c24x0_usb_device { #ifdef __BIG_ENDIAN u8 res1[3]; - u8 FUNC_ADDR_REG; + u8 func_addr_reg; u8 res2[3]; - u8 PWR_REG; + u8 pwr_reg; u8 res3[3]; - u8 EP_INT_REG; + u8 ep_int_reg; u8 res4[15]; - u8 USB_INT_REG; + u8 usb_int_reg; u8 res5[3]; - u8 EP_INT_EN_REG; + u8 ep_int_en_reg; u8 res6[15]; - u8 USB_INT_EN_REG; + u8 usb_int_en_reg; u8 res7[3]; - u8 FRAME_NUM1_REG; + u8 frame_num1_reg; u8 res8[3]; - u8 FRAME_NUM2_REG; + u8 frame_num2_reg; u8 res9[3]; - u8 INDEX_REG; + u8 index_reg; u8 res10[7]; - u8 MAXP_REG; + u8 maxp_reg; u8 res11[3]; - u8 EP0_CSR_IN_CSR1_REG; + u8 ep0_csr_in_csr1_reg; u8 res12[3]; - u8 IN_CSR2_REG; + u8 in_csr2_reg; u8 res13[7]; - u8 OUT_CSR1_REG; + u8 out_csr1_reg; u8 res14[3]; - u8 OUT_CSR2_REG; + u8 out_csr2_reg; u8 res15[3]; - u8 OUT_FIFO_CNT1_REG; + u8 out_fifo_cnt1_reg; u8 res16[3]; - u8 OUT_FIFO_CNT2_REG; + u8 out_fifo_cnt2_reg; #else /* little endian */ - u8 FUNC_ADDR_REG; + u8 func_addr_reg; u8 res1[3]; - u8 PWR_REG; + u8 pwr_reg; u8 res2[3]; - u8 EP_INT_REG; + u8 ep_int_reg; u8 res3[15]; - u8 USB_INT_REG; + u8 usb_int_reg; u8 res4[3]; - u8 EP_INT_EN_REG; + u8 ep_int_en_reg; u8 res5[15]; - u8 USB_INT_EN_REG; + u8 usb_int_en_reg; u8 res6[3]; - u8 FRAME_NUM1_REG; + u8 frame_num1_reg; u8 res7[3]; - u8 FRAME_NUM2_REG; + u8 frame_num2_reg; u8 res8[3]; - u8 INDEX_REG; + u8 index_reg; u8 res9[7]; - u8 MAXP_REG; + u8 maxp_reg; u8 res10[7]; - u8 EP0_CSR_IN_CSR1_REG; + u8 ep0_csr_in_csr1_reg; u8 res11[3]; - u8 IN_CSR2_REG; + u8 in_csr2_reg; u8 res12[3]; - u8 OUT_CSR1_REG; + u8 out_csr1_reg; u8 res13[7]; - u8 OUT_CSR2_REG; + u8 out_csr2_reg; u8 res14[3]; - u8 OUT_FIFO_CNT1_REG; + u8 out_fifo_cnt1_reg; u8 res15[3]; - u8 OUT_FIFO_CNT2_REG; + u8 out_fifo_cnt2_reg; u8 res16[3]; #endif /* __BIG_ENDIAN */ struct s3c24x0_usb_dev_fifos fifo[5]; @@ -319,18 +338,18 @@ struct s3c24x0_usb_device { /* WATCH DOG TIMER (see manual chapter 18) */ struct s3c24x0_watchdog { - u32 WTCON; - u32 WTDAT; - u32 WTCNT; + u32 wtcon; + u32 wtdat; + u32 wtcnt; }; /* IIC (see manual chapter 20) */ struct s3c24x0_i2c { - u32 IICCON; - u32 IICSTAT; - u32 IICADD; - u32 IICDS; + u32 iiccon; + u32 iicstat; + u32 iicadd; + u32 iicds; }; @@ -338,25 +357,25 @@ struct s3c24x0_i2c { struct s3c24x0_i2s { #ifdef __BIG_ENDIAN u16 res1; - u16 IISCON; + u16 iiscon; u16 res2; - u16 IISMOD; + u16 iismod; u16 res3; - u16 IISPSR; + u16 iispsr; u16 res4; - u16 IISFCON; + u16 iisfcon; u16 res5; - u16 IISFIFO; + u16 iisfifo; #else /* little endian */ - u16 IISCON; + u16 iiscon; u16 res1; - u16 IISMOD; + u16 iismod; u16 res2; - u16 IISPSR; + u16 iispsr; u16 res3; - u16 IISFCON; + u16 iisfcon; u16 res4; - u16 IISFIFO; + u16 iisfifo; u16 res5; #endif }; @@ -365,87 +384,146 @@ struct s3c24x0_i2s { /* I/O PORT (see manual chapter 9) */ struct s3c24x0_gpio { #ifdef CONFIG_S3C2400 - u32 PACON; - u32 PADAT; + u32 pacon; + u32 padat; - u32 PBCON; - u32 PBDAT; - u32 PBUP; + u32 pbcon; + u32 pbdat; + u32 pbup; - u32 PCCON; - u32 PCDAT; - u32 PCUP; + u32 pccon; + u32 pcdat; + u32 pcup; - u32 PDCON; - u32 PDDAT; - u32 PDUP; + u32 pdcon; + u32 pddat; + u32 pdup; - u32 PECON; - u32 PEDAT; - u32 PEUP; + u32 pecon; + u32 pedat; + u32 peup; - u32 PFCON; - u32 PFDAT; - u32 PFUP; + u32 pfcon; + u32 pfdat; + u32 pfup; - u32 PGCON; - u32 PGDAT; - u32 PGUP; + u32 pgcon; + u32 pgdat; + u32 pgup; - u32 OPENCR; + u32 opencr; - u32 MISCCR; - u32 EXTINT; + u32 misccr; + u32 extint; #endif #ifdef CONFIG_S3C2410 - u32 GPACON; - u32 GPADAT; + u32 gpacon; + u32 gpadat; + u32 res1[2]; + u32 gpbcon; + u32 gpbdat; + u32 gpbup; + u32 res2; + u32 gpccon; + u32 gpcdat; + u32 gpcup; + u32 res3; + u32 gpdcon; + u32 gpddat; + u32 gpdup; + u32 res4; + u32 gpecon; + u32 gpedat; + u32 gpeup; + u32 res5; + u32 gpfcon; + u32 gpfdat; + u32 gpfup; + u32 res6; + u32 gpgcon; + u32 gpgdat; + u32 gpgup; + u32 res7; + u32 gphcon; + u32 gphdat; + u32 gphup; + u32 res8; + + u32 misccr; + u32 dclkcon; + u32 extint0; + u32 extint1; + u32 extint2; + u32 eintflt0; + u32 eintflt1; + u32 eintflt2; + u32 eintflt3; + u32 eintmask; + u32 eintpend; + u32 gstatus0; + u32 gstatus1; + u32 gstatus2; + u32 gstatus3; + u32 gstatus4; +#endif +#if defined(CONFIG_S3C2440) + u32 gpacon; + u32 gpadat; u32 res1[2]; - u32 GPBCON; - u32 GPBDAT; - u32 GPBUP; + u32 gpbcon; + u32 gpbdat; + u32 gpbup; u32 res2; - u32 GPCCON; - u32 GPCDAT; - u32 GPCUP; + u32 gpccon; + u32 gpcdat; + u32 gpcup; u32 res3; - u32 GPDCON; - u32 GPDDAT; - u32 GPDUP; + u32 gpdcon; + u32 gpddat; + u32 gpdup; u32 res4; - u32 GPECON; - u32 GPEDAT; - u32 GPEUP; + u32 gpecon; + u32 gpedat; + u32 gpeup; u32 res5; - u32 GPFCON; - u32 GPFDAT; - u32 GPFUP; + u32 gpfcon; + u32 gpfdat; + u32 gpfup; u32 res6; - u32 GPGCON; - u32 GPGDAT; - u32 GPGUP; + u32 gpgcon; + u32 gpgdat; + u32 gpgup; u32 res7; - u32 GPHCON; - u32 GPHDAT; - u32 GPHUP; + u32 gphcon; + u32 gphdat; + u32 gphup; u32 res8; - u32 MISCCR; - u32 DCLKCON; - u32 EXTINT0; - u32 EXTINT1; - u32 EXTINT2; - u32 EINTFLT0; - u32 EINTFLT1; - u32 EINTFLT2; - u32 EINTFLT3; - u32 EINTMASK; - u32 EINTPEND; - u32 GSTATUS0; - u32 GSTATUS1; - u32 GSTATUS2; - u32 GSTATUS3; - u32 GSTATUS4; + u32 misccr; + u32 dclkcon; + u32 extint0; + u32 extint1; + u32 extint2; + u32 eintflt0; + u32 eintflt1; + u32 eintflt2; + u32 eintflt3; + u32 eintmask; + u32 eintpend; + u32 gstatus0; + u32 gstatus1; + u32 gstatus2; + u32 gstatus3; + u32 gstatus4; + + u32 res9; + u32 dsc0; + u32 dsc1; + u32 mslcon; + u32 gpjcon; + u32 gpjdat; + u32 gpjup; + u32 res10; #endif }; @@ -454,74 +532,74 @@ struct s3c24x0_gpio { struct s3c24x0_rtc { #ifdef __BIG_ENDIAN u8 res1[67]; - u8 RTCCON; + u8 rtccon; u8 res2[3]; - u8 TICNT; + u8 ticnt; u8 res3[11]; - u8 RTCALM; + u8 rtcalm; u8 res4[3]; - u8 ALMSEC; + u8 almsec; u8 res5[3]; - u8 ALMMIN; + u8 almmin; u8 res6[3]; - u8 ALMHOUR; + u8 almhour; u8 res7[3]; - u8 ALMDATE; + u8 almdate; u8 res8[3]; - u8 ALMMON; + u8 almmon; u8 res9[3]; - u8 ALMYEAR; + u8 almyear; u8 res10[3]; - u8 RTCRST; + u8 rtcrst; u8 res11[3]; - u8 BCDSEC; + u8 bcdsec; u8 res12[3]; - u8 BCDMIN; + u8 bcdmin; u8 res13[3]; - u8 BCDHOUR; + u8 bcdhour; u8 res14[3]; - u8 BCDDATE; + u8 bcddate; u8 res15[3]; - u8 BCDDAY; + u8 bcdday; u8 res16[3]; - u8 BCDMON; + u8 bcdmon; u8 res17[3]; - u8 BCDYEAR; + u8 bcdyear; #else /* little endian */ u8 res0[64]; - u8 RTCCON; + u8 rtccon; u8 res1[3]; - u8 TICNT; + u8 ticnt; u8 res2[11]; - u8 RTCALM; + u8 rtcalm; u8 res3[3]; - u8 ALMSEC; + u8 almsec; u8 res4[3]; - u8 ALMMIN; + u8 almmin; u8 res5[3]; - u8 ALMHOUR; + u8 almhour; u8 res6[3]; - u8 ALMDATE; + u8 almdate; u8 res7[3]; - u8 ALMMON; + u8 almmon; u8 res8[3]; - u8 ALMYEAR; + u8 almyear; u8 res9[3]; - u8 RTCRST; + u8 rtcrst; u8 res10[3]; - u8 BCDSEC; + u8 bcdsec; u8 res11[3]; - u8 BCDMIN; + u8 bcdmin; u8 res12[3]; - u8 BCDHOUR; + u8 bcdhour; u8 res13[3]; - u8 BCDDATE; + u8 bcddate; u8 res14[3]; - u8 BCDDAY; + u8 bcdday; u8 res15[3]; - u8 BCDMON; + u8 bcdmon; u8 res16[3]; - u8 BCDYEAR; + u8 bcdyear; u8 res17[3]; #endif }; @@ -529,34 +607,34 @@ struct s3c24x0_rtc { /* ADC (see manual chapter 16) */ struct s3c2400_adc { - u32 ADCCON; - u32 ADCDAT; + u32 adccon; + u32 adcdat; }; /* ADC (see manual chapter 16) */ struct s3c2410_adc { - u32 ADCCON; - u32 ADCTSC; - u32 ADCDLY; - u32 ADCDAT0; - u32 ADCDAT1; + u32 adccon; + u32 adctsc; + u32 adcdly; + u32 adcdat0; + u32 adcdat1; }; /* SPI (see manual chapter 22) */ struct s3c24x0_spi_channel { - u8 SPCON; + u8 spcon; u8 res1[3]; - u8 SPSTA; + u8 spsta; u8 res2[3]; - u8 SPPIN; + u8 sppin; u8 res3[3]; - u8 SPPRE; + u8 sppre; u8 res4[3]; - u8 SPTDAT; + u8 sptdat; u8 res5[3]; - u8 SPRDAT; + u8 sprdat; u8 res6[3]; u8 res7[16]; }; @@ -570,53 +648,53 @@ struct s3c24x0_spi { struct s3c2400_mmc { #ifdef __BIG_ENDIAN u8 res1[3]; - u8 MMCON; + u8 mmcon; u8 res2[3]; - u8 MMCRR; + u8 mmcrr; u8 res3[3]; - u8 MMFCON; + u8 mmfcon; u8 res4[3]; - u8 MMSTA; + u8 mmsta; u16 res5; - u16 MMFSTA; + u16 mmfsta; u8 res6[3]; - u8 MMPRE; + u8 mmpre; u16 res7; - u16 MMLEN; + u16 mmlen; u8 res8[3]; - u8 MMCR7; - u32 MMRSP[4]; + u8 mmcr7; + u32 mmrsp[4]; u8 res9[3]; - u8 MMCMD0; - u32 MMCMD1; + u8 mmcmd0; + u32 mmcmd1; u16 res10; - u16 MMCR16; + u16 mmcr16; u8 res11[3]; - u8 MMDAT; + u8 mmdat; #else - u8 MMCON; + u8 mmcon; u8 res1[3]; - u8 MMCRR; + u8 mmcrr; u8 res2[3]; - u8 MMFCON; + u8 mmfcon; u8 res3[3]; - u8 MMSTA; + u8 mmsta; u8 res4[3]; - u16 MMFSTA; + u16 mmfsta; u16 res5; - u8 MMPRE; + u8 mmpre; u8 res6[3]; - u16 MMLEN; + u16 mmlen; u16 res7; - u8 MMCR7; + u8 mmcr7; u8 res8[3]; - u32 MMRSP[4]; - u8 MMCMD0; + u32 mmrsp[4]; + u8 mmcmd0; u8 res9[3]; - u32 MMCMD1; - u16 MMCR16; + u32 mmcmd1; + u16 mmcr16; u16 res10; - u8 MMDAT; + u8 mmdat; u8 res11[3]; #endif }; @@ -624,29 +702,29 @@ struct s3c2400_mmc { /* SD INTERFACE (see S3C2410 manual chapter 19) */ struct s3c2410_sdi { - u32 SDICON; - u32 SDIPRE; - u32 SDICARG; - u32 SDICCON; - u32 SDICSTA; - u32 SDIRSP0; - u32 SDIRSP1; - u32 SDIRSP2; - u32 SDIRSP3; - u32 SDIDTIMER; - u32 SDIBSIZE; - u32 SDIDCON; - u32 SDIDCNT; - u32 SDIDSTA; - u32 SDIFSTA; + u32 sdicon; + u32 sdipre; + u32 sdicarg; + u32 sdiccon; + u32 sdicsta; + u32 sdirsp0; + u32 sdirsp1; + u32 sdirsp2; + u32 sdirsp3; + u32 sdidtimer; + u32 sdibsize; + u32 sdidcon; + u32 sdidcnt; + u32 sdidsta; + u32 sdifsta; #ifdef __BIG_ENDIAN u8 res[3]; - u8 SDIDAT; + u8 sdidat; #else - u8 SDIDAT; + u8 sdidat; u8 res[3]; #endif - u32 SDIIMSK; + u32 sdiimsk; }; #endif /*__S3C24X0_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h index c37d4a108d7..54184c460bb 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h @@ -22,6 +22,8 @@ #include #elif defined CONFIG_S3C2410 #include +#elif defined CONFIG_S3C2440 + #include #else #error Please define the s3c24x0 cpu type #endif diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index eaeec828d70..978e6fdeff9 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -78,42 +78,43 @@ int board_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; + clk_power->locktime = 0xFFFFFF; /* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); /* some delay between MPLL and UPLL */ delay (4000); /* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); /* some delay between MPLL and UPLL */ delay (8000); /* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x002AAAAA; - gpio->GPBUP = 0x000002BF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x000037F7; - gpio->GPFCON = 0x00000000; - gpio->GPFUP = 0x00000000; - gpio->GPGCON = 0xFFEAFF5A; - gpio->GPGUP = 0x0000F0DC; - gpio->GPHCON = 0x0028AAAA; - gpio->GPHUP = 0x00000656; + gpio->gpacon = 0x007FFFFF; + gpio->gpbcon = 0x002AAAAA; + gpio->gpbup = 0x000002BF; + gpio->gpccon = 0xAAAAAAAA; + gpio->gpcup = 0x0000FFFF; + gpio->gpdcon = 0xAAAAAAAA; + gpio->gpdup = 0x0000FFFF; + gpio->gpecon = 0xAAAAAAAA; + gpio->gpeup = 0x000037F7; + gpio->gpfcon = 0x00000000; + gpio->gpfup = 0x00000000; + gpio->gpgcon = 0xFFEAFF5A; + gpio->gpgup = 0x0000F0DC; + gpio->gphcon = 0x0028AAAA; + gpio->gphup = 0x00000656; /* setup correct IRQ modes for NIC */ - gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */ + /* rising edge mode */ + gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8); /* select USB port 2 to be host or device (fix to host for now) */ - gpio->MISCCR |= 0x08; + gpio->misccr |= 0x08; /* init serial */ gd->baudrate = CONFIG_BAUDRATE; diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c index 1294d3f1b1c..895bd7789ab 100644 --- a/board/samsung/smdk2400/smdk2400.c +++ b/board/samsung/smdk2400/smdk2400.c @@ -52,30 +52,30 @@ int board_init (void) /* memory and cpu-speed are setup before relocation */ /* change the clock to be 50 MHz 1:1:1 */ - clk_power->MPLLCON = 0x5c042; - clk_power->CLKDIVN = 0; + clk_power->mpllcon = 0x5c042; + clk_power->clkdivn = 0; /* set up the I/O ports */ - gpio->PACON = 0x3ffff; - gpio->PBCON = 0xaaaaaaaa; - gpio->PBUP = 0xffff; - gpio->PECON = 0x0; - gpio->PEUP = 0x0; + gpio->pacon = 0x3ffff; + gpio->pbcon = 0xaaaaaaaa; + gpio->pbup = 0xffff; + gpio->pecon = 0x0; + gpio->peup = 0x0; #ifdef CONFIG_HWFLOW /*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */ /* 10, 10, 00, 00, 10, 00, 10 */ - gpio->PFCON=0xa22; + gpio->pfcon = 0xa22; /* Disable pull-up on Rx, Tx, CTS and RTS pins */ - gpio->PFUP=0x35; + gpio->pfup = 0x35; #else /*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */ /* 00, 00, 00, 00, 10, 00, 10 */ - gpio->PFCON = 0x22; + gpio->pfcon = 0x22; /* Disable pull-up on Rx and Tx pins */ - gpio->PFUP = 0x5; + gpio->pfup = 0x5; #endif /* CONFIG_HWFLOW */ - gpio->PGCON = 0x0; - gpio->PGUP = 0x0; - gpio->OPENCR = 0x0; + gpio->pgcon = 0x0; + gpio->pgup = 0x0; + gpio->opencr = 0x0; /* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2400; diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c index 5d1a8bb0cf6..76a24bb9398 100644 --- a/board/samsung/smdk2410/smdk2410.c +++ b/board/samsung/smdk2410/smdk2410.c @@ -73,36 +73,36 @@ int board_init (void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; + clk_power->locktime = 0xFFFFFF; /* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); /* some delay between MPLL and UPLL */ delay (4000); /* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); /* some delay between MPLL and UPLL */ delay (8000); /* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x00044555; - gpio->GPBUP = 0x000007FF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x0000FFFF; - gpio->GPFCON = 0x000055AA; - gpio->GPFUP = 0x000000FF; - gpio->GPGCON = 0xFF95FFBA; - gpio->GPGUP = 0x0000FFFF; - gpio->GPHCON = 0x002AFAAA; - gpio->GPHUP = 0x000007FF; + gpio->gpacon = 0x007FFFFF; + gpio->gpbcon = 0x00044555; + gpio->gpbup = 0x000007FF; + gpio->gpccon = 0xAAAAAAAA; + gpio->gpcup = 0x0000FFFF; + gpio->gpdcon = 0xAAAAAAAA; + gpio->gpdup = 0x0000FFFF; + gpio->gpecon = 0xAAAAAAAA; + gpio->gpeup = 0x0000FFFF; + gpio->gpfcon = 0x000055AA; + gpio->gpfup = 0x000000FF; + gpio->gpgcon = 0xFF95FFBA; + gpio->gpgup = 0x0000FFFF; + gpio->gphcon = 0x002AFAAA; + gpio->gphup = 0x000007FF; /* arch number of SMDK2410-Board */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index 3a936778ec4..c82382dc828 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -80,40 +80,40 @@ int board_init (void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; + clk_power->locktime = 0xFFFFFF; /* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); /* some delay between MPLL and UPLL */ delay (4000); /* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); /* some delay between MPLL and UPLL */ delay (8000); /* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x00044556; - gpio->GPBUP = 0x000007FF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x0000FFFF; - gpio->GPFCON = 0x000055AA; - gpio->GPFUP = 0x000000FF; - gpio->GPGCON = 0xFF95FF3A; - gpio->GPGUP = 0x0000FFFF; - gpio->GPHCON = 0x0016FAAA; - gpio->GPHUP = 0x000007FF; - - gpio->EXTINT0=0x22222222; - gpio->EXTINT1=0x22222222; - gpio->EXTINT2=0x22222222; + gpio->gpacon = 0x007FFFFF; + gpio->gpbcon = 0x00044556; + gpio->gpbup = 0x000007FF; + gpio->gpccon = 0xAAAAAAAA; + gpio->gpcup = 0x0000FFFF; + gpio->gpdcon = 0xAAAAAAAA; + gpio->gpdup = 0x0000FFFF; + gpio->gpecon = 0xAAAAAAAA; + gpio->gpeup = 0x0000FFFF; + gpio->gpfcon = 0x000055AA; + gpio->gpfup = 0x000000FF; + gpio->gpgcon = 0xFF95FF3A; + gpio->gpgup = 0x0000FFFF; + gpio->gphcon = 0x0016FAAA; + gpio->gphup = 0x000007FF; + + gpio->extint0 = 0x22222222; + gpio->extint1 = 0x22222222; + gpio->extint2 = 0x22222222; /* arch number of SMDK2410-Board */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c index ca4415c0b92..dec3c618279 100644 --- a/board/trab/cmd_trab.c +++ b/board/trab/cmd_trab.c @@ -637,28 +637,28 @@ static int adc_read (unsigned int channel) adc_init (); - padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ - padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ - padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); + padc->adccon &= ~ADC_STDBM; /* select normal mode */ + padc->adccon &= ~(0x7 << 3); /* clear the channel bits */ + padc->adccon |= ((channel << 3) | ADC_ENABLE_START); while (j--) { - if ((padc->ADCCON & ADC_ENABLE_START) == 0) + if ((padc->adccon & ADC_ENABLE_START) == 0) break; udelay (1); } if (j == 0) { printf("%s: ADC timeout\n", __FUNCTION__); - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + padc->adccon |= ADC_STDBM; /* select standby mode */ return -1; } - result = padc->ADCDAT & 0x3FF; + result = padc->adcdat & 0x3FF; - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + padc->adccon |= ADC_STDBM; /* select standby mode */ debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, - (padc->ADCCON >> 3) & 0x7, result); + (padc->adccon >> 3) & 0x7, result); /* * Wait for ADC to be ready for next conversion. This delay value was @@ -676,8 +676,8 @@ static void adc_init (void) padc = s3c2400_get_base_adc(); - padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ - padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ + padc->adccon &= ~(0xff << 6); /* clear prescaler bits */ + padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ /* * Wait some time to avoid problem with very first call of @@ -699,10 +699,10 @@ static void led_set (unsigned int state) switch (state) { case 0: /* turn LED off */ - gpio->PADAT |= (1 << 12); + gpio->padat |= (1 << 12); break; case 1: /* turn LED on */ - gpio->PADAT &= ~(1 << 12); + gpio->padat &= ~(1 << 12); break; default: break; @@ -729,8 +729,8 @@ static void led_init (void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* configure GPA12 as output and set to High -> LED off */ - gpio->PACON &= ~(1 << 12); - gpio->PADAT |= (1 << 12); + gpio->pacon &= ~(1 << 12); + gpio->padat |= (1 << 12); } diff --git a/board/trab/rs485.c b/board/trab/rs485.c index 6a3a4cda9ce..30336f262cf 100644 --- a/board/trab/rs485.c +++ b/board/trab/rs485.c @@ -51,16 +51,16 @@ static void rs485_setbrg (void) reg = (33000000 / (16 * 38400)) - 1; /* FIFO enable, Tx/Rx FIFO clear */ - uart->UFCON = 0x07; - uart->UMCON = 0x0; + uart->ufcon = 0x07; + uart->umcon = 0x0; /* Normal,No parity,1 stop,8 bit */ - uart->ULCON = 0x3; + uart->ulcon = 0x3; /* * tx=level,rx=edge,disable timeout int.,enable rx error int., * normal,interrupt or polling */ - uart->UCON = 0x245; - uart->UBRDIV = reg; + uart->ucon = 0x245; + uart->ubrdiv = reg; for (i = 0; i < 100; i++); } @@ -69,16 +69,16 @@ static void rs485_cfgio (void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PFCON &= ~(0x3 << 2); - gpio->PFCON |= (0x2 << 2); /* configure GPF1 as RXD1 */ + gpio->pfcon &= ~(0x3 << 2); + gpio->pfcon |= (0x2 << 2); /* configure GPF1 as RXD1 */ - gpio->PFCON &= ~(0x3 << 6); - gpio->PFCON |= (0x2 << 6); /* configure GPF3 as TXD1 */ + gpio->pfcon &= ~(0x3 << 6); + gpio->pfcon |= (0x2 << 6); /* configure GPF3 as TXD1 */ - gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */ - gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */ + gpio->pfup |= (1 << 1); /* disable pullup on GPF1 */ + gpio->pfup |= (1 << 3); /* disable pullup on GPF3 */ - gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */ + gpio->pacon &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */ } /* @@ -104,9 +104,10 @@ int rs485_getc (void) struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR); /* wait for character to arrive */ - while (!(uart->UTRSTAT & 0x1)); + while (!(uart->utrstat & 0x1)) + ; - return uart->URXH & 0xff; + return uart->urxh & 0xff; } /* @@ -117,9 +118,10 @@ void rs485_putc (const char c) struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR); /* wait for room in the tx FIFO */ - while (!(uart->UTRSTAT & 0x2)); + while (!(uart->utrstat & 0x2)) + ; - uart->UTXH = c; + uart->utxh = c; /* If \n, also do \r */ if (c == '\n') @@ -133,7 +135,7 @@ int rs485_tstc (void) { struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR); - return uart->UTRSTAT & 0x1; + return uart->utrstat & 0x1; } void rs485_puts (const char *s) @@ -172,9 +174,9 @@ static void set_rs485de(unsigned char rs485de_state) /* This is on PORT A bit 11 */ if(rs485de_state) - gpio->PADAT |= (1 << 11); + gpio->padat |= (1 << 11); else - gpio->PADAT &= ~(1 << 11); + gpio->padat &= ~(1 << 11); } diff --git a/board/trab/trab.c b/board/trab/trab.c index 828facd763e..0f74e8fa1b7 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -77,36 +77,36 @@ int board_init () #ifdef CONFIG_TRAB_50MHZ /* change the clock to be 50 MHz 1:1:1 */ /* MDIV:0x5c PDIV:4 SDIV:2 */ - clk_power->MPLLCON = 0x5c042; - clk_power->CLKDIVN = 0; + clk_power->mpllcon = 0x5c042; + clk_power->clkdivn = 0; #else /* change the clock to be 133 MHz 1:2:4 */ /* MDIV:0x7d PDIV:4 SDIV:1 */ - clk_power->MPLLCON = 0x7d041; - clk_power->CLKDIVN = 3; + clk_power->mpllcon = 0x7d041; + clk_power->clkdivn = 3; #endif /* set up the I/O ports */ - gpio->PACON = 0x3ffff; - gpio->PBCON = 0xaaaaaaaa; - gpio->PBUP = 0xffff; + gpio->pacon = 0x3ffff; + gpio->pbcon = 0xaaaaaaaa; + gpio->pbup = 0xffff; /* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */ /* 00, 10, 10, 10, 10, 10, 10 */ - gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10); + gpio->pfcon = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10); #ifdef CONFIG_HWFLOW /* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */ - gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5); + gpio->pfup = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5); #else /* do not pull up RXD0, RXD1, TXD0, TXD1 */ - gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3); + gpio->pfup = (1<<0) | (1<<1) | (1<<2) | (1<<3); #endif - gpio->PGCON = 0x0; - gpio->PGUP = 0x0; - gpio->OPENCR= 0x0; + gpio->pgcon = 0x0; + gpio->pgup = 0x0; + gpio->opencr = 0x0; /* suppress flicker of the VFDs */ - gpio->MISCCR = 0x40; - gpio->PFCON |= (2<<12); + gpio->misccr = 0x40; + gpio->pfcon |= (2<<12); gd->bd->bi_arch_number = MACH_TYPE_TRAB; @@ -114,8 +114,8 @@ int board_init () gd->bd->bi_boot_params = 0x0c000100; /* Make sure both buzzers are turned off */ - gpio->PDCON |= 0x5400; - gpio->PDDAT &= ~0xE0; + gpio->pdcon |= 0x5400; + gpio->pddat &= ~0xE0; #ifdef CONFIG_VFD vfd_init_clocks(); @@ -132,7 +132,7 @@ int board_init () #ifdef CONFIG_DRIVER_S3C24X0_I2C /* Configure I/O ports PG5 und PG6 for I2C */ - gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00; + gpio->pgcon = (gpio->pgcon & 0x003c00) | 0x003c00; #endif /* CONFIG_DRIVER_S3C24X0_I2C */ return 0; @@ -341,14 +341,14 @@ static inline void SET_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PDDAT &= 0x5FF; + gpio->pddat &= 0x5FF; } static inline void CLR_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PDDAT |= 0x200; + gpio->pddat |= 0x200; } static void spi_init(void) @@ -358,20 +358,20 @@ static void spi_init(void) int i; /* Configure I/O ports. */ - gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; - gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; - gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; - gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; + gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000; + gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000; + gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000; + gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000; CLR_CS_TOUCH(); - spi->ch[0].SPPRE = 0x1F; /* Baudrate ca. 514kHz */ - spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */ - spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */ + spi->ch[0].sppre = 0x1F; /* Baudrate ca. 514kHz */ + spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */ + spi->ch[0].spcon = 0x1A; /* Polling, Prescale, Master, CPOL=0, CPHA=1 */ /* Dummy byte ensures clock to be low. */ for (i = 0; i < 10; i++) { - spi->ch[0].SPTDAT = 0xFF; + spi->ch[0].sptdat = 0xFF; } wait_transmit_done(); } @@ -380,7 +380,8 @@ static void wait_transmit_done(void) { struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */ + while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */ + ; } static void tsc2000_write(unsigned int page, unsigned int reg, @@ -394,13 +395,13 @@ static void tsc2000_write(unsigned int page, unsigned int reg, command |= (page << 11); command |= (reg << 5); - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + spi->ch[0].sptdat = (command & 0xFF00) >> 8; wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); + spi->ch[0].sptdat = (command & 0x00FF); wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; + spi->ch[0].sptdat = (data & 0xFF00) >> 8; wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0x00FF); + spi->ch[0].sptdat = (data & 0x00FF); wait_transmit_done(); CLR_CS_TOUCH(); diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c index 268162e53ae..fe3dab351f9 100644 --- a/board/trab/trab_fkt.c +++ b/board/trab/trab_fkt.c @@ -411,28 +411,28 @@ static int adc_read (unsigned int channel) padc = s3c2400_get_base_adc(); channel &= 0x7; - padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ - padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ - padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); + padc->adccon &= ~ADC_STDBM; /* select normal mode */ + padc->adccon &= ~(0x7 << 3); /* clear the channel bits */ + padc->adccon |= ((channel << 3) | ADC_ENABLE_START); while (j--) { - if ((padc->ADCCON & ADC_ENABLE_START) == 0) + if ((padc->adccon & ADC_ENABLE_START) == 0) break; udelay (1); } if (j == 0) { printf("%s: ADC timeout\n", __FUNCTION__); - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + padc->adccon |= ADC_STDBM; /* select standby mode */ return -1; } - result = padc->ADCDAT & 0x3FF; + result = padc->adcdat & 0x3FF; - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + padc->adccon |= ADC_STDBM; /* select standby mode */ debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, - (padc->ADCCON >> 3) & 0x7, result); + (padc->adccon >> 3) & 0x7, result); /* * Wait for ADC to be ready for next conversion. This delay value was @@ -450,8 +450,8 @@ static void adc_init (void) padc = s3c2400_get_base_adc(); - padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ - padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ + padc->adccon &= ~(0xff << 6); /* clear prescaler bits */ + padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ /* * Wait some time to avoid problem with very first call of @@ -493,10 +493,10 @@ int do_power_switch (void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* configure GPE7 as input */ - gpio->PECON &= ~(0x3 << (2 * 7)); + gpio->pecon &= ~(0x3 << (2 * 7)); /* signal GPE7 from power switch is low active: 0=on , 1=off */ - result = ((gpio->PEDAT & (1 << 7)) == (1 << 7)) ? 0 : 1; + result = ((gpio->pedat & (1 << 7)) == (1 << 7)) ? 0 : 1; print_identifier (); printf("%d\n", result); @@ -561,17 +561,17 @@ int do_vfd_id (void) /* try to red vfd board id from the value defined by pull-ups */ - pcup_old = gpio->PCUP; - pccon_old = gpio->PCCON; + pcup_old = gpio->pcup; + pccon_old = gpio->pccon; - gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pull-ups */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as + gpio->pcup = (gpio->pcup & 0xFFF0); /* activate GPC0...GPC3 pull-ups */ + gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* configure GPC0...GPC3 as * inputs */ udelay (10); /* allow signals to settle */ - vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */ + vfd_board_id = (~gpio->pcdat) & 0x000F; /* read GPC0...GPC3 port pins */ - gpio->PCCON = pccon_old; - gpio->PCUP = pcup_old; + gpio->pccon = pccon_old; + gpio->pcup = pcup_old; /* print vfd_board_id to console */ print_identifier (); @@ -593,40 +593,40 @@ int do_buzzer (char * const *argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* set prescaler for timer 2, 3 and 4 */ - timers->TCFG0 &= ~0xFF00; - timers->TCFG0 |= 0x0F00; + timers->tcfg0 &= ~0xFF00; + timers->tcfg0 |= 0x0F00; /* set divider for timer 2 */ - timers->TCFG1 &= ~0xF00; - timers->TCFG1 |= 0x300; + timers->tcfg1 &= ~0xF00; + timers->tcfg1 |= 0x300; /* set frequency */ counter = (PCLK / BUZZER_FREQ) >> 9; - timers->ch[2].TCNTB = counter; - timers->ch[2].TCMPB = counter / 2; + timers->ch[2].tcntb = counter; + timers->ch[2].tcmpb = counter / 2; if (strcmp (argv[2], "on") == 0) { debug ("%s: frequency: %d\n", __FUNCTION__, BUZZER_FREQ); /* configure pin GPD7 as TOUT2 */ - gpio->PDCON &= ~0xC000; - gpio->PDCON |= 0x8000; + gpio->pdcon &= ~0xC000; + gpio->pdcon |= 0x8000; /* start */ - timers->TCON = (timers->TCON | UPDATE2 | RELOAD2) & + timers->tcon = (timers->tcon | UPDATE2 | RELOAD2) & ~INVERT2; - timers->TCON = (timers->TCON | START2) & ~UPDATE2; + timers->tcon = (timers->tcon | START2) & ~UPDATE2; return (0); } else if (strcmp (argv[2], "off") == 0) { /* stop */ - timers->TCON &= ~(START2 | RELOAD2); + timers->tcon &= ~(START2 | RELOAD2); /* configure GPD7 as output and set to low */ - gpio->PDCON &= ~0xC000; - gpio->PDCON |= 0x4000; - gpio->PDDAT &= ~0x80; + gpio->pdcon &= ~0xC000; + gpio->pdcon |= 0x4000; + gpio->pddat &= ~0x80; return (0); } @@ -640,12 +640,12 @@ int do_led (char * const *argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* configure PC14 and PC15 as output */ - gpio->PCCON &= ~(0xF << 28); - gpio->PCCON |= (0x5 << 28); + gpio->pccon &= ~(0xF << 28); + gpio->pccon |= (0x5 << 28); /* configure PD0 and PD4 as output */ - gpio->PDCON &= ~((0x3 << 8) | 0x3); - gpio->PDCON |= ((0x1 << 8) | 0x1); + gpio->pdcon &= ~((0x3 << 8) | 0x3); + gpio->pdcon |= ((0x1 << 8) | 0x1); switch (simple_strtoul(argv[2], NULL, 10)) { @@ -655,30 +655,30 @@ int do_led (char * const *argv) case 2: if (strcmp (argv[3], "on") == 0) - gpio->PCDAT |= (1 << 14); + gpio->pcdat |= (1 << 14); else - gpio->PCDAT &= ~(1 << 14); + gpio->pcdat &= ~(1 << 14); return 0; case 3: if (strcmp (argv[3], "on") == 0) - gpio->PCDAT |= (1 << 15); + gpio->pcdat |= (1 << 15); else - gpio->PCDAT &= ~(1 << 15); + gpio->pcdat &= ~(1 << 15); return 0; case 4: if (strcmp (argv[3], "on") == 0) - gpio->PDDAT |= (1 << 0); + gpio->pddat |= (1 << 0); else - gpio->PDDAT &= ~(1 << 0); + gpio->pddat &= ~(1 << 0); return 0; case 5: if (strcmp (argv[3], "on") == 0) - gpio->PDDAT |= (1 << 4); + gpio->pddat |= (1 << 4); else - gpio->PDDAT &= ~(1 << 4); + gpio->pddat &= ~(1 << 4); return 0; default: @@ -695,22 +695,22 @@ int do_full_bridge (char * const *argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* configure PD5 and PD6 as output */ - gpio->PDCON &= ~((0x3 << 5*2) | (0x3 << 6*2)); - gpio->PDCON |= ((0x1 << 5*2) | (0x1 << 6*2)); + gpio->pdcon &= ~((0x3 << 5*2) | (0x3 << 6*2)); + gpio->pdcon |= ((0x1 << 5*2) | (0x1 << 6*2)); if (strcmp (argv[2], "+") == 0) { - gpio->PDDAT |= (1 << 5); - gpio->PDDAT |= (1 << 6); + gpio->pddat |= (1 << 5); + gpio->pddat |= (1 << 6); return 0; } else if (strcmp (argv[2], "-") == 0) { - gpio->PDDAT &= ~(1 << 5); - gpio->PDDAT |= (1 << 6); + gpio->pddat &= ~(1 << 5); + gpio->pddat |= (1 << 6); return 0; } else if (strcmp (argv[2], "off") == 0) { - gpio->PDDAT &= ~(1 << 5); - gpio->PDDAT &= ~(1 << 6); + gpio->pddat &= ~(1 << 5); + gpio->pddat &= ~(1 << 6); return 0; } printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); @@ -804,15 +804,15 @@ int do_motor (char * const *argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* Configure I/O port */ - gpio->PGCON &= ~(0x3 << 0); - gpio->PGCON |= (0x1 << 0); + gpio->pgcon &= ~(0x3 << 0); + gpio->pgcon |= (0x1 << 0); if (strcmp (argv[2], "on") == 0) { - gpio->PGDAT &= ~(1 << 0); + gpio->pgdat &= ~(1 << 0); return 0; } if (strcmp (argv[2], "off") == 0) { - gpio->PGDAT |= (1 << 0); + gpio->pgdat |= (1 << 0); return 0; } printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); @@ -832,36 +832,36 @@ int do_pwm (char * const *argv) if (strcmp (argv[2], "on") == 0) { /* configure pin GPD8 as TOUT3 */ - gpio->PDCON &= ~(0x3 << 8*2); - gpio->PDCON |= (0x2 << 8*2); + gpio->pdcon &= ~(0x3 << 8*2); + gpio->pdcon |= (0x2 << 8*2); /* set prescaler for timer 2, 3 and 4 */ - timers->TCFG0 &= ~0xFF00; - timers->TCFG0 |= 0x0F00; + timers->tcfg0 &= ~0xFF00; + timers->tcfg0 |= 0x0F00; /* set divider for timer 3 */ - timers->TCFG1 &= ~(0xf << 12); - timers->TCFG1 |= (0x3 << 12); + timers->tcfg1 &= ~(0xf << 12); + timers->tcfg1 |= (0x3 << 12); /* set frequency */ counter = (PCLK / PWM_FREQ) >> 9; - timers->ch[3].TCNTB = counter; - timers->ch[3].TCMPB = counter / 2; + timers->ch[3].tcntb = counter; + timers->ch[3].tcmpb = counter / 2; /* start timer */ - timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3; - timers->TCON = (timers->TCON | START3) & ~UPDATE3; + timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3; + timers->tcon = (timers->tcon | START3) & ~UPDATE3; return 0; } if (strcmp (argv[2], "off") == 0) { /* stop timer */ - timers->TCON &= ~(START2 | RELOAD2); + timers->tcon &= ~(START2 | RELOAD2); /* configure pin GPD8 as output and set to 0 */ - gpio->PDCON &= ~(0x3 << 8*2); - gpio->PDCON |= (0x1 << 8*2); - gpio->PDDAT &= ~(1 << 8); + gpio->pdcon &= ~(0x3 << 8*2); + gpio->pdcon |= (0x1 << 8*2); + gpio->pddat &= ~(1 << 8); return 0; } printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c index 5890624f0f0..426ed9c520b 100644 --- a/board/trab/tsc2000.c +++ b/board/trab/tsc2000.c @@ -50,21 +50,21 @@ void tsc2000_spi_init(void) int i; /* Configure I/O ports. */ - gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; - gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; - gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; - gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; + gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000; + gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000; + gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000; + gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000; CLR_CS_TOUCH(); - spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */ - spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */ - spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0, + spi->ch[0].sppre = 0x1F; /* Baud-rate ca. 514kHz */ + spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */ + spi->ch[0].spcon = 0x1A; /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */ /* Dummy byte ensures clock to be low. */ for (i = 0; i < 10; i++) { - spi->ch[0].SPTDAT = 0xFF; + spi->ch[0].sptdat = 0xFF; } spi_wait_transmit_done(); } @@ -74,7 +74,8 @@ void spi_wait_transmit_done(void) { struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */ + while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */ + ; } @@ -85,13 +86,13 @@ void tsc2000_write(unsigned short reg, unsigned short data) SET_CS_TOUCH(); command = reg; - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + spi->ch[0].sptdat = (command & 0xFF00) >> 8; spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); + spi->ch[0].sptdat = (command & 0x00FF); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; + spi->ch[0].sptdat = (data & 0xFF00) >> 8; spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0x00FF); + spi->ch[0].sptdat = (data & 0x00FF); spi_wait_transmit_done(); CLR_CS_TOUCH(); @@ -106,19 +107,19 @@ unsigned short tsc2000_read (unsigned short reg) SET_CS_TOUCH(); command = 0x8000 | reg; - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + spi->ch[0].sptdat = (command & 0xFF00) >> 8; spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); + spi->ch[0].sptdat = (command & 0x00FF); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = 0xFF; + spi->ch[0].sptdat = 0xFF; spi_wait_transmit_done(); - data = spi->ch[0].SPRDAT; - spi->ch[0].SPTDAT = 0xFF; + data = spi->ch[0].sprdat; + spi->ch[0].sptdat = 0xFF; spi_wait_transmit_done(); CLR_CS_TOUCH(); - return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8); + return (spi->ch[0].sprdat & 0x0FF) | (data << 8); } diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h index 0b6253f6566..f3cecb928e2 100644 --- a/board/trab/tsc2000.h +++ b/board/trab/tsc2000.h @@ -29,45 +29,49 @@ #define _TSC2000_H_ /* temperature channel multiplexer definitions */ -#define CON_MUX0 (gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100) -#define CLR_MUX0 (gpio->PCDAT &= 0x0FFEF) -#define SET_MUX0 (gpio->PCDAT |= 0x00010) - -#define CON_MUX1 (gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400) -#define CLR_MUX1 (gpio->PCDAT &= 0x0FFDF) -#define SET_MUX1 (gpio->PCDAT |= 0x00020) - -#define CON_MUX1_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000) -#define CLR_MUX1_ENABLE (gpio->PCDAT |= 0x00040) -#define SET_MUX1_ENABLE (gpio->PCDAT &= 0x0FFBF) - -#define CON_MUX2_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000) -#define CLR_MUX2_ENABLE (gpio->PCDAT |= 0x00080) -#define SET_MUX2_ENABLE (gpio->PCDAT &= 0x0FF7F) - -#define CON_MUX3_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000) -#define CLR_MUX3_ENABLE (gpio->PCDAT |= 0x00100) -#define SET_MUX3_ENABLE (gpio->PCDAT &= 0x0FEFF) - -#define CON_MUX4_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000) -#define CLR_MUX4_ENABLE (gpio->PCDAT |= 0x00200) -#define SET_MUX4_ENABLE (gpio->PCDAT &= 0x0FDFF) - -#define CON_SEL_TEMP_V_0 (gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000) -#define CLR_SEL_TEMP_V_0 (gpio->PCDAT &= 0x0FBFF) -#define SET_SEL_TEMP_V_0 (gpio->PCDAT |= 0x00400) - -#define CON_SEL_TEMP_V_1 (gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000) -#define CLR_SEL_TEMP_V_1 (gpio->PCDAT &= 0x0F7FF) -#define SET_SEL_TEMP_V_1 (gpio->PCDAT |= 0x00800) - -#define CON_SEL_TEMP_V_2 (gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000) -#define CLR_SEL_TEMP_V_2 (gpio->PCDAT &= 0x0EFFF) -#define SET_SEL_TEMP_V_2 (gpio->PCDAT |= 0x01000) - -#define CON_SEL_TEMP_V_3 (gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000) -#define CLR_SEL_TEMP_V_3 (gpio->PCDAT &= 0x0DFFF) -#define SET_SEL_TEMP_V_3 (gpio->PCDAT |= 0x02000) +#define CON_MUX0 (gpio->pccon = (gpio->pccon & 0x0FFFFFCFF) | 0x00000100) +#define CLR_MUX0 (gpio->pcdat &= 0x0FFEF) +#define SET_MUX0 (gpio->pcdat |= 0x00010) + +#define CON_MUX1 (gpio->pccon = (gpio->pccon & 0x0FFFFF3FF) | 0x00000400) +#define CLR_MUX1 (gpio->pcdat &= 0x0FFDF) +#define SET_MUX1 (gpio->pcdat |= 0x00020) + +#define CON_MUX1_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFFCFFF) | 0x00001000) +#define CLR_MUX1_ENABLE (gpio->pcdat |= 0x00040) +#define SET_MUX1_ENABLE (gpio->pcdat &= 0x0FFBF) + +#define CON_MUX2_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFF3FFF) | 0x00004000) +#define CLR_MUX2_ENABLE (gpio->pcdat |= 0x00080) +#define SET_MUX2_ENABLE (gpio->pcdat &= 0x0FF7F) + +#define CON_MUX3_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFCFFFF) | 0x00010000) +#define CLR_MUX3_ENABLE (gpio->pcdat |= 0x00100) +#define SET_MUX3_ENABLE (gpio->pcdat &= 0x0FEFF) + +#define CON_MUX4_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFF3FFFF) | 0x00040000) +#define CLR_MUX4_ENABLE (gpio->pcdat |= 0x00200) +#define SET_MUX4_ENABLE (gpio->pcdat &= 0x0FDFF) + +#define CON_SEL_TEMP_V_0 (gpio->pccon = (gpio->pccon & 0x0FFCFFFFF) | \ + 0x00100000) +#define CLR_SEL_TEMP_V_0 (gpio->pcdat &= 0x0FBFF) +#define SET_SEL_TEMP_V_0 (gpio->pcdat |= 0x00400) + +#define CON_SEL_TEMP_V_1 (gpio->pccon = (gpio->pccon & 0x0FF3FFFFF) | \ + 0x00400000) +#define CLR_SEL_TEMP_V_1 (gpio->pcdat &= 0x0F7FF) +#define SET_SEL_TEMP_V_1 (gpio->pcdat |= 0x00800) + +#define CON_SEL_TEMP_V_2 (gpio->pccon = (gpio->pccon & 0x0FCFFFFFF) | \ + 0x01000000) +#define CLR_SEL_TEMP_V_2 (gpio->pcdat &= 0x0EFFF) +#define SET_SEL_TEMP_V_2 (gpio->pcdat |= 0x01000) + +#define CON_SEL_TEMP_V_3 (gpio->pccon = (gpio->pccon & 0x0F3FFFFFF) | \ + 0x04000000) +#define CLR_SEL_TEMP_V_3 (gpio->pcdat &= 0x0DFFF) +#define SET_SEL_TEMP_V_3 (gpio->pcdat |= 0x02000) /* TSC2000 register definition */ #define TSC2000_REG_X ((0 << 11) | (0 << 5)) @@ -130,7 +134,7 @@ static inline void SET_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PDDAT &= 0x5FF; + gpio->pddat &= 0x5FF; } @@ -138,7 +142,7 @@ static inline void CLR_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PDDAT |= 0x200; + gpio->pddat |= 0x200; } #endif /* _TSC2000_H_ */ diff --git a/board/trab/vfd.c b/board/trab/vfd.c index b7eb8cce03c..9a2b1ba1a5a 100644 --- a/board/trab/vfd.c +++ b/board/trab/vfd.c @@ -365,12 +365,12 @@ int vfd_init_clocks (void) /* try to determine display type from the value * defined by pull-ups */ - gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */ + gpio->pcup = (gpio->pcup & 0xFFF0); /* activate GPC0...GPC3 pullups */ + gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* cfg GPC0...GPC3 inputs */ /* allow signals to settle */ for (i=0; i<10000; i++) /* udelay isn't working yet at this point! */ __asm__("NOP"); - vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */ + vfd_board_id = (~gpio->pcdat) & 0x000F; /* read GPC0...GPC3 port pins */ VFD_DISABLE; /* activate blank for the vfd */ @@ -381,39 +381,39 @@ int vfd_init_clocks (void) /* If new board revision, then use PWM 3 as cpld-clock */ /* Enable 500 Hz timer for fill level sensor to operate properly */ /* Configure TOUT3 as functional pin, disable pull-up */ - gpio->PDCON &= ~0x30000; - gpio->PDCON |= 0x20000; - gpio->PDUP |= (1 << 8); + gpio->pdcon &= ~0x30000; + gpio->pdcon |= 0x20000; + gpio->pdup |= (1 << 8); /* Configure the prescaler */ - timers->TCFG0 &= ~0xff00; - timers->TCFG0 |= 0x0f00; + timers->tcfg0 &= ~0xff00; + timers->tcfg0 |= 0x0f00; /* Select MUX input (divider) for timer3 (1/16) */ - timers->TCFG1 &= ~0xf000; - timers->TCFG1 |= 0x3000; + timers->tcfg1 &= ~0xf000; + timers->tcfg1 |= 0x3000; /* Enable autoreload and set the counter and compare * registers to values for the 500 Hz clock * (for a given prescaler (15) and divider (16)): * counter = (66000000 / 500) >> 9; */ - timers->ch[3].TCNTB = 0x101; - timers->ch[3].TCMPB = 0x101 / 2; + timers->ch[3].tcntb = 0x101; + timers->ch[3].tcmpb = 0x101 / 2; /* Start timer */ - timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3; - timers->TCON = (timers->TCON | START3) & ~UPDATE3; + timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3; + timers->tcon = (timers->tcon | START3) & ~UPDATE3; } #endif /* If old board revision, then use vm-signal as cpld-clock */ - lcd->LCDCON2 = 0x00FFC000; - lcd->LCDCON3 = 0x0007FF00; - lcd->LCDCON4 = 0x00000000; - lcd->LCDCON5 = 0x00000400; - lcd->LCDCON1 = 0x00000B75; + lcd->lcdcon2 = 0x00FFC000; + lcd->lcdcon3 = 0x0007FF00; + lcd->lcdcon4 = 0x00000000; + lcd->lcdcon5 = 0x00000400; + lcd->lcdcon1 = 0x00000B75; /* VM (GPD1) is used as clock for the CPLD */ - gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008; + gpio->pdcon = (gpio->pdcon & 0xFFFFFFF3) | 0x00000008; return 0; } @@ -485,40 +485,44 @@ int drv_vfd_init(void) * see manual S3C2400 */ /* Stopp LCD-Controller */ - lcd->LCDCON1 = 0x00000000; + lcd->lcdcon1 = 0x00000000; /* frame buffer startadr */ - lcd->LCDSADDR1 = gd->fb_base >> 1; + lcd->lcdsaddr1 = gd->fb_base >> 1; /* frame buffer endadr */ - lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1; - lcd->LCDSADDR3 = ((256/4)); - lcd->LCDCON2 = 0x000DC000; + lcd->lcdsaddr2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1; + lcd->lcdsaddr3 = ((256/4)); + lcd->lcdcon2 = 0x000DC000; if(gd->vfd_type == VFD_TYPE_MN11236) - lcd->LCDCON2 = 37 << 14; /* MN11236: 38 lines */ + lcd->lcdcon2 = 37 << 14; /* MN11236: 38 lines */ else - lcd->LCDCON2 = 55 << 14; /* T119C: 56 lines */ - lcd->LCDCON3 = 0x0051000A; - lcd->LCDCON4 = 0x00000001; + lcd->lcdcon2 = 55 << 14; /* T119C: 56 lines */ + lcd->lcdcon3 = 0x0051000A; + lcd->lcdcon4 = 0x00000001; if (gd->vfd_type && vfd_inv_data) - lcd->LCDCON5 = 0x000004C0; + lcd->lcdcon5 = 0x000004C0; else - lcd->LCDCON5 = 0x00000440; + lcd->lcdcon5 = 0x00000440; /* Port pins as LCD output */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00)| 0x000000AA; - gpio->PDCON = (gpio->PDCON & 0xFFFFFF03)| 0x000000A8; + gpio->pccon = (gpio->pccon & 0xFFFFFF00) | 0x000000AA; + gpio->pdcon = (gpio->pdcon & 0xFFFFFF03) | 0x000000A8; /* Synchronize VFD enable with LCD controller to avoid flicker */ - lcd->LCDCON1 = 0x00000B75; /* Start LCD-Controller */ - while((lcd->LCDCON5 & 0x180000)!=0x100000); /* Wait for end of VSYNC */ - while((lcd->LCDCON5 & 0x060000)!=0x040000); /* Wait for next HSYNC */ - while((lcd->LCDCON5 & 0x060000)==0x040000); - while((lcd->LCDCON5 & 0x060000)!=0x000000); + lcd->lcdcon1 = 0x00000B75; /* Start LCD-Controller */ + while ((lcd->lcdcon5 & 0x180000) != 0x100000) /* Wait for VSYNC end */ + ; + while ((lcd->lcdcon5 & 0x060000) != 0x040000) /* Wait for next HSYNC */ + ; + while ((lcd->lcdcon5 & 0x060000) == 0x040000) + ; + while ((lcd->lcdcon5 & 0x060000) != 0x000000) + ; if(gd->vfd_type) VFD_ENABLE; - debug ("LCDSADDR1: %lX\n", lcd->LCDSADDR1); - debug ("LCDSADDR2: %lX\n", lcd->LCDSADDR2); - debug ("LCDSADDR3: %lX\n", lcd->LCDSADDR3); + debug("LCDSADDR1: %lX\n", lcd->lcdsaddr1); + debug("LCDSADDR2: %lX\n", lcd->lcdsaddr2); + debug("LCDSADDR3: %lX\n", lcd->lcdsaddr3); return 0; } @@ -532,8 +536,8 @@ void disable_vfd (void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); VFD_DISABLE; - gpio->PDCON &= ~0xC; - gpio->PDUP &= ~0x2; + gpio->pdcon &= ~0xC; + gpio->pdup &= ~0x2; } /************************************************************************/ diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index c8371cf730c..ba6f39bee11 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -58,10 +58,10 @@ static int GetI2CSDA(void) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); #ifdef CONFIG_S3C2410 - return (readl(&gpio->GPEDAT) & 0x8000) >> 15; + return (readl(&gpio->gpedat) & 0x8000) >> 15; #endif #ifdef CONFIG_S3C2400 - return (readl(&gpio->PGDAT) & 0x0020) >> 5; + return (readl(&gpio->pgdat) & 0x0020) >> 5; #endif } @@ -77,10 +77,10 @@ static void SetI2CSCL(int x) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); #ifdef CONFIG_S3C2410 - writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT); + writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat); #endif #ifdef CONFIG_S3C2400 - writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT); + writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); #endif } @@ -90,26 +90,26 @@ static int WaitForXfer(void) int i; i = I2C_TIMEOUT * 10000; - while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) { + while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) { udelay(100); i--; } - return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; + return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; } static int IsACK(void) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); - return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK); + return !(readl(&i2c->iicstat) & I2CSTAT_NACK); } static void ReadWriteByte(void) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); - writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON); + writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); } void i2c_init(int speed, int slaveadd) @@ -122,30 +122,30 @@ void i2c_init(int speed, int slaveadd) /* wait for some time to give previous transfer a chance to finish */ i = I2C_TIMEOUT * 1000; - while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) { + while ((readl(&i2c->iicstat) && I2CSTAT_BSY) && (i > 0)) { udelay(1000); i--; } - if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || GetI2CSDA() == 0) { + if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) { #ifdef CONFIG_S3C2410 - ulong old_gpecon = readl(&gpio->GPECON); + ulong old_gpecon = readl(&gpio->gpecon); #endif #ifdef CONFIG_S3C2400 - ulong old_gpecon = readl(&gpio->PGCON); + ulong old_gpecon = readl(&gpio->pgcon); #endif /* bus still busy probably by (most) previously interrupted transfer */ #ifdef CONFIG_S3C2410 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ - writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000, - &gpio->GPECON); + writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000, + &gpio->gpecon); #endif #ifdef CONFIG_S3C2400 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ - writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000, - &gpio->PGCON); + writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000, + &gpio->pgcon); #endif /* toggle I2CSCL until bus idle */ @@ -164,10 +164,10 @@ void i2c_init(int speed, int slaveadd) /* restore pin functions */ #ifdef CONFIG_S3C2410 - writel(old_gpecon, &gpio->GPECON); + writel(old_gpecon, &gpio->gpecon); #endif #ifdef CONFIG_S3C2400 - writel(old_gpecon, &gpio->PGCON); + writel(old_gpecon, &gpio->pgcon); #endif } @@ -183,13 +183,13 @@ void i2c_init(int speed, int slaveadd) /* set prescaler, divisor according to freq, also set * ACKGEN, IRQ */ - writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON); + writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); /* init to SLAVE REVEIVE and set slaveaddr */ - writel(0, &i2c->IICSTAT); - writel(slaveadd, &i2c->IICADD); + writel(0, &i2c->iicstat); + writel(slaveadd, &i2c->iicadd); /* program Master Transmit (and implicit STOP) */ - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); } @@ -218,47 +218,47 @@ int i2c_transfer(unsigned char cmd_type, /* Check I2C bus idle */ i = I2C_TIMEOUT * 1000; - while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) { + while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { udelay(1000); i--; } - if (readl(&i2c->IICSTAT) & I2CSTAT_BSY) + if (readl(&i2c->iicstat) & I2CSTAT_BSY) return I2C_NOK_TOUT; - writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon); result = I2C_OK; switch (cmd_type) { case I2C_WRITE: if (addr && addr_len) { - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* send START */ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->IICSTAT); + &i2c->iicstat); i = 0; while ((i < addr_len) && (result == I2C_OK)) { result = WaitForXfer(); - writel(addr[i], &i2c->IICDS); + writel(addr[i], &i2c->iicds); ReadWriteByte(); i++; } i = 0; while ((i < data_len) && (result == I2C_OK)) { result = WaitForXfer(); - writel(data[i], &i2c->IICDS); + writel(data[i], &i2c->iicds); ReadWriteByte(); i++; } } else { - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* send START */ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->IICSTAT); + &i2c->iicstat); i = 0; while ((i < data_len) && (result = I2C_OK)) { result = WaitForXfer(); - writel(data[i], &i2c->IICDS); + writel(data[i], &i2c->iicds); ReadWriteByte(); i++; } @@ -268,42 +268,42 @@ int i2c_transfer(unsigned char cmd_type, result = WaitForXfer(); /* send STOP */ - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); ReadWriteByte(); break; case I2C_READ: if (addr && addr_len) { - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); - writel(chip, &i2c->IICDS); + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); + writel(chip, &i2c->iicds); /* send START */ - writel(readl(&i2c->IICSTAT) | I2C_START_STOP, - &i2c->IICSTAT); + writel(readl(&i2c->iicstat) | I2C_START_STOP, + &i2c->iicstat); result = WaitForXfer(); if (IsACK()) { i = 0; while ((i < addr_len) && (result == I2C_OK)) { - writel(addr[i], &i2c->IICDS); + writel(addr[i], &i2c->iicds); ReadWriteByte(); result = WaitForXfer(); i++; } - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* resend START */ writel(I2C_MODE_MR | I2C_TXRX_ENA | - I2C_START_STOP, &i2c->IICSTAT); + I2C_START_STOP, &i2c->iicstat); ReadWriteByte(); result = WaitForXfer(); i = 0; while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - writel(readl(&i2c->IICCON) - & ~0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) + & ~0x80, &i2c->iiccon); ReadWriteByte(); result = WaitForXfer(); - data[i] = readl(&i2c->IICDS); + data[i] = readl(&i2c->iicds); i++; } } else { @@ -311,11 +311,11 @@ int i2c_transfer(unsigned char cmd_type, } } else { - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); - writel(chip, &i2c->IICDS); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); + writel(chip, &i2c->iicds); /* send START */ - writel(readl(&i2c->IICSTAT) | I2C_START_STOP, - &i2c->IICSTAT); + writel(readl(&i2c->iicstat) | I2C_START_STOP, + &i2c->iicstat); result = WaitForXfer(); if (IsACK()) { @@ -323,11 +323,11 @@ int i2c_transfer(unsigned char cmd_type, while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - writel(readl(&i2c->IICCON) & - ~0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) & + ~0x80, &i2c->iiccon); ReadWriteByte(); result = WaitForXfer(); - data[i] = readl(&i2c->IICDS); + data[i] = readl(&i2c->iicds); i++; } } else { @@ -336,7 +336,7 @@ int i2c_transfer(unsigned char cmd_type, } /* send STOP */ - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); ReadWriteByte(); break; diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index a27d47e5f1f..f70daefbfe1 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -69,11 +69,11 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) chip->IO_ADDR_W = (void *)IO_ADDR_W; if (ctrl & NAND_NCE) - writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE, - &nand->NFCONF); + writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE, + &nand->nfconf); else - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE, - &nand->NFCONF); + writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE, + &nand->nfconf); } if (cmd != NAND_CMD_NONE) @@ -84,7 +84,7 @@ static int s3c2410_dev_ready(struct mtd_info *mtd) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); debugX(1, "dev_ready\n"); - return readl(&nand->NFSTAT) & 0x01; + return readl(&nand->nfstat) & 0x01; } #ifdef CONFIG_S3C2410_NAND_HWECC @@ -92,16 +92,16 @@ void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF); + writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf); } static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); - ecc_code[0] = readb(&nand->NFECC); - ecc_code[1] = readb(&nand->NFECC + 1); - ecc_code[2] = readb(&nand->NFECC + 2); + ecc_code[0] = readb(&nand->nfecc); + ecc_code[1] = readb(&nand->nfecc + 1); + ecc_code[2] = readb(&nand->nfecc + 2); debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", mtd , ecc_code[0], ecc_code[1], ecc_code[2]); @@ -130,7 +130,7 @@ int board_nand_init(struct nand_chip *nand) debugX(1, "board_nand_init()\n"); - writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); /* initialize hardware */ twrph0 = 3; @@ -141,10 +141,11 @@ int board_nand_init(struct nand_chip *nand) cfg |= S3C2410_NFCONF_TACLS(tacls - 1); cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); - writel(cfg, &nand_reg->NFCONF); + writel(cfg, &nand_reg->nfconf); /* initialize nand_chip data structure */ - nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; + nand->IO_ADDR_R = (void *)&nand_reg->nfdata; + nand->IO_ADDR_W = (void *)&nand_reg->nfdata; nand->select_chip = NULL; diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c index 04de5ca545d..7f02f0585ff 100644 --- a/drivers/rtc/s3c24x0_rtc.c +++ b/drivers/rtc/s3c24x0_rtc.c @@ -49,11 +49,11 @@ static inline void SetRTC_Access(RTC_ACCESS a) switch (a) { case RTC_ENABLE: - writeb(readb(&rtc->RTCCON) | 0x01, &rtc->RTCCON); + writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon); break; case RTC_DISABLE: - writeb(readb(&rtc->RTCCON) & ~0x01, &rtc->RTCCON); + writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon); break; } } @@ -71,23 +71,23 @@ int rtc_get(struct rtc_time *tmp) /* read RTC registers */ do { - sec = readb(&rtc->BCDSEC); - min = readb(&rtc->BCDMIN); - hour = readb(&rtc->BCDHOUR); - mday = readb(&rtc->BCDDATE); - wday = readb(&rtc->BCDDAY); - mon = readb(&rtc->BCDMON); - year = readb(&rtc->BCDYEAR); - } while (sec != readb(&rtc->BCDSEC)); + sec = readb(&rtc->bcdsec); + min = readb(&rtc->bcdmin); + hour = readb(&rtc->bcdhour); + mday = readb(&rtc->bcddate); + wday = readb(&rtc->bcdday); + mon = readb(&rtc->bcdmon); + year = readb(&rtc->bcdyear); + } while (sec != readb(&rtc->bcdsec)); /* read ALARM registers */ - a_sec = readb(&rtc->ALMSEC); - a_min = readb(&rtc->ALMMIN); - a_hour = readb(&rtc->ALMHOUR); - a_date = readb(&rtc->ALMDATE); - a_mon = readb(&rtc->ALMMON); - a_year = readb(&rtc->ALMYEAR); - a_armed = readb(&rtc->RTCALM); + a_sec = readb(&rtc->almsec); + a_min = readb(&rtc->almmin); + a_hour = readb(&rtc->almhour); + a_date = readb(&rtc->almdate); + a_mon = readb(&rtc->almmon); + a_year = readb(&rtc->almyear); + a_armed = readb(&rtc->rtcalm); /* disable access to RTC registers */ SetRTC_Access(RTC_DISABLE); @@ -145,13 +145,13 @@ int rtc_set(struct rtc_time *tmp) SetRTC_Access(RTC_ENABLE); /* write RTC registers */ - writeb(sec, &rtc->BCDSEC); - writeb(min, &rtc->BCDMIN); - writeb(hour, &rtc->BCDHOUR); - writeb(mday, &rtc->BCDDATE); - writeb(wday, &rtc->BCDDAY); - writeb(mon, &rtc->BCDMON); - writeb(year, &rtc->BCDYEAR); + writeb(sec, &rtc->bcdsec); + writeb(min, &rtc->bcdmin); + writeb(hour, &rtc->bcdhour); + writeb(mday, &rtc->bcddate); + writeb(wday, &rtc->bcdday); + writeb(mon, &rtc->bcdmon); + writeb(year, &rtc->bcdyear); /* disable access to RTC registers */ SetRTC_Access(RTC_DISABLE); @@ -163,8 +163,8 @@ void rtc_reset(void) { struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - writeb((readb(&rtc->RTCCON) & ~0x06) | 0x08, &rtc->RTCCON); - writeb(readb(&rtc->RTCCON) & ~(0x08 | 0x01), &rtc->RTCCON); + writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon); + writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon); } #endif diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index 8a3e30209cf..f42b15e45ec 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -101,7 +101,7 @@ void _serial_setbrg(const int dev_index) /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ reg = get_PCLK() / (16 * gd->baudrate) - 1; - writel(reg, &uart->UBRDIV); + writel(reg, &uart->ubrdiv); for (i = 0; i < 100; i++) /* Delay */ ; } @@ -131,26 +131,26 @@ static int serial_init_dev(const int dev_index) #endif /* FIFO enable, Tx/Rx FIFO clear */ - writel(0x07, &uart->UFCON); - writel(0x0, &uart->UMCON); + writel(0x07, &uart->ufcon); + writel(0x0, &uart->umcon); /* Normal,No parity,1 stop,8 bit */ - writel(0x3, &uart->ULCON); + writel(0x3, &uart->ulcon); /* * tx=level,rx=edge,disable timeout int.,enable rx error int., * normal,interrupt or polling */ - writel(0x245, &uart->UCON); + writel(0x245, &uart->ucon); #ifdef CONFIG_HWFLOW - writel(0x1, &uart->UMCON); /* RTS up */ + writel(0x1, &uart->umcon); /* rts up */ #endif /* FIXME: This is sooooooooooooooooooo ugly */ #if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2) /* we need auto hw flow control on the gsm and gps port */ if (dev_index == 0 || dev_index == 1) - writel(0x10, &uart->UMCON); + writel(0x10, &uart->umcon); #endif _serial_setbrg(dev_index); @@ -176,10 +176,10 @@ int _serial_getc(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - while (!(readl(&uart->UTRSTAT) & 0x1)) + while (!(readl(&uart->utrstat) & 0x1)) /* wait for character to arrive */ ; - return readb(&uart->URXH) & 0xff; + return readb(&uart->urxh) & 0xff; } #if defined(CONFIG_SERIAL_MULTI) @@ -237,15 +237,15 @@ void _serial_putc(const char c, const int dev_index) return; #endif - while (!(readl(&uart->UTRSTAT) & 0x2)) + while (!(readl(&uart->utrstat) & 0x2)) /* wait for room in the tx FIFO */ ; #ifdef CONFIG_HWFLOW - while (hwflow && !(readl(&uart->UMSTAT) & 0x1)) + while (hwflow && !(readl(&uart->umstat) & 0x1)) /* Wait for CTS up */ ; #endif - writeb(c, &uart->UTXH); + writeb(c, &uart->utxh); /* If \n, also do \r */ if (c == '\n') @@ -272,7 +272,7 @@ int _serial_tstc(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - return readl(&uart->UTRSTAT) & 0x1; + return readl(&uart->utrstat) & 0x1; } #if defined(CONFIG_SERIAL_MULTI) -- cgit v1.3.1 From 2e5167ccad93ca9cfa6a2acfab5e4785418e477e Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 28 Oct 2010 20:00:11 +0200 Subject: Replace CONFIG_RELOC_FIXUP_WORKS by CONFIG_NEEDS_MANUAL_RELOC By now, the majority of architectures have working relocation support, so the few remaining architectures have become exceptions. To make this more obvious, we make working relocation now the default case, and flag the remaining cases with CONFIG_NEEDS_MANUAL_RELOC. Signed-off-by: Wolfgang Denk Tested-by: Heiko Schocher Tested-by: Reinhard Meyer --- arch/arm/include/asm/config.h | 3 --- arch/arm/lib/board.c | 32 -------------------------------- arch/avr32/include/asm/config.h | 2 ++ arch/avr32/lib/board.c | 4 ++-- arch/blackfin/include/asm/config.h | 3 --- arch/i386/include/asm/config.h | 2 -- arch/m68k/include/asm/config.h | 2 ++ arch/m68k/lib/board.c | 4 ++-- arch/microblaze/include/asm/config.h | 3 --- arch/mips/include/asm/config.h | 2 ++ arch/mips/lib/board.c | 4 ++-- arch/nios2/include/asm/config.h | 3 --- arch/powerpc/include/asm/config.h | 3 --- arch/sh/include/asm/config.h | 3 --- arch/sparc/include/asm/config.h | 2 ++ arch/sparc/lib/board.c | 4 ++-- common/cmd_bmp.c | 2 +- common/cmd_bootm.c | 2 +- common/cmd_date.c | 6 +++--- common/cmd_i2c.c | 2 +- common/cmd_nvedit.c | 2 +- common/cmd_onenand.c | 2 +- common/command.c | 2 +- common/dlmalloc.c | 2 +- common/env_common.c | 2 +- common/hush.c | 4 ++-- common/image.c | 8 ++++---- common/serial.c | 2 +- common/stdio.c | 4 ++-- disk/part.c | 4 ++-- doc/README.arm-relocation | 5 ++--- drivers/mtd/nand/nand.c | 2 +- drivers/net/phy/miiphybb.c | 2 +- fs/ubifs/ubifs.c | 2 +- include/command.h | 2 +- include/post.h | 2 +- post/post.c | 2 +- 37 files changed, 46 insertions(+), 91 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 4124f0a9922..c60dba26bfa 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -21,9 +21,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -/* Relocation to SDRAM works on all ARM boards */ -#define CONFIG_RELOC_FIXUP_WORKS - #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH #endif diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index af9a414b88b..33b369496a1 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -678,15 +678,6 @@ void board_init_r (gd_t *id, ulong dest_addr) ulong malloc_start; #if !defined(CONFIG_SYS_NO_FLASH) ulong flash_size; -#endif -#if !defined(CONFIG_RELOC_FIXUP_WORKS) - extern void malloc_bin_reloc (void); -#if defined(CONFIG_CMD_BMP) - extern void bmp_reloc(void); -#endif -#if defined(CONFIG_CMD_I2C) - extern void i2c_reloc(void); -#endif #endif gd = id; @@ -704,39 +695,16 @@ void board_init_r (gd_t *id, ulong dest_addr) debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); -#if !defined(CONFIG_RELOC_FIXUP_WORKS) - /* - * We have to relocate the command table manually - */ - fixup_cmdtable(&__u_boot_cmd_start, - (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); -#if defined(CONFIG_CMD_BMP) - bmp_reloc(); -#endif -#if defined(CONFIG_CMD_I2C) - i2c_reloc(); -#endif -#if defined(CONFIG_CMD_ONENAND) - onenand_reloc(); -#endif -#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */ - #ifdef CONFIG_LOGBUFFER logbuff_init_ptrs (); #endif #ifdef CONFIG_POST post_output_backlog (); -#ifndef CONFIG_RELOC_FIXUP_WORKS - post_reloc (); -#endif #endif /* The Malloc area is immediately below the monitor copy in DRAM */ malloc_start = dest_addr - TOTAL_MALLOC_LEN; mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN); -#if !defined(CONFIG_RELOC_FIXUP_WORKS) - malloc_bin_reloc (); -#endif #if !defined(CONFIG_SYS_NO_FLASH) puts ("FLASH: "); diff --git a/arch/avr32/include/asm/config.h b/arch/avr32/include/asm/config.h index 049c44eaf84..02fbfb3abfe 100644 --- a/arch/avr32/include/asm/config.h +++ b/arch/avr32/include/asm/config.h @@ -21,4 +21,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_NEEDS_MANUAL_RELOC + #endif diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index 96ccc7fa795..8b56237f189 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -272,13 +272,13 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) monitor_flash_len = _edata - _text; -#if !defined(CONFIG_RELOC_FIXUP_WORKS) +#if defined(CONFIG_NEEDS_MANUAL_RELOC) /* * We have to relocate the command table manually */ fixup_cmdtable(&__u_boot_cmd_start, (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); -#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */ +#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ /* there are some other pointer constants we must deal with */ #ifndef CONFIG_ENV_IS_NOWHERE diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h index 34ca68c9d54..388434fea26 100644 --- a/arch/blackfin/include/asm/config.h +++ b/arch/blackfin/include/asm/config.h @@ -13,9 +13,6 @@ # define CONFIG_BFIN_SCRATCH_REG retn #endif -/* Relocation to SDRAM works on all Blackfin boards */ -#define CONFIG_RELOC_FIXUP_WORKS - /* Make sure the structure is properly aligned */ #if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR) # error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned diff --git a/arch/i386/include/asm/config.h b/arch/i386/include/asm/config.h index 1952de79f8a..049c44eaf84 100644 --- a/arch/i386/include/asm/config.h +++ b/arch/i386/include/asm/config.h @@ -21,6 +21,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_RELOC_FIXUP_WORKS - #endif diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h index ec2cc16beba..51050a39a3e 100644 --- a/arch/m68k/include/asm/config.h +++ b/arch/m68k/include/asm/config.h @@ -21,6 +21,8 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_NEEDS_MANUAL_RELOC + #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH #define CONFIG_SYS_BOOT_GET_CMDLINE diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index 976d5bf28af..9a519088582 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -420,13 +420,13 @@ void board_init_r (gd_t *id, ulong dest_addr) monitor_flash_len = (ulong)&__init_end - dest_addr; -#if !defined(CONFIG_RELOC_FIXUP_WORKS) +#if defined(CONFIG_NEEDS_MANUAL_RELOC) /* * We have to relocate the command table manually */ fixup_cmdtable(&__u_boot_cmd_start, (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); -#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */ +#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ /* there are some other pointer constants we must deal with */ #ifndef CONFIG_ENV_IS_NOWHERE diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h index 8a9064b3c88..049c44eaf84 100644 --- a/arch/microblaze/include/asm/config.h +++ b/arch/microblaze/include/asm/config.h @@ -21,7 +21,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -/* Relocation to SDRAM works on all Microblaze boards */ -#define CONFIG_RELOC_FIXUP_WORKS - #endif diff --git a/arch/mips/include/asm/config.h b/arch/mips/include/asm/config.h index 049c44eaf84..02fbfb3abfe 100644 --- a/arch/mips/include/asm/config.h +++ b/arch/mips/include/asm/config.h @@ -21,4 +21,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_NEEDS_MANUAL_RELOC + #endif diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index 4a22f7b41c7..f3171241556 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -295,13 +295,13 @@ void board_init_r (gd_t *id, ulong dest_addr) monitor_flash_len = (ulong)&uboot_end_data - dest_addr; -#if !defined(CONFIG_RELOC_FIXUP_WORKS) +#if defined(CONFIG_NEEDS_MANUAL_RELOC) /* * We have to relocate the command table manually */ fixup_cmdtable(&__u_boot_cmd_start, (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); -#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */ +#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ /* there are some other pointer constants we must deal with */ #ifndef CONFIG_ENV_IS_NOWHERE diff --git a/arch/nios2/include/asm/config.h b/arch/nios2/include/asm/config.h index 011d603a4b8..049c44eaf84 100644 --- a/arch/nios2/include/asm/config.h +++ b/arch/nios2/include/asm/config.h @@ -21,7 +21,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -/* Relocation to SDRAM works on all NIOS2 boards */ -#define CONFIG_RELOC_FIXUP_WORKS - #endif diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index a1942ca2bd9..76dedebe67c 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -89,9 +89,6 @@ #define CONFIG_SYS_NUM_TLBCAMS 16 #endif -/* Relocation to SDRAM works on all PPC boards */ -#define CONFIG_RELOC_FIXUP_WORKS - /* Since so many PPC SOCs have a semi-common LBC, define this here */ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ defined(CONFIG_MPC83xx) diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h index 978cc92f40a..049c44eaf84 100644 --- a/arch/sh/include/asm/config.h +++ b/arch/sh/include/asm/config.h @@ -21,7 +21,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -/* Relocation to SDRAM works on all sh boards */ -#define CONFIG_RELOC_FIXUP_WORKS - #endif diff --git a/arch/sparc/include/asm/config.h b/arch/sparc/include/asm/config.h index 6ddc3494c6b..7b6f30bd4a8 100644 --- a/arch/sparc/include/asm/config.h +++ b/arch/sparc/include/asm/config.h @@ -21,6 +21,8 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_NEEDS_MANUAL_RELOC + #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index 4a6041f51ca..ab31cfb50ad 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -252,13 +252,13 @@ void board_init_f(ulong bootflag) post_run(NULL, POST_ROM | post_bootmode_get(0)); #endif -#if !defined(CONFIG_RELOC_FIXUP_WORKS) +#if defined(CONFIG_NEEDS_MANUAL_RELOC) /* * We have to relocate the command table manually */ fixup_cmdtable(&__u_boot_cmd_start, (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); -#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */ +#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ #if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP) puts("AMBA:\n"); diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c index 6fa8a150235..f2a48f751c2 100644 --- a/common/cmd_bmp.c +++ b/common/cmd_bmp.c @@ -137,7 +137,7 @@ static cmd_tbl_t cmd_bmp_sub[] = { U_BOOT_CMD_MKENT(display, 5, 0, do_bmp_display, "", ""), }; -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC void bmp_reloc(void) { fixup_cmdtable(cmd_bmp_sub, ARRAY_SIZE(cmd_bmp_sub)); } diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index ce3c77c6157..1a024f168f7 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -590,7 +590,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ulong load_end = 0; int ret; boot_os_fn *boot_fn; -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC static int relocated = 0; /* relocate boot function table */ diff --git a/common/cmd_date.c b/common/cmd_date.c index 50b42402673..8dbf16d32a1 100644 --- a/common/cmd_date.c +++ b/common/cmd_date.c @@ -35,10 +35,10 @@ const char *weekdays[] = { "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", }; -#ifdef CONFIG_RELOC_FIXUP_WORKS -#define RELOC(a) a -#else +#ifdef CONFIG_NEEDS_MANUAL_RELOC #define RELOC(a) ((typeof(a))((unsigned long)(a) + gd->reloc_off)) +#else +#define RELOC(a) a #endif int mk_date (char *, struct rtc_time *); diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 0a0cfceb45c..c272b0dd4f7 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -1284,7 +1284,7 @@ static cmd_tbl_t cmd_i2c_sub[] = { U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""), }; -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC void i2c_reloc(void) { fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub)); } diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 3d30c321d5b..3fd8abc157f 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -837,7 +837,7 @@ static cmd_tbl_t cmd_env_sub[] = { U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 0, do_env_set, "", ""), }; -#if !defined(CONFIG_RELOC_FIXUP_WORKS) +#if defined(CONFIG_NEEDS_MANUAL_RELOC) void env_reloc(void) { fixup_cmdtable(cmd_env_sub, ARRAY_SIZE(cmd_env_sub)); diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c index 5550b40b81d..33108f1b34a 100644 --- a/common/cmd_onenand.c +++ b/common/cmd_onenand.c @@ -525,7 +525,7 @@ static cmd_tbl_t cmd_onenand_sub[] = { U_BOOT_CMD_MKENT(markbad, CONFIG_SYS_MAXARGS, 0, do_onenand_markbad, "", ""), }; -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC void onenand_reloc(void) { fixup_cmdtable(cmd_onenand_sub, ARRAY_SIZE(cmd_onenand_sub)); } diff --git a/common/command.c b/common/command.c index d47d719779f..0020eacf5c4 100644 --- a/common/command.c +++ b/common/command.c @@ -466,7 +466,7 @@ int cmd_get_data_size(char* arg, int default_size) } #endif -#if !defined(CONFIG_RELOC_FIXUP_WORKS) +#if defined(CONFIG_NEEDS_MANUAL_RELOC) DECLARE_GLOBAL_DATA_PTR; void fixup_cmdtable(cmd_tbl_t *cmdtp, int size) diff --git a/common/dlmalloc.c b/common/dlmalloc.c index fce7a762b1e..4871f4b0990 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1491,7 +1491,7 @@ static mbinptr av_[NAV * 2 + 2] = { IAV(120), IAV(121), IAV(122), IAV(123), IAV(124), IAV(125), IAV(126), IAV(127) }; -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC void malloc_bin_reloc (void) { unsigned long *p = (unsigned long *)(&av_[2]); diff --git a/common/env_common.c b/common/env_common.c index 5acda4d49ed..a276efc6347 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -227,7 +227,7 @@ int env_import(const char *buf, int check) void env_relocate (void) { -#if !defined(CONFIG_RELOC_FIXUP_WORKS) +#if defined(CONFIG_NEEDS_MANUAL_RELOC) extern void env_reloc(void); env_reloc(); diff --git a/common/hush.c b/common/hush.c index 4dd9513b036..2188fd4ac8d 100644 --- a/common/hush.c +++ b/common/hush.c @@ -3268,7 +3268,7 @@ int parse_file_outer(void) } #ifdef __U_BOOT__ -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC static void u_boot_hush_reloc(void) { unsigned long addr; @@ -3290,7 +3290,7 @@ int u_boot_hush_start(void) top_vars->next = 0; top_vars->flg_export = 0; top_vars->flg_read_only = 1; -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC u_boot_hush_reloc(); #endif } diff --git a/common/image.c b/common/image.c index 89c10b8596e..42f5b79cf2e 100644 --- a/common/image.c +++ b/common/image.c @@ -520,7 +520,7 @@ char *get_table_entry_name (table_entry_t *table, char *msg, int id) { for (; table->id >= 0; ++table) { if (table->id == id) -#if defined(USE_HOSTCC) || defined(CONFIG_RELOC_FIXUP_WORKS) +#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC) return table->lname; #else return table->lname + gd->reloc_off; @@ -585,10 +585,10 @@ int get_table_entry_id (table_entry_t *table, fprintf (stderr, "\n"); #else for (t = table; t->id >= 0; ++t) { -#ifdef CONFIG_RELOC_FIXUP_WORKS - if (t->sname && strcmp(t->sname, name) == 0) -#else +#ifdef CONFIG_NEEDS_MANUAL_RELOC if (t->sname && strcmp(t->sname + gd->reloc_off, name) == 0) +#else + if (t->sname && strcmp(t->sname, name) == 0) #endif return (t->id); } diff --git a/common/serial.c b/common/serial.c index c3323ea51ac..051ae4e1d22 100644 --- a/common/serial.c +++ b/common/serial.c @@ -99,7 +99,7 @@ struct serial_device *default_serial_console(void) __attribute__((weak, alias("_ int serial_register (struct serial_device *dev) { -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC dev->init += gd->reloc_off; dev->setbrg += gd->reloc_off; dev->getc += gd->reloc_off; diff --git a/common/stdio.c b/common/stdio.c index 25013693f7d..ab7c5abde1b 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -193,7 +193,7 @@ int stdio_deregister(char *devname) int stdio_init (void) { -#if !defined(CONFIG_RELOC_FIXUP_WORKS) +#if defined(CONFIG_NEEDS_MANUAL_RELOC) /* already relocated for current ARM implementation */ ulong relocation_offset = gd->reloc_off; int i; @@ -203,7 +203,7 @@ int stdio_init (void) stdio_names[i] = (char *) (((ulong) stdio_names[i]) + relocation_offset); } -#endif /* !CONFIG_RELOC_FIXUP_WORKS */ +#endif /* CONFIG_NEEDS_MANUAL_RELOC */ /* Initialize the list */ INIT_LIST_HEAD(&(devs.list)); diff --git a/disk/part.c b/disk/part.c index 2b63db6c75f..13723f23b31 100644 --- a/disk/part.c +++ b/disk/part.c @@ -81,13 +81,13 @@ block_dev_desc_t *get_dev(char* ifname, int dev) char *name; name = drvr->name; -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC name += gd->reloc_off; #endif while (name) { name = drvr->name; reloc_get_dev = drvr->get_dev; -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC name += gd->reloc_off; reloc_get_dev += gd->reloc_off; #endif diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation index dc7be7e42e4..2f91d0ac43f 100644 --- a/doc/README.arm-relocation +++ b/doc/README.arm-relocation @@ -36,15 +36,14 @@ At lib level: At config level: - Define CONFIG_RELOC_FIXUP_WORKS. Undefine CONFIG_SYS_ARM_WITHOUT_RELOC * WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING * Boards which are not fixed to support relocation will be REMOVED! -Eventually, CONFIG_SYS_ARM_WITHOUT_RELOC and CONFIG_RELOC_FIXUP_WORKS will -disappear and boards which have to migrated to relocation will disappear too. +Eventually, CONFIG_SYS_ARM_WITHOUT_RELOC will disappear and boards +which have to migrated to relocation will disappear too. ----------------------------------------------------------------------------- diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index 47d6872fd03..c0e068ab7d5 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -54,7 +54,7 @@ static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand, if (nand_scan(mtd, maxchips) == 0) { if (!mtd->name) mtd->name = (char *)default_nand_name; -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC else mtd->name += gd->reloc_off; #endif diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index 1045cf1ba98..49a1f5fb49f 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -127,7 +127,7 @@ void bb_miiphy_init(void) int i; for (i = 0; i < bb_miiphy_buses_num; i++) { -#if !defined(CONFIG_RELOC_FIXUP_WORKS) +#if defined(CONFIG_NEEDS_MANUAL_RELOC) /* Relocate the hook pointers*/ BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off); BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off); diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 3fc79909eaa..1cc31a968dd 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -121,7 +121,7 @@ static int __init compr_init(struct ubifs_compressor *compr) { ubifs_compressors[compr->compr_type] = compr; -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC ubifs_compressors[compr->compr_type]->name += gd->reloc_off; ubifs_compressors[compr->compr_type]->capi_name += gd->reloc_off; ubifs_compressors[compr->compr_type]->decompress += gd->reloc_off; diff --git a/include/command.h b/include/command.h index 5c146162337..46a9ec4c4ca 100644 --- a/include/command.h +++ b/include/command.h @@ -125,7 +125,7 @@ cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage} #endif /* CONFIG_SYS_LONGHELP */ -#if !defined(CONFIG_RELOC_FIXUP_WORKS) +#if defined(CONFIG_NEEDS_MANUAL_RELOC) void fixup_cmdtable(cmd_tbl_t *cmdtp, int size); #endif #endif /* __COMMAND_H */ diff --git a/include/post.h b/include/post.h index abe47da53bf..957ce3b1616 100644 --- a/include/post.h +++ b/include/post.h @@ -137,7 +137,7 @@ void post_output_backlog ( void ); int post_run (char *name, int flags); int post_info (char *name); int post_log (char *format, ...); -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC void post_reloc (void); #endif unsigned long post_time_ms (unsigned long base); diff --git a/post/post.c b/post/post.c index 8a9fd0d2ec1..1b7f2aa075e 100644 --- a/post/post.c +++ b/post/post.c @@ -422,7 +422,7 @@ int post_log (char *format, ...) return 0; } -#ifndef CONFIG_RELOC_FIXUP_WORKS +#ifdef CONFIG_NEEDS_MANUAL_RELOC void post_reloc (void) { unsigned int i; -- cgit v1.3.1