From 352214e8b2fadae4af7b7d9c849af24a7350ab2b Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Thu, 23 Oct 2025 17:16:01 +0530 Subject: pci_endpoint: pci_cdns_ti_ep: Add delay after power domain reset Add a 1ms delay after powering on the PCIe power domain to ensure the controller stabilizes before subsequent operations. This prevents potential timing issues during PCIe endpoint initialization. The delay allows sufficient time for the power domain to fully come up and the hardware to be in a stable state before configuration begins. Signed-off-by: Hrushikesh Salunke --- drivers/pci_endpoint/pcie_cdns_ti_ep.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci_endpoint/pcie_cdns_ti_ep.c b/drivers/pci_endpoint/pcie_cdns_ti_ep.c index 661b6ba5b55..541616ab7d0 100644 --- a/drivers/pci_endpoint/pcie_cdns_ti_ep.c +++ b/drivers/pci_endpoint/pcie_cdns_ti_ep.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "pcie-cadence.h" @@ -90,7 +91,7 @@ static int pcie_cdns_reset(struct udevice *dev, struct power_domain *pci_pwrdmn) dev_err(dev, "failed to power on: %d\n", ret); return ret; } - + mdelay(1); return 0; } -- cgit v1.2.3 From f0c7d4b4c637a3ae74f71d4a4b565e8ba999d744 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Thu, 23 Oct 2025 17:16:02 +0530 Subject: pci_endpoint: pci_cdns_ti_ep: Add SERDES mux configuration support Probe the mux device early in the SERDES configuration flow to ensure proper lane routing before PHY initialization. This is required for SoCs where SERDES lanes can be muxed between different controllers (PCIe, USB, etc), and different mux configurations are required between different boot phases. Signed-off-by: Hrushikesh Salunke --- drivers/pci_endpoint/pcie_cdns_ti_ep.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci_endpoint/pcie_cdns_ti_ep.c b/drivers/pci_endpoint/pcie_cdns_ti_ep.c index 541616ab7d0..dd3dc939a7e 100644 --- a/drivers/pci_endpoint/pcie_cdns_ti_ep.c +++ b/drivers/pci_endpoint/pcie_cdns_ti_ep.c @@ -97,9 +97,20 @@ static int pcie_cdns_reset(struct udevice *dev, struct power_domain *pci_pwrdmn) static int pcie_cdns_config_serdes(struct udevice *dev) { + int ret; + + if (CONFIG_IS_ENABLED(MUX_MMIO)) { + struct udevice *mux; + + ret = uclass_get_device_by_seq(UCLASS_MUX, 0, &mux); + if (ret) { + dev_err(dev, "unable to get mux\n"); + return ret; + } + } + if (CONFIG_IS_ENABLED(PHY_CADENCE_TORRENT)) { struct phy serdes; - int ret = 7; ret = generic_phy_get_by_name(dev, "pcie-phy", &serdes); if (ret != 0 && ret != -EBUSY) { -- cgit v1.2.3 From 8692f48baad3b94357dc6fd114ebed8c633637a6 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Thu, 23 Oct 2025 17:16:03 +0530 Subject: pci_endpoint: pci_cdns_ti_ep: Enable PCIe Endpoint mode in J784S4 SoC TI's J784S4 SoC has two instances of PCIe Controller namely PCIe0 and PCIe1 which are Cadence PCIe Controllers. Add support to configure PCIe instances in Endpoint mode of operation. While at it disable all endpoint functions except function 0 during probe to prevent the Root Complex from enumerating unconfigured functions. This ensures only properly configured endpoint functions are visible to the host and avoids enumeration issues with multi-function devices. Signed-off-by: Hrushikesh Salunke --- drivers/pci_endpoint/pcie_cdns_ti_ep.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers') diff --git a/drivers/pci_endpoint/pcie_cdns_ti_ep.c b/drivers/pci_endpoint/pcie_cdns_ti_ep.c index dd3dc939a7e..021bd73a383 100644 --- a/drivers/pci_endpoint/pcie_cdns_ti_ep.c +++ b/drivers/pci_endpoint/pcie_cdns_ti_ep.c @@ -275,9 +275,11 @@ static int pcie_cdns_ti_ep_probe(struct udevice *dev) struct pcie_cdns_ti_ep *pcie = dev_get_priv(dev); struct pcie_cdns_ti_ep_data *data; struct power_domain pci_pwrdmn; + struct cdns_pcie pcie_dev; struct clk *clk; int ret; + pcie_dev.reg_base = pcie->reg_base; pcie->dev = dev; data = (struct pcie_cdns_ti_ep_data *)dev_get_driver_data(dev); if (!data) @@ -328,6 +330,13 @@ static int pcie_cdns_ti_ep_probe(struct udevice *dev) return ret; } + /* + * Disable all the functions except function 0 (anyway BIT(0) is + * hardwired to 1). This is required to avoid RC from enumerating + * those functions which are not even configured. + */ + cdns_pcie_writel(&pcie_dev, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0)); + return 0; } @@ -389,11 +398,19 @@ static const struct pcie_cdns_ti_ep_data am64_pcie_ep_data = { .max_lanes = 1, }; +static const struct pcie_cdns_ti_ep_data j784s4_pcie_ep_data = { + .max_lanes = 4, +}; + static const struct udevice_id pcie_cdns_ti_ep_ids[] = { { .compatible = "ti,am64-pcie-ep", .data = (ulong)&am64_pcie_ep_data, }, + { + .compatible = "ti,j784s4-pcie-ep", + .data = (ulong)&j784s4_pcie_ep_data, + }, {}, }; -- cgit v1.2.3