From 959198f7cacea1076b3a43721ec173266f3158af Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 16 May 2014 13:59:52 +0900 Subject: mmc: exynos_dw_mmc: restore the property into host Restore the platdata(property of dt) into host struct. Then data's information is maintained and reused anywhere. Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/mmc/exynos_dw_mmc.c | 204 ++++++++++++++++++++++++++++---------------- 1 file changed, 131 insertions(+), 73 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index de8cdcc42b3..28941ad0fd5 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #define DWMMC_MAX_CH_NUM 4 #define DWMMC_MAX_FREQ 52000000 @@ -44,7 +46,11 @@ unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) & DWMCI_DIVRATIO_MASK) + 1; sclk = get_mmc_clk(host->dev_index); - return sclk / clk_div; + /* + * Assume to know divider value. + * When clock unit is broken, need to set "host->div" + */ + return sclk / clk_div / (host->div + 1); } static void exynos_dwmci_board_init(struct dwmci_host *host) @@ -60,45 +66,32 @@ static void exynos_dwmci_board_init(struct dwmci_host *host) } } -/* - * This function adds the mmc channel to be registered with mmc core. - * index - mmc channel number. - * regbase - register base address of mmc channel specified in 'index'. - * bus_width - operating bus width of mmc channel specified in 'index'. - * clksel - value to be written into CLKSEL register in case of FDT. - * NULL in case od non-FDT. - */ -int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) +static int exynos_dwmci_core_init(struct dwmci_host *host, int index) { - struct dwmci_host *host = NULL; unsigned int div; unsigned long freq, sclk; - host = malloc(sizeof(struct dwmci_host)); - if (!host) { - printf("dwmci_host malloc fail!\n"); - return 1; - } + + if (host->bus_hz) + freq = host->bus_hz; + else + freq = DWMMC_MAX_FREQ; + /* request mmc clock vlaue of 52MHz. */ - freq = 52000000; sclk = get_mmc_clk(index); div = DIV_ROUND_UP(sclk, freq); /* set the clock divisor for mmc */ set_mmc_clk(index, div); host->name = "EXYNOS DWMMC"; - host->ioaddr = (void *)regbase; - host->buswidth = bus_width; #ifdef CONFIG_EXYNOS5420 host->quirks = DWMCI_QUIRK_DISABLE_SMU; #endif host->board_init = exynos_dwmci_board_init; - if (clksel) { - host->clksel_val = clksel; - } else { - if (0 == index) + if (!host->clksel_val) { + if (index == 0) host->clksel_val = DWMMC_MMC0_CLKSEL_VAL; - if (2 == index) + else if (index == 2) host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; } @@ -113,69 +106,134 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) return 0; } +/* + * This function adds the mmc channel to be registered with mmc core. + * index - mmc channel number. + * regbase - register base address of mmc channel specified in 'index'. + * bus_width - operating bus width of mmc channel specified in 'index'. + * clksel - value to be written into CLKSEL register in case of FDT. + * NULL in case od non-FDT. + */ +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) +{ + struct dwmci_host *host = NULL; + + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + error("dwmci_host malloc fail!\n"); + return -ENOMEM; + } + + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + + if (clksel) + host->clksel_val = clksel; + + return exynos_dwmci_core_init(host, index); +} + #ifdef CONFIG_OF_CONTROL -int exynos_dwmmc_init(const void *blob) +static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; + +static int do_dwmci_init(struct dwmci_host *host) { - int index, bus_width; - int node_list[DWMMC_MAX_CH_NUM]; - int err = 0, dev_id, flag, count, i; - u32 clksel_val, base, timing[3]; + int index, flag, err; - count = fdtdec_find_aliases_for_id(blob, "mmc", - COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list, - DWMMC_MAX_CH_NUM); + index = host->dev_index; - for (i = 0; i < count; i++) { - int node = node_list[i]; + flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; + err = exynos_pinmux_config(host->dev_id, flag); + if (err) { + debug("DWMMC not configure\n"); + return err; + } - if (node <= 0) - continue; + return exynos_dwmci_core_init(host, index); +} - /* Extract device id for each mmc channel */ - dev_id = pinmux_decode_periph_id(blob, node); +static int exynos_dwmci_get_config(const void *blob, int node, + struct dwmci_host *host) +{ + int err = 0; + u32 base, clksel_val, timing[3]; - /* Get the bus width from the device node */ - bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); - if (bus_width <= 0) { - debug("DWMMC: Can't get bus-width\n"); - return -1; - } - if (8 == bus_width) - flag = PINMUX_FLAG_8BIT_MODE; - else - flag = PINMUX_FLAG_NONE; + /* Extract device id for each mmc channel */ + host->dev_id = pinmux_decode_periph_id(blob, node); - /* config pinmux for each mmc channel */ - err = exynos_pinmux_config(dev_id, flag); - if (err) { - debug("DWMMC not configured\n"); - return err; - } + /* Get the bus width from the device node */ + host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0); + if (host->buswidth <= 0) { + debug("DWMMC: Can't get bus-width\n"); + return -EINVAL; + } - index = dev_id - PERIPH_ID_SDMMC0; + host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); + if (host->dev_index == host->dev_id) + host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; - /* Get the base address from the device node */ - base = fdtdec_get_addr(blob, node, "reg"); - if (!base) { - debug("DWMMC: Can't get base address\n"); - return -1; - } - /* Extract the timing info from the node */ - err = fdtdec_get_int_array(blob, node, "samsung,timing", - timing, 3); + /* Set the base address from the device node */ + base = fdtdec_get_addr(blob, node, "reg"); + if (!base) { + debug("DWMMC: Can't get base address\n"); + return -EINVAL; + } + host->ioaddr = (void *)base; + + /* Extract the timing info from the node */ + err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); + if (err) { + debug("Can't get sdr-timings for devider\n"); + return -EINVAL; + } + + clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(timing[2])); + if (clksel_val) + host->clksel_val = clksel_val; + + host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); + host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); + host->div = fdtdec_get_int(blob, node, "div", 0); + + return 0; +} + +static int exynos_dwmci_process_node(const void *blob, + int node_list[], int count) +{ + struct dwmci_host *host; + int i, node, err; + + for (i = 0; i < count; i++) { + node = node_list[i]; + if (node <= 0) + continue; + host = &dwmci_host[i]; + err = exynos_dwmci_get_config(blob, node, host); if (err) { - debug("Can't get sdr-timings for divider\n"); - return -1; + debug("%s: failed to decode dev %d\n", __func__, i); + return err; } - clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | - DWMCI_SET_DRV_CLK(timing[1]) | - DWMCI_SET_DIV_RATIO(timing[2])); - /* Initialise each mmc channel */ - err = exynos_dwmci_add_port(index, base, bus_width, clksel_val); - if (err) - debug("dwmmc Channel-%d init failed\n", index); + do_dwmci_init(host); } return 0; } + +int exynos_dwmmc_init(const void *blob) +{ + int compat_id; + int node_list[DWMMC_MAX_CH_NUM]; + int err = 0, count; + + compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC; + + count = fdtdec_find_aliases_for_id(blob, "mmc", + compat_id, node_list, DWMMC_MAX_CH_NUM); + err = exynos_dwmci_process_node(blob, node_list, count); + + return err; +} #endif -- cgit v1.3.1 From 8caf46d1890b625aafe9cc16114b3c65842dbb98 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 16 May 2014 13:59:53 +0900 Subject: mmc: remove the unnecessary define and fix the wrong bit control Signed-off-by: Jaehoon Chung Reviewed-by: Lukasz Majeski Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/mmc/mmc.c | 2 +- include/mmc.h | 18 ++++++------------ 2 files changed, 7 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 16051e52ff1..dd6a6ef57ce 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -514,7 +514,7 @@ static int mmc_change_freq(struct mmc *mmc) return 0; /* High Speed is set, there are two types: 52MHz and 26MHz */ - if (cardtype & MMC_HS_52MHZ) + if (cardtype & EXT_CSD_CARD_TYPE_52) mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; else mmc->card_caps |= MMC_MODE_HS; diff --git a/include/mmc.h b/include/mmc.h index bc11f45a6fc..d5a896fbb13 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -32,15 +32,12 @@ #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405) -#define MMC_MODE_HS 0x001 -#define MMC_MODE_HS_52MHz 0x010 -#define MMC_MODE_4BIT 0x100 -#define MMC_MODE_8BIT 0x200 -#define MMC_MODE_SPI 0x400 -#define MMC_MODE_HC 0x800 - -#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT) -#define MMC_MODE_WIDTH_BITS_SHIFT 8 +#define MMC_MODE_HS (1 << 0) +#define MMC_MODE_HS_52MHz (1 << 1) +#define MMC_MODE_4BIT (1 << 2) +#define MMC_MODE_8BIT (1 << 3) +#define MMC_MODE_SPI (1 << 4) +#define MMC_MODE_HC (1 << 5) #define SD_DATA_4BIT 0x00040000 @@ -98,9 +95,6 @@ #define SD_HIGHSPEED_BUSY 0x00020000 #define SD_HIGHSPEED_SUPPORTED 0x00020000 -#define MMC_HS_TIMING 0x00000100 -#define MMC_HS_52MHZ 0x2 - #define OCR_BUSY 0x80000000 #define OCR_HCS 0x40000000 #define OCR_VOLTAGE_MASK 0x007FFF80 -- cgit v1.3.1 From d22e3d46a918bde2e6d3bc3f5782548d5ed75358 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 16 May 2014 13:59:54 +0900 Subject: mmc: support the DDR mode for eMMC Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/mmc/mmc.c | 16 +++++++++++++--- include/mmc.h | 7 +++++++ 2 files changed, 20 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index dd6a6ef57ce..08187d5f3ea 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -158,6 +158,9 @@ int mmc_set_blocklen(struct mmc *mmc, int len) { struct mmc_cmd cmd; + if (mmc->card_caps & MMC_MODE_DDR_52MHz) + return 0; + cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; cmd.resp_type = MMC_RSP_R1; cmd.cmdarg = len; @@ -514,10 +517,13 @@ static int mmc_change_freq(struct mmc *mmc) return 0; /* High Speed is set, there are two types: 52MHz and 26MHz */ - if (cardtype & EXT_CSD_CARD_TYPE_52) + if (cardtype & EXT_CSD_CARD_TYPE_52) { + if (cardtype & EXT_CSD_CARD_TYPE_DDR_52) + mmc->card_caps |= MMC_MODE_DDR_52MHz; mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; - else + } else { mmc->card_caps |= MMC_MODE_HS; + } return 0; } @@ -1054,6 +1060,8 @@ static int mmc_startup(struct mmc *mmc) /* An array of possible bus widths in order of preference */ static unsigned ext_csd_bits[] = { + EXT_CSD_DDR_BUS_WIDTH_8, + EXT_CSD_DDR_BUS_WIDTH_4, EXT_CSD_BUS_WIDTH_8, EXT_CSD_BUS_WIDTH_4, EXT_CSD_BUS_WIDTH_1, @@ -1061,13 +1069,15 @@ static int mmc_startup(struct mmc *mmc) /* An array to map CSD bus widths to host cap bits */ static unsigned ext_to_hostcaps[] = { + [EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz, + [EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz, [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, }; /* An array to map chosen bus width to an integer */ static unsigned widths[] = { - 8, 4, 1, + 8, 4, 8, 4, 1, }; for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { diff --git a/include/mmc.h b/include/mmc.h index d5a896fbb13..aa2d1ca3605 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -38,6 +38,7 @@ #define MMC_MODE_8BIT (1 << 3) #define MMC_MODE_SPI (1 << 4) #define MMC_MODE_HC (1 << 5) +#define MMC_MODE_DDR_52MHz (1 << 6) #define SD_DATA_4BIT 0x00040000 @@ -169,10 +170,16 @@ #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) +#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) +#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ + | EXT_CSD_CARD_TYPE_DDR_1_2V) #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ +#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) -- cgit v1.3.1 From 045bdcd0b2ff02effef09d945cee685b88ec521d Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 16 May 2014 13:59:55 +0900 Subject: mmc: dw_mmc: support the DDR mode Support the DDR mode at dw-mmc controller Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/mmc/dw_mmc.c | 12 ++++++++++-- include/dwmmc.h | 3 +++ 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index eb4e2be5143..5bf36a0309d 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -284,8 +284,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) static void dwmci_set_ios(struct mmc *mmc) { - struct dwmci_host *host = mmc->priv; - u32 ctype; + struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + u32 ctype, regs; debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock); @@ -304,6 +304,14 @@ static void dwmci_set_ios(struct mmc *mmc) dwmci_writel(host, DWMCI_CTYPE, ctype); + regs = dwmci_readl(host, DWMCI_UHS_REG); + if (mmc->card_caps & MMC_MODE_DDR_52MHz) + regs |= DWMCI_DDR_MODE; + else + regs &= DWMCI_DDR_MODE; + + dwmci_writel(host, DWMCI_UHS_REG, regs); + if (host->clksel) host->clksel(host); } diff --git a/include/dwmmc.h b/include/dwmmc.h index 14c7db82691..b67f11b113f 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,9 @@ #define DWMCI_BMOD_IDMAC_FB (1 << 1) #define DWMCI_BMOD_IDMAC_EN (1 << 7) +/* UHS register */ +#define DWMCI_DDR_MODE (1 << 16) + /* quirks */ #define DWMCI_QUIRK_DISABLE_SMU (1 << 0) -- cgit v1.3.1 From e09bd85329186015ec1bc663c0d55dd6bec41d2a Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 16 May 2014 13:59:57 +0900 Subject: mmc: exynos_dw_mmc: enable the DDR mode Set the ddr mode capability by default. Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/mmc/exynos_dw_mmc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 28941ad0fd5..d96dfe16a53 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -95,6 +95,7 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index) host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; } + host->caps = MMC_MODE_DDR_52MHz; host->clksel = exynos_dwmci_clksel; host->dev_index = index; host->get_mmc_clk = exynos_dwmci_get_clk; -- cgit v1.3.1 From 9b8c9a3c093afbde1577bd8270904c4d36969ff9 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 16 May 2014 13:59:59 +0900 Subject: mmc: s5p_sdhci: add the s5p_sdhci_core_init function To reuse the code, added the s5p_sdhci_core_init function. Before applied this patch, didn't use the 8-bit mode at exynos baord. Because it didn't set "MMC_MODE_8BIT". Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/mmc/s5p_sdhci.c | 42 +++++++++++++++++------------------------- 1 file changed, 17 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index ccae4ccae15..2ff0ec2a422 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -65,17 +65,9 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host *host) sdhci_writel(host, ctrl, SDHCI_CONTROL2); } -int s5p_sdhci_init(u32 regbase, int index, int bus_width) +static int s5p_sdhci_core_init(struct sdhci_host *host) { - struct sdhci_host *host = NULL; - host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); - if (!host) { - printf("sdhci__host malloc fail!\n"); - return 1; - } - host->name = S5P_NAME; - host->ioaddr = (void *)regbase; host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | @@ -85,15 +77,28 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width) host->set_control_reg = &s5p_sdhci_set_control_reg; host->set_clock = set_mmc_clk; - host->index = index; host->host_caps = MMC_MODE_HC; - if (bus_width == 8) + if (host->bus_width == 8) host->host_caps |= MMC_MODE_8BIT; return add_sdhci(host, 52000000, 400000); } +int s5p_sdhci_init(u32 regbase, int index, int bus_width) +{ + struct sdhci_host *host = malloc(sizeof(struct sdhci_host)); + if (!host) { + printf("sdhci__host malloc fail!\n"); + return 1; + } + host->ioaddr = (void *)regbase; + host->index = index; + host->bus_width = bus_width; + + return s5p_sdhci_core_init(host); +} + #ifdef CONFIG_OF_CONTROL struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS]; @@ -126,20 +131,7 @@ static int do_sdhci_init(struct sdhci_host *host) } } - host->name = S5P_NAME; - - host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | - SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | - SDHCI_QUIRK_WAIT_SEND_CMD; - host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - - host->set_control_reg = &s5p_sdhci_set_control_reg; - host->set_clock = set_mmc_clk; - - host->host_caps = MMC_MODE_HC; - - return add_sdhci(host, 52000000, 400000); + return s5p_sdhci_core_init(host); } static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) -- cgit v1.3.1 From 7d82d897722f57389ebe15924f47fab452cc3a19 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Wed, 7 May 2014 16:50:45 +0800 Subject: gpio: at91: add sanity check for the NULL pointer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need check the NULL pointer as at91_pio_get_port() may return NULL. Also print a error message when at91_pio_get_port() failed otherwise we cannot notice the failure. Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- drivers/gpio/at91_gpio.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 0b70071871c..6517af16281 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -34,6 +34,7 @@ static struct at91_port *at91_pio_get_port(unsigned port) #endif #endif default: + printf("Error: at91_gpio: Fail to get PIO base!\n"); return NULL; } } @@ -200,7 +201,7 @@ int at91_set_pio_output(unsigned port, u32 pin, int value) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &at91_port->idr); writel(mask, &at91_port->pudr); -- cgit v1.3.1 From 9902c7b6f1c9b1e99e4d7c62cc7e98257aa04d0b Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Wed, 7 May 2014 17:06:08 +0800 Subject: mmc: atmel_mci: fix print incorrect buffer content for debug MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Josh Wu [fix checkpatch line length warning] Signed-off-by: Andreas Bießmann --- drivers/mmc/gen_atmel_mci.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index acca0269e58..a57a9b1faff 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -243,9 +243,10 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) #ifdef DEBUG if (data->flags & MMC_DATA_READ) { + u32 cnt = word_count * 4; printf("Read Data:\n"); - print_buffer(0, data->dest, 1, - word_count*4, 0); + print_buffer(0, data->dest + cnt * block_count, + 1, cnt, 0); } #endif #ifdef DEBUG -- cgit v1.3.1 From 54c5d08a09e631f88738db54c75395c6457c2157 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 22 May 2014 12:43:05 +0200 Subject: dm: rename device struct to udevice using UBI and DM together leads in compiler error, as both define a "struct device", so rename "struct device" in include/dm/device.h to "struct udevice", as we use linux code (MTD/UBI/UBIFS some USB code,...) and cannot change the linux "struct device" Signed-off-by: Heiko Schocher Cc: Simon Glass Cc: Marek Vasut --- arch/sandbox/include/asm/gpio.h | 8 ++++---- common/cmd_demo.c | 4 ++-- common/cmd_gpio.c | 4 ++-- doc/driver-model/README.txt | 8 ++++---- drivers/core/device.c | 32 ++++++++++++++++---------------- drivers/core/lists.c | 8 ++++---- drivers/core/root.c | 2 +- drivers/core/uclass.c | 31 ++++++++++++++++--------------- drivers/demo/demo-shape.c | 6 +++--- drivers/demo/demo-simple.c | 4 ++-- drivers/demo/demo-uclass.c | 6 +++--- drivers/gpio/gpio-uclass.c | 28 ++++++++++++++-------------- drivers/gpio/sandbox.c | 34 +++++++++++++++++----------------- include/asm-generic/global_data.h | 2 +- include/asm-generic/gpio.h | 22 +++++++++++----------- include/dm-demo.h | 10 +++++----- include/dm/device-internal.h | 16 ++++++++-------- include/dm/device.h | 20 ++++++++++---------- include/dm/lists.h | 4 ++-- include/dm/root.h | 4 ++-- include/dm/test.h | 12 ++++++------ include/dm/uclass-internal.h | 10 +++++----- include/dm/uclass.h | 18 +++++++++--------- test/dm/cmd_dm.c | 10 +++++----- test/dm/core.c | 32 ++++++++++++++++---------------- test/dm/gpio.c | 2 +- test/dm/test-driver.c | 20 ++++++++++---------- test/dm/test-fdt.c | 10 +++++----- test/dm/test-main.c | 2 +- test/dm/test-uclass.c | 15 ++++++++------- 30 files changed, 193 insertions(+), 191 deletions(-) (limited to 'drivers') diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h index 95b59da6b4d..8317db1ad3d 100644 --- a/arch/sandbox/include/asm/gpio.h +++ b/arch/sandbox/include/asm/gpio.h @@ -29,7 +29,7 @@ * @param gp GPIO number * @return -1 on error, 0 if GPIO is low, >0 if high */ -int sandbox_gpio_get_value(struct device *dev, unsigned int offset); +int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset); /** * Set the simulated value of a GPIO (used only in sandbox test code) @@ -38,7 +38,7 @@ int sandbox_gpio_get_value(struct device *dev, unsigned int offset); * @param value value to set (0 for low, non-zero for high) * @return -1 on error, 0 if ok */ -int sandbox_gpio_set_value(struct device *dev, unsigned int offset, int value); +int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value); /** * Return the simulated direction of a GPIO (used only in sandbox test code) @@ -46,7 +46,7 @@ int sandbox_gpio_set_value(struct device *dev, unsigned int offset, int value); * @param gp GPIO number * @return -1 on error, 0 if GPIO is input, >0 if output */ -int sandbox_gpio_get_direction(struct device *dev, unsigned int offset); +int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset); /** * Set the simulated direction of a GPIO (used only in sandbox test code) @@ -55,7 +55,7 @@ int sandbox_gpio_get_direction(struct device *dev, unsigned int offset); * @param output 0 to set as input, 1 to set as output * @return -1 on error, 0 if ok */ -int sandbox_gpio_set_direction(struct device *dev, unsigned int offset, +int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset, int output); #endif diff --git a/common/cmd_demo.c b/common/cmd_demo.c index a3bba7fdf3c..652c61c7077 100644 --- a/common/cmd_demo.c +++ b/common/cmd_demo.c @@ -11,7 +11,7 @@ #include #include -struct device *demo_dev; +struct udevice *demo_dev; static int do_demo_hello(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -41,7 +41,7 @@ static int do_demo_status(cmd_tbl_t *cmdtp, int flag, int argc, int do_demo_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct device *dev; + struct udevice *dev; int i, ret; puts("Demo uclass entries:\n"); diff --git a/common/cmd_gpio.c b/common/cmd_gpio.c index aff044518f4..4634f914e66 100644 --- a/common/cmd_gpio.c +++ b/common/cmd_gpio.c @@ -30,7 +30,7 @@ static const char * const gpio_function[] = { "unknown", }; -static void show_gpio(struct device *dev, const char *bank_name, int offset) +static void show_gpio(struct udevice *dev, const char *bank_name, int offset) { struct dm_gpio_ops *ops = gpio_get_ops(dev); char buf[80]; @@ -62,7 +62,7 @@ static void show_gpio(struct device *dev, const char *bank_name, int offset) static int do_gpio_status(const char *gpio_name) { - struct device *dev; + struct udevice *dev; int newline = 0; int ret; diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt index e0b395a6186..dcecb9a8c0a 100644 --- a/doc/driver-model/README.txt +++ b/doc/driver-model/README.txt @@ -122,7 +122,7 @@ What is going on? Let's start at the top. The demo command is in common/cmd_demo.c. It does the usual command procesing and then: - struct device *demo_dev; + struct udevice *demo_dev; ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev); @@ -147,7 +147,7 @@ this particular device may use one or other of them. The code for demo_hello() is in drivers/demo/demo-uclass.c: -int demo_hello(struct device *dev, int ch) +int demo_hello(struct udevice *dev, int ch) { const struct demo_ops *ops = device_get_ops(dev); @@ -160,7 +160,7 @@ int demo_hello(struct device *dev, int ch) As you can see it just calls the relevant driver method. One of these is in drivers/demo/demo-simple.c: -static int simple_hello(struct device *dev, int ch) +static int simple_hello(struct udevice *dev, int ch) { const struct dm_demo_pdata *pdata = dev_get_platdata(dev); @@ -321,7 +321,7 @@ instead of struct instance, struct platdata, etc.) this concept relates to a class of drivers (or a subsystem). We shouldn't use 'class' since it is a C++ reserved word, so U-Boot class (uclass) seems better than 'core'. -- Remove 'struct driver_instance' and just use a single 'struct device'. +- Remove 'struct driver_instance' and just use a single 'struct udevice'. This removes a level of indirection that doesn't seem necessary. - Built in device tree support, to avoid the need for platdata - Removed the concept of driver relocation, and just make it possible for diff --git a/drivers/core/device.c b/drivers/core/device.c index 55ba281be0d..c73c339d18c 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -30,9 +30,9 @@ * @dev: The device that is to be stripped of its children * @return 0 on success, -ve on error */ -static int device_chld_unbind(struct device *dev) +static int device_chld_unbind(struct udevice *dev) { - struct device *pos, *n; + struct udevice *pos, *n; int ret, saved_ret = 0; assert(dev); @@ -51,9 +51,9 @@ static int device_chld_unbind(struct device *dev) * @dev: The device whose children are to be removed * @return 0 on success, -ve on error */ -static int device_chld_remove(struct device *dev) +static int device_chld_remove(struct udevice *dev) { - struct device *pos, *n; + struct udevice *pos, *n; int ret; assert(dev); @@ -67,10 +67,10 @@ static int device_chld_remove(struct device *dev) return 0; } -int device_bind(struct device *parent, struct driver *drv, const char *name, - void *platdata, int of_offset, struct device **devp) +int device_bind(struct udevice *parent, struct driver *drv, const char *name, + void *platdata, int of_offset, struct udevice **devp) { - struct device *dev; + struct udevice *dev; struct uclass *uc; int ret = 0; @@ -82,7 +82,7 @@ int device_bind(struct device *parent, struct driver *drv, const char *name, if (ret) return ret; - dev = calloc(1, sizeof(struct device)); + dev = calloc(1, sizeof(struct udevice)); if (!dev) return -ENOMEM; @@ -129,8 +129,8 @@ fail_bind: return ret; } -int device_bind_by_name(struct device *parent, const struct driver_info *info, - struct device **devp) +int device_bind_by_name(struct udevice *parent, const struct driver_info *info, + struct udevice **devp) { struct driver *drv; @@ -142,7 +142,7 @@ int device_bind_by_name(struct device *parent, const struct driver_info *info, -1, devp); } -int device_unbind(struct device *dev) +int device_unbind(struct udevice *dev) { struct driver *drv; int ret; @@ -181,7 +181,7 @@ int device_unbind(struct device *dev) * device_free() - Free memory buffers allocated by a device * @dev: Device that is to be started */ -static void device_free(struct device *dev) +static void device_free(struct udevice *dev) { int size; @@ -200,7 +200,7 @@ static void device_free(struct device *dev) } } -int device_probe(struct device *dev) +int device_probe(struct udevice *dev) { struct driver *drv; int size = 0; @@ -279,7 +279,7 @@ fail: return ret; } -int device_remove(struct device *dev) +int device_remove(struct udevice *dev) { struct driver *drv; int ret; @@ -327,7 +327,7 @@ err: return ret; } -void *dev_get_platdata(struct device *dev) +void *dev_get_platdata(struct udevice *dev) { if (!dev) { dm_warn("%s: null device", __func__); @@ -337,7 +337,7 @@ void *dev_get_platdata(struct device *dev) return dev->platdata; } -void *dev_get_priv(struct device *dev) +void *dev_get_priv(struct udevice *dev) { if (!dev) { dm_warn("%s: null device", __func__); diff --git a/drivers/core/lists.c b/drivers/core/lists.c index 4f2c12631d4..205b140ef3d 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -60,13 +60,13 @@ struct uclass_driver *lists_uclass_lookup(enum uclass_id id) return NULL; } -int lists_bind_drivers(struct device *parent) +int lists_bind_drivers(struct udevice *parent) { struct driver_info *info = ll_entry_start(struct driver_info, driver_info); const int n_ents = ll_entry_count(struct driver_info, driver_info); struct driver_info *entry; - struct device *dev; + struct udevice *dev; int result = 0; int ret; @@ -116,12 +116,12 @@ static int driver_check_compatible(const void *blob, int offset, return -ENOENT; } -int lists_bind_fdt(struct device *parent, const void *blob, int offset) +int lists_bind_fdt(struct udevice *parent, const void *blob, int offset) { struct driver *driver = ll_entry_start(struct driver, driver); const int n_ents = ll_entry_count(struct driver, driver); struct driver *entry; - struct device *dev; + struct udevice *dev; const char *name; int result = 0; int ret; diff --git a/drivers/core/root.c b/drivers/core/root.c index 407bc0d0464..4977875c7f9 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -24,7 +24,7 @@ static const struct driver_info root_info = { .name = "root_driver", }; -struct device *dm_root(void) +struct udevice *dm_root(void) { if (!gd->dm_root) { dm_warn("Virtual root driver does not exist!\n"); diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 4df5a8bd399..f6867e4a232 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -101,7 +101,7 @@ fail_mem: int uclass_destroy(struct uclass *uc) { struct uclass_driver *uc_drv; - struct device *dev, *tmp; + struct udevice *dev, *tmp; int ret; list_for_each_entry_safe(dev, tmp, &uc->dev_head, uclass_node) { @@ -137,10 +137,10 @@ int uclass_get(enum uclass_id id, struct uclass **ucp) return 0; } -int uclass_find_device(enum uclass_id id, int index, struct device **devp) +int uclass_find_device(enum uclass_id id, int index, struct udevice **devp) { struct uclass *uc; - struct device *dev; + struct udevice *dev; int ret; *devp = NULL; @@ -158,9 +158,9 @@ int uclass_find_device(enum uclass_id id, int index, struct device **devp) return -ENODEV; } -int uclass_get_device(enum uclass_id id, int index, struct device **devp) +int uclass_get_device(enum uclass_id id, int index, struct udevice **devp) { - struct device *dev; + struct udevice *dev; int ret; *devp = NULL; @@ -177,10 +177,10 @@ int uclass_get_device(enum uclass_id id, int index, struct device **devp) return 0; } -int uclass_first_device(enum uclass_id id, struct device **devp) +int uclass_first_device(enum uclass_id id, struct udevice **devp) { struct uclass *uc; - struct device *dev; + struct udevice *dev; int ret; *devp = NULL; @@ -190,7 +190,7 @@ int uclass_first_device(enum uclass_id id, struct device **devp) if (list_empty(&uc->dev_head)) return 0; - dev = list_first_entry(&uc->dev_head, struct device, uclass_node); + dev = list_first_entry(&uc->dev_head, struct udevice, uclass_node); ret = device_probe(dev); if (ret) return ret; @@ -199,16 +199,17 @@ int uclass_first_device(enum uclass_id id, struct device **devp) return 0; } -int uclass_next_device(struct device **devp) +int uclass_next_device(struct udevice **devp) { - struct device *dev = *devp; + struct udevice *dev = *devp; int ret; *devp = NULL; if (list_is_last(&dev->uclass_node, &dev->uclass->dev_head)) return 0; - dev = list_entry(dev->uclass_node.next, struct device, uclass_node); + dev = list_entry(dev->uclass_node.next, struct udevice, + uclass_node); ret = device_probe(dev); if (ret) return ret; @@ -217,7 +218,7 @@ int uclass_next_device(struct device **devp) return 0; } -int uclass_bind_device(struct device *dev) +int uclass_bind_device(struct udevice *dev) { struct uclass *uc; int ret; @@ -237,7 +238,7 @@ int uclass_bind_device(struct device *dev) return 0; } -int uclass_unbind_device(struct device *dev) +int uclass_unbind_device(struct udevice *dev) { struct uclass *uc; int ret; @@ -253,7 +254,7 @@ int uclass_unbind_device(struct device *dev) return 0; } -int uclass_post_probe_device(struct device *dev) +int uclass_post_probe_device(struct udevice *dev) { struct uclass_driver *uc_drv = dev->uclass->uc_drv; @@ -263,7 +264,7 @@ int uclass_post_probe_device(struct device *dev) return 0; } -int uclass_pre_remove_device(struct device *dev) +int uclass_pre_remove_device(struct udevice *dev) { struct uclass_driver *uc_drv; struct uclass *uc; diff --git a/drivers/demo/demo-shape.c b/drivers/demo/demo-shape.c index 2f0eb96bb62..a68cc1092cf 100644 --- a/drivers/demo/demo-shape.c +++ b/drivers/demo/demo-shape.c @@ -23,7 +23,7 @@ struct shape_data { }; /* Crazy little function to draw shapes on the console */ -static int shape_hello(struct device *dev, int ch) +static int shape_hello(struct udevice *dev, int ch) { const struct dm_demo_pdata *pdata = dev_get_platdata(dev); struct shape_data *data = dev_get_priv(dev); @@ -81,7 +81,7 @@ static int shape_hello(struct device *dev, int ch) return 0; } -static int shape_status(struct device *dev, int *status) +static int shape_status(struct udevice *dev, int *status) { struct shape_data *data = dev_get_priv(dev); @@ -94,7 +94,7 @@ static const struct demo_ops shape_ops = { .status = shape_status, }; -static int shape_ofdata_to_platdata(struct device *dev) +static int shape_ofdata_to_platdata(struct udevice *dev) { struct dm_demo_pdata *pdata = dev_get_platdata(dev); int ret; diff --git a/drivers/demo/demo-simple.c b/drivers/demo/demo-simple.c index 6ba8131728d..11def86032c 100644 --- a/drivers/demo/demo-simple.c +++ b/drivers/demo/demo-simple.c @@ -12,7 +12,7 @@ #include #include -static int simple_hello(struct device *dev, int ch) +static int simple_hello(struct udevice *dev, int ch) { const struct dm_demo_pdata *pdata = dev_get_platdata(dev); @@ -26,7 +26,7 @@ static const struct demo_ops simple_ops = { .hello = simple_hello, }; -static int demo_shape_ofdata_to_platdata(struct device *dev) +static int demo_shape_ofdata_to_platdata(struct udevice *dev) { /* Parse the data that is common with all demo devices */ return demo_parse_dt(dev); diff --git a/drivers/demo/demo-uclass.c b/drivers/demo/demo-uclass.c index 48588be9074..636fd8831f5 100644 --- a/drivers/demo/demo-uclass.c +++ b/drivers/demo/demo-uclass.c @@ -22,7 +22,7 @@ UCLASS_DRIVER(demo) = { .id = UCLASS_DEMO, }; -int demo_hello(struct device *dev, int ch) +int demo_hello(struct udevice *dev, int ch) { const struct demo_ops *ops = device_get_ops(dev); @@ -32,7 +32,7 @@ int demo_hello(struct device *dev, int ch) return ops->hello(dev, ch); } -int demo_status(struct device *dev, int *status) +int demo_status(struct udevice *dev, int *status) { const struct demo_ops *ops = device_get_ops(dev); @@ -42,7 +42,7 @@ int demo_status(struct device *dev, int *status) return ops->status(dev, status); } -int demo_parse_dt(struct device *dev) +int demo_parse_dt(struct udevice *dev) { struct dm_demo_pdata *pdata = dev_get_platdata(dev); int dn = dev->of_offset; diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 56bfd114665..fa2c2fb7c47 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -17,11 +17,11 @@ * or GPIO blocks registered with the GPIO controller. Returns * entry on success, NULL on error. */ -static int gpio_to_device(unsigned int gpio, struct device **devp, +static int gpio_to_device(unsigned int gpio, struct udevice **devp, unsigned int *offset) { struct gpio_dev_priv *uc_priv; - struct device *dev; + struct udevice *dev; int ret; for (ret = uclass_first_device(UCLASS_GPIO, &dev); @@ -40,11 +40,11 @@ static int gpio_to_device(unsigned int gpio, struct device **devp, return ret ? ret : -EINVAL; } -int gpio_lookup_name(const char *name, struct device **devp, +int gpio_lookup_name(const char *name, struct udevice **devp, unsigned int *offsetp, unsigned int *gpiop) { struct gpio_dev_priv *uc_priv; - struct device *dev; + struct udevice *dev; int ret; if (devp) @@ -86,7 +86,7 @@ int gpio_lookup_name(const char *name, struct device **devp, int gpio_request(unsigned gpio, const char *label) { unsigned int offset; - struct device *dev; + struct udevice *dev; int ret; ret = gpio_to_device(gpio, &dev, &offset); @@ -110,7 +110,7 @@ int gpio_request(unsigned gpio, const char *label) int gpio_free(unsigned gpio) { unsigned int offset; - struct device *dev; + struct udevice *dev; int ret; ret = gpio_to_device(gpio, &dev, &offset); @@ -133,7 +133,7 @@ int gpio_free(unsigned gpio) int gpio_direction_input(unsigned gpio) { unsigned int offset; - struct device *dev; + struct udevice *dev; int ret; ret = gpio_to_device(gpio, &dev, &offset); @@ -155,7 +155,7 @@ int gpio_direction_input(unsigned gpio) int gpio_direction_output(unsigned gpio, int value) { unsigned int offset; - struct device *dev; + struct udevice *dev; int ret; ret = gpio_to_device(gpio, &dev, &offset); @@ -177,7 +177,7 @@ int gpio_direction_output(unsigned gpio, int value) int gpio_get_value(unsigned gpio) { unsigned int offset; - struct device *dev; + struct udevice *dev; int ret; ret = gpio_to_device(gpio, &dev, &offset); @@ -199,7 +199,7 @@ int gpio_get_value(unsigned gpio) int gpio_set_value(unsigned gpio, int value) { unsigned int offset; - struct device *dev; + struct udevice *dev; int ret; ret = gpio_to_device(gpio, &dev, &offset); @@ -209,7 +209,7 @@ int gpio_set_value(unsigned gpio, int value) return gpio_get_ops(dev)->set_value(dev, offset, value); } -const char *gpio_get_bank_info(struct device *dev, int *bit_count) +const char *gpio_get_bank_info(struct udevice *dev, int *bit_count) { struct gpio_dev_priv *priv; @@ -225,7 +225,7 @@ const char *gpio_get_bank_info(struct device *dev, int *bit_count) static int gpio_renumber(void) { struct gpio_dev_priv *uc_priv; - struct device *dev; + struct udevice *dev; struct uclass *uc; unsigned base; int ret; @@ -247,12 +247,12 @@ static int gpio_renumber(void) return 0; } -static int gpio_post_probe(struct device *dev) +static int gpio_post_probe(struct udevice *dev) { return gpio_renumber(); } -static int gpio_pre_remove(struct device *dev) +static int gpio_pre_remove(struct udevice *dev) { return gpio_renumber(); } diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index 22b6a5f7941..09cebe2286f 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -22,7 +22,7 @@ struct gpio_state { }; /* Access routines for GPIO state */ -static u8 *get_gpio_flags(struct device *dev, unsigned offset) +static u8 *get_gpio_flags(struct udevice *dev, unsigned offset) { struct gpio_dev_priv *uc_priv = dev->uclass_priv; struct gpio_state *state = dev_get_priv(dev); @@ -36,12 +36,12 @@ static u8 *get_gpio_flags(struct device *dev, unsigned offset) return &state[offset].flags; } -static int get_gpio_flag(struct device *dev, unsigned offset, int flag) +static int get_gpio_flag(struct udevice *dev, unsigned offset, int flag) { return (*get_gpio_flags(dev, offset) & flag) != 0; } -static int set_gpio_flag(struct device *dev, unsigned offset, int flag, +static int set_gpio_flag(struct udevice *dev, unsigned offset, int flag, int value) { u8 *gpio = get_gpio_flags(dev, offset); @@ -54,7 +54,7 @@ static int set_gpio_flag(struct device *dev, unsigned offset, int flag, return 0; } -static int check_reserved(struct device *dev, unsigned offset, +static int check_reserved(struct udevice *dev, unsigned offset, const char *func) { if (!get_gpio_flag(dev, offset, GPIOF_RESERVED)) { @@ -70,24 +70,24 @@ static int check_reserved(struct device *dev, unsigned offset, * Back-channel sandbox-internal-only access to GPIO state */ -int sandbox_gpio_get_value(struct device *dev, unsigned offset) +int sandbox_gpio_get_value(struct udevice *dev, unsigned offset) { if (get_gpio_flag(dev, offset, GPIOF_OUTPUT)) debug("sandbox_gpio: get_value on output gpio %u\n", offset); return get_gpio_flag(dev, offset, GPIOF_HIGH); } -int sandbox_gpio_set_value(struct device *dev, unsigned offset, int value) +int sandbox_gpio_set_value(struct udevice *dev, unsigned offset, int value) { return set_gpio_flag(dev, offset, GPIOF_HIGH, value); } -int sandbox_gpio_get_direction(struct device *dev, unsigned offset) +int sandbox_gpio_get_direction(struct udevice *dev, unsigned offset) { return get_gpio_flag(dev, offset, GPIOF_OUTPUT); } -int sandbox_gpio_set_direction(struct device *dev, unsigned offset, int output) +int sandbox_gpio_set_direction(struct udevice *dev, unsigned offset, int output) { return set_gpio_flag(dev, offset, GPIOF_OUTPUT, output); } @@ -97,7 +97,7 @@ int sandbox_gpio_set_direction(struct device *dev, unsigned offset, int output) */ /* set GPIO port 'offset' as an input */ -static int sb_gpio_direction_input(struct device *dev, unsigned offset) +static int sb_gpio_direction_input(struct udevice *dev, unsigned offset) { debug("%s: offset:%u\n", __func__, offset); @@ -108,7 +108,7 @@ static int sb_gpio_direction_input(struct device *dev, unsigned offset) } /* set GPIO port 'offset' as an output, with polarity 'value' */ -static int sb_gpio_direction_output(struct device *dev, unsigned offset, +static int sb_gpio_direction_output(struct udevice *dev, unsigned offset, int value) { debug("%s: offset:%u, value = %d\n", __func__, offset, value); @@ -121,7 +121,7 @@ static int sb_gpio_direction_output(struct device *dev, unsigned offset, } /* read GPIO IN value of port 'offset' */ -static int sb_gpio_get_value(struct device *dev, unsigned offset) +static int sb_gpio_get_value(struct udevice *dev, unsigned offset) { debug("%s: offset:%u\n", __func__, offset); @@ -132,7 +132,7 @@ static int sb_gpio_get_value(struct device *dev, unsigned offset) } /* write GPIO OUT value to port 'offset' */ -static int sb_gpio_set_value(struct device *dev, unsigned offset, int value) +static int sb_gpio_set_value(struct udevice *dev, unsigned offset, int value) { debug("%s: offset:%u, value = %d\n", __func__, offset, value); @@ -148,7 +148,7 @@ static int sb_gpio_set_value(struct device *dev, unsigned offset, int value) return sandbox_gpio_set_value(dev, offset, value); } -static int sb_gpio_request(struct device *dev, unsigned offset, +static int sb_gpio_request(struct udevice *dev, unsigned offset, const char *label) { struct gpio_dev_priv *uc_priv = dev->uclass_priv; @@ -171,7 +171,7 @@ static int sb_gpio_request(struct device *dev, unsigned offset, return set_gpio_flag(dev, offset, GPIOF_RESERVED, 1); } -static int sb_gpio_free(struct device *dev, unsigned offset) +static int sb_gpio_free(struct udevice *dev, unsigned offset) { struct gpio_state *state = dev_get_priv(dev); @@ -184,7 +184,7 @@ static int sb_gpio_free(struct device *dev, unsigned offset) return set_gpio_flag(dev, offset, GPIOF_RESERVED, 0); } -static int sb_gpio_get_state(struct device *dev, unsigned int offset, +static int sb_gpio_get_state(struct udevice *dev, unsigned int offset, char *buf, int bufsize) { struct gpio_dev_priv *uc_priv = dev->uclass_priv; @@ -213,7 +213,7 @@ static const struct dm_gpio_ops gpio_sandbox_ops = { .get_state = sb_gpio_get_state, }; -static int sandbox_gpio_ofdata_to_platdata(struct device *dev) +static int sandbox_gpio_ofdata_to_platdata(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev->uclass_priv; @@ -225,7 +225,7 @@ static int sandbox_gpio_ofdata_to_platdata(struct device *dev) return 0; } -static int gpio_sandbox_probe(struct device *dev) +static int gpio_sandbox_probe(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev->uclass_priv; diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index e98b661e358..2850ed8a69f 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -65,7 +65,7 @@ typedef struct global_data { struct global_data *new_gd; /* relocated global data */ #ifdef CONFIG_DM - struct device *dm_root; /* Root instance for Driver Model */ + struct udevice *dm_root;/* Root instance for Driver Model */ struct list_head uclass_root; /* Head of core tree */ #endif diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index e325df40d93..a6e52a0de63 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -86,7 +86,7 @@ enum { GPIOF_UNKNOWN, }; -struct device; +struct udevice; /** * struct struct dm_gpio_ops - Driver model GPIO operations @@ -116,15 +116,15 @@ struct device; * all devices. Be careful not to confuse offset with gpio in the parameters. */ struct dm_gpio_ops { - int (*request)(struct device *dev, unsigned offset, const char *label); - int (*free)(struct device *dev, unsigned offset); - int (*direction_input)(struct device *dev, unsigned offset); - int (*direction_output)(struct device *dev, unsigned offset, + int (*request)(struct udevice *dev, unsigned offset, const char *label); + int (*free)(struct udevice *dev, unsigned offset); + int (*direction_input)(struct udevice *dev, unsigned offset); + int (*direction_output)(struct udevice *dev, unsigned offset, int value); - int (*get_value)(struct device *dev, unsigned offset); - int (*set_value)(struct device *dev, unsigned offset, int value); - int (*get_function)(struct device *dev, unsigned offset); - int (*get_state)(struct device *dev, unsigned offset, char *state, + int (*get_value)(struct udevice *dev, unsigned offset); + int (*set_value)(struct udevice *dev, unsigned offset, int value); + int (*get_function)(struct udevice *dev, unsigned offset); + int (*get_state)(struct udevice *dev, unsigned offset, char *state, int maxlen); }; @@ -166,7 +166,7 @@ struct gpio_dev_priv { * @offset_count: Returns number of GPIOs within this bank * @return bank name of this device */ -const char *gpio_get_bank_info(struct device *dev, int *offset_count); +const char *gpio_get_bank_info(struct udevice *dev, int *offset_count); /** * gpio_lookup_name - Look up a GPIO name and return its details @@ -179,7 +179,7 @@ const char *gpio_get_bank_info(struct device *dev, int *offset_count); * @offsetp: Returns the offset number within this device * @gpiop: Returns the absolute GPIO number, numbered from 0 */ -int gpio_lookup_name(const char *name, struct device **devp, +int gpio_lookup_name(const char *name, struct udevice **devp, unsigned int *offsetp, unsigned int *gpiop); #endif /* _ASM_GENERIC_GPIO_H_ */ diff --git a/include/dm-demo.h b/include/dm-demo.h index 6e38d3c5b3a..a24fec6658e 100644 --- a/include/dm-demo.h +++ b/include/dm-demo.h @@ -23,14 +23,14 @@ struct dm_demo_pdata { }; struct demo_ops { - int (*hello)(struct device *dev, int ch); - int (*status)(struct device *dev, int *status); + int (*hello)(struct udevice *dev, int ch); + int (*status)(struct udevice *dev, int *status); }; -int demo_hello(struct device *dev, int ch); -int demo_status(struct device *dev, int *status); +int demo_hello(struct udevice *dev, int ch); +int demo_status(struct udevice *dev, int *status); int demo_list(void); -int demo_parse_dt(struct device *dev); +int demo_parse_dt(struct udevice *dev); #endif diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index c026e8e49c7..ea3df36632d 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -11,7 +11,7 @@ #ifndef _DM_DEVICE_INTERNAL_H #define _DM_DEVICE_INTERNAL_H -struct device; +struct udevice; /** * device_bind() - Create a device and bind it to a driver @@ -34,9 +34,9 @@ struct device; * @devp: Returns a pointer to the bound device * @return 0 if OK, -ve on error */ -int device_bind(struct device *parent, struct driver *drv, +int device_bind(struct udevice *parent, struct driver *drv, const char *name, void *platdata, int of_offset, - struct device **devp); + struct udevice **devp); /** * device_bind_by_name: Create a device and bind it to a driver @@ -49,8 +49,8 @@ int device_bind(struct device *parent, struct driver *drv, * @devp: Returns a pointer to the bound device * @return 0 if OK, -ve on error */ -int device_bind_by_name(struct device *parent, const struct driver_info *info, - struct device **devp); +int device_bind_by_name(struct udevice *parent, const struct driver_info *info, + struct udevice **devp); /** * device_probe() - Probe a device, activating it @@ -61,7 +61,7 @@ int device_bind_by_name(struct device *parent, const struct driver_info *info, * @dev: Pointer to device to probe * @return 0 if OK, -ve on error */ -int device_probe(struct device *dev); +int device_probe(struct udevice *dev); /** * device_remove() - Remove a device, de-activating it @@ -72,7 +72,7 @@ int device_probe(struct device *dev); * @dev: Pointer to device to remove * @return 0 if OK, -ve on error (an error here is normally a very bad thing) */ -int device_remove(struct device *dev); +int device_remove(struct udevice *dev); /** * device_unbind() - Unbind a device, destroying it @@ -82,6 +82,6 @@ int device_remove(struct device *dev); * @dev: Pointer to device to unbind * @return 0 if OK, -ve on error */ -int device_unbind(struct device *dev); +int device_unbind(struct udevice *dev); #endif diff --git a/include/dm/device.h b/include/dm/device.h index 4cd38ed2d03..ec049824e8c 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -24,7 +24,7 @@ struct driver_info; #define DM_FLAG_ALLOC_PDATA (2 << 0) /** - * struct device - An instance of a driver + * struct udevice - An instance of a driver * * This holds information about a device, which is a driver bound to a * particular port or peripheral (essentially a driver instance). @@ -53,12 +53,12 @@ struct driver_info; * @sibling_node: Next device in list of all devices * @flags: Flags for this device DM_FLAG_... */ -struct device { +struct udevice { struct driver *driver; const char *name; void *platdata; int of_offset; - struct device *parent; + struct udevice *parent; void *priv; struct uclass *uclass; void *uclass_priv; @@ -122,11 +122,11 @@ struct driver { char *name; enum uclass_id id; const struct device_id *of_match; - int (*bind)(struct device *dev); - int (*probe)(struct device *dev); - int (*remove)(struct device *dev); - int (*unbind)(struct device *dev); - int (*ofdata_to_platdata)(struct device *dev); + int (*bind)(struct udevice *dev); + int (*probe)(struct udevice *dev); + int (*remove)(struct udevice *dev); + int (*unbind)(struct udevice *dev); + int (*ofdata_to_platdata)(struct udevice *dev); int priv_auto_alloc_size; int platdata_auto_alloc_size; const void *ops; /* driver-specific operations */ @@ -144,7 +144,7 @@ struct driver { * @dev Device to check * @return platform data, or NULL if none */ -void *dev_get_platdata(struct device *dev); +void *dev_get_platdata(struct udevice *dev); /** * dev_get_priv() - Get the private data for a device @@ -154,6 +154,6 @@ void *dev_get_platdata(struct device *dev); * @dev Device to check * @return private data, or NULL if none */ -void *dev_get_priv(struct device *dev); +void *dev_get_priv(struct udevice *dev); #endif diff --git a/include/dm/lists.h b/include/dm/lists.h index 0d09f9a14f5..7feba4b00ff 100644 --- a/include/dm/lists.h +++ b/include/dm/lists.h @@ -32,8 +32,8 @@ struct driver *lists_driver_lookup_name(const char *name); */ struct uclass_driver *lists_uclass_lookup(enum uclass_id id); -int lists_bind_drivers(struct device *parent); +int lists_bind_drivers(struct udevice *parent); -int lists_bind_fdt(struct device *parent, const void *blob, int offset); +int lists_bind_fdt(struct udevice *parent, const void *blob, int offset); #endif diff --git a/include/dm/root.h b/include/dm/root.h index 0ebccda3557..3018bc8627a 100644 --- a/include/dm/root.h +++ b/include/dm/root.h @@ -10,7 +10,7 @@ #ifndef _DM_ROOT_H_ #define _DM_ROOT_H_ -struct device; +struct udevice; /** * dm_root() - Return pointer to the top of the driver tree @@ -19,7 +19,7 @@ struct device; * * @return pointer to root device, or NULL if not inited yet */ -struct device *dm_root(void); +struct udevice *dm_root(void); /** * dm_scan_platdata() - Scan all platform data and bind drivers diff --git a/include/dm/test.h b/include/dm/test.h index eeaa2eb2f46..409f1a3667f 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -30,7 +30,7 @@ struct dm_test_pdata { * @return 0 if OK, -ve on error */ struct test_ops { - int (*ping)(struct device *dev, int pingval, int *pingret); + int (*ping)(struct udevice *dev, int pingval, int *pingret); }; /* Operations that our test driver supports */ @@ -102,8 +102,8 @@ extern struct dm_test_state global_test_state; * @skip_post_probe: Skip uclass post-probe processing */ struct dm_test_state { - struct device *root; - struct device *testdev; + struct udevice *root; + struct udevice *testdev; int fail_count; int force_fail_alloc; int skip_post_probe; @@ -138,8 +138,8 @@ struct dm_test { } /* Declare ping methods for the drivers */ -int test_ping(struct device *dev, int pingval, int *pingret); -int testfdt_ping(struct device *dev, int pingval, int *pingret); +int test_ping(struct udevice *dev, int pingval, int *pingret); +int testfdt_ping(struct udevice *dev, int pingval, int *pingret); /** * dm_check_operations() - Check that we can perform ping operations @@ -152,7 +152,7 @@ int testfdt_ping(struct device *dev, int pingval, int *pingret); * @priv: Pointer to private test information * @return 0 if OK, -ve on error */ -int dm_check_operations(struct dm_test_state *dms, struct device *dev, +int dm_check_operations(struct dm_test_state *dms, struct udevice *dev, uint32_t base, struct dm_test_priv *priv); /** diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h index cc65d5259f1..1434db3eb4c 100644 --- a/include/dm/uclass-internal.h +++ b/include/dm/uclass-internal.h @@ -21,7 +21,7 @@ * @return the uclass pointer of a child at the given index or * return NULL on error. */ -int uclass_find_device(enum uclass_id id, int index, struct device **devp); +int uclass_find_device(enum uclass_id id, int index, struct udevice **devp); /** * uclass_bind_device() - Associate device with a uclass @@ -31,7 +31,7 @@ int uclass_find_device(enum uclass_id id, int index, struct device **devp); * @dev: Pointer to the device * #return 0 on success, -ve on error */ -int uclass_bind_device(struct device *dev); +int uclass_bind_device(struct udevice *dev); /** * uclass_unbind_device() - Deassociate device with a uclass @@ -41,7 +41,7 @@ int uclass_bind_device(struct device *dev); * @dev: Pointer to the device * #return 0 on success, -ve on error */ -int uclass_unbind_device(struct device *dev); +int uclass_unbind_device(struct udevice *dev); /** * uclass_post_probe_device() - Deal with a device that has just been probed @@ -52,7 +52,7 @@ int uclass_unbind_device(struct device *dev); * @dev: Pointer to the device * #return 0 on success, -ve on error */ -int uclass_post_probe_device(struct device *dev); +int uclass_post_probe_device(struct udevice *dev); /** * uclass_pre_remove_device() - Handle a device which is about to be removed @@ -62,7 +62,7 @@ int uclass_post_probe_device(struct device *dev); * @dev: Pointer to the device * #return 0 on success, -ve on error */ -int uclass_pre_remove_device(struct device *dev); +int uclass_pre_remove_device(struct udevice *dev); /** * uclass_find() - Find uclass by its id diff --git a/include/dm/uclass.h b/include/dm/uclass.h index cd23cfed163..931d9c0b9a1 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -37,7 +37,7 @@ struct uclass { struct list_head sibling_node; }; -struct device; +struct udevice; /** * struct uclass_driver - Driver for the uclass @@ -65,10 +65,10 @@ struct device; struct uclass_driver { const char *name; enum uclass_id id; - int (*post_bind)(struct device *dev); - int (*pre_unbind)(struct device *dev); - int (*post_probe)(struct device *dev); - int (*pre_remove)(struct device *dev); + int (*post_bind)(struct udevice *dev); + int (*pre_unbind)(struct udevice *dev); + int (*post_probe)(struct udevice *dev); + int (*pre_remove)(struct udevice *dev); int (*init)(struct uclass *class); int (*destroy)(struct uclass *class); int priv_auto_alloc_size; @@ -101,7 +101,7 @@ int uclass_get(enum uclass_id key, struct uclass **ucp); * @ucp: Returns pointer to uclass (there is only one per for each ID) * @return 0 if OK, -ve on error */ -int uclass_get_device(enum uclass_id id, int index, struct device **ucp); +int uclass_get_device(enum uclass_id id, int index, struct udevice **ucp); /** * uclass_first_device() - Get the first device in a uclass @@ -110,7 +110,7 @@ int uclass_get_device(enum uclass_id id, int index, struct device **ucp); * @devp: Returns pointer to the first device in that uclass, or NULL if none * @return 0 if OK (found or not found), -1 on error */ -int uclass_first_device(enum uclass_id id, struct device **devp); +int uclass_first_device(enum uclass_id id, struct udevice **devp); /** * uclass_next_device() - Get the next device in a uclass @@ -119,7 +119,7 @@ int uclass_first_device(enum uclass_id id, struct device **devp); * to the next device in the same uclass, or NULL if none * @return 0 if OK (found or not found), -1 on error */ -int uclass_next_device(struct device **devp); +int uclass_next_device(struct udevice **devp); /** * uclass_foreach_dev() - Helper function to iteration through devices @@ -127,7 +127,7 @@ int uclass_next_device(struct device **devp); * This creates a for() loop which works through the available devices in * a uclass in order from start to end. * - * @pos: struct device * to hold the current device. Set to NULL when there + * @pos: struct udevice * to hold the current device. Set to NULL when there * are no more devices. * uc: uclass to scan */ diff --git a/test/dm/cmd_dm.c b/test/dm/cmd_dm.c index a03fe20f0d3..083f15c31d1 100644 --- a/test/dm/cmd_dm.c +++ b/test/dm/cmd_dm.c @@ -16,12 +16,12 @@ #include #include -static int display_succ(struct device *in, char *buf) +static int display_succ(struct udevice *in, char *buf) { int len; int ip = 0; char local[16]; - struct device *pos, *n, *prev = NULL; + struct udevice *pos, *n, *prev = NULL; printf("%s- %s @ %08x", buf, in->name, map_to_sysmem(in)); if (in->flags & DM_FLAG_ACTIVATED) @@ -49,7 +49,7 @@ static int display_succ(struct device *in, char *buf) return 0; } -static int dm_dump(struct device *dev) +static int dm_dump(struct udevice *dev) { if (!dev) return -EINVAL; @@ -59,7 +59,7 @@ static int dm_dump(struct device *dev) static int do_dm_dump_all(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct device *root; + struct udevice *root; root = dm_root(); printf("ROOT %08x\n", map_to_sysmem(root)); @@ -74,7 +74,7 @@ static int do_dm_dump_uclass(cmd_tbl_t *cmdtp, int flag, int argc, int id; for (id = 0; id < UCLASS_COUNT; id++) { - struct device *dev; + struct udevice *dev; ret = uclass_get(id, &uc); if (ret) diff --git a/test/dm/core.c b/test/dm/core.c index 14a57c3106d..be3646b968b 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -60,7 +60,7 @@ static struct driver_info driver_info_manual = { /* Test that binding with platdata occurs correctly */ static int dm_test_autobind(struct dm_test_state *dms) { - struct device *dev; + struct udevice *dev; /* * We should have a single class (UCLASS_ROOT) and a single root @@ -95,7 +95,7 @@ DM_TEST(dm_test_autobind, 0); static int dm_test_autoprobe(struct dm_test_state *dms) { int expected_base_add; - struct device *dev; + struct udevice *dev; struct uclass *uc; int i; @@ -157,7 +157,7 @@ DM_TEST(dm_test_autoprobe, DM_TESTF_SCAN_PDATA); static int dm_test_platdata(struct dm_test_state *dms) { const struct dm_test_pdata *pdata; - struct device *dev; + struct udevice *dev; int i; for (i = 0; i < 3; i++) { @@ -175,7 +175,7 @@ DM_TEST(dm_test_platdata, DM_TESTF_SCAN_PDATA); static int dm_test_lifecycle(struct dm_test_state *dms) { int op_count[DM_TEST_OP_COUNT]; - struct device *dev, *test_dev; + struct udevice *dev, *test_dev; int pingret; int ret; @@ -229,7 +229,7 @@ DM_TEST(dm_test_lifecycle, DM_TESTF_SCAN_PDATA | DM_TESTF_PROBE_TEST); /* Test that we can bind/unbind and the lists update correctly */ static int dm_test_ordering(struct dm_test_state *dms) { - struct device *dev, *dev_penultimate, *dev_last, *test_dev; + struct udevice *dev, *dev_penultimate, *dev_last, *test_dev; int pingret; ut_assertok(device_bind_by_name(dms->root, &driver_info_manual, @@ -281,7 +281,7 @@ static int dm_test_ordering(struct dm_test_state *dms) DM_TEST(dm_test_ordering, DM_TESTF_SCAN_PDATA); /* Check that we can perform operations on a device (do a ping) */ -int dm_check_operations(struct dm_test_state *dms, struct device *dev, +int dm_check_operations(struct dm_test_state *dms, struct udevice *dev, uint32_t base, struct dm_test_priv *priv) { int expected; @@ -311,7 +311,7 @@ int dm_check_operations(struct dm_test_state *dms, struct device *dev, /* Check that we can perform operations on devices */ static int dm_test_operations(struct dm_test_state *dms) { - struct device *dev; + struct udevice *dev; int i; /* @@ -341,7 +341,7 @@ DM_TEST(dm_test_operations, DM_TESTF_SCAN_PDATA); /* Remove all drivers and check that things work */ static int dm_test_remove(struct dm_test_state *dms) { - struct device *dev; + struct udevice *dev; int i; for (i = 0; i < 3; i++) { @@ -367,7 +367,7 @@ static int dm_test_leak(struct dm_test_state *dms) for (i = 0; i < 2; i++) { struct mallinfo start, end; - struct device *dev; + struct udevice *dev; int ret; int id; @@ -435,10 +435,10 @@ DM_TEST(dm_test_uclass, 0); * this array. * @return 0 if OK, -ve on error */ -static int create_children(struct dm_test_state *dms, struct device *parent, - int count, int key, struct device *child[]) +static int create_children(struct dm_test_state *dms, struct udevice *parent, + int count, int key, struct udevice *child[]) { - struct device *dev; + struct udevice *dev; int i; for (i = 0; i < count; i++) { @@ -460,10 +460,10 @@ static int create_children(struct dm_test_state *dms, struct device *parent, static int dm_test_children(struct dm_test_state *dms) { - struct device *top[NODE_COUNT]; - struct device *child[NODE_COUNT]; - struct device *grandchild[NODE_COUNT]; - struct device *dev; + struct udevice *top[NODE_COUNT]; + struct udevice *child[NODE_COUNT]; + struct udevice *grandchild[NODE_COUNT]; + struct udevice *dev; int total; int ret; int i; diff --git a/test/dm/gpio.c b/test/dm/gpio.c index bf632bca54e..2b2b0b51fa7 100644 --- a/test/dm/gpio.c +++ b/test/dm/gpio.c @@ -17,7 +17,7 @@ static int dm_test_gpio(struct dm_test_state *dms) { unsigned int offset, gpio; struct dm_gpio_ops *ops; - struct device *dev; + struct udevice *dev; const char *name; int offset_count; char buf[80]; diff --git a/test/dm/test-driver.c b/test/dm/test-driver.c index c4be8a12d71..0f1a37b36e5 100644 --- a/test/dm/test-driver.c +++ b/test/dm/test-driver.c @@ -18,7 +18,7 @@ int dm_testdrv_op_count[DM_TEST_OP_COUNT]; static struct dm_test_state *dms = &global_test_state; -static int testdrv_ping(struct device *dev, int pingval, int *pingret) +static int testdrv_ping(struct udevice *dev, int pingval, int *pingret) { const struct dm_test_pdata *pdata = dev_get_platdata(dev); struct dm_test_priv *priv = dev_get_priv(dev); @@ -33,7 +33,7 @@ static const struct test_ops test_ops = { .ping = testdrv_ping, }; -static int test_bind(struct device *dev) +static int test_bind(struct udevice *dev) { /* Private data should not be allocated */ ut_assert(!dev_get_priv(dev)); @@ -42,7 +42,7 @@ static int test_bind(struct device *dev) return 0; } -static int test_probe(struct device *dev) +static int test_probe(struct udevice *dev) { struct dm_test_priv *priv = dev_get_priv(dev); @@ -54,7 +54,7 @@ static int test_probe(struct device *dev) return 0; } -static int test_remove(struct device *dev) +static int test_remove(struct udevice *dev) { /* Private data should still be allocated */ ut_assert(dev_get_priv(dev)); @@ -63,7 +63,7 @@ static int test_remove(struct device *dev) return 0; } -static int test_unbind(struct device *dev) +static int test_unbind(struct udevice *dev) { /* Private data should not be allocated */ ut_assert(!dev->priv); @@ -94,7 +94,7 @@ U_BOOT_DRIVER(test2_drv) = { .priv_auto_alloc_size = sizeof(struct dm_test_priv), }; -static int test_manual_drv_ping(struct device *dev, int pingval, int *pingret) +static int test_manual_drv_ping(struct udevice *dev, int pingval, int *pingret) { *pingret = pingval + 2; @@ -105,14 +105,14 @@ static const struct test_ops test_manual_ops = { .ping = test_manual_drv_ping, }; -static int test_manual_bind(struct device *dev) +static int test_manual_bind(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_BIND]++; return 0; } -static int test_manual_probe(struct device *dev) +static int test_manual_probe(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_PROBE]++; if (!dms->force_fail_alloc) @@ -123,13 +123,13 @@ static int test_manual_probe(struct device *dev) return 0; } -static int test_manual_remove(struct device *dev) +static int test_manual_remove(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_REMOVE]++; return 0; } -static int test_manual_unbind(struct device *dev) +static int test_manual_unbind(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_UNBIND]++; return 0; diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index e1d982fd7d1..6eccf111279 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; -static int testfdt_drv_ping(struct device *dev, int pingval, int *pingret) +static int testfdt_drv_ping(struct udevice *dev, int pingval, int *pingret) { const struct dm_test_pdata *pdata = dev->platdata; struct dm_test_priv *priv = dev_get_priv(dev); @@ -33,7 +33,7 @@ static const struct test_ops test_ops = { .ping = testfdt_drv_ping, }; -static int testfdt_ofdata_to_platdata(struct device *dev) +static int testfdt_ofdata_to_platdata(struct udevice *dev) { struct dm_test_pdata *pdata = dev_get_platdata(dev); @@ -44,7 +44,7 @@ static int testfdt_ofdata_to_platdata(struct device *dev) return 0; } -static int testfdt_drv_probe(struct device *dev) +static int testfdt_drv_probe(struct udevice *dev) { struct dm_test_priv *priv = dev_get_priv(dev); @@ -75,7 +75,7 @@ U_BOOT_DRIVER(testfdt_drv) = { }; /* From here is the testfdt uclass code */ -int testfdt_ping(struct device *dev, int pingval, int *pingret) +int testfdt_ping(struct udevice *dev, int pingval, int *pingret) { const struct test_ops *ops = device_get_ops(dev); @@ -94,7 +94,7 @@ UCLASS_DRIVER(testfdt) = { static int dm_test_fdt(struct dm_test_state *dms) { const int num_drivers = 3; - struct device *dev; + struct udevice *dev; struct uclass *uc; int ret; int i; diff --git a/test/dm/test-main.c b/test/dm/test-main.c index 828ed46f8e7..fbdae688e09 100644 --- a/test/dm/test-main.c +++ b/test/dm/test-main.c @@ -32,7 +32,7 @@ static int dm_test_init(struct dm_test_state *dms) /* Ensure all the test devices are probed */ static int do_autoprobe(struct dm_test_state *dms) { - struct device *dev; + struct udevice *dev; int ret; /* Scanning the uclass is enough to probe all the devices */ diff --git a/test/dm/test-uclass.c b/test/dm/test-uclass.c index 8b564b89d98..017e097928c 100644 --- a/test/dm/test-uclass.c +++ b/test/dm/test-uclass.c @@ -18,7 +18,7 @@ static struct dm_test_state *dms = &global_test_state; -int test_ping(struct device *dev, int pingval, int *pingret) +int test_ping(struct udevice *dev, int pingval, int *pingret) { const struct test_ops *ops = device_get_ops(dev); @@ -28,24 +28,25 @@ int test_ping(struct device *dev, int pingval, int *pingret) return ops->ping(dev, pingval, pingret); } -static int test_post_bind(struct device *dev) +static int test_post_bind(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_POST_BIND]++; return 0; } -static int test_pre_unbind(struct device *dev) +static int test_pre_unbind(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]++; return 0; } -static int test_post_probe(struct device *dev) +static int test_post_probe(struct udevice *dev) { - struct device *prev = list_entry(dev->uclass_node.prev, struct device, - uclass_node); + struct udevice *prev = list_entry(dev->uclass_node.prev, + struct udevice, uclass_node); + struct dm_test_uclass_perdev_priv *priv = dev->uclass_priv; struct uclass *uc = dev->uclass; @@ -68,7 +69,7 @@ static int test_post_probe(struct device *dev) return 0; } -static int test_pre_remove(struct device *dev) +static int test_pre_remove(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]++; -- cgit v1.3.1 From 913702ca397755e06fcc126a063ebbf814ac869b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 20 May 2014 06:01:34 -0600 Subject: power: Rename CONFIG_PMIC_... to CONFIG_POWER_... Commit be3b51aa did this mostly, but several have been added since. Do the job again. Signed-off-by: Simon Glass Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/power/power_fsl.c | 6 +++--- include/configs/arndale.h | 4 ++-- include/configs/exynos5250-dt.h | 2 +- include/configs/mx25pdk.h | 2 +- include/configs/mx35pdk.h | 2 +- include/configs/mx53evk.h | 2 +- include/configs/mx53loco.h | 2 +- include/configs/woodburn_common.h | 2 +- 8 files changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index ac0b541d797..a64161b2430 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -11,9 +11,9 @@ #include #include -#if defined(CONFIG_PMIC_FSL_MC13892) +#if defined(CONFIG_POWER_FSL_MC13892) #define FSL_PMIC_I2C_LENGTH 3 -#elif defined(CONFIG_PMIC_FSL_MC34704) +#elif defined(CONFIG_POWER_FSL_MC34704) #define FSL_PMIC_I2C_LENGTH 1 #endif @@ -51,7 +51,7 @@ int pmic_init(unsigned char bus) p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR; p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH; #else -#error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C" +#error "You must select CONFIG_POWER_SPI or CONFIG_POWER_I2C" #endif return 0; diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 515facfd675..30ecd45584e 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -224,8 +224,8 @@ /* PMIC */ #define CONFIG_PMIC -#define CONFIG_PMIC_I2C -#define CONFIG_PMIC_MAX77686 +#define CONFIG_POWER_I2C +#define CONFIG_POWER_MAX77686 #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index b7ff47236b7..9d1d56a53b4 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -45,7 +45,7 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK /* PMIC */ -#define CONFIG_PMIC_MAX77686 +#define CONFIG_POWER_MAX77686 /* Sound */ #define CONFIG_CMD_SOUND diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index aff2419f852..d464ad964b9 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -107,7 +107,7 @@ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_FSL -#define CONFIG_PMIC_FSL_MC34704 +#define CONFIG_POWER_FSL_MC34704 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54 #define CONFIG_DOS_PARTITION diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 0a46f4c305f..ab481441b29 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -52,7 +52,7 @@ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_FSL -#define CONFIG_PMIC_FSL_MC13892 +#define CONFIG_POWER_FSL_MC13892 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 #define CONFIG_RTC_MC13XXX diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 3f0d80ac680..042cdd03235 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -45,7 +45,7 @@ #define CONFIG_POWER_I2C #define CONFIG_POWER_FSL #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8 -#define CONFIG_PMIC_FSL_MC13892 +#define CONFIG_POWER_FSL_MC13892 #define CONFIG_RTC_MC13XXX /* MMC Configs */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 5859f360e00..c7f54d4e8cb 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -80,7 +80,7 @@ #define CONFIG_POWER_I2C #define CONFIG_DIALOG_POWER #define CONFIG_POWER_FSL -#define CONFIG_PMIC_FSL_MC13892 +#define CONFIG_POWER_FSL_MC13892 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 695bc230c03..259205e8817 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -55,7 +55,7 @@ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_FSL -#define CONFIG_PMIC_FSL_MC13892 +#define CONFIG_POWER_FSL_MC13892 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 #define CONFIG_RTC_MC13XXX -- cgit v1.3.1 From 78a36c3ef390f7780840db3b42837e55e002829a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 20 May 2014 06:01:35 -0600 Subject: power: Add PMIC_ prefix to CHARGER_EN/DISABLE This enum should be common across all PMICs rather than having it independently defined with the same name in multiple places. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- drivers/power/battery/bat_trats.c | 4 ++-- drivers/power/battery/bat_trats2.c | 2 +- drivers/power/mfd/pmic_max77693.c | 2 +- drivers/power/pmic/pmic_max8997.c | 2 +- include/power/max77693_pmic.h | 2 -- include/power/max8997_pmic.h | 1 - include/power/pmic.h | 5 +++++ 7 files changed, 10 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/power/battery/bat_trats.c b/drivers/power/battery/bat_trats.c index 41b179fc540..bfde6921764 100644 --- a/drivers/power/battery/bat_trats.c +++ b/drivers/power/battery/bat_trats.c @@ -19,7 +19,7 @@ static int power_battery_charge(struct pmic *bat) struct battery *battery = p_bat->bat; int k; - if (bat->chrg->chrg_state(p_bat->chrg, CHARGER_ENABLE, 450)) + if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450)) return -1; for (k = 0; bat->chrg->chrg_bat_present(p_bat->chrg) && @@ -42,7 +42,7 @@ static int power_battery_charge(struct pmic *bat) } } exit: - bat->chrg->chrg_state(p_bat->chrg, CHARGER_DISABLE, 0); + bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_DISABLE, 0); return 0; } diff --git a/drivers/power/battery/bat_trats2.c b/drivers/power/battery/bat_trats2.c index 94015aa41a1..57221adf818 100644 --- a/drivers/power/battery/bat_trats2.c +++ b/drivers/power/battery/bat_trats2.c @@ -17,7 +17,7 @@ static int power_battery_charge(struct pmic *bat) { struct power_battery *p_bat = bat->pbat; - if (bat->chrg->chrg_state(p_bat->chrg, CHARGER_ENABLE, 450)) + if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450)) return -1; return 0; diff --git a/drivers/power/mfd/pmic_max77693.c b/drivers/power/mfd/pmic_max77693.c index 1a4416b54f4..6b28e28b3f8 100644 --- a/drivers/power/mfd/pmic_max77693.c +++ b/drivers/power/mfd/pmic_max77693.c @@ -22,7 +22,7 @@ static int max77693_charger_state(struct pmic *p, int state, int current) val = MAX77693_CHG_UNLOCK; pmic_reg_write(p, MAX77693_CHG_CNFG_06, val); - if (state == CHARGER_DISABLE) { + if (state == PMIC_CHARGER_DISABLE) { puts("Disable the charger.\n"); pmic_reg_read(p, MAX77693_CHG_CNFG_00, &val); val &= ~0x01; diff --git a/drivers/power/pmic/pmic_max8997.c b/drivers/power/pmic/pmic_max8997.c index ba016923275..a36a9a08bf4 100644 --- a/drivers/power/pmic/pmic_max8997.c +++ b/drivers/power/pmic/pmic_max8997.c @@ -35,7 +35,7 @@ static int pmic_charger_state(struct pmic *p, int state, int current) if (pmic_probe(p)) return -1; - if (state == CHARGER_DISABLE) { + if (state == PMIC_CHARGER_DISABLE) { puts("Disable the charger.\n"); pmic_reg_read(p, MAX8997_REG_MBCCTRL2, &val); val &= ~(MBCHOSTEN | VCHGR_FC); diff --git a/include/power/max77693_pmic.h b/include/power/max77693_pmic.h index 616d051f178..3d59e5916e5 100644 --- a/include/power/max77693_pmic.h +++ b/include/power/max77693_pmic.h @@ -10,8 +10,6 @@ #include -enum {CHARGER_ENABLE, CHARGER_DISABLE}; - #define CHARGER_MIN_CURRENT 200 #define CHARGER_MAX_CURRENT 2000 diff --git a/include/power/max8997_pmic.h b/include/power/max8997_pmic.h index 74c5d543871..728d60afa59 100644 --- a/include/power/max8997_pmic.h +++ b/include/power/max8997_pmic.h @@ -170,7 +170,6 @@ enum { #define SAFEOUT_3_30V 0x03 /* Charger */ -enum {CHARGER_ENABLE, CHARGER_DISABLE}; #define DETBAT (1 << 2) #define MBCICHFCSET (1 << 4) #define MBCHOSTEN (1 << 6) diff --git a/include/power/pmic.h b/include/power/pmic.h index 8f282dd2f29..a62e6c90a5e 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -17,6 +17,11 @@ enum { I2C_PMIC, I2C_NUM, }; enum { PMIC_READ, PMIC_WRITE, }; enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, }; +enum { + PMIC_CHARGER_DISABLE, + PMIC_CHARGER_ENABLE, +}; + struct p_i2c { unsigned char addr; unsigned char *buf; -- cgit v1.3.1 From ac1058fdb72b8a6dade7c81be31b22760099ee91 Mon Sep 17 00:00:00 2001 From: Tom Wai-Hong Tam Date: Tue, 20 May 2014 06:01:36 -0600 Subject: power: Add support for TPS65090 PMU chip. This adds driver support for the TPS65090 PMU. Support includes hooking into the pmic infrastructure so that the pmic commands can be used on the console. The TPS65090 supports the following functionality: - fet enable/disable/querying - getting and setting of charge state Even though it is connected to the pmic infrastructure it does not hook into the pmic charging charging infrastructure. The device tree binding is from Linux, but only a small subset of functionality is supported. Signed-off-by: Tom Wai-Hong Tam Signed-off-by: Hatim Ali Signed-off-by: Katie Roberts-Hoffman Signed-off-by: Rong Chang Signed-off-by: Sean Paul Signed-off-by: Vincent Palatin Signed-off-by: Aaron Durbin Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- doc/device-tree-bindings/power/tps65090.txt | 17 ++ doc/device-tree-bindings/regulator/tps65090.txt | 122 ++++++++++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65090.c | 310 ++++++++++++++++++++++++ include/fdtdec.h | 1 + include/power/tps65090_pmic.h | 73 ++++++ lib/fdtdec.c | 1 + 7 files changed, 525 insertions(+) create mode 100644 doc/device-tree-bindings/power/tps65090.txt create mode 100644 doc/device-tree-bindings/regulator/tps65090.txt create mode 100644 drivers/power/pmic/pmic_tps65090.c create mode 100644 include/power/tps65090_pmic.h (limited to 'drivers') diff --git a/doc/device-tree-bindings/power/tps65090.txt b/doc/device-tree-bindings/power/tps65090.txt new file mode 100644 index 00000000000..8e5e0d3910d --- /dev/null +++ b/doc/device-tree-bindings/power/tps65090.txt @@ -0,0 +1,17 @@ +TPS65090 Frontend PMU with Switchmode Charger + +Required Properties: +-compatible: "ti,tps65090-charger" + +Optional Properties: +-ti,enable-low-current-chrg: Enables charging when a low current is detected + while the default logic is to stop charging. + +This node is a subnode of the tps65090 PMIC. + +Example: + + tps65090-charger { + compatible = "ti,tps65090-charger"; + ti,enable-low-current-chrg; + }; diff --git a/doc/device-tree-bindings/regulator/tps65090.txt b/doc/device-tree-bindings/regulator/tps65090.txt new file mode 100644 index 00000000000..313a60ba61d --- /dev/null +++ b/doc/device-tree-bindings/regulator/tps65090.txt @@ -0,0 +1,122 @@ +TPS65090 regulators + +Required properties: +- compatible: "ti,tps65090" +- reg: I2C slave address +- interrupts: the interrupt outputs of the controller +- regulators: A node that houses a sub-node for each regulator within the + device. Each sub-node is identified using the node's name, with valid + values listed below. The content of each sub-node is defined by the + standard binding for regulators; see regulator.txt. + dcdc[1-3], fet[1-7] and ldo[1-2] respectively. +- vsys[1-3]-supply: The input supply for DCDC[1-3] respectively. +- infet[1-7]-supply: The input supply for FET[1-7] respectively. +- vsys-l[1-2]-supply: The input supply for LDO[1-2] respectively. + +Optional properties: +- ti,enable-ext-control: This is applicable for DCDC1, DCDC2 and DCDC3. + If DCDCs are externally controlled then this property should be there. +- "dcdc-ext-control-gpios: This is applicable for DCDC1, DCDC2 and DCDC3. + If DCDCs are externally controlled and if it is from GPIO then GPIO + number should be provided. If it is externally controlled and no GPIO + entry then driver will just configure this rails as external control + and will not provide any enable/disable APIs. + +Each regulator is defined using the standard binding for regulators. + +Example: + + tps65090@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + interrupts = <0 88 0x4>; + + vsys1-supply = <&some_reg>; + vsys2-supply = <&some_reg>; + vsys3-supply = <&some_reg>; + infet1-supply = <&some_reg>; + infet2-supply = <&some_reg>; + infet3-supply = <&some_reg>; + infet4-supply = <&some_reg>; + infet5-supply = <&some_reg>; + infet6-supply = <&some_reg>; + infet7-supply = <&some_reg>; + vsys_l1-supply = <&some_reg>; + vsys_l2-supply = <&some_reg>; + + regulators { + dcdc1 { + regulator-name = "dcdc1"; + regulator-boot-on; + regulator-always-on; + ti,enable-ext-control; + dcdc-ext-control-gpios = <&gpio 10 0>; + }; + + dcdc2 { + regulator-name = "dcdc2"; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3 { + regulator-name = "dcdc3"; + regulator-boot-on; + regulator-always-on; + }; + + fet1 { + regulator-name = "fet1"; + regulator-boot-on; + regulator-always-on; + }; + + fet2 { + regulator-name = "fet2"; + regulator-boot-on; + regulator-always-on; + }; + + fet3 { + regulator-name = "fet3"; + regulator-boot-on; + regulator-always-on; + }; + + fet4 { + regulator-name = "fet4"; + regulator-boot-on; + regulator-always-on; + }; + + fet5 { + regulator-name = "fet5"; + regulator-boot-on; + regulator-always-on; + }; + + fet6 { + regulator-name = "fet6"; + regulator-boot-on; + regulator-always-on; + }; + + fet7 { + regulator-name = "fet7"; + regulator-boot-on; + regulator-always-on; + }; + + ldo1 { + regulator-name = "ldo1"; + regulator-boot-on; + regulator-always-on; + }; + + ldo2 { + regulator-name = "ldo2"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 4129bdabfbe..3244f690b9c 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o +obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps65090.c b/drivers/power/pmic/pmic_tps65090.c new file mode 100644 index 00000000000..c5b396610ac --- /dev/null +++ b/drivers/power/pmic/pmic_tps65090.c @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define TPS65090_NAME "TPS65090_PMIC" + +/* TPS65090 register addresses */ +enum { + REG_IRQ1 = 0, + REG_CG_CTRL0 = 4, + REG_CG_STATUS1 = 0xa, + REG_FET1_CTRL = 0x0f, + REG_FET2_CTRL, + REG_FET3_CTRL, + REG_FET4_CTRL, + REG_FET5_CTRL, + REG_FET6_CTRL, + REG_FET7_CTRL, + TPS65090_NUM_REGS, +}; + +enum { + IRQ1_VBATG = 1 << 3, + CG_CTRL0_ENC_MASK = 0x01, + + MAX_FET_NUM = 7, + MAX_CTRL_READ_TRIES = 5, + + /* TPS65090 FET_CTRL register values */ + FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ + FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ + FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ + FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ + FET_CTRL_ENFET = 1 << 0, /* Enable FET */ +}; + +/** + * Checks for a valid FET number + * + * @param fet_id FET number to check + * @return 0 if ok, -EINVAL if FET value is out of range + */ +static int tps65090_check_fet(unsigned int fet_id) +{ + if (fet_id == 0 || fet_id > MAX_FET_NUM) { + debug("parameter fet_id is out of range, %u not in 1 ~ %u\n", + fet_id, MAX_FET_NUM); + return -EINVAL; + } + + return 0; +} + +/** + * Set the power state for a FET + * + * @param pmic pmic structure for the tps65090 + * @param fet_id Fet number to set (1..MAX_FET_NUM) + * @param set 1 to power on FET, 0 to power off + * @return -EIO if we got a comms error, -EAGAIN if the FET failed to + * change state. If all is ok, returns 0. + */ +static int tps65090_fet_set(struct pmic *pmic, int fet_id, bool set) +{ + int retry; + u32 reg, value; + + value = FET_CTRL_ADENFET | FET_CTRL_WAIT; + if (set) + value |= FET_CTRL_ENFET; + + if (pmic_reg_write(pmic, REG_FET1_CTRL + fet_id - 1, value)) + return -EIO; + + /* Try reading until we get a result */ + for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) { + if (pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, ®)) + return -EIO; + + /* Check that the fet went into the expected state */ + if (!!(reg & FET_CTRL_PGFET) == set) + return 0; + + /* If we got a timeout, there is no point in waiting longer */ + if (reg & FET_CTRL_TOFET) + break; + + mdelay(1); + } + + debug("FET %d: Power good should have set to %d but reg=%#02x\n", + fet_id, set, reg); + return -EAGAIN; +} + +int tps65090_fet_enable(unsigned int fet_id) +{ + struct pmic *pmic; + ulong start; + int loops; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -EACCES; + + start = get_timer(0); + for (loops = 0;; loops++) { + ret = tps65090_fet_set(pmic, fet_id, true); + if (!ret) + break; + + if (get_timer(start) > 100) + break; + + /* Turn it off and try again until we time out */ + tps65090_fet_set(pmic, fet_id, false); + } + + if (ret) + debug("%s: FET%d failed to power on: time=%lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + else if (loops) + debug("%s: FET%d powered on after %lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + + /* + * Unfortunately, there are some conditions where the power + * good bit will be 0, but the fet still comes up. One such + * case occurs with the lcd backlight. We'll just return 0 here + * and assume that the fet will eventually come up. + */ + if (ret == -EAGAIN) + ret = 0; + + return ret; +} + +int tps65090_fet_disable(unsigned int fet_id) +{ + struct pmic *pmic; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -EACCES; + ret = tps65090_fet_set(pmic, fet_id, false); + + return ret; +} + +int tps65090_fet_is_enabled(unsigned int fet_id) +{ + struct pmic *pmic; + u32 reg; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -ENODEV; + ret = pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, ®); + if (ret) { + debug("fail to read FET%u_CTRL register over I2C", fet_id); + return -EIO; + } + + return reg & FET_CTRL_ENFET; +} + +int tps65090_get_charging(void) +{ + struct pmic *pmic; + u32 val; + int ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -EACCES; + + ret = pmic_reg_read(pmic, REG_CG_CTRL0, &val); + if (ret) + return ret; + + return !!(val & CG_CTRL0_ENC_MASK); +} + +static int tps65090_charger_state(struct pmic *pmic, int state, + int current) +{ + u32 val; + int ret; + + ret = pmic_reg_read(pmic, REG_CG_CTRL0, &val); + if (!ret) { + if (state == PMIC_CHARGER_ENABLE) + val |= CG_CTRL0_ENC_MASK; + else + val &= ~CG_CTRL0_ENC_MASK; + ret = pmic_reg_write(pmic, REG_CG_CTRL0, val); + } + if (ret) { + debug("%s: Failed to read/write register\n", __func__); + return ret; + } + + return 0; +} + +int tps65090_get_status(void) +{ + struct pmic *pmic; + u32 val; + int ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -EACCES; + + ret = pmic_reg_read(pmic, REG_CG_STATUS1, &val); + if (ret) + return ret; + + return val; +} + +static int tps65090_charger_bat_present(struct pmic *pmic) +{ + u32 val; + int ret; + + ret = pmic_reg_read(pmic, REG_IRQ1, &val); + if (ret) + return ret; + + return !!(val & IRQ1_VBATG); +} + +static struct power_chrg power_chrg_pmic_ops = { + .chrg_bat_present = tps65090_charger_bat_present, + .chrg_state = tps65090_charger_state, +}; + +int tps65090_init(void) +{ + struct pmic *p; + int bus; + int addr; + const void *blob = gd->fdt_blob; + int node, parent; + + node = fdtdec_next_compatible(blob, 0, COMPAT_TI_TPS65090); + if (node < 0) { + debug("PMIC: No node for PMIC Chip in device tree\n"); + debug("node = %d\n", node); + return -ENODEV; + } + + parent = fdt_parent_offset(blob, node); + if (parent < 0) { + debug("%s: Cannot find node parent\n", __func__); + return -EINVAL; + } + + bus = i2c_get_bus_num_fdt(parent); + if (p->bus < 0) { + debug("%s: Cannot find I2C bus\n", __func__); + return -ENOENT; + } + addr = fdtdec_get_int(blob, node, "reg", TPS65090_I2C_ADDR); + p = pmic_alloc(); + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = TPS65090_NAME; + p->bus = bus; + p->interface = PMIC_I2C; + p->number_of_regs = TPS65090_NUM_REGS; + p->hw.i2c.addr = addr; + p->hw.i2c.tx_num = 1; + p->chrg = &power_chrg_pmic_ops; + + puts("TPS65090 PMIC init\n"); + + return 0; +} diff --git a/include/fdtdec.h b/include/fdtdec.h index 8c751fdc5f1..4b029d72588 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -92,6 +92,7 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */ COMPAT_SANDBOX_HOST_EMULATION, /* Sandbox emulation of a function */ COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */ + COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */ COMPAT_COUNT, }; diff --git a/include/power/tps65090_pmic.h b/include/power/tps65090_pmic.h new file mode 100644 index 00000000000..dcf99c956a5 --- /dev/null +++ b/include/power/tps65090_pmic.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TPS65090_PMIC_H_ +#define __TPS65090_PMIC_H_ + +/* I2C device address for TPS65090 PMU */ +#define TPS65090_I2C_ADDR 0x48 + +enum { + /* Status register fields */ + TPS65090_ST1_OTC = 1 << 0, + TPS65090_ST1_OCC = 1 << 1, + TPS65090_ST1_STATE_SHIFT = 4, + TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT, +}; + +/** + * Enable FET + * + * @param fet_id FET ID, value between 1 and 7 + * @return 0 on success, non-0 on failure + */ +int tps65090_fet_enable(unsigned int fet_id); + +/** + * Disable FET + * + * @param fet_id FET ID, value between 1 and 7 + * @return 0 on success, non-0 on failure + */ +int tps65090_fet_disable(unsigned int fet_id); + +/** + * Is FET enabled? + * + * @param fet_id FET ID, value between 1 and 7 + * @return 1 enabled, 0 disabled, negative value on failure + */ +int tps65090_fet_is_enabled(unsigned int fet_id); + +/** + * Enable / disable the battery charger + * + * @param enable 0 to disable charging, non-zero to enable + */ +int tps65090_set_charge_enable(int enable); + +/** + * Check whether we have enabled battery charging + * + * @return 1 if enabled, 0 if disabled + */ +int tps65090_get_charging(void); + +/** + * Return the value of the status register + * + * @return status register value, or -1 on error + */ +int tps65090_get_status(void); + +/** + * Initialize the TPS65090 PMU. + * + * @return 0 on success, non-0 on failure + */ +int tps65090_init(void); + +#endif /* __TPS65090_PMIC_H_ */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 35e91b4ef08..6cccfe57cd8 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -66,6 +66,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"), COMPAT(SANDBOX_HOST_EMULATION, "sandbox,host-emulation"), COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"), + COMPAT(TI_TPS65090, "ti,tps65090"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- cgit v1.3.1 From 0b259dc2e849183dfea604fa137bb616e09b319a Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 20 May 2014 06:01:38 -0600 Subject: power: Explicitly select pmic device's bus The current pmic i2c code assumes the current i2c bus is the same as the pmic device's bus. There is nothing ensuring that to be true. Therefore, select the proper bus before performing a transaction. Signed-off-by: Aaron Durbin Signed-off-by: Simon Glass Acked-by: Heiko Schocher Reviewed-by: Simon Glass Signed-off-by: Minkyu Kang --- drivers/power/power_i2c.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c index ac768708ead..594cd11725e 100644 --- a/drivers/power/power_i2c.c +++ b/drivers/power/power_i2c.c @@ -23,6 +23,8 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val) if (check_reg(p, reg)) return -1; + I2C_SET_BUS(p->bus); + switch (pmic_i2c_tx_num) { case 3: if (p->sensor_byte_order == PMIC_SENSOR_BYTE_ORDER_BIG) { @@ -66,6 +68,8 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) if (check_reg(p, reg)) return -1; + I2C_SET_BUS(p->bus); + if (i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num)) return -1; -- cgit v1.3.1 From 18d66533ac773f59efc93e5c19971fad5e6af82f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 10 Apr 2014 20:01:25 -0600 Subject: move CLI prototypes to cli.h and add comments Move the CLI prototypes from common.h to cli.h as part of an effort to reduce the size of common.h. Signed-off-by: Simon Glass --- board/ait/cam_enc_4xx/cam_enc_4xx.c | 1 + board/amcc/yucca/cmd_yucca.c | 1 + board/eltec/elppc/misc.c | 1 + board/eltec/mhpc/mhpc.c | 1 + board/hymod/hymod.c | 1 + board/hymod/input.c | 1 + common/cli_hush.c | 1 + common/cmd_bedbug.c | 1 + common/cmd_dcr.c | 1 + common/cmd_i2c.c | 1 + common/cmd_mem.c | 1 + common/cmd_nvedit.c | 1 + common/cmd_pci.c | 1 + common/main.c | 1 + common/menu.c | 1 + drivers/ddr/fsl/interactive.c | 1 + include/cli.h | 102 ++++++++++++++++++++++++++++++++++++ include/common.h | 4 -- 18 files changed, 118 insertions(+), 4 deletions(-) create mode 100644 include/cli.h (limited to 'drivers') diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index b5cc3ed3635..7c26ba0059b 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c index dc78b737315..3257c29871c 100644 --- a/board/amcc/yucca/cmd_yucca.c +++ b/board/amcc/yucca/cmd_yucca.c @@ -8,6 +8,7 @@ */ #include +#include #include #include "yucca.h" #include diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c index d80eaba2d0a..70d1f9a17fa 100644 --- a/board/eltec/elppc/misc.c +++ b/board/eltec/elppc/misc.c @@ -7,6 +7,7 @@ /* includes */ #include +#include #include #include #include diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c index f3f564ffe4b..ff9e0ab9723 100644 --- a/board/eltec/mhpc/mhpc.c +++ b/board/eltec/mhpc/mhpc.c @@ -14,6 +14,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include "mpc8xx.h" diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c index 5fec914f5ad..ea49e26dd2f 100644 --- a/board/hymod/hymod.c +++ b/board/hymod/hymod.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/board/hymod/input.c b/board/hymod/input.c index 184902cde57..23d3f19e3e9 100644 --- a/board/hymod/input.c +++ b/board/hymod/input.c @@ -6,6 +6,7 @@ */ #include +#include int hymod_get_serno (const char *prompt) diff --git a/common/cli_hush.c b/common/cli_hush.c index 012004aea54..91e495690c9 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -79,6 +79,7 @@ #include /* malloc, free, realloc*/ #include /* isalpha, isdigit */ #include /* readline */ +#include #include #include /* find_cmd */ #ifndef CONFIG_SYS_PROMPT_HUSH_PS2 diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c index 77b6e3e88e4..f1a70ef2028 100644 --- a/common/cmd_bedbug.c +++ b/common/cmd_bedbug.c @@ -3,6 +3,7 @@ */ #include +#include #include #include #include diff --git a/common/cmd_dcr.c b/common/cmd_dcr.c index 896f79f416c..c5bcb8b89dc 100644 --- a/common/cmd_dcr.c +++ b/common/cmd_dcr.c @@ -10,6 +10,7 @@ */ #include +#include #include #include diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index ebce7d4c3c0..8ccde68110e 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -66,6 +66,7 @@ */ #include +#include #include #include #include diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 5b03c2d5b10..4b8738b4f03 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -12,6 +12,7 @@ */ #include +#include #include #ifdef CONFIG_HAS_DATAFLASH #include diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index f4e306ceba9..a1e98c6d955 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -25,6 +25,7 @@ */ #include +#include #include #include #include diff --git a/common/cmd_pci.c b/common/cmd_pci.c index d3e7c089b00..ddda207e584 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include diff --git a/common/main.c b/common/main.c index a80fb7c3441..6d1c3a9fadb 100644 --- a/common/main.c +++ b/common/main.c @@ -12,6 +12,7 @@ /* #define DEBUG */ #include +#include #include #include #include diff --git a/common/menu.c b/common/menu.c index ba393adc32c..88d4697254e 100644 --- a/common/menu.c +++ b/common/menu.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index cfe1e1f55aa..4e2120f7c45 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -12,6 +12,7 @@ */ #include +#include #include #include #include diff --git a/include/cli.h b/include/cli.h new file mode 100644 index 00000000000..0075bd44c94 --- /dev/null +++ b/include/cli.h @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2014 Google, Inc + * Simon Glass + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CLI_H +#define __CLI_H + +/** + * Go into the command loop + * + * This will return if we get a timeout waiting for a command. See + * CONFIG_BOOT_RETRY_TIME. + */ +void cli_loop(void); + +/** + * cli_simple_run_command() - Execute a command with the simple CLI + * + * @cmd: String containing the command to execute + * @flag Flag value - see CMD_FLAG_... + * @return 1 - command executed, repeatable + * 0 - command executed but not repeatable, interrupted commands are + * always considered not repeatable + * -1 - not executed (unrecognized, bootd recursion or too many args) + * (If cmd is NULL or "" or longer than CONFIG_SYS_CBSIZE-1 it is + * considered unrecognized) + */ +int cli_simple_run_command(const char *cmd, int flag); + +/** + * cli_simple_run_command_list() - Execute a list of command + * + * The commands should be separated by ; or \n and will be executed + * by the built-in parser. + * + * This function cannot take a const char * for the command, since if it + * finds newlines in the string, it replaces them with \0. + * + * @param cmd String containing list of commands + * @param flag Execution flags (CMD_FLAG_...) + * @return 0 on success, or != 0 on error. + */ +int cli_simple_run_command_list(char *cmd, int flag); + +/** + * cli_readline() - read a line into the console_buffer + * + * This is a convenience function which calls cli_readline_into_buffer(). + * + * @prompt: Prompt to display + * @return command line length excluding terminator, or -ve on error + */ +int readline(const char *const prompt); + +/** + * readline_into_buffer() - read a line into a buffer + * + * Display the prompt, then read a command line into @buffer. The + * maximum line length is CONFIG_SYS_CBSIZE including a \0 terminator, which + * will always be added. + * + * The command is echoed as it is typed. Command editing is supported if + * CONFIG_CMDLINE_EDITING is defined. Tab auto-complete is supported if + * CONFIG_AUTO_COMPLETE is defined. If CONFIG_BOOT_RETRY_TIME is defined, + * then a timeout will be applied. + * + * If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0, + * time out when time goes past endtime (timebase time in ticks). + * + * @prompt: Prompt to display + * @buffer: Place to put the line that is entered + * @timeout: Timeout in milliseconds, 0 if none + * @return command line length excluding terminator, or -ve on error: of the + * timeout is exceeded (either CONFIG_BOOT_RETRY_TIME or the timeout + * parameter), then -2 is returned. If a break is detected (Ctrl-C) then + * -1 is returned. + */ +int readline_into_buffer(const char *const prompt, char *buffer, int timeout); + +/** + * parse_line() - split a command line down into separate arguments + * + * The argv[] array is filled with pointers into @line, and each argument + * is terminated by \0 (i.e. @line is changed in the process unless there + * is only one argument). + * + * #argv is terminated by a NULL after the last argument pointer. + * + * At most CONFIG_SYS_MAXARGS arguments are permited - if there are more + * than that then an error is printed, and this function returns + * CONFIG_SYS_MAXARGS, with argv[] set up to that point. + * + * @line: Command line to parse + * @args: Array to hold arguments + * @return number of arguments + */ +int parse_line(char *line, char *argv[]); + +#endif diff --git a/include/common.h b/include/common.h index 232136c0cd1..75cb525f3ec 100644 --- a/include/common.h +++ b/include/common.h @@ -286,10 +286,6 @@ int run_command(const char *cmd, int flag); * @return 0 on success, or != 0 on error. */ int run_command_list(const char *cmd, int len, int flag); -int readline (const char *const prompt); -int readline_into_buffer(const char *const prompt, char *buffer, - int timeout); -int parse_line (char *, char *[]); void init_cmd_timeout(void); void reset_cmd_timeout(void); extern char console_buffer[]; -- cgit v1.3.1 From e1bf824dfd6881f6f633238c275bfa1e5d83c433 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 10 Apr 2014 20:01:27 -0600 Subject: Add cli_ prefix to readline functions This makes it clear where the code resides. Signed-off-by: Simon Glass --- board/ait/cam_enc_4xx/cam_enc_4xx.c | 2 +- board/amcc/yucca/cmd_yucca.c | 20 ++++++++++---------- board/eltec/elppc/misc.c | 14 +++++++------- board/eltec/mhpc/mhpc.c | 12 ++++++------ board/hymod/hymod.c | 2 +- board/hymod/input.c | 4 ++-- common/cli_hush.c | 4 ++-- common/cli_readline.c | 7 ++++--- common/cli_simple.c | 6 +++--- common/cmd_bedbug.c | 28 ++++++++++++++-------------- common/cmd_dcr.c | 2 +- common/cmd_i2c.c | 2 +- common/cmd_mem.c | 2 +- common/cmd_nvedit.c | 4 ++-- common/cmd_pci.c | 2 +- common/menu.c | 5 +++-- drivers/ddr/fsl/interactive.c | 7 ++++--- include/cli.h | 7 ++++--- 18 files changed, 67 insertions(+), 63 deletions(-) (limited to 'drivers') diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index 7c26ba0059b..9aa1d7aece4 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -777,7 +777,7 @@ static void ait_menu_read_env(char *name) sprintf(output, "%s old: %s value: ", name, getenv(name)); memset(cbuf, 0, CONFIG_SYS_CBSIZE); - readret = readline_into_buffer(output, cbuf, 0); + readret = cli_readline_into_buffer(output, cbuf, 0); if (readret >= 0) { ret = setenv(name, cbuf); diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c index 3257c29871c..c1724bf0348 100644 --- a/board/amcc/yucca/cmd_yucca.c +++ b/board/amcc/yucca/cmd_yucca.c @@ -52,7 +52,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, do { printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n"); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -75,7 +75,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n"); #endif } - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -119,7 +119,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, printf("enter plb clock frequency 133, 166 MHz or quit to abort\n"); #endif - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -143,7 +143,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, do { printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n"); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -164,13 +164,13 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, printf("Pci-X clk = %s MHz\n", pcixClock); do { - printf("\npress [y] to write I2C bootstrap \n"); - printf("or [n] to abort. \n"); - printf("Don't forget to set board switches \n"); - printf("according to your choice before re-starting \n"); - printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n"); + printf("\npress [y] to write I2C bootstrap\n"); + printf("or [n] to abort.\n"); + printf("Don't forget to set board switches\n"); + printf("according to your choice before re-starting\n"); + printf("(refer to 440spe_uboot_kit_um_1_01.pdf)\n"); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "n") == 0) return 0; diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c index 70d1f9a17fa..2acf80047fe 100644 --- a/board/eltec/elppc/misc.c +++ b/board/eltec/elppc/misc.c @@ -114,7 +114,7 @@ int misc_init_r (void) printf ("Press key:\n to copy current revision info to nvram.\n"); printf (" to reenter revision info.\n"); printf ("=> "); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { switch ((char) toupper (console_buffer[0])) { case 'C': copyNv = 1; @@ -131,7 +131,7 @@ int misc_init_r (void) memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */ printf ("Enter revision number (0-9): %c ", eerev.revision[0][0]); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { eerev.revision[0][0] = (char) toupper (console_buffer[0]); memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */ @@ -139,14 +139,14 @@ int misc_init_r (void) printf ("Enter revision character (A-Z): %c ", eerev.revision[0][1]); - if (1 == readline (NULL)) { + if (1 == cli_readline(NULL)) { eerev.revision[0][1] = (char) toupper (console_buffer[0]); } printf ("Enter board name (V-XXXX-XXXX): %s ", (char *) &eerev.board); - if (11 == readline (NULL)) { + if (11 == cli_readline(NULL)) { for (i = 0; i < 11; i++) eerev.board[i] = (char) toupper (console_buffer[i]); @@ -154,14 +154,14 @@ int misc_init_r (void) } printf ("Enter serial number: %s ", (char *) &eerev.serial); - if (6 == readline (NULL)) { + if (6 == cli_readline(NULL)) { for (i = 0; i < 6; i++) eerev.serial[i] = console_buffer[i]; eerev.serial[6] = '\0'; } printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]); - if (12 == readline (NULL)) { + if (12 == cli_readline(NULL)) { for (i = 0; i < 12; i += 2) eerev.etheraddr[i >> 1] = (char) (16 * @@ -176,7 +176,7 @@ int misc_init_r (void) l = strlen ((char *) &eerev.text); printf ("Add to text section (max 64 chr): %s ", (char *) &eerev.text); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { for (i = l; i < 63; i++) eerev.text[i] = console_buffer[i - l]; eerev.text[63] = '\0'; diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c index ff9e0ab9723..5781b2a54f3 100644 --- a/board/eltec/mhpc/mhpc.c +++ b/board/eltec/mhpc/mhpc.c @@ -147,21 +147,21 @@ int misc_init_r (void) if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) { printf ("Enter revision number (0-9): %c ", mhpcRevInfo.revision[0]); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { mhpcRevInfo.revision[0] = (char) toupper (console_buffer[0]); } printf ("Enter revision character (A-Z): %c ", mhpcRevInfo.revision[1]); - if (1 == readline (NULL)) { + if (1 == cli_readline(NULL)) { mhpcRevInfo.revision[1] = (char) toupper (console_buffer[0]); } printf ("Enter board name (V-XXXX-XXXX): %s ", (char *) &mhpcRevInfo.board); - if (11 == readline (NULL)) { + if (11 == cli_readline(NULL)) { for (i = 0; i < 11; i++) { mhpcRevInfo.board[i] = (char) toupper (console_buffer[i]); @@ -178,7 +178,7 @@ int misc_init_r (void) do { printf ("\nEnter sensor number (0-255): %d ", (int) mhpcRevInfo.sensor); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { mhpcRevInfo.sensor = (unsigned char) simple_strtoul (console_buffer, NULL, @@ -188,7 +188,7 @@ int misc_init_r (void) printf ("Enter serial number: %s ", (char *) &mhpcRevInfo.serial); - if (6 == readline (NULL)) { + if (6 == cli_readline(NULL)) { for (i = 0; i < 6; i++) { mhpcRevInfo.serial[i] = console_buffer[i]; } @@ -196,7 +196,7 @@ int misc_init_r (void) } printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); - if (12 == readline (NULL)) { + if (12 == cli_readline(NULL)) { for (i = 0; i < 12; i += 2) { mhpcRevInfo.etheraddr[i >> 1] = (char) (16 * diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c index ea49e26dd2f..55ffd676cf5 100644 --- a/board/hymod/hymod.c +++ b/board/hymod/hymod.c @@ -416,7 +416,7 @@ last_stage_init (void) #ifdef CONFIG_BOOT_RETRY_TIME /* - * we use the readline () function, but we also want + * we use the cli_readline() function, but we also want * command timeout enabled */ init_cmd_timeout (); diff --git a/board/hymod/input.c b/board/hymod/input.c index 23d3f19e3e9..59ad6aa3ed9 100644 --- a/board/hymod/input.c +++ b/board/hymod/input.c @@ -19,7 +19,7 @@ hymod_get_serno (const char *prompt) reset_cmd_timeout (); #endif - n = readline (prompt); + n = cli_readline(prompt); if (n < 0) return (n); @@ -47,7 +47,7 @@ hymod_get_ethaddr (void) reset_cmd_timeout (); #endif - n = readline ("Enter board ethernet address: "); + n = cli_readline("Enter board ethernet address: "); if (n < 0) return (n); diff --git a/common/cli_hush.c b/common/cli_hush.c index 91e495690c9..a612bfbef51 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -1007,9 +1007,9 @@ static void get_user_input(struct in_str *i) #endif i->__promptme = 1; if (i->promptmode == 1) { - n = readline(CONFIG_SYS_PROMPT); + n = cli_readline(CONFIG_SYS_PROMPT); } else { - n = readline(CONFIG_SYS_PROMPT_HUSH_PS2); + n = cli_readline(CONFIG_SYS_PROMPT_HUSH_PS2); } #ifdef CONFIG_BOOT_RETRY_TIME if (n == -2) { diff --git a/common/cli_readline.c b/common/cli_readline.c index cea0b7c81b8..df446b8c836 100644 --- a/common/cli_readline.c +++ b/common/cli_readline.c @@ -484,7 +484,7 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len, /****************************************************************************/ -int readline(const char *const prompt) +int cli_readline(const char *const prompt) { /* * If console_buffer isn't 0-length the user will be prompted to modify @@ -492,11 +492,12 @@ int readline(const char *const prompt) */ console_buffer[0] = '\0'; - return readline_into_buffer(prompt, console_buffer, 0); + return cli_readline_into_buffer(prompt, console_buffer, 0); } -int readline_into_buffer(const char *const prompt, char *buffer, int timeout) +int cli_readline_into_buffer(const char *const prompt, char *buffer, + int timeout) { char *p = buffer; #ifdef CONFIG_CMDLINE_EDITING diff --git a/common/cli_simple.c b/common/cli_simple.c index 0610615ea5a..3039cfcca1f 100644 --- a/common/cli_simple.c +++ b/common/cli_simple.c @@ -19,7 +19,7 @@ debug_cond(DEBUG_PARSER, fmt, ##args) -int parse_line(char *line, char *argv[]) +int cli_simple_parse_line(char *line, char *argv[]) { int nargs = 0; @@ -238,7 +238,7 @@ int cli_simple_run_command(const char *cmd, int flag) process_macros(token, finaltoken); /* Extract arguments */ - argc = parse_line(finaltoken, argv); + argc = cli_simple_parse_line(finaltoken, argv); if (argc == 0) { rc = -1; /* no command at all */ continue; @@ -272,7 +272,7 @@ void cli_loop(void) reset_cmd_timeout(); } #endif - len = readline(CONFIG_SYS_PROMPT); + len = cli_readline(CONFIG_SYS_PROMPT); flag = 0; /* assume no special flags for now */ if (len > 0) diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c index f1a70ef2028..bdcf712d111 100644 --- a/common/cmd_bedbug.c +++ b/common/cmd_bedbug.c @@ -20,7 +20,7 @@ extern int run_command __P ((const char *, int)); ulong dis_last_addr = 0; /* Last address disassembled */ ulong dis_last_len = 20; /* Default disassembler length */ CPU_DEBUG_CTX bug_ctx; /* Bedbug context structure */ - + /* ====================================================================== * U-Boot's puts function does not append a newline, so the bedbug stuff @@ -34,7 +34,7 @@ int bedbug_puts (const char *str) printf ("%s\r\n", str); return 0; } /* bedbug_puts */ - + /* ====================================================================== @@ -66,7 +66,7 @@ void bedbug_init (void) return; } /* bedbug_init */ - + /* ====================================================================== @@ -107,7 +107,7 @@ int do_bedbug_dis (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (ds, 3, 1, do_bedbug_dis, "disassemble memory", "ds
[# instructions]"); - + /* ====================================================================== * Entry point from the interpreter to the assembler. Assembles * instructions in consecutive memory locations until a '.' (period) is @@ -135,7 +135,7 @@ int do_bedbug_asm (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) F_RADHEX); sprintf (prompt, "%08lx: ", mem_addr); - readline (prompt); + cli_readline(prompt); if (console_buffer[0] && strcmp (console_buffer, ".")) { if ((instr = @@ -157,7 +157,7 @@ int do_bedbug_asm (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (as, 2, 0, do_bedbug_asm, "assemble memory", "as
"); - + /* ====================================================================== * Used to set a break point from the interpreter. Simply calls into the * CPU-specific break point set routine. @@ -178,7 +178,7 @@ U_BOOT_CMD (break, 3, 0, do_bedbug_break, "break
- Break at an address\n" "break off - Disable breakpoint.\n" "break show - List breakpoints."); - + /* ====================================================================== * Called from the debug interrupt routine. Simply calls the CPU-specific * breakpoint handling routine. @@ -193,7 +193,7 @@ void do_bedbug_breakpoint (struct pt_regs *regs) return; } /* do_bedbug_breakpoint */ - + /* ====================================================================== @@ -226,7 +226,7 @@ void bedbug_main_loop (unsigned long addr, struct pt_regs *regs) /* A miniature main loop */ while (bug_ctx.stopped) { - len = readline (prompt_str); + len = cli_readline(prompt_str); flag = 0; /* assume no special flags for now */ @@ -251,7 +251,7 @@ void bedbug_main_loop (unsigned long addr, struct pt_regs *regs) return; } /* bedbug_main_loop */ - + /* ====================================================================== @@ -275,7 +275,7 @@ int do_bedbug_continue (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv U_BOOT_CMD (continue, 1, 0, do_bedbug_continue, "continue from a breakpoint", ""); - + /* ====================================================================== * Interpreter command to continue to the next instruction, stepping into * subroutines. Works by calling the find_next_addr() routine to compute @@ -306,7 +306,7 @@ int do_bedbug_step (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (step, 1, 1, do_bedbug_step, "single step execution.", ""); - + /* ====================================================================== * Interpreter command to continue to the next instruction, stepping over * subroutines. Works by calling the find_next_addr() routine to compute @@ -337,7 +337,7 @@ int do_bedbug_next (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (next, 1, 1, do_bedbug_next, "single step execution, stepping over subroutines.", ""); - + /* ====================================================================== * Interpreter command to print the current stack. This assumes an EABI * architecture, so it starts with GPR R1 and works back up the stack. @@ -382,7 +382,7 @@ int do_bedbug_stack (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (where, 1, 1, do_bedbug_stack, "Print the running stack.", ""); - + /* ====================================================================== * Interpreter command to dump the registers. Calls the CPU-specific * show registers routine. diff --git a/common/cmd_dcr.c b/common/cmd_dcr.c index c5bcb8b89dc..4fddd804abd 100644 --- a/common/cmd_dcr.c +++ b/common/cmd_dcr.c @@ -63,7 +63,7 @@ int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) do { value = get_dcr (dcrn); printf ("%04x: %08lx", dcrn, value); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (nbytes == 0) { /* * pressed as only input, don't modify current diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 8ccde68110e..7158b5a2db1 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -613,7 +613,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg printf(" %08lx", data); } - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (nbytes == 0) { /* * pressed as only input, don't modify current diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 4b8738b4f03..15a4b84efdc 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -1150,7 +1150,7 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) else printf(" %02x", *((u8 *)ptr)); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { /* pressed as only input, don't modify current * location and move to next. "-" pressed will go back. diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index a1e98c6d955..e6c33956e7b 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -409,7 +409,7 @@ int do_env_ask(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; /* prompt for input */ - len = readline(message); + len = cli_readline(message); if (size < len) console_buffer[size] = '\0'; @@ -592,7 +592,7 @@ static int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc, else buffer[0] = '\0'; - if (readline_into_buffer("edit: ", buffer, 0) < 0) + if (cli_readline_into_buffer("edit: ", buffer, 0) < 0) return 1; return setenv(argv[1], buffer); diff --git a/common/cmd_pci.c b/common/cmd_pci.c index ddda207e584..1ed55cedb16 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -346,7 +346,7 @@ pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag printf(" %02x", val1); } - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { /* pressed as only input, don't modify current * location and move to next. "-" pressed will go back. diff --git a/common/menu.c b/common/menu.c index 88d4697254e..94afeb29009 100644 --- a/common/menu.c +++ b/common/menu.c @@ -197,8 +197,9 @@ static inline int menu_interactive_choice(struct menu *m, void **choice) menu_display(m); if (!m->item_choice) { - readret = readline_into_buffer("Enter choice: ", cbuf, - m->timeout / 10); + readret = cli_readline_into_buffer("Enter choice: ", + cbuf, + m->timeout / 10); if (readret >= 0) { choice_item = menu_item_by_key(m, cbuf); diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index 4e2120f7c45..c9f86302d77 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -1865,11 +1865,12 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set) } else { /* * No need to worry for buffer overflow here in - * this function; readline() maxes out at CFG_CBSIZE + * this function; cli_readline() maxes out at + * CFG_CBSIZE */ - readline_into_buffer(prompt, buffer, 0); + cli_readline_into_buffer(prompt, buffer, 0); } - argc = parse_line(buffer, argv); + argc = cli_simple_parse_line(buffer, argv); if (argc == 0) continue; diff --git a/include/cli.h b/include/cli.h index b04539f3202..61f8aee4add 100644 --- a/include/cli.h +++ b/include/cli.h @@ -53,7 +53,7 @@ int cli_simple_run_command_list(char *cmd, int flag); * @prompt: Prompt to display * @return command line length excluding terminator, or -ve on error */ -int readline(const char *const prompt); +int cli_readline(const char *const prompt); /** * readline_into_buffer() - read a line into a buffer @@ -78,7 +78,8 @@ int readline(const char *const prompt); * parameter), then -2 is returned. If a break is detected (Ctrl-C) then * -1 is returned. */ -int readline_into_buffer(const char *const prompt, char *buffer, int timeout); +int cli_readline_into_buffer(const char *const prompt, char *buffer, + int timeout); /** * parse_line() - split a command line down into separate arguments @@ -97,7 +98,7 @@ int readline_into_buffer(const char *const prompt, char *buffer, int timeout); * @args: Array to hold arguments * @return number of arguments */ -int parse_line(char *line, char *argv[]); +int cli_simple_parse_line(char *line, char *argv[]); /** bootretry_dont_retry() - Indicate that we should not retry the boot */ void bootretry_dont_retry(void); -- cgit v1.3.1 From bd694244db7bc9699548ca276f992aa5ce9bbac0 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Mon, 12 May 2014 10:43:36 +0200 Subject: dfu: Introduction of the "dfu_hash_algo" env variable for checksum method setting Up till now the CRC32 of received data was calculated unconditionally. The standard crc32 implementation causes long delay when large images were uploaded. The "dfu_hash_algo" environment variable gives the opportunity to disable on demand the hash (crc32) calculation. It can be done without the need to recompile the u-boot binary. By default the crc32 is calculated, which means that legacy behavior has been preserved. Tests results: 400 MiB ums.img file With crc32 calculation: 65 sec [avg 6.29 MB/s] Without crc32 calculation: 25 sec [avg 16.17 MB/s] Signed-off-by: Lukasz Majewski Cc: Marek Vasut --- drivers/dfu/dfu.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index a93810934ac..5878f991d92 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -20,6 +21,7 @@ static bool dfu_reset_request; static LIST_HEAD(dfu_list); static int dfu_alt_num; static int alt_num_cnt; +static struct hash_algo *dfu_hash_algo; bool dfu_reset(void) { @@ -99,6 +101,29 @@ unsigned char *dfu_get_buf(void) return dfu_buf; } +static char *dfu_get_hash_algo(void) +{ + char *s; + + s = getenv("dfu_hash_algo"); + /* + * By default the legacy behaviour to calculate the crc32 hash + * value is preserved. + * + * To disable calculation of the hash algorithm for received data + * specify the "dfu_hash_algo = disabled" at your board envs. + */ + debug("%s: DFU hash method: %s\n", __func__, s ? s : "not specified"); + + if (!s || !strcmp(s, "crc32")) + return "crc32"; + + if (!strcmp(s, "disabled")) + return NULL; + + return NULL; +} + static int dfu_write_buffer_drain(struct dfu_entity *dfu) { long w_size; @@ -109,8 +134,9 @@ static int dfu_write_buffer_drain(struct dfu_entity *dfu) if (w_size == 0) return 0; - /* update CRC32 */ - dfu->crc = crc32(dfu->crc, dfu->i_buf_start, w_size); + if (dfu_hash_algo) + dfu_hash_algo->hash_update(dfu_hash_algo, &dfu->crc, + dfu->i_buf_start, w_size, 0); ret = dfu->write_medium(dfu, dfu->offset, dfu->i_buf_start, &w_size); if (ret) @@ -138,7 +164,9 @@ int dfu_flush(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) if (dfu->flush_medium) ret = dfu->flush_medium(dfu); - printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc); + if (dfu_hash_algo) + printf("\nDFU complete %s: 0x%08x\n", dfu_hash_algo->name, + dfu->crc); /* clear everything */ dfu_free_buf(); @@ -238,7 +266,11 @@ static int dfu_read_buffer_fill(struct dfu_entity *dfu, void *buf, int size) /* consume */ if (chunk > 0) { memcpy(buf, dfu->i_buf, chunk); - dfu->crc = crc32(dfu->crc, buf, chunk); + if (dfu_hash_algo) + dfu_hash_algo->hash_update(dfu_hash_algo, + &dfu->crc, buf, + chunk, 0); + dfu->i_buf += chunk; dfu->b_left -= chunk; dfu->r_left -= chunk; @@ -322,7 +354,9 @@ int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) } if (ret < size) { - debug("%s: %s CRC32: 0x%x\n", __func__, dfu->name, dfu->crc); + if (dfu_hash_algo) + debug("%s: %s %s: 0x%x\n", __func__, dfu->name, + dfu_hash_algo->name, dfu->crc); puts("\nUPLOAD ... done\nCtrl+C to exit ...\n"); dfu_free_buf(); @@ -397,6 +431,14 @@ int dfu_config_entities(char *env, char *interface, int num) dfu_alt_num = dfu_find_alt_num(env); debug("%s: dfu_alt_num=%d\n", __func__, dfu_alt_num); + dfu_hash_algo = NULL; + s = dfu_get_hash_algo(); + if (s) { + ret = hash_lookup_algo(s, &dfu_hash_algo); + if (ret) + error("Hash algorithm %s not supported\n", s); + } + dfu = calloc(sizeof(*dfu), dfu_alt_num); if (!dfu) return -1; -- cgit v1.3.1 From 7484d84cbb58e01ff1d2d458d899ea1fba012724 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 29 May 2014 14:53:00 -0600 Subject: usb: ci_udc: detect queued requests on ep0 The flipping of ep0 between IN and OUT relies on ci_ep_queue() consuming the current IN/OUT setting immediately. If this is deferred to a later point when the req is pulled out of ci_req->queue, then the IN/OUT setting may have been changed since the req was queued, and state will get out of sync. This condition doesn't occur today, but could if bugs were introduced later, and this error-check will save a lot of debugging time. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 9cd003636a4..a68a85f84e7 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -397,6 +397,21 @@ static int ci_ep_queue(struct usb_ep *ep, num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + if (!num && ci_ep->req_primed) { + /* + * The flipping of ep0 between IN and OUT relies on + * ci_ep_queue consuming the current IN/OUT setting + * immediately. If this is deferred to a later point when the + * req is pulled out of ci_req->queue, then the IN/OUT setting + * may have been changed since the req was queued, and state + * will get out of sync. This condition doesn't occur today, + * but could if bugs were introduced later, and this error + * check will save a lot of debugging time. + */ + printf("%s: ep0 transaction already in progress\n", __func__); + return -EPROTO; + } + ret = ci_bounce(ci_req, in); if (ret) return ret; -- cgit v1.3.1 From 054731b09e1944cdb130b755ac0f6c188920e98a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 29 May 2014 14:53:01 -0600 Subject: usb: ci_udc: use a single descriptor for ep0 ci_udc currently points ep->desc at separate descriptors for IN and OUT. These descriptors only differ in the ep address IN/OUT field. Modify the code to use a single descriptor, and change that descriptor's ep address to indicate IN/OUT as required. This removes some data duplication. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index a68a85f84e7..77f8c9ef7f0 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -56,14 +56,7 @@ static const char *reqname(unsigned r) } #endif -static struct usb_endpoint_descriptor ep0_out_desc = { - .bLength = sizeof(struct usb_endpoint_descriptor), - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0, - .bmAttributes = USB_ENDPOINT_XFER_CONTROL, -}; - -static struct usb_endpoint_descriptor ep0_in_desc = { +static struct usb_endpoint_descriptor ep0_desc = { .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = USB_DIR_IN, @@ -435,7 +428,7 @@ static void handle_ep_complete(struct ci_ep *ep) num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; if (num == 0) - ep->desc = &ep0_out_desc; + ep0_desc.bEndpointAddress = 0; item = ci_get_qtd(num, in); ci_invalidate_qtd(num); @@ -460,7 +453,7 @@ static void handle_ep_complete(struct ci_ep *ep) if (num == 0) { ci_req->req.length = 0; usb_ep_queue(&ep->ep, &ci_req->req, 0); - ep->desc = &ep0_in_desc; + ep0_desc.bEndpointAddress = USB_DIR_IN; } } @@ -771,7 +764,7 @@ static int ci_udc_probe(void) /* Init EP 0 */ memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init)); - controller.ep[0].desc = &ep0_in_desc; + controller.ep[0].desc = &ep0_desc; INIT_LIST_HEAD(&controller.ep[0].queue); controller.ep[0].req_primed = false; controller.gadget.ep0 = &controller.ep[0].ep; -- cgit v1.3.1 From a2d8f929857b7bc50528114c29e48a99cbcee1f1 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 29 May 2014 14:53:02 -0600 Subject: usb: ci_udc: pre-allocate ep0 req Allocate ep0's USB request object when the UDC driver is probed. This solves a couple of issues in the current code: a) A request object always exists for ep0. Prior to this patch, if setup transactions arrived in an unexpected order, handle_setup() would need to reply to a setup transaction before any ep0 usb_req was created. This issue was introduced in commit 2813006fecda "usb: ci_udc: allow multiple buffer allocs per ep." b) handle_ep_complete no longer /has/ to queue the ep0 request again after every single request completion. This is currently required, since handle_setup() assumes it can find some request object in ep0's request queue. This patch doesn't actually stop handle_ep_complete() from always requeueing the request, but the next patch will. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 17 ++++++++++++++++- drivers/usb/gadget/ci_udc.h | 1 + 2 files changed, 17 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 77f8c9ef7f0..03ad23164fe 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -198,8 +198,14 @@ static void ci_invalidate_qtd(int ep_num) static struct usb_request * ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) { + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + int num; struct ci_req *ci_req; + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + if (num == 0 && controller.ep0_req) + return &controller.ep0_req->req; + ci_req = memalign(ARCH_DMA_MINALIGN, sizeof(*ci_req)); if (!ci_req) return NULL; @@ -207,6 +213,9 @@ ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) INIT_LIST_HEAD(&ci_req->queue); ci_req->b_buf = 0; + if (num == 0) + controller.ep0_req = ci_req; + return &ci_req->req; } @@ -471,7 +480,7 @@ static void handle_setup(void) int num, in, _num, _in, i; char *buf; - ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); + ci_req = controller.ep0_req; req = &ci_req->req; head = ci_get_qh(0, 0); /* EP0 OUT */ @@ -780,6 +789,12 @@ static int ci_udc_probe(void) &controller.gadget.ep_list); } + ci_ep_alloc_request(&controller.ep[0].ep, 0); + if (!controller.ep0_req) { + free(controller.epts); + return -ENOMEM; + } + return 0; } diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h index 23cff56d7ec..7d76af84f03 100644 --- a/drivers/usb/gadget/ci_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -97,6 +97,7 @@ struct ci_ep { struct ci_drv { struct usb_gadget gadget; + struct ci_req *ep0_req; struct usb_gadget_driver *driver; struct ehci_ctrl *ctrl; struct ept_queue_head *epts; -- cgit v1.3.1 From 006c7026882011ba49c9a39d27c4aff3ace07847 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 29 May 2014 14:53:03 -0600 Subject: usb: ci_udc: complete ep0 direction handling handle_setup() currently assumes that the response to a Setup transaction will be an OUT transaction, and any subsequent packet (if any) will be an IN transaction. This appears to be valid in many cases; both USB enumeration and Mass Storage work OK with this restriction. However, DFU uses ep0 to transfer data in both directions. This renders the assumption invalid; when sending data from device to host, the Data Stage is an IN transaction, and the Status Stage is an OUT transaction. Enhance handle_setup() to deduce the correct direction for the USB transactions based on Setup transaction data. ep0's request object only needs to be automatically re-queued when the Data Stage completes, in order to implement the Status Stage. Once the Status Stage transaction is complete, there is no need to re-queue the USB request, so don't do that. Don't sent USB request completion callbacks for Status Stage transactions. These were queued by ci_udc itself, and only serve to confuse the USB function code. For example, f_dfu attempts to interpret the 0-length data buffers for Status Stage transactions as DFU packets. These buffers contain stale data from the previous transaction. This causes f_dfu to complain about a sequence number mismatch. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 48 ++++++++++++++++++++++++++++++++++++++------- drivers/usb/gadget/ci_udc.h | 1 + 2 files changed, 42 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 03ad23164fe..6dc20c6c954 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -428,6 +428,17 @@ static int ci_ep_queue(struct usb_ep *ep, return 0; } +static void flip_ep0_direction(void) +{ + if (ep0_desc.bEndpointAddress == USB_DIR_IN) { + DBG("%s: Flipping ep0 ot OUT\n", __func__); + ep0_desc.bEndpointAddress = 0; + } else { + DBG("%s: Flipping ep0 ot IN\n", __func__); + ep0_desc.bEndpointAddress = USB_DIR_IN; + } +} + static void handle_ep_complete(struct ci_ep *ep) { struct ept_queue_item *item; @@ -436,8 +447,6 @@ static void handle_ep_complete(struct ci_ep *ep) num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; - if (num == 0) - ep0_desc.bEndpointAddress = 0; item = ci_get_qtd(num, in); ci_invalidate_qtd(num); @@ -458,11 +467,18 @@ static void handle_ep_complete(struct ci_ep *ep) DBG("ept%d %s req %p, complete %x\n", num, in ? "in" : "out", ci_req, len); - ci_req->req.complete(&ep->ep, &ci_req->req); - if (num == 0) { + if (num != 0 || controller.ep0_data_phase) + ci_req->req.complete(&ep->ep, &ci_req->req); + if (num == 0 && controller.ep0_data_phase) { + /* + * Data Stage is complete, so flip ep0 dir for Status Stage, + * which always transfers a packet in the opposite direction. + */ + DBG("%s: flip ep0 dir for Status Stage\n", __func__); + flip_ep0_direction(); + controller.ep0_data_phase = false; ci_req->req.length = 0; usb_ep_queue(&ep->ep, &ci_req->req, 0); - ep0_desc.bEndpointAddress = USB_DIR_IN; } } @@ -491,8 +507,26 @@ static void handle_setup(void) #else writel(EPT_RX(0), &udc->epstat); #endif - DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), - r.bRequestType, r.bRequest, r.wIndex, r.wValue); + DBG("handle setup %s, %x, %x index %x value %x length %x\n", + reqname(r.bRequest), r.bRequestType, r.bRequest, r.wIndex, + r.wValue, r.wLength); + + /* Set EP0 dir for Data Stage based on Setup Stage data */ + if (r.bRequestType & USB_DIR_IN) { + DBG("%s: Set ep0 to IN for Data Stage\n", __func__); + ep0_desc.bEndpointAddress = USB_DIR_IN; + } else { + DBG("%s: Set ep0 to OUT for Data Stage\n", __func__); + ep0_desc.bEndpointAddress = 0; + } + if (r.wLength) { + controller.ep0_data_phase = true; + } else { + /* 0 length -> no Data Stage. Flip dir for Status Stage */ + DBG("%s: 0 length: flip ep0 dir for Status Stage\n", __func__); + flip_ep0_direction(); + controller.ep0_data_phase = false; + } list_del_init(&ci_req->queue); ci_ep->req_primed = false; diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h index 7d76af84f03..c2144021e67 100644 --- a/drivers/usb/gadget/ci_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -98,6 +98,7 @@ struct ci_ep { struct ci_drv { struct usb_gadget gadget; struct ci_req *ep0_req; + bool ep0_data_phase; struct usb_gadget_driver *driver; struct ehci_ctrl *ctrl; struct ept_queue_head *epts; -- cgit v1.3.1 From 08be2836df0b07aac65fea583b762335569fd47a Mon Sep 17 00:00:00 2001 From: "Cormier, Jonathan" Date: Wed, 21 May 2014 13:08:52 -0400 Subject: phy: fix create_phy_by_mask for when its given an actual search mask get_phy_id returns -EIO when it can't read from a phy at a given addr. This would cause create_phy_by_mask to return prematurely before it had tested the other addresses in the provided mask. Example usage: Replace phydev = phy_connect(bus, phy_addr, dev, phy_if) with phydev = phy_find_by_mask(bus, phy_mask, phy_if) if (phydev) phy_connect_dev(phydev, dev); Signed-off-by: Cormier, Jonathan Cc: Joe Hershberger --- drivers/net/phy/phy.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 230ed97dd12..aac85c4d092 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -609,10 +609,8 @@ static struct phy_device *create_phy_by_mask(struct mii_dev *bus, while (phy_mask) { int addr = ffs(phy_mask) - 1; int r = get_phy_id(bus, addr, devad, &phy_id); - if (r < 0) - return ERR_PTR(r); /* If the PHY ID is mostly f's, we didn't find anything */ - if ((phy_id & 0x1fffffff) != 0x1fffffff) + if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff) return phy_device_create(bus, addr, phy_id, interface); phy_mask &= ~(1 << addr); } -- cgit v1.3.1 From afb907061a0a2175c840e8bfc3ad04fd2d6721ed Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 21 May 2014 10:25:10 +0800 Subject: powerpc/espi: remove 80us delay to improve transfer performance Replace 80 mircoseconds delay with polling flag ESPI_EV_TXE. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- drivers/spi/fsl_espi.c | 138 +++++++++++++++++++++++++++++++++++++------------ 1 file changed, 106 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 7c845827627..ae0fe58f2c0 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -15,8 +15,10 @@ struct fsl_spi_slave { struct spi_slave slave; + ccsr_espi_t *espi; unsigned int div16; unsigned int pm; + int tx_timeout; unsigned int mode; size_t cmd_len; u8 cmd_buf[16]; @@ -25,11 +27,17 @@ struct fsl_spi_slave { }; #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) +#define US_PER_SECOND 1000000UL #define ESPI_MAX_CS_NUM 4 +#define ESPI_FIFO_WIDTH_BIT 32 #define ESPI_EV_RNE (1 << 9) #define ESPI_EV_TNF (1 << 8) +#define ESPI_EV_DON (1 << 14) +#define ESPI_EV_TXE (1 << 15) +#define ESPI_EV_RFCNT_SHIFT 24 +#define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT) #define ESPI_MODE_EN (1 << 31) /* Enable interface */ #define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ @@ -61,6 +69,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, struct fsl_spi_slave *fsl; sys_info_t sysinfo; unsigned long spibrg = 0; + unsigned long spi_freq = 0; unsigned char pm = 0; if (!spi_cs_is_valid(bus, cs)) @@ -70,6 +79,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!fsl) return NULL; + fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); fsl->mode = mode; fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; @@ -91,6 +101,15 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, pm--; fsl->pm = pm; + if (fsl->div16) + spi_freq = spibrg / ((pm + 1) * 2 * 16); + else + spi_freq = spibrg / ((pm + 1) * 2); + + /* set tx_timeout to 10 times of one espi FIFO entry go out */ + fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT + * 10), spi_freq); + return &fsl->slave; } @@ -108,7 +127,7 @@ void spi_init(void) int spi_claim_bus(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + ccsr_espi_t *espi = fsl->espi; unsigned char pm = fsl->pm; unsigned int cs = slave->cs; unsigned int mode = fsl->mode; @@ -161,24 +180,86 @@ void spi_release_bus(struct spi_slave *slave) } +static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) +{ + ccsr_espi_t *espi = fsl->espi; + unsigned int tmpdout, event; + int tmp_tx_timeout; + + if (dout) + tmpdout = *(u32 *)dout; + else + tmpdout = 0; + + out_be32(&espi->tx, tmpdout); + out_be32(&espi->event, ESPI_EV_TNF); + debug("***spi_xfer:...%08x written\n", tmpdout); + + tmp_tx_timeout = fsl->tx_timeout; + /* Wait for eSPI transmit to go out */ + while (tmp_tx_timeout--) { + event = in_be32(&espi->event); + if (event & ESPI_EV_DON || event & ESPI_EV_TXE) { + out_be32(&espi->event, ESPI_EV_TXE); + break; + } + udelay(1); + } + + if (tmp_tx_timeout < 0) + debug("***spi_xfer:...Tx timeout! event = %08x\n", event); +} + +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) +{ + ccsr_espi_t *espi = fsl->espi; + unsigned int tmpdin, rx_times; + unsigned char *buf, *p_cursor; + + if (bytes <= 0) + return 0; + + rx_times = DIV_ROUND_UP(bytes, 4); + buf = (unsigned char *)malloc(4 * rx_times); + if (!buf) { + debug("SF: Failed to malloc memory.\n"); + return -1; + } + p_cursor = buf; + while (rx_times--) { + tmpdin = in_be32(&espi->rx); + debug("***spi_xfer:...%08x readed\n", tmpdin); + *(u32 *)p_cursor = tmpdin; + p_cursor += 4; + } + + if (din) + memcpy(din, buf, bytes); + + free(buf); + out_be32(&espi->event, ESPI_EV_RNE); + + return bytes; +} + int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, void *data_in, unsigned long flags) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); - unsigned int tmpdout, tmpdin, event; + ccsr_espi_t *espi = fsl->espi; + unsigned int event, rx_bytes; const void *dout = NULL; void *din = NULL; int len = 0; int num_blks, num_chunks, max_tran_len, tran_len; int num_bytes; - unsigned char *ch; unsigned char *buffer = NULL; size_t buf_len; u8 *cmd_buf = fsl->cmd_buf; size_t cmd_len = fsl->cmd_len; size_t data_len = bitlen / 8; size_t rx_offset = 0; + int rf_cnt; max_tran_len = fsl->max_transfer_length; switch (flags) { @@ -217,9 +298,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, break; } - debug("spi_xfer: slave %u:%u dout %08X(%p) din %08X(%p) len %u\n", - slave->bus, slave->cs, *(uint *) dout, - dout, *(uint *) din, din, len); + debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) len %u\n", + *(uint *)data_out, data_out, *(uint *)data_in, data_in, len); num_chunks = DIV_ROUND_UP(data_len, max_tran_len); while (num_chunks--) { @@ -235,41 +315,34 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, /* Clear all eSPI events */ out_be32(&espi->event , 0xffffffff); /* handle data in 32-bit chunks */ - while (num_blks--) { - + while (num_blks) { event = in_be32(&espi->event); if (event & ESPI_EV_TNF) { - tmpdout = *(u32 *)dout; - + fsl_espi_tx(fsl, dout); /* Set up the next iteration */ if (len > 4) { len -= 4; dout += 4; } - - out_be32(&espi->tx, tmpdout); - out_be32(&espi->event, ESPI_EV_TNF); - debug("***spi_xfer:...%08x written\n", tmpdout); } - /* Wait for eSPI transmit to get out */ - udelay(80); - event = in_be32(&espi->event); if (event & ESPI_EV_RNE) { - tmpdin = in_be32(&espi->rx); - if (num_blks == 0 && num_bytes != 0) { - ch = (unsigned char *)&tmpdin; - while (num_bytes--) - *(unsigned char *)din++ = *ch++; - } else { - *(u32 *) din = tmpdin; - din += 4; + rf_cnt = ((event & ESPI_EV_RFCNT_MASK) + >> ESPI_EV_RFCNT_SHIFT); + if (rf_cnt >= 4) + rx_bytes = 4; + else if (num_blks == 1 && rf_cnt == num_bytes) + rx_bytes = num_bytes; + else + continue; + if (fsl_espi_rx(fsl, din, rx_bytes) + == rx_bytes) { + num_blks--; + if (din) + din = (unsigned char *)din + + rx_bytes; } - - out_be32(&espi->event, in_be32(&espi->event) - | ESPI_EV_RNE); - debug("***spi_xfer:...%08x readed\n", tmpdin); } } if (data_in) { @@ -295,7 +368,7 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) void spi_cs_activate(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + ccsr_espi_t *espi = fsl->espi; unsigned int com = 0; size_t data_len = fsl->data_len; @@ -307,7 +380,8 @@ void spi_cs_activate(struct spi_slave *slave) void spi_cs_deactivate(struct spi_slave *slave) { - ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = fsl->espi; /* clear the RXCNT and TXCNT */ out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); -- cgit v1.3.1 From 9855b3beca648dabe4d86b06d36bf219ebd0732d Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 23 May 2014 13:15:00 -0700 Subject: powerpc/mpc85xx: Add workaround for DDR erratum A004508 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the DDR controller is initialized below a junction temperature of 0°C and then operated above a junction temperature of 65°C, the DDR controller may cause receive data errors, resulting ECC errors and/or corrupted data. This erratum applies to the following SoCs and their variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023, P2020. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 18 ++++++++++++++++++ drivers/ddr/fsl/ctrl_regs.c | 5 +++++ 3 files changed, 26 insertions(+) (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3d37a7614f9..f69c8348973 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -231,6 +231,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) puts("Work-around for Erratum NMG ETSEC129 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004508 + puts("Work-around for Erratum A004508 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 puts("Work-around for Erratum A004510 enabled\n"); #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 34fc8fb5347..c9fd2a554aa 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -38,6 +38,7 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8540) @@ -122,6 +123,7 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8572) @@ -132,6 +134,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1010) @@ -154,6 +157,7 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 @@ -171,6 +175,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1012 is single core version of P1021 */ @@ -188,6 +193,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1013 is single core version of P1022 */ @@ -202,6 +208,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1014) @@ -219,6 +226,7 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_A004508 /* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) @@ -234,6 +242,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1020) @@ -246,6 +255,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 @@ -264,6 +274,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 @@ -278,6 +289,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1023) @@ -293,6 +305,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 @@ -309,6 +322,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1025 is lower end variant of P1021 */ @@ -326,6 +340,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P2010 is single core version of P2020 */ @@ -338,6 +353,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P2020) @@ -353,8 +369,10 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 78e82bba3d4..dcf6287f663 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -2304,5 +2304,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, ddr->debug[2] = 0x00000400; ddr->debug[4] = 0xff800000; #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004508 + if ((ip_rev >= 0x40000) && (ip_rev < 0x40400)) + ddr->debug[2] |= 0x00000200; /* set bit 22 */ +#endif + return check_fsl_memctl_config_regs(ddr); } -- cgit v1.3.1 From 353527d527b78297571c05b8a1687c92d42f6d20 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 5 Jun 2014 12:32:15 -0700 Subject: driver/ddr/fsl: Fix printing unspecified module info for DDR4 The offset of module information is at 128, different from DDR3. Signed-off-by: York Sun --- drivers/ddr/fsl/interactive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index c9f86302d77..7fb418744e0 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -1579,7 +1579,7 @@ void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd) printf("%-3d-%3d: ", 128, 255); for (i = 128; i <= 255; i++) - printf("%02x", spd->mod_section.uc[i - 60]); + printf("%02x", spd->mod_section.uc[i - 128]); break; } -- cgit v1.3.1 From b98c5755c04eb5e15c614efefa7b9a2f3b0cd06c Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:29 +0530 Subject: mtd: nand: omap_elm: remove #include omap_gpmc.h There is no dependency of omap_elm.c on omap_gpmc.h Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- drivers/mtd/nand/omap_elm.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c index 47b1f1bfe27..4c65f3b6f5f 100644 --- a/drivers/mtd/nand/omap_elm.c +++ b/drivers/mtd/nand/omap_elm.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include -- cgit v1.3.1 From 41bbe4dd49a3825e024e874ee19c6527860a3f16 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:30 +0530 Subject: mtd: nand: omap_elm: use bch_type instead of nibble count to differentiate between BCH4/BCH8/BCH16 ELM hardware engine support ECC error detection for multiple ECC strengths like +------+------------------------+ |Type | ECC syndrome length | +------+------------------------+ |BCH4 | 6.5 bytes = 13 nibbles | |BCH8 | 13 byte = 26 nibbles | |BCH16 | 26 bytes = 52 nibbles | +------+------------------------+ Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles') to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type' Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- drivers/mtd/nand/omap_elm.c | 20 ++++++++------------ drivers/mtd/nand/omap_gpmc.c | 10 ++-------- include/linux/mtd/omap_elm.h | 2 +- 3 files changed, 11 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c index 4c65f3b6f5f..afa629a8135 100644 --- a/drivers/mtd/nand/omap_elm.c +++ b/drivers/mtd/nand/omap_elm.c @@ -24,14 +24,12 @@ struct elm *elm_cfg; /** - * elm_load_syndromes - Load BCH syndromes based on nibble selection + * elm_load_syndromes - Load BCH syndromes based on bch_type selection * @syndrome: BCH syndrome - * @nibbles: + * @bch_type: BCH4/BCH8/BCH16 * @poly: Syndrome Polynomial set to use - * - * Load BCH syndromes based on nibble selection */ -static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) +static void elm_load_syndromes(u8 *syndrome, enum bch_level bch_type, u8 poly) { u32 *ptr; u32 val; @@ -47,8 +45,7 @@ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) (syndrome[7] << 24); writel(val, ptr); - /* BCH 8-bit with 26 nibbles (4*8=32) */ - if (nibbles > 13) { + if (bch_type == BCH_8_BIT || bch_type == BCH_16_BIT) { /* reg 2 */ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2]; val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) | @@ -61,8 +58,7 @@ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) writel(val, ptr); } - /* BCH 16-bit with 52 nibbles (7*8=56) */ - if (nibbles > 26) { + if (bch_type == BCH_16_BIT) { /* reg 4 */ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4]; val = syndrome[16] | (syndrome[17] << 8) | @@ -86,7 +82,7 @@ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) /** * elm_check_errors - Check for BCH errors and return error locations * @syndrome: BCH syndrome - * @nibbles: + * @bch_type: BCH4/BCH8/BCH16 * @error_count: Returns number of errrors in the syndrome * @error_locations: Returns error locations (in decimal) in this array * @@ -94,14 +90,14 @@ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) * and locations in the array passed. Returns -1 if error is not correctable, * else returns 0 */ -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, +int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, u32 *error_locations) { u8 poly = ELM_DEFAULT_POLY; s8 i; u32 location_status; - elm_load_syndromes(syndrome, nibbles, poly); + elm_load_syndromes(syndrome, bch_type, poly); /* start processing */ writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index bf99b8e6759..e84bc7b060c 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -153,7 +153,6 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, struct nand_bch_priv { uint8_t mode; uint8_t type; - uint8_t nibbles; struct bch_control *control; enum omap_ecc ecc_scheme; }; @@ -163,11 +162,6 @@ struct nand_bch_priv { #define ECC_BCH8 1 #define ECC_BCH16 2 -/* BCH nibbles for diff bch levels */ -#define ECC_BCH4_NIBBLES 13 -#define ECC_BCH8_NIBBLES 26 -#define ECC_BCH16_NIBBLES 52 - /* * This can be a single instance cause all current users have only one NAND * with nearly the same setup (BCH8, some with ELM and others with sw BCH @@ -176,7 +170,6 @@ struct nand_bch_priv { */ static __maybe_unused struct nand_bch_priv bch_priv = { .type = ECC_BCH8, - .nibbles = ECC_BCH8_NIBBLES, .control = NULL }; @@ -383,7 +376,8 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, } /* use elm module to check for errors */ elm_config((enum bch_level)(bch->type)); - if (elm_check_error(calc_ecc, bch->nibbles, &error_count, error_loc)) { + if (elm_check_error(calc_ecc, (enum bch_level)bch->type, + &error_count, error_loc)) { printf("nand: error: uncorrectable ECC errors\n"); return -EINVAL; } diff --git a/include/linux/mtd/omap_elm.h b/include/linux/mtd/omap_elm.h index 45454eaf0f1..a6e9591d379 100644 --- a/include/linux/mtd/omap_elm.h +++ b/include/linux/mtd/omap_elm.h @@ -68,7 +68,7 @@ struct elm { struct location error_location[8]; /* 0x800 */ }; -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, +int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, u32 *error_locations); int elm_config(enum bch_level level); void elm_reset(void); -- cgit v1.3.1 From d21e77ff84019b17e180b27267b23f51e6d609fa Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:32 +0530 Subject: mtd: nand: omap_gpmc: remove unused members of 'struct nand_bch_priv' This patch prepares to refactor 'struct nand_bch_priv' -> 'struct omap_nand_info' And thus performs following clean-ups: - remove nand_bch_priv.type: use nand_bch_priv.ecc_scheme instead - remove nand_bch_priv.mode: Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- drivers/mtd/nand/omap_gpmc.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index e84bc7b060c..1972b0ecae6 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -151,17 +151,10 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, * Generic BCH interface */ struct nand_bch_priv { - uint8_t mode; - uint8_t type; struct bch_control *control; enum omap_ecc ecc_scheme; }; -/* bch types */ -#define ECC_BCH4 0 -#define ECC_BCH8 1 -#define ECC_BCH16 2 - /* * This can be a single instance cause all current users have only one NAND * with nearly the same setup (BCH8, some with ELM and others with sw BCH @@ -169,7 +162,6 @@ struct nand_bch_priv { * When some users with other BCH strength will exists this have to change! */ static __maybe_unused struct nand_bch_priv bch_priv = { - .type = ECC_BCH8, .control = NULL }; @@ -342,6 +334,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, uint32_t eccbytes = chip->ecc.bytes; uint32_t error_count = 0, error_max; uint32_t error_loc[8]; + enum bch_level bch_type; uint32_t i, ecc_flag = 0; uint8_t count, err = 0; uint32_t byte_pos, bit_pos; @@ -369,22 +362,22 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, */ switch (bch->ecc_scheme) { case OMAP_ECC_BCH8_CODE_HW: + bch_type = BCH_8_BIT; omap_reverse_list(calc_ecc, eccbytes - 1); break; default: return -EINVAL; } /* use elm module to check for errors */ - elm_config((enum bch_level)(bch->type)); - if (elm_check_error(calc_ecc, (enum bch_level)bch->type, - &error_count, error_loc)) { + elm_config(bch_type); + if (elm_check_error(calc_ecc, bch_type, &error_count, error_loc)) { printf("nand: error: uncorrectable ECC errors\n"); return -EINVAL; } /* correct bch error */ for (count = 0; count < error_count; count++) { - switch (bch->type) { - case ECC_BCH8: + switch (bch->ecc_scheme) { + case OMAP_ECC_BCH8_CODE_HW: /* 14th byte in ECC is reserved to match ROM layout */ error_max = SECTOR_BYTES + (eccbytes - 1); break; @@ -562,7 +555,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are * initialized in nand_scan_tail(), so just set ecc.mode */ bch_priv.control = NULL; - bch_priv.type = 0; nand->ecc.mode = NAND_ECC_SOFT; nand->ecc.layout = NULL; nand->ecc.size = 0; @@ -578,7 +570,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, return -EINVAL; } bch_priv.control = NULL; - bch_priv.type = 0; /* populate ecc specific fields */ memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); nand->ecc.mode = NAND_ECC_HW; @@ -617,7 +608,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, printf("nand: error: could not init_bch()\n"); return -ENODEV; } - bch_priv.type = ECC_BCH8; /* populate ecc specific fields */ memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); nand->ecc.mode = NAND_ECC_HW; @@ -659,7 +649,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, } /* intialize ELM for ECC error detection */ elm_init(); - bch_priv.type = ECC_BCH8; /* populate ecc specific fields */ memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); nand->ecc.mode = NAND_ECC_HW; -- cgit v1.3.1 From 9233279f8e33d1b3d21958d8afe10fbc3e46b3f2 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:33 +0530 Subject: mtd: nand: omap_gpmc: rename struct nand_bch_priv to struct omap_nand_info This patch renames 'struct nand_bch_priv' which currently holds private data only for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for all ECC schemes Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- drivers/mtd/nand/omap_gpmc.c | 58 ++++++++++++++++++++------------------------ 1 file changed, 26 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 1972b0ecae6..391a26858cd 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -148,9 +148,9 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, } /* - * Generic BCH interface + * Driver configurations */ -struct nand_bch_priv { +struct omap_nand_info { struct bch_control *control; enum omap_ecc ecc_scheme; }; @@ -161,7 +161,7 @@ struct nand_bch_priv { * library). * When some users with other BCH strength will exists this have to change! */ -static __maybe_unused struct nand_bch_priv bch_priv = { +static __maybe_unused struct omap_nand_info omap_nand_info = { .control = NULL }; @@ -191,7 +191,7 @@ __maybe_unused static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) { struct nand_chip *nand = mtd->priv; - struct nand_bch_priv *bch = nand->priv; + struct omap_nand_info *info = nand->priv; unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0; unsigned int ecc_algo = 0; unsigned int bch_type = 0; @@ -200,7 +200,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) u32 ecc_config_val = 0; /* configure GPMC for specific ecc-scheme */ - switch (bch->ecc_scheme) { + switch (info->ecc_scheme) { case OMAP_ECC_HAM1_CODE_SW: return; case OMAP_ECC_HAM1_CODE_HW: @@ -262,11 +262,11 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) { struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; + struct omap_nand_info *info = chip->priv; uint32_t *ptr, val = 0; int8_t i = 0, j; - switch (bch->ecc_scheme) { + switch (info->ecc_scheme) { case OMAP_ECC_HAM1_CODE_HW: val = readl(&gpmc_cfg->ecc1_result); ecc_code[0] = val & 0xFF; @@ -294,7 +294,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return -EINVAL; } /* ECC scheme specific syndrome customizations */ - switch (bch->ecc_scheme) { + switch (info->ecc_scheme) { case OMAP_ECC_HAM1_CODE_HW: break; #ifdef CONFIG_BCH @@ -330,7 +330,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc) { struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; + struct omap_nand_info *info = chip->priv; uint32_t eccbytes = chip->ecc.bytes; uint32_t error_count = 0, error_max; uint32_t error_loc[8]; @@ -360,7 +360,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, * while reading ECC result we read it in big endian. * Hence while loading to ELM we have rotate to get the right endian. */ - switch (bch->ecc_scheme) { + switch (info->ecc_scheme) { case OMAP_ECC_BCH8_CODE_HW: bch_type = BCH_8_BIT; omap_reverse_list(calc_ecc, eccbytes - 1); @@ -376,7 +376,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, } /* correct bch error */ for (count = 0; count < error_count; count++) { - switch (bch->ecc_scheme) { + switch (info->ecc_scheme) { case OMAP_ECC_BCH8_CODE_HW: /* 14th byte in ECC is reserved to match ROM layout */ error_max = SECTOR_BYTES + (eccbytes - 1); @@ -483,10 +483,10 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, /* cannot correct more than 8 errors */ unsigned int errloc[8]; struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *chip_priv = chip->priv; - struct bch_control *bch = chip_priv->control; + struct omap_nand_info *info = chip->priv; - count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc); + count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc, + NULL, errloc); if (count > 0) { /* correct errors */ for (i = 0; i < count; i++) { @@ -522,15 +522,11 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, static void __maybe_unused omap_free_bch(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *chip_priv = chip->priv; - struct bch_control *bch = NULL; + struct omap_nand_info *info = chip->priv; - if (chip_priv) - bch = chip_priv->control; - - if (bch) { - free_bch(bch); - chip_priv->control = NULL; + if (info->control) { + free_bch(info->control); + info->control = NULL; } } #endif /* CONFIG_BCH */ @@ -544,7 +540,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) */ static int omap_select_ecc_scheme(struct nand_chip *nand, enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { - struct nand_bch_priv *bch = nand->priv; + struct omap_nand_info *info = nand->priv; struct nand_ecclayout *ecclayout = &omap_ecclayout; int eccsteps = pagesize / SECTOR_BYTES; int i; @@ -554,11 +550,10 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n"); /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are * initialized in nand_scan_tail(), so just set ecc.mode */ - bch_priv.control = NULL; + info->control = NULL; nand->ecc.mode = NAND_ECC_SOFT; nand->ecc.layout = NULL; nand->ecc.size = 0; - bch->ecc_scheme = OMAP_ECC_HAM1_CODE_SW; break; case OMAP_ECC_HAM1_CODE_HW: @@ -569,7 +564,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, (3 * eccsteps) + BADBLOCK_MARKER_LENGTH)); return -EINVAL; } - bch_priv.control = NULL; + info->control = NULL; /* populate ecc specific fields */ memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); nand->ecc.mode = NAND_ECC_HW; @@ -590,7 +585,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - BADBLOCK_MARKER_LENGTH; - bch->ecc_scheme = OMAP_ECC_HAM1_CODE_HW; break; case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: @@ -603,8 +597,8 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, return -EINVAL; } /* check if BCH S/W library can be used for error detection */ - bch_priv.control = init_bch(13, 8, 0x201b); - if (!bch_priv.control) { + info->control = init_bch(13, 8, 0x201b); + if (!info->control) { printf("nand: error: could not init_bch()\n"); return -ENODEV; } @@ -631,7 +625,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - BADBLOCK_MARKER_LENGTH; - bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; break; #else printf("nand: error: CONFIG_BCH required for ECC\n"); @@ -649,6 +642,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, } /* intialize ELM for ECC error detection */ elm_init(); + info->control = NULL; /* populate ecc specific fields */ memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); nand->ecc.mode = NAND_ECC_HW; @@ -666,7 +660,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - BADBLOCK_MARKER_LENGTH; - bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW; break; #else printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); @@ -682,6 +675,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW) nand->ecc.layout = ecclayout; + info->ecc_scheme = ecc_scheme; return 0; } @@ -785,7 +779,7 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; - nand->priv = &bch_priv; + nand->priv = &omap_nand_info; nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; /* If we are 16 bit dev, our gpmc config tells us that */ -- cgit v1.3.1 From a09431da381ce8d1b4d48e1cbca5f2b4eea662f4 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:34 +0530 Subject: mtd: nand: omap_gpmc: minor cleanup of omap_correct_data_bch This patch tries to avoid some local pointer dereferences, by using common local variables in omap_correct_data_bch() Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- drivers/mtd/nand/omap_gpmc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 391a26858cd..2d893e1c6c9 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -331,7 +331,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, { struct nand_chip *chip = mtd->priv; struct omap_nand_info *info = chip->priv; - uint32_t eccbytes = chip->ecc.bytes; + struct nand_ecc_ctrl *ecc = &chip->ecc; uint32_t error_count = 0, error_max; uint32_t error_loc[8]; enum bch_level bch_type; @@ -340,7 +340,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, uint32_t byte_pos, bit_pos; /* check calculated ecc */ - for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) { + for (i = 0; i < ecc->bytes && !ecc_flag; i++) { if (calc_ecc[i] != 0x00) ecc_flag = 1; } @@ -349,7 +349,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, /* check for whether its a erased-page */ ecc_flag = 0; - for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) { + for (i = 0; i < ecc->bytes && !ecc_flag; i++) { if (read_ecc[i] != 0xff) ecc_flag = 1; } @@ -363,7 +363,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, switch (info->ecc_scheme) { case OMAP_ECC_BCH8_CODE_HW: bch_type = BCH_8_BIT; - omap_reverse_list(calc_ecc, eccbytes - 1); + omap_reverse_list(calc_ecc, ecc->bytes - 1); break; default: return -EINVAL; @@ -379,7 +379,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, switch (info->ecc_scheme) { case OMAP_ECC_BCH8_CODE_HW: /* 14th byte in ECC is reserved to match ROM layout */ - error_max = SECTOR_BYTES + (eccbytes - 1); + error_max = SECTOR_BYTES + (ecc->bytes - 1); break; default: return -EINVAL; -- cgit v1.3.1 From 3f990dc83bc3197b17bd847241671917826152cc Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:35 +0530 Subject: mtd: nand: omap: fix error-codes returned from omap-elm driver This patch omap-elm.c: replaces -ve integer value returned during errorneous condition, with proper error-codes. omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from omap-elm driver to upper layers Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- drivers/mtd/nand/omap_elm.c | 7 +++++-- drivers/mtd/nand/omap_gpmc.c | 8 ++++---- 2 files changed, 9 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c index afa629a8135..d963e6c07c5 100644 --- a/drivers/mtd/nand/omap_elm.c +++ b/drivers/mtd/nand/omap_elm.c @@ -19,6 +19,7 @@ #include #include +#define DRIVER_NAME "omap-elm" #define ELM_DEFAULT_POLY (0) struct elm *elm_cfg; @@ -113,8 +114,10 @@ int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, /* check if correctable */ location_status = readl(&elm_cfg->error_location[poly].location_status); - if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) - return -1; + if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) { + printf("%s: uncorrectable ECC errors\n", DRIVER_NAME); + return -EBADMSG; + } /* get error count */ *error_count = readl(&elm_cfg->error_location[poly].location_status) & diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 2d893e1c6c9..d2fedf9faca 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -370,10 +370,10 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, } /* use elm module to check for errors */ elm_config(bch_type); - if (elm_check_error(calc_ecc, bch_type, &error_count, error_loc)) { - printf("nand: error: uncorrectable ECC errors\n"); - return -EINVAL; - } + err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc); + if (err) + return err; + /* correct bch error */ for (count = 0; count < error_count; count++) { switch (info->ecc_scheme) { -- cgit v1.3.1 From b9ae609fdbb7f8149a13bb9c67006b7237cbf83e Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 6 May 2014 00:46:16 +0530 Subject: mtd: nand: don't use read_buf for 8-bit ONFI transfers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Porting below commit from linux-tree, preserving original authorship & commit log commit bd9c6e99b58255b9de1982711ac9487c9a2f18be Author: Brian Norris mtd: nand: don't use read_buf for 8-bit ONFI transfers Use a repeated read_byte() instead of read_buf(), since for x16 buswidth devices, we need to avoid the upper I/O[16:9] bits. See the following commit for reference: commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree) Author: Uwe Kleine-König Date: Thu Dec 5 22:22:04 2013 +0100 mtd: nand: don't use {read,write}_buf for 8-bit transfers Now, I think that all barriers to probing ONFI on x16 devices are removed, so remove the check from nand_flash_detect_onfi(). Signed-off-by: Pekon Gupta --- drivers/mtd/nand/nand_base.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 1ce55fde8b7..5d3232c634c 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2582,7 +2582,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, int *busw) { struct nand_onfi_params *p = &chip->onfi_params; - int i; + int i, j; int val; /* Try ONFI for unknown chip or LP */ @@ -2593,7 +2593,8 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); for (i = 0; i < 3; i++) { - chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); + for (j = 0; j < sizeof(*p); j++) + ((uint8_t *)p)[j] = chip->read_byte(mtd); if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == le16_to_cpu(p->crc)) { pr_info("ONFI param page %d valid\n", i); -- cgit v1.3.1 From 27ce9e4290b168a1241699d411678959aaf9649b Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 6 May 2014 00:46:17 +0530 Subject: mtd: nand: force NAND_CMD_READID onto 8-bit bus As per following Sections in ONFI Spec, NAND_CMD_READID should use only lower 8-bit for transfering command, address and data even on x16 NAND device. *Section: Target Initialization" "The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page." *Section: Bus Width Requirements* "When the host supports a 16-bit bus width, only data is transferred at the 16-bit width. All address and command line transfers shall use only the lower 8-bits of the data bus. During command transfers, the host may place any value on the upper 8-bits of the data bus. During address transfers, the host shall set the upper 8-bits of the data bus to 00h." Thus porting following commit from linux-kernel to ensure that column address is not altered to align to x16 bus when issuing NAND_CMD_READID command. commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7 mtd: nand: force NAND_CMD_READID onto 8-bit bus Author: Brian Norris (preserving authorship) The NAND command helpers tend to automatically shift the column address for x16 bus devices, since most commands expect a word address, not a byte address. The Read ID command, however, expects an 8-bit address (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or 0x20). This fixes the column address for a few drivers which imitate the nand_base defaults. Signed-off-by: Pekon Gupta --- drivers/mtd/nand/am335x_spl_bch.c | 2 +- drivers/mtd/nand/atmel_nand.c | 2 +- drivers/mtd/nand/nand_base.c | 6 ++++-- drivers/mtd/nand/nand_spl_simple.c | 2 +- include/linux/mtd/nand.h | 10 ++++++++++ 5 files changed, 17 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c index bd89b067d5b..ce65d8e12b1 100644 --- a/drivers/mtd/nand/am335x_spl_bch.c +++ b/drivers/mtd/nand/am335x_spl_bch.c @@ -55,7 +55,7 @@ static int nand_command(int block, int page, uint32_t offs, } /* Shift the offset from byte addressing to word addressing. */ - if (this->options & NAND_BUSWIDTH_16) + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) offs >>= 1; /* Set ALE and clear CLE to start address cycle */ diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index e1fc48fca4f..e73834d2ef1 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1195,7 +1195,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - if (this->options & NAND_BUSWIDTH_16) + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) offs >>= 1; hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE); diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 5d3232c634c..376976d5795 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -575,7 +575,8 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, /* Serially input address */ if (column != -1) { /* Adjust columns for 16 bit buswidth */ - if (chip->options & NAND_BUSWIDTH_16) + if ((chip->options & NAND_BUSWIDTH_16) && + !nand_opcode_8bits(command)) column >>= 1; chip->cmd_ctrl(mtd, column, ctrl); ctrl &= ~NAND_CTRL_CHANGE; @@ -668,7 +669,8 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command, /* Serially input address */ if (column != -1) { /* Adjust columns for 16 bit buswidth */ - if (chip->options & NAND_BUSWIDTH_16) + if ((chip->options & NAND_BUSWIDTH_16) && + !nand_opcode_8bits(command)) column >>= 1; chip->cmd_ctrl(mtd, column, ctrl); ctrl &= ~NAND_CTRL_CHANGE; diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c index cead4b506cf..700ca324e21 100644 --- a/drivers/mtd/nand/nand_spl_simple.c +++ b/drivers/mtd/nand/nand_spl_simple.c @@ -78,7 +78,7 @@ static int nand_command(int block, int page, uint32_t offs, } /* Shift the offset from byte addressing to word addressing. */ - if (this->options & NAND_BUSWIDTH_16) + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) offs >>= 1; /* Begin command latch cycle */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 05465655935..4be885823cf 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -719,4 +719,14 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) } #endif +/** + * Check if the opcode's address should be sent only on the lower 8 bits + * @command: opcode to check + */ +static inline int nand_opcode_8bits(unsigned int command) +{ + return command == NAND_CMD_READID; +} + + #endif /* __LINUX_MTD_NAND_H */ -- cgit v1.3.1 From b80a66033856cc89c62886ae3e5ba54a7faf31ae Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Tue, 6 May 2014 00:46:19 +0530 Subject: mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device bus-width GPMC controller needs to be configured based on bus-width of the NAND device connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI parameters is not possible in following situations: SPL: SPL NAND drivers does not support ONFI parameter reading. U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init() which is called before probing for devices, hence any ONFI parameter information is not available during GPMC initialization. Thus, OMAP NAND driver expected board developers to explicitely write GPMC configurations specific to NAND device attached on board in board files itself. But this was troublesome for board manufacturers as they need to dive into lengthy platform & SoC documents to find details of GPMC registers and appropriate configurations to get NAND device working. This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config hich indicates that connected NAND device has x16 bus-width. And then based on this config GPMC driver itself initializes itself based on NAND bus-width. This keeps board developers free from knowing GPMC controller specific internals. Signed-off-by: Pekon Gupta --- doc/README.nand | 18 ++++++++++++++++++ drivers/mtd/nand/omap_gpmc.c | 13 +++++++++---- include/configs/am3517_crane.h | 1 + include/configs/devkit8000.h | 1 + include/configs/dig297.h | 1 + include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm_common.h | 2 +- include/configs/omap3_igep00x0.h | 1 + include/configs/omap3_logic.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/omap3_zoom1.h | 1 + include/configs/tam3517-common.h | 1 + include/configs/tao3530.h | 1 + 13 files changed, 38 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/doc/README.nand b/doc/README.nand index b91f1985d18..2bc5b391f80 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -190,6 +190,24 @@ Configuration Options: This is used by SoC platforms which do not have built-in ELM hardware engine required for BCH ECC correction. + CONFIG_SYS_NAND_BUSWIDTH_16BIT + Indicates that NAND device has 16-bit wide data-bus. In absence of this + config, bus-width of NAND device is assumed to be either 8-bit and later + determined by reading ONFI params. + Above config is useful when NAND device's bus-width information cannot + be determined from on-chip ONFI params, like in following scenarios: + - SPL boot does not support reading of ONFI parameters. This is done to + keep SPL code foot-print small. + - In current U-Boot flow using nand_init(), driver initialization + happens in board_nand_init() which is called before any device probe + (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are + not available while configuring controller. So a static CONFIG_NAND_xx + is needed to know the device's bus-width in advance. + Some drivers using above config are: + drivers/mtd/nand/mxc_nand.c + drivers/mtd/nand/ndfc.c + drivers/mtd/nand/omap_gpmc.c + Platform specific options ========================= diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index d2fedf9faca..cdfa6bc1c9f 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -782,13 +782,18 @@ int board_nand_init(struct nand_chip *nand) nand->priv = &omap_nand_info; nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; - /* If we are 16 bit dev, our gpmc config tells us that */ - if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) - nand->options |= NAND_BUSWIDTH_16; - nand->chip_delay = 100; nand->ecc.layout = &omap_ecclayout; + /* configure driver and controller based on NAND device bus-width */ + gpmc_config = readl(&gpmc_cfg->cs[cs].config1); +#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT) + nand->options |= NAND_BUSWIDTH_16; + writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1); +#else + nand->options &= ~NAND_BUSWIDTH_16; + writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1); +#endif /* select ECC scheme */ #if defined(CONFIG_NAND_OMAP_ECCSCHEME) err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME, diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 4407b454dd1..ad4cbd88b89 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -329,6 +329,7 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 16a00ebe867..5308790fe6b 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -314,6 +314,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/dig297.h b/include/configs/dig297.h index af6f56bb348..ce205e9b3eb 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -138,6 +138,7 @@ * Board NAND Info. */ #define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 0a7df60f281..c02348354a0 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -295,6 +295,7 @@ #define CONFIG_SPL_OMAP3_ID_NAND /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 7f3424b4f0e..ae4ce63f67f 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -120,7 +120,7 @@ /* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 - +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 /* Timeout values (in ticks) */ #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index d56d5b00cc7..79daabd6bbf 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -187,6 +187,7 @@ /* NAND boot config */ #ifdef CONFIG_NAND +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 0d03c75ce30..8dcbba3c40d 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -141,6 +141,7 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 7b97be9ace1..1a136339493 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -206,6 +206,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 7c5540ff660..3efe4cf8157 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -98,6 +98,7 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 /* Environment information */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 3522c1a07a7..eda536b8661 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -249,6 +249,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* NAND boot config */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 9c04c23ab76..44719352878 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -141,6 +141,7 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 /* Environment information */ #define CONFIG_BOOTDELAY 3 -- cgit v1.3.1 From 46840f66caf564866d191886d2bd86742f982010 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Mon, 2 Jun 2014 17:14:42 +0530 Subject: mtd: nand: omap: add support for BCH16_ECC - NAND driver updates This patch add support for BCH16_ECC to omap_gpmc driver. *need to BCH16 ECC scheme* With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes Flash devices have become more suspectible to bit-flips. Thus stronger ECC schemes are required for protecting the data. But stronger ECC schemes have come with larger-sized ECC syndromes which require more space in OOB/Spare. This puts constrains like; (a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data. (b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page >= 26 * (page-size / 512) Signed-off-by: Pekon Gupta --- drivers/mtd/nand/omap_gpmc.c | 79 ++++++++++++++++++++++++++++++++++++++++++- include/linux/mtd/omap_gpmc.h | 8 +++++ 2 files changed, 86 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index cdfa6bc1c9f..1acf06b237c 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -224,6 +224,19 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) eccsize1 = 2; /* non-ECC bits in nibbles per sector */ } break; + case OMAP_ECC_BCH16_CODE_HW: + ecc_algo = 0x1; + bch_type = 0x2; + if (mode == NAND_ECC_WRITE) { + bch_wrapmode = 0x01; + eccsize0 = 0; /* extra bits in nibbles per sector */ + eccsize1 = 52; /* OOB bits in nibbles per sector */ + } else { + bch_wrapmode = 0x01; + eccsize0 = 52; /* ECC bits in nibbles per sector */ + eccsize1 = 0; /* non-ECC bits in nibbles per sector */ + } + break; default: return; } @@ -290,6 +303,29 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, ptr--; } break; + case OMAP_ECC_BCH16_CODE_HW: + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]); + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]); + ecc_code[i++] = (val >> 24) & 0xFF; + ecc_code[i++] = (val >> 16) & 0xFF; + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]); + ecc_code[i++] = (val >> 24) & 0xFF; + ecc_code[i++] = (val >> 16) & 0xFF; + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + for (j = 3; j >= 0; j--) { + val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j] + ); + ecc_code[i++] = (val >> 24) & 0xFF; + ecc_code[i++] = (val >> 16) & 0xFF; + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + } + break; default: return -EINVAL; } @@ -308,6 +344,8 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, case OMAP_ECC_BCH8_CODE_HW: ecc_code[chip->ecc.bytes - 1] = 0x00; break; + case OMAP_ECC_BCH16_CODE_HW: + break; default: return -EINVAL; } @@ -333,7 +371,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, struct omap_nand_info *info = chip->priv; struct nand_ecc_ctrl *ecc = &chip->ecc; uint32_t error_count = 0, error_max; - uint32_t error_loc[8]; + uint32_t error_loc[ELM_MAX_ERROR_COUNT]; enum bch_level bch_type; uint32_t i, ecc_flag = 0; uint8_t count, err = 0; @@ -365,6 +403,10 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, bch_type = BCH_8_BIT; omap_reverse_list(calc_ecc, ecc->bytes - 1); break; + case OMAP_ECC_BCH16_CODE_HW: + bch_type = BCH_16_BIT; + omap_reverse_list(calc_ecc, ecc->bytes); + break; default: return -EINVAL; } @@ -381,6 +423,9 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, /* 14th byte in ECC is reserved to match ROM layout */ error_max = SECTOR_BYTES + (ecc->bytes - 1); break; + case OMAP_ECC_BCH16_CODE_HW: + error_max = SECTOR_BYTES + ecc->bytes; + break; default: return -EINVAL; } @@ -666,6 +711,38 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, return -EINVAL; #endif + case OMAP_ECC_BCH16_CODE_HW: +#ifdef CONFIG_NAND_OMAP_ELM + debug("nand: using OMAP_ECC_BCH16_CODE_HW\n"); + /* check ecc-scheme requirements before updating ecc info */ + if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { + printf("nand: error: insufficient OOB: require=%d\n", ( + (26 * eccsteps) + BADBLOCK_MARKER_LENGTH)); + return -EINVAL; + } + /* intialize ELM for ECC error detection */ + elm_init(); + /* populate ecc specific fields */ + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = SECTOR_BYTES; + nand->ecc.bytes = 26; + nand->ecc.strength = 16; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data_bch; + nand->ecc.calculate = omap_calculate_ecc; + nand->ecc.read_page = omap_read_page_bch; + /* define ecc-layout */ + ecclayout->eccbytes = nand->ecc.bytes * eccsteps; + for (i = 0; i < ecclayout->eccbytes; i++) + ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes - + BADBLOCK_MARKER_LENGTH; + break; +#else + printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); + return -EINVAL; +#endif default: debug("nand: error: ecc scheme not enabled or supported\n"); return -EINVAL; diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h index d55fe328e64..9a8658257ff 100644 --- a/include/linux/mtd/omap_gpmc.h +++ b/include/linux/mtd/omap_gpmc.h @@ -27,6 +27,8 @@ enum omap_ecc { OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, /* 8-bit ECC calculation by GPMC, Error detection by ELM */ OMAP_ECC_BCH8_CODE_HW, + /* 16-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH16_CODE_HW, }; struct gpmc_cs { @@ -47,6 +49,10 @@ struct bch_res_0_3 { u32 bch_result_x[4]; }; +struct bch_res_4_6 { + u32 bch_result_x[3]; +}; + struct gpmc { u8 res1[0x10]; u32 sysconfig; /* 0x10 */ @@ -77,6 +83,8 @@ struct gpmc { u32 testmomde_ctrl; /* 0x230 */ u8 res8[12]; /* 0x234 */ struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */ + u8 res9[16 * 4]; /* 0x2C0 - 0x2FF */ + struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */ }; /* Used for board specific gpmc initialization */ -- cgit v1.3.1 From ce3cc8ecf52f798cc980a2c49bdc5cbca6b3be29 Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Mon, 19 May 2014 16:53:38 -0400 Subject: ti: qspi: populate slave device to set flash quad bit. The patch populates the slave data which will be used by flash driver to set the flash quad enable bit. Signed-off-by: Sourav Poddar --- drivers/spi/ti_qspi.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index c5d2245e446..fd7fea8df5b 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -106,6 +106,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) slave->memory_map = (void *)MMAP_START_ADDR_DRA; #else slave->memory_map = (void *)MMAP_START_ADDR_AM43x; + slave->op_mode_rx = 8; #endif memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | -- cgit v1.3.1 From 86db550b3864bcb3c9567fbdb67b49a244f5263e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 5 Jun 2014 11:15:29 -0400 Subject: power: Add support for the TPS65218 PMIC Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and may be used by TI AM335x SoCs. Signed-off-by: Tom Rini --- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65218.c | 97 ++++++++++++++++++++++++++++++++++++++ include/power/tps65218.h | 63 +++++++++++++++++++++++++ 3 files changed, 161 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps65218.c create mode 100644 include/power/tps65218.h (limited to 'drivers') diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 9a8bfe07b8e..a472f61f88f 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -13,4 +13,5 @@ obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o +obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c new file mode 100644 index 00000000000..09524563799 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65218.c @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/** + * tps65218_reg_write() - Generic function that can write a TPS65218 PMIC + * register or bit field regardless of protection + * level. + * + * @prot_level: Register password protection. Use + * TPS65218_PROT_LEVEL_NONE, + * TPS65218_PROT_LEVEL_1 or TPS65218_PROT_LEVEL_2 + * @dest_reg: Register address to write. + * @dest_val: Value to write. + * @mask: Bit mask (8 bits) to be applied. Function will only + * change bits that are set in the bit mask. + * + * @return: 0 for success, not 0 on failure, as per the i2c API + */ +int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask) +{ + uchar read_val; + uchar xor_reg; + int ret; + + /* + * If we are affecting only a bit field, read dest_reg and apply the + * mask + */ + if (mask != TPS65218_MASK_ALL_BITS) { + ret = i2c_read(TPS65218_CHIP_PM, dest_reg, 1, &read_val, 1); + if (ret) + return ret; + read_val &= (~mask); + read_val |= (dest_val & mask); + dest_val = read_val; + } + + if (prot_level > 0) { + xor_reg = dest_reg ^ TPS65218_PASSWORD_UNLOCK; + ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + } + + ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + + if (prot_level == TPS65218_PROT_LEVEL_2) { + ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + + ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + } + + return 0; +} + +/** + * tps65218_voltage_update() - Function to change a voltage level, as this + * is a multi-step process. + * @dc_cntrl_reg: DC voltage control register to change. + * @volt_sel: New value for the voltage register + * @return: 0 for success, not 0 on failure. + */ +int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) +{ + if ((dc_cntrl_reg != TPS65218_DCDC1) && + (dc_cntrl_reg != TPS65218_DCDC2)) + return 1; + + /* set voltage level */ + if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, dc_cntrl_reg, volt_sel, + TPS65218_MASK_ALL_BITS)) + return 1; + + /* set GO bit to initiate voltage transition */ + if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_SLEW, + TPS65218_DCDC_GO, TPS65218_DCDC_GO)) + return 1; + + return 0; +} diff --git a/include/power/tps65218.h b/include/power/tps65218.h new file mode 100644 index 00000000000..67aa2f8c8d4 --- /dev/null +++ b/include/power/tps65218.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2014 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __POWER_TPS65218_H__ +#define __POWER_TPS65218_H__ + +/* I2C chip address */ +#define TPS65218_CHIP_PM 0x24 + +/* Registers */ +enum { + TPS65218_CHIPID = 0x00, + TPS65218_INT1, + TPS65218_INT2, + TPS65218_INT_MASK1, + TPS65218_INT_MASK2, + TPS65218_STATUS, + TPS65218_CONTROL, + TPS65218_FLAG, + TPS65218_PASSWORD = 0x10, + TPS65218_ENABLE1, + TPS65218_ENABLE2, + TPS65218_CONFIG1, + TPS65218_CONFIG2, + TPS65218_CONFIG3, + TPS65218_DCDC1, + TPS65218_DCDC2, + TPS65218_DCDC3, + TPS65218_DCDC4, + TPS65218_SLEW, + TPS65218_LDO1, + TPS65218_SEQ1 = 0x20, + TPS65218_SEQ2, + TPS65218_SEQ3, + TPS65218_SEQ4, + TPS65218_SEQ5, + TPS65218_SEQ6, + TPS65218_SEQ7, + TPS65218_PMIC_NUM_OF_REGS, +}; + +#define TPS65218_PROT_LEVEL_NONE 0x00 +#define TPS65218_PROT_LEVEL_1 0x01 +#define TPS65218_PROT_LEVEL_2 0x02 + +#define TPS65218_PASSWORD_LOCK_FOR_WRITE 0x00 +#define TPS65218_PASSWORD_UNLOCK 0x7D + +#define TPS65218_DCDC_GO 0x80 + +#define TPS65218_MASK_ALL_BITS 0xFF + +#define TPS65218_DCDC_VOLT_SEL_1100MV 0x19 +#define TPS65218_DCDC_VOLT_SEL_1330MV 0x30 + +int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask); +int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); +#endif /* __POWER_TPS65218_H__ */ -- cgit v1.3.1 From 04728086088e2dcc37ae0512a521246b21389838 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 25 Apr 2014 15:47:13 +0200 Subject: sf: params: Added support for Spansion S25FL512S_512K Added support for Spansion chip "S25FL512S_512K". Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek Reviewed-by: Jagannadha Sutradharudu Teki --- drivers/mtd/spi/sf_params.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index eb372b75755..ac886fd071c 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -60,6 +60,7 @@ const struct spi_flash_params spi_flash_params_table[] = { {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP}, {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP}, {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP}, + {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP}, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0}, -- cgit v1.3.1 From c1c0dd2644d6bdd64f5d36528d801d14832f6394 Mon Sep 17 00:00:00 2001 From: Andrew Ruder Date: Thu, 24 Apr 2014 13:39:32 -0500 Subject: spi: soft_spi: Support NULL din/dout buffers This mirrors the conventions used in other SPI drivers (kirkwood, davinci, atmel, et al) where the din/dout buffer can be NULL when the received/transmitted data isn't important. This reduces the need for allocating additional buffers when write-only/read-only functionality is needed. In the din == NULL case, the received data is simply not stored. In the dout == NULL case, zeroes are transmitted. Signed-off-by: Andrew Ruder Cc: Jean-Christophe PLAGNIOL-VILLARD Reviewed-by: Jagannadha Sutradharudu Teki --- drivers/spi/soft_spi.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index 5d22351290b..c969be31eb3 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -136,10 +136,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, /* * Check if it is time to work on a new byte. */ - if((j % 8) == 0) { - tmpdout = *txd++; + if ((j % 8) == 0) { + if (txd) + tmpdout = *txd++; + else + tmpdout = 0; if(j != 0) { - *rxd++ = tmpdin; + if (rxd) + *rxd++ = tmpdin; } tmpdin = 0; } @@ -164,9 +168,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, * bits over to left-justify them. Then store the last byte * read in. */ - if((bitlen % 8) != 0) - tmpdin <<= 8 - (bitlen % 8); - *rxd++ = tmpdin; + if (rxd) { + if ((bitlen % 8) != 0) + tmpdin <<= 8 - (bitlen % 8); + *rxd++ = tmpdin; + } if (flags & SPI_XFER_END) spi_cs_deactivate(slave); -- cgit v1.3.1 From 1f436a6ddf7eb7f2da1c8df6c13100429baf844a Mon Sep 17 00:00:00 2001 From: "Poddar, Sourav" Date: Wed, 23 Apr 2014 18:57:03 +0530 Subject: sf: probe: Fix quad bit set path Currently, flash quad bit is set in "spi_flash_validate_params" and later at the end in the same api, we write 0 to status register for few flashes, thereby overriding the quad bit set. This fix moves the quad bit setting outside this api in "spi_flash_probe_slave" Signed-off-by: Sourav Poddar Reviewed-by: Jagannadha Sutradharudu Teki --- drivers/mtd/spi/sf_probe.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 0a46fe38da6..36ae5e0a773 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -197,16 +197,6 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, /* Go for default supported write cmd */ flash->write_cmd = CMD_PAGE_PROGRAM; - /* Set the quad enable bit - only for quad commands */ - if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || - (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || - (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { - if (spi_flash_set_qeb(flash, idcode[0])) { - debug("SF: Fail to set QEB for %02x\n", idcode[0]); - return NULL; - } - } - /* Read dummy_byte: dummy byte is determined based on the * dummy cycles of a particular command. * Fast commands - dummy_byte = dummy_cycles/8 @@ -327,6 +317,16 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi) if (!flash) goto err_read_id; + /* Set the quad enable bit - only for quad commands */ + if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || + (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || + (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { + if (spi_flash_set_qeb(flash, idcode[0])) { + debug("SF: Fail to set QEB for %02x\n", idcode[0]); + return NULL; + } + } + #ifdef CONFIG_OF_CONTROL if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { debug("SF: FDT decode error\n"); -- cgit v1.3.1 From 6b57ff6fd5111840dd4787f3d08596076e752676 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 6 May 2014 09:13:01 +0800 Subject: arm: vf610: Add QSPI driver support Add Freescale QSPI driver support for VF610. Signed-off-by: Alison Wang Signed-off-by: Chao Fu --- drivers/spi/Makefile | 1 + drivers/spi/fsl_qspi.c | 482 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/fsl_qspi.h | 127 +++++++++++++ 3 files changed, 610 insertions(+) create mode 100644 drivers/spi/fsl_qspi.c create mode 100644 drivers/spi/fsl_qspi.h (limited to 'drivers') diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 81b6af66949..b587308c849 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -40,3 +40,4 @@ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o +obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c new file mode 100644 index 00000000000..ba20beff4f9 --- /dev/null +++ b/drivers/spi/fsl_qspi.c @@ -0,0 +1,482 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * Freescale Quad Serial Peripheral Interface (QSPI) driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "fsl_qspi.h" + +#define RX_BUFFER_SIZE 0x80 +#define TX_BUFFER_SIZE 0x40 + +#define OFFSET_BITS_MASK 0x00ffffff + +#define FLASH_STATUS_WEL 0x02 + +/* SEQID */ +#define SEQID_WREN 1 +#define SEQID_FAST_READ 2 +#define SEQID_RDSR 3 +#define SEQID_SE 4 +#define SEQID_CHIP_ERASE 5 +#define SEQID_PP 6 +#define SEQID_RDID 7 + +/* Flash opcodes */ +#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ +#define OPCODE_RDSR 0x05 /* Read status register */ +#define OPCODE_WREN 0x06 /* Write enable */ +#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ +#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define OPCODE_RDID 0x9f /* Read JEDEC ID */ + +/* 4-byte address opcodes - used on Spansion and some Macronix flashes */ +#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ +#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */ +#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */ + +#ifdef CONFIG_SYS_FSL_QSPI_LE +#define qspi_read32 in_le32 +#define qspi_write32 out_le32 +#elif defined(CONFIG_SYS_FSL_QSPI_BE) +#define qspi_read32 in_be32 +#define qspi_write32 out_be32 +#endif + +static unsigned long spi_bases[] = { + QSPI0_BASE_ADDR, +}; + +static unsigned long amba_bases[] = { + QSPI0_AMBA_BASE, +}; + +struct fsl_qspi { + struct spi_slave slave; + unsigned long reg_base; + unsigned long amba_base; + u32 sf_addr; + u8 cur_seqid; +}; + +/* QSPI support swapping the flash read/write data + * in hardware for LS102xA, but not for VF610 */ +static inline u32 qspi_endian_xchg(u32 data) +{ +#ifdef CONFIG_VF610 + return swab32(data); +#else + return data; +#endif +} + +static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) +{ + return container_of(slave, struct fsl_qspi, slave); +} + +static void qspi_set_lut(struct fsl_qspi *qspi) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 lut_base; + + /* Unlock the LUT */ + qspi_write32(®s->lutkey, LUT_KEY_VALUE); + qspi_write32(®s->lckcr, QSPI_LCKCR_UNLOCK); + + /* Write Enable */ + lut_base = SEQID_WREN * 4; + qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_WREN) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + qspi_write32(®s->lut[lut_base + 1], 0); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* Fast Read */ + lut_base = SEQID_FAST_READ * 4; + if (FSL_QSPI_FLASH_SIZE <= SZ_16M) + qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_FAST_READ) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_FAST_READ_4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + qspi_write32(®s->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) | + INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) | + INSTR1(LUT_READ)); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* Read Status */ + lut_base = SEQID_RDSR * 4; + qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_RDSR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + qspi_write32(®s->lut[lut_base + 1], 0); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* Erase a sector */ + lut_base = SEQID_SE * 4; + if (FSL_QSPI_FLASH_SIZE <= SZ_16M) + qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_SE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_SE_4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + qspi_write32(®s->lut[lut_base + 1], 0); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* Erase the whole chip */ + lut_base = SEQID_CHIP_ERASE * 4; + qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_CHIP_ERASE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + qspi_write32(®s->lut[lut_base + 1], 0); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* Page Program */ + lut_base = SEQID_PP * 4; + if (FSL_QSPI_FLASH_SIZE <= SZ_16M) + qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_PP) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + else + qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_PP_4B) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + qspi_write32(®s->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) | + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* READ ID */ + lut_base = SEQID_RDID * 4; + qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_RDID) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + qspi_write32(®s->lut[lut_base + 1], 0); + qspi_write32(®s->lut[lut_base + 2], 0); + qspi_write32(®s->lut[lut_base + 3], 0); + + /* Lock the LUT */ + qspi_write32(®s->lutkey, LUT_KEY_VALUE); + qspi_write32(®s->lckcr, QSPI_LCKCR_LOCK); +} + +void spi_init() +{ + /* do nothing */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct fsl_qspi *qspi; + struct fsl_qspi_regs *regs; + u32 reg_val, smpr_val; + u32 total_size, seq_id; + + if (bus >= ARRAY_SIZE(spi_bases)) + return NULL; + + qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); + if (!qspi) + return NULL; + + qspi->reg_base = spi_bases[bus]; + qspi->amba_base = amba_bases[bus]; + + qspi->slave.max_write_size = TX_BUFFER_SIZE; + + regs = (struct fsl_qspi_regs *)qspi->reg_base; + qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); + + smpr_val = qspi_read32(®s->smpr); + qspi_write32(®s->smpr, smpr_val & ~(QSPI_SMPR_FSDLY_MASK | + QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK)); + qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK); + + total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; + qspi_write32(®s->sfa1ad, FSL_QSPI_FLASH_SIZE | qspi->amba_base); + qspi_write32(®s->sfa2ad, FSL_QSPI_FLASH_SIZE | qspi->amba_base); + qspi_write32(®s->sfb1ad, total_size | qspi->amba_base); + qspi_write32(®s->sfb2ad, total_size | qspi->amba_base); + + qspi_set_lut(qspi); + + smpr_val = qspi_read32(®s->smpr); + smpr_val &= ~QSPI_SMPR_DDRSMP_MASK; + qspi_write32(®s->smpr, smpr_val); + qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK); + + seq_id = 0; + reg_val = qspi_read32(®s->bfgencr); + reg_val &= ~QSPI_BFGENCR_SEQID_MASK; + reg_val |= (seq_id << QSPI_BFGENCR_SEQID_SHIFT); + reg_val &= ~QSPI_BFGENCR_PAR_EN_MASK; + qspi_write32(®s->bfgencr, reg_val); + + return &qspi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct fsl_qspi *qspi = to_qspi_spi(slave); + + free(qspi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf, u32 len) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg, rbsr_reg, data; + int i, size; + + mcr_reg = qspi_read32(®s->mcr); + qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + + qspi_write32(®s->sfar, qspi->amba_base); + + qspi_write32(®s->ipcr, (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + i = 0; + size = len; + while ((RX_BUFFER_SIZE >= size) && (size > 0)) { + rbsr_reg = qspi_read32(®s->rbsr); + if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) { + data = qspi_read32(®s->rbdr[i]); + data = qspi_endian_xchg(data); + memcpy(rxbuf, &data, 4); + rxbuf++; + size -= 4; + i++; + } + } + + qspi_write32(®s->mcr, mcr_reg); +} + +static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg, data; + int i, size; + u32 to_or_from; + + mcr_reg = qspi_read32(®s->mcr); + qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + + to_or_from = qspi->sf_addr + qspi->amba_base; + + while (len > 0) { + qspi_write32(®s->sfar, to_or_from); + + size = (len > RX_BUFFER_SIZE) ? + RX_BUFFER_SIZE : len; + + qspi_write32(®s->ipcr, + (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) | size); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + to_or_from += size; + len -= size; + + i = 0; + while ((RX_BUFFER_SIZE >= size) && (size > 0)) { + data = qspi_read32(®s->rbdr[i]); + data = qspi_endian_xchg(data); + memcpy(rxbuf, &data, 4); + rxbuf++; + size -= 4; + i++; + } + qspi_write32(®s->mcr, qspi_read32(®s->mcr) | + QSPI_MCR_CLR_RXF_MASK); + } + + qspi_write32(®s->mcr, mcr_reg); +} + +static void qspi_op_pp(struct fsl_qspi *qspi, u32 *txbuf, u32 len) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg, data, reg, status_reg; + int i, size, tx_size; + u32 to_or_from = 0; + + mcr_reg = qspi_read32(®s->mcr); + qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + + status_reg = 0; + while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) { + qspi_write32(®s->ipcr, + (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + qspi_write32(®s->ipcr, + (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + reg = qspi_read32(®s->rbsr); + if (reg & QSPI_RBSR_RDBFL_MASK) { + status_reg = qspi_read32(®s->rbdr[0]); + status_reg = qspi_endian_xchg(status_reg); + } + qspi_write32(®s->mcr, + qspi_read32(®s->mcr) | QSPI_MCR_CLR_RXF_MASK); + } + + to_or_from = qspi->sf_addr + qspi->amba_base; + qspi_write32(®s->sfar, to_or_from); + + tx_size = (len > TX_BUFFER_SIZE) ? + TX_BUFFER_SIZE : len; + + size = (tx_size + 3) / 4; + + for (i = 0; i < size; i++) { + data = qspi_endian_xchg(*txbuf); + qspi_write32(®s->tbdr, data); + txbuf++; + } + + qspi_write32(®s->ipcr, + (SEQID_PP << QSPI_IPCR_SEQID_SHIFT) | tx_size); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + qspi_write32(®s->mcr, mcr_reg); +} + +static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg, reg, data; + + mcr_reg = qspi_read32(®s->mcr); + qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + + qspi_write32(®s->sfar, qspi->amba_base); + + qspi_write32(®s->ipcr, + (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + while (1) { + reg = qspi_read32(®s->rbsr); + if (reg & QSPI_RBSR_RDBFL_MASK) { + data = qspi_read32(®s->rbdr[0]); + data = qspi_endian_xchg(data); + memcpy(rxbuf, &data, 4); + qspi_write32(®s->mcr, qspi_read32(®s->mcr) | + QSPI_MCR_CLR_RXF_MASK); + break; + } + } + + qspi_write32(®s->mcr, mcr_reg); +} + +static void qspi_op_se(struct fsl_qspi *qspi) +{ + struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; + u32 mcr_reg; + u32 to_or_from = 0; + + mcr_reg = qspi_read32(®s->mcr); + qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | + QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS); + + to_or_from = qspi->sf_addr + qspi->amba_base; + qspi_write32(®s->sfar, to_or_from); + + qspi_write32(®s->ipcr, + (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + qspi_write32(®s->ipcr, + (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0); + while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) + ; + + qspi_write32(®s->mcr, mcr_reg); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct fsl_qspi *qspi = to_qspi_spi(slave); + u32 bytes = DIV_ROUND_UP(bitlen, 8); + static u32 pp_sfaddr; + u32 txbuf; + + if (dout) { + memcpy(&txbuf, dout, 4); + qspi->cur_seqid = *(u8 *)dout; + + if (flags == SPI_XFER_END) { + qspi->sf_addr = pp_sfaddr; + qspi_op_pp(qspi, (u32 *)dout, bytes); + return 0; + } + + if (qspi->cur_seqid == OPCODE_FAST_READ) { + qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; + } else if (qspi->cur_seqid == OPCODE_SE) { + qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; + qspi_op_se(qspi); + } else if (qspi->cur_seqid == OPCODE_PP) { + pp_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; + } + } + + if (din) { + if (qspi->cur_seqid == OPCODE_FAST_READ) + qspi_op_read(qspi, din, bytes); + else if (qspi->cur_seqid == OPCODE_RDID) + qspi_op_rdid(qspi, din, bytes); + else if (qspi->cur_seqid == OPCODE_RDSR) + qspi_op_rdsr(qspi, din); + } + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Nothing to do */ +} diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h new file mode 100644 index 00000000000..db400e66b50 --- /dev/null +++ b/drivers/spi/fsl_qspi.h @@ -0,0 +1,127 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * Register definitions for Freescale QSPI + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_QSPI_H_ +#define _FSL_QSPI_H_ + +struct fsl_qspi_regs { + u32 mcr; + u32 rsvd0[1]; + u32 ipcr; + u32 flshcr; + u32 buf0cr; + u32 buf1cr; + u32 buf2cr; + u32 buf3cr; + u32 bfgencr; + u32 soccr; + u32 rsvd1[2]; + u32 buf0ind; + u32 buf1ind; + u32 buf2ind; + u32 rsvd2[49]; + u32 sfar; + u32 rsvd3[1]; + u32 smpr; + u32 rbsr; + u32 rbct; + u32 rsvd4[15]; + u32 tbsr; + u32 tbdr; + u32 rsvd5[1]; + u32 sr; + u32 fr; + u32 rser; + u32 spndst; + u32 sptrclr; + u32 rsvd6[4]; + u32 sfa1ad; + u32 sfa2ad; + u32 sfb1ad; + u32 sfb2ad; + u32 rsvd7[28]; + u32 rbdr[32]; + u32 rsvd8[32]; + u32 lutkey; + u32 lckcr; + u32 rsvd9[2]; + u32 lut[64]; +}; + +#define QSPI_IPCR_SEQID_SHIFT 24 +#define QSPI_IPCR_SEQID_MASK (0xf << QSPI_IPCR_SEQID_SHIFT) + +#define QSPI_MCR_END_CFD_SHIFT 2 +#define QSPI_MCR_END_CFD_MASK (3 << QSPI_MCR_END_CFD_SHIFT) +#define QSPI_MCR_END_CFD_LE (1 << QSPI_MCR_END_CFD_SHIFT) +#define QSPI_MCR_DDR_EN_SHIFT 7 +#define QSPI_MCR_DDR_EN_MASK (1 << QSPI_MCR_DDR_EN_SHIFT) +#define QSPI_MCR_CLR_RXF_SHIFT 10 +#define QSPI_MCR_CLR_RXF_MASK (1 << QSPI_MCR_CLR_RXF_SHIFT) +#define QSPI_MCR_CLR_TXF_SHIFT 11 +#define QSPI_MCR_CLR_TXF_MASK (1 << QSPI_MCR_CLR_TXF_SHIFT) +#define QSPI_MCR_MDIS_SHIFT 14 +#define QSPI_MCR_MDIS_MASK (1 << QSPI_MCR_MDIS_SHIFT) +#define QSPI_MCR_RESERVED_SHIFT 16 +#define QSPI_MCR_RESERVED_MASK (0xf << QSPI_MCR_RESERVED_SHIFT) + +#define QSPI_SMPR_HSENA_SHIFT 0 +#define QSPI_SMPR_HSENA_MASK (1 << QSPI_SMPR_HSENA_SHIFT) +#define QSPI_SMPR_FSPHS_SHIFT 5 +#define QSPI_SMPR_FSPHS_MASK (1 << QSPI_SMPR_FSPHS_SHIFT) +#define QSPI_SMPR_FSDLY_SHIFT 6 +#define QSPI_SMPR_FSDLY_MASK (1 << QSPI_SMPR_FSDLY_SHIFT) +#define QSPI_SMPR_DDRSMP_SHIFT 16 +#define QSPI_SMPR_DDRSMP_MASK (7 << QSPI_SMPR_DDRSMP_SHIFT) + +#define QSPI_BFGENCR_SEQID_SHIFT 12 +#define QSPI_BFGENCR_SEQID_MASK (0xf << QSPI_BFGENCR_SEQID_SHIFT) +#define QSPI_BFGENCR_PAR_EN_SHIFT 16 +#define QSPI_BFGENCR_PAR_EN_MASK (1 << QSPI_BFGENCR_PAR_EN_SHIFT) + +#define QSPI_RBSR_RDBFL_SHIFT 8 +#define QSPI_RBSR_RDBFL_MASK (0x3f << QSPI_RBSR_RDBFL_SHIFT) + +#define QSPI_RBCT_RXBRD_SHIFT 8 +#define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT) + +#define QSPI_SR_BUSY_SHIFT 0 +#define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT) + +#define QSPI_LCKCR_LOCK 0x1 +#define QSPI_LCKCR_UNLOCK 0x2 + +#define LUT_KEY_VALUE 0x5af05af0 + +#define OPRND0_SHIFT 0 +#define OPRND0(x) ((x) << OPRND0_SHIFT) +#define PAD0_SHIFT 8 +#define PAD0(x) ((x) << PAD0_SHIFT) +#define INSTR0_SHIFT 10 +#define INSTR0(x) ((x) << INSTR0_SHIFT) +#define OPRND1_SHIFT 16 +#define OPRND1(x) ((x) << OPRND1_SHIFT) +#define PAD1_SHIFT 24 +#define PAD1(x) ((x) << PAD1_SHIFT) +#define INSTR1_SHIFT 26 +#define INSTR1(x) ((x) << INSTR1_SHIFT) + +#define LUT_CMD 1 +#define LUT_ADDR 2 +#define LUT_DUMMY 3 +#define LUT_READ 7 +#define LUT_WRITE 8 + +#define LUT_PAD1 0 +#define LUT_PAD2 1 +#define LUT_PAD4 2 + +#define ADDR24BIT 0x18 +#define ADDR32BIT 0x20 + +#endif /* _FSL_QSPI_H_ */ -- cgit v1.3.1 From 62cbddc493e5f4c6c1e1ba62bdf36f3df4708a16 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 23 Jan 2014 07:52:18 +0900 Subject: net: sh-eth: Add support R7S72100 of rmobile The R7S72100 of ARM SoC that Renesas manufactured has one Ether port. This has the same IP SH-Ether. This patch adds support of the R7S72100 in SH-Ether. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- drivers/net/sh_eth.c | 10 ++++--- drivers/net/sh_eth.h | 81 +++++++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 77 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 5e132f2b537..0cb963f8dec 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -148,7 +148,7 @@ int sh_eth_recv(struct eth_device *dev) static int sh_eth_reset(struct sh_eth_dev *eth) { -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) int ret = 0, i; /* Start e-dmac transmitter and receiver */ @@ -218,7 +218,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the tx descriptor list. Must use physical addresses */ sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ @@ -288,7 +288,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the rx descriptor list */ sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); sh_eth_write(eth, RDFFR_RDLF, RDFFR); @@ -384,7 +384,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, 0, TFTR); sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); sh_eth_write(eth, RMCR_RST, RMCR); -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, 0, RPADIR); #endif sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); @@ -403,6 +403,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, RFLR_RFL_MIN, RFLR); #if defined(SH_ETH_TYPE_GETHER) sh_eth_write(eth, 0, PIPR); +#endif +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) sh_eth_write(eth, APR_AP, APR); sh_eth_write(eth, MPR_MP, MPR); sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 331c07cb596..09257590fdb 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -230,6 +230,61 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { [RMII_MII] = 0x0790, }; +#if defined(SH_ETH_TYPE_RZ) +static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = { + [EDSR] = 0x0000, + [EDMR] = 0x0400, + [EDTRR] = 0x0408, + [EDRRR] = 0x0410, + [EESR] = 0x0428, + [EESIPR] = 0x0430, + [TDLAR] = 0x0010, + [TDFAR] = 0x0014, + [TDFXR] = 0x0018, + [TDFFR] = 0x001c, + [RDLAR] = 0x0030, + [RDFAR] = 0x0034, + [RDFXR] = 0x0038, + [RDFFR] = 0x003c, + [TRSCER] = 0x0438, + [RMFCR] = 0x0440, + [TFTR] = 0x0448, + [FDR] = 0x0450, + [RMCR] = 0x0458, + [RPADIR] = 0x0460, + [FCFTR] = 0x0468, + [CSMR] = 0x04E4, + + [ECMR] = 0x0500, + [ECSR] = 0x0510, + [ECSIPR] = 0x0518, + [PSR] = 0x0528, + [PIPR] = 0x052c, + [RFLR] = 0x0508, + [APR] = 0x0554, + [MPR] = 0x0558, + [PFTCR] = 0x055c, + [PFRCR] = 0x0560, + [TPAUSER] = 0x0564, + [GECMR] = 0x05b0, + [BCULR] = 0x05b4, + [MAHR] = 0x05c0, + [MALR] = 0x05c8, + [TROCR] = 0x0700, + [CDCR] = 0x0708, + [LCCR] = 0x0710, + [CEFCR] = 0x0740, + [FRECR] = 0x0748, + [TSFRCR] = 0x0750, + [TLFRCR] = 0x0758, + [RFCR] = 0x0760, + [CERCR] = 0x0768, + [CEECR] = 0x0770, + [MAFCR] = 0x0778, + [RMII_MII] = 0x0790, +}; +#endif + static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { [ECMR] = 0x0100, [RFLR] = 0x0108, @@ -306,13 +361,16 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) #define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xEE700200 +#elif defined(CONFIG_R7S72100) +#define SH_ETH_TYPE_RZ +#define BASE_IO_ADDR 0xE8203000 #endif /* * Register's bits * Copy from Linux driver source code */ -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) /* EDSR */ enum EDSR_BIT { EDSR_ENT = 0x01, EDSR_ENR = 0x02, @@ -323,7 +381,7 @@ enum EDSR_BIT { /* EDMR */ enum DMAC_M_BIT { EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) EDMR_SRST = 0x03, /* Receive/Send reset */ EMDR_DESC_R = 0x30, /* Descriptor reserve size */ EDMR_EL = 0x40, /* Litte endian */ @@ -349,7 +407,7 @@ enum DMAC_M_BIT { /* EDTRR */ enum DMAC_T_BIT { -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) EDTRR_TRNS = 0x03, #else EDTRR_TRNS = 0x01, @@ -424,7 +482,7 @@ enum EESR_BIT { }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define TX_CHECK (EESR_TC1 | EESR_FTC) # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) @@ -484,7 +542,8 @@ enum FCFTR_BIT { /* Transfer descriptor bit */ enum TD_STS_BIT { -#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \ + defined(SH_ETH_TYPE_RZ) TD_TACT = 0x80000000, #else TD_TACT = 0x7fffffff, @@ -500,7 +559,7 @@ enum TD_STS_BIT { enum RECV_RST_BIT { RMCR_RST = 0x01, }; /* ECMR */ enum FELIC_MODE_BIT { -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, ECMR_RZPF = 0x00100000, #endif @@ -517,7 +576,7 @@ enum FELIC_MODE_BIT { }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ ECMR_TXF | ECMR_MCT) #elif defined(SH_ETH_TYPE_ETHER) @@ -535,7 +594,7 @@ enum ECSR_STATUS_BIT { ECSR_MPD = 0x02, ECSR_ICD = 0x01, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) #else # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ @@ -556,7 +615,7 @@ enum ECSIPR_STATUS_MASK_BIT { ECSIPR_ICDIP = 0x01, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) #else # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ @@ -587,7 +646,7 @@ enum RPADIR_BIT { RPADIR_PADR = 0x0003f, }; -#if defined(SH_ETH_TYPE_GETHER) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define RPADIR_INIT (0x00) #else # define RPADIR_INIT (RPADIR_PADS1) @@ -605,6 +664,8 @@ static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, const u16 *reg_offset = sh_eth_offset_gigabit; #elif defined(SH_ETH_TYPE_ETHER) const u16 *reg_offset = sh_eth_offset_fast_sh4; +#elif defined(SH_ETH_TYPE_RZ) + const u16 *reg_offset = sh_eth_offset_rz; #else #error #endif -- cgit v1.3.1 From e2752db0520541d6c62401eb4acfc738c5d0b9db Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 23 Jan 2014 07:52:19 +0900 Subject: net: sh-eth: Fix coding style This fixes checkpatch's warning. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- drivers/net/sh_eth.c | 35 ++++++++++++++++++----------------- drivers/net/sh_eth.h | 9 ++++----- 2 files changed, 22 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 0cb963f8dec..81e8ddbbc7e 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -67,7 +67,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len) /* packet must be a 4 byte boundary */ if ((int)packet & 3) { - printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__); + printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n" + , __func__); ret = -EFAULT; goto err; } @@ -156,7 +157,7 @@ static int sh_eth_reset(struct sh_eth_dev *eth) /* Perform a software reset and wait for it to complete */ sh_eth_write(eth, EDMR_SRST, EDMR); - for (i = 0; i < TIMEOUT_CNT ; i++) { + for (i = 0; i < TIMEOUT_CNT; i++) { if (!(sh_eth_read(eth, EDMR) & EDMR_SRST)) break; udelay(1000); @@ -523,41 +524,41 @@ void sh_eth_halt(struct eth_device *dev) int sh_eth_initialize(bd_t *bd) { - int ret = 0; + int ret = 0; struct sh_eth_dev *eth = NULL; - struct eth_device *dev = NULL; + struct eth_device *dev = NULL; - eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); + eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); if (!eth) { printf(SHETHER_NAME ": %s: malloc failed\n", __func__); ret = -ENOMEM; goto err; } - dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (!dev) { printf(SHETHER_NAME ": %s: malloc failed\n", __func__); ret = -ENOMEM; goto err; } - memset(dev, 0, sizeof(struct eth_device)); - memset(eth, 0, sizeof(struct sh_eth_dev)); + memset(dev, 0, sizeof(struct eth_device)); + memset(eth, 0, sizeof(struct sh_eth_dev)); eth->port = CONFIG_SH_ETHER_USE_PORT; eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; - dev->priv = (void *)eth; - dev->iobase = 0; - dev->init = sh_eth_init; - dev->halt = sh_eth_halt; - dev->send = sh_eth_send; - dev->recv = sh_eth_recv; - eth->port_info[eth->port].dev = dev; + dev->priv = (void *)eth; + dev->iobase = 0; + dev->init = sh_eth_init; + dev->halt = sh_eth_halt; + dev->send = sh_eth_send; + dev->recv = sh_eth_recv; + eth->port_info[eth->port].dev = dev; sprintf(dev->name, SHETHER_NAME); - /* Register Device to EtherNet subsystem */ - eth_register(dev); + /* Register Device to EtherNet subsystem */ + eth_register(dev); bb_miiphy_buses[0].priv = eth; miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 09257590fdb..2909659fd59 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -452,7 +452,6 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; /* EESR */ enum EESR_BIT { - #if defined(SH_ETH_TYPE_ETHER) EESR_TWB = 0x40000000, #else @@ -560,8 +559,8 @@ enum RECV_RST_BIT { RMCR_RST = 0x01, }; /* ECMR */ enum FELIC_MODE_BIT { #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) - ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, - ECMR_RZPF = 0x00100000, + ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000, + ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, #endif ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, @@ -577,8 +576,8 @@ enum FELIC_MODE_BIT { }; #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) -#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ - ECMR_TXF | ECMR_MCT) +#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \ + ECMR_RXF | ECMR_TXF | ECMR_MCT) #elif defined(SH_ETH_TYPE_ETHER) #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) #else -- cgit v1.3.1 From 1dbd7280dc73dd4a6b38f3d17426393951d7d53e Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 23 Jan 2014 07:52:20 +0900 Subject: net: sh-eth: Fix typo from rESR_RTLF to EESR_RTLF 'r' of rESR_RTLF is a mistake of E. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- drivers/net/sh_eth.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 2909659fd59..d0d9aaa703d 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -476,7 +476,7 @@ enum EESR_BIT { EESR_CD = 0x00000200, EESR_RTO = 0x00000100, EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, - rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, + EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, }; -- cgit v1.3.1 From 43a8f25b6ca77894ddfd46c2b1196c7bd487561f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 10 Jun 2014 11:02:35 -0600 Subject: usb: ci_udc: call udc_disconnect() from ci_pullup() ci_pullup()'s !is_on path contains a cut/paste copy of udc_disconnect(). Remove the duplication by simply calling udc_disconnect() instead. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 6dc20c6c954..5f308563e24 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -697,6 +697,17 @@ int usb_gadget_handle_interrupts(void) return value; } +void udc_disconnect(void) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + /* disable pullup */ + stop_activity(); + writel(USBCMD_FS2, &udc->usbcmd); + udelay(800); + if (controller.driver) + controller.driver->disconnect(&controller.gadget); +} + static int ci_pullup(struct usb_gadget *gadget, int is_on) { struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; @@ -715,27 +726,12 @@ static int ci_pullup(struct usb_gadget *gadget, int is_on) /* Turn on the USB connection by enabling the pullup resistor */ writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd); } else { - stop_activity(); - writel(USBCMD_FS2, &udc->usbcmd); - udelay(800); - if (controller.driver) - controller.driver->disconnect(gadget); + udc_disconnect(); } return 0; } -void udc_disconnect(void) -{ - struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; - /* disable pullup */ - stop_activity(); - writel(USBCMD_FS2, &udc->usbcmd); - udelay(800); - if (controller.driver) - controller.driver->disconnect(&controller.gadget); -} - static int ci_udc_probe(void) { struct ept_queue_head *head; -- cgit v1.3.1 From bdf81611e444e8aef21cb05eeae69f694c0c7a39 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 10 Jun 2014 11:02:36 -0600 Subject: usb: ci_udc: fix freeing of ep0 req ci_ep_alloc_request() avoids allocating multiple request objects for ep0 by keeping a record of the first req allocated for ep0, and always returning that instead of allocating a new req. However, if this req is ever freed, the record of the previous allocation is not cleared, so ci_ep_alloc_request() will keep returning this stale pointer. Fix ci_ep_free_request() to clear the record of the previous allocation. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 5f308563e24..7a6563f83fd 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -221,9 +221,14 @@ ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req) { - struct ci_req *ci_req; + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + struct ci_req *ci_req = container_of(req, struct ci_req, req); + int num; + + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + if (num == 0) + controller.ep0_req = 0; - ci_req = container_of(req, struct ci_req, req); if (ci_req->b_buf) free(ci_req->b_buf); free(ci_req); -- cgit v1.3.1 From 9a7d34be13a6934e0fddfaf12236d8784343f902 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 10 Jun 2014 11:02:37 -0600 Subject: usb: ci_udc: fix probe error cleanup If allocation of the ep0 req fails, clean up all the allocations that were made in ci_udc_probe(). Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 7a6563f83fd..1428af85cff 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -826,6 +826,7 @@ static int ci_udc_probe(void) ci_ep_alloc_request(&controller.ep[0].ep, 0); if (!controller.ep0_req) { + free(controller.items_mem); free(controller.epts); return -ENOMEM; } -- cgit v1.3.1 From b7c0051687f42173e15b151a74e524587e8b59db Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 10 Jun 2014 11:02:38 -0600 Subject: usb: ci_udc: clean up all allocations in unregister usb_gadget_unregister_driver() is called to tear down the USB device mode stack. Fix the driver to stop the USB HW (which causes any attached host to notice the disappearance of the device), and free all allocations (which obviously prevents memory leaks). Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 1428af85cff..435a2720e96 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -875,5 +875,11 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) { + udc_disconnect(); + + ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req); + free(controller.items_mem); + free(controller.epts); + return 0; } -- cgit v1.3.1 From e0672b3c3ae4fdd48a66af9f7932d2c8e839e459 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 10 Jun 2014 15:27:39 -0600 Subject: usb: ci_udc: terminate ep0 INs with a zlp when required Sometimes, a zero-length packet is required at the end of an IN transaction so that the host knows the device is done sending data. Enhance ci_udc to send a zlp when necessary. See the comments for more details. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 38 +++++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 435a2720e96..b18bee43ad8 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -369,18 +369,50 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); len = ci_req->req.length; - item->next = TERMINATE; - item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; + item->info = INFO_BYTES(len) | INFO_ACTIVE; item->page0 = (uint32_t)ci_req->hw_buf; item->page1 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x1000; item->page2 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x2000; item->page3 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x3000; item->page4 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x4000; - ci_flush_qtd(num); head->next = (unsigned) item; head->info = 0; + /* + * When sending the data for an IN transaction, the attached host + * knows that all data for the IN is sent when one of the following + * occurs: + * a) A zero-length packet is transmitted. + * b) A packet with length that isn't an exact multiple of the ep's + * maxpacket is transmitted. + * c) Enough data is sent to exactly fill the host's maximum expected + * IN transaction size. + * + * One of these conditions MUST apply at the end of an IN transaction, + * or the transaction will not be considered complete by the host. If + * none of (a)..(c) already applies, then we must force (a) to apply + * by explicitly sending an extra zero-length packet. + */ + /* IN !a !b !c */ + if (in && len && !(len % ci_ep->ep.maxpacket) && ci_req->req.zero) { + /* + * Each endpoint has 2 items allocated, even though typically + * only 1 is used at a time since either an IN or an OUT but + * not both is queued. For an IN transaction, item currently + * points at the second of these items, so we know that we + * can use (item - 1) to transmit the extra zero-length packet + */ + item->next = (unsigned)(item - 1); + item--; + item->info = INFO_ACTIVE; + } + + item->next = TERMINATE; + item->info |= INFO_IOC; + + ci_flush_qtd(num); + DBG("ept%d %s queue len %x, req %p, buffer %p\n", num, in ? "in" : "out", len, ci_req, ci_req->hw_buf); ci_flush_qh(num); -- cgit v1.3.1 From 3d83e6752d5595351a47309aab0749984c5909b7 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 10 Jun 2014 12:25:59 +0200 Subject: dfu: Disable default calculation of CRC32 Patch (SHA1: bd694244db7bc969954) dfu: Introduction of the "dfu_hash_algo" env variable for checksum method setting already introduced more generic handling of the crc32 calculation. Up till now the CRC32 of received data was calculated unconditionally. This patch changes this and from now - by default the crc32 is NOT calculated anymore. Signed-off-by: Lukasz Majewski Cc: Marek Vasut --- drivers/dfu/dfu.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 5878f991d92..dc09ff6466e 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -106,21 +106,15 @@ static char *dfu_get_hash_algo(void) char *s; s = getenv("dfu_hash_algo"); - /* - * By default the legacy behaviour to calculate the crc32 hash - * value is preserved. - * - * To disable calculation of the hash algorithm for received data - * specify the "dfu_hash_algo = disabled" at your board envs. - */ - debug("%s: DFU hash method: %s\n", __func__, s ? s : "not specified"); - - if (!s || !strcmp(s, "crc32")) - return "crc32"; - - if (!strcmp(s, "disabled")) + if (!s) return NULL; + if (!strcmp(s, "crc32")) { + debug("%s: DFU hash method: %s\n", __func__, s); + return s; + } + + error("DFU hash method: %s not supported!\n", s); return NULL; } -- cgit v1.3.1 From ddc94378db9fe0c9076512768b3576e0fdc580dd Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 7 Jun 2014 22:07:58 -0600 Subject: m68k: Fix warnings with gcc 4.6 Most of the warnings seem to be related to using 'int' for size_t. Change this and fix up the remaining warnings and problems. For bootm, the warning was masked by others, and there is an actual bug in the code. Signed-off-by: Simon Glass --- arch/m68k/cpu/mcf532x/cpu_init.c | 2 +- arch/m68k/include/asm/posix_types.h | 2 +- arch/m68k/lib/bootm.c | 7 ++----- board/astro/mcf5373l/fpga.c | 2 +- board/astro/mcf5373l/mcf5373l.c | 2 +- drivers/fpga/altera.c | 6 +++--- drivers/fpga/xilinx.c | 6 +++--- 7 files changed, 12 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c index db7ded4782b..8d01f5fcf0d 100644 --- a/arch/m68k/cpu/mcf532x/cpu_init.c +++ b/arch/m68k/cpu/mcf532x/cpu_init.c @@ -208,10 +208,10 @@ void cpu_init_f(void) scm2_t *scm2 = (scm2_t *) MMAP_SCM2; gpio_t *gpio = (gpio_t *) MMAP_GPIO; fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; +#ifndef CONFIG_WATCHDOG wdog_t *wdog = (wdog_t *) MMAP_WDOG; /* watchdog is enabled by default - disable the watchdog */ -#ifndef CONFIG_WATCHDOG out_be16(&wdog->cr, 0); #endif diff --git a/arch/m68k/include/asm/posix_types.h b/arch/m68k/include/asm/posix_types.h index 4fbc0405f74..b97d2674236 100644 --- a/arch/m68k/include/asm/posix_types.h +++ b/arch/m68k/include/asm/posix_types.h @@ -15,7 +15,7 @@ typedef long __kernel_off_t; typedef int __kernel_pid_t; typedef unsigned int __kernel_uid_t; typedef unsigned int __kernel_gid_t; -typedef unsigned int __kernel_size_t; +typedef unsigned long __kernel_size_t; typedef int __kernel_ssize_t; typedef long __kernel_ptrdiff_t; typedef long __kernel_time_t; diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c index 804e01dae68..fa9c4930814 100644 --- a/arch/m68k/lib/bootm.c +++ b/arch/m68k/lib/bootm.c @@ -50,11 +50,7 @@ void arch_lmb_reserve(struct lmb *lmb) int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) { - ulong rd_len; - ulong initrd_start, initrd_end; int ret; - - ulong cmd_start, cmd_end; bd_t *kbd; void (*kernel) (bd_t *, ulong, ulong, ulong, ulong); struct lmb *lmb = &images->lmb; @@ -96,7 +92,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima * sp+16: Start of command line string * sp+20: End of command line string */ - (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); + (*kernel)(kbd, images->initrd_start, images->initrd_end, + images->cmdline_start, images->cmdline_end); /* does not return */ error: return 1; diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index 1d044d96a56..d1110dfd6e7 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -100,7 +100,7 @@ int altera_done_fn(int cookie) * writing the complete buffer in one function is much faster, * then calling it for every bit */ -int altera_write_fn(void *buf, size_t len, int flush, int cookie) +int altera_write_fn(const void *buf, size_t len, int flush, int cookie) { size_t bytecount = 0; gpio_t *gpiop = (gpio_t *)MMAP_GPIO; diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c index daba32c9dc1..7ec7cb378f5 100644 --- a/board/astro/mcf5373l/mcf5373l.c +++ b/board/astro/mcf5373l/mcf5373l.c @@ -79,7 +79,7 @@ phys_size_t initdram(int board_type) * (Do not rely on the SDCS register(s) being set to 0x00000000 * during reset as stated in the data sheet.) */ - return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE, + return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000 - CONFIG_SYS_SDRAM_BASE); } diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index af189f4ef4c..6e34a8e56e9 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -153,9 +153,9 @@ int altera_info( Altera_desc *desc ) printf ("Unsupported interface type, %d\n", desc->iface); } - printf ("Device Size: \t%d bytes\n" - "Cookie: \t0x%x (%d)\n", - desc->size, desc->cookie, desc->cookie); + printf("Device Size: \t%zd bytes\n" + "Cookie: \t0x%x (%d)\n", + desc->size, desc->cookie, desc->cookie); if (desc->iface_fns) { printf ("Device Function Table @ 0x%p\n", desc->iface_fns); diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 3795c1aff6e..adb4b8cd25f 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -220,9 +220,9 @@ int xilinx_info(xilinx_desc *desc) printf ("Unsupported interface type, %d\n", desc->iface); } - printf ("Device Size: \t%d bytes\n" - "Cookie: \t0x%x (%d)\n", - desc->size, desc->cookie, desc->cookie); + printf("Device Size: \t%zd bytes\n" + "Cookie: \t0x%x (%d)\n", + desc->size, desc->cookie, desc->cookie); if (desc->name) printf("Device name: \t%s\n", desc->name); -- cgit v1.3.1 From 6736ec15c518d013263fa97fc48ca22a50753792 Mon Sep 17 00:00:00 2001 From: Steve Rae Date: Mon, 26 May 2014 12:33:29 -0700 Subject: i2c: kona: Resolve Kona I2C driver issue - "i2c mw" command hangs (with some compilers) Signed-off-by: Steve Rae --- drivers/i2c/kona_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c index 0b1715abf0d..5eab338cfc4 100644 --- a/drivers/i2c/kona_i2c.c +++ b/drivers/i2c/kona_i2c.c @@ -663,7 +663,7 @@ static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, int alen, uchar *buffer, int len) { - struct i2c_msg msg[0]; + struct i2c_msg msg[1]; unsigned char msgbuf0[64]; unsigned int i; struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); -- cgit v1.3.1 From d4622df34280830cfe0678f098d3d9f62e6b5d94 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 23 May 2014 12:47:06 -0600 Subject: mmc: return meaningful error codes from mmc_select_hwpart Rather than just returning -1 everywhere, try to return something meaningful from mmc_select_hwpart(). Note that most other MMC functions don't do this, including functions called from mmc_select_hwpart(), so I'm not sure how effective this will be. Still, it's one less place with hard-coded -1. Suggested-by: Pantelis Antoniou Signed-off-by: Stephen Warren Acked-by: Pantelis Antoniou --- drivers/mmc/mmc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 55c2c68cdb2..b5477b12711 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -564,19 +565,19 @@ int mmc_select_hwpart(int dev_num, int hwpart) int ret; if (!mmc) - return -1; + return -ENODEV; if (mmc->part_num == hwpart) return 0; if (mmc->part_config == MMCPART_NOAVAILABLE) { printf("Card doesn't support part_switch\n"); - return -1; + return -EMEDIUMTYPE; } ret = mmc_switch_part(dev_num, hwpart); if (ret) - return -1; + return ret; mmc->part_num = hwpart; -- cgit v1.3.1 From 3d6a5a4dfca25a202e356e4d63e89cdc6bd7255a Mon Sep 17 00:00:00 2001 From: Darwin Rambo Date: Mon, 26 May 2014 13:31:12 -0700 Subject: mmc: free allocated memory on initialization errors Cleanup to balance malloc/free calls. Signed-off-by: Darwin Rambo Reviewed-by: Steve Rae Acked-by: Pantelis Antoniou --- drivers/mmc/kona_sdhci.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/kona_sdhci.c b/drivers/mmc/kona_sdhci.c index 77e42c8afe8..f804f4c0dbf 100644 --- a/drivers/mmc/kona_sdhci.c +++ b/drivers/mmc/kona_sdhci.c @@ -113,16 +113,20 @@ int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks) __func__, dev_index); ret = -EINVAL; } - if (ret) + if (ret) { + free(host); return ret; + } host->name = "kona-sdhci"; host->ioaddr = reg_base; host->quirks = quirks; host->host_caps = MMC_MODE_HC; - if (init_kona_mmc_core(host)) + if (init_kona_mmc_core(host)) { + free(host); return -EINVAL; + } if (quirks & SDHCI_QUIRK_REG32_RW) host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; -- cgit v1.3.1 From ceef983bf9b687926b274ad0eee8aae5a1812c92 Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Mon, 26 May 2014 22:55:18 +0200 Subject: macb: make checkpatch clean MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This also renames the CONFIG_SYS_MACB_xx defines. They are used just local and therefore don't need the CONFIG_SYS_ prefix. Signed-off-by: Andreas Bießmann Reviewed-by: Josh Wu --- drivers/net/macb.c | 56 ++++++++++++++++++++++++++++-------------------------- 1 file changed, 29 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 781a272cff2..750331d0540 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -40,11 +40,11 @@ #include "macb.h" -#define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096 -#define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128) -#define CONFIG_SYS_MACB_TX_RING_SIZE 16 -#define CONFIG_SYS_MACB_TX_TIMEOUT 1000 -#define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000 +#define MACB_RX_BUFFER_SIZE 4096 +#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) +#define MACB_TX_RING_SIZE 16 +#define MACB_TX_TIMEOUT 1000 +#define MACB_AUTONEG_TIMEOUT 5000000 struct macb_dma_desc { u32 addr; @@ -170,7 +170,7 @@ int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) struct eth_device *dev = eth_get_dev_by_name(devname); struct macb_device *macb = to_macb(dev); - if ( macb->phy_addr != phy_adr ) + if (macb->phy_addr != phy_adr) return -1; arch_get_mdio_control(devname); @@ -184,7 +184,7 @@ int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) struct eth_device *dev = eth_get_dev_by_name(devname); struct macb_device *macb = to_macb(dev); - if ( macb->phy_addr != phy_adr ) + if (macb->phy_addr != phy_adr) return -1; arch_get_mdio_control(devname); @@ -208,11 +208,12 @@ static int macb_send(struct eth_device *netdev, void *packet, int length) ctrl = length & TXBUF_FRMLEN_MASK; ctrl |= TXBUF_FRAME_END; - if (tx_head == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) { + if (tx_head == (MACB_TX_RING_SIZE - 1)) { ctrl |= TXBUF_WRAP; macb->tx_head = 0; - } else + } else { macb->tx_head++; + } macb->tx_ring[tx_head].ctrl = ctrl; macb->tx_ring[tx_head].addr = paddr; @@ -223,7 +224,7 @@ static int macb_send(struct eth_device *netdev, void *packet, int length) * I guess this is necessary because the networking core may * re-use the transmit buffer as soon as we return... */ - for (i = 0; i <= CONFIG_SYS_MACB_TX_TIMEOUT; i++) { + for (i = 0; i <= MACB_TX_TIMEOUT; i++) { barrier(); ctrl = macb->tx_ring[tx_head].ctrl; if (ctrl & TXBUF_USED) @@ -233,7 +234,7 @@ static int macb_send(struct eth_device *netdev, void *packet, int length) dma_unmap_single(packet, length, paddr); - if (i <= CONFIG_SYS_MACB_TX_TIMEOUT) { + if (i <= MACB_TX_TIMEOUT) { if (ctrl & TXBUF_UNDERRUN) printf("%s: TX underrun\n", netdev->name); if (ctrl & TXBUF_EXHAUSTED) @@ -256,7 +257,7 @@ static void reclaim_rx_buffers(struct macb_device *macb, while (i > new_tail) { macb->rx_ring[i].addr &= ~RXADDR_USED; i++; - if (i > CONFIG_SYS_MACB_RX_RING_SIZE) + if (i > MACB_RX_RING_SIZE) i = 0; } @@ -295,7 +296,7 @@ static int macb_recv(struct eth_device *netdev) if (wrapped) { unsigned int headlen, taillen; - headlen = 128 * (CONFIG_SYS_MACB_RX_RING_SIZE + headlen = 128 * (MACB_RX_RING_SIZE - macb->rx_tail); taillen = length - headlen; memcpy((void *)NetRxPackets[0], @@ -306,11 +307,11 @@ static int macb_recv(struct eth_device *netdev) } NetReceive(buffer, length); - if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) + if (++rx_tail >= MACB_RX_RING_SIZE) rx_tail = 0; reclaim_rx_buffers(macb, rx_tail); } else { - if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) { + if (++rx_tail >= MACB_RX_RING_SIZE) { wrapped = 1; rx_tail = 0; } @@ -333,7 +334,7 @@ static void macb_phy_reset(struct macb_device *macb) macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); - for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) { + for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { status = macb_mdio_read(macb, MII_BMSR); if (status & BMSR_ANEGCOMPLETE) break; @@ -385,9 +386,8 @@ static int macb_phy_init(struct macb_device *macb) arch_get_mdio_control(netdev->name); #ifdef CONFIG_MACB_SEARCH_PHY /* Auto-detect phy_addr */ - if (!macb_phy_find(macb)) { + if (!macb_phy_find(macb)) return 0; - } #endif /* CONFIG_MACB_SEARCH_PHY */ /* Check if the PHY is up to snuff... */ @@ -414,7 +414,7 @@ static int macb_phy_init(struct macb_device *macb) /* Try to re-negotiate if we don't have link already. */ macb_phy_reset(macb); - for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) { + for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { status = macb_mdio_read(macb, MII_BMSR); if (status & BMSR_LSTATUS) break; @@ -499,21 +499,23 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) /* initialize DMA descriptors */ paddr = macb->rx_buffer_dma; - for (i = 0; i < CONFIG_SYS_MACB_RX_RING_SIZE; i++) { - if (i == (CONFIG_SYS_MACB_RX_RING_SIZE - 1)) + for (i = 0; i < MACB_RX_RING_SIZE; i++) { + if (i == (MACB_RX_RING_SIZE - 1)) paddr |= RXADDR_WRAP; macb->rx_ring[i].addr = paddr; macb->rx_ring[i].ctrl = 0; paddr += 128; } - for (i = 0; i < CONFIG_SYS_MACB_TX_RING_SIZE; i++) { + for (i = 0; i < MACB_TX_RING_SIZE; i++) { macb->tx_ring[i].addr = 0; - if (i == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) + if (i == (MACB_TX_RING_SIZE - 1)) macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; else macb->tx_ring[i].ctrl = TXBUF_USED; } - macb->rx_tail = macb->tx_head = macb->tx_tail = 0; + macb->rx_tail = 0; + macb->tx_head = 0; + macb->tx_tail = 0; macb_writel(macb, RBQP, macb->rx_ring_dma); macb_writel(macb, TBQP, macb->tx_ring_dma); @@ -654,12 +656,12 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) netdev = &macb->netdev; - macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE, + macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE, &macb->rx_buffer_dma); - macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE + macb->rx_ring = dma_alloc_coherent(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc), &macb->rx_ring_dma); - macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE + macb->tx_ring = dma_alloc_coherent(MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc), &macb->tx_ring_dma); -- cgit v1.3.1 From 5ae0e38278ad3becfc9a0a6bfc5ab8c531ccd621 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Tue, 27 May 2014 16:31:05 +0800 Subject: net: macb: enable dcache in macb MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add to code to flush the dcache after we writing in DMA buffer. Also we need invalidate the dcache before we check the status in the DMA buffer. Tested in SAMA5D3x-EK with gmac0. Tftp download speed shows in below: Disable DCache: 1.1 MiB/s Enable DCache: 1.6 MiB/s Increase speed with about 40%. The code should have no impact with the boards which are not enable_dcache(). Tested in AT91SAM9M10G45EK. Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- drivers/net/macb.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 57 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 750331d0540..01a94a4c4d1 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -51,6 +51,10 @@ struct macb_dma_desc { u32 ctrl; }; +#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc)) +#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE)) +#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE)) + #define RXADDR_USED 0x00000001 #define RXADDR_WRAP 0x00000002 @@ -194,6 +198,39 @@ int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) } #endif +#define RX 1 +#define TX 0 +static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx) +{ + if (rx) + invalidate_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + + MACB_RX_DMA_DESC_SIZE); + else + invalidate_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + + MACB_TX_DMA_DESC_SIZE); +} + +static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx) +{ + if (rx) + flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + + MACB_RX_DMA_DESC_SIZE); + else + flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + + MACB_TX_DMA_DESC_SIZE); +} + +static inline void macb_flush_rx_buffer(struct macb_device *macb) +{ + flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + + MACB_RX_BUFFER_SIZE); +} + +static inline void macb_invalidate_rx_buffer(struct macb_device *macb) +{ + invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + + MACB_RX_BUFFER_SIZE); +} #if defined(CONFIG_CMD_NET) @@ -218,6 +255,9 @@ static int macb_send(struct eth_device *netdev, void *packet, int length) macb->tx_ring[tx_head].ctrl = ctrl; macb->tx_ring[tx_head].addr = paddr; barrier(); + macb_flush_ring_desc(macb, TX); + /* Do we need check paddr and length is dcache line aligned? */ + flush_dcache_range(paddr, paddr + length); macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); /* @@ -226,6 +266,7 @@ static int macb_send(struct eth_device *netdev, void *packet, int length) */ for (i = 0; i <= MACB_TX_TIMEOUT; i++) { barrier(); + macb_invalidate_ring_desc(macb, TX); ctrl = macb->tx_ring[tx_head].ctrl; if (ctrl & TXBUF_USED) break; @@ -254,6 +295,8 @@ static void reclaim_rx_buffers(struct macb_device *macb, unsigned int i; i = macb->rx_tail; + + macb_invalidate_ring_desc(macb, RX); while (i > new_tail) { macb->rx_ring[i].addr &= ~RXADDR_USED; i++; @@ -267,6 +310,7 @@ static void reclaim_rx_buffers(struct macb_device *macb, } barrier(); + macb_flush_ring_desc(macb, RX); macb->rx_tail = new_tail; } @@ -280,6 +324,8 @@ static int macb_recv(struct eth_device *netdev) u32 status; for (;;) { + macb_invalidate_ring_desc(macb, RX); + if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) return -1; @@ -293,6 +339,8 @@ static int macb_recv(struct eth_device *netdev) if (status & RXBUF_FRAME_END) { buffer = macb->rx_buffer + 128 * macb->rx_tail; length = status & RXBUF_FRMLEN_MASK; + + macb_invalidate_rx_buffer(macb); if (wrapped) { unsigned int headlen, taillen; @@ -506,6 +554,9 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) macb->rx_ring[i].ctrl = 0; paddr += 128; } + macb_flush_ring_desc(macb, RX); + macb_flush_rx_buffer(macb); + for (i = 0; i < MACB_TX_RING_SIZE; i++) { macb->tx_ring[i].addr = 0; if (i == (MACB_TX_RING_SIZE - 1)) @@ -513,6 +564,8 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) else macb->tx_ring[i].ctrl = TXBUF_USED; } + macb_flush_ring_desc(macb, TX); + macb->rx_tail = 0; macb->tx_head = 0; macb->tx_tail = 0; @@ -658,13 +711,13 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE, &macb->rx_buffer_dma); - macb->rx_ring = dma_alloc_coherent(MACB_RX_RING_SIZE - * sizeof(struct macb_dma_desc), + macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE, &macb->rx_ring_dma); - macb->tx_ring = dma_alloc_coherent(MACB_TX_RING_SIZE - * sizeof(struct macb_dma_desc), + macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE, &macb->tx_ring_dma); + /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */ + macb->regs = regs; macb->phy_addr = phy_addr; -- cgit v1.3.1 From b137bd8c8d75062719c2fe2880205f8b707a89a8 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Mon, 19 May 2014 19:51:27 +0800 Subject: video: atmel_hlcdfb: enable dcache support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To support dcache, we need flush DMA descriptor buffer before enable lcd DMA. Also we need call lcd_set_flush_dcache(1) to make lcd driver flush the lcd buffer if there is any change. Cc: Anatolij Gustschin Signed-off-by: Josh Wu Acked-by: Anatolij Gustschin Signed-off-by: Andreas Bießmann --- drivers/video/atmel_hlcdfb.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index bb4d7d8c147..935ae42a9c8 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -171,6 +171,9 @@ void lcd_ctrl_init(void *lcdbase) | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH; desc->next = (u32)desc; + /* Flush the DMA descriptor if we enabled dcache */ + flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc)); + lcdc_writel(®s->lcdc_baseaddr, desc->address); lcdc_writel(®s->lcdc_basectrl, desc->control); lcdc_writel(®s->lcdc_basenext, desc->next); @@ -194,4 +197,7 @@ void lcd_ctrl_init(void *lcdbase) lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN); while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) udelay(1); + + /* Enable flushing if we enabled dcache */ + lcd_set_flush_dcache(1); } -- cgit v1.3.1 From 2b9912e6a7df7b1f60beb7942bd0e6fa5f9d0167 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Thu, 12 Jun 2014 22:27:12 +0200 Subject: includes: move openssl headers to include/u-boot commit 18b06652cd "tools: include u-boot version of sha256.h" unconditionally forced the sha256.h from u-boot to be used for tools instead of the host version. This is fragile though as it will also include the host version. Therefore move it to include/u-boot to join u-boot/md5.h etc which were renamed for the same reason. cc: Simon Glass Signed-off-by: Jeroen Hofstee --- board/gdsys/p1022/controlcenterd-id.c | 2 +- board/pcs440ep/pcs440ep.c | 2 +- common/cmd_sha1sum.c | 2 +- common/hash.c | 4 +- common/image-fit.c | 4 +- common/image-sig.c | 4 +- common/image.c | 2 +- drivers/crypto/ace_sha.c | 4 +- drivers/misc/cros_ec_sandbox.c | 2 +- drivers/mmc/rpmb.c | 2 +- include/image.h | 2 +- include/rsa-checksum.h | 24 ------- include/rsa.h | 117 --------------------------------- include/sha1.h | 118 ---------------------------------- include/sha256.h | 22 ------- include/u-boot/rsa-checksum.h | 24 +++++++ include/u-boot/rsa.h | 117 +++++++++++++++++++++++++++++++++ include/u-boot/sha1.h | 118 ++++++++++++++++++++++++++++++++++ include/u-boot/sha256.h | 22 +++++++ lib/rsa/rsa-checksum.c | 6 +- lib/rsa/rsa-verify.c | 6 +- lib/sha1.c | 2 +- lib/sha256.c | 2 +- lib/tpm.c | 2 +- tools/Makefile | 1 - tools/dumpimage.h | 2 +- tools/imagetool.h | 2 +- tools/mkimage.h | 2 +- tools/ubsha1.c | 2 +- 29 files changed, 309 insertions(+), 310 deletions(-) delete mode 100644 include/rsa-checksum.h delete mode 100644 include/rsa.h delete mode 100644 include/sha1.h delete mode 100644 include/sha256.h create mode 100644 include/u-boot/rsa-checksum.h create mode 100644 include/u-boot/rsa.h create mode 100644 include/u-boot/sha1.h create mode 100644 include/u-boot/sha256.h (limited to 'drivers') diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c index 3fca3c53b2e..7e13c9051cb 100644 --- a/board/gdsys/p1022/controlcenterd-id.c +++ b/board/gdsys/p1022/controlcenterd-id.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index f90e809d158..267c0014359 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/common/cmd_sha1sum.c b/common/cmd_sha1sum.c index 644b9a0e668..783ea2e32db 100644 --- a/common/cmd_sha1sum.c +++ b/common/cmd_sha1sum.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/common/hash.c b/common/hash.c index 3d953784af5..12d67594abe 100644 --- a/common/hash.c +++ b/common/hash.c @@ -15,8 +15,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/common/image-fit.c b/common/image-fit.c index 3311343be6d..c61be651334 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -21,10 +21,10 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* !USE_HOSTCC*/ #include -#include -#include #include #include +#include +#include /*****************************************************************************/ /* New uImage format routines */ diff --git a/common/image-sig.c b/common/image-sig.c index 48788f91000..8601edaca35 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -13,8 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* !USE_HOSTCC*/ #include -#include -#include +#include +#include #define IMAGE_MAX_HASHED_NODES 100 diff --git a/common/image.c b/common/image.c index 828b0af6d22..11b3cf58e6f 100644 --- a/common/image.c +++ b/common/image.c @@ -34,7 +34,7 @@ #endif #include -#include +#include #include #include diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c index ed4f5418238..efef4911233 100644 --- a/drivers/crypto/ace_sha.c +++ b/drivers/crypto/ace_sha.c @@ -8,8 +8,8 @@ #include "ace_sha.h" #ifdef CONFIG_SHA_HW_ACCEL -#include -#include +#include +#include #include /* SHA1 value for the message of zero length */ diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index 4bb1d60e5a9..8a04af557d0 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c index 05936f5d1f3..9d0b8bc0c8f 100644 --- a/drivers/mmc/rpmb.c +++ b/drivers/mmc/rpmb.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include "mmc_private.h" /* Request codes */ diff --git a/include/image.h b/include/image.h index ab93eb63339..0a072f5336c 100644 --- a/include/image.h +++ b/include/image.h @@ -886,7 +886,7 @@ struct image_region { }; #if IMAGE_ENABLE_VERIFY -# include +# include #endif struct checksum_algo { const char *name; diff --git a/include/rsa-checksum.h b/include/rsa-checksum.h deleted file mode 100644 index 612db85fe0f..00000000000 --- a/include/rsa-checksum.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2013, Andreas Oetken. - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef _RSA_CHECKSUM_H -#define _RSA_CHECKSUM_H - -#include -#include -#include -#include - -extern const uint8_t padding_sha256_rsa4096[]; -extern const uint8_t padding_sha256_rsa2048[]; -extern const uint8_t padding_sha1_rsa2048[]; - -void sha256_calculate(const struct image_region region[], int region_count, - uint8_t *checksum); -void sha1_calculate(const struct image_region region[], int region_count, - uint8_t *checksum); - -#endif diff --git a/include/rsa.h b/include/rsa.h deleted file mode 100644 index 325751ab7e1..00000000000 --- a/include/rsa.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) 2013, Google Inc. - * - * (C) Copyright 2008 Semihalf - * - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _RSA_H -#define _RSA_H - -#include -#include - -/** - * struct rsa_public_key - holder for a public key - * - * An RSA public key consists of a modulus (typically called N), the inverse - * and R^2, where R is 2^(# key bits). - */ - -struct rsa_public_key { - uint len; /* len of modulus[] in number of uint32_t */ - uint32_t n0inv; /* -1 / modulus[0] mod 2^32 */ - uint32_t *modulus; /* modulus as little endian array */ - uint32_t *rr; /* R^2 as little endian array */ -}; - -#if IMAGE_ENABLE_SIGN -/** - * sign() - calculate and return signature for given input data - * - * @info: Specifies key and FIT information - * @data: Pointer to the input data - * @data_len: Data length - * @sigp: Set to an allocated buffer holding the signature - * @sig_len: Set to length of the calculated hash - * - * This computes input data signature according to selected algorithm. - * Resulting signature value is placed in an allocated buffer, the - * pointer is returned as *sigp. The length of the calculated - * signature is returned via the sig_len pointer argument. The caller - * should free *sigp. - * - * @return: 0, on success, -ve on error - */ -int rsa_sign(struct image_sign_info *info, - const struct image_region region[], - int region_count, uint8_t **sigp, uint *sig_len); - -/** - * add_verify_data() - Add verification information to FDT - * - * Add public key information to the FDT node, suitable for - * verification at run-time. The information added depends on the - * algorithm being used. - * - * @info: Specifies key and FIT information - * @keydest: Destination FDT blob for public key data - * @return: 0, on success, -ENOSPC if the keydest FDT blob ran out of space, - other -ve value on error -*/ -int rsa_add_verify_data(struct image_sign_info *info, void *keydest); -#else -static inline int rsa_sign(struct image_sign_info *info, - const struct image_region region[], int region_count, - uint8_t **sigp, uint *sig_len) -{ - return -ENXIO; -} - -static inline int rsa_add_verify_data(struct image_sign_info *info, - void *keydest) -{ - return -ENXIO; -} -#endif - -#if IMAGE_ENABLE_VERIFY -/** - * rsa_verify() - Verify a signature against some data - * - * Verify a RSA PKCS1.5 signature against an expected hash. - * - * @info: Specifies key and FIT information - * @data: Pointer to the input data - * @data_len: Data length - * @sig: Signature - * @sig_len: Number of bytes in signature - * @return 0 if verified, -ve on error - */ -int rsa_verify(struct image_sign_info *info, - const struct image_region region[], int region_count, - uint8_t *sig, uint sig_len); -#else -static inline int rsa_verify(struct image_sign_info *info, - const struct image_region region[], int region_count, - uint8_t *sig, uint sig_len) -{ - return -ENXIO; -} -#endif - -#define RSA2048_BYTES (2048 / 8) -#define RSA4096_BYTES (4096 / 8) - -/* This is the minimum/maximum key size we support, in bits */ -#define RSA_MIN_KEY_BITS 2048 -#define RSA_MAX_KEY_BITS 4096 - -/* This is the maximum signature length that we support, in bits */ -#define RSA_MAX_SIG_BITS 4096 - -#endif diff --git a/include/sha1.h b/include/sha1.h deleted file mode 100644 index da09dab9769..00000000000 --- a/include/sha1.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * \file sha1.h - * based from http://xyssl.org/code/source/sha1/ - * FIPS-180-1 compliant SHA-1 implementation - * - * Copyright (C) 2003-2006 Christophe Devine - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License, version 2.1 as published by the Free Software Foundation. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ -/* - * The SHA-1 standard was published by NIST in 1993. - * - * http://www.itl.nist.gov/fipspubs/fip180-1.htm - */ -#ifndef _SHA1_H -#define _SHA1_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define SHA1_SUM_POS -0x20 -#define SHA1_SUM_LEN 20 - -/** - * \brief SHA-1 context structure - */ -typedef struct -{ - unsigned long total[2]; /*!< number of bytes processed */ - unsigned long state[5]; /*!< intermediate digest state */ - unsigned char buffer[64]; /*!< data block being processed */ -} -sha1_context; - -/** - * \brief SHA-1 context setup - * - * \param ctx SHA-1 context to be initialized - */ -void sha1_starts( sha1_context *ctx ); - -/** - * \brief SHA-1 process buffer - * - * \param ctx SHA-1 context - * \param input buffer holding the data - * \param ilen length of the input data - */ -void sha1_update(sha1_context *ctx, const unsigned char *input, - unsigned int ilen); - -/** - * \brief SHA-1 final digest - * - * \param ctx SHA-1 context - * \param output SHA-1 checksum result - */ -void sha1_finish( sha1_context *ctx, unsigned char output[20] ); - -/** - * \brief Output = SHA-1( input buffer ) - * - * \param input buffer holding the data - * \param ilen length of the input data - * \param output SHA-1 checksum result - */ -void sha1_csum(const unsigned char *input, unsigned int ilen, - unsigned char *output); - -/** - * \brief Output = SHA-1( input buffer ), with watchdog triggering - * - * \param input buffer holding the data - * \param ilen length of the input data - * \param output SHA-1 checksum result - * \param chunk_sz watchdog triggering period (in bytes of input processed) - */ -void sha1_csum_wd(const unsigned char *input, unsigned int ilen, - unsigned char *output, unsigned int chunk_sz); - -/** - * \brief Output = HMAC-SHA-1( input buffer, hmac key ) - * - * \param key HMAC secret key - * \param keylen length of the HMAC key - * \param input buffer holding the data - * \param ilen length of the input data - * \param output HMAC-SHA-1 result - */ -void sha1_hmac(const unsigned char *key, int keylen, - const unsigned char *input, unsigned int ilen, - unsigned char *output); - -/** - * \brief Checkup routine - * - * \return 0 if successful, or 1 if the test failed - */ -int sha1_self_test( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* sha1.h */ diff --git a/include/sha256.h b/include/sha256.h deleted file mode 100644 index beadab35ffc..00000000000 --- a/include/sha256.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _SHA256_H -#define _SHA256_H - -#define SHA256_SUM_LEN 32 - -/* Reset watchdog each time we process this many bytes */ -#define CHUNKSZ_SHA256 (64 * 1024) - -typedef struct { - uint32_t total[2]; - uint32_t state[8]; - uint8_t buffer[64]; -} sha256_context; - -void sha256_starts(sha256_context * ctx); -void sha256_update(sha256_context *ctx, const uint8_t *input, uint32_t length); -void sha256_finish(sha256_context * ctx, uint8_t digest[SHA256_SUM_LEN]); - -void sha256_csum_wd(const unsigned char *input, unsigned int ilen, - unsigned char *output, unsigned int chunk_sz); - -#endif /* _SHA256_H */ diff --git a/include/u-boot/rsa-checksum.h b/include/u-boot/rsa-checksum.h new file mode 100644 index 00000000000..c996fb3e4c1 --- /dev/null +++ b/include/u-boot/rsa-checksum.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013, Andreas Oetken. + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef _RSA_CHECKSUM_H +#define _RSA_CHECKSUM_H + +#include +#include +#include +#include + +extern const uint8_t padding_sha256_rsa4096[]; +extern const uint8_t padding_sha256_rsa2048[]; +extern const uint8_t padding_sha1_rsa2048[]; + +void sha256_calculate(const struct image_region region[], int region_count, + uint8_t *checksum); +void sha1_calculate(const struct image_region region[], int region_count, + uint8_t *checksum); + +#endif diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h new file mode 100644 index 00000000000..325751ab7e1 --- /dev/null +++ b/include/u-boot/rsa.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2013, Google Inc. + * + * (C) Copyright 2008 Semihalf + * + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _RSA_H +#define _RSA_H + +#include +#include + +/** + * struct rsa_public_key - holder for a public key + * + * An RSA public key consists of a modulus (typically called N), the inverse + * and R^2, where R is 2^(# key bits). + */ + +struct rsa_public_key { + uint len; /* len of modulus[] in number of uint32_t */ + uint32_t n0inv; /* -1 / modulus[0] mod 2^32 */ + uint32_t *modulus; /* modulus as little endian array */ + uint32_t *rr; /* R^2 as little endian array */ +}; + +#if IMAGE_ENABLE_SIGN +/** + * sign() - calculate and return signature for given input data + * + * @info: Specifies key and FIT information + * @data: Pointer to the input data + * @data_len: Data length + * @sigp: Set to an allocated buffer holding the signature + * @sig_len: Set to length of the calculated hash + * + * This computes input data signature according to selected algorithm. + * Resulting signature value is placed in an allocated buffer, the + * pointer is returned as *sigp. The length of the calculated + * signature is returned via the sig_len pointer argument. The caller + * should free *sigp. + * + * @return: 0, on success, -ve on error + */ +int rsa_sign(struct image_sign_info *info, + const struct image_region region[], + int region_count, uint8_t **sigp, uint *sig_len); + +/** + * add_verify_data() - Add verification information to FDT + * + * Add public key information to the FDT node, suitable for + * verification at run-time. The information added depends on the + * algorithm being used. + * + * @info: Specifies key and FIT information + * @keydest: Destination FDT blob for public key data + * @return: 0, on success, -ENOSPC if the keydest FDT blob ran out of space, + other -ve value on error +*/ +int rsa_add_verify_data(struct image_sign_info *info, void *keydest); +#else +static inline int rsa_sign(struct image_sign_info *info, + const struct image_region region[], int region_count, + uint8_t **sigp, uint *sig_len) +{ + return -ENXIO; +} + +static inline int rsa_add_verify_data(struct image_sign_info *info, + void *keydest) +{ + return -ENXIO; +} +#endif + +#if IMAGE_ENABLE_VERIFY +/** + * rsa_verify() - Verify a signature against some data + * + * Verify a RSA PKCS1.5 signature against an expected hash. + * + * @info: Specifies key and FIT information + * @data: Pointer to the input data + * @data_len: Data length + * @sig: Signature + * @sig_len: Number of bytes in signature + * @return 0 if verified, -ve on error + */ +int rsa_verify(struct image_sign_info *info, + const struct image_region region[], int region_count, + uint8_t *sig, uint sig_len); +#else +static inline int rsa_verify(struct image_sign_info *info, + const struct image_region region[], int region_count, + uint8_t *sig, uint sig_len) +{ + return -ENXIO; +} +#endif + +#define RSA2048_BYTES (2048 / 8) +#define RSA4096_BYTES (4096 / 8) + +/* This is the minimum/maximum key size we support, in bits */ +#define RSA_MIN_KEY_BITS 2048 +#define RSA_MAX_KEY_BITS 4096 + +/* This is the maximum signature length that we support, in bits */ +#define RSA_MAX_SIG_BITS 4096 + +#endif diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h new file mode 100644 index 00000000000..da09dab9769 --- /dev/null +++ b/include/u-boot/sha1.h @@ -0,0 +1,118 @@ +/** + * \file sha1.h + * based from http://xyssl.org/code/source/sha1/ + * FIPS-180-1 compliant SHA-1 implementation + * + * Copyright (C) 2003-2006 Christophe Devine + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License, version 2.1 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ +/* + * The SHA-1 standard was published by NIST in 1993. + * + * http://www.itl.nist.gov/fipspubs/fip180-1.htm + */ +#ifndef _SHA1_H +#define _SHA1_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define SHA1_SUM_POS -0x20 +#define SHA1_SUM_LEN 20 + +/** + * \brief SHA-1 context structure + */ +typedef struct +{ + unsigned long total[2]; /*!< number of bytes processed */ + unsigned long state[5]; /*!< intermediate digest state */ + unsigned char buffer[64]; /*!< data block being processed */ +} +sha1_context; + +/** + * \brief SHA-1 context setup + * + * \param ctx SHA-1 context to be initialized + */ +void sha1_starts( sha1_context *ctx ); + +/** + * \brief SHA-1 process buffer + * + * \param ctx SHA-1 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void sha1_update(sha1_context *ctx, const unsigned char *input, + unsigned int ilen); + +/** + * \brief SHA-1 final digest + * + * \param ctx SHA-1 context + * \param output SHA-1 checksum result + */ +void sha1_finish( sha1_context *ctx, unsigned char output[20] ); + +/** + * \brief Output = SHA-1( input buffer ) + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-1 checksum result + */ +void sha1_csum(const unsigned char *input, unsigned int ilen, + unsigned char *output); + +/** + * \brief Output = SHA-1( input buffer ), with watchdog triggering + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-1 checksum result + * \param chunk_sz watchdog triggering period (in bytes of input processed) + */ +void sha1_csum_wd(const unsigned char *input, unsigned int ilen, + unsigned char *output, unsigned int chunk_sz); + +/** + * \brief Output = HMAC-SHA-1( input buffer, hmac key ) + * + * \param key HMAC secret key + * \param keylen length of the HMAC key + * \param input buffer holding the data + * \param ilen length of the input data + * \param output HMAC-SHA-1 result + */ +void sha1_hmac(const unsigned char *key, int keylen, + const unsigned char *input, unsigned int ilen, + unsigned char *output); + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + */ +int sha1_self_test( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* sha1.h */ diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h new file mode 100644 index 00000000000..beadab35ffc --- /dev/null +++ b/include/u-boot/sha256.h @@ -0,0 +1,22 @@ +#ifndef _SHA256_H +#define _SHA256_H + +#define SHA256_SUM_LEN 32 + +/* Reset watchdog each time we process this many bytes */ +#define CHUNKSZ_SHA256 (64 * 1024) + +typedef struct { + uint32_t total[2]; + uint32_t state[8]; + uint8_t buffer[64]; +} sha256_context; + +void sha256_starts(sha256_context * ctx); +void sha256_update(sha256_context *ctx, const uint8_t *input, uint32_t length); +void sha256_finish(sha256_context * ctx, uint8_t digest[SHA256_SUM_LEN]); + +void sha256_csum_wd(const unsigned char *input, unsigned int ilen, + unsigned char *output, unsigned int chunk_sz); + +#endif /* _SHA256_H */ diff --git a/lib/rsa/rsa-checksum.c b/lib/rsa/rsa-checksum.c index 32d6602e975..8d8b59f779a 100644 --- a/lib/rsa/rsa-checksum.c +++ b/lib/rsa/rsa-checksum.c @@ -13,9 +13,9 @@ #else #include "fdt_host.h" #endif -#include -#include -#include +#include +#include +#include /* PKCS 1.5 paddings as described in the RSA PKCS#1 v2.1 standard. */ diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 587da5b4706..bcb906368d0 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -17,9 +17,9 @@ #include "mkimage.h" #include #endif -#include -#include -#include +#include +#include +#include #define UINT64_MULT32(v, multby) (((uint64_t)(v)) * ((uint32_t)(multby))) diff --git a/lib/sha1.c b/lib/sha1.c index a121224855f..0a5f68864c7 100644 --- a/lib/sha1.c +++ b/lib/sha1.c @@ -36,7 +36,7 @@ #include #endif /* USE_HOSTCC */ #include -#include "sha1.h" +#include /* * 32-bit integer manipulation macros (big endian) diff --git a/lib/sha256.c b/lib/sha256.c index b1085ea7917..bb338baefa8 100644 --- a/lib/sha256.c +++ b/lib/sha256.c @@ -13,7 +13,7 @@ #include #endif /* USE_HOSTCC */ #include -#include +#include /* * 32-bit integer manipulation macros (big endian) diff --git a/lib/tpm.c b/lib/tpm.c index 967c8e65150..d9789b022ab 100644 --- a/lib/tpm.c +++ b/lib/tpm.c @@ -7,7 +7,7 @@ #include #include -#include +#include #include #include diff --git a/tools/Makefile b/tools/Makefile index 949b6c6c38b..3a1180f433c 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -192,7 +192,6 @@ endif # !LOGO_BMP # Define _GNU_SOURCE to obtain the getline prototype from stdio.h # HOST_EXTRACFLAGS += -include $(srctree)/include/libfdt_env.h \ - -include $(srctree)/include/sha256.h \ $(patsubst -I%,-idirafter%, $(UBOOTINCLUDE)) \ -I$(srctree)/lib/libfdt \ -I$(srctree)/tools \ diff --git a/tools/dumpimage.h b/tools/dumpimage.h index d78523ded72..e415f14e147 100644 --- a/tools/dumpimage.h +++ b/tools/dumpimage.h @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include "fdt_host.h" #include "imagetool.h" diff --git a/tools/imagetool.h b/tools/imagetool.h index c480687ec13..c8af0e82f8b 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include "fdt_host.h" #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) diff --git a/tools/mkimage.h b/tools/mkimage.h index d5491b6e60a..3f369b748ed 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include "fdt_host.h" #include "imagetool.h" diff --git a/tools/ubsha1.c b/tools/ubsha1.c index 1041588d0b0..4a17246da78 100644 --- a/tools/ubsha1.c +++ b/tools/ubsha1.c @@ -13,7 +13,7 @@ #include #include #include -#include "sha1.h" +#include int main (int argc, char **argv) { -- cgit v1.3.1 From a348d56934d6b0de31d5bdc12911a63e186e8ffa Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Sun, 15 Jun 2014 17:17:04 +0200 Subject: pmic: tps65090: correct checking i2c bus The function tps65090_init checks the i2c bus of p->bus. However the pointer p is not intialiased at this point. Check the local variable bus instead. cc: Tom Wai-Hong Tam Signed-off-by: Jeroen Hofstee Acked-by: Simon Glass --- drivers/power/pmic/pmic_tps65090.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/pmic/pmic_tps65090.c b/drivers/power/pmic/pmic_tps65090.c index c5b396610ac..337903acec8 100644 --- a/drivers/power/pmic/pmic_tps65090.c +++ b/drivers/power/pmic/pmic_tps65090.c @@ -285,7 +285,7 @@ int tps65090_init(void) } bus = i2c_get_bus_num_fdt(parent); - if (p->bus < 0) { + if (bus < 0) { debug("%s: Cannot find I2C bus\n", __func__); return -ENOENT; } -- cgit v1.3.1 From 3e01ed00da98a29fe2b71c6d60309d5b09adc0de Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Sat, 7 Jun 2014 04:22:52 +0300 Subject: mtd: nand: davinci: add header file for driver definitions The definitions inside emif_defs.h concern davinci nand driver and should be in it's header. So create header file for davinci nand driver and move definitions from emif_defs.h and nand_defs.h to it. Acked-by: Vitaly Andrianov Signed-off-by: Ivan Khoronzhuk [trini: Fixup more davinci breakage] Signed-off-by: Tom Rini --- arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 2 +- arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c | 1 + arch/arm/cpu/armv7/keystone/aemif.c | 2 +- arch/arm/include/asm/arch-davinci/emif_defs.h | 72 ------------------ arch/arm/include/asm/arch-davinci/hardware.h | 1 - arch/arm/include/asm/arch-davinci/nand_defs.h | 38 ---------- arch/arm/include/asm/arch-keystone/emif_defs.h | 73 ------------------ arch/arm/include/asm/arch-keystone/nand_defs.h | 23 ------ arch/arm/include/asm/arch-tnetv107x/emif_defs.h | 1 - arch/arm/include/asm/arch-tnetv107x/hardware.h | 2 + arch/arm/include/asm/arch-tnetv107x/nand_defs.h | 23 ------ arch/arm/include/asm/ti-common/davinci_nand.h | 98 +++++++++++++++++++++++++ board/Barix/ipam390/ipam390.c | 2 +- board/ait/cam_enc_4xx/cam_enc_4xx.c | 2 +- board/davinci/da8xxevm/da830evm.c | 3 +- board/davinci/da8xxevm/da850evm.c | 2 +- board/davinci/dm355evm/dm355evm.c | 3 +- board/davinci/dm355leopard/dm355leopard.c | 2 +- board/davinci/dm365evm/dm365evm.c | 3 +- board/davinci/dm6467evm/dm6467evm.c | 3 +- board/davinci/ea20/ea20.c | 2 +- board/davinci/sonata/sonata.c | 2 +- board/enbw/enbw_cmc/enbw_cmc.c | 2 +- board/omicron/calimain/calimain.c | 2 +- board/ti/k2hk_evm/board.c | 1 - board/ti/tnetv107xevm/sdb_board.c | 2 +- drivers/mtd/nand/davinci_nand.c | 3 +- include/configs/davinci_dm6467evm.h | 2 + include/configs/k2hk_evm.h | 2 + 29 files changed, 122 insertions(+), 252 deletions(-) delete mode 100644 arch/arm/include/asm/arch-davinci/emif_defs.h delete mode 100644 arch/arm/include/asm/arch-davinci/nand_defs.h delete mode 100644 arch/arm/include/asm/arch-keystone/emif_defs.h delete mode 100644 arch/arm/include/asm/arch-keystone/nand_defs.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/emif_defs.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/nand_defs.h create mode 100644 arch/arm/include/asm/ti-common/davinci_nand.h (limited to 'drivers') diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index b91e948ce3e..19730cef8c0 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include void davinci_enable_uart0(void) diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c index ee096fe7219..c8b44988d3c 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/cpu/armv7/keystone/aemif.c b/arch/arm/cpu/armv7/keystone/aemif.c index 9b26886dba6..bcbb95aa448 100644 --- a/arch/arm/cpu/armv7/keystone/aemif.c +++ b/arch/arm/cpu/armv7/keystone/aemif.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) #define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) diff --git a/arch/arm/include/asm/arch-davinci/emif_defs.h b/arch/arm/include/asm/arch-davinci/emif_defs.h deleted file mode 100644 index 7e19cfeed44..00000000000 --- a/arch/arm/include/asm/arch-davinci/emif_defs.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _EMIF_DEFS_H_ -#define _EMIF_DEFS_H_ - -#include - -struct davinci_emif_regs { - u_int32_t ercsr; - u_int32_t awccr; - u_int32_t sdbcr; - u_int32_t sdrcr; - u_int32_t ab1cr; - u_int32_t ab2cr; - u_int32_t ab3cr; - u_int32_t ab4cr; - u_int32_t sdtimr; - u_int32_t ddrsr; - u_int32_t ddrphycr; - u_int32_t ddrphysr; - u_int32_t totar; - u_int32_t totactr; - u_int32_t ddrphyid_rev; - u_int32_t sdsretr; - u_int32_t eirr; - u_int32_t eimr; - u_int32_t eimsr; - u_int32_t eimcr; - u_int32_t ioctrlr; - u_int32_t iostatr; - u_int8_t rsvd0[8]; - u_int32_t nandfcr; - u_int32_t nandfsr; - u_int8_t rsvd1[8]; - u_int32_t nandfecc[4]; - u_int8_t rsvd2[60]; - u_int32_t nand4biteccload; - u_int32_t nand4bitecc[4]; - u_int32_t nanderradd1; - u_int32_t nanderradd2; - u_int32_t nanderrval1; - u_int32_t nanderrval2; -}; - -#define davinci_emif_regs \ - ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) - -#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) -#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) -#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) -#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) -#define DAVINCI_NANDFCR_CS2NAND (1 << 0) - -/* Chip Select setup */ -#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) -#define DAVINCI_ABCR_EXT_WAIT (1 << 30) -#define DAVINCI_ABCR_WSETUP(n) (n << 26) -#define DAVINCI_ABCR_WSTROBE(n) (n << 20) -#define DAVINCI_ABCR_WHOLD(n) (n << 17) -#define DAVINCI_ABCR_RSETUP(n) (n << 13) -#define DAVINCI_ABCR_RSTROBE(n) (n << 7) -#define DAVINCI_ABCR_RHOLD(n) (n << 4) -#define DAVINCI_ABCR_TA(n) (n << 2) -#define DAVINCI_ABCR_ASIZE_16BIT 1 -#define DAVINCI_ABCR_ASIZE_8BIT 0 - -#endif diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 98fe56e6865..a4eb0bd89b0 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -597,7 +597,6 @@ static inline enum davinci_clk_ids get_async3_src(void) #if defined(CONFIG_SOC_DM365) #include #include -#include #include #include #include diff --git a/arch/arm/include/asm/arch-davinci/nand_defs.h b/arch/arm/include/asm/arch-davinci/nand_defs.h deleted file mode 100644 index dee1c6f814e..00000000000 --- a/arch/arm/include/asm/arch-davinci/nand_defs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Parts shamelesly stolen from Linux Kernel source tree. - * - * ------------------------------------------------------------ - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include - -#ifdef CONFIG_SOC_DM646X -#define MASK_CLE 0x80000 -#define MASK_ALE 0x40000 -#else -#define MASK_CLE 0x10 -#define MASK_ALE 0x08 -#endif - -#ifdef CONFIG_SYS_NAND_MASK_CLE -#undef MASK_CLE -#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE -#endif -#ifdef CONFIG_SYS_NAND_MASK_ALE -#undef MASK_ALE -#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE -#endif - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -extern void davinci_nand_init(struct nand_chip *nand); - -#endif diff --git a/arch/arm/include/asm/arch-keystone/emif_defs.h b/arch/arm/include/asm/arch-keystone/emif_defs.h deleted file mode 100644 index a3378aa30e8..00000000000 --- a/arch/arm/include/asm/arch-keystone/emif_defs.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * emif definitions to re-use davinci emif driver on Keystone2 - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * (C) Copyright 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _EMIF_DEFS_H_ -#define _EMIF_DEFS_H_ - -#include - -struct davinci_emif_regs { - uint32_t ercsr; - uint32_t awccr; - uint32_t sdbcr; - uint32_t sdrcr; - uint32_t abncr[4]; - uint32_t sdtimr; - uint32_t ddrsr; - uint32_t ddrphycr; - uint32_t ddrphysr; - uint32_t totar; - uint32_t totactr; - uint32_t ddrphyid_rev; - uint32_t sdsretr; - uint32_t eirr; - uint32_t eimr; - uint32_t eimsr; - uint32_t eimcr; - uint32_t ioctrlr; - uint32_t iostatr; - uint32_t rsvd0; - uint32_t one_nand_cr; - uint32_t nandfcr; - uint32_t nandfsr; - uint32_t rsvd1[2]; - uint32_t nandfecc[4]; - uint32_t rsvd2[15]; - uint32_t nand4biteccload; - uint32_t nand4bitecc[4]; - uint32_t nanderradd1; - uint32_t nanderradd2; - uint32_t nanderrval1; - uint32_t nanderrval2; -}; - -#define davinci_emif_regs \ - ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) - -#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) -#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) -#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) -#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) - -/* Chip Select setup */ -#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) -#define DAVINCI_ABCR_EXT_WAIT (1 << 30) -#define DAVINCI_ABCR_WSETUP(n) ((n) << 26) -#define DAVINCI_ABCR_WSTROBE(n) ((n) << 20) -#define DAVINCI_ABCR_WHOLD(n) ((n) << 17) -#define DAVINCI_ABCR_RSETUP(n) ((n) << 13) -#define DAVINCI_ABCR_RSTROBE(n) ((n) << 7) -#define DAVINCI_ABCR_RHOLD(n) ((n) << 4) -#define DAVINCI_ABCR_TA(n) ((n) << 2) -#define DAVINCI_ABCR_ASIZE_16BIT 1 -#define DAVINCI_ABCR_ASIZE_8BIT 0 - -#endif diff --git a/arch/arm/include/asm/arch-keystone/nand_defs.h b/arch/arm/include/asm/arch-keystone/nand_defs.h deleted file mode 100644 index 58417dbc0b5..00000000000 --- a/arch/arm/include/asm/arch-keystone/nand_defs.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * nand driver definitions to re-use davinci nand driver on Keystone2 - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * (C) Copyright 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include -#include - -#define MASK_CLE 0x4000 -#define MASK_ALE 0x2000 - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -#endif diff --git a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h b/arch/arm/include/asm/arch-tnetv107x/emif_defs.h deleted file mode 100644 index 9969a018e75..00000000000 --- a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h index 2a7ca4e00c1..d458e0bdf09 100644 --- a/arch/arm/include/asm/arch-tnetv107x/hardware.h +++ b/arch/arm/include/asm/arch-tnetv107x/hardware.h @@ -155,4 +155,6 @@ int wdt_kick(void); #define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500) #define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h b/arch/arm/include/asm/arch-tnetv107x/nand_defs.h deleted file mode 100644 index b298fba9058..00000000000 --- a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * TNETV107X: NAND definitions - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include -#include - -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE - -#define MASK_CLE 0x4000 -#define MASK_ALE 0x2000 - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -extern void davinci_nand_init(struct nand_chip *nand); - -#endif diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h new file mode 100644 index 00000000000..11407be1446 --- /dev/null +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -0,0 +1,98 @@ +/* + * NAND Flash Driver + * + * Copyright (C) 2006-2014 Texas Instruments. + * + * Based on Linux DaVinci NAND driver by TI. + */ + +#ifndef _DAVINCI_NAND_H_ +#define _DAVINCI_NAND_H_ + +#include +#include + +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 + +#define MASK_CLE 0x10 +#define MASK_ALE 0x08 + +#ifdef CONFIG_SYS_NAND_MASK_CLE +#undef MASK_CLE +#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE +#endif +#ifdef CONFIG_SYS_NAND_MASK_ALE +#undef MASK_ALE +#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE +#endif + +struct davinci_emif_regs { + uint32_t ercsr; + uint32_t awccr; + uint32_t sdbcr; + uint32_t sdrcr; + union { + uint32_t abncr[4]; + uint32_t ab1cr; + uint32_t ab2cr; + uint32_t ab3cr; + uint32_t ab4cr; + }; + uint32_t sdtimr; + uint32_t ddrsr; + uint32_t ddrphycr; + uint32_t ddrphysr; + uint32_t totar; + uint32_t totactr; + uint32_t ddrphyid_rev; + uint32_t sdsretr; + uint32_t eirr; + uint32_t eimr; + uint32_t eimsr; + uint32_t eimcr; + uint32_t ioctrlr; + uint32_t iostatr; + uint32_t rsvd0; + uint32_t one_nand_cr; + uint32_t nandfcr; + uint32_t nandfsr; + uint32_t rsvd1[2]; + uint32_t nandfecc[4]; + uint32_t rsvd2[15]; + uint32_t nand4biteccload; + uint32_t nand4bitecc[4]; + uint32_t nanderradd1; + uint32_t nanderradd2; + uint32_t nanderrval1; + uint32_t nanderrval2; +}; + +#define davinci_emif_regs \ + ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) + +#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) +#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) +#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) +#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) +#define DAVINCI_NANDFCR_CS2NAND (1 << 0) + +/* Chip Select setup */ +#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) +#define DAVINCI_ABCR_EXT_WAIT (1 << 30) +#define DAVINCI_ABCR_WSETUP(n) (n << 26) +#define DAVINCI_ABCR_WSTROBE(n) (n << 20) +#define DAVINCI_ABCR_WHOLD(n) (n << 17) +#define DAVINCI_ABCR_RSETUP(n) (n << 13) +#define DAVINCI_ABCR_RSTROBE(n) (n << 7) +#define DAVINCI_ABCR_RHOLD(n) (n << 4) +#define DAVINCI_ABCR_TA(n) (n << 2) +#define DAVINCI_ABCR_ASIZE_16BIT 1 +#define DAVINCI_ABCR_ASIZE_8BIT 0 + +void davinci_nand_init(struct nand_chip *nand); + +#endif diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c index ae88b4230a2..6ce8960bbd6 100644 --- a/board/Barix/ipam390/ipam390.c +++ b/board/Barix/ipam390/ipam390.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index 7e1b16ac465..1f816b3df6e 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #ifdef CONFIG_DAVINCI_MMC #include diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c index 4f5c780e549..c40587ff098 100644 --- a/board/davinci/da8xxevm/da830evm.c +++ b/board/davinci/da8xxevm/da830evm.c @@ -25,12 +25,11 @@ #include #include #include -#include #include #include #include #include -#include +#include #include #ifdef CONFIG_DAVINCI_MMC diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 85b483096b3..b9ca38e9293 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c index 10422b226b8..e5a958f7e0c 100644 --- a/board/davinci/dm355evm/dm355evm.c +++ b/board/davinci/dm355evm/dm355evm.c @@ -8,8 +8,7 @@ #include #include #include -#include -#include +#include #include #include #include diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c index 534184329cb..53902f996c7 100644 --- a/board/davinci/dm355leopard/dm355leopard.c +++ b/board/davinci/dm355leopard/dm355leopard.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c index ceffd4d6038..24bec56d568 100644 --- a/board/davinci/dm365evm/dm365evm.c +++ b/board/davinci/dm365evm/dm365evm.c @@ -8,8 +8,7 @@ #include #include #include -#include -#include +#include #include #include #include diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c index 469c9bac4b2..e51cc9e6389 100644 --- a/board/davinci/dm6467evm/dm6467evm.c +++ b/board/davinci/dm6467evm/dm6467evm.c @@ -8,7 +8,8 @@ #include #include #include -#include +#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index c4444c7c7f5..66804d75bd0 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index aa04041246f..f5c3258de56 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include #include diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c index 39efe20bfdf..53b83621473 100644 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c index dd28915cdc4..32f2b201838 100644 --- a/board/omicron/calimain/calimain.c +++ b/board/omicron/calimain/calimain.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c index dc39139565f..53f26b2ef33 100644 --- a/board/ti/k2hk_evm/board.c +++ b/board/ti/k2hk_evm/board.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c index a95434b5efe..a84ec84baeb 100644 --- a/board/ti/tnetv107xevm/sdb_board.c +++ b/board/ti/tnetv107xevm/sdb_board.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 75b03a74b65..5d425092f43 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -32,8 +32,7 @@ #include #include #include -#include -#include +#include /* Definitions for 4-bit hardware ECC */ #define NAND_TIMEOUT 10240 diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h index 8a3c4533473..b1b18ad0412 100644 --- a/include/configs/davinci_dm6467evm.h +++ b/include/configs/davinci_dm6467evm.h @@ -78,6 +78,8 @@ extern unsigned int davinci_arm_clk_get(void); #define CONFIG_SYS_NO_FLASH #ifdef CONFIG_SYS_USE_NAND #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_MASK_CLE 0x80000 +#define CONFIG_SYS_NAND_MASK_ALE 0x40000 #define CONFIG_SYS_NAND_CS 2 #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_IS_IN_NAND diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 6ba7e62e554..fcfbca92d18 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -136,6 +136,8 @@ #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_SYS_NAND_MASK_CLE 0x4000 +#define CONFIG_SYS_NAND_MASK_ALE 0x2000 #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } -- cgit v1.3.1 From 909ea9aa264423c99cd3039475c98f4a069cb7a4 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Sat, 7 Jun 2014 05:10:49 +0300 Subject: ARM: keystone: aemif: move aemif driver to drivers/memory/ti-aemif.c Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h Acked-by: Vitaly Andrianov Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/Makefile | 1 - arch/arm/cpu/armv7/keystone/aemif.c | 71 ------------------- arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 7 -- arch/arm/include/asm/arch-keystone/hardware.h | 30 ++------ arch/arm/include/asm/ti-common/ti-aemif.h | 39 +++++++++++ board/ti/k2hk_evm/board.c | 9 +-- drivers/Makefile | 1 + drivers/memory/Makefile | 1 + drivers/memory/ti-aemif.c | 80 ++++++++++++++++++++++ include/configs/k2hk_evm.h | 4 ++ 10 files changed, 134 insertions(+), 109 deletions(-) delete mode 100644 arch/arm/cpu/armv7/keystone/aemif.c create mode 100644 arch/arm/include/asm/ti-common/ti-aemif.h create mode 100644 drivers/memory/Makefile create mode 100644 drivers/memory/ti-aemif.c (limited to 'drivers') diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile index b1bd0224eae..c4af2521102 100644 --- a/arch/arm/cpu/armv7/keystone/Makefile +++ b/arch/arm/cpu/armv7/keystone/Makefile @@ -5,7 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += aemif.o obj-y += init.o obj-y += psc.o obj-y += clock.o diff --git a/arch/arm/cpu/armv7/keystone/aemif.c b/arch/arm/cpu/armv7/keystone/aemif.c deleted file mode 100644 index bcbb95aa448..00000000000 --- a/arch/arm/cpu/armv7/keystone/aemif.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Keystone2: Asynchronous EMIF Configuration - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) -#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) -#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26) -#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20) -#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17) -#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13) -#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7) -#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4) -#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2) -#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0) - -#define set_config_field(reg, field, val) \ - do { \ - if (val != -1) { \ - reg &= ~AEMIF_CFG_##field(0xffffffff); \ - reg |= AEMIF_CFG_##field(val); \ - } \ - } while (0) - -void configure_async_emif(int cs, struct async_emif_config *cfg) -{ - unsigned long tmp; - - if (cfg->mode == ASYNC_EMIF_MODE_NAND) { - tmp = __raw_readl(&davinci_emif_regs->nandfcr); - tmp |= (1 << cs); - __raw_writel(tmp, &davinci_emif_regs->nandfcr); - - } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) { - tmp = __raw_readl(&davinci_emif_regs->one_nand_cr); - tmp |= (1 << cs); - __raw_writel(tmp, &davinci_emif_regs->one_nand_cr); - } - - tmp = __raw_readl(&davinci_emif_regs->abncr[cs]); - - set_config_field(tmp, SELECT_STROBE, cfg->select_strobe); - set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); - set_config_field(tmp, WR_SETUP, cfg->wr_setup); - set_config_field(tmp, WR_STROBE, cfg->wr_strobe); - set_config_field(tmp, WR_HOLD, cfg->wr_hold); - set_config_field(tmp, RD_SETUP, cfg->rd_setup); - set_config_field(tmp, RD_STROBE, cfg->rd_strobe); - set_config_field(tmp, RD_HOLD, cfg->rd_hold); - set_config_field(tmp, TURN_AROUND, cfg->turn_around); - set_config_field(tmp, WIDTH, cfg->width); - - __raw_writel(tmp, &davinci_emif_regs->abncr[cs]); -} - -void init_async_emif(int num_cs, struct async_emif_config *config) -{ - int cs; - - for (cs = 0; cs < num_cs; cs++) - configure_async_emif(cs, config + cs); -} diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index 7ac2662f1fb..50ce649d4c0 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -9,13 +9,6 @@ #ifndef __ASM_ARCH_HARDWARE_K2HK_H #define __ASM_ARCH_HARDWARE_K2HK_H -#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE -#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 -#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000 -#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000 -#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000 - #define K2HK_PLL_CNTRL_BASE 0x02310000 #define CLOCK_BASE K2HK_PLL_CNTRL_BASE #define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8) diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 6c532ca8700..ffdecbfcd6d 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -22,32 +22,6 @@ typedef volatile unsigned int dv_reg; typedef volatile unsigned int *dv_reg_p; -#define ASYNC_EMIF_NUM_CS 4 -#define ASYNC_EMIF_MODE_NOR 0 -#define ASYNC_EMIF_MODE_NAND 1 -#define ASYNC_EMIF_MODE_ONENAND 2 -#define ASYNC_EMIF_PRESERVE -1 - -struct async_emif_config { - unsigned mode; - unsigned select_strobe; - unsigned extend_wait; - unsigned wr_setup; - unsigned wr_strobe; - unsigned wr_hold; - unsigned rd_setup; - unsigned rd_strobe; - unsigned rd_hold; - unsigned turn_around; - enum { - ASYNC_EMIF_8 = 0, - ASYNC_EMIF_16 = 1, - ASYNC_EMIF_32 = 2, - } width; -}; - -void init_async_emif(int num_cs, struct async_emif_config *config); - struct ddr3_phy_config { unsigned int pllcr; unsigned int pgcr1_mask; @@ -145,6 +119,10 @@ struct ddr3_emif_config { #define KS2_UART0_BASE 0x02530c00 #define KS2_UART1_BASE 0x02531000 +/* AEMIF */ +#define KS2_AEMIF_CNTRL_BASE 0x21000a00 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + #ifdef CONFIG_SOC_K2HK #include #endif diff --git a/arch/arm/include/asm/ti-common/ti-aemif.h b/arch/arm/include/asm/ti-common/ti-aemif.h new file mode 100644 index 00000000000..4a311d4a2f7 --- /dev/null +++ b/arch/arm/include/asm/ti-common/ti-aemif.h @@ -0,0 +1,39 @@ +/* + * AEMIF definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _AEMIF_H_ +#define _AEMIF_H_ + +#define AEMIF_NUM_CS 4 +#define AEMIF_MODE_NOR 0 +#define AEMIF_MODE_NAND 1 +#define AEMIF_MODE_ONENAND 2 +#define AEMIF_PRESERVE -1 + +struct aemif_config { + unsigned mode; + unsigned select_strobe; + unsigned extend_wait; + unsigned wr_setup; + unsigned wr_strobe; + unsigned wr_hold; + unsigned rd_setup; + unsigned rd_strobe; + unsigned rd_hold; + unsigned turn_around; + enum { + AEMIF_WIDTH_8 = 0, + AEMIF_WIDTH_16 = 1, + AEMIF_WIDTH_32 = 2, + } width; +}; + +void aemif_init(int num_cs, struct aemif_config *config); + +#endif diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c index 53f26b2ef33..ef90f9d8213 100644 --- a/board/ti/k2hk_evm/board.c +++ b/board/ti/k2hk_evm/board.c @@ -18,6 +18,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -39,9 +40,9 @@ unsigned int external_clk[ext_clk_count] = { what is that */ }; -static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = { +static struct aemif_config aemif_configs[] = { { /* CS0 */ - .mode = ASYNC_EMIF_MODE_NAND, + .mode = AEMIF_MODE_NAND, .wr_setup = 0xf, .wr_strobe = 0x3f, .wr_hold = 7, @@ -49,7 +50,7 @@ static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = { .rd_strobe = 0x3f, .rd_hold = 7, .turn_around = 3, - .width = ASYNC_EMIF_8, + .width = AEMIF_WIDTH_8, }, }; @@ -66,7 +67,7 @@ int dram_init(void) gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); - init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config); + aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); return 0; } diff --git a/drivers/Makefile b/drivers/Makefile index 5d03f37a187..b23076f614a 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -14,3 +14,4 @@ obj-y += twserial/ obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ +obj-y += memory/ diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile new file mode 100644 index 00000000000..9bfb9c785dc --- /dev/null +++ b/drivers/memory/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_TI_AEMIF) += ti-aemif.o diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c new file mode 100644 index 00000000000..f821daea4e1 --- /dev/null +++ b/drivers/memory/ti-aemif.c @@ -0,0 +1,80 @@ +/* + * Keystone2: Asynchronous EMIF Configuration + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define AEMIF_WAITCYCLE_CONFIG (CONFIG_AEMIF_CNTRL_BASE + 0x4) +#define AEMIF_NAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x60) +#define AEMIF_ONENAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x5c) +#define AEMIF_CONFIG(cs) (CONFIG_AEMIF_CNTRL_BASE + 0x10 \ + + (cs * 4)) + +#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) +#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) +#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26) +#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20) +#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17) +#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13) +#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7) +#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4) +#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2) +#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0) + +#define set_config_field(reg, field, val) \ + do { \ + if (val != -1) { \ + reg &= ~AEMIF_CFG_##field(0xffffffff); \ + reg |= AEMIF_CFG_##field(val); \ + } \ + } while (0) + +static void aemif_configure(int cs, struct aemif_config *cfg) +{ + unsigned long tmp; + + if (cfg->mode == AEMIF_MODE_NAND) { + tmp = __raw_readl(AEMIF_NAND_CONTROL); + tmp |= (1 << cs); + __raw_writel(tmp, AEMIF_NAND_CONTROL); + + } else if (cfg->mode == AEMIF_MODE_ONENAND) { + tmp = __raw_readl(AEMIF_ONENAND_CONTROL); + tmp |= (1 << cs); + __raw_writel(tmp, AEMIF_ONENAND_CONTROL); + } + + tmp = __raw_readl(AEMIF_CONFIG(cs)); + + set_config_field(tmp, SELECT_STROBE, cfg->select_strobe); + set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); + set_config_field(tmp, WR_SETUP, cfg->wr_setup); + set_config_field(tmp, WR_STROBE, cfg->wr_strobe); + set_config_field(tmp, WR_HOLD, cfg->wr_hold); + set_config_field(tmp, RD_SETUP, cfg->rd_setup); + set_config_field(tmp, RD_STROBE, cfg->rd_strobe); + set_config_field(tmp, RD_HOLD, cfg->rd_hold); + set_config_field(tmp, TURN_AROUND, cfg->turn_around); + set_config_field(tmp, WIDTH, cfg->width); + + __raw_writel(tmp, AEMIF_CONFIG(cs)); +} + +void aemif_init(int num_cs, struct aemif_config *config) +{ + int cs; + + if (num_cs > AEMIF_NUM_CS) { + num_cs = AEMIF_NUM_CS; + printf("AEMIF: csnum has to be <= 5"); + } + + for (cs = 0; cs < num_cs; cs++) + aemif_configure(cs, config + cs); +} diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index fcfbca92d18..858329f9586 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -129,6 +129,10 @@ #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 #define CONFIG_SYS_SGMII_RATESCALE 2 +/* AEMIF */ +#define CONFIG_TI_AEMIF +#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + /* NAND Configuration */ #define CONFIG_NAND_DAVINCI #define CONFIG_CMD_NAND_ECCLAYOUT -- cgit v1.3.1 From 7a4861fad0f6adc5d59a2c95899e47a0759af2b7 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Wed, 18 Jun 2014 09:09:34 +0800 Subject: spi: davinci: Fix register address for SPI1_BUS Fix a trivial copy-paste bug. Signed-off-by: Axel Lin --- drivers/spi/davinci_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 28fb3a2e9f8..0ec5b9d8592 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -41,7 +41,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, break; #ifdef CONFIG_SYS_SPI1 case SPI1_BUS: - ds->regs = (struct davinci_spi_regs *)SPI0_BASE; + ds->regs = (struct davinci_spi_regs *)SPI1_BASE; break; #endif #ifdef CONFIG_SYS_SPI2 -- cgit v1.3.1 From ae7f4513087e7f7996cebc9db642917dde9ea561 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 11 Jun 2014 23:29:45 -0600 Subject: dm: Rename struct device_id to udevice_id It is best to avoid having any occurence of 'struct device' in driver model, so rename to achieve this. Signed-off-by: Simon Glass --- doc/driver-model/README.txt | 2 +- drivers/core/lists.c | 2 +- drivers/demo/demo-shape.c | 2 +- drivers/demo/demo-simple.c | 2 +- drivers/gpio/sandbox.c | 2 +- include/dm/device.h | 6 +++--- test/dm/test-fdt.c | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt index a5035beca6e..0b295acbf91 100644 --- a/doc/driver-model/README.txt +++ b/doc/driver-model/README.txt @@ -315,7 +315,7 @@ is little or no 'driver model' code to write. - Moved some data from code into data structure - e.g. store a pointer to the driver operations structure in the driver, rather than passing it to the driver bind function. -- Rename some structures to make them more similar to Linux (struct device +- Rename some structures to make them more similar to Linux (struct udevice instead of struct instance, struct platdata, etc.) - Change the name 'core' to 'uclass', meaning U-Boot class. It seems that this concept relates to a class of drivers (or a subsystem). We shouldn't diff --git a/drivers/core/lists.c b/drivers/core/lists.c index 205b140ef3d..9f2917f4bb2 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -94,7 +94,7 @@ int lists_bind_drivers(struct udevice *parent) * tree error */ static int driver_check_compatible(const void *blob, int offset, - const struct device_id *of_match) + const struct udevice_id *of_match) { int ret; diff --git a/drivers/demo/demo-shape.c b/drivers/demo/demo-shape.c index a68cc1092cf..3fa9c599470 100644 --- a/drivers/demo/demo-shape.c +++ b/drivers/demo/demo-shape.c @@ -111,7 +111,7 @@ static int shape_ofdata_to_platdata(struct udevice *dev) return 0; } -static const struct device_id demo_shape_id[] = { +static const struct udevice_id demo_shape_id[] = { { "demo-shape", 0 }, { }, }; diff --git a/drivers/demo/demo-simple.c b/drivers/demo/demo-simple.c index 11def86032c..2bcb7dfb479 100644 --- a/drivers/demo/demo-simple.c +++ b/drivers/demo/demo-simple.c @@ -32,7 +32,7 @@ static int demo_shape_ofdata_to_platdata(struct udevice *dev) return demo_parse_dt(dev); } -static const struct device_id demo_shape_id[] = { +static const struct udevice_id demo_shape_id[] = { { "demo-simple", 0 }, { }, }; diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index 09cebe2286f..75ada5d3871 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -239,7 +239,7 @@ static int gpio_sandbox_probe(struct udevice *dev) return 0; } -static const struct device_id sandbox_gpio_ids[] = { +static const struct udevice_id sandbox_gpio_ids[] = { { .compatible = "sandbox,gpio" }, { } }; diff --git a/include/dm/device.h b/include/dm/device.h index ec049824e8c..19f20390d79 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -75,11 +75,11 @@ struct udevice { #define device_active(dev) ((dev)->flags & DM_FLAG_ACTIVATED) /** - * struct device_id - Lists the compatible strings supported by a driver + * struct udevice_id - Lists the compatible strings supported by a driver * @compatible: Compatible string * @data: Data for this compatible string */ -struct device_id { +struct udevice_id { const char *compatible; ulong data; }; @@ -121,7 +121,7 @@ struct device_id { struct driver { char *name; enum uclass_id id; - const struct device_id *of_match; + const struct udevice_id *of_match; int (*bind)(struct udevice *dev); int (*probe)(struct udevice *dev); int (*remove)(struct udevice *dev); diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index 6eccf111279..98e3936527e 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -53,7 +53,7 @@ static int testfdt_drv_probe(struct udevice *dev) return 0; } -static const struct device_id testfdt_ids[] = { +static const struct udevice_id testfdt_ids[] = { { .compatible = "denx,u-boot-fdt-test", .data = DM_TEST_TYPE_FIRST }, -- cgit v1.3.1 From 939cda5bf06205971c1e6849032144454017f200 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 11 Jun 2014 23:29:47 -0600 Subject: dm: Use case-insensitive comparison for GPIO banks We want 'N0' and 'n0' to mean the same thing, so ensure that case is not considered when naming GPIO banks. Signed-off-by: Simon Glass --- drivers/gpio/gpio-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index fa2c2fb7c47..f1bbc587961 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -58,7 +58,7 @@ int gpio_lookup_name(const char *name, struct udevice **devp, uc_priv = dev->uclass_priv; len = uc_priv->bank_name ? strlen(uc_priv->bank_name) : 0; - if (!strncmp(name, uc_priv->bank_name, len)) { + if (!strncasecmp(name, uc_priv->bank_name, len)) { if (strict_strtoul(name + len, 10, &offset)) continue; if (devp) -- cgit v1.3.1 From 6a6d8fbef7eb801a6babad8a62b1318d098ed7ed Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 11 Jun 2014 23:29:48 -0600 Subject: dm: Add missing header files in lists and root These files don't compile in some architectures. Fix it by adding the missing headers. Signed-off-by: Simon Glass --- drivers/core/lists.c | 1 + drivers/core/root.c | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/core/lists.c b/drivers/core/lists.c index 9f2917f4bb2..afb59d1d8dd 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -14,6 +14,7 @@ #include #include #include +#include #include struct driver *lists_driver_lookup_name(const char *name) diff --git a/drivers/core/root.c b/drivers/core/root.c index 4977875c7f9..f31be72cd05 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include -- cgit v1.3.1 From 89876a55a62f495302e2fd76094e45a65ca188b2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 11 Jun 2014 23:29:49 -0600 Subject: dm: Cast away the const-ness of the global_data pointer In a very few cases we need to adjust the driver model root device, such as when setting it up at initialisation. Add a macro to make this easier. Signed-off-by: Simon Glass --- drivers/core/root.c | 6 +++--- drivers/core/uclass.c | 2 +- include/dm/device-internal.h | 4 ++++ 3 files changed, 8 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/core/root.c b/drivers/core/root.c index f31be72cd05..1cbb096494d 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -43,9 +43,9 @@ int dm_init(void) dm_warn("Virtual root driver already exists!\n"); return -EINVAL; } - INIT_LIST_HEAD(&gd->uclass_root); + INIT_LIST_HEAD(&DM_UCLASS_ROOT_NON_CONST); - ret = device_bind_by_name(NULL, &root_info, &gd->dm_root); + ret = device_bind_by_name(NULL, &root_info, &DM_ROOT_NON_CONST); if (ret) return ret; @@ -56,7 +56,7 @@ int dm_scan_platdata(void) { int ret; - ret = lists_bind_drivers(gd->dm_root); + ret = lists_bind_drivers(DM_ROOT_NON_CONST); if (ret == -ENOENT) { dm_warn("Some drivers were not found\n"); ret = 0; diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index f6867e4a232..34723ec42a7 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -75,7 +75,7 @@ static int uclass_add(enum uclass_id id, struct uclass **ucp) uc->uc_drv = uc_drv; INIT_LIST_HEAD(&uc->sibling_node); INIT_LIST_HEAD(&uc->dev_head); - list_add(&uc->sibling_node, &gd->uclass_root); + list_add(&uc->sibling_node, &DM_UCLASS_ROOT_NON_CONST); if (uc_drv->init) { ret = uc_drv->init(uc); diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index ea3df36632d..26e5cf530eb 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -84,4 +84,8 @@ int device_remove(struct udevice *dev); */ int device_unbind(struct udevice *dev); +/* Cast away any volatile pointer */ +#define DM_ROOT_NON_CONST (((gd_t *)gd)->dm_root) +#define DM_UCLASS_ROOT_NON_CONST (((gd_t *)gd)->uclass_root) + #endif -- cgit v1.3.1 From e76d2a81bc350aebf4ae56753fb75983c7a4efdd Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Wed, 18 Jun 2014 17:52:41 +0530 Subject: Exynos: SPI: Fix reading data from SPI flash SPI recieve and transfer code in exynos_spi driver has a logical bug. We read data in a variable which can hold an integer. Then we assign this integer 32 bit value to another variable which has data type uchar. Latter represents a unit of our recieve buffer. Everytime when we write a value to our recieve buffer we step ahead by 4 units when actually we wrote to one unit. This results in the loss of 3 bytes out of every 4 bytes recieved. This patch intends to fix this bug. Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- drivers/spi/exynos_spi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index 4d5def2d319..c92276fdf71 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -302,7 +302,10 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, } } else { if (rxp || stopping) { - *rxp = temp; + if (step == 4) + *(uint32_t *)rxp = temp; + else + *rxp = temp; rxp += step; } in_bytes -= step; -- cgit v1.3.1 From 00d4796c555b95e986b4a01a9322d49f64c1349f Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Wed, 18 Jun 2014 22:13:52 +0200 Subject: PMIC: MAX77686: fix invalid bus check Since p->bus is unsigned checking for negative values is optimized away. Since bus is already used as an argument use tmp. While at it, don't declare variables in the middle of a function. cc: Rajeshwari Shinde Signed-off-by: Jeroen Hofstee Signed-off-by: Minkyu Kang --- drivers/power/pmic/pmic_max77686.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/power/pmic/pmic_max77686.c b/drivers/power/pmic/pmic_max77686.c index d4c430e22ed..df1fd91de38 100644 --- a/drivers/power/pmic/pmic_max77686.c +++ b/drivers/power/pmic/pmic_max77686.c @@ -210,6 +210,10 @@ int pmic_init(unsigned char bus) { static const char name[] = "MAX77686_PMIC"; struct pmic *p = pmic_alloc(); +#ifdef CONFIG_OF_CONTROL + const void *blob = gd->fdt_blob; + int node, parent, tmp; +#endif if (!p) { printf("%s: POWER allocation error!\n", __func__); @@ -217,9 +221,6 @@ int pmic_init(unsigned char bus) } #ifdef CONFIG_OF_CONTROL - const void *blob = gd->fdt_blob; - int node, parent; - node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_MAX77686_PMIC); if (node < 0) { debug("PMIC: No node for PMIC Chip in device tree\n"); @@ -233,11 +234,13 @@ int pmic_init(unsigned char bus) return -1; } - p->bus = i2c_get_bus_num_fdt(parent); - if (p->bus < 0) { + /* tmp since p->bus is unsigned */ + tmp = i2c_get_bus_num_fdt(parent); + if (tmp < 0) { debug("%s: Cannot find I2C bus\n", __func__); return -1; } + p->bus = tmp; p->hw.i2c.addr = fdtdec_get_int(blob, node, "reg", 9); #else p->bus = bus; -- cgit v1.3.1 From fb22ae6c7e0ffe438103c948c87c5ddf2ef56e7e Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 23 Jun 2014 12:02:48 -0600 Subject: usb: ci_udc: fix interaction with CONFIG_USB_ETH_CDC ci_udc.c's usb_gadget_unregister_driver() doesn't call driver->unbind() unlike other USB gadget drivers. Fix it to do this. Without this, when ether.c's CDC Ethernet device is torn down, eth_unbind() is never called, so dev->gadget is never set to NULL. For some reason, usb_eth_halt() is called both at the end of the first use of the Ethernet device, and prior to any subsequent use. Since dev->gadget is never cleared, all calls to usb_eth_halt() attempt to stop, disconnect, and clean up the device, resulting in double cleanup, which hangs U-Boot on my Tegra device at least. ci_udc allocates its own singleton EP0 request object, and cleans it up during usb_gadget_unregister_driver(). This appears necessary when using the USB gadget framework in U-Boot, since that does not allocate/free the EP0 request. However, the CDC Ethernet driver *does* allocate and free its own EP0 requests. Consequently, we must protect ci_ep_free_request() against double-freeing the request. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index b18bee43ad8..c3f6467b7db 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -226,8 +226,11 @@ static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req) int num; num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - if (num == 0) + if (num == 0) { + if (!controller.ep0_req) + return; controller.ep0_req = 0; + } if (ci_req->b_buf) free(ci_req->b_buf); @@ -909,6 +912,9 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) { udc_disconnect(); + driver->unbind(&controller.gadget); + controller.driver = NULL; + ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req); free(controller.items_mem); free(controller.epts); -- cgit v1.3.1 From 83c3750088aced8e5439fe889b3b8de7edea3aa8 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Jun 2014 11:03:18 -0600 Subject: usb: ci_udc: fix typo in debug message s/ot/to/ Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index c3f6467b7db..a6433e8d2d8 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -471,10 +471,10 @@ static int ci_ep_queue(struct usb_ep *ep, static void flip_ep0_direction(void) { if (ep0_desc.bEndpointAddress == USB_DIR_IN) { - DBG("%s: Flipping ep0 ot OUT\n", __func__); + DBG("%s: Flipping ep0 to OUT\n", __func__); ep0_desc.bEndpointAddress = 0; } else { - DBG("%s: Flipping ep0 ot IN\n", __func__); + DBG("%s: Flipping ep0 to IN\n", __func__); ep0_desc.bEndpointAddress = USB_DIR_IN; } } -- cgit v1.3.1 From 51afc2c68cb88a10e7b7910c4c4f7c50546b0963 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Tue, 17 Jun 2014 21:14:17 +0200 Subject: usb: cosmetic: double const For plain array const can be either before or after the type definition. Adding both is simply redundand. Remove the later one. cc: marex@denx.de Signed-off-by: Jeroen Hofstee --- drivers/usb/eth/asix.c | 2 +- drivers/usb/eth/mcs7830.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c index ce133f00698..6557055e02b 100644 --- a/drivers/usb/eth/asix.c +++ b/drivers/usb/eth/asix.c @@ -565,7 +565,7 @@ struct asix_dongle { int flags; }; -static const struct asix_dongle const asix_dongles[] = { +static const struct asix_dongle asix_dongles[] = { { 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */ { 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */ { 0x2001, 0x1a02, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver C1 */ diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c index c353286b60d..8e738d40e3f 100644 --- a/drivers/usb/eth/mcs7830.c +++ b/drivers/usb/eth/mcs7830.c @@ -666,7 +666,7 @@ struct mcs7830_dongle { /* * mcs7830_dongles - the list of supported Moschip based USB ethernet dongles */ -static const struct mcs7830_dongle const mcs7830_dongles[] = { +static const struct mcs7830_dongle mcs7830_dongles[] = { { 0x9710, 0x7832, }, /* Moschip 7832 */ { 0x9710, 0x7830, }, /* Moschip 7830 */ { 0x9710, 0x7730, }, /* Moschip 7730 */ -- cgit v1.3.1 From 8ecdce7280fff9347ba137ea7431664e1bf57534 Mon Sep 17 00:00:00 2001 From: yasuhisa umano Date: Fri, 18 Apr 2014 11:33:08 +0900 Subject: usb: r8a66597: Fix initialization hub that using R8A66597_MAX_ROOT_HUB This driver is processed as two USB hub despite one. The number of root hub is defined in R8A66597_MAX_ROOT_HUB. This fixes that register is accessed by using the definition of R8A66597_MAX_ROOT_HUB. Signed-off-by: Yasuhisa Umano --- drivers/usb/host/r8a66597-hcd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index dfe5423b8ab..c58d2a9d115 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -164,8 +164,8 @@ static int enable_controller(struct r8a66597 *r8a66597) r8a66597_bset(r8a66597, INTL, SOFCFG); r8a66597_write(r8a66597, 0, INTENB0); - r8a66597_write(r8a66597, 0, INTENB1); - r8a66597_write(r8a66597, 0, INTENB2); + for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) + r8a66597_write(r8a66597, 0, get_intenb_reg(port)); r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, CFIFOSEL); r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, D0FIFOSEL); -- cgit v1.3.1 From 198c5f998a1fbbdb5cfe6035f8c890ffb1526d8e Mon Sep 17 00:00:00 2001 From: Yasuhisa Umano Date: Fri, 18 Apr 2014 11:33:15 +0900 Subject: usb: r8a66597: Fix initilization size of r8a66597 info structure Initialization of r8a66597 info structure is not enough. Because initilization was used size of pointer. This fixes that use size of r8a6659 info structure. Signed-off-by: Yasuhisa Umano --- drivers/usb/host/r8a66597-hcd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index c58d2a9d115..511454479b1 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -807,7 +807,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) R8A66597_DPRINT("%s\n", __func__); - memset(r8a66597, 0, sizeof(r8a66597)); + memset(r8a66597, 0, sizeof(*r8a66597)); r8a66597->reg = CONFIG_R8A66597_BASE_ADDR; disable_controller(r8a66597); -- cgit v1.3.1 From 933611f7bbeb1b29218dca74cf1acfa910006cef Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Mon, 9 Jun 2014 15:28:59 +0200 Subject: usb:composite: clear the whole common buffer Since the struct fsg_common is calloced, reset it completely with zero's when reused. While at it, make checkpatch happy. cc: Lukasz Majewski cc: Piotr Wilczek cc: Kyungmin Park cc: Marek Vasut Signed-off-by: Jeroen Hofstee Acked-by: Marek Vasut Acked-by: Lukasz Majewski --- drivers/usb/gadget/f_mass_storage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index 6374bb953a9..f274d9679fb 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -2462,12 +2462,12 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common, /* Allocate? */ if (!common) { - common = calloc(sizeof *common, 1); + common = calloc(sizeof(*common), 1); if (!common) return ERR_PTR(-ENOMEM); common->free_storage_on_release = 1; } else { - memset(common, 0, sizeof common); + memset(common, 0, sizeof(*common)); common->free_storage_on_release = 0; } -- cgit v1.3.1 From 19a2a67fa27ac5bf50808bbded5c19279c7d86e5 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Mon, 9 Jun 2014 15:28:58 +0200 Subject: usb:g_dnl:f_thor: remove memset before memcpy since ALLOC_CACHE_ALIGN_BUFFER defines a pointer and not a buffer, the memset with sizeof(rqt) likely does something else then intended. Since there is a memcpy directly after it with the full size, drop the memset completely. Cc: Lukasz Majewski Cc: Marek Vasut Signed-off-by: Jeroen Hofstee Acked-by: Lukasz Majewski --- drivers/usb/gadget/f_thor.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index 28f215e07c6..4e06273f7fb 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -306,7 +306,6 @@ static int process_data(void) ALLOC_CACHE_ALIGN_BUFFER(struct rqt_box, rqt, sizeof(struct rqt_box)); int ret = -EINVAL; - memset(rqt, 0, sizeof(rqt)); memcpy(rqt, thor_rx_data_buf, sizeof(struct rqt_box)); debug("+RQT: %d, %d\n", rqt->rqt, rqt->rqt_data); -- cgit v1.3.1 From 25d1936a192ac62b8df5dc33e37455dcaeb19fae Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Thu, 12 Jun 2014 00:31:27 +0200 Subject: usb: xhci: (likely) fix bracket in if condition Because of the brackets the & and && is evaluated before the comparison. This is likely not the intention. Change it to test the first and second condition to both be true. cc: Marek Vasut Signed-off-by: Jeroen Hofstee --- drivers/usb/host/xhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index d1c2e5c4551..59dc096b0c3 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -643,8 +643,8 @@ static int xhci_submit_root(struct usb_device *udev, unsigned long pipe, struct xhci_ctrl *ctrl = udev->controller; struct xhci_hcor *hcor = ctrl->hcor; - if (((req->requesttype & USB_RT_PORT) && - le16_to_cpu(req->index)) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) { + if ((req->requesttype & USB_RT_PORT) && + le16_to_cpu(req->index) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) { printf("The request port(%d) is not configured\n", le16_to_cpu(req->index) - 1); return -EINVAL; -- cgit v1.3.1 From 29425be49bf301b55807dd27f55678e6d0a81060 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Sat, 14 Jun 2014 00:57:14 +0200 Subject: usb: fastboot: fix potential buffer overflow cb_getvar tries to prevent overflowing the response buffer by using strncat. But strncat takes the number of data bytes copied as a limit not the total buffer length so it can still overflow. Pass the correct value instead. cc: Sebastian Andrzej Siewior cc: Rob Herring Signed-off-by: Jeroen Hofstee --- drivers/usb/gadget/f_fastboot.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 9dd85b636e9..7a1acb9df02 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -331,8 +331,11 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) char *cmd = req->buf; char response[RESPONSE_LEN]; const char *s; + size_t chars_left; strcpy(response, "OKAY"); + chars_left = sizeof(response) - strlen(response) - 1; + strsep(&cmd, ":"); if (!cmd) { fastboot_tx_write_str("FAILmissing var"); @@ -340,18 +343,18 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) } if (!strcmp_l1("version", cmd)) { - strncat(response, FASTBOOT_VERSION, sizeof(response)); + strncat(response, FASTBOOT_VERSION, chars_left); } else if (!strcmp_l1("bootloader-version", cmd)) { - strncat(response, U_BOOT_VERSION, sizeof(response)); + strncat(response, U_BOOT_VERSION, chars_left); } else if (!strcmp_l1("downloadsize", cmd)) { char str_num[12]; sprintf(str_num, "%08x", CONFIG_USB_FASTBOOT_BUF_SIZE); - strncat(response, str_num, sizeof(response)); + strncat(response, str_num, chars_left); } else if (!strcmp_l1("serialno", cmd)) { s = getenv("serial#"); if (s) - strncat(response, s, sizeof(response)); + strncat(response, s, chars_left); else strcpy(response, "FAILValue not set"); } else { -- cgit v1.3.1 From 08ebd467c8649493404e5cc513abd096076c733e Mon Sep 17 00:00:00 2001 From: Ilya Ledvich Date: Wed, 12 Mar 2014 10:36:31 +0200 Subject: usb: eth: smsc95xx: add LAN9500A device ID Add LAN9500A product ID (0x9e00) in order to support LAN9500A based dongles. Tested on cm_t335. Signed-off-by: Ilya Ledvich Acked-by: Marek Vasut --- drivers/usb/eth/smsc95xx.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index 7bf0a340788..7a7a6767c70 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -799,6 +799,7 @@ static const struct smsc95xx_dongle smsc95xx_dongles[] = { { 0x0424, 0x9500 }, /* LAN9500 Ethernet */ { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */ { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */ + { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */ { 0x0000, 0x0000 } /* END - Do not remove */ }; -- cgit v1.3.1 From d7beeb9358a93e2dfd01e0ab5ff4317ce106c4d7 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 1 Jul 2014 11:41:13 -0600 Subject: usb: ci_udc: fix ci_flush_{qh,qtd} calls in ci_udc_probe() ci_udc_probe() initializes a pair of QHs and QTDs for each EP. After each pair has been initialized, the pair is cache-flushed. The conversion from QH/QTD index [0..2*NUM_END_POINTS) to EP index [0..NUM_ENDPOINTS] is incorrect; it simply subtracts 1 (which yields the QH/QTD index of the first entry in the pair) rather than dividing by two (which scales the range). Fix this. On my system, this avoids cache debug prints due to requests to flush unaligned ranges. This is caused because the flush calls happen before the items[] array entries are initialized for all but EP0. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index a6433e8d2d8..8ba604841c4 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -834,8 +834,8 @@ static int ci_udc_probe(void) controller.items[i] = (struct ept_queue_item *)imem; if (i & 1) { - ci_flush_qh(i - 1); - ci_flush_qtd(i - 1); + ci_flush_qh(i / 2); + ci_flush_qtd(i / 2); } } -- cgit v1.3.1 From 8d7c39d3e8ad43dab3158220f3347186e6f1aa66 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 1 Jul 2014 11:41:14 -0600 Subject: usb: ci_udc: don't assume QTDs are adjacent when transmitting ZLPs Fix ci_ep_submit_next_request()'s ZLP transmission code to explicitly call ci_get_qtd() to find the address of the other QTD to use. This will allow us to correctly align each QTD individually in the future, which may involve leaving a gap between the QTDs. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 8ba604841c4..4115cd5dab0 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -404,10 +404,11 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) * only 1 is used at a time since either an IN or an OUT but * not both is queued. For an IN transaction, item currently * points at the second of these items, so we know that we - * can use (item - 1) to transmit the extra zero-length packet + * can use the other to transmit the extra zero-length packet. */ - item->next = (unsigned)(item - 1); - item--; + struct ept_queue_item *other_item = ci_get_qtd(num, 0); + item->next = (unsigned)other_item; + item = other_item; item->info = INFO_ACTIVE; } -- cgit v1.3.1 From 06b38fcbae9294d337578d583309f99de12a0d23 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 1 Jul 2014 11:41:15 -0600 Subject: usb: ci_udc: lift ilist size calculations to global scope This will allow functions other than ci_udc_probe() to make use of the constants in a future change. This in turn requires converting the const int variables to #defines, since the initialization of one global const int can't depend on the value of another const int; the compiler thinks it's non-constant if that dependency exists. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 4115cd5dab0..3a114cf11e1 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -34,6 +34,17 @@ #error This driver can not work on systems with caches longer than 128b #endif +/* + * Each qTD item must be 32-byte aligned, each qTD touple must be + * cacheline aligned. There are two qTD items for each endpoint and + * only one of them is used for the endpoint at time, so we can group + * them together. + */ +#define ILIST_ALIGN roundup(ARCH_DMA_MINALIGN, 32) +#define ILIST_ENT_RAW_SZ (2 * sizeof(struct ept_queue_item)) +#define ILIST_ENT_SZ roundup(ILIST_ENT_RAW_SZ, ARCH_DMA_MINALIGN) +#define ILIST_SZ (NUM_ENDPOINTS * ILIST_ENT_SZ) + #ifndef DEBUG #define DBG(x...) do {} while (0) #else @@ -786,29 +797,18 @@ static int ci_udc_probe(void) const int eplist_raw_sz = num * sizeof(struct ept_queue_head); const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN); - const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32); - const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item); - const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN); - const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz; - /* The QH list must be aligned to 4096 bytes. */ controller.epts = memalign(eplist_align, eplist_sz); if (!controller.epts) return -ENOMEM; memset(controller.epts, 0, eplist_sz); - /* - * Each qTD item must be 32-byte aligned, each qTD touple must be - * cacheline aligned. There are two qTD items for each endpoint and - * only one of them is used for the endpoint at time, so we can group - * them together. - */ - controller.items_mem = memalign(ilist_align, ilist_sz); + controller.items_mem = memalign(ILIST_ALIGN, ILIST_SZ); if (!controller.items_mem) { free(controller.epts); return -ENOMEM; } - memset(controller.items_mem, 0, ilist_sz); + memset(controller.items_mem, 0, ILIST_SZ); for (i = 0; i < 2 * NUM_ENDPOINTS; i++) { /* @@ -828,7 +828,7 @@ static int ci_udc_probe(void) head->next = TERMINATE; head->info = 0; - imem = controller.items_mem + ((i >> 1) * ilist_ent_sz); + imem = controller.items_mem + ((i >> 1) * ILIST_ENT_SZ); if (i & 1) imem += sizeof(struct ept_queue_item); -- cgit v1.3.1 From 7e5418877550d8d7a9a2c5d73f93fc95ecd595a9 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 1 Jul 2014 11:41:16 -0600 Subject: usb: ci_udc: fix items array size/stride calculation 2 QTDs are allocated for each EP. The current allocation scheme aligns the first QTD in each pair, but simply adds the struct size to calculate the second QTD's address. This will result in a non-cache-aligned addresss IF the system's ARCH_DMA_MINALIGN is not 32 bytes (i.e. the size of struct ept_queue_item). Similarly, the original ilist_ent_sz calculation aligned the value to ARCH_DMA_MINALIGN but didn't take the USB HW's 32-byte alignment requirement into account. This doesn't cause a practical issue unless ARCH_DMA_MINALIGN < 32 (which I suspect is quite unlikely), but we may as well fix the code to be explicit, so it's obviously completely correct. The new value of ILIST_ENT_SZ takes all alignment requirements into account, so we can simplify ci_{flush,invalidate}_qtd() by simply using that macro rather than calling roundup(). Similarly, the calculation of controller.items[i] can be simplified, since each QTD is evenly spaced at its individual alignment requirement, rather than each pair being aligned, and entries within the pair being spaced apart only by structure size. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 3a114cf11e1..abaf8985503 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -35,15 +35,20 @@ #endif /* - * Each qTD item must be 32-byte aligned, each qTD touple must be - * cacheline aligned. There are two qTD items for each endpoint and - * only one of them is used for the endpoint at time, so we can group - * them together. + * Every QTD must be individually aligned, since we can program any + * QTD's address into HW. Cache flushing requires ARCH_DMA_MINALIGN, + * and the USB HW requires 32-byte alignment. Align to both: */ #define ILIST_ALIGN roundup(ARCH_DMA_MINALIGN, 32) -#define ILIST_ENT_RAW_SZ (2 * sizeof(struct ept_queue_item)) -#define ILIST_ENT_SZ roundup(ILIST_ENT_RAW_SZ, ARCH_DMA_MINALIGN) -#define ILIST_SZ (NUM_ENDPOINTS * ILIST_ENT_SZ) +/* Each QTD is this size */ +#define ILIST_ENT_RAW_SZ sizeof(struct ept_queue_item) +/* + * Align the size of the QTD too, so we can add this value to each + * QTD's address to get another aligned address. + */ +#define ILIST_ENT_SZ roundup(ILIST_ENT_RAW_SZ, ILIST_ALIGN) +/* For each endpoint, we need 2 QTDs, one for each of IN and OUT */ +#define ILIST_SZ (NUM_ENDPOINTS * 2 * ILIST_ENT_SZ) #ifndef DEBUG #define DBG(x...) do {} while (0) @@ -184,8 +189,7 @@ static void ci_flush_qtd(int ep_num) { struct ept_queue_item *item = ci_get_qtd(ep_num, 0); const uint32_t start = (uint32_t)item; - const uint32_t end_raw = start + 2 * sizeof(*item); - const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); + const uint32_t end = start + 2 * ILIST_ENT_SZ; flush_dcache_range(start, end); } @@ -200,8 +204,7 @@ static void ci_invalidate_qtd(int ep_num) { struct ept_queue_item *item = ci_get_qtd(ep_num, 0); const uint32_t start = (uint32_t)item; - const uint32_t end_raw = start + 2 * sizeof(*item); - const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); + const uint32_t end = start + 2 * ILIST_ENT_SZ; invalidate_dcache_range(start, end); } @@ -828,10 +831,7 @@ static int ci_udc_probe(void) head->next = TERMINATE; head->info = 0; - imem = controller.items_mem + ((i >> 1) * ILIST_ENT_SZ); - if (i & 1) - imem += sizeof(struct ept_queue_item); - + imem = controller.items_mem + (i * ILIST_ENT_SZ); controller.items[i] = (struct ept_queue_item *)imem; if (i & 1) { -- cgit v1.3.1 From 6ac15fda4e2b9ad45b7769037964110f7f597b5c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 1 Jul 2014 11:41:17 -0600 Subject: usb: ci_udc: remove controller.items array There's no need to store an array of QTD pointers in the controller. Since the calculation is so simple, just have ci_get_qtd() perform it at run-time, rather than pre-calculating everything. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 8 +++----- drivers/usb/gadget/ci_udc.h | 1 - 2 files changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index abaf8985503..89138675c32 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -146,7 +146,9 @@ static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in) */ static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in) { - return controller.items[(ep_num * 2) + dir_in]; + int index = (ep_num * 2) + dir_in; + uint8_t *imem = controller.items_mem + (index * ILIST_ENT_SZ); + return (struct ept_queue_item *)imem; } /** @@ -790,7 +792,6 @@ static int ci_pullup(struct usb_gadget *gadget, int is_on) static int ci_udc_probe(void) { struct ept_queue_head *head; - uint8_t *imem; int i; const int num = 2 * NUM_ENDPOINTS; @@ -831,9 +832,6 @@ static int ci_udc_probe(void) head->next = TERMINATE; head->info = 0; - imem = controller.items_mem + (i * ILIST_ENT_SZ); - controller.items[i] = (struct ept_queue_item *)imem; - if (i & 1) { ci_flush_qh(i / 2); ci_flush_qtd(i / 2); diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h index c2144021e67..346164a6413 100644 --- a/drivers/usb/gadget/ci_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -102,7 +102,6 @@ struct ci_drv { struct usb_gadget_driver *driver; struct ehci_ctrl *ctrl; struct ept_queue_head *epts; - struct ept_queue_item *items[2 * NUM_ENDPOINTS]; uint8_t *items_mem; struct ci_ep ep[NUM_ENDPOINTS]; }; -- cgit v1.3.1 From 639e9903c20611772cb38433add6fe2383b9fabf Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 1 Jul 2014 11:41:18 -0600 Subject: usb: ci_udc: don't memalign() struct ci_req allocations struct ci_req is a purely software structure, and needs no specific memory alignment. Hence, allocate it with calloc() rather than memalign(). The use of memalign() was left-over from when struct ci_req was going to hold the aligned bounce buffer, but this is now dynamically allocated. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 89138675c32..b8c36523eb1 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -222,12 +222,11 @@ ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) if (num == 0 && controller.ep0_req) return &controller.ep0_req->req; - ci_req = memalign(ARCH_DMA_MINALIGN, sizeof(*ci_req)); + ci_req = calloc(1, sizeof(*ci_req)); if (!ci_req) return NULL; INIT_LIST_HEAD(&ci_req->queue); - ci_req->b_buf = 0; if (num == 0) controller.ep0_req = ci_req; -- cgit v1.3.1 From 369d3c439a39dea6020e3a5ae25821b0832822da Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 1 Jul 2014 16:59:08 -0600 Subject: USB: gadget: atmel: zero out allocated requests A UDC's alloc_request method should zero out the newly allocated request. Ensure the Atmel driver does so. This issue was found by code inspection, following the investigation of an intermittent issue with ci_udc, which was tracked down to failing to zero out allocated requests following some of my changes. All other UDC drivers already zero out requests in one way or another. Signed-off-by: Stephen Warren --- drivers/usb/gadget/atmel_usba_udc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c index c99208d1020..2c709738a3c 100644 --- a/drivers/usb/gadget/atmel_usba_udc.c +++ b/drivers/usb/gadget/atmel_usba_udc.c @@ -314,7 +314,7 @@ usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags); - req = malloc(sizeof(struct usba_request)); + req = calloc(1, sizeof(struct usba_request)); if (!req) return NULL; -- cgit v1.3.1 From dcb89b5aa0a90f791a594e0177cb144fdccec784 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 1 Jul 2014 14:22:27 -0600 Subject: usb: ci_udc: use var name ep/ci_ep consistently Almost all of ci_udc.c uses variable name "ep" for a struct usb_ep and "ci_ep" for a struct ci_ep. This is nice and consistent, and helps people know what type a variable is without searching for the declaration. handle_ep_complete() doesn't do this, so fix it to be consistent. Signed-off-by: Stephen Warren --- drivers/usb/gadget/ci_udc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index b8c36523eb1..4cd19c3afd2 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -495,14 +495,14 @@ static void flip_ep0_direction(void) } } -static void handle_ep_complete(struct ci_ep *ep) +static void handle_ep_complete(struct ci_ep *ci_ep) { struct ept_queue_item *item; int num, in, len; struct ci_req *ci_req; - num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; item = ci_get_qtd(num, in); ci_invalidate_qtd(num); @@ -511,12 +511,12 @@ static void handle_ep_complete(struct ci_ep *ep) printf("EP%d/%s FAIL info=%x pg0=%x\n", num, in ? "in" : "out", item->info, item->page0); - ci_req = list_first_entry(&ep->queue, struct ci_req, queue); + ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); list_del_init(&ci_req->queue); - ep->req_primed = false; + ci_ep->req_primed = false; - if (!list_empty(&ep->queue)) - ci_ep_submit_next_request(ep); + if (!list_empty(&ci_ep->queue)) + ci_ep_submit_next_request(ci_ep); ci_req->req.actual = ci_req->req.length - len; ci_debounce(ci_req, in); @@ -524,7 +524,7 @@ static void handle_ep_complete(struct ci_ep *ep) DBG("ept%d %s req %p, complete %x\n", num, in ? "in" : "out", ci_req, len); if (num != 0 || controller.ep0_data_phase) - ci_req->req.complete(&ep->ep, &ci_req->req); + ci_req->req.complete(&ci_ep->ep, &ci_req->req); if (num == 0 && controller.ep0_data_phase) { /* * Data Stage is complete, so flip ep0 dir for Status Stage, @@ -534,7 +534,7 @@ static void handle_ep_complete(struct ci_ep *ep) flip_ep0_direction(); controller.ep0_data_phase = false; ci_req->req.length = 0; - usb_ep_queue(&ep->ep, &ci_req->req, 0); + usb_ep_queue(&ci_ep->ep, &ci_req->req, 0); } } -- cgit v1.3.1 From 68049a082b8aedf09e769e61885e000e598bb516 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Jun 2014 10:57:27 -0600 Subject: i2c: tegra: use repeated start for reads I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Signed-off-by: Stephen Warren Reviewed-by: Yen Lin --- arch/arm/include/asm/arch-tegra/tegra_i2c.h | 2 ++ drivers/i2c/tegra_i2c.c | 24 ++++++++++++++++-------- 2 files changed, 18 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index 853e59bb6e6..7ca690700cb 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -124,6 +124,8 @@ struct i2c_ctlr { /* bit fields definitions for IO Packet Header 3 format */ #define PKT_HDR3_READ_MODE_SHIFT 19 #define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) +#define PKT_HDR3_REPEAT_START_SHIFT 16 +#define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT) #define PKT_HDR3_SLAVE_ADDR_SHIFT 0 #define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 594e5ddeb43..97f0ca44c59 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -110,7 +110,8 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) static void send_packet_headers( struct i2c_bus *i2c_bus, struct i2c_trans_info *trans, - u32 packet_id) + u32 packet_id, + bool end_with_repeated_start) { u32 data; @@ -132,6 +133,8 @@ static void send_packet_headers( /* Enable Read if it is not a write transaction */ if (!(trans->flags & I2C_IS_WRITE)) data |= PKT_HDR3_READ_MODE_MASK; + if (end_with_repeated_start) + data |= PKT_HDR3_REPEAT_START_MASK; /* Write I2C specific header */ writel(data, &i2c_bus->control->tx_fifo); @@ -209,7 +212,8 @@ static int send_recv_packets(struct i2c_bus *i2c_bus, int_status = readl(&control->int_status); writel(int_status, &control->int_status); - send_packet_headers(i2c_bus, trans, 1); + send_packet_headers(i2c_bus, trans, 1, + trans->flags & I2C_USE_REPEATED_START); words = DIV_ROUND_UP(trans->num_bytes, 4); last_bytes = trans->num_bytes & 3; @@ -267,7 +271,7 @@ exit: } static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data, - u32 len) + u32 len, bool end_with_repeated_start) { int error; struct i2c_trans_info trans_info; @@ -275,6 +279,8 @@ static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data, trans_info.address = addr; trans_info.buf = data; trans_info.flags = I2C_IS_WRITE; + if (end_with_repeated_start) + trans_info.flags |= I2C_USE_REPEATED_START; trans_info.num_bytes = len; trans_info.is_10bit_address = 0; @@ -463,7 +469,8 @@ static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) } /* i2c write version without the register address */ -int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len) +int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len, + bool end_with_repeated_start) { int rc; @@ -475,7 +482,8 @@ int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len) debug("\n"); /* Shift 7-bit address over for lower-level i2c functions */ - rc = tegra_i2c_write_data(bus, chip << 1, buffer, len); + rc = tegra_i2c_write_data(bus, chip << 1, buffer, len, + end_with_repeated_start); if (rc) debug("i2c_write_data(): rc=%d\n", rc); @@ -516,7 +524,7 @@ static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip) if (!bus) return 1; reg = 0; - rc = i2c_write_data(bus, chip, ®, 1); + rc = i2c_write_data(bus, chip, ®, 1, false); if (rc) { debug("Error probing 0x%x.\n", chip); return 1; @@ -554,7 +562,7 @@ static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, data[alen - i - 1] = (addr + offset) >> (8 * i); } - if (i2c_write_data(bus, chip, data, alen)) { + if (i2c_write_data(bus, chip, data, alen, true)) { debug("i2c_read: error sending (0x%x)\n", addr); return 1; @@ -591,7 +599,7 @@ static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, for (i = 0; i < alen; i++) data[alen - i - 1] = (addr + offset) >> (8 * i); data[alen] = buffer[offset]; - if (i2c_write_data(bus, chip, data, alen + 1)) { + if (i2c_write_data(bus, chip, data, alen + 1, false)) { debug("i2c_write: error sending (0x%x)\n", addr); return 1; } -- cgit v1.3.1 From 981b14f01ae79f85eae3dc6873456abd08de2d86 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Jun 2014 10:57:28 -0600 Subject: i2c: tegra: write clean data to TX FIFO The Tegra I2C controller's TX FIFO contains 32-bit words. If the final FIFO entry of a transaction contains fewer than 4 bytes, the driver currently fills the unused FIFO bytes with uninitialized data. This can be confusing when reading back the FIFO content for debugging purposes. Solve this by explicitly initializing the variable containing FIFO data before filling it (partially) with data. With this change, send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e. read) branch. Signed-off-by: Stephen Warren Reviewed-by: Yen Lin --- drivers/i2c/tegra_i2c.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 97f0ca44c59..a62f30e66ce 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -224,14 +224,16 @@ static int send_recv_packets(struct i2c_bus *i2c_bus, if (is_write) { /* deal with word alignment */ - if ((unsigned)dptr & 3) { + if ((words == 1) && last_bytes) { + local = 0; + memcpy(&local, dptr, last_bytes); + } else if ((unsigned)dptr & 3) { memcpy(&local, dptr, sizeof(u32)); - writel(local, &control->tx_fifo); - debug("pkt data sent (0x%x)\n", local); } else { - writel(*wptr, &control->tx_fifo); - debug("pkt data sent (0x%x)\n", *wptr); + local = *wptr; } + writel(local, &control->tx_fifo); + debug("pkt data sent (0x%x)\n", local); if (!wait_for_tx_fifo_empty(control)) { error = -1; goto exit; -- cgit v1.3.1 From ad3091ad03e39f88c0bcc566c7a691c4475e2c40 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Jun 2014 10:57:29 -0600 Subject: i2c: tegra: dump alen in debug statements Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump the address length (alen) too, so the address value can be correctly interpreted. Signed-off-by: Stephen Warren Reviewed-by: Yen Lin --- drivers/i2c/tegra_i2c.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index a62f30e66ce..257b72f0f7c 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -548,8 +548,8 @@ static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, uint offset; int i; - debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n", - chip, addr, len); + debug("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n", + chip, addr, alen, len); bus = tegra_i2c_get_bus(adap); if (!bus) return 1; @@ -587,8 +587,8 @@ static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, uint offset; int i; - debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n", - chip, addr, len); + debug("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n", + chip, addr, alen, len); bus = tegra_i2c_get_bus(adap); if (!bus) return 1; -- cgit v1.3.1 From 2f78eae5064728d6cd907148cfeaf8ba3e63b0ef Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 23 Jun 2014 15:15:54 -0700 Subject: ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun Signed-off-by: Varun Sethi Signed-off-by: Arnab Basu --- arch/arm/cpu/armv8/cache_v8.c | 7 +- arch/arm/cpu/armv8/fsl-lsch3/Makefile | 9 + arch/arm/cpu/armv8/fsl-lsch3/README | 10 + arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 425 ++++++++++++++++++++++ arch/arm/cpu/armv8/fsl-lsch3/cpu.h | 7 + arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 65 ++++ arch/arm/cpu/armv8/fsl-lsch3/speed.c | 176 +++++++++ arch/arm/cpu/armv8/fsl-lsch3/speed.h | 7 + arch/arm/include/asm/arch-fsl-lsch3/clock.h | 23 ++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 65 ++++ arch/arm/include/asm/arch-fsl-lsch3/gpio.h | 9 + arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 116 ++++++ arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h | 13 + arch/arm/include/asm/config.h | 4 + arch/arm/include/asm/system.h | 2 + drivers/i2c/mxc_i2c.c | 5 + include/common.h | 5 +- 17 files changed, 944 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/Makefile create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/README create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/cpu.c create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/cpu.h create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/speed.c create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/speed.h create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/clock.h create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/config.h create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/gpio.h create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h (limited to 'drivers') diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index af3c4945ecb..9dbcdf22afe 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -73,12 +73,17 @@ void invalidate_dcache_all(void) __asm_invalidate_dcache_all(); } +void __weak flush_l3_cache(void) +{ +} + /* * Performs a clean & invalidation of the entire data cache at all levels */ void flush_dcache_all(void) { __asm_flush_dcache_all(); + flush_l3_cache(); } /* @@ -211,7 +216,7 @@ void invalidate_icache_all(void) * Enable dCache & iCache, whether cache is actually enabled * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF */ -void enable_caches(void) +void __weak enable_caches(void) { icache_enable(); dcache_enable(); diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile new file mode 100644 index 00000000000..9249537c65a --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2014, Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += lowlevel.o +obj-y += speed.o diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README new file mode 100644 index 00000000000..de34a91da54 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -0,0 +1,10 @@ +# +# Copyright 2014 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Freescale LayerScape with Chassis Generation 3 + +This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, +for example LS2100A. diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c new file mode 100644 index 00000000000..46965f08ad3 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -0,0 +1,425 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "cpu.h" +#include "speed.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_DCACHE_OFF +/* + * To start MMU before DDR is available, we create MMU table in SRAM. + * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three + * levels of translation tables here to cover 40-bit address space. + * We use 4KB granule size, with 40 bits physical address, T0SZ=24 + * Level 0 IA[39], table address @0 + * Level 1 IA[31:30], table address @01000, 0x2000 + * Level 2 IA[29:21], table address @0x3000 + */ + +#define SECTION_SHIFT_L0 39UL +#define SECTION_SHIFT_L1 30UL +#define SECTION_SHIFT_L2 21UL +#define BLOCK_SIZE_L0 0x8000000000UL +#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) +#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) +#define CONFIG_SYS_IFC_BASE 0x30000000 +#define CONFIG_SYS_IFC_SIZE 0x10000000 +#define CONFIG_SYS_IFC_BASE2 0x500000000 +#define CONFIG_SYS_IFC_SIZE2 0x100000000 +#define TCR_EL2_PS_40BIT (2 << 16) +#define LSCH3_VA_BITS (40) +#define LSCH3_TCR (TCR_TG0_4K | \ + TCR_EL2_PS_40BIT | \ + TCR_SHARED_NON | \ + TCR_ORGN_NC | \ + TCR_IRGN_NC | \ + TCR_T0SZ(LSCH3_VA_BITS)) + +/* + * Final MMU + * Let's start from the same layout as early MMU and modify as needed. + * IFC regions will be cache-inhibit. + */ +#define FINAL_QBMAN_CACHED_MEM 0x818000000UL +#define FINAL_QBMAN_CACHED_SIZE 0x4000000 + + +static inline void early_mmu_setup(void) +{ + int el; + u64 i; + u64 section_l1t0, section_l1t1, section_l2; + u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE; + u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000); + u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); + u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); + + + level0_table[0] = + (u64)level1_table_0 | PMD_TYPE_TABLE; + level0_table[1] = + (u64)level1_table_1 | PMD_TYPE_TABLE; + + /* + * set level 1 table 0 to cache_inhibit, covering 0 to 512GB + * set level 1 table 1 to cache enabled, covering 512GB to 1TB + * set level 2 table to cache-inhibit, covering 0 to 1GB + */ + section_l1t0 = 0; + section_l1t1 = BLOCK_SIZE_L0; + section_l2 = 0; + for (i = 0; i < 512; i++) { + set_pgtable_section(level1_table_0, i, section_l1t0, + MT_DEVICE_NGNRNE); + set_pgtable_section(level1_table_1, i, section_l1t1, + MT_NORMAL); + set_pgtable_section(level2_table, i, section_l2, + MT_DEVICE_NGNRNE); + section_l1t0 += BLOCK_SIZE_L1; + section_l1t1 += BLOCK_SIZE_L1; + section_l2 += BLOCK_SIZE_L2; + } + + level1_table_0[0] = + (u64)level2_table | PMD_TYPE_TABLE; + level1_table_0[1] = + 0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT | + PMD_ATTRINDX(MT_DEVICE_NGNRNE); + level1_table_0[2] = + 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | + PMD_ATTRINDX(MT_NORMAL); + level1_table_0[3] = + 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | + PMD_ATTRINDX(MT_NORMAL); + + /* Rewrite table to enable cache */ + set_pgtable_section(level2_table, + CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, + CONFIG_SYS_FSL_OCRAM_BASE, + MT_NORMAL); + for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2; + i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE) + >> SECTION_SHIFT_L2; i++) { + section_l2 = i << SECTION_SHIFT_L2; + set_pgtable_section(level2_table, i, + section_l2, MT_NORMAL); + } + + el = current_el(); + set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES); + set_sctlr(get_sctlr() | CR_M); +} + +/* + * This final tale looks similar to early table, but different in detail. + * These tables are in regular memory. Cache on IFC is disabled. One sub table + * is added to enable cache for QBMan. + */ +static inline void final_mmu_setup(void) +{ + int el; + u64 i, tbl_base, tbl_limit, section_base; + u64 section_l1t0, section_l1t1, section_l2; + u64 *level0_table = (u64 *)gd->arch.tlb_addr; + u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + 0x1000); + u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + 0x2000); + u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + 0x3000); + u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + 0x4000); + + + level0_table[0] = + (u64)level1_table_0 | PMD_TYPE_TABLE; + level0_table[1] = + (u64)level1_table_1 | PMD_TYPE_TABLE; + + /* + * set level 1 table 0 to cache_inhibit, covering 0 to 512GB + * set level 1 table 1 to cache enabled, covering 512GB to 1TB + * set level 2 table 0 to cache-inhibit, covering 0 to 1GB + */ + section_l1t0 = 0; + section_l1t1 = BLOCK_SIZE_L0; + section_l2 = 0; + for (i = 0; i < 512; i++) { + set_pgtable_section(level1_table_0, i, section_l1t0, + MT_DEVICE_NGNRNE); + set_pgtable_section(level1_table_1, i, section_l1t1, + MT_NORMAL); + set_pgtable_section(level2_table_0, i, section_l2, + MT_DEVICE_NGNRNE); + section_l1t0 += BLOCK_SIZE_L1; + section_l1t1 += BLOCK_SIZE_L1; + section_l2 += BLOCK_SIZE_L2; + } + + level1_table_0[0] = + (u64)level2_table_0 | PMD_TYPE_TABLE; + level1_table_0[2] = + 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | + PMD_ATTRINDX(MT_NORMAL); + level1_table_0[3] = + 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | + PMD_ATTRINDX(MT_NORMAL); + + /* Rewrite table to enable cache */ + set_pgtable_section(level2_table_0, + CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, + CONFIG_SYS_FSL_OCRAM_BASE, + MT_NORMAL); + + /* + * Fill in other part of tables if cache is needed + * If finer granularity than 1GB is needed, sub table + * should be created. + */ + section_base = FINAL_QBMAN_CACHED_MEM & ~(BLOCK_SIZE_L1 - 1); + i = section_base >> SECTION_SHIFT_L1; + level1_table_0[i] = (u64)level2_table_1 | PMD_TYPE_TABLE; + section_l2 = section_base; + for (i = 0; i < 512; i++) { + set_pgtable_section(level2_table_1, i, section_l2, + MT_DEVICE_NGNRNE); + section_l2 += BLOCK_SIZE_L2; + } + tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1); + tbl_limit = (FINAL_QBMAN_CACHED_MEM + FINAL_QBMAN_CACHED_SIZE) & + (BLOCK_SIZE_L1 - 1); + for (i = tbl_base >> SECTION_SHIFT_L2; + i < tbl_limit >> SECTION_SHIFT_L2; i++) { + section_l2 = section_base + (i << SECTION_SHIFT_L2); + set_pgtable_section(level2_table_1, i, + section_l2, MT_NORMAL); + } + + /* flush new MMU table */ + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + /* point TTBR to the new table */ + el = current_el(); + asm volatile("dsb sy"); + if (el == 1) { + asm volatile("msr ttbr0_el1, %0" + : : "r" ((u64)level0_table) : "memory"); + } else if (el == 2) { + asm volatile("msr ttbr0_el2, %0" + : : "r" ((u64)level0_table) : "memory"); + } else if (el == 3) { + asm volatile("msr ttbr0_el3, %0" + : : "r" ((u64)level0_table) : "memory"); + } else { + hang(); + } + asm volatile("isb"); + + /* + * MMU is already enabled, just need to invalidate TLB to load the + * new table. The new table is compatible with the current table, if + * MMU somehow walks through the new table before invalidation TLB, + * it still works. So we don't need to turn off MMU here. + */ +} + +int arch_cpu_init(void) +{ + icache_enable(); + __asm_invalidate_dcache_all(); + __asm_invalidate_tlb_all(); + early_mmu_setup(); + set_sctlr(get_sctlr() | CR_C); + return 0; +} + +/* + * flush_l3_cache + * Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power + * state, by writing to HP-F P-state request register. + * Fixme: This function should moved to a common file if other SoCs also use + * the same Dickens. + */ +#define HNF0_PSTATE_REQ 0x04200010 +#define HNF1_PSTATE_REQ 0x04210010 +#define HNF2_PSTATE_REQ 0x04220010 +#define HNF3_PSTATE_REQ 0x04230010 +#define HNF4_PSTATE_REQ 0x04240010 +#define HNF5_PSTATE_REQ 0x04250010 +#define HNF6_PSTATE_REQ 0x04260010 +#define HNF7_PSTATE_REQ 0x04270010 +#define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC) +#define HNFPSTAT_FAM 0x3 +#define HNFPSTAT_SFONLY 0x01 + +static void hnf_pstate_req(u64 *ptr, u64 state) +{ + int timeout = 1000; + out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3)); + ptr++; + /* checking if the transition is completed */ + while (timeout > 0) { + if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3)) + break; + udelay(100); + timeout--; + } +} + +void flush_l3_cache(void) +{ + hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY); + hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM); + hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM); +} + +/* + * This function is called from lib/board.c. + * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. + * There is no need to disable d-cache for this operation. + */ +void enable_caches(void) +{ + final_mmu_setup(); + __asm_invalidate_tlb_all(); +} +#endif + +static inline u32 initiator_type(u32 cluster, int init_id) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; + u32 type = in_le32(&gur->tp_ityp[idx]); + + if (type & TP_ITYP_AV) + return type; + + return 0; +} + +u32 cpu_mask(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + int i = 0, count = 0; + u32 cluster, type, mask = 0; + + do { + int j; + cluster = in_le32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + type = initiator_type(cluster, j); + if (type) { + if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) + mask |= 1 << count; + count++; + } + } + i++; + } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + + return mask; +} + +/* + * Return the number of cores on this SOC. + */ +int cpu_numcores(void) +{ + return hweight32(cpu_mask()); +} + +int fsl_qoriq_core_to_cluster(unsigned int core) +{ + struct ccsr_gur __iomem *gur = + (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); + int i = 0, count = 0; + u32 cluster; + + do { + int j; + cluster = in_le32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + if (initiator_type(cluster, j)) { + if (count == core) + return i; + count++; + } + } + i++; + } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + + return -1; /* cannot identify the cluster */ +} + +u32 fsl_qoriq_core_to_type(unsigned int core) +{ + struct ccsr_gur __iomem *gur = + (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); + int i = 0, count = 0; + u32 cluster, type; + + do { + int j; + cluster = in_le32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + type = initiator_type(cluster, j); + if (type) { + if (count == core) + return type; + count++; + } + } + i++; + } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + + return -1; /* cannot identify the cluster */ +} + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + struct sys_info sysinfo; + char buf[32]; + unsigned int i, core; + u32 type; + + get_sys_info(&sysinfo); + puts("Clock Configuration:"); + for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { + if (!(i % 3)) + puts("\n "); + type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); + printf("CPU%d(%s):%-4s MHz ", core, + type == TY_ITYP_VER_A7 ? "A7 " : + (type == TY_ITYP_VER_A53 ? "A53" : + (type == TY_ITYP_VER_A57 ? "A57" : " ")), + strmhz(buf, sysinfo.freq_processor[core])); + } + printf("\n Bus: %-4s MHz ", + strmhz(buf, sysinfo.freq_systembus)); + printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus)); + puts("\n"); + + return 0; +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h new file mode 100644 index 00000000000..28544d7c14d --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h @@ -0,0 +1,7 @@ +/* + * Copyright 2014, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +int fsl_qoriq_core_to_cluster(unsigned int core); diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S new file mode 100644 index 00000000000..ad32b6cd520 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Extracted from armv8/start.S + */ + +#include +#include +#include + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + + /* Set the SMMU page size in the sACR register */ + ldr x1, =SMMU_BASE + ldr w0, [x1, #0x10] + orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */ + str w0, [x1, #0x10] + + /* Initialize GIC Secure Bank Status */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + branch_if_slave x0, 1f + ldr x0, =GICD_BASE + bl gic_init_secure +1: +#ifdef CONFIG_GICV3 + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + + branch_if_master x0, x1, 1f + + /* + * Slave should wait for master clearing spin table. + * This sync prevent salves observing incorrect + * value of spin table and jumping to wrong place. + */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif + + /* + * All processors will enter EL2 and optionally EL1. + */ + bl armv8_switch_to_el2 +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + bl armv8_switch_to_el1 +#endif + b 2f + +1: +2: + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c new file mode 100644 index 00000000000..dc4a34bce5c --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c @@ -0,0 +1,176 @@ +/* + * Copyright 2014, Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived from arch/power/cpu/mpc85xx/speed.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS +#define CONFIG_SYS_FSL_NUM_CC_PLLS 6 +#endif + + +void get_sys_info(struct sys_info *sys_info) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#ifdef CONFIG_FSL_IFC + struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; + u32 ccr; +#endif + struct ccsr_clk_cluster_group __iomem *clk_grp[2] = { + (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR), + (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR) + }; + struct ccsr_clk_ctrl __iomem *clk_ctrl = + (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR); + unsigned int cpu; + const u8 core_cplx_pll[16] = { + [0] = 0, /* CC1 PPL / 1 */ + [1] = 0, /* CC1 PPL / 2 */ + [2] = 0, /* CC1 PPL / 4 */ + [4] = 1, /* CC2 PPL / 1 */ + [5] = 1, /* CC2 PPL / 2 */ + [6] = 1, /* CC2 PPL / 4 */ + [8] = 2, /* CC3 PPL / 1 */ + [9] = 2, /* CC3 PPL / 2 */ + [10] = 2, /* CC3 PPL / 4 */ + [12] = 3, /* CC4 PPL / 1 */ + [13] = 3, /* CC4 PPL / 2 */ + [14] = 3, /* CC4 PPL / 4 */ + }; + + const u8 core_cplx_pll_div[16] = { + [0] = 1, /* CC1 PPL / 1 */ + [1] = 2, /* CC1 PPL / 2 */ + [2] = 4, /* CC1 PPL / 4 */ + [4] = 1, /* CC2 PPL / 1 */ + [5] = 2, /* CC2 PPL / 2 */ + [6] = 4, /* CC2 PPL / 4 */ + [8] = 1, /* CC3 PPL / 1 */ + [9] = 2, /* CC3 PPL / 2 */ + [10] = 4, /* CC3 PPL / 4 */ + [12] = 1, /* CC4 PPL / 1 */ + [13] = 2, /* CC4 PPL / 2 */ + [14] = 4, /* CC4 PPL / 4 */ + }; + + uint i, cluster; + uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; + uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; + unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; + u32 c_pll_sel, cplx_pll; + void *offset; + + sys_info->freq_systembus = sysclk; +#ifdef CONFIG_DDR_CLK_FREQ + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#else + sys_info->freq_ddrbus = sysclk; +#endif + + sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; + sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; + + for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { + /* + * fixme: prefer to combine the following into one line, but + * cannot pass compiling without warning about in_le32. + */ + offset = (void *)((size_t)clk_grp[i/3] + + offsetof(struct ccsr_clk_cluster_group, + pllngsr[i%3].gsr)); + ratio[i] = (in_le32(offset) >> 1) & 0x3f; + if (ratio[i] > 4) + freq_c_pll[i] = sysclk * ratio[i]; + else + freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; + } + + for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { + cluster = fsl_qoriq_core_to_cluster(cpu); + c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27) + & 0xf; + cplx_pll = core_cplx_pll[c_pll_sel]; + cplx_pll += cc_group[cluster] - 1; + sys_info->freq_processor[cpu] = + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + } + +#if defined(CONFIG_FSL_IFC) + ccr = in_le32(&ifc_regs->ifc_ccr); + ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; + + sys_info->freq_localbus = sys_info->freq_systembus / ccr; +#endif +} + + +int get_clocks(void) +{ + struct sys_info sys_info; + get_sys_info(&sys_info); + gd->cpu_clk = sys_info.freq_processor[0]; + gd->bus_clk = sys_info.freq_systembus; + gd->mem_clk = sys_info.freq_ddrbus; + +#if defined(CONFIG_FSL_ESDHC) + gd->arch.sdhc_clk = gd->bus_clk / 2; +#endif /* defined(CONFIG_FSL_ESDHC) */ + + if (gd->cpu_clk != 0) + return 0; + else + return 1; +} + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq(ulong dummy) +{ + if (!gd->bus_clk) + get_clocks(); + + return gd->bus_clk; +} + +/******************************************** + * get_ddr_freq + * return ddr bus freq in Hz + *********************************************/ +ulong get_ddr_freq(ulong dummy) +{ + if (!gd->mem_clk) + get_clocks(); + + return gd->mem_clk; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_I2C_CLK: + return get_bus_freq(0) / 2; + default: + printf("Unsupported clock\n"); + } + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.h b/arch/arm/cpu/armv8/fsl-lsch3/speed.h new file mode 100644 index 00000000000..15af5b9f918 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.h @@ -0,0 +1,7 @@ +/* + * Copyright 2014, Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void get_sys_info(struct sys_info *sys_info); diff --git a/arch/arm/include/asm/arch-fsl-lsch3/clock.h b/arch/arm/include/asm/arch-fsl-lsch3/clock.h new file mode 100644 index 00000000000..831af0bda3a --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/clock.h @@ -0,0 +1,23 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_ +#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_ + +#include + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_BUS_CLK, + MXC_UART_CLK, + MXC_ESDHC_CLK, + MXC_I2C_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); + +#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h new file mode 100644 index 00000000000..c987a19db7d --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -0,0 +1,65 @@ +/* + * Copyright 2014, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_ +#define _ASM_ARMV8_FSL_LSCH3_CONFIG_ + +#include + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +/* Link Definitions */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) + +#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) +#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) +#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) +#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) +#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) +#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) +#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) +#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 +#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ + 0x18A0) + +#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) +#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) +#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) +#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06100000 + +/* SMMU Defintions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* DDR */ +#define CONFIG_SYS_FSL_DDR_LE +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ +#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ +#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 + + +/* IFC */ +#define CONFIG_SYS_FSL_IFC_LE + +#ifdef CONFIG_LS2100A +#define CONFIG_MAX_CPUS 16 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } +#else +#error SoC not defined +#endif + +#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h new file mode 100644 index 00000000000..f23a78c62d3 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h @@ -0,0 +1,9 @@ +/* + * Copyright 2014, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_ +#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_ +#endif /* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h new file mode 100644 index 00000000000..18e66bdf411 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -0,0 +1,116 @@ +/* + * LayerScape Internal Memory Map + * + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_FSL_LSCH3_IMMAP_H +#define __ARCH_FSL_LSCH3_IMMAP_H_ + +/* This is chassis generation 3 */ + +struct sys_info { + unsigned long freq_processor[CONFIG_MAX_CPUS]; + unsigned long freq_systembus; + unsigned long freq_ddrbus; + unsigned long freq_localbus; + unsigned long freq_qe; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; +#endif +#ifdef CONFIG_SYS_DPAA_QBMAN + unsigned long freq_qman; +#endif +#ifdef CONFIG_SYS_DPAA_PME + unsigned long freq_pme; +#endif +}; + +/* Global Utilities Block */ +struct ccsr_gur { + u32 porsr1; /* POR status 1 */ + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; /* General-purpose POR configuration 2 */ + u32 dcfg_fusesr; /* Fuse status register */ + u32 gpporcr3; + u32 gpporcr4; + u8 res_034[0x70-0x34]; + u32 devdisr; /* Device disable control */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u32 devdisr6; /* Device disable control 6 */ + u32 devdisr7; /* Device disable control 7 */ + u8 res_08c[0x90-0x8c]; + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ + u8 res_098[0xa0-0x98]; + u32 pvr; /* Processor version */ + u32 svr; /* System version */ + u32 mvr; /* Manufacturing version */ + u8 res_0ac[0x100-0xac]; + u32 rcwsr[32]; /* Reset control word status */ + +#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 +#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 +#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f + u8 res_180[0x200-0x180]; + u32 scratchrw[32]; /* Scratch Read/Write */ + u8 res_280[0x300-0x280]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 bootlocptrl; /* Boot location pointer low-order addr */ + u32 bootlocptrh; /* Boot location pointer high-order addr */ + u8 res_408[0x500-0x408]; + u8 res_500[0x740-0x500]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[3]; /* Core Cluster n Topology Register */ + u8 res_858[0x1000-0x858]; +}; + +#define TP_ITYP_AV 0x00000001 /* Initiator available */ +#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ +#define TP_ITYP_TYPE_ARM 0x0 +#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ +#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ +#define TY_ITYP_VER_A7 0x1 +#define TY_ITYP_VER_A53 0x2 +#define TY_ITYP_VER_A57 0x3 + +#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4 + +struct ccsr_clk_cluster_group { + struct { + u8 res_00[0x10]; + u32 csr; + u8 res_14[0x20-0x14]; + } hwncsr[3]; + u8 res_60[0x80-0x60]; + struct { + u32 gsr; + u8 res_84[0xa0-0x84]; + } pllngsr[3]; + u8 res_e0[0x100-0xe0]; +}; + +struct ccsr_clk_ctrl { + struct { + u32 csr; /* core cluster n clock control status */ + u8 res_04[0x20-0x04]; + } clkcncsr[8]; +}; +#endif /* __ARCH_FSL_LSCH3_IMMAP_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h new file mode 100644 index 00000000000..8f005353b4f --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ +#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ + +#define I2C_QUIRK_REG /* enable 8-bit driver */ + +#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */ diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 2a20a770bcd..d3433dafd9f 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -17,4 +17,8 @@ #define CONFIG_STATIC_RELA #endif +#ifdef CONFIG_FSL_LSCH3 +#include +#endif + #endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 74ee9a4df9b..d51ba668f32 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -78,6 +78,8 @@ void gic_send_sgi(unsigned long sgino); void wait_for_wakeup(void); void smp_kick_all_cpus(void); +void flush_l3_cache(void); + #endif /* __ASSEMBLY__ */ #else /* CONFIG_ARM64 */ diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 48468d74bdd..c14797ce0ed 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -429,6 +429,11 @@ static void * const i2c_bases[] = { (void *)I2C3_BASE_ADDR #elif defined(CONFIG_VF610) (void *)I2C0_BASE_ADDR +#elif defined(CONFIG_FSL_LSCH3) + (void *)I2C1_BASE_ADDR, + (void *)I2C2_BASE_ADDR, + (void *)I2C3_BASE_ADDR, + (void *)I2C4_BASE_ADDR #else #error "architecture not supported" #endif diff --git a/include/common.h b/include/common.h index cc74633df5e..2e5a6d3d2f1 100644 --- a/include/common.h +++ b/include/common.h @@ -687,9 +687,6 @@ ulong get_PERCLK3(void); ulong get_bus_freq (ulong); int get_serial_clock(void); -#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) -ulong get_ddr_freq(ulong); -#endif #if defined(CONFIG_MPC85xx) typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); @@ -705,6 +702,8 @@ static inline ulong get_ddr_freq(ulong dummy) { return get_bus_freq(dummy); } +#else +ulong get_ddr_freq(ulong); #endif #if defined(CONFIG_4xx) -- cgit v1.3.1 From b940ca64b22ba8980fd4ec8dda028f6b1a2ed79d Mon Sep 17 00:00:00 2001 From: "J. German Rivera" Date: Mon, 23 Jun 2014 15:15:55 -0700 Subject: armv8/fsl-lsch3: Add support to load and start MC Firmware Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera Signed-off-by: York Sun Signed-off-by: Lijun Pan Signed-off-by: Shruti Kanetkar --- README | 27 ++++ arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 11 ++ drivers/net/Makefile | 1 + drivers/net/fsl_mc/Makefile | 8 ++ drivers/net/fsl_mc/mc.c | 266 +++++++++++++++++++++++++++++++++++++ include/fdt_support.h | 14 +- include/fsl_mc.h | 59 ++++++++ 7 files changed, 383 insertions(+), 3 deletions(-) create mode 100644 drivers/net/fsl_mc/Makefile create mode 100644 drivers/net/fsl_mc/mc.c create mode 100644 include/fsl_mc.h (limited to 'drivers') diff --git a/README b/README index fe5cacbaa55..55c3fcdca48 100644 --- a/README +++ b/README @@ -4676,6 +4676,33 @@ within that device. window->master inbound window->master LAW->the ucode address in master's memory space. +Freescale Layerscape Management Complex Firmware Support: +--------------------------------------------------------- +The Freescale Layerscape Management Complex (MC) supports the loading of +"firmware". +This firmware often needs to be loaded during U-Boot booting, so macros +are used to identify the storage device (NOR flash, SPI, etc) and the address +within that device. + +- CONFIG_FSL_MC_ENET + Enable the MC driver for Layerscape SoCs. + +- CONFIG_SYS_LS_MC_FW_ADDR + The address in the storage device where the firmware is located. The + meaning of this address depends on which CONFIG_SYS_LS_MC_FW_IN_xxx macro + is also specified. + +- CONFIG_SYS_LS_MC_FW_LENGTH + The maximum possible size of the firmware. The firmware binary format + has a field that specifies the actual size of the firmware, but it + might not be possible to read any part of the firmware unless some + local storage is allocated to hold the entire firmware first. + +- CONFIG_SYS_LS_MC_FW_IN_NOR + Specifies that MC firmware is located in NOR flash, mapped as + normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the + virtual address in NOR flash. + Building the Software: ====================== diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 46965f08ad3..c129d032f40 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -12,6 +12,7 @@ #include #include "cpu.h" #include "speed.h" +#include DECLARE_GLOBAL_DATA_PTR; @@ -423,3 +424,13 @@ int print_cpuinfo(void) return 0; } #endif + +int cpu_eth_init(bd_t *bis) +{ + int error = 0; + +#ifdef CONFIG_FSL_MC_ENET + error = mc_init(bis); +#endif + return error; +} diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 6005f7e4137..6226cb259f8 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -64,3 +64,4 @@ obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \ xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o +obj-$(CONFIG_FSL_MC_ENET) += fsl_mc/ diff --git a/drivers/net/fsl_mc/Makefile b/drivers/net/fsl_mc/Makefile new file mode 100644 index 00000000000..483408623c4 --- /dev/null +++ b/drivers/net/fsl_mc/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# Layerscape MC driver +obj-y += mc.o diff --git a/drivers/net/fsl_mc/mc.c b/drivers/net/fsl_mc/mc.c new file mode 100644 index 00000000000..df84568a945 --- /dev/null +++ b/drivers/net/fsl_mc/mc.c @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +static int mc_boot_status; + +/** + * Copying MC firmware or DPL image to DDR + */ +static int mc_copy_image(const char *title, + u64 image_addr, u32 image_size, u64 mc_ram_addr) +{ + debug("%s copied to address %p\n", title, (void *)mc_ram_addr); + memcpy((void *)mc_ram_addr, (void *)image_addr, image_size); + return 0; +} + +/** + * MC firmware FIT image parser checks if the image is in FIT + * format, verifies integrity of the image and calculates + * raw image address and size values. + * Returns 0 if success and 1 if any of the above mentioned + * task fail. + **/ + +int parse_mc_firmware_fit_image(const void **raw_image_addr, + size_t *raw_image_size) +{ + int format; + void *fit_hdr; + int node_offset; + const void *data; + size_t size; + const char *uname = "firmware"; + + /* Check if the image is in NOR flash*/ +#ifdef CONFIG_SYS_LS_MC_FW_IN_NOR + fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR; +#else +#error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined" +#endif + + /* Check if Image is in FIT format */ + format = genimg_get_format(fit_hdr); + + if (format != IMAGE_FORMAT_FIT) { + debug("Not a FIT image\n"); + return 1; + } + + if (!fit_check_format(fit_hdr)) { + debug("Bad FIT image format\n"); + return 1; + } + + node_offset = fit_image_get_node(fit_hdr, uname); + + if (node_offset < 0) { + debug("Can not find %s subimage\n", uname); + return 1; + } + + /* Verify MC firmware image */ + if (!(fit_image_verify(fit_hdr, node_offset))) { + debug("Bad MC firmware hash"); + return 1; + } + + /* Get address and size of raw image */ + fit_image_get_data(fit_hdr, node_offset, &data, &size); + + *raw_image_addr = data; + *raw_image_size = size; + + return 0; +} + +int mc_init(bd_t *bis) +{ + int error = 0; + int timeout = 200000; + struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; + u64 mc_ram_addr; + u64 mc_dpl_offset; + u32 reg_gsr; + u32 mc_fw_boot_status; + void *fdt_hdr; + int dpl_size; + const void *raw_image_addr; + size_t raw_image_size = 0; + + BUILD_BUG_ON(CONFIG_SYS_LS_MC_FW_LENGTH % 4 != 0); + + /* + * The MC private DRAM block was already carved at the end of DRAM + * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: + */ + if (gd->bd->bi_dram[1].start) { + mc_ram_addr = + gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; + } else { + mc_ram_addr = + gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; + } + + /* + * Management Complex cores should be held at reset out of POR. + * U-boot should be the first software to touch MC. To be safe, + * we reset all cores again by setting GCR1 to 0. It doesn't do + * anything if they are held at reset. After we setup the firmware + * we kick off MC by deasserting the reset bit for core 0, and + * deasserting the reset bits for Command Portal Managers. + * The stop bits are not touched here. They are used to stop the + * cores when they are active. Setting stop bits doesn't stop the + * cores from fetching instructions when they are released from + * reset. + */ + out_le32(&mc_ccsr_regs->reg_gcr1, 0); + dmb(); + + error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size); + if (error != 0) + goto out; + /* + * Load the MC FW at the beginning of the MC private DRAM block: + */ + mc_copy_image( + "MC Firmware", + (u64)raw_image_addr, + raw_image_size, + mc_ram_addr); + + /* + * Calculate offset in the MC private DRAM block at which the MC DPL + * blob is to be placed: + */ +#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET + BUILD_BUG_ON( + (CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || + CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); + + mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET; +#else + mc_dpl_offset = mc_get_dram_block_size() - + roundup(CONFIG_SYS_LS_MC_DPL_LENGTH, 4096); + + if ((mc_dpl_offset & 0x3) != 0 || mc_dpl_offset > 0xffffffff) { + printf("%s: Invalid MC DPL offset: %llu\n", + __func__, mc_dpl_offset); + error = -EINVAL; + goto out; + } +#endif + + /* Check if DPL image is in NOR flash */ +#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR + fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR; +#else +#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined" +#endif + + dpl_size = fdt_totalsize(fdt_hdr); + + /* + * Load the MC DPL blob at the far end of the MC private DRAM block: + */ + mc_copy_image( + "MC DPL blob", + (u64)fdt_hdr, + dpl_size, + mc_ram_addr + mc_dpl_offset); + + debug("mc_ccsr_regs %p\n", mc_ccsr_regs); + + /* + * Tell MC where the MC Firmware image was loaded in DDR: + */ + out_le32(&mc_ccsr_regs->reg_mcfbalr, (u32)mc_ram_addr); + out_le32(&mc_ccsr_regs->reg_mcfbahr, (u32)((u64)mc_ram_addr >> 32)); + out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK); + + /* + * Tell MC where the DPL blob was loaded in DDR, by indicating + * its offset relative to the beginning of the DDR block + * allocated to the MC firmware. The MC firmware is responsible + * for checking that there is no overlap between the DPL blob + * and the runtime heap and stack of the MC firmware itself. + * + * NOTE: bits [31:2] of this offset need to be stored in bits [29:0] of + * the GSR MC CCSR register. So, this offset is assumed to be 4-byte + * aligned. + * Care must be taken not to write 1s into bits 31 and 30 of the GSR in + * this case as the SoC COP or PIC will be signaled. + */ + out_le32(&mc_ccsr_regs->reg_gsr, (u32)(mc_dpl_offset >> 2)); + + /* + * Deassert reset and release MC core 0 to run + */ + out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST); + dmb(); + debug("Polling mc_ccsr_regs->reg_gsr ...\n"); + + for (;;) { + reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr); + mc_fw_boot_status = (reg_gsr & GSR_FS_MASK); + if (mc_fw_boot_status & 0x1) + break; + + udelay(1000); /* throttle polling */ + if (timeout-- <= 0) + break; + } + + if (timeout <= 0) { + printf("%s: timeout booting management complex firmware\n", + __func__); + + /* TODO: Get an error status from an MC CCSR register */ + error = -ETIMEDOUT; + goto out; + } + + printf("Management complex booted (boot status: %#x)\n", + mc_fw_boot_status); + + if (mc_fw_boot_status != 0x1) { + /* + * TODO: Identify critical errors from the GSR register's FS + * field and for those errors, set error to -ENODEV or other + * appropriate errno, so that the status property is set to + * failure in the fsl,dprc device tree node. + */ + } + +out: + if (error != 0) + mc_boot_status = -error; + else + mc_boot_status = 0; + + return error; +} + +int get_mc_boot_status(void) +{ + return mc_boot_status; +} + +/** + * Return the actual size of the MC private DRAM block. + * + * NOTE: For now this function always returns the minimum required size, + * However, in the future, the actual size may be obtained from an environment + * variable. + */ +unsigned long mc_get_dram_block_size(void) +{ + return CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; +} diff --git a/include/fdt_support.h b/include/fdt_support.h index 21d7b444532..fd44d7e2f64 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -113,17 +113,25 @@ static inline int fdt_status_disabled(void *fdt, int nodeoffset) { return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_DISABLED, 0); } +static inline int fdt_status_fail(void *fdt, int nodeoffset) +{ + return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_FAIL, 0); +} -int fdt_set_status_by_alias(void *fdt, const char* alias, +int fdt_set_status_by_alias(void *fdt, const char *alias, enum fdt_status status, unsigned int error_code); -static inline int fdt_status_okay_by_alias(void *fdt, const char* alias) +static inline int fdt_status_okay_by_alias(void *fdt, const char *alias) { return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_OKAY, 0); } -static inline int fdt_status_disabled_by_alias(void *fdt, const char* alias) +static inline int fdt_status_disabled_by_alias(void *fdt, const char *alias) { return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_DISABLED, 0); } +static inline int fdt_status_fail_by_alias(void *fdt, const char *alias) +{ + return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_FAIL, 0); +} #endif /* ifdef CONFIG_OF_LIBFDT */ diff --git a/include/fsl_mc.h b/include/fsl_mc.h new file mode 100644 index 00000000000..b9f089e5f32 --- /dev/null +++ b/include/fsl_mc.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_MC_H__ +#define __FSL_MC_H__ + +#include + +#define MC_CCSR_BASE_ADDR \ + ((struct mc_ccsr_registers __iomem *)0x8340000) + +#define BIT(x) (1 << (x)) +#define GCR1_P1_STOP BIT(31) +#define GCR1_P2_STOP BIT(30) +#define GCR1_P1_DE_RST BIT(23) +#define GCR1_P2_DE_RST BIT(22) +#define GCR1_M1_DE_RST BIT(15) +#define GCR1_M2_DE_RST BIT(14) +#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST) +#define GSR_FS_MASK 0x3fffffff +#define MCFAPR_PL_MASK (0x1 << 18) +#define MCFAPR_BMT_MASK (0x1 << 17) +#define MCFAPR_BYPASS_ICID_MASK \ + (MCFAPR_PL_MASK | MCFAPR_BMT_MASK) + +#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000) +#define SOC_MC_PORTAL_STRIDE 0x10000 + +#define SOC_MC_PORTAL_ADDR(_portal_id) \ + ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \ + (_portal_id) * SOC_MC_PORTAL_STRIDE)) + +struct mc_ccsr_registers { + u32 reg_gcr1; + u32 reserved1; + u32 reg_gsr; + u32 reserved2; + u32 reg_sicbalr; + u32 reg_sicbahr; + u32 reg_sicapr; + u32 reserved3; + u32 reg_mcfbalr; + u32 reg_mcfbahr; + u32 reg_mcfapr; + u32 reserved4[0x2f1]; + u32 reg_psr; + u32 reserved5; + u32 reg_brr[2]; + u32 reserved6[0x80]; + u32 reg_error[]; +}; + +int mc_init(bd_t *bis); + +int get_mc_boot_status(void); +#endif -- cgit v1.3.1 From c0c374024dbd38b1045784cb2880ba21db552c54 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Sun, 25 May 2014 10:31:18 +0800 Subject: gpio: spear_gpio: Fix gpio_set_value() implementation In current gpio_set_value() implementation, it always sets the gpio control bit no matter the value argument is 0 or 1. Thus the GPIOs never set to low. This patch fixes this bug. The address bus is used as a mask on read/write operations, so that independent software drivers can set their GPIO bits without affecting any other pins in a single write operation. Thus we don't need a read-modify-write to update the register. Signed-off-by: Axel Lin Acked-by: Stefan Roese Reviewed-by: Vipin Kumar Reviewed-by: Michael Trimarchi --- drivers/gpio/spear_gpio.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c index 367b6701663..6fb4117dbea 100644 --- a/drivers/gpio/spear_gpio.c +++ b/drivers/gpio/spear_gpio.c @@ -36,7 +36,10 @@ int gpio_set_value(unsigned gpio, int value) { struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE; - writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]); + if (value) + writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]); + else + writel(0, ®s->gpiodata[DATA_REG_ADDR(gpio)]); return 0; } -- cgit v1.3.1 From 7237d22baac9ebeffc946dfd30b9f61aaf0bfdbc Mon Sep 17 00:00:00 2001 From: Sergey Kostanbaev Date: Wed, 25 Jun 2014 23:44:29 +0400 Subject: arm: ep9315: Return back Cirrus Logic EDB9315A board support This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev Cc: albert.u.boot@aribaud.net --- arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S | 463 ++++++++++++++++++++++++++-- arch/arm/include/asm/arch-ep93xx/ep93xx.h | 85 +++++ board/cirrus/edb93xx/Makefile | 11 + board/cirrus/edb93xx/edb93xx.c | 382 +++++++++++++++++++++++ board/cirrus/edb93xx/u-boot.lds | 115 +++++++ boards.cfg | 1 + drivers/spi/Makefile | 1 + drivers/spi/ep93xx_spi.c | 274 ++++++++++++++++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ohci-ep93xx.c | 38 +++ include/configs/edb93xx.h | 292 ++++++++++++++++++ 11 files changed, 1636 insertions(+), 27 deletions(-) create mode 100644 board/cirrus/edb93xx/Makefile create mode 100644 board/cirrus/edb93xx/edb93xx.c create mode 100644 board/cirrus/edb93xx/u-boot.lds create mode 100644 drivers/spi/ep93xx_spi.c create mode 100644 drivers/usb/host/ohci-ep93xx.c create mode 100644 include/configs/edb93xx.h (limited to 'drivers') diff --git a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S index bf2fa2ac320..cfad206eddb 100644 --- a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S +++ b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S @@ -2,48 +2,457 @@ * Low-level initialization for EP93xx * * Copyright (C) 2009 Matthias Kaehlcke + * Copyright (C) 2013 + * Sergey Kostanabev fairwaves.ru> * * Copyright (C) 2006 Dominic Rath + * Copyright (C) 2006 Cirrus Logic Inc. + * + * See file CREDITS for list of people who contributed to this + * project. * * SPDX-License-Identifier: GPL-2.0+ */ -#include -#include +#include +#include + +/* +/* Configure the SDRAM based on the supplied settings. + * + * Input: r0 - SDRAM DEVCFG register + * r2 - configuration for SDRAM chips + * Output: none + * Modifies: r3, r4 + */ +ep93xx_sdram_config: + /* Program the SDRAM device configuration register. */ + ldr r3, =SDRAM_BASE +#ifdef CONFIG_EDB93XX_SDCS0 + str r0, [r3, #SDRAM_OFF_DEVCFG0] +#endif +#ifdef CONFIG_EDB93XX_SDCS1 + str r0, [r3, #SDRAM_OFF_DEVCFG1] +#endif +#ifdef CONFIG_EDB93XX_SDCS2 + str r0, [r3, #SDRAM_OFF_DEVCFG2] +#endif +#ifdef CONFIG_EDB93XX_SDCS3 + str r0, [r3, #SDRAM_OFF_DEVCFG3] +#endif + + /* Set the Initialize and MRS bits (issue continuous NOP commands + * (INIT & MRS set)) + */ + ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \ + EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \ + EP93XX_SDRAMCTRL_GLOBALCFG_CKE) + str r4, [r3, #SDRAM_OFF_GLCONFIG] + + /* Delay for 200us. */ + mov r4, #0x3000 +delay1: + subs r4, r4, #1 + bne delay1 + + /* Clear the MRS bit to issue a precharge all. */ + ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \ + EP93XX_SDRAMCTRL_GLOBALCFG_CKE) + str r4, [r3, #SDRAM_OFF_GLCONFIG] + + /* Temporarily set the refresh timer to 0x10. Make it really low so + * that refresh cycles are generated. + */ + ldr r4, =0x10 + str r4, [r3, #SDRAM_OFF_REFRSHTIMR] + + /* Delay for at least 80 SDRAM clock cycles. */ + mov r4, #80 +delay2: + subs r4, r4, #1 + bne delay2 + + /* Set the refresh timer to the fastest required for any device + * that might be used. Set 9.6 ms refresh time. + */ + ldr r4, =0x01e0 + str r4, [r3, #SDRAM_OFF_REFRSHTIMR] + + /* Select mode register update mode. */ + ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \ + EP93XX_SDRAMCTRL_GLOBALCFG_MRS) + str r4, [r3, #SDRAM_OFF_GLCONFIG] + + /* Program the mode register on the SDRAM by performing fake read */ + ldr r4, [r2] + + /* Select normal operating mode. */ + ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE + str r4, [r3, #SDRAM_OFF_GLCONFIG] + + /* Return to the caller. */ + mov pc, lr + +/* + * Test to see if the SDRAM has been configured in a usable mode. + * + * Input: r0 - Test address of SDRAM + * Output: r0 - 0 -- Test OK, -1 -- Failed + * Modifies: r0-r5 + */ +ep93xx_sdram_test: + /* Load the test patterns to be written to SDRAM. */ + ldr r1, =0xf00dface + ldr r2, =0xdeadbeef + ldr r3, =0x08675309 + ldr r4, =0xdeafc0ed + + /* Store the test patterns to SDRAM. */ + stmia r0, {r1-r4} + + /* Load the test patterns from SDRAM one at a time and compare them + * to the actual pattern. + */ + ldr r5, [r0] + cmp r5, r1 + ldreq r5, [r0, #0x0004] + cmpeq r5, r2 + ldreq r5, [r0, #0x0008] + cmpeq r5, r3 + ldreq r5, [r0, #0x000c] + cmpeq r5, r4 + + /* Return -1 if a mismatch was encountered, 0 otherwise. */ + mvnne r0, #0xffffffff + moveq r0, #0x00000000 + + /* Return to the caller. */ + mov pc, lr + +/* + * Determine the size of the SDRAM. Use data=address for the scan. + * + * Input: r0 - Start SDRAM address + * Return: r0 - Single block size + * r1 - Valid block mask + * r2 - Total block count + * Modifies: r0-r5 + */ +ep93xx_sdram_size: + /* Store zero at offset zero. */ + str r0, [r0] + + /* Start checking for an alias at 1MB into SDRAM. */ + ldr r1, =0x00100000 + + /* Store the offset at the current offset. */ +check_block_size: + str r1, [r0, r1] + + /* Read back from zero. */ + ldr r2, [r0] + + /* Stop searching of an alias was found. */ + cmp r1, r2 + beq found_block_size + + /* Advance to the next power of two boundary. */ + mov r1, r1, lsl #1 + + /* Loop back if the size has not reached 256MB. */ + cmp r1, #0x10000000 + bne check_block_size + + /* A full 256MB of memory was found, so return it now. */ + ldr r0, =0x10000000 + ldr r1, =0x00000000 + ldr r2, =0x00000001 + mov pc, lr + + /* An alias was found. See if the first block is 128MB in size. */ +found_block_size: + cmp r1, #0x08000000 + + /* The first block is 128MB, so there is no further memory. Return it + * now. + */ + ldreq r0, =0x08000000 + ldreq r1, =0x00000000 + ldreq r2, =0x00000001 + moveq pc, lr + + /* Save the block size, set the block address bits to zero, and + * initialize the block count to one. + */ + mov r3, r1 + ldr r4, =0x00000000 + ldr r5, =0x00000001 + + /* Look for additional blocks of memory by searching for non-aliases. */ +find_blocks: + /* Store zero back to address zero. It may be overwritten. */ + str r0, [r0] + + /* Advance to the next power of two boundary. */ + mov r1, r1, lsl #1 + + /* Store the offset at the current offset. */ + str r1, [r0, r1] + + /* Read back from zero. */ + ldr r2, [r0] + + /* See if a non-alias was found. */ + cmp r1, r2 + + /* If a non-alias was found, then or in the block address bit and + * multiply the block count by two (since there are two unique + * blocks, one with this bit zero and one with it one). + */ + orrne r4, r4, r1 + movne r5, r5, lsl #1 + + /* Continue searching if there are more address bits to check. */ + cmp r1, #0x08000000 + bne find_blocks + + /* Return the block size, address mask, and count. */ + mov r0, r3 + mov r1, r4 + mov r2, r5 + + /* Return to the caller. */ + mov pc, lr + .globl lowlevel_init lowlevel_init: - /* backup return address */ - ldr r1, =SYSCON_SCRATCH0 - str lr, [r1] - /* Turn on both LEDs */ - bl red_led_on - bl green_led_on + mov r6, lr + + /* Make sure caches are off and invalidated. */ + ldr r0, =0x00000000 + mcr p15, 0, r0, c1, c0, 0 + nop + nop + nop + nop + nop + + /* Turn off the green LED and turn on the red LED. If the red LED + * is left on for too long, the external reset circuit described + * by application note AN258 will cause the system to reset. + */ + ldr r1, =EP93XX_LED_DATA + ldr r0, [r1] + bic r0, r0, #EP93XX_LED_GREEN_ON + orr r0, r0, #EP93XX_LED_RED_ON + str r0, [r1] + + /* Undo the silly static memory controller programming performed + * by the boot rom. + */ + ldr r0, =SMC_BASE + + /* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */ + ldr r1, =0x0000fbe0 + + /* Reset EP93XX_OFF_SMCBCR0 */ + ldr r2, [r0] + orr r2, r2, r1 + str r2, [r0] + + ldr r2, [r0, #EP93XX_OFF_SMCBCR1] + orr r2, r2, r1 + str r2, [r0, #EP93XX_OFF_SMCBCR1] + + ldr r2, [r0, #EP93XX_OFF_SMCBCR2] + orr r2, r2, r1 + str r2, [r0, #EP93XX_OFF_SMCBCR2] + + ldr r2, [r0, #EP93XX_OFF_SMCBCR3] + orr r2, r2, r1 + str r2, [r0, #EP93XX_OFF_SMCBCR3] + + ldr r2, [r0, #EP93XX_OFF_SMCBCR6] + orr r2, r2, r1 + str r2, [r0, #EP93XX_OFF_SMCBCR6] + + ldr r2, [r0, #EP93XX_OFF_SMCBCR7] + orr r2, r2, r1 + str r2, [r0, #EP93XX_OFF_SMCBCR7] + + /* Set the PLL1 and processor clock. */ + ldr r0, =SYSCON_BASE +#ifdef CONFIG_EDB9301 + /* 332MHz, giving a 166MHz processor clock. */ + ldr r1, = 0x02b49907 +#else + +#ifdef CONFIG_EDB93XX_INDUSTRIAL + /* 384MHz, giving a 196MHz processor clock. */ + ldr r1, =0x02a4bb38 +#else + /* 400MHz, giving a 200MHz processor clock. */ + ldr r1, =0x02a4e39e +#endif +#endif + str r1, [r0, #SYSCON_OFF_CLKSET1] + + nop + nop + nop + nop + nop + + /* Need to make sure that SDRAM is configured correctly before + * coping the code into it. + */ + +#ifdef CONFIG_EDB93XX_SDCS0 + mov r11, #SDRAM_DEVCFG0_BASE +#endif +#ifdef CONFIG_EDB93XX_SDCS1 + mov r11, #SDRAM_DEVCFG1_BASE +#endif +#ifdef CONFIG_EDB93XX_SDCS2 + mov r11, #SDRAM_DEVCFG2_BASE +#endif +#ifdef CONFIG_EDB93XX_SDCS3 + ldr r0, =SYSCON_BASE + ldr r0, [r0, #SYSCON_OFF_SYSCFG] + ands r0, r0, #SYSCON_SYSCFG_LASDO + moveq r11, #SDRAM_DEVCFG3_ASD0_BASE + movne r11, #SDRAM_DEVCFG3_ASD1_BASE +#endif + /* See Table 13-5 in EP93xx datasheet for more info about DRAM + * register mapping */ + + /* Try a 32-bit wide configuration of SDRAM. */ + ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \ + EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \ + EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \ + EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2) + + /* Set burst count: 4 and CAS: 2 + * Burst mode [A11:A10]; CAS [A16:A14] + */ + orr r2, r11, #0x00008800 + bl ep93xx_sdram_config + + /* Test the SDRAM. */ + mov r0, r11 + bl ep93xx_sdram_test + cmp r0, #0x00000000 + beq ep93xx_sdram_done + + /* Try a 16-bit wide configuration of SDRAM. */ + ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \ + EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \ + EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \ + EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \ + EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH) + + /* Set burst count: 8, CAS: 2, sequential burst + * Accoring to Table 13-3 for 16bit operations mapping must be shifted. + * Burst mode [A10:A9]; CAS [A15:A13] + */ + orr r2, r11, #0x00004600 + bl ep93xx_sdram_config + + /* Test the SDRAM. */ + mov r0, r11 + bl ep93xx_sdram_test + cmp r0, #0x00000000 + beq ep93xx_sdram_done + + /* Turn off the red LED. */ + ldr r0, =EP93XX_LED_DATA + ldr r1, [r0] + bic r1, r1, #EP93XX_LED_RED_ON + str r1, [r0] + + /* There is no SDRAM so flash the green LED. */ +flash_green: + orr r1, r1, #EP93XX_LED_GREEN_ON + str r1, [r0] + ldr r2, =0x00010000 +flash_green_delay_1: + subs r2, r2, #1 + bne flash_green_delay_1 + bic r1, r1, #EP93XX_LED_GREEN_ON + str r1, [r0] + ldr r2, =0x00010000 +flash_green_delay_2: + subs r2, r2, #1 + bne flash_green_delay_2 + orr r1, r1, #EP93XX_LED_GREEN_ON + str r1, [r0] + ldr r2, =0x00010000 +flash_green_delay_3: + subs r2, r2, #1 + bne flash_green_delay_3 + bic r1, r1, #EP93XX_LED_GREEN_ON + str r1, [r0] + ldr r2, =0x00050000 +flash_green_delay_4: + subs r2, r2, #1 + bne flash_green_delay_4 + b flash_green + - /* Configure flash wait states before we switch to the PLL */ - bl flash_cfg +ep93xx_sdram_done: + ldr r1, =EP93XX_LED_DATA + ldr r0, [r1] + bic r0, r0, #EP93XX_LED_RED_ON + str r0, [r1] - /* Set up PLL */ - bl pll_cfg + /* Determine the size of the SDRAM. */ + mov r0, r11 + bl ep93xx_sdram_size - /* Turn off the Green LED and leave the Red LED on */ - bl green_led_off + /* Save the SDRAM characteristics. */ + mov r8, r0 + mov r9, r1 + mov r10, r2 - /* Setup SDRAM */ - bl sdram_cfg + /* Compute total memory size into r1 */ + mul r1, r8, r10 +#ifdef CONFIG_EDB93XX_SDCS0 + ldr r2, [r0, #SDRAM_OFF_DEVCFG0] +#endif +#ifdef CONFIG_EDB93XX_SDCS1 + ldr r2, [r0, #SDRAM_OFF_DEVCFG1] +#endif +#ifdef CONFIG_EDB93XX_SDCS2 + ldr r2, [r0, #SDRAM_OFF_DEVCFG2] +#endif +#ifdef CONFIG_EDB93XX_SDCS3 + ldr r2, [r0, #SDRAM_OFF_DEVCFG3] +#endif - /* Turn on Green LED, Turn off the Red LED */ - bl green_led_on - bl red_led_off + /* Consider small DRAM size as: + * < 32Mb for 32bit bus + * < 64Mb for 16bit bus + */ + tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH + moveq r1, r1, lsr #1 + cmp r1, #0x02000000 - /* FIXME: we use async mode for now */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #0xc0000000 - mcr p15, 0, r0, c1, c0, 0 +#if defined(CONFIG_EDB9301) + /* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */ + movlt r1, #0x03f0 + movge r1, #0x01e0 +#else + /* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */ + movlt r1, #0x0600 + movge r1, #0x2f0 +#endif + str r1, [r0, #SDRAM_OFF_REFRSHTIMR] - /* restore return address */ - ldr r1, =SYSCON_SCRATCH0 - ldr lr, [r1] + /* Save the memory configuration information. */ + orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE + stmia r0, {r8-r11} - mov pc, lr + mov lr, r6 + mov pc, lr diff --git a/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/arch/arm/include/asm/arch-ep93xx/ep93xx.h index 9e7f2f3480b..330493b6065 100644 --- a/arch/arm/include/asm/arch-ep93xx/ep93xx.h +++ b/arch/arm/include/asm/arch-ep93xx/ep93xx.h @@ -1,6 +1,9 @@ /* * Cirrus Logic EP93xx register definitions. * + * Copyright (C) 2013 + * Sergey Kostanbaev fairwaves.ru> + * * Copyright (C) 2009 * Matthias Kaehlcke * @@ -287,6 +290,20 @@ struct sdram_regs { #define SDRAM_DEVCFG_CASLAT_2 0x00010000 #define SDRAM_DEVCFG_RASTOCAS_2 0x00200000 +#define SDRAM_OFF_GLCONFIG 0x0004 +#define SDRAM_OFF_REFRSHTIMR 0x0008 + +#define SDRAM_OFF_DEVCFG0 0x0010 +#define SDRAM_OFF_DEVCFG1 0x0014 +#define SDRAM_OFF_DEVCFG2 0x0018 +#define SDRAM_OFF_DEVCFG3 0x001C + +#define SDRAM_DEVCFG0_BASE 0xC0000000 +#define SDRAM_DEVCFG1_BASE 0xD0000000 +#define SDRAM_DEVCFG2_BASE 0xE0000000 +#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000 +#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000 + #define GLCONFIG_INIT (1 << 0) #define GLCONFIG_MRS (1 << 1) #define GLCONFIG_SMEMBUSY (1 << 5) @@ -295,6 +312,43 @@ struct sdram_regs { #define GLCONFIG_CLKSHUTDOWN (1 << 30) #define GLCONFIG_CKE (1 << 31) +#define EP93XX_SDRAMCTRL 0x80060000 +#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001 +#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002 +#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020 +#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040 +#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080 +#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000 +#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000 + +#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF + +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004 + +#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004 +#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008 +#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010 +#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020 +#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040 +#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000 +#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000 +#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000 + /* * 0x80070000 - 0x8007FFFF: Reserved */ @@ -324,6 +378,13 @@ struct smc_regs { }; #endif +#define EP93XX_OFF_SMCBCR0 0x00 +#define EP93XX_OFF_SMCBCR1 0x04 +#define EP93XX_OFF_SMCBCR2 0x08 +#define EP93XX_OFF_SMCBCR3 0x0C +#define EP93XX_OFF_SMCBCR6 0x18 +#define EP93XX_OFF_SMCBCR7 0x1C + #define SMC_BCR_IDCY_SHIFT 0 #define SMC_BCR_WST1_SHIFT 5 #define SMC_BCR_BLE (1 << 10) @@ -445,6 +506,14 @@ struct gpio_regs { }; #endif +#define EP93XX_LED_DATA 0x80840020 +#define EP93XX_LED_GREEN_ON 0x0001 +#define EP93XX_LED_RED_ON 0x0002 + +#define EP93XX_LED_DDR 0x80840024 +#define EP93XX_LED_GREEN_ENABLE 0x0001 +#define EP93XX_LED_RED_ENABLE 0x00020000 + /* * 0x80850000 - 0x8087FFFF: Reserved */ @@ -519,6 +588,9 @@ struct gpio_regs { #define SYSCON_OFFSET 0x930000 #define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET) +/* Security */ +#define SECURITY_EXTENSIONID 0x80832714 + #ifndef __ASSEMBLY__ struct syscon_regs { uint32_t pwrsts; @@ -553,7 +625,11 @@ struct syscon_regs { #define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040) #endif +#define SYSCON_OFF_CLKSET1 0x0020 +#define SYSCON_OFF_SYSCFG 0x009c + #define SYSCON_PWRCNT_UART_BAUD (1 << 29) +#define SYSCON_PWRCNT_USH_EN (1 << 28) #define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0 #define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5 @@ -571,6 +647,8 @@ struct syscon_regs { #define SYSCON_CHIPID_REV_MASK 0xF0000000 #define SYSCON_DEVICECFG_SWRST (1 << 31) +#define SYSCON_SYSCFG_LASDO 0x00000020 + /* * 0x80930000 - 0x8093FFFF: Watchdog Timer */ @@ -580,3 +658,10 @@ struct syscon_regs { /* * 0x80950000 - 0x9000FFFF: Reserved */ + +/* + * During low_level init we store memory layout in memory at specific location + */ +#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000 +#define UBOOT_MEMORYCNF_BANK_MASK 0x2004 +#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008 diff --git a/board/cirrus/edb93xx/Makefile b/board/cirrus/edb93xx/Makefile new file mode 100644 index 00000000000..d03c498478b --- /dev/null +++ b/board/cirrus/edb93xx/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2013 +# Sergey Kostanbaev fairwaves.ru> +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd denx.de. +# +# * SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := edb93xx.o diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c new file mode 100644 index 00000000000..8963d3a5828 --- /dev/null +++ b/board/cirrus/edb93xx/edb93xx.c @@ -0,0 +1,382 @@ +/* + * Board initialization for EP93xx + * + * Copyright (C) 2013 + * Sergey Kostanbaev fairwaves.ru> + * + * Copyright (C) 2009 + * Matthias Kaehlcke kaehlcke.net> + * + * (C) Copyright 2002 2003 + * Network Audio Technologies, Inc. + * Adam Bezanson netaudiotech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * usb_div: 4, nbyp2: 1, pll2_en: 1 + * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000, + * pll2_x2: 384000000.000000, pll2_out: 192000000.000000 + */ +#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ + 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ + 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ + 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \ + SYSCON_CLKSET2_PLL2_EN | \ + SYSCON_CLKSET2_NBYP2 | \ + 3 << SYSCON_CLKSET2_USB_DIV_SHIFT) + +#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \ + SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \ + 1 << SMC_BCR_MW_SHIFT) + +/* delay execution before timers are initialized */ +static inline void early_udelay(uint32_t usecs) +{ + /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */ + register uint32_t loops = (usecs * 1000) / 20; + + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + +#ifndef CONFIG_EP93XX_NO_FLASH_CFG +static void flash_cfg(void) +{ + struct smc_regs *smc = (struct smc_regs *)SMC_BASE; + + writel(SMC_BCR6_VALUE, &smc->bcr6); +} +#else +#define flash_cfg() +#endif + +int board_init(void) +{ + /* + * Setup PLL2, PPL1 has been set during lowlevel init + */ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + writel(CLKSET2_VAL, &syscon->clkset2); + + /* + * the user's guide recommends to wait at least 1 ms for PLL2 to + * stabilize + */ + early_udelay(1000); + + /* Go to Async mode */ + __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0"); + __asm__ volatile ("orr r0, r0, #0xc0000000"); + __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0"); + + icache_enable(); + +#ifdef USE_920T_MMU + dcache_enable(); +#endif + + /* Machine number, as defined in linux/arch/arm/tools/mach-types */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* We have a console */ + gd->have_console = 1; + + enable_interrupts(); + + flash_cfg(); + + green_led_on(); + red_led_off(); + + return 0; +} + +int board_early_init_f(void) +{ + /* + * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of + * 14.7456/2 MHz + */ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt); + return 0; +} + +int board_eth_init(bd_t *bd) +{ + return ep93xx_eth_initialize(0, MAC_BASE); +} + +static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt, + unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS]) +{ + if (dram_bank_cnt == 1) { + dram_bank_base[0] = PHYS_SDRAM_1; + } else { + /* Table lookup for holes in address space. Maximum memory + * for the single SDCS may be up to 256Mb. We start scanning + * banks from 1Mb, so it could be up to 128 banks theoretically. + * We need at maximum 7 bits for the loockup, 8 slots is + * enough for the worst case. + */ + unsigned tbl[8]; + unsigned i = dram_bank_cnt / 2; + unsigned j = 0x00100000; /* 1 Mb */ + unsigned *ptbl = tbl; + do { + while (!(dram_addr_mask & j)) { + j <<= 1; + } + *ptbl++ = j; + j <<= 1; + i >>= 1; + } while (i != 0); + + for (i = dram_bank_cnt, j = 0; + (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) { + unsigned addr = PHYS_SDRAM_1; + unsigned k; + unsigned bit; + + for (k = 0, bit = 1; k < 8; k++, bit <<= 1) { + if (bit & j) + addr |= tbl[k]; + } + + dram_bank_base[j] = addr; + } + } +} + +/* called in board_init_f (before relocation) */ +static unsigned dram_init_banksize_int(int print) +{ + /* + * Collect information of banks that has been filled during lowlevel + * initialization + */ + unsigned i; + unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS]; + unsigned dram_total = 0; + unsigned dram_bank_size = *(unsigned *) + (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE); + unsigned dram_addr_mask = *(unsigned *) + (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK); + unsigned dram_bank_cnt = *(unsigned *) + (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT); + + dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base); + + for (i = 0; i < dram_bank_cnt; i++) { + gd->bd->bi_dram[i].start = dram_bank_base[i]; + gd->bd->bi_dram[i].size = dram_bank_size; + dram_total += dram_bank_size; + } + for (; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = 0; + gd->bd->bi_dram[i].size = 0; + } + + if (print) { + printf("DRAM mask: %08x\n", dram_addr_mask); + printf("DRAM total %u banks:\n", dram_bank_cnt); + printf("bank base-address size\n"); + + if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) { + printf("WARNING! UBoot was configured for %u banks,\n" + "but %u has been found. " + "Supressing extra memory banks\n", + CONFIG_NR_DRAM_BANKS, dram_bank_cnt); + dram_bank_cnt = CONFIG_NR_DRAM_BANKS; + } + + for (i = 0; i < dram_bank_cnt; i++) { + printf(" %u %08x %08x\n", + i, dram_bank_base[i], dram_bank_size); + } + printf(" ------------------------------------------\n" + "Total %9d\n\n", + dram_total); + } + + return dram_total; +} + +void dram_init_banksize(void) +{ + dram_init_banksize_int(0); +} + +/* called in board_init_f (before relocation) */ +int dram_init(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + unsigned sec_id = readl(SECURITY_EXTENSIONID); + unsigned chip_id = readl(&syscon->chipid); + + printf("CPU: Cirrus Logic "); + switch (sec_id & 0x000001FE) { + case 0x00000008: + printf("EP9301"); + break; + case 0x00000004: + printf("EP9307"); + break; + case 0x00000002: + printf("EP931x"); + break; + case 0x00000000: + printf("EP9315"); + break; + default: + printf(""); + break; + } + + printf(" - Rev. "); + switch (chip_id & 0xF0000000) { + case 0x00000000: + printf("A"); + break; + case 0x10000000: + printf("B"); + break; + case 0x20000000: + printf("C"); + break; + case 0x30000000: + printf("D0"); + break; + case 0x40000000: + printf("D1"); + break; + case 0x50000000: + printf("E0"); + break; + case 0x60000000: + printf("E1"); + break; + case 0x70000000: + printf("E2"); + break; + default: + printf("?"); + break; + } + printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id); + + gd->ram_size = dram_init_banksize_int(1); + return 0; +} + + +#ifdef CONFIG_EP93XX_SPI +#include + +/* + * EGIO0-EGIPO7 -> port A + * EGIO8-EGIP15 -> port B + */ + +static void ep93xx_set_epgio(unsigned num) +{ + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; + if (num < 8) + writel(readl(®s->padr) | (1<padr); + else + writel(readl(®s->pbdr) | (1<<(num-8)), ®s->pbdr); +} + +static void ep93xx_clear_epgio(unsigned num) +{ + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; + if (num < 8) + writel(readl(®s->padr) & (~(1<padr); + else + writel(readl(®s->pbdr) & (~(1<<(num-8))), ®s->pbdr); +} + +static void ep93xx_dir_epgio_out(unsigned num) +{ + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; + if (num < 8) + writel(readl(®s->paddr) | (1<paddr); + else + writel(readl(®s->pbddr) | (1<<(num-8)), ®s->pbddr); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + if (bus == 0 && cs < 16) + return 1; + + return 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + ep93xx_clear_epgio(slave->cs); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + ep93xx_set_epgio(slave->cs); +} + +#ifdef CONFIG_MMC_SPI +#include + +#ifndef CONFIG_MMC_SPI_CS_EPGIO +# define CONFIG_MMC_SPI_CS_EPGIO 4 +#endif + +#ifndef CONFIG_MMC_SPI_SPEED +# define CONFIG_MMC_SPI_SPEED 25000000 +#endif + +#ifndef CONFIG_MMC_SPI_MODE +# define CONFIG_MMC_SPI_MODE SPI_MODE_0 +#endif + +int board_mmc_init(bd_t *bis) +{ + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE; + + ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO); + ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO); + +#ifdef CONFIG_MMC_SPI_POWER_EGPIO + ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO); + ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO); +#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO) + ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO); + ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO); +#endif + struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO, + CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE); + + if (!mmc) { + printf("Failed to create MMC Device\n"); + return 1; + } + mmc_init(mmc); + return 0; +} + + +#endif /* CONFIG_MMC_SPI */ +#endif /* CONFIG_EP93XX_SPI */ diff --git a/board/cirrus/edb93xx/u-boot.lds b/board/cirrus/edb93xx/u-boot.lds new file mode 100644 index 00000000000..b0d892a59f4 --- /dev/null +++ b/board/cirrus/edb93xx/u-boot.lds @@ -0,0 +1,115 @@ +/* + * + * Copyright (C) 2013 + * Sergey Kostanbaev fairwaves.ru> + * + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : { + *(.__image_copy_start) + arch/arm/cpu/arm920t/start.o (.text*) + . = 0x1000; + + LONG(0x53555243) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu.hash : { *(.gnu.hash) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } + .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } +} diff --git a/boards.cfg b/boards.cfg index fda4f9ca084..7a3b7c1aadf 100644 --- a/boards.cfg +++ b/boards.cfg @@ -78,6 +78,7 @@ Active arm arm920t ks8695 - - Active arm arm920t ks8695 - - cm41xx - - Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller +Active arm arm920t ep93xx cirrus edb93xx edb9315a edb93xx:MK_edb9315a Sergey Kostanbaev Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij Active arm arm926ejs - armltd integrator integratorcp_cm926ejs integratorcp:CM924EJ_S Linus Walleij Active arm arm926ejs armada100 Marvell - aspenite - Prafulla Wadaskar diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index b587308c849..f02c35a52c0 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -8,6 +8,7 @@ # There are many options which enable SPI, so make this library available obj-y += spi.o +obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ANDES_SPI) += andes_spi.o obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o diff --git a/drivers/spi/ep93xx_spi.c b/drivers/spi/ep93xx_spi.c new file mode 100644 index 00000000000..235557ea3c5 --- /dev/null +++ b/drivers/spi/ep93xx_spi.c @@ -0,0 +1,274 @@ +/* + * SPI Driver for EP93xx + * + * Copyright (C) 2013 Sergey Kostanabev fairwaves.ru> + * + * Inspired form linux kernel driver and atmel uboot driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include + +#include + + +#define BIT(x) (1<<(x)) +#define SSPBASE SPI_BASE + +#define SSPCR0 0x0000 +#define SSPCR0_MODE_SHIFT 6 +#define SSPCR0_SCR_SHIFT 8 +#define SSPCR0_SPH BIT(7) +#define SSPCR0_SPO BIT(6) +#define SSPCR0_FRF_SPI 0 +#define SSPCR0_DSS_8BIT 7 + +#define SSPCR1 0x0004 +#define SSPCR1_RIE BIT(0) +#define SSPCR1_TIE BIT(1) +#define SSPCR1_RORIE BIT(2) +#define SSPCR1_LBM BIT(3) +#define SSPCR1_SSE BIT(4) +#define SSPCR1_MS BIT(5) +#define SSPCR1_SOD BIT(6) + +#define SSPDR 0x0008 + +#define SSPSR 0x000c +#define SSPSR_TFE BIT(0) +#define SSPSR_TNF BIT(1) +#define SSPSR_RNE BIT(2) +#define SSPSR_RFF BIT(3) +#define SSPSR_BSY BIT(4) +#define SSPCPSR 0x0010 + +#define SSPIIR 0x0014 +#define SSPIIR_RIS BIT(0) +#define SSPIIR_TIS BIT(1) +#define SSPIIR_RORIS BIT(2) +#define SSPICR SSPIIR + +#define SSPCLOCK 14745600 +#define SSP_MAX_RATE (SSPCLOCK / 2) +#define SSP_MIN_RATE (SSPCLOCK / (254 * 256)) + +/* timeout in milliseconds */ +#define SPI_TIMEOUT 5 +/* maximum depth of RX/TX FIFO */ +#define SPI_FIFO_SIZE 8 + +struct ep93xx_spi_slave { + struct spi_slave slave; + + unsigned sspcr0; + unsigned sspcpsr; +}; + +static inline struct ep93xx_spi_slave *to_ep93xx_spi(struct spi_slave *slave) +{ + return container_of(slave, struct ep93xx_spi_slave, slave); +} + +void spi_init() +{ +} + +static inline void ep93xx_spi_write_u8(u16 reg, u8 value) +{ + writel(value, (unsigned int *)(SSPBASE + reg)); +} + +static inline u8 ep93xx_spi_read_u8(u16 reg) +{ + return readl((unsigned int *)(SSPBASE + reg)); +} + +static inline void ep93xx_spi_write_u16(u16 reg, u16 value) +{ + writel(value, (unsigned int *)(SSPBASE + reg)); +} + +static inline u16 ep93xx_spi_read_u16(u16 reg) +{ + return (u16)readl((unsigned int *)(SSPBASE + reg)); +} + +static int ep93xx_spi_init_hw(unsigned int rate, unsigned int mode, + struct ep93xx_spi_slave *slave) +{ + unsigned cpsr, scr; + + if (rate > SSP_MAX_RATE) + rate = SSP_MAX_RATE; + + if (rate < SSP_MIN_RATE) + return -1; + + /* Calculate divisors so that we can get speed according the + * following formula: + * rate = spi_clock_rate / (cpsr * (1 + scr)) + * + * cpsr must be even number and starts from 2, scr can be any number + * between 0 and 255. + */ + for (cpsr = 2; cpsr <= 254; cpsr += 2) { + for (scr = 0; scr <= 255; scr++) { + if ((SSPCLOCK / (cpsr * (scr + 1))) <= rate) { + /* Set CHPA and CPOL, SPI format and 8bit */ + unsigned sspcr0 = (scr << SSPCR0_SCR_SHIFT) | + SSPCR0_FRF_SPI | SSPCR0_DSS_8BIT; + if (mode & SPI_CPHA) + sspcr0 |= SSPCR0_SPH; + if (mode & SPI_CPOL) + sspcr0 |= SSPCR0_SPO; + + slave->sspcr0 = sspcr0; + slave->sspcpsr = cpsr; + return 0; + } + } + } + + return -1; +} + +void spi_set_speed(struct spi_slave *slave, unsigned int hz) +{ + struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); + + unsigned int mode = 0; + if (as->sspcr0 & SSPCR0_SPH) + mode |= SPI_CPHA; + if (as->sspcr0 & SSPCR0_SPO) + mode |= SPI_CPOL; + + ep93xx_spi_init_hw(hz, mode, as); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct ep93xx_spi_slave *as; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + as = spi_alloc_slave(struct ep93xx_spi_slave, bus, cs); + if (!as) + return NULL; + + if (ep93xx_spi_init_hw(max_hz, mode, as)) { + free(as); + return NULL; + } + + return &as->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); + + free(as); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); + + /* Enable the SPI hardware */ + ep93xx_spi_write_u8(SSPCR1, SSPCR1_SSE); + + + ep93xx_spi_write_u8(SSPCPSR, as->sspcpsr); + ep93xx_spi_write_u16(SSPCR0, as->sspcr0); + + debug("Select CS:%d SSPCPSR=%02x SSPCR0=%04x\n", + slave->cs, as->sspcpsr, as->sspcr0); + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Disable the SPI hardware */ + ep93xx_spi_write_u8(SSPCR1, 0); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + unsigned int len_tx; + unsigned int len_rx; + unsigned int len; + u32 status; + const u8 *txp = dout; + u8 *rxp = din; + u8 value; + + debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n", + slave->bus, slave->cs, (uint *)dout, (uint *)din, bitlen); + + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + if (bitlen % 8) { + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + + if (flags & SPI_XFER_BEGIN) { + /* Empty RX FIFO */ + while ((ep93xx_spi_read_u8(SSPSR) & SSPSR_RNE)) + ep93xx_spi_read_u8(SSPDR); + + spi_cs_activate(slave); + } + + for (len_tx = 0, len_rx = 0; len_rx < len; ) { + status = ep93xx_spi_read_u8(SSPSR); + + if ((len_tx < len) && (status & SSPSR_TNF)) { + if (txp) + value = *txp++; + else + value = 0xff; + + ep93xx_spi_write_u8(SSPDR, value); + len_tx++; + } + + if (status & SSPSR_RNE) { + value = ep93xx_spi_read_u8(SSPDR); + + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) { + /* + * Wait until the transfer is completely done before + * we deactivate CS. + */ + do { + status = ep93xx_spi_read_u8(SSPSR); + } while (status & SSPSR_BSY); + + spi_cs_deactivate(slave); + } + + return 0; +} diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 7211c6ad964..04c1a642a3f 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o obj-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o +obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o # echi obj-$(CONFIG_USB_EHCI) += ehci-hcd.o diff --git a/drivers/usb/host/ohci-ep93xx.c b/drivers/usb/host/ohci-ep93xx.c new file mode 100644 index 00000000000..8fb4ababec1 --- /dev/null +++ b/drivers/usb/host/ohci-ep93xx.c @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2013 + * Sergey Kostanbaev < sergey.kostanbaev fairwaves.ru > + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) +#include +#include + +int usb_cpu_init(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + unsigned long pwr = readl(&syscon->pwrcnt); + writel(pwr | SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt); + + return 0; +} + +int usb_cpu_stop(void) +{ + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + unsigned long pwr = readl(&syscon->pwrcnt); + writel(pwr & ~SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt); + + return 0; +} + +int usb_cpu_init_fail(void) +{ + return usb_cpu_stop(); +} + +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h new file mode 100644 index 00000000000..37bdcc0f332 --- /dev/null +++ b/include/configs/edb93xx.h @@ -0,0 +1,292 @@ +/* + * U-boot - Configuration file for Cirrus Logic EDB93xx boards + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_MK_edb9301 +#define CONFIG_EDB9301 +#elif defined(CONFIG_MK_edb9302) +#define CONFIG_EDB9302 +#elif defined(CONFIG_MK_edb9302a) +#define CONFIG_EDB9302A +#elif defined(CONFIG_MK_edb9307) +#define CONFIG_EDB9307 +#elif defined(CONFIG_MK_edb9307a) +#define CONFIG_EDB9307A +#elif defined(CONFIG_MK_edb9312) +#define CONFIG_EDB9312 +#elif defined(CONFIG_MK_edb9315) +#define CONFIG_EDB9315 +#elif defined(CONFIG_MK_edb9315a) +#define CONFIG_EDB9315A +#else +#error "no board defined" +#endif + +/* Initial environment and monitor configuration options. */ +#define CONFIG_BOOTDELAY 2 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp" +#define CONFIG_BOOTFILE "edb93xx.img" + +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + + +#define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds" + + +#ifdef CONFIG_EDB9301 +#define CONFIG_EP9301 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301 +#define CONFIG_SYS_PROMPT "EDB9301> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9302) +#define CONFIG_EP9302 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302 +#define CONFIG_SYS_PROMPT "EDB9302> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9302A) +#define CONFIG_EP9302 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A +#define CONFIG_SYS_PROMPT "EDB9302A> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9307) +#define CONFIG_EP9307 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307 +#define CONFIG_SYS_PROMPT "EDB9307> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9307A) +#define CONFIG_EP9307 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A +#define CONFIG_SYS_PROMPT "EDB9307A> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9312) +#define CONFIG_EP9312 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312 +#define CONFIG_SYS_PROMPT "EDB9312> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9315) +#define CONFIG_EP9315 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315 +#define CONFIG_SYS_PROMPT "EDB9315> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9315A) +#define CONFIG_EP9315 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A +#define CONFIG_SYS_PROMPT "EDB9315A> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#else +#error "no board defined" +#endif + +/* High-level configuration options */ +#define CONFIG_ARM920T 1 /* This is an ARM920T core... */ +#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */ + +#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ +#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */ +#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ + +/* Monitor configuration */ +#include +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#undef CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_JFFS2 + +#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +/* Print buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +/* Boot argument buffer size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ + +/* Serial port hardware configuration */ +#define CONFIG_PL010_SERIAL +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \ + 115200, 230400} +#define CONFIG_SYS_SERIAL0 0x808C0000 +#define CONFIG_SYS_SERIAL1 0x808D0000 +/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} */ + +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} + +/* Status LED */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 +#define STATUS_LED_GREEN 0 +#define STATUS_LED_RED 1 +/* Green */ +#define STATUS_LED_BIT STATUS_LED_GREEN +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +/* Red */ +#define STATUS_LED_BIT1 STATUS_LED_RED +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* Optional value */ +#define STATUS_LED_BOOT STATUS_LED_BIT + +/* Network hardware configuration */ +#define CONFIG_DRIVER_EP93XX_MAC +#define CONFIG_MII_SUPPRESS_PREAMBLE +#define CONFIG_MII +#define CONFIG_PHY_ADDR 1 +#define CONFIG_NET_MULTI +#undef CONFIG_NETCONSOLE + +/* SDRAM configuration */ +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ + defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \ + defined(CONFIG_EDB9315) +/* + * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + * + * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of + * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of + * 64 MB of SDRAM. + */ + +#define CONFIG_EDB93XX_SDCS3 + +#elif defined(CONFIG_EDB9302A) || \ + defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A) +/* + * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + * + * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung + * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM. + */ +#define CONFIG_EDB93XX_SDCS0 + +#else +#error "no SDCS configuration for this board" +#endif + + +#if defined(CONFIG_EDB93XX_SDCS3) +#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */ +#define PHYS_SDRAM_1 0x00000000 +#elif defined(CONFIG_EDB93XX_SDCS0) +#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */ +#define PHYS_SDRAM_1 0xc0000000 +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_NR_DRAM_BANKS 8 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE) + + +/* Must match kernel config */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) + +/* Run-time memory allocatons */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_STACKSIZE (128 * 1024) + +#if defined(CONFIG_USE_IRQ) +#define CONFIG_STACKSIZE_IRQ (4 * 1024) +#define CONFIG_STACKSIZE_FIQ (4 * 1024) +#endif + +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) + +/* ----------------------------------------------------------------------------- + * FLASH and environment organization + * + * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at + * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit + * data bus, for a total of 16 MB of CFI-compatible flash. + * + * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at + * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit + * data bus, for a total of 32 MB of CFI-compatible flash. + * + * + * EDB9301/02(a)7a/15a EDB9307/12/15 + * 0x60000000 - 0x0003FFFF u-boot u-boot + * 0x60040000 - 0x0005FFFF environment #1 environment #1 + * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued) + * 0x60080000 - 0x0009FFFF unused environment #2 + * 0x600A0000 - 0x000BFFFF unused environment #2 (continued) + * 0x600C0000 - 0x00FFFFFF unused unused + * 0x61000000 - 0x01FFFFFF not present unused + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + + +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT (256+8) + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */ +#define CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_ADDR 0x60040000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) + +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* Define to enable MMC on SPI support */ +/* #define CONFIG_EP93XX_SPI_MMC */ + +#ifdef CONFIG_EP93XX_SPI_MMC +#define CONFIG_EP93XX_SPI +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SPI +#define CONFIG_CMD_MMC +#define CONFIG_MMC_SPI_NPOWER_EGPIO 9 +#endif + +#define CONFIG_USB_STORAGE +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_OHCI_EP93XX +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci" +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000 + +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_CMD_BOOTZ + +/* Define to disable flash configuration*/ +/* #define CONFIG_EP93XX_NO_FLASH_CFG */ + +/* Define this for indusrial rated chips */ +/* #define CONFIG_EDB93XX_INDUSTRIAL */ + +#endif /* !defined (__CONFIG_H) */ -- cgit v1.3.1 From d8c67dc6e1f861bcf6e61c0b67782fbac2e0a010 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 10 Jun 2014 01:10:21 -0500 Subject: watchdog/denali: Adding DesignWare watchdog driver support To add the DesignWare watchdog driver support. It required information such as register base address and clock info from configuration header file within include/configs folder. Signed-off-by: Chin Liang See Cc: Anatolij Gustschin Cc: Albert Aribaud Cc: Heiko Schocher Cc: Tom Rini --- drivers/watchdog/Makefile | 1 + drivers/watchdog/designware_wdt.c | 74 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 drivers/watchdog/designware_wdt.c (limited to 'drivers') diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 06ced10c356..0276a10564c 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o +obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c new file mode 100644 index 00000000000..e788e1b65d0 --- /dev/null +++ b/drivers/watchdog/designware_wdt.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define DW_WDT_CR 0x00 +#define DW_WDT_TORR 0x04 +#define DW_WDT_CRR 0x0C + +#define DW_WDT_CR_EN_OFFSET 0x00 +#define DW_WDT_CR_RMOD_OFFSET 0x01 +#define DW_WDT_CR_RMOD_VAL 0x00 +#define DW_WDT_CRR_RESTART_VAL 0x76 + +/* + * Set the watchdog time interval. + * Counter is 32 bit. + */ +static int designware_wdt_settimeout(unsigned int timeout) +{ + signed int i; + + /* calculate the timeout range value */ + i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16; + if (i > 15) + i = 15; + if (i < 0) + i = 0; + + writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR)); + return 0; +} + +static void designware_wdt_enable(void) +{ + writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | + (0x1 << DW_WDT_CR_EN_OFFSET)), + (CONFIG_DW_WDT_BASE + DW_WDT_CR)); +} + +static unsigned int designware_wdt_is_enabled(void) +{ + unsigned long val; + val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR)); + return val & 0x1; +} + +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ + if (designware_wdt_is_enabled()) + /* restart the watchdog counter */ + writel(DW_WDT_CRR_RESTART_VAL, + (CONFIG_DW_WDT_BASE + DW_WDT_CRR)); +} + +void hw_watchdog_init(void) +{ + /* reset to disable the watchdog */ + hw_watchdog_reset(); + /* set timer in miliseconds */ + designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS); + /* enable the watchdog */ + designware_wdt_enable(); + /* reset the watchdog */ + hw_watchdog_reset(); +} +#endif -- cgit v1.3.1 From a8b0f9b685072e1d3acd01741e7db6833b445b2a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Jun 2014 22:10:52 +0900 Subject: build: define CPU only when arch/${ARCH}/cpu/${CPU} exists MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The directory arch/${ARCH}/cpu/${CPU} does not exist in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86. These architectures have only one CPU type. Defining CPU should not be required for such architectures. This commit allows cpu field (= the 3rd field of boards.cfg) to be kept blank. Signed-off-by: Masahiro Yamada Cc: Andreas Bießmann Cc: Simon Glass Cc: Sonic Zhang Cc: Michal Simek Cc: Thomas Chou Cc: Stefan Kristiansson --- arch/sandbox/include/asm/arch-sandbox/sound.h | 14 ---- arch/sandbox/include/asm/sound.h | 14 ++++ boards.cfg | 104 +++++++++++++------------- config.mk | 5 +- drivers/sound/sandbox.c | 2 +- mkconfig | 11 ++- 6 files changed, 76 insertions(+), 74 deletions(-) delete mode 100644 arch/sandbox/include/asm/arch-sandbox/sound.h create mode 100644 arch/sandbox/include/asm/sound.h (limited to 'drivers') diff --git a/arch/sandbox/include/asm/arch-sandbox/sound.h b/arch/sandbox/include/asm/arch-sandbox/sound.h deleted file mode 100644 index a32e8c802d7..00000000000 --- a/arch/sandbox/include/asm/arch-sandbox/sound.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2013 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __SANDBOX_SOUND_H -#define __SANDBOX_SOUND_H - -int sound_play(unsigned int msec, unsigned int frequency); - -int sound_init(const void *blob); - -#endif diff --git a/arch/sandbox/include/asm/sound.h b/arch/sandbox/include/asm/sound.h new file mode 100644 index 00000000000..a32e8c802d7 --- /dev/null +++ b/arch/sandbox/include/asm/sound.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SANDBOX_SOUND_H +#define __SANDBOX_SOUND_H + +int sound_play(unsigned int msec, unsigned int frequency); + +int sound_init(const void *blob); + +#endif diff --git a/boards.cfg b/boards.cfg index 6f8d168cf15..3fbf714b327 100644 --- a/boards.cfg +++ b/boards.cfg @@ -419,36 +419,36 @@ Active arm pxa - - vpac270 Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich Active arm pxa - toradex - colibri_pxa270 - Marek Vasut Active arm sa1100 - - - jornada - Kristoffer Ericson -Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann -Active avr32 at32ap at32ap700x in-circuit - grasshopper - Andreas Bießmann -Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson -Active avr32 at32ap at32ap700x miromico - hammerhead - Alex Raimondi -Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald -Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang -Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang -Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang :Chong Huang -Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang -Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang -Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang -Active blackfin blackfin - - - bf527-sdp - Sonic Zhang -Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang -Active blackfin blackfin - - - bf533-stamp - Sonic Zhang -Active blackfin blackfin - - - bf537-minotaur - Martin Strubel -Active blackfin blackfin - - - bf537-pnav - Sonic Zhang -Active blackfin blackfin - - - bf537-srv1 - Martin Strubel -Active blackfin blackfin - - - bf537-stamp - Sonic Zhang -Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang -Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang -Active blackfin blackfin - - - bf561-acvilon - Valentin Yakovenkov -Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang -Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang -Active blackfin blackfin - - - blackstamp - Wojtek Skulski :Wojtek Skulski :Benjamin Matthews -Active blackfin blackfin - - - blackvme - Wojtek Skulski :Wojtek Skulski :Benjamin Matthews -Active blackfin blackfin - - - br4 - Dimitar Penev -Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) -Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule -Active blackfin blackfin - - - pr1 - Dimitar Penev -Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang +Active avr32 - at32ap700x atmel - atngw100mkii - Andreas Bießmann +Active avr32 - at32ap700x in-circuit - grasshopper - Andreas Bießmann +Active avr32 - at32ap700x mimc - mimc200 - Mark Jackson +Active avr32 - at32ap700x miromico - hammerhead - Alex Raimondi +Active blackfin - - - - bct-brettl2 - Peter Meerwald +Active blackfin - - - - bf506f-ezkit - Sonic Zhang +Active blackfin - - - - bf518f-ezbrd - Sonic Zhang +Active blackfin - - - - bf525-ucr2 - Haitao Zhang :Chong Huang +Active blackfin - - - - bf526-ezbrd - Sonic Zhang +Active blackfin - - - - bf527-ad7160-eval - Sonic Zhang +Active blackfin - - - - bf527-ezkit - Sonic Zhang +Active blackfin - - - - bf527-sdp - Sonic Zhang +Active blackfin - - - - bf533-ezkit - Sonic Zhang +Active blackfin - - - - bf533-stamp - Sonic Zhang +Active blackfin - - - - bf537-minotaur - Martin Strubel +Active blackfin - - - - bf537-pnav - Sonic Zhang +Active blackfin - - - - bf537-srv1 - Martin Strubel +Active blackfin - - - - bf537-stamp - Sonic Zhang +Active blackfin - - - - bf538f-ezkit - Sonic Zhang +Active blackfin - - - - bf548-ezkit - Sonic Zhang +Active blackfin - - - - bf561-acvilon - Valentin Yakovenkov +Active blackfin - - - - bf561-ezkit - Sonic Zhang +Active blackfin - - - - bf609-ezkit - Sonic Zhang +Active blackfin - - - - blackstamp - Wojtek Skulski :Wojtek Skulski :Benjamin Matthews +Active blackfin - - - - blackvme - Wojtek Skulski :Wojtek Skulski :Benjamin Matthews +Active blackfin - - - - br4 - Dimitar Penev +Active blackfin - - - - dnp5370 - M.Hasewinkel (MHA) +Active blackfin - - - - ibf-dsp561 - I-SYST Micromodule +Active blackfin - - - - pr1 - Dimitar Penev +Active blackfin - - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew @@ -496,7 +496,7 @@ Active m68k mcf547x_8x - freescale m548xevb Active m68k mcf547x_8x - freescale m548xevb M5485FFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew -Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek +Active microblaze - - xilinx microblaze-generic microblaze-generic - Michal Simek Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN - Active mips mips32 - imgtec malta malta malta:SYS_BIG_ENDIAN Paul Burton @@ -524,10 +524,10 @@ Active mips mips64 - - qemu-mips Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes Active nds32 n1213 ag101 AndesTech adp-ag101p adp-ag101p - Andes Active nds32 n1213 ag102 AndesTech adp-ag102 adp-ag102 - Andes -Active nios2 nios2 - altera nios2-generic nios2-generic - Scott McNutt -Active nios2 nios2 - psyent pci5441 PCI5441 - Scott McNutt -Active nios2 nios2 - psyent pk1c20 PK1C20 - Scott McNutt -Active openrisc or1200 - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson +Active nios2 - - altera nios2-generic nios2-generic - Scott McNutt +Active nios2 - - psyent pci5441 PCI5441 - Scott McNutt +Active nios2 - - psyent pk1c20 PK1C20 - Scott McNutt +Active openrisc - - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson Active powerpc 74xx_7xx - - - ppmc7xx - - Active powerpc 74xx_7xx - - evb64260 P3G4 - Wolfgang Denk Active powerpc 74xx_7xx - eltec elppc ELPPC - - @@ -1150,7 +1150,7 @@ Active powerpc ppc4xx - xilinx ppc405-generic Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda -Active sandbox sandbox - - sandbox sandbox - Simon Glass +Active sandbox - - - sandbox sandbox - Simon Glass Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu :Nobuhiro Iwamatsu Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy Active sh sh2 - renesas rsk7269 rsk7269 - - @@ -1178,7 +1178,7 @@ Active sparc leon3 - gaisler - Active sparc leon3 - gaisler - gr_ep2s60 - - Active sparc leon3 - gaisler - gr_xc3s_1500 - - Active sparc leon3 - gaisler - grsim - - -Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 Simon Glass +Active x86 - coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 Simon Glass # The following were moved to "Orphan" in June, 2014 Orphan arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park Orphan arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre @@ -1189,13 +1189,13 @@ Orphan arm arm926ejs at91 calao tny_a9260 Orphan arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre Orphan arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre Orphan arm pxa - - - palmtreo680 - Mike Dunn -Orphan avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen -Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen -Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen -Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen -Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen -Orphan avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt -Orphan blackfin blackfin - - - ip04 - Brent Kandetzki +Orphan avr32 - at32ap700x atmel - atngw100 - Haavard Skinnemoen +Orphan avr32 - at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen +Orphan avr32 - at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen +Orphan avr32 - at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen +Orphan avr32 - at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen +Orphan avr32 - at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt +Orphan blackfin - - - - ip04 - Brent Kandetzki Orphan m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt @@ -1226,14 +1226,14 @@ Orphan powerpc mpc824x - - musenki Orphan powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson Orphan powerpc mpc8260 - - - ppmc8260 - Brad Kemp # The following were moved to "Orphan" in March, 2014 -Orphan blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards -Orphan blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards -Orphan blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards -Orphan blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards -Orphan blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards -Orphan blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards -Orphan blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards -Orphan blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards +Orphan blackfin - - - - cm-bf527 - Bluetechnix Tinyboards +Orphan blackfin - - - - cm-bf533 - Bluetechnix Tinyboards +Orphan blackfin - - - - cm-bf537e - Bluetechnix Tinyboards +Orphan blackfin - - - - cm-bf537u - Bluetechnix Tinyboards +Orphan blackfin - - - - cm-bf548 - Bluetechnix Tinyboards +Orphan blackfin - - - - cm-bf561 - Bluetechnix Tinyboards +Orphan blackfin - - - - tcm-bf518 - Bluetechnix Tinyboards +Orphan blackfin - - - - tcm-bf537 - Bluetechnix Tinyboards Orphan powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz Orphan powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov diff --git a/config.mk b/config.mk index 05864aabb5a..bd74732d48d 100644 --- a/config.mk +++ b/config.mk @@ -24,10 +24,7 @@ OBJCOPYFLAGS := # so calculate CPUDIR before including ARCH/SOC/CPU config.mk files. # Check if arch/$ARCH/cpu/$CPU exists, otherwise assume arch/$ARCH/cpu contains # CPU-specific code. -CPUDIR=arch/$(ARCH)/cpu/$(CPU) -ifneq ($(srctree)/$(CPUDIR),$(wildcard $(srctree)/$(CPUDIR))) -CPUDIR=arch/$(ARCH)/cpu -endif +CPUDIR=arch/$(ARCH)/cpu$(if $(CPU),/$(CPU),) sinclude $(srctree)/arch/$(ARCH)/config.mk # include architecture dependend rules sinclude $(srctree)/$(CPUDIR)/config.mk # include CPU specific rules diff --git a/drivers/sound/sandbox.c b/drivers/sound/sandbox.c index fe5c9e9b38d..5599bb948fe 100644 --- a/drivers/sound/sandbox.c +++ b/drivers/sound/sandbox.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include int sound_play(uint32_t msec, uint32_t frequency) diff --git a/mkconfig b/mkconfig index 2bf5897528d..401f2623f35 100755 --- a/mkconfig +++ b/mkconfig @@ -55,6 +55,11 @@ CONFIG_NAME="${7%_config}" arch="$2" cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $1}'` spl_cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $2}'` + +if [ "$cpu" = "-" ] ; then + cpu= +fi + if [ "$6" = "" ] ; then board= elif [ "$6" = "-" ] ; then @@ -114,10 +119,10 @@ fi rm -f asm/arch -if [ -z "${soc}" ] ; then - ln -s ${LNPREFIX}arch-${cpu} asm/arch -else +if [ "${soc}" ] ; then ln -s ${LNPREFIX}arch-${soc} asm/arch +elif [ "${cpu}" ] ; then + ln -s ${LNPREFIX}arch-${cpu} asm/arch fi if [ -z "$KBUILD_SRC" ] ; then -- cgit v1.3.1 From 49f9337956af6d52470c8082c8e7088b0c030334 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Wed, 18 Jun 2014 22:59:48 +0200 Subject: tpm: don't use unneeded double brackets clang is tempted to inteprete such a condition as a assignment as well. Since it isn't don't use double brackets. cc: Tom Wai-Hong Tam Signed-off-by: Jeroen Hofstee --- drivers/tpm/tpm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/tpm/tpm.c b/drivers/tpm/tpm.c index b6573341956..bc0f9645b59 100644 --- a/drivers/tpm/tpm.c +++ b/drivers/tpm/tpm.c @@ -411,7 +411,7 @@ static ssize_t tpm_transmit(const unsigned char *buf, size_t bufsiz) goto out_recv; } - if ((status == chip->vendor.req_canceled)) { + if (status == chip->vendor.req_canceled) { error("Operation Canceled\n"); rc = -ECANCELED; goto out; -- cgit v1.3.1 From 0657e46e28a3b0cf5fe1219f50a9f99fe7f9e90a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 20 Jun 2014 13:54:52 +0900 Subject: mpc8xx: remove RPXlite_dw, quantum board support These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc8xx/cpu_init.c | 5 - arch/powerpc/cpu/mpc8xx/scc.c | 4 - arch/powerpc/cpu/mpc8xx/serial.c | 5 - board/RPXlite_dw/Makefile | 8 - board/RPXlite_dw/README | 161 ------------- board/RPXlite_dw/RPXlite_dw.c | 164 ------------- board/RPXlite_dw/flash.c | 474 ------------------------------------- board/RPXlite_dw/u-boot.lds | 82 ------- board/RPXlite_dw/u-boot.lds.debug | 121 ---------- board/quantum/Makefile | 8 - board/quantum/fpga.c | 247 ------------------- board/quantum/fpga.h | 16 -- board/quantum/quantum.c | 243 ------------------- board/quantum/u-boot.lds | 82 ------- board/quantum/u-boot.lds.debug | 114 --------- boards.cfg | 9 - doc/README.scrapyard | 2 + drivers/pcmcia/Makefile | 1 - drivers/pcmcia/mpc8xx_pcmcia.c | 10 - drivers/pcmcia/rpx_pcmcia.c | 73 ------ drivers/video/mpc8xx_lcd.c | 5 - include/common.h | 2 - include/commproc.h | 26 -- include/configs/RPXlite_DW.h | 462 ------------------------------------ include/configs/quantum.h | 430 --------------------------------- include/pcmcia.h | 5 +- post/cpu/mpc8xx/ether.c | 4 - post/cpu/mpc8xx/uart.c | 5 - 28 files changed, 3 insertions(+), 2765 deletions(-) delete mode 100644 board/RPXlite_dw/Makefile delete mode 100644 board/RPXlite_dw/README delete mode 100644 board/RPXlite_dw/RPXlite_dw.c delete mode 100644 board/RPXlite_dw/flash.c delete mode 100644 board/RPXlite_dw/u-boot.lds delete mode 100644 board/RPXlite_dw/u-boot.lds.debug delete mode 100644 board/quantum/Makefile delete mode 100644 board/quantum/fpga.c delete mode 100644 board/quantum/fpga.h delete mode 100644 board/quantum/quantum.c delete mode 100644 board/quantum/u-boot.lds delete mode 100644 board/quantum/u-boot.lds.debug delete mode 100644 drivers/pcmcia/rpx_pcmcia.c delete mode 100644 include/configs/RPXlite_DW.h delete mode 100644 include/configs/quantum.h (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 9c3102dc69f..b4001de5120 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -138,7 +138,6 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_MHPC) || \ defined(CONFIG_R360MPI) || \ defined(CONFIG_RMU) || \ - defined(CONFIG_RPXLITE) || \ defined(CONFIG_SPC1920) || \ defined(CONFIG_SPD823TS) @@ -206,10 +205,6 @@ void cpu_init_f (volatile immap_t * immr) __asm__ ("eieio"); } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); -#if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM) - rpxlite_init (); -#endif - #ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */ /* write config value */ immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index da372d039eb..7ed98b879f8 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -461,10 +461,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined #endif -#ifdef CONFIG_RPXLITE - *((uchar *) BCSR0) |= BCSR0_ETHEN; -#endif - #if defined(CONFIG_NETVIA) #if defined(PA_ENET_PDN) immr->im_ioport.iop_papar &= ~PA_ENET_PDN; diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c index 932141144ce..802d4f1ca81 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -182,11 +182,6 @@ static int smc_init (void) #endif #endif /* CONFIG_FADS */ -#if defined(CONFIG_RPXLITE) - /* Enable Monitor Port Transceiver */ - *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ; -#endif /* CONFIG_RPXLITE */ - /* Set the physical address of the host memory buffers in * the buffer descriptors. */ diff --git a/board/RPXlite_dw/Makefile b/board/RPXlite_dw/Makefile deleted file mode 100644 index eff33cff956..00000000000 --- a/board/RPXlite_dw/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = RPXlite_dw.o flash.o diff --git a/board/RPXlite_dw/README b/board/RPXlite_dw/README deleted file mode 100644 index 9e2d0f42a0a..00000000000 --- a/board/RPXlite_dw/README +++ /dev/null @@ -1,161 +0,0 @@ - -After following the step of Yoo. Jonghoon and Wolfgang Denk, -I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW. - -There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW. - -Board(in U-Boot) version(in EmbeddedPlanet) CPU SDRAM FLASH -RPXlite RPXlite CW 850 16MB 4MB -RPXlite_DW RPXlite DW(EP 823 H1 DW) 823e 64MB 16MB - -This fireware is specially coded for EmbeddedPlanet Co. Software Development -Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel. - -It has the following three features: - -1. 64MHz/48MHz system frequence setting options. -The default setting is 48MHz.To get a 64MHz u-boot,just add -'64' in make command,like - -make distclean -make RPXlite_DW_64_config -make all - -2. CONFIG_ENV_IS_IN_FLASH/CONFIG_ENV_IS_IN_NVRAM - -The default environment parameter is stored in FLASH because it is a common choice for -environment parameter.So I make NVRAM as backup parameter storeage.The reason why I -didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter -home.Because of the possibility of using two firewares on this board,I didn't -'disturb' EEPROM.To get NVRAM support,you may use the following build command: - -make distclean -make RPXlite_DW_NVRAM_config -make all - -3. LCD panel support - -To support the Platform better,I added LCD panel(NL6448BC20-08) function. -For the convenience of debug, CONFIG_PERBOOT was supported. So you just -perss ENTER if you want to get a serial console in boot downcounting. -Then you can switch to LCD and serial console freely just typing -'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled. - -To get a LCD support u-boot,you can do the following: - -make distclean -make RPXlite_DW_LCD_config -make all - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The basic make commands could be: - -make RPXlite_DW_config -make RPXlite_DW_64_config -make RPXlite_DW_LCD_config -make RPXlite_DW_NVRAM_config - -BTW,you can combine the above features together and get a workable u-boot to meet your need. -For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type: - -make RPXlite_DW_NVRAM_64_LCD_config -make all - -So other combining make commands could be: - -make RPXlite_DW_NVRAM_64_config -make RPXlite_DW_NVRAM_LCD_config -make RPXlite_DW_64_LCD_config - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The boot process by "make RPXlite_DW_config" could be: - -U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) - -CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache -Board: RPXlite_DW -DRAM: 64 MB -FLASH: 16 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET -u-boot> - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -A word on the U-Boot environment variable setting and usage : - -In the beginning, you could just need very simple default environment variable setting, -like[include/configs/RPXlite.h] : - -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -This is enough for kernel NFS test. But as debug process goes on, you would expect -to save some time on environment variable setting and u-boot/kernel updating. -So the default environment variable setting would become more complicated. Just like -the one I did in include/configs/RPXlite_DW.h. - -Two u-boot commands, ku and uu, should be careful to use. They were designed to update -kernel and u-boot image file respectively. You must tftp your image to default address -'100000' and then use them correctly. Yeah, you can create your own command to do this -job. :-) The example u-boot image updating process could be : - -u-boot>t 100000 RPXlite_DW_LCD.bin -Using SCC ETHERNET device -TFTP from server 172.16.115.6; our IP address is 172.16.115.7 -Filename 'RPXlite_DW_LCD.bin'. -Load address: 0x100000 -Loading: ############################# -done -Bytes transferred = 144700 (2353c hex) -u-boot>run uu -Un-Protect Flash Sectors 0-4 in Bank # 1 -Erase Flash Sectors 0-4 in Bank # 1 -.... done -Copy to Flash... done -ff000000: 27051956 552d426f 6f742031 2e312e32 '..VU-Boot 1.1.2 -ff000010: 20284175 67203239 20323030 34202d20 (Aug 29 2004 - -ff000020: 31353a32 303a3238 29000000 00000000 15:20:28)....... -ff000030: 00000000 00000000 00000000 00000000 ................ -ff000040: 00000000 00000000 00000000 00000000 ................ -ff000050: 00000000 00000000 00000000 00000000 ................ -ff000060: 00000000 00000000 00000000 00000000 ................ -ff000070: 00000000 00000000 00000000 00000000 ................ -ff000080: 00000000 00000000 00000000 00000000 ................ -ff000090: 00000000 00000000 00000000 00000000 ................ -ff0000a0: 00000000 00000000 00000000 00000000 ................ -ff0000b0: 00000000 00000000 00000000 00000000 ................ -ff0000c0: 00000000 00000000 00000000 00000000 ................ -ff0000d0: 00000000 00000000 00000000 00000000 ................ -ff0000e0: 00000000 00000000 00000000 00000000 ................ -ff0000f0: 00000000 00000000 00000000 00000000 ................ -u-boot updating finished -u-boot> - -Also for environment updating, 'run eu' could let you erase OLD default environment variable -and then use the working u-boot environment setting. - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Finally, if you want to keep the serial port to possible debug on spot for deployment, you -just need to enable 'DEPLOYMENT' in RPXlite_DW.h as 'DEBUG' does. Only the special string -defined by CONFIG_AUTOBOOT_STOP_STR like 'st' can stop the autoboot. - -I'd like to extend my heartfelt gratitute to kind people for helping me work it out. -I would particually thank Wolfgang Denk for his nice help. - -Enjoy, - -Sam Song, samsongshu@yahoo.com.cn -Institute of Electrical Machinery and Controls -Shanghai University - -Oct. 11, 2004 diff --git a/board/RPXlite_dw/RPXlite_dw.c b/board/RPXlite_dw/RPXlite_dw.c deleted file mode 100644 index 29d52dec8c8..00000000000 --- a/board/RPXlite_dw/RPXlite_dw.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2004 - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Sam Song - * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW - * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz - * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75. - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ -static long int dram_size (long int, long int *, long int); -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, - 0x01FFCC20, 0x1FF74C20, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */ - _NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35, - _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, - 0x01FFFC24, 0x1FF74C25, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, - 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4, - /* INIT sequence RAM WORDS - * SDRAM Initialization (offset 0x36 in UPMA RAM) - * The above definition uses the remaining space - * to establish an initialization sequence, - * which is executed by a RUN command. - * The sequence is COMMAND INHIBIT(NOP),Precharge, - * Load Mode Register,NOP,Auto Refresh. - */ - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ -}; - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXlite_DW\n") ; - return (0) ; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size9; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR ; - - memctl->memc_mar = 0x00000088; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ - /*Disable Periodic timer A. */ - - udelay(200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002236; /* SDRAM bank 0 - refresh twice */ - - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - /*Enable Periodic timer A */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 9 column mode - */ - - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); - - /* - * Final mapping: - */ - - memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - - udelay (1000); - - return (size9); -} - -void rpxlite_init (void) -{ - /* Enable NVRAM */ - *((uchar *) BCSR0) |= BCSR0_ENNVRAM; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} diff --git a/board/RPXlite_dw/flash.c b/board/RPXlite_dw/flash.c deleted file mode 100644 index c8de5ef5eeb..00000000000 --- a/board/RPXlite_dw/flash.c +++ /dev/null @@ -1,474 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -/* Yes,Yoo.They do use other FLASH for the board. - * - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * U-Boot port on RPXlite DW version board - * - * By now,it uses 4 AM29DL323DB90VI devices(4x8bit). - * The total FLASH has 16MB(4x4MB). - * I just made some necessary changes on the basis of Wolfgang and Yoo's job. - * - * June 8, 2004 */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions vu_long : volatile unsigned long IN include/common.h - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -unsigned long flash_init (void) -{ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE - /* If Monitor is in the cope of FLASH,then - * protect this area by default in case for - * other occupation. [SAM] */ - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, - &flash_info[0]); -#endif - flash_info[0].size = size_b0; - return (size_b0); -} - -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000); - } - } else { - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - -} - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sector)\n"); - break; - /* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM] */ - default: printf ("Unknown Chip Type\n"); - break; - } - printf (" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count); - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0x00AA00AA ; - addr[0x555] = 0x00550055 ; - addr[0xAAA] = 0x00900090 ; - - value = addr[0] ; - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: /* AMD_MANUFACT =0x00010001 in flash.h */ - info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h */ - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - switch (value & 0x00FF00FF) { - case (AMD_ID_LV400T & 0x00FF00FF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - case (AMD_ID_LV400B & 0x00FF00FF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - case (AMD_ID_LV800T & 0x00FF00FF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - case (AMD_ID_LV800B & 0x00FF00FF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /* Size doubled by yooth */ - break; /* => 4 MB */ - case (AMD_ID_LV160T & 0x00FF00FF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - case (AMD_ID_LV160B & 0x00FF00FF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - case (AMD_ID_DL323B & 0x00FF00FF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* => 16 MB(4x4MB) */ - /* AMD_ID_DL323B= 0x22532253 FLASH_AMDL323B= 0x0013 - * AMD_ID_DL323B could be found in .[SAM] - * So we could get : flash_id = 0x00000013. - * The first four-bit represents VEDOR ID,leaving others for FLASH ID. */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1, - * it means bottom boot flash. GOOD IDEA! [SAM] - */ - - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - /* info->protect[i] = addr[4] & 1 ; */ - /* Mask it for disorder FLASH protection **[Sam]** */ - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank */ - } - return (info->size); -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds deleted file mode 100644 index 0eb2fba00c2..00000000000 --- a/board/RPXlite_dw/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug deleted file mode 100644 index 0ea27e87599..00000000000 --- a/board/RPXlite_dw/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/quantum/Makefile b/board/quantum/Makefile deleted file mode 100644 index 6918f63c3e9..00000000000 --- a/board/quantum/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = quantum.o fpga.o diff --git a/board/quantum/fpga.c b/board/quantum/fpga.c deleted file mode 100644 index 4bd391a5466..00000000000 --- a/board/quantum/fpga.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* The DEBUG define must be before common to enable debugging */ -#undef DEBUG -#include -#include -#include -#include "fpga.h" -/* ------------------------------------------------------------------------- */ - -#define MAX_ONES 226 - -/* MPC850 port D */ -#define PD(bit) (1 << (15 - (bit))) -# define FPGA_INIT PD(11) /* FPGA init pin (ppc input) */ -# define FPGA_PRG PD(12) /* FPGA program pin (ppc output) */ -# define FPGA_CLK PD(13) /* FPGA clk pin (ppc output) */ -# define FPGA_DATA PD(14) /* FPGA data pin (ppc output) */ -# define FPGA_DONE PD(15) /* FPGA done pin (ppc input) */ - - -/* DDR 0 - input, 1 - output */ -#define FPGA_INIT_PDDIR FPGA_PRG | FPGA_CLK | FPGA_DATA /* just set outputs */ - - -#define SET_FPGA(data) immr->im_ioport.iop_pddat = (data) -#define GET_FPGA immr->im_ioport.iop_pddat - -#define FPGA_WRITE_1 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG); /* set data to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - - -int fpga_boot (unsigned char *fpgadata, int size) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int i, index, len; - int count; - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - int j; - unsigned char data; -#else - unsigned char b; - int bit; -#endif - - debug ("fpga_boot: fpgadata = %p, size = %d\n", fpgadata, size); - - /* display infos on fpgaimage */ - printf ("FPGA:"); - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf (" %s", &(fpgadata[index + 1])); - index += len + 3; - } - printf ("\n"); - - - index = 0; - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* search for preamble 0xFFFFFFFF */ - while (1) { - if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) - && (fpgadata[index + 2] == 0xff) - && (fpgadata[index + 3] == 0xff)) - break; /* preamble found */ - else - index++; - } -#else - /* search for preamble 0xFF2X */ - for (index = 0; index < size - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x30)) - break; - } - index += 2; -#endif - - debug ("FPGA: configdata starts at position 0x%x\n", index); - debug ("FPGA: length of fpga-data %d\n", size - index); - - /* - * Setup port pins for fpga programming - */ - immr->im_ioport.iop_pddir = FPGA_INIT_PDDIR; - - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA (FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA init line low */ - count = 0; - while (GET_FPGA & FPGA_INIT) { - udelay (1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) { - debug ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } - } - - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* deassert PROGRAM* */ - SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA end of init period . */ - count = 0; - while (!(GET_FPGA & FPGA_INIT)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - debug ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } - } - - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - debug ("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* - * Load uncompressed image into fpga - */ - for (i = index; i < size; i++) { -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if ((i % 1024) == 0) - printf ("%6d out of %6d\r", i, size); /* let them know we are alive */ -#endif - - data = fpgadata[i]; - for (j = 0; j < 8; j++) { - if ((data & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - data <<= 1; - } - } - /* add some 0xff to the end of the file */ - for (i = 0; i < 8; i++) { - data = 0xff; - for (j = 0; j < 8; j++) { - if ((data & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - data <<= 1; - } - } -#else - /* send 0xff 0x20 */ - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - - /* - ** Bit_DeCompression - ** Code 1 .. maxOnes : n '1's followed by '0' - ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' - ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' - ** 255 : '1' - */ - - for (i = index; i < size; i++) { - b = fpgadata[i]; - if ((b >= 1) && (b <= MAX_ONES)) { - for (bit = 0; bit < b; bit++) { - FPGA_WRITE_1; - } - FPGA_WRITE_0; - } else if (b == (MAX_ONES + 1)) { - for (bit = 1; bit < b; bit++) { - FPGA_WRITE_1; - } - } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { - for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { - FPGA_WRITE_0; - } - FPGA_WRITE_1; - } else if (b == 255) { - FPGA_WRITE_1; - } - } -#endif - debug ("\n\n"); - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Check if fpga's DONE signal - correctly booted ? - */ - - /* Wait for FPGA end of programming period . */ - count = 0; - while (!(GET_FPGA & FPGA_DONE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - debug ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } - } - - debug ("FPGA: Booting successful!\n"); - return 0; -} diff --git a/board/quantum/fpga.h b/board/quantum/fpga.h deleted file mode 100644 index a9f4086297f..00000000000 --- a/board/quantum/fpga.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Virtex2 FPGA configuration support for the QUANTUM computer - */ -int fpga_boot(unsigned char *fpgadata, int size); - -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c deleted file mode 100644 index 17e3fc26790..00000000000 --- a/board/quantum/quantum.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include -#include "fpga.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -unsigned long flash_init (void); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = { - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, - 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, - 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - * (Initialization code at 0x36) - */ - 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, - 0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board QUANTUM, Serial No: "); - - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc (buf[i]); - } - putc ('\n'); - return (0); /* success */ -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000088; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size, - * 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - /* - * Final mapping: - */ - memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - udelay (1000); - - return (size9); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile ulong *addr; - ulong cnt, val, size; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - memctl->memc_mamr = mamr_value; - - for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = (volatile ulong *)(base + cnt); /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = (volatile ulong *)base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - /* Restore the original data before leaving the function. - */ - *addr = save[i]; - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *) base + cnt; - *addr = save[--i]; - } - return (0); - } - - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *)(base + cnt); /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - size = cnt * sizeof (long); - /* Restore the original data before returning - */ - for (cnt <<= 1; cnt <= maxsize / sizeof (long); - cnt <<= 1) { - addr = (volatile ulong *) base + cnt; - *addr = save[--i]; - } - return (size); - } - } - return (maxsize); -} - -/* - * Miscellaneous intialization - */ -int misc_init_r (void) -{ - char *fpga_data_str = getenv ("fpgadata"); - char *fpga_size_str = getenv ("fpgasize"); - void *fpga_data; - int fpga_size; - int status; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - int flash_size; - - /* Remap FLASH according to real size */ - flash_size = flash_init (); - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - if (fpga_data_str && fpga_size_str) { - fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16); - fpga_size = simple_strtoul (fpga_size_str, NULL, 10); - - status = fpga_boot (fpga_data, fpga_size); - if (status != 0) { - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - } - } - return 0; -} diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds deleted file mode 100644 index 0eb2fba00c2..00000000000 --- a/board/quantum/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug deleted file mode 100644 index b2c562c33d9..00000000000 --- a/board/quantum/u-boot.lds.debug +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index 2a3c2ff7f8f..e5665ddd026 100644 --- a/boards.cfg +++ b/boards.cfg @@ -977,7 +977,6 @@ Active powerpc mpc86xx - freescale mpc8610hpcd Active powerpc mpc86xx - xes - xpedite517x - - Active powerpc mpc8xx - - - hermes - Wolfgang Denk Active powerpc mpc8xx - - - lwmon - Wolfgang Denk -Active powerpc mpc8xx - - - quantum - - Active powerpc mpc8xx - - - RRvision - Wolfgang Denk Active powerpc mpc8xx - - - spc1920 - - Active powerpc mpc8xx - - - v37 - - @@ -1010,14 +1009,6 @@ Active powerpc mpc8xx - - netvia Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk Active powerpc mpc8xx - - rbc823 RBC823 - - -Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW - - -Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz - -Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 - -Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 - -Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM RPXlite_DW:ENV_IS_IN_NVRAM - -Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64 RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM - -Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM - -Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM - Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 6d340d5d8a9..017c25ba9e8 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,8 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +quantum powerpc mpc8xx - - +RPXlite_dw powerpc mpc8xx - - qs850 powerpc mpc8xx - - qs860t powerpc mpc8xx - - simpc8313 powerpc mpc83xx 7445207f 2014-06-05 Ron Madrid diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index ae3cafbea4e..91821f4c770 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -7,7 +7,6 @@ obj-$(CONFIG_I82365) += i82365.o obj-$(CONFIG_8xx) += mpc8xx_pcmcia.o -obj-y += rpx_pcmcia.o obj-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o obj-y += tqm8xx_pcmcia.o obj-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c index 663827780e9..af774260ee3 100644 --- a/drivers/pcmcia/mpc8xx_pcmcia.c +++ b/drivers/pcmcia/mpc8xx_pcmcia.c @@ -211,16 +211,6 @@ static u_int m8xx_get_graycode(u_int size) #if 0 -#if defined(CONFIG_RPXLITE) - -/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. - * SYPCR is write once only, therefore must the slowest memory be faster - * than the bus monitor or we will get a machine check due to the bus timeout. - */ -#undef PCMCIA_BMT_LIMIT -#define PCMCIA_BMT_LIMIT (6*8) -#endif - static u_int m8xx_get_speed(u_int ns, u_int is_io) { u_int reg, clocks, psst, psl, psht; diff --git a/drivers/pcmcia/rpx_pcmcia.c b/drivers/pcmcia/rpx_pcmcia.c deleted file mode 100644 index 5b24f0bfbe4..00000000000 --- a/drivers/pcmcia/rpx_pcmcia.c +++ /dev/null @@ -1,73 +0,0 @@ -/* -------------------------------------------------------------------- */ -/* RPX Boards from Embedded Planet */ -/* -------------------------------------------------------------------- */ -#include -#ifdef CONFIG_8xx -#include -#endif -#include - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_PCMCIA) \ - && defined(CONFIG_RPXLITE) - -#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - u_long reg = 0; - - switch(vcc) { - case 0: break; - case 33: reg |= BCSR1_PCVCTL4; break; - case 50: reg |= BCSR1_PCVCTL5; break; - default: return 1; - } - - switch(vpp) { - case 0: break; - case 33: - case 50: - if(vcc == vpp) - reg |= BCSR1_PCVCTL6; - else - return 1; - break; - case 120: - reg |= BCSR1_PCVCTL7; - default: return 1; - } - - /* first, turn off all power */ - *((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 - | BCSR1_PCVCTL6 | BCSR1_PCVCTL7); - - /* enable new powersettings */ - *((uint *)RPX_CSR_ADDR) |= reg; - - return 0; -} - -int pcmcia_hardware_enable (int slot) -{ - return 0; /* No hardware to enable */ -} - -#if defined(CONFIG_CMD_PCMCIA) -static int pcmcia_hardware_disable(int slot) -{ - return 0; /* No hardware to disable */ -} -#endif - - -#endif /* CONFIG_PCMCIA && CONFIG_RPXLITE */ diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c index fceed871a71..b6062f9128e 100644 --- a/drivers/video/mpc8xx_lcd.c +++ b/drivers/video/mpc8xx_lcd.c @@ -268,11 +268,6 @@ void lcd_ctrl_init (void *lcdbase) * the controller. */ -#ifdef CONFIG_RPXLITE - /* This is special for RPXlite_DW Software Development Platform **[Sam]** */ - panel_info.vl_dp = CONFIG_SYS_LOW; -#endif - lccrtmp = LCDBIT (LCCR_BNUM_BIT, (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128)); diff --git a/include/common.h b/include/common.h index 2e5a6d3d2f1..136a4451397 100644 --- a/include/common.h +++ b/include/common.h @@ -499,8 +499,6 @@ extern ssize_t spi_read (uchar *, int, uchar *, int); extern ssize_t spi_write (uchar *, int, uchar *, int); #endif -void rpxlite_init (void); - #ifdef CONFIG_HERMES /* $(BOARD)/hermes.c */ void hermes_start_lxt980 (int speed); diff --git a/include/commproc.h b/include/commproc.h index 5992f11de34..ef59df9388a 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -900,32 +900,6 @@ typedef struct scc_enet { #endif /* CONFIG_NETVIA */ -/*** RPXLITE ********************************************************/ - -#ifdef CONFIG_RPXLITE -/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of - * this may be unique to the RPX-Lite configuration. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#if defined(CONFIG_RMU) -#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */ -#else -#define PB_ENET_TENA ((uint)0x00002000) -#endif -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003d00) -#endif /* CONFIG_RPXLITE */ - /*** SM850 *********************************************************/ /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h deleted file mode 100644 index 50c82c68ebd..00000000000 --- a/include/configs/RPXlite_DW.h +++ /dev/null @@ -1,462 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-BOOT port on RPXlite board - */ - -/* - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * U-BOOT port on RPXlite DW version board--RPXlite_DW - * June 8 ,2004 - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* #define DEBUG 1 */ -/* #define DEPLOYMENT 1 */ - -#undef CONFIG_MPC860 -#define CONFIG_MPC823 1 /* This is a MPC823e CPU. */ -#define CONFIG_RPXLITE 1 /* RPXlite DW version board */ - -#define CONFIG_SYS_TEXT_BASE 0xff000000 - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_MPC8XX_LCD -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */ - -#ifdef DEBUG -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */ - -#ifdef DEPLOYMENT -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "autoboot in %d seconds (stop with 'st')...\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR "st" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1 -#define CONFIG_BOOT_RETRY_MIN 1 -#endif /* DEPLOYMENT */ -#endif /* DEBUG */ - -/* pre-boot commands */ -#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "gatewayip=172.16.115.254\0" \ - "netmask=255.255.255.0\0" \ - "kernel_addr=ff040000\0" \ - "ramdisk_addr=ff200000\0" \ - "ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} " \ - "${filesize};md ${kernel_addr};" \ - "echo kernel updating finished\0" \ - "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \ - "${filesize};md ff000000;" \ - "echo u-boot updating finished\0" \ - "eu=protect off 1:6;era 1:6;reset\0" \ - "lcd=setenv stdout lcd;setenv stdin lcd\0" \ - "ser=setenv stdout serial;setenv stdin serial\0" \ - "verify=no" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you - don't want the advanced function */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_DHCP - -#ifdef CONFIG_SPLASH_SCREEN -#define CONFIG_CMD_BMP -#endif - - -/* test-only */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ - -#define CONFIG_NETCONSOLE - -#endif /* 1 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "u-boot>" /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFA200000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 - -#if defined(DEBUG) || defined(CONFIG_CMD_IDE) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif - -#define CONFIG_SYS_MONITOR_BASE 0xFF000000 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#ifdef CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_ADDR 0xFA000100 -#define CONFIG_ENV_SIZE 0x1000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ -#endif /* CONFIG_ENV_IS_IN_NVRAM */ - -#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res))) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 32-bit 12-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif /* We can get SYPCR: 0xFFFF0689. */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 32-bit 12-30 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */ - -/*--------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 16-bit 12-16 - *--------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) -/* TBSCR: 0x00C3 [SAM] */ - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18 - *----------------------------------------------------------------------- - * [RTC enabled but not stopped on FRZ] - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */ - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 16-bit 12-23 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - * [Periodic timer enabled,Periodic timer interrupt disable. ] - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -/* up to 64 MHz we use a 1:2 clock */ -#if defined(RPXlite_64MHz) -#define CONFIG_SYS_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */ -#else -#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) -#endif - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 5-3 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */ -#if defined(RPXlite_64MHz) -#define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */ -#else -#define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ -#endif - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ -#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFC000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 -#define CONFIG_SYS_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK)) -#define CONFIG_SYS_OR1_PRELIM ( CONFIG_SYS_OR_AM_SDRAM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXlite mem setting */ -#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */ -#define CONFIG_SYS_OR3_PRELIM 0xFF7F8900 -#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CONFIG_SYS_OR4_PRELIM 0xFFFE0040 - -/* - * Memory Periodic Timer Prescaler - */ -/* periodic timer for refresh */ -#if defined(RPXlite_64MHz) -#define CONFIG_SYS_MAMR_PTA 32 -#else -#define CONFIG_SYS_MAMR_PTA 20 -#endif - -/* - * Refresh clock Prescalar - */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2 - -/* - * MAMR settings for SDRAM - */ - -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10) -/* CONFIG_SYS_MAMR_9COL:0x20904000 @ 64MHz */ - -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* Configuration variable added by yooth. */ -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* - * BCSRx - * - * Board Status and Control Registers - * - */ -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR1_SMC1CTS 0x40 /* Added by SAM. */ -#define BCSR1_SMC1TRS 0x80 /* Added by SAM. */ - -#define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */ -#define BCSR2_ENBRG1 0x04 /* Added by SAM. */ - -#define BCSR2_ENPA5HDR 0x08 /* USB Control */ -#define BCSR2_ENUSBCLK 0x10 -#define BCSR2_USBPWREN 0x20 -#define BCSR2_USBSPD 0x40 -#define BCSR2_USBSUSP 0x80 - -#define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */ -#define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */ -#define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */ - -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - -/* - * Environment setting - */ -#define CONFIG_ETHADDR 00:10:EC:00:37:5B -#define CONFIG_IPADDR 172.16.115.7 -#define CONFIG_SERVERIP 172.16.115.6 -#define CONFIG_ROOTPATH "/workspace/myfilesystem/target/" -#define CONFIG_BOOTFILE "uImage.rpxusb" -#define CONFIG_HOSTNAME LITE_H1_DW - -#endif /* __CONFIG_H */ diff --git a/include/configs/quantum.h b/include/configs/quantum.h deleted file mode 100644 index f3540c1421c..00000000000 --- a/include/configs/quantum.h +++ /dev/null @@ -1,430 +0,0 @@ -/* - * (C) Copyright 2003-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - * changes for 16M board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#undef CONFIG_MPC860 -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */ -#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -/* default developmenmt environment */ - -#define CONFIG_ETHADDR 00:0B:17:00:00:00 - -#define CONFIG_IPADDR 10.10.69.10 -#define CONFIG_SERVERIP 10.10.69.49 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME QUANTUM -#define CONFIG_ROOTPATH "/opt/eldk/pcc_8xx" - -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#define CONFIG_BOOTCOMMAND "bootm ff000000" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=12345\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" - -/* - * Select the more full-featured memory test (Barr embedded systems) - */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - - -/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/ -#define CONFIG_RTC_M48T35A 1 - -#if 0 -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ -#else -#undef CONFIG_WATCHDOG -#endif - -/* NVRAM and RTC */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000 -#define CONFIG_SYS_NVRAM_SIZE 2048 - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT \ - "\nEnter password - autoboot in %d sec...\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "system" -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFA200000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 - -#if 1 - #define CONFIG_FLASH_CFI_DRIVER -#else - #undef CONFIG_FLASH_CFI_DRIVER -#endif - - -#ifdef CONFIG_FLASH_CFI_DRIVER - #define CONFIG_SYS_FLASH_CFI 1 - #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#endif - -/*%%% #define CONFIG_SYS_FLASH_BASE 0xFFF00000 */ -#if defined(DEBUG) || defined(CONFIG_CMD_IDE) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 -/*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector absolute address 0xfff40000*/ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* FPGA */ -#define CONFIG_MISC_INIT_R -#define CONFIG_SYS_FPGA_SPARTAN2 -#define CONFIG_SYS_FPGA_PROG_FEEDBACK - - -/*----------------------------------------------------------------------- - * Reset address - */ -#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res))) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CONFIG_SYS_DER 0x2002000F*/ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 - -#define CONFIG_SYS_OR1_PRELIM (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */ -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* FPGA */ -#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910 - -#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 20 - -/* - * Refresh clock Prescalar - */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2 - -/* - * MAMR settings for SDRAM - */ - -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_ENPA5HDR 0x08 /* USB Control */ -#define BCSR2_ENUSBCLK 0x10 -#define BCSR2_USBPWREN 0x20 -#define BCSR2_USBSPD 0x40 -#define BCSR2_USBSUSP 0x80 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - -#endif /* __CONFIG_H */ diff --git a/include/pcmcia.h b/include/pcmcia.h index 952a67c17c2..b0f6b924043 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -21,10 +21,7 @@ #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) - /* The RPX series use SLOT_B */ -#if defined(CONFIG_RPXLITE) -# define CONFIG_PCMCIA_SLOT_B -#elif defined(CONFIG_FADS) /* The FADS series are a mess */ +#if defined(CONFIG_FADS) /* The FADS series are a mess */ # if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821) # define CONFIG_PCMCIA_SLOT_A # else diff --git a/post/cpu/mpc8xx/ether.c b/post/cpu/mpc8xx/ether.c index d12250018ae..7dce6a0d24c 100644 --- a/post/cpu/mpc8xx/ether.c +++ b/post/cpu/mpc8xx/ether.c @@ -365,10 +365,6 @@ static void scc_init (int scc_index) immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC | SCC_PSMR_NIB22 | SCC_PSMR_LPB; -#ifdef CONFIG_RPXLITE - *((uchar *) BCSR0) |= BCSR0_ETHEN; -#endif - /* * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive */ diff --git a/post/cpu/mpc8xx/uart.c b/post/cpu/mpc8xx/uart.c index 5214c71b085..b3cb1923db7 100644 --- a/post/cpu/mpc8xx/uart.c +++ b/post/cpu/mpc8xx/uart.c @@ -106,11 +106,6 @@ static void smc_init (int smc_index) ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2); #endif -#if defined(CONFIG_RPXLITE) - /* Enable Monitor Port Transceiver */ - *((uchar *) BCSR0) |= BCSR0_ENMONXCVR; -#endif - /* Set the physical address of the host memory buffers in * the buffer descriptors. */ -- cgit v1.3.1 From c750b9c01223034f5ad49da3f0fe834f1cb0a93f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 20 Jun 2014 13:54:53 +0900 Subject: mpc8xx: remove rbc823 board support This board is old enough and has no maintainer. Signed-off-by: Masahiro Yamada --- board/rbc823/Makefile | 8 - board/rbc823/flash.c | 445 --------------------------------------------- board/rbc823/kbd.c | 253 -------------------------- board/rbc823/rbc823.c | 256 -------------------------- board/rbc823/u-boot.lds | 92 ---------- boards.cfg | 1 - doc/README.scrapyard | 1 + drivers/video/mpc8xx_lcd.c | 67 +------ include/commproc.h | 2 +- include/configs/RBC823.h | 407 ----------------------------------------- include/lcd.h | 4 - include/status_led.h | 19 -- 12 files changed, 3 insertions(+), 1552 deletions(-) delete mode 100644 board/rbc823/Makefile delete mode 100644 board/rbc823/flash.c delete mode 100644 board/rbc823/kbd.c delete mode 100644 board/rbc823/rbc823.c delete mode 100644 board/rbc823/u-boot.lds delete mode 100644 include/configs/RBC823.h (limited to 'drivers') diff --git a/board/rbc823/Makefile b/board/rbc823/Makefile deleted file mode 100644 index 060a144a92e..00000000000 --- a/board/rbc823/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = rbc823.o flash.o kbd.o diff --git a/board/rbc823/flash.c b/board/rbc823/flash.c deleted file mode 100644 index 8a2265263c8..00000000000 --- a/board/rbc823/flash.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/* - * Functions - */ -static ulong flash_get_size(vu_long *addr, flash_info_t *info); -static int write_word(flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets(ulong base, flash_info_t *info); - -unsigned long flash_init(void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Detect size */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, - &flash_info[0]); - - /* Setup offsets */ - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return size_b0; -} - -/*----------------------------------------------------------------------- - * Fix this to support variable sector sizes -*/ -static void flash_get_offsets(ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - /* set sector offsets for bottom boot block type */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_BM: - printf("BRIGHT MICRO "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - if (info->size >> 20) { - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - } else { - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, - info->sector_count); - } - - puts(" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - puts("\n "); - - printf(" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - putc('\n'); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long *addr, flash_info_t *info) -{ - short i; - volatile unsigned char *caddr; - char value; - - caddr = (volatile unsigned char *)addr ; - - /* Write auto select command: read Manufacturer ID */ - - debug("Base address is: %8p\n", caddr); - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - value = caddr[0]; - - debug("Manufact ID: %02x\n", value); - - switch (value) { - case 0x01: /*AMD_MANUFACT*/ - info->flash_id = FLASH_MAN_AMD; - break; - - case 0x04: /*FUJ_MANUFACT*/ - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = caddr[1]; /* device ID */ - - debug("Device ID: %02x\n", value); - - switch (value) { - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, &flash_info[0]); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* - * read sector protection at sector address, - * (A7 .. A0) = 0x02 - * D0 = 1 if protected - */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - *caddr = 0xF0; /* reset bank */ - } - - return info->size; -} - - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile unsigned char *addr = - (volatile unsigned char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile unsigned char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - - while ((addr[0] & 0xFF) != 0xFF) { - now = get_timer(start); - if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - l = addr - wp; - - if (l != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return 0; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - return write_word(info, wp, data); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - volatile unsigned char *cdest, *cdata; - volatile unsigned char *addr = - (volatile unsigned char *)(info->start[0]); - ulong start; - int flag, count = 4 ; - - cdest = (volatile unsigned char *)dest ; - cdata = (volatile unsigned char *)&data ; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest)&data) != data) - return 2; - - while (count--) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *cdest = *cdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*cdest ^ *cdata) & 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } - - cdata++ ; - cdest++ ; - } - return 0; -} diff --git a/board/rbc823/kbd.c b/board/rbc823/kbd.c deleted file mode 100644 index b35509ab399..00000000000 --- a/board/rbc823/kbd.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Modified by Udi Finkelstein - * - * This file includes communication routines for SMC1 that can run even if - * SMC2 have already been initialized. - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define SMC_INDEX 0 -#define PROFF_SMC PROFF_SMC1 -#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 - -#define RBC823_KBD_BAUDRATE 38400 -#define CPM_KEYBOARD_BASE 0x1000 -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -void smc1_setbrg (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG2 to SMC1, BRG1 to SMC2 - */ - - cp->cp_simode = 0x00001000; - - cp->cp_brgc2 = - (((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN; -} - -int smc1_init (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); - up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* Enable SDMA. - */ - im->im_siu_conf.sc_sdcr = 1; - - /* clear error conditions */ -#ifdef CONFIG_SYS_SDSR - im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; -#else - im->im_sdma.sdma_sdsr = 0x83; -#endif - - /* clear SDMA interrupt mask */ -#ifdef CONFIG_SYS_SDMR - im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; -#else - im->im_sdma.sdma_sdmr = 0x00; -#endif - - /* Use Port B for SMC1 instead of other functions. - */ - cp->cp_pbpar |= 0x000000c0; - cp->cp_pbdir &= ~0x000000c0; - cp->cp_pbodr &= ~0x000000c0; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - -#ifdef CONFIG_SYS_ALLOC_DPRAM - dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; -#else - dpaddr = CPM_KEYBOARD_BASE ; -#endif - - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - * damm: allocating space after the two buffers for rx/tx data - */ - - rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* Set up the baud rate generator. - */ - smc1_setbrg (); - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - return (0); -} - -void smc1_putc(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *)tbdf->cbd_bufaddr; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__("eieio"); - - while (tbdf->cbd_sc & BD_SC_READY) { - WATCHDOG_RESET (); - __asm__("eieio"); - } -} - -int smc1_getc(void) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - - while (rbdf->cbd_sc & BD_SC_EMPTY) - WATCHDOG_RESET (); - - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -int smc1_tstc(void) -{ - volatile cbd_t *rbdf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); -} - -/* search for keyboard and register it if found */ -int drv_keyboard_init(void) -{ - int error = 0; - struct stdio_dev kbd_dev; - - if (0) { - /* register the keyboard */ - memset (&kbd_dev, 0, sizeof(struct stdio_dev)); - strcpy(kbd_dev.name, "kbd"); - kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbd_dev.putc = NULL; - kbd_dev.puts = NULL; - kbd_dev.getc = smc1_getc; - kbd_dev.tstc = smc1_tstc; - error = stdio_register (&kbd_dev); - } else { - lcd_is_enabled = 0; - lcd_disable(); - } - return error; -} diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c deleted file mode 100644 index 5881111c70e..00000000000 --- a/board/rbc823/rbc823.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include "mpc8xx.h" -#include - -extern int kbd_init(void); -extern int drv_kbd_init(void); - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x1FF7FC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -const uint static_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04, - 0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04, - 0xFFFFFC04, 0xFFFFFC05, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04, - 0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * Test TQ ID string (TQM8xx...) - * If present, check for "L" type (no second DRAM bank), - * otherwise "L" type is assumed as default. - * - * Return 1 for "L" type, 0 else. - */ - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - if (i < 0 || strncmp(buf, "TQM8", 4)) { - printf ("### No HW ID - assuming RBC823\n"); - return (0); - } - - puts(buf); - putc('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * 1 Bank of 64Mbit x 2 devices - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; - memctl->memc_mar = 0x00000088; - - /* - * Map controller SDRAM bank 0 - */ - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - udelay (200); - - /* - * Perform SDRAM initializsation sequence - */ - memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X; - udelay (200); - memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */ - udelay (1); - memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X; - udelay (200); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; /* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */ - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM, - SDRAM_MAX_SIZE); - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - udelay (10000); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -#ifdef CONFIG_CMD_DOC -void doc_init (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig (UPMB, (uint *) static_table, - sizeof (static_table) / sizeof (uint)); - memctl->memc_mbmr = MAMR_DSA_1_CYCL; - - doc_probe (FLASH_BASE1_PRELIM); -} -#endif diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds deleted file mode 100644 index 7676cf43b17..00000000000 --- a/board/rbc823/u-boot.lds +++ /dev/null @@ -1,92 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - lib/built-in.o (.text*) - net/built-in.o (.text*) - arch/powerpc/cpu/mpc8xx/built-in.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index e5665ddd026..cedf69bef58 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1008,7 +1008,6 @@ Active powerpc mpc8xx - - netta2 Active powerpc mpc8xx - - netvia NETVIA NETVIA:NETVIA_VERSION=1 Pantelis Antoniou Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk -Active powerpc mpc8xx - - rbc823 RBC823 - - Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 017c25ba9e8..fe666a572b1 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +rbc823 powerpc mpc8xx - - quantum powerpc mpc8xx - - RPXlite_dw powerpc mpc8xx - - qs850 powerpc mpc8xx - - diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c index b6062f9128e..eafeff73b8b 100644 --- a/drivers/video/mpc8xx_lcd.c +++ b/drivers/video/mpc8xx_lcd.c @@ -292,9 +292,6 @@ void lcd_ctrl_init (void *lcdbase) /* Initialize LCD controller bus priorities. */ -#ifdef CONFIG_RBC823 - immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */ -#else immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */ /* set SHFT/CLOCK division factor 4 @@ -308,21 +305,7 @@ void lcd_ctrl_init (void *lcdbase) immr->im_clkrst.car_sccr &= ~0x1F; immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */ -#endif /* CONFIG_RBC823 */ - -#if defined(CONFIG_RBC823) - /* Enable LCD on port D. - */ - immr->im_ioport.iop_pddat &= 0x0300; - immr->im_ioport.iop_pdpar |= 0x1CFF; - immr->im_ioport.iop_pddir |= 0x1CFF; - - /* Configure LCD_ON, VEE_ON, CCFL_ON on port B. - */ - immr->im_cpm.cp_pbdat &= ~0x00005001; - immr->im_cpm.cp_pbpar &= ~0x00005001; - immr->im_cpm.cp_pbdir |= 0x00005001; -#elif !defined(CONFIG_EDT32F10) +#if !defined(CONFIG_EDT32F10) /* Enable LCD on port D. */ immr->im_ioport.iop_pdpar |= 0x1FFF; @@ -427,18 +410,13 @@ void lcd_enable (void) volatile lcd823_t *lcdp = &immr->im_lcd; /* Enable the LCD panel */ -#ifndef CONFIG_RBC823 immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */ -#endif lcdp->lcd_lccr |= LCCR_PON; #ifdef CONFIG_V37 /* Turn on display backlight */ immr->im_cpm.cp_pbpar |= 0x00008000; immr->im_cpm.cp_pbdir |= 0x00008000; -#elif defined(CONFIG_RBC823) - /* Turn on display backlight */ - immr->im_cpm.cp_pbdat |= 0x00004000; #endif #if defined(CONFIG_LWMON) @@ -476,14 +454,6 @@ void lcd_enable (void) r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF); } #endif /* CONFIG_R360MPI */ -#ifdef CONFIG_RBC823 - udelay(200000); /* wait 200ms */ - /* Turn VEE_ON first */ - immr->im_cpm.cp_pbdat |= 0x00000001; - udelay(200000); /* wait 200ms */ - /* Now turn on LCD_ON */ - immr->im_cpm.cp_pbdat |= 0x00001000; -#endif #ifdef CONFIG_RRVISION debug ("PC4->Output(1): enable LVDS\n"); debug ("PC5->Output(0): disable PAL clock\n"); @@ -503,41 +473,6 @@ void lcd_enable (void) #endif } -/*----------------------------------------------------------------------*/ - -#if defined (CONFIG_RBC823) -void lcd_disable (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile lcd823_t *lcdp = &immr->im_lcd; - -#if defined(CONFIG_LWMON) - { uchar c = pic_read (0x60); - c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */ - pic_write (0x60, c); - } -#elif defined(CONFIG_R360MPI) - { - extern void r360_i2c_lcd_write (uchar data0, uchar data1); - - r360_i2c_lcd_write(0x10, 0x00); - r360_i2c_lcd_write(0x20, 0x00); - r360_i2c_lcd_write(0x30, 0x00); - r360_i2c_lcd_write(0x40, 0x00); - } -#endif /* CONFIG_LWMON */ - /* Disable the LCD panel */ - lcdp->lcd_lccr &= ~LCCR_PON; -#ifdef CONFIG_RBC823 - /* Turn off display backlight, VEE and LCD_ON */ - immr->im_cpm.cp_pbdat &= ~0x00005001; -#else - immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */ -#endif /* CONFIG_RBC823 */ -} -#endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */ - - /************************************************************************/ #endif /* CONFIG_LCD */ diff --git a/include/commproc.h b/include/commproc.h index ef59df9388a..d53cbdd6596 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -968,7 +968,7 @@ typedef struct scc_enet { /*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/ #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ - defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \ + defined(CONFIG_R360MPI) || \ defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \ defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \ diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h deleted file mode 100644 index e7e061cb3e3..00000000000 --- a/include/configs/RBC823.h +++ /dev/null @@ -1,407 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Udi Finkelstein udif@udif.com - * For the RBC823 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_RBC823 1 /* ...on a RBC823 module */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#if 0 -#define DEBUG 1 -#define CONFIG_LAST_STAGE_INIT -#endif -#define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */ -#define CONFIG_LCD 1 /* use LCD controller ... */ -#define CONFIG_MPC8XX_LCD -#define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */ - -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_SMC1 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_8xx_GCLK_FREQ 48000000L - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#undef CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */ - -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 40000 -#define CONFIG_SYS_I2C_SLAVE 0xfe -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_WRITE_DELAY_MS 10 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_BMP -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_KGDB -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM - -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_XIMG - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x0100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -/* -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -*/ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -/* - * for 48 MHz, we use a 4 MHz clock * 12 - */ -#define CONFIG_SYS_PLPRCR \ - ( (12-1)< Date: Fri, 20 Jun 2014 13:54:56 +0900 Subject: mpc8xx: remove v37 board support This board is old enough and has no maintainer. Signed-off-by: Masahiro Yamada --- board/v37/Makefile | 8 - board/v37/flash.c | 543 --------------------------------------------- board/v37/u-boot.lds | 82 ------- board/v37/v37.c | 202 ----------------- boards.cfg | 1 - doc/README.scrapyard | 1 + drivers/video/mpc8xx_lcd.c | 8 +- include/commproc.h | 23 -- include/configs/v37.h | 375 ------------------------------- 9 files changed, 2 insertions(+), 1241 deletions(-) delete mode 100644 board/v37/Makefile delete mode 100644 board/v37/flash.c delete mode 100644 board/v37/u-boot.lds delete mode 100644 board/v37/v37.c delete mode 100644 include/configs/v37.h (limited to 'drivers') diff --git a/board/v37/Makefile b/board/v37/Makefile deleted file mode 100644 index 2df4b82fb85..00000000000 --- a/board/v37/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = v37.o flash.o diff --git a/board/v37/flash.c b/board/v37/flash.c deleted file mode 100644 index 5b34af249be..00000000000 --- a/board/v37/flash.c +++ /dev/null @@ -1,543 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips); -static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id); -static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - short manu, dev_id; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b0); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE0 - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_get_id_long((void*)CONFIG_SYS_FLASH_BASE1,&manu,&dev_id); - - size_b1 = 2 * flash_get_size(manu, dev_id, &flash_info[1]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE1, &flash_info[1],1); - - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b1); - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0+size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips) -{ - int i, addr_shift; - vu_short *addr = (vu_short*)base; - - addr[0x555] = 0x00AA ; - addr[0xAAA] = 0x0055 ; - addr[0x555] = 0x0090 ; - - addr_shift = (two_chips ? 2 : 1 ); - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + (0x00000000<start[1] = base + (0x00002000<start[2] = base + (0x00003000<start[3] = base + (0x00004000<sector_count; i++) { - info->start[i] = base + ((i-3) * (0x00008000<sector_count - 1; - info->start[i--] = base + info->size - (0x00002000<start[i--] = base + info->size - (0x00003000<start[i--] = base + info->size - (0x00004000<= 0; i--) { - info->start[i] = base + i * (0x00008000<sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (vu_short *)(info->start[i]); - info->protect[i] = addr[1<start[0]; - *addr = 0xF0F0; /* reset bank */ -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_TOSH: printf ("TOSHIBA "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id) -{ - vu_short *addr = (vu_short*)ptr; - - addr[0x555] = 0x00AA ; - addr[0xAAA] = 0x0055 ; - addr[0x555] = 0x0090 ; - - *ptr_manuf = addr[0]; - *ptr_dev_id = addr[1]; - - addr[0] = 0xf0f0; /* return to normal */ -} - -static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id) -{ - vu_short *addr = (vu_short*)ptr; - vu_short *addr1, *addr2, *addr3; - - addr1 = (vu_short*) ( ((int)ptr) + (0x5555<<2) ); - addr2 = (vu_short*) ( ((int)ptr) + (0x2AAA<<2) ); - addr3 = (vu_short*) ( ((int)ptr) + (0x5555<<2) ); - - *addr1 = 0xAAAA; - *addr2 = 0x5555; - *addr3 = 0x9090; - - *ptr_manuf = addr[0]; - *ptr_dev_id = addr[2]; - - addr[0] = 0xf0f0; /* return to normal */ -} - -static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info) -{ - switch (manu) { - case ((short)AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - case ((short)FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - case ((short)TOSH_MANUFACT): - info->flash_id = FLASH_MAN_TOSH; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - - switch (dev_id) { - case ((short)TOSH_ID_FVT160): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 1 MB */ - - case ((short)TOSH_ID_FVB160): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 1 MB */ - - case ((short)AMD_ID_LV400T): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case ((short)AMD_ID_LV400B): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case ((short)AMD_ID_LV800T): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case ((short)AMD_ID_LV800B): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /*%%% Size doubled by yooth */ - break; /* => 4 MB */ - - case ((short)AMD_ID_LV160T): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 4 MB */ - - case ((short)AMD_ID_LV160B): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 4 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x555] = (vu_short)0xAAAAAAAA; - addr[0xAAA] = (vu_short)0x55555555; - addr[0x555] = (vu_short)0x80808080; - addr[0x555] = (vu_short)0xAAAAAAAA; - addr[0xAAA] = (vu_short)0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short *)(info->start[sect]) ; - addr[0] = (vu_short)0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_short *)(info->start[l_sect]); - while ((addr[0] & 0x8080) != 0x8080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = (vu_short)0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_short *addr = (vu_short *)(info->start[0]); - vu_short sdata; - - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* First write upper 16 bits */ - sdata = (short)(data>>16); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x555] = 0xAAAA; - addr[0xAAA] = 0x5555; - addr[0x555] = 0xA0A0; - - *((vu_short *)dest) = sdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_short *)dest) & 0x8080) != (sdata & 0x8080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - - /* Now write lower 16 bits */ - sdata = (short)(data&0xffff); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x555] = 0xAAAA; - addr[0xAAA] = 0x5555; - addr[0x555] = 0xA0A0; - - *((vu_short *)dest + 1) = sdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_short *)dest + 1) & 0x8080) != (sdata & 0x8080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds deleted file mode 100644 index 6e19b3f4585..00000000000 --- a/board/v37/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2003-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/v37/v37.c b/board/v37/v37.c deleted file mode 100644 index 438117e60c0..00000000000 --- a/board/v37/v37.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * DRAM related UPMA register values are modified. - * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS - */ - -#include -#include "mpc8xx.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (void); - -/* ------------------------------------------------------------------------- */ - -#define MBYTE (1024*1024) -#define DRAM_DELAY 0x00000379 /* DRAM delay count */ -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000, - 0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, - - /* burst read. (Offset 8 in upm RAM) */ - 0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000, - 0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* single write. (Offset 0x18 in upm RAM) */ - 0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* burst write. (Offset 0x20 in upm RAM) */ - 0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000, - 0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Refresh cycle, offset 0x30 */ - 0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Exception, 0ffset 0x3C */ - 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, -}; -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Return 1 for now. - * - */ - -int checkboard (void) -{ - printf("Marel V37\n") ; - return (0) ; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long temp; - volatile int delay_cnt; - long int ramsize; - - ramsize = dram_size(); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = 0x400 ; - - if( ramsize == 32*MBYTE ) - temp = 0xd0904110; - else /* 16MB */ - temp = 0xd0802110; - - memctl->memc_mbmr = temp; - - upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* Map controller banks 2 to the SDRAM bank */ - memctl->memc_or2 = 0xA00 | (0 - ramsize); - memctl->memc_br2 = 0xC1; - - memctl->memc_mbmr = temp | 0x08; - memctl->memc_mcr = 0x80804130; - - delay_cnt = 0; - while( delay_cnt++ < DRAM_DELAY ) - ; - - /* Run MRS command in location 5-8 of UPMB */ - - memctl->memc_mbmr = temp | 0x04; - memctl->memc_mar = 0x88; - - memctl->memc_mcr = 0x80804105; - - delay_cnt = 0; - while( delay_cnt++ < DRAM_DELAY ) - ; - -#ifdef CONFIG_CAN_DRIVER - /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CONFIG_SYS_OR3_CAN; - memctl->memc_br3 = CONFIG_SYS_BR3_CAN; - - /* Initialize MBMR */ - memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFC004; - memctl->memc_mcr = 0x0100 | UPMA; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMA; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMA; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMA; - - memctl->memc_mdr = 0xFFFFDC05; - memctl->memc_mcr = 0x0104 | UPMA; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x0118 | UPMA; - - memctl->memc_mdr = 0xCFFCD004; - memctl->memc_mcr = 0x0119 | UPMA; - - memctl->memc_mdr = 0x0FFCC000; - memctl->memc_mcr = 0x011A | UPMA; - - memctl->memc_mdr = 0x7FFCC004; - memctl->memc_mcr = 0x011B | UPMA; - - memctl->memc_mdr = 0xFFFDCC05; - memctl->memc_mcr = 0x011C | UPMA; -#endif /* CONFIG_CAN_DRIVER */ - - return (dram_size()); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Find size of RAM from configuration pins. - * The input pins that contain the memory size are also the debug port - * pins. Normally they are configured as debug port pins. To be able - * to read the memory configuration, we must deactivate the debug port - * and enable the pcmcia input pins. Then return the register to - * previous state. - */ - -static long int dram_size () -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile sysconf8xx_t *siu = &immap->im_siu_conf; - volatile pcmconf8xx_t *pcm = &immap->im_pcmcia; - long int i, memory=1; - unsigned long siu_mcr; - - siu_mcr = siu->sc_siumcr; - siu->sc_siumcr = siu_mcr & 0xFF9FFFFF; - for(i=0; i<10; i++) i = i; - - memory = (pcm->pcmc_pipr>>12) & 0x3; - - siu->sc_siumcr = siu_mcr; - - switch( memory ) - { - case 1: - return( 32*MBYTE ); - case 2: - return( 64*MBYTE ); - default: - break; - } - return( 16*MBYTE ); -} diff --git a/boards.cfg b/boards.cfg index b654b076c4e..e09a92738ba 100644 --- a/boards.cfg +++ b/boards.cfg @@ -979,7 +979,6 @@ Active powerpc mpc8xx - - - Active powerpc mpc8xx - - - lwmon - Wolfgang Denk Active powerpc mpc8xx - - - RRvision - Wolfgang Denk Active powerpc mpc8xx - - - spc1920 - - -Active powerpc mpc8xx - - - v37 - - Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 3d2e4655dfa..d8678af39c2 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +v37 powerpc mpc8xx - - fads powerpc mpc8xx - - netphone powerpc mpc8xx - - netta2 powerpc mpc8xx - - diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c index eafeff73b8b..2bc3ceb418b 100644 --- a/drivers/video/mpc8xx_lcd.c +++ b/drivers/video/mpc8xx_lcd.c @@ -34,7 +34,7 @@ #define CONFIG_LCD_INFO /* Display Logo, (C) and system info */ #endif -#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10) +#if defined(CONFIG_EDT32F10) #undef CONFIG_LCD_LOGO #undef CONFIG_LCD_INFO #endif @@ -413,12 +413,6 @@ void lcd_enable (void) immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */ lcdp->lcd_lccr |= LCCR_PON; -#ifdef CONFIG_V37 - /* Turn on display backlight */ - immr->im_cpm.cp_pbpar |= 0x00008000; - immr->im_cpm.cp_pbdir |= 0x00008000; -#endif - #if defined(CONFIG_LWMON) { uchar c = pic_read (0x60); #if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON) diff --git a/include/commproc.h b/include/commproc.h index 48b761fd829..52ac4caf5a4 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -1023,29 +1023,6 @@ typedef struct scc_enet { # endif /* CONFIG_FEC_ENET */ #endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ -/*** V37 **********************************************************/ - -#ifdef CONFIG_V37 -/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of - * this may be unique to the Marel V37 configuration. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0400) -#define PA_ENET_RCLK ((ushort)0x0200) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) -#endif /* CONFIG_V37 */ - - /*********************************************************************/ /* SCC Event register as used by Ethernet. diff --git a/include/configs/v37.h b/include/configs/v37.h deleted file mode 100644 index 0d01fe207e0..00000000000 --- a/include/configs/v37.h +++ /dev/null @@ -1,375 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_V37 1 /* ...on a Marel V37 board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_LCD -#define CONFIG_MPC8XX_LCD -#define CONFIG_SHARP_LQ084V1DG21 -#undef CONFIG_LCD_LOGO - -/*----------------------------------------------------------------------------- - * I2C Configuration - *----------------------------------------------------------------------------- - */ -#define CONFIG_I2C 1 -#define CONFIG_SYS_I2C_SLAVE 0x2 - -#define CONFIG_8xx_CONS_SMC1 1 -#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs console=tty0 " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_DATE - - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor1=v37-1" -#define MTDPARTS_DEFAULT "mtdparts=v37-1:-(jffs2)" -*/ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE0 0x40000000 -#define CONFIG_SYS_FLASH_BASE1 0x60000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE1 - -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_ADDR 0x80000000/* Address of Environment */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -#define CONFIG_ENV_OFFSET 0 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR 0xFFFFFF88 -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) -/* -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) -*/ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR ( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -#define CONFIG_SYS_OR_TIMING_FLASH 0xF56 - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V) - -#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR5_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V) - -/* - * BR1 and OR1 (Battery backed SRAM) - */ -#define CONFIG_SYS_BR1_PRELIM 0x80000401 -#define CONFIG_SYS_OR1_PRELIM 0xFFC00736 - -/* - * BR2 and OR2 (SDRAM) - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB */ - -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* Marel V37 mem setting */ - -#define CONFIG_SYS_BR3_CAN 0xC0000401 -#define CONFIG_SYS_OR3_CAN 0xFFFF0724 - -/* -#define CONFIG_SYS_BR3_PRELIM 0xFA400001 -#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910 -#define CONFIG_SYS_BR4_PRELIM 0xFA000401 -#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970 -*/ - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* - * Refresh clock Prescalar - */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16 - -/* - * MAMR settings for SDRAM - */ - -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ - MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 0519e80d834f18fa92c24ac42937271ea97d7347 Mon Sep 17 00:00:00 2001 From: Vasili Galka Date: Mon, 30 Jun 2014 12:59:56 +0300 Subject: blackfin: Fix warning about undefined function get_sclk() was not defined in bfin_wdt.c, include the corresponding header. Cc: Sonic Zhang Signed-off-by: Vasili Galka --- drivers/watchdog/bfin_wdt.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c index 7a6756b2e52..6a8db59fdff 100644 --- a/drivers/watchdog/bfin_wdt.c +++ b/drivers/watchdog/bfin_wdt.c @@ -9,6 +9,7 @@ #include #include #include +#include #include void hw_watchdog_reset(void) -- cgit v1.3.1 From b46226bdb5a1690756daf77c42bdec91194927b0 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Thu, 3 Jul 2014 09:28:18 +0200 Subject: i2c: IHS I2C master driver IHS I2C master support was merely a hack in the osd driver. Now it is a proper u-boot I2C framework driver, supporting the v2.00 master features. Signed-off-by: Dirk Eibach --- README | 15 +++ drivers/i2c/Makefile | 1 + drivers/i2c/ihs_i2c.c | 204 +++++++++++++++++++++++++++++++++++++++++ include/configs/dlvision-10g.h | 11 +++ include/configs/iocon.h | 23 ++++- include/gdsys_fpga.h | 25 +++-- 6 files changed, 261 insertions(+), 18 deletions(-) create mode 100644 drivers/i2c/ihs_i2c.c (limited to 'drivers') diff --git a/README b/README index 2bc0d3560c7..082bd2ab1ce 100644 --- a/README +++ b/README @@ -2288,6 +2288,21 @@ CBFS (Coreboot Filesystem) support 9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung) with a fix speed from 100000 and the slave addr 0! + - drivers/i2c/ihs_i2c.c + - activate this driver with CONFIG_SYS_I2C_IHS + - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0 + - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0 + - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0 + - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1 + - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1 + - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1 + - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2 + - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2 + - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2 + - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3 + - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3 + - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3 + additional defines: CONFIG_SYS_NUM_I2C_BUSES diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index e33586d8a6b..96bd45d8539 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_SYS_I2C) += i2c_core.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o +obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c new file mode 100644 index 00000000000..ecc5856b936 --- /dev/null +++ b/drivers/i2c/ihs_i2c.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2013 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + I2CINT_ERROR_EV = 1 << 13, + I2CINT_TRANSMIT_EV = 1 << 14, + I2CINT_RECEIVE_EV = 1 << 15, +}; + +enum { + I2CMB_WRITE = 1 << 10, + I2CMB_2BYTE = 1 << 11, + I2CMB_HOLD_BUS = 1 << 13, + I2CMB_NATIVE = 2 << 14, +}; + +static int wait_for_int(bool read) +{ + u16 val; + unsigned int ctr = 0; + + FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); + while (!(val & (I2CINT_ERROR_EV + | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { + udelay(10); + if (ctr++ > 5000) { + printf("I2C timeout\n"); + return 1; + } + FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); + } + + return (val & I2CINT_ERROR_EV) ? 1 : 0; +} + +static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, + bool is_last) +{ + u16 val; + + FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV + | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV); + FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); + + if (!read && len) { + val = buffer[0]; + + if (len > 1) + val |= buffer[1] << 8; + FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val); + } + + FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox, + I2CMB_NATIVE + | (read ? 0 : I2CMB_WRITE) + | (chip << 1) + | ((len > 1) ? I2CMB_2BYTE : 0) + | (is_last ? 0 : I2CMB_HOLD_BUS)); + + if (wait_for_int(read)) + return 1; + + if (read) { + FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, &val); + buffer[0] = val & 0xff; + if (len > 1) + buffer[1] = val >> 8; + } + + return 0; +} + +static int ihs_i2c_address(uchar chip, uint addr, int alen, bool hold_bus) +{ + int shift = (alen-1) * 8; + + while (alen) { + int transfer = MIN(alen, 2); + uchar buf[2]; + bool is_last = alen <= transfer; + + buf[0] = addr >> shift; + if (alen > 1) + buf[1] = addr >> (shift - 8); + + if (ihs_i2c_transfer(chip, buf, transfer, false, + hold_bus ? false : is_last)) + return 1; + + shift -= 16; + alen -= transfer; + } + + return 0; +} + +static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len, bool read) +{ + if (len <= 0) + return 1; + + if (ihs_i2c_address(chip, addr, alen, !read)) + return 1; + + while (len) { + int transfer = MIN(len, 2); + + if (ihs_i2c_transfer(chip, buffer, transfer, read, + len <= transfer)) + return 1; + + buffer += transfer; + addr += transfer; + len -= transfer; + } + + return 0; +} + + +static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) +{ +#ifdef CONFIG_SYS_I2C_INIT_BOARD + /* + * Call board specific i2c bus reset routine before accessing the + * environment, which might be in a chip on that bus. For details + * about this problem see doc/I2C_Edge_Conditions. + */ + i2c_init_board(); +#endif +} + +static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip) +{ + uchar buffer[2]; + + if (ihs_i2c_transfer(chip, buffer, 0, true, true)) + return 1; + + return 0; +} + +static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + return ihs_i2c_access(adap, chip, addr, alen, buffer, len, true); +} + +static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + return ihs_i2c_access(adap, chip, addr, alen, buffer, len, false); +} + +static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) +{ + if (speed != adap->speed) + return 1; + return speed; +} + +/* + * Register IHS i2c adapters + */ +#ifdef CONFIG_SYS_I2C_IHS_CH0 +U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe, + ihs_i2c_read, ihs_i2c_write, + ihs_i2c_set_bus_speed, + CONFIG_SYS_I2C_IHS_SPEED_0, + CONFIG_SYS_I2C_IHS_SLAVE_0, 0) +#endif +#ifdef CONFIG_SYS_I2C_IHS_CH1 +U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe, + ihs_i2c_read, ihs_i2c_write, + ihs_i2c_set_bus_speed, + CONFIG_SYS_I2C_IHS_SPEED_1, + CONFIG_SYS_I2C_IHS_SLAVE_1, 1) +#endif +#ifdef CONFIG_SYS_I2C_IHS_CH2 +U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe, + ihs_i2c_read, ihs_i2c_write, + ihs_i2c_set_bus_speed, + CONFIG_SYS_I2C_IHS_SPEED_2, + CONFIG_SYS_I2C_IHS_SLAVE_2, 2) +#endif +#ifdef CONFIG_SYS_I2C_IHS_CH3 +U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe, + ihs_i2c_read, ihs_i2c_write, + ihs_i2c_set_bus_speed, + CONFIG_SYS_I2C_IHS_SPEED_3, + CONFIG_SYS_I2C_IHS_SLAVE_3, 3) +#endif diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index 78778970f4a..05a97bf9989 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -99,7 +99,18 @@ */ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 +#define CONFIG_SYS_I2C_IHS +#define CONFIG_SYS_I2C_IHS_CH0 +#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_IHS_CH1 +#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F + +#define CONFIG_SYS_SPD_BUS_NUM 2 + /* Temp sensor/hwmon/dtt */ +#define CONFIG_SYS_DTT_BUS_NUM 2 #define CONFIG_DTT_LM63 1 /* National LM63 */ #define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */ #define CONFIG_DTT_PWM_LOOKUPTABLE \ diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 5636f382408..36b4b550396 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -99,12 +99,27 @@ #define CONFIG_SYS_I2C_PPC4XX_CH0 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_IHS #define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_SPD_BUS_NUM 4 #define CONFIG_PCA953X /* NXP PCA9554 */ #define CONFIG_PCA9698 /* NXP PCA9698 */ +#define CONFIG_SYS_I2C_IHS_CH0 +#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F +#define CONFIG_SYS_I2C_IHS_CH1 +#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F +#define CONFIG_SYS_I2C_IHS_CH2 +#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F +#define CONFIG_SYS_I2C_IHS_CH3 +#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 +#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F + /* * Software (bit-bang) I2C driver configuration */ @@ -121,9 +136,9 @@ #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F -#define CONFIG_SYS_ICS8N3QV01_I2C {1, 2, 3, 4} -#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} +#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} +#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} +#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3} #ifndef __ASSEMBLY__ void fpga_gpio_set(unsigned int bus, int pin); @@ -148,8 +163,6 @@ int fpga_gpio_get(unsigned int bus, int pin); fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \ else \ fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \ - while (!!fpga_gpio_get(I2C_ADAP_HWNR, 0x0020) != !!bit) \ - ; \ } while (0) #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 85ddbcb93be..276a01e744e 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -43,10 +43,12 @@ struct ihs_gpio { }; struct ihs_i2c { - u16 write_mailbox; + u16 interrupt_status; + u16 interrupt_enable; u16 write_mailbox_ext; - u16 read_mailbox; + u16 write_mailbox; u16 read_mailbox_ext; + u16 read_mailbox; }; struct ihs_osd { @@ -84,7 +86,6 @@ struct ihs_fpga { #endif #ifdef CONFIG_IO64 - struct ihs_fpga_channel { u16 status_int; u16 config_int; @@ -121,9 +122,9 @@ struct ihs_fpga { u16 reserved_0[6]; /* 0x0008 */ struct ihs_gpio gpio; /* 0x0014 */ u16 mpc3w_control; /* 0x001a */ - u16 reserved_1[19]; /* 0x001c */ - u16 videocontrol; /* 0x0042 */ - u16 reserved_2[14]; /* 0x0044 */ + u16 reserved_1[18]; /* 0x001c */ + struct ihs_i2c i2c; /* 0x0040 */ + u16 reserved_2[10]; /* 0x004c */ u16 mc_int; /* 0x0060 */ u16 mc_int_en; /* 0x0062 */ u16 mc_status; /* 0x0064 */ @@ -150,15 +151,13 @@ struct ihs_fpga { u16 fpga_features; /* 0x0006 */ u16 reserved_0[10]; /* 0x0008 */ u16 extended_interrupt; /* 0x001c */ - u16 reserved_1[9]; /* 0x001e */ - struct ihs_i2c i2c; /* 0x0030 */ - u16 reserved_2[16]; /* 0x0038 */ + u16 reserved_1[29]; /* 0x001e */ u16 mpc3w_control; /* 0x0058 */ - u16 reserved_3[34]; /* 0x005a */ - u16 videocontrol; /* 0x009e */ - u16 reserved_4[176]; /* 0x00a0 */ + u16 reserved_2[3]; /* 0x005a */ + struct ihs_i2c i2c; /* 0x0060 */ + u16 reserved_3[205]; /* 0x0066 */ struct ihs_osd osd; /* 0x0200 */ - u16 reserved_5[761]; /* 0x020e */ + u16 reserved_4[761]; /* 0x020e */ u16 videomem[31736]; /* 0x0800 */ }; #endif -- cgit v1.3.1 From 3a990bfaeaf3d8388e1a62163e9361fe89ae3c79 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Thu, 3 Jul 2014 09:28:22 +0200 Subject: board: gdsys: Make gdsys osd hardware detection more robust Signed-off-by: Dirk Eibach --- board/gdsys/405ep/iocon.c | 17 ++----- board/gdsys/common/osd.c | 113 +++++++++++++++++++++++++++-------------- drivers/i2c/ihs_i2c.c | 1 - include/configs/dlvision-10g.h | 2 - include/configs/iocon.h | 6 --- 5 files changed, 79 insertions(+), 60 deletions(-) (limited to 'drivers') diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index 079dfb2e73f..6ae15e13f46 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -15,7 +15,6 @@ #include "405ep.h" #include -#include "../common/dp501.h" #include "../common/osd.h" #include "../common/mclink.h" @@ -99,8 +98,6 @@ enum { unsigned int mclink_fpgacount; struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; -int dp501_i2c[] = CONFIG_SYS_DP501_I2C; - static int setup_88e1518(const char *bus, unsigned char addr); int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) @@ -374,20 +371,16 @@ int last_stage_init(void) u16 fpga_features; int feature_carrier_speed = fpga_features & (1<<4); bool ch0_rgmii2_present = false; - int old_bus = i2c_get_bus_num(); FPGA_GET_REG(0, fpga_features, &fpga_features); - /* Turn on Parade DP501 */ - pca9698_direction_output(0x20, 9, 1); - udelay(500000); - - i2c_set_bus_num(dp501_i2c[0]); - dp501_powerup(0x08); - i2c_set_bus_num(old_bus); + if (!legacy) { + /* Turn on Parade DP501 */ + pca9698_direction_output(0x20, 9, 1); + udelay(500000); - if (!legacy) ch0_rgmii2_present = !pca9698_get_value(0x20, 30); + } print_fpga_info(0, ch0_rgmii2_present); osd_probe(0); diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index a839a4ec8e6..1c765e4cbfb 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -9,6 +9,7 @@ #include #include +#include "dp501.h" #include #define CH7301_I2C_ADDR 0x75 @@ -24,6 +25,8 @@ #define SIL1178_MASTER_I2C_ADDRESS 0x38 #define SIL1178_SLAVE_I2C_ADDRESS 0x39 +#define DP501_I2C_ADDR 0x08 + #define PIXCLK_640_480_60 25180000 enum { @@ -54,18 +57,23 @@ u16 *buf; unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1; -#ifdef CONFIG_SYS_CH7301 -int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; +#ifdef CONFIG_SYS_ICS8N3QV01_I2C +int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C; #endif -#ifdef CONFIG_SYS_ICS8N3QV01 -int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C; +#ifdef CONFIG_SYS_CH7301_I2C +int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; #endif -#ifdef CONFIG_SYS_SIL1178 +#ifdef CONFIG_SYS_SIL1178_I2C int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C; #endif +#ifdef CONFIG_SYS_DP501_I2C +int dp501_i2c[] = CONFIG_SYS_DP501_I2C; +#endif + + #ifdef CONFIG_SYS_MPC92469AC static void mpc92469ac_calc_parameters(unsigned int fout, unsigned int *post_div, unsigned int *feedback_div) @@ -118,7 +126,7 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout) } #endif -#ifdef CONFIG_SYS_ICS8N3QV01 +#ifdef CONFIG_SYS_ICS8N3QV01_I2C static unsigned int ics8n3qv01_get_fout_calc(unsigned index) { @@ -283,6 +291,8 @@ int osd_probe(unsigned screen) u16 features; u8 value; int old_bus = i2c_get_bus_num(); + bool pixclock_present = false; + bool output_driver_present = false; FPGA_GET_REG(0, osd.version, &version); FPGA_GET_REG(0, osd.features, &features); @@ -297,51 +307,76 @@ int osd_probe(unsigned screen) printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n", screen, version/100, version%100, base_width, base_height); -#ifdef CONFIG_SYS_CH7301 - i2c_set_bus_num(ch7301_i2c[screen]); - value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); - if (value != 0x17) { - printf(" Probing CH7301 failed, DID %02x\n", value); - i2c_set_bus_num(old_bus); - return -1; - } - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); - i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); -#endif + /* setup pixclock */ #ifdef CONFIG_SYS_MPC92469AC + pixclock_present = true; mpc92469ac_set(screen, PIXCLK_640_480_60); #endif -#ifdef CONFIG_SYS_ICS8N3QV01 +#ifdef CONFIG_SYS_ICS8N3QV01_I2C i2c_set_bus_num(ics8n3qv01_i2c[screen]); - ics8n3qv01_set(PIXCLK_640_480_60); + if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) { + ics8n3qv01_set(PIXCLK_640_480_60); + pixclock_present = true; + } #endif -#ifdef CONFIG_SYS_SIL1178 + if (!pixclock_present) + printf(" no pixelclock found\n"); + + /* setup output driver */ + +#ifdef CONFIG_SYS_CH7301_I2C + i2c_set_bus_num(ch7301_i2c[screen]); + if (!i2c_probe(CH7301_I2C_ADDR)) { + value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); + if (value == 0x17) { + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); + i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); + output_driver_present = true; + } + } +#endif + +#ifdef CONFIG_SYS_SIL1178_I2C i2c_set_bus_num(sil1178_i2c[screen]); - value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02); - if (value != 0x06) { - printf(" Probing SIL1178, DEV_IDL %02x\n", value); - i2c_set_bus_num(old_bus); - return -1; + if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) { + value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02); + if (value == 0x06) { + /* + * magic initialization sequence, + * adapted from datasheet + */ + i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36); + i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); + output_driver_present = true; + } + } +#endif + +#ifdef CONFIG_SYS_DP501_I2C + i2c_set_bus_num(dp501_i2c[screen]); + if (!i2c_probe(DP501_I2C_ADDR)) { + dp501_powerup(DP501_I2C_ADDR); + output_driver_present = true; } - /* magic initialization sequence adapted from datasheet */ - i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36); - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44); - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c); - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10); - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80); - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30); - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89); - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60); - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36); - i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); #endif + if (!output_driver_present) + printf(" no output driver found\n"); + FPGA_SET_REG(screen, osd.control, 0x0049); FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1)); diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c index ecc5856b936..fe66ce2a4ac 100644 --- a/drivers/i2c/ihs_i2c.c +++ b/drivers/i2c/ihs_i2c.c @@ -34,7 +34,6 @@ static int wait_for_int(bool read) | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { udelay(10); if (ctr++ > 5000) { - printf("I2C timeout\n"); return 1; } FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val); diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index c2289ce9b52..08ab5c31773 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -121,9 +121,7 @@ { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } } #define CONFIG_DTT_TACH_LIMIT 0xa10 -#define CONFIG_SYS_ICS8N3QV01 #define CONFIG_SYS_ICS8N3QV01_I2C {0, 1} -#define CONFIG_SYS_SIL1178 #define CONFIG_SYS_SIL1178_I2C {0, 1} /* EBC peripherals */ diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 1aebab37bb0..1836d127aaf 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -166,11 +166,6 @@ int fpga_gpio_get(unsigned int bus, int pin); } while (0) #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ -/* - * OSD hardware - */ -#define CONFIG_SYS_MPC92469AC - /* * FLASH organization */ @@ -298,7 +293,6 @@ int fpga_gpio_get(unsigned int bus, int pin); /* * OSD Setup */ -#define CONFIG_SYS_ICS8N3QV01 #define CONFIG_SYS_MPC92469AC #define CONFIG_SYS_OSD_SCREENS 1 #define CONFIG_SYS_DP501_DIFFERENTIAL -- cgit v1.3.1 From 26707d9e6bb0d2e5e6de706cd68bddcea34e731f Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 23 Jun 2014 16:25:38 -0500 Subject: usb: host: xhci: make sure to power up PHY some boards won't work if the PHY isn't explicitly powered up. Signed-off-by: Felipe Balbi --- drivers/usb/host/xhci-omap.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c index e667810bb3d..912b2bd8d58 100644 --- a/drivers/usb/host/xhci-omap.c +++ b/drivers/usb/host/xhci-omap.c @@ -98,6 +98,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap) { int ret = 0; + usb_phy_power(1); omap_enable_phy(omap); ret = dwc3_core_init(omap->dwc3_reg); -- cgit v1.3.1 From 5ba95541b700d2edecb4d97d4b905f51ed8551b3 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 23 Jun 2014 17:18:24 -0500 Subject: usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x Newer AM437x silicon requires us to explicitly power up the USB2 PHY. By implementing usb_phy_power() we can achieve that. Signed-off-by: Felipe Balbi --- arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 5 +++++ drivers/usb/phy/omap_usb_phy.c | 17 ++++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index b4703192499..efdecf46136 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -43,6 +43,11 @@ #define VTP0_CTRL_ADDR 0x44E10E0C #define VTP1_CTRL_ADDR 0x48140E10 +/* USB CTRL Base Address */ +#define USB1_CTRL 0x44e10628 +#define USB1_CTRL_CM_PWRDN BIT(0) +#define USB1_CTRL_OTG_PWRDN BIT(1) + /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x44E12000 #define DDR_PHY_DATA_ADDR 0x44E120C8 diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c index af46db2eddd..f78d5329668 100644 --- a/drivers/usb/phy/omap_usb_phy.c +++ b/drivers/usb/phy/omap_usb_phy.c @@ -222,7 +222,22 @@ static void am437x_enable_usb2_phy2(struct omap_xhci *omap) void usb_phy_power(int on) { - return; + u32 val; + + /* USB1_CTRL */ + val = readl(USB1_CTRL); + if (on) { + /* + * these bits are re-used on AM437x to power up/down the USB + * CM and OTG PHYs, if we don't toggle them, USB will not be + * functional on newer silicon revisions + */ + val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN); + } else { + val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN; + } + + writel(val, USB1_CTRL); } #endif /* CONFIG_AM437X_USB2PHY2_HOST */ -- cgit v1.3.1