From 4bc97a3b816914d8b37e3d1ecac464e6193fd230 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:24 +0100 Subject: mpc83xx: Introduce ARCH_MPC830* Replace CONFIG_MPC830* with proper CONFIG_ARCH_MPC830* Kconfig options. Signed-off-by: Mario Six --- drivers/qe/qe.c | 2 +- drivers/ram/mpc83xx_sdram.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 70d02d3f939..505ae9b45fb 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -119,7 +119,7 @@ static void qe_sdma_init(void) */ static u8 thread_snum[] = { /* Evthreads 16-29 are not supported in MPC8309 */ -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) 0x04, 0x05, 0x0c, 0x0d, 0x14, 0x15, 0x1c, 0x1d, 0x24, 0x25, 0x2c, 0x2d, diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index 441baeb6f1a..e3523299812 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -179,7 +179,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_RD_NEVER: case ODT_RD_ONLY_CURRENT: case ODT_RD_ONLY_OTHER_CS: - if (!IS_ENABLED(CONFIG_MPC830x) && + if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_MPC831x) && !IS_ENABLED(CONFIG_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { @@ -210,7 +210,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_WR_NEVER: case ODT_WR_ONLY_CURRENT: case ODT_WR_ONLY_OTHER_CS: - if (!IS_ENABLED(CONFIG_MPC830x) && + if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_MPC831x) && !IS_ENABLED(CONFIG_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { -- cgit v1.3.1 From 9403fc41c71fc4146ab0e890ed90b28fc053791f Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:25 +0100 Subject: mpc83xx: Introduce ARCH_MPC831* Replace CONFIG_MPC833* with proper CONFIG_ARCH_MPC833* Kconfig options. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 15 +++++++++++ arch/powerpc/cpu/mpc83xx/cpu.c | 2 +- arch/powerpc/cpu/mpc83xx/cpu_init.c | 4 +-- arch/powerpc/cpu/mpc83xx/fdt.c | 6 ++--- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- arch/powerpc/cpu/mpc83xx/speed.c | 40 ++++++++++++++-------------- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 4 +-- arch/powerpc/include/asm/global_data.h | 8 +++--- arch/powerpc/include/asm/immap_83xx.h | 4 +-- arch/powerpc/include/asm/mpc8xxx_spi.h | 4 +-- drivers/ram/mpc83xx_sdram.c | 4 +-- include/configs/MPC8313ERDB.h | 2 -- include/configs/MPC8315ERDB.h | 2 -- include/configs/ids8313.h | 3 --- include/configs/ve8313.h | 2 -- include/mpc83xx.h | 20 +++++++------- scripts/config_whitelist.txt | 3 --- 17 files changed, 64 insertions(+), 61 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 142b9247860..20780ba68bd 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -17,6 +17,7 @@ config TARGET_SBC8349 config TARGET_VE8313 bool "Support ve8313" + select ARCH_MPC8313 config TARGET_VME8349 bool "Support vme8349" @@ -28,11 +29,13 @@ config TARGET_MPC8308RDB config TARGET_MPC8313ERDB bool "Support MPC8313ERDB" + select ARCH_MPC8313 select BOARD_EARLY_INIT_F select SUPPORT_SPL config TARGET_MPC8315ERDB bool "Support MPC8315ERDB" + select ARCH_MPC8315 select BOARD_EARLY_INIT_F config TARGET_MPC8323ERDB @@ -65,6 +68,7 @@ config TARGET_MPC837XERDB config TARGET_IDS8313 bool "Support ids8313" + select ARCH_MPC8313 select DM imply CMD_DM @@ -113,6 +117,17 @@ config ARCH_MPC8309 bool select ARCH_MPC830X +config ARCH_MPC831X + bool + +config ARCH_MPC8313 + bool + select ARCH_MPC831X + +config ARCH_MPC8315 + bool + select ARCH_MPC831X + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index b29f271e9bc..8a88068fdba 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -18,7 +18,7 @@ #include #include #include -#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x) +#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X) #include #include #endif diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 1555205e069..7d8d5516b4c 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -240,7 +240,7 @@ void cpu_init_f (volatile immap_t * im) /* System General Purpose Register */ #ifdef CONFIG_SYS_SICRH -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313) +#if defined(CONFIG_MPC834x) || defined(CONFIG_ARCH_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, &im->sysconf.sicrh); @@ -312,7 +312,7 @@ void cpu_init_f (volatile immap_t * im) im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR; #endif -#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x) +#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X) uint32_t temp; struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index 0ecafd708fc..cfd391b78ab 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -16,7 +16,7 @@ extern void ft_qe_setup(void *blob); DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_BOOTCOUNT_LIMIT) && \ - (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) + (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X)) #include void fdt_fixup_muram (void *blob) @@ -52,7 +52,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\ defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) -#ifdef CONFIG_MPC8313 +#ifdef CONFIG_ARCH_MPC8313 /* * mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1 * h/w (see AN3545). The base device tree in use has rev. 1 ID numbers, @@ -123,7 +123,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #if defined(CONFIG_BOOTCOUNT_LIMIT) && \ - (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) + (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X)) fdt_fixup_muram (blob); #endif } diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 97ef77121b5..3f18aadf19b 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -31,7 +31,7 @@ void board_add_ram_info(int use_default) printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) puts(", 16-bit"); else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index d537af5130a..9f09d2955f8 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -85,7 +85,7 @@ int get_clocks(void) u32 lcrr; u32 csb_clk; -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; @@ -101,7 +101,7 @@ int get_clocks(void) #if !defined(CONFIG_MPC832x) u32 i2c2_clk; #endif -#if defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) u32 tdm_clk; #endif #if defined(CONFIG_FSL_ESDHC) @@ -122,12 +122,12 @@ int get_clocks(void) u32 qe_clk; u32 brg_clk; #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) u32 pciexp1_clk; u32 pciexp2_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; #endif @@ -155,7 +155,7 @@ int get_clocks(void) sccr = im->clk.sccr; -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: @@ -176,7 +176,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: @@ -197,7 +197,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: @@ -216,7 +216,7 @@ int get_clocks(void) /* unknown SCCR_TSEC2CM value */ return -4; } -#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) tsec2_clk = tsec1_clk; if (!(sccr & SCCR_TSEC1ON)) @@ -291,7 +291,7 @@ int get_clocks(void) return -8; } #endif -#if defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) { case 0: tdm_clk = 0; @@ -317,7 +317,7 @@ int get_clocks(void) i2c1_clk = csb_clk; #elif defined(CONFIG_MPC832x) i2c1_clk = enc_clk; -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; @@ -330,7 +330,7 @@ int get_clocks(void) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: @@ -369,7 +369,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { case 0: sata_clk = 0; @@ -448,7 +448,7 @@ int get_clocks(void) #endif gd->arch.csb_clk = csb_clk; -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; @@ -459,7 +459,7 @@ int get_clocks(void) #if defined(CONFIG_MPC834x) gd->arch.usbmph_clk = usbmph_clk; #endif -#if defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) gd->arch.tdm_clk = tdm_clk; #endif #if defined(CONFIG_FSL_ESDHC) @@ -483,12 +483,12 @@ int get_clocks(void) gd->arch.qe_clk = qe_clk; gd->arch.brg_clk = brg_clk; #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) gd->arch.pciexp1_clk = pciexp1_clk; gd->arch.pciexp2_clk = pciexp2_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) gd->arch.sata_clk = sata_clk; #endif gd->pci_clk = pci_sync_in; @@ -550,7 +550,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->arch.i2c2_clk)); #endif -#if defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) printf(" TDM: %-4s MHz\n", strmhz(buf, gd->arch.tdm_clk)); #endif @@ -558,7 +558,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->arch.sdhc_clk)); #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->arch.tsec1_clk)); @@ -574,14 +574,14 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->arch.usbmph_clk)); #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->arch.pciexp1_clk)); printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->arch.pciexp2_clk)); #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) printf(" SATA: %-4s MHz\n", strmhz(buf, gd->arch.sata_clk)); #endif diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 4e5a352ac67..74ba91a4695 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -6,8 +6,8 @@ /* * The MCP83xx's 1-2 GPIO controllers each with 32 bits. */ -#if defined(CONFIG_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ - defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ + defined(CONFIG_ARCH_MPC8315) #define MPC83XX_GPIO_CTRLRS 1 #elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) #define MPC83XX_GPIO_CTRLRS 2 diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 700e2be0ee2..0c3a4ade5c3 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -35,7 +35,7 @@ struct arch_global_data { #else /* There are other clocks in the MPC83XX */ u32 csb_clk; -# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; @@ -46,19 +46,19 @@ struct arch_global_data { # if defined(CONFIG_MPC834x) u32 usbmph_clk; # endif /* CONFIG_MPC834x */ -# if defined(CONFIG_MPC8315) +# if defined(CONFIG_ARCH_MPC8315) u32 tdm_clk; # endif u32 core_clk; u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; -# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) u32 pciexp1_clk; u32 pciexp2_clk; # endif -# if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +# if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; # endif # if defined(CONFIG_MPC8360) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index b10feb546c6..d22d887babd 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -679,7 +679,7 @@ typedef struct immap { #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 #endif -#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ @@ -714,7 +714,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 518d0c388a7..3edd5610072 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -11,8 +11,8 @@ #include #if defined(CONFIG_ARCH_MPC8308) || \ - defined(CONFIG_MPC8313) || \ - defined(CONFIG_MPC8315) || \ + defined(CONFIG_ARCH_MPC8313) || \ + defined(CONFIG_ARCH_MPC8315) || \ defined(CONFIG_MPC834x) || \ defined(CONFIG_MPC837x) diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index e3523299812..58db7948c15 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -180,7 +180,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_RD_ONLY_CURRENT: case ODT_RD_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && - !IS_ENABLED(CONFIG_MPC831x) && + !IS_ENABLED(CONFIG_ARCH_MPC831X) && !IS_ENABLED(CONFIG_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_rd_cfg value %d invalid.\n", @@ -211,7 +211,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_WR_ONLY_CURRENT: case ODT_WR_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && - !IS_ENABLED(CONFIG_MPC831x) && + !IS_ENABLED(CONFIG_ARCH_MPC831X) && !IS_ENABLED(CONFIG_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_wr_cfg value %d invalid.\n", diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index cfa5b565248..c5a8065d6a4 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -13,8 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC831x 1 -#define CONFIG_MPC8313 1 #define CONFIG_MPC8313ERDB 1 #ifdef CONFIG_NAND diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 0ccf4acb827..b8506321af3 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -22,8 +22,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC831x 1 /* MPC831x CPU family */ -#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ /* diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 7e4c497fe0a..caa3dd1f1a6 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -14,9 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC831x -#define CONFIG_MPC8313 - #define CONFIG_FSL_ELBC #define CONFIG_BOOT_RETRY_TIME 900 diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 85f678e5c4a..791eac363bd 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -16,8 +16,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC831x 1 -#define CONFIG_MPC8313 1 #define CONFIG_PCI_INDIRECT_BRIDGE 1 #define CONFIG_FSL_ELBC 1 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index e93f50d0b33..0da271b2f36 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -129,7 +129,7 @@ #define SPCR_TSEC2EP 0x00000003 #define SPCR_TSEC2EP_SHIFT (31-31) -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) /* SPCR bits - MPC8308, MPC831x and MPC837x specific */ /* TSEC data priority */ @@ -216,7 +216,7 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000 -#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) /* SICRL bits - MPC8313 specific */ #define SICRL_LBC 0x30000000 #define SICRL_UART 0x0C000000 @@ -248,7 +248,7 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001 -#elif defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8315) /* SICRL bits - MPC8315 specific */ #define SICRL_DMA_CH0 0xc0000000 #define SICRL_DMA_SPI 0x30000000 @@ -639,7 +639,7 @@ #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_2 0x00000000 @@ -765,7 +765,7 @@ #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 @@ -818,7 +818,7 @@ /* * RSR - Reset Status Register */ -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 @@ -965,7 +965,7 @@ #define SCCR_USBCM_2 0x00A00000 #define SCCR_USBCM_3 0x00F00000 -#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) /* TSEC1 bits are for TSEC2 as well */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -986,7 +986,7 @@ #define SCCR_USBDRCM_2 0x00200000 #define SCCR_USBDRCM_3 0x00300000 -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) /* SCCR bits - MPC8315/MPC8308 specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -1117,7 +1117,7 @@ */ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 -#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 @@ -1239,7 +1239,7 @@ #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) #define SDRAM_CFG_DBW_MASK 0x00180000 #define SDRAM_CFG_DBW_16 0x00100000 #define SDRAM_CFG_DBW_32 0x00080000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d7d1b563591..d7bd37adf5d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1220,11 +1220,8 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC8313 CONFIG_MPC8313ERDB -CONFIG_MPC8315 CONFIG_MPC8315ERDB -CONFIG_MPC831x CONFIG_MPC832XEMDS CONFIG_MPC832x CONFIG_MPC8349 -- cgit v1.3.1 From d5cfa4aa5d6422ad654bbc4032361c2367439de8 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:27 +0100 Subject: mpc83xx: Introduce ARCH_MPC834* Replace CONFIG_MPC834* with proper CONFIG_ARCH_MPC834* Kconfig options. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 12 ++++++++++++ arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- arch/powerpc/cpu/mpc83xx/speed.c | 22 +++++++++++----------- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 2 +- arch/powerpc/include/asm/fsl_lbc.h | 8 ++++---- arch/powerpc/include/asm/global_data.h | 6 +++--- arch/powerpc/include/asm/immap_83xx.h | 6 +++--- arch/powerpc/include/asm/mpc8xxx_spi.h | 2 +- drivers/pci/pci_auto.c | 2 +- drivers/pci/pci_auto_old.c | 2 +- include/configs/MPC8349EMDS.h | 2 -- include/configs/MPC8349ITX.h | 3 --- include/configs/TQM834x.h | 2 -- include/configs/sbc8349.h | 2 -- include/configs/vme8349.h | 2 -- include/mpc83xx.h | 18 +++++++++--------- include/usb/ehci-ci.h | 2 +- scripts/config_whitelist.txt | 2 -- 19 files changed, 49 insertions(+), 50 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 1b9402e024b..6cca45e4026 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -14,6 +14,7 @@ config TARGET_MPC8308_P1M config TARGET_SBC8349 bool "Support sbc8349" + select ARCH_MPC8349 config TARGET_VE8313 bool "Support ve8313" @@ -21,6 +22,7 @@ config TARGET_VE8313 config TARGET_VME8349 bool "Support vme8349" + select ARCH_MPC8349 config TARGET_MPC8308RDB bool "Support MPC8308RDB" @@ -49,6 +51,7 @@ config TARGET_MPC832XEMDS config TARGET_MPC8349EMDS bool "Support MPC8349EMDS" + select ARCH_MPC8349 select BOARD_EARLY_INIT_F select SYS_FSL_DDR select SYS_FSL_DDR_BE @@ -56,6 +59,7 @@ config TARGET_MPC8349EMDS config TARGET_MPC8349ITX bool "Support MPC8349ITX" + select ARCH_MPC8349 imply CMD_IRQ config TARGET_MPC837XEMDS @@ -96,6 +100,7 @@ config TARGET_TUXX1 config TARGET_TQM834X bool "Support TQM834x" + select ARCH_MPC8349 config TARGET_HRCON bool "Support hrcon" @@ -135,6 +140,13 @@ config ARCH_MPC8315 config ARCH_MPC832X bool +config ARCH_MPC834X + bool + +config ARCH_MPC8349 + bool + select ARCH_MPC834X + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 7d8d5516b4c..7c378671feb 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -240,7 +240,7 @@ void cpu_init_f (volatile immap_t * im) /* System General Purpose Register */ #ifdef CONFIG_SYS_SICRH -#if defined(CONFIG_MPC834x) || defined(CONFIG_ARCH_MPC8313) +#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, &im->sysconf.sicrh); diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 3f18aadf19b..b3cbf9f8823 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -426,7 +426,7 @@ long int spd_sdram() /* * Errata DDR6 work around: input enable 2 cycles earlier. - * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2. + * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2. */ if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){ if (caslat == 2) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index ab025af70d4..7cb6f3727df 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -86,14 +86,14 @@ int get_clocks(void) u32 csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; #elif defined(CONFIG_ARCH_MPC8309) u32 usbdr_clk; #endif -#ifdef CONFIG_MPC834x +#ifdef CONFIG_ARCH_MPC834X u32 usbmph_clk; #endif u32 core_clk; @@ -156,7 +156,7 @@ int get_clocks(void) sccr = im->clk.sccr; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -177,7 +177,7 @@ int get_clocks(void) #endif #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: usbdr_clk = 0; @@ -198,7 +198,7 @@ int get_clocks(void) #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: tsec2_clk = 0; @@ -225,7 +225,7 @@ int get_clocks(void) tsec2_clk = 0; #endif -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { case 0: usbmph_clk = 0; @@ -311,7 +311,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) i2c1_clk = tsec2_clk; #elif defined(CONFIG_MPC8360) i2c1_clk = csb_clk; @@ -449,14 +449,14 @@ int get_clocks(void) gd->arch.csb_clk = csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; gd->arch.usbdr_clk = usbdr_clk; #elif defined(CONFIG_ARCH_MPC8309) gd->arch.usbdr_clk = usbdr_clk; #endif -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) gd->arch.usbmph_clk = usbmph_clk; #endif #if defined(CONFIG_ARCH_MPC8315) @@ -559,7 +559,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.sdhc_clk)); #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->arch.tsec1_clk)); printf(" TSEC2: %-4s MHz\n", @@ -570,7 +570,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->arch.usbdr_clk)); #endif -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->arch.usbmph_clk)); #endif diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 74ba91a4695..16997316ff0 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -9,7 +9,7 @@ #if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8315) #define MPC83XX_GPIO_CTRLRS 1 -#elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) #define MPC83XX_GPIO_CTRLRS 2 #else #define MPC83XX_GPIO_CTRLRS 0 diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index cf89e186a67..0ea44560332 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -43,10 +43,10 @@ void lbc_sdram_init(void); #define BR_MSEL 0x000000E0 #define BR_MSEL_SHIFT 5 #define BR_MS_GPCM 0x00000000 /* GPCM */ -#if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360) +#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_MPC8360) #define BR_MS_FCM 0x00000020 /* FCM */ #endif -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC8360) #define BR_MS_SDRAM 0x00000060 /* SDRAM */ #elif defined(CONFIG_MPC85xx) #define BR_MS_SDRAM 0x00000000 /* SDRAM */ @@ -54,7 +54,7 @@ void lbc_sdram_init(void); #define BR_MS_UPMA 0x00000080 /* UPMA */ #define BR_MS_UPMB 0x000000A0 /* UPMB */ #define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if !defined(CONFIG_MPC834x) +#if !defined(CONFIG_ARCH_MPC834X) #define BR_ATOM 0x0000000C #define BR_ATOM_SHIFT 2 #endif @@ -67,7 +67,7 @@ void lbc_sdram_init(void); #define UPMB 1 #define UPMC 2 -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) #else #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 0c3a4ade5c3..cd0d76696d2 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -36,16 +36,16 @@ struct arch_global_data { /* There are other clocks in the MPC83XX */ u32 csb_clk; # if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; # elif defined(CONFIG_ARCH_MPC8309) u32 usbdr_clk; # endif -# if defined(CONFIG_MPC834x) +# if defined(CONFIG_ARCH_MPC834X) u32 usbmph_clk; -# endif /* CONFIG_MPC834x */ +# endif /* CONFIG_ARCH_MPC834X */ # if defined(CONFIG_ARCH_MPC8315) u32 tdm_clk; # endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 318b79d0b8a..bf7a4b9250c 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -625,7 +625,7 @@ typedef struct tdmdmac83xx { u8 fixme[0x2000]; } tdmdmac83xx_t; -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ @@ -666,7 +666,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#ifndef CONFIG_MPC834x +#ifndef CONFIG_ARCH_MPC834X #ifdef CONFIG_HAS_FSL_MPH_USB #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 @@ -946,7 +946,7 @@ typedef struct immap { #endif #define CONFIG_SYS_MPC83xx_USB1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET) -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define CONFIG_SYS_MPC83xx_USB2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET) #endif diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 3edd5610072..0c2bdb326b2 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -13,7 +13,7 @@ #if defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8313) || \ defined(CONFIG_ARCH_MPC8315) || \ - defined(CONFIG_MPC834x) || \ + defined(CONFIG_ARCH_MPC834X) || \ defined(CONFIG_MPC837x) typedef struct spi8xxx { diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index d7237f6eee0..a673d8ae136 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -359,7 +359,7 @@ int dm_pciauto_config_device(struct udevice *dev) PCI_DEV(dm_pci_get_bdf(dev))); break; #endif -#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_VME8349) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c index e705a3072e7..90c22a08cbc 100644 --- a/drivers/pci/pci_auto_old.c +++ b/drivers/pci/pci_auto_old.c @@ -376,7 +376,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) PCI_DEV(dev)); break; #endif -#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_VME8349) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index bda477cc160..93de2cc1c07 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -16,8 +16,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_PCI_66M #ifdef CONFIG_PCI_66M diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 111023b7bee..496780d80c0 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -46,9 +46,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ -#define CONFIG_MPC8349 /* MPC8349 specific */ - #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ #define CONFIG_MISC_INIT_F diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 0942b872ac3..2b82bd82eb7 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -15,8 +15,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x specific */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ /* IMMR Base Address Register, use Freescale default: 0xff400000 */ #define CONFIG_SYS_IMMR 0xff400000 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 9074be80f11..6ae11185cb7 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -18,8 +18,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 805f7d3df66..56955501309 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -28,8 +28,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 0f4466ae896..feb8fef6018 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -55,7 +55,7 @@ #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) #define REVID_MINOR(spridr) (spridr & 0x000000FF) #else @@ -108,7 +108,7 @@ #define SPCR_COREPR 0x00300000 #define SPCR_COREPR_SHIFT (31-11) -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) /* SPCR bits - MPC8349 specific */ /* TSEC1 data priority */ #define SPCR_TSEC1DP 0x00003000 @@ -145,7 +145,7 @@ /* SICRL/H - System I/O Configuration Register Low/High */ -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) /* SICRL bits - MPC8349 specific */ #define SICRL_LDP_A 0x80000000 #define SICRL_USB1 0x40000000 @@ -720,7 +720,7 @@ #define HRCWH_PCI_HOST_SHIFT 31 #define HRCWH_PCI_AGENT 0x00000000 -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define HRCWH_32_BIT_PCI 0x00000000 #define HRCWH_64_BIT_PCI 0x40000000 #endif @@ -731,7 +731,7 @@ #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 @@ -755,7 +755,7 @@ #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 #define HRCWH_ROM_LOC_PCI1 0x00100000 -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif #if defined(CONFIG_MPC837x) @@ -790,7 +790,7 @@ #define HRCWH_TSEC2M_IN_SGMII 0x00001800 #endif -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define HRCWH_TSEC1M_IN_RGMII 0x00000000 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 #define HRCWH_TSEC1M_IN_GMII 0x00008000 @@ -937,8 +937,8 @@ #define SCCR_PCICM 0x00010000 #define SCCR_PCICM_SHIFT 16 -#if defined(CONFIG_MPC834x) -/* SCCR bits - MPC834x specific */ +#if defined(CONFIG_ARCH_MPC834X) +/* SCCR bits - MPC834X specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC1CM_0 0x00000000 diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index e4579a5bec8..efb2eec5ce7 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -147,7 +147,7 @@ #if defined(CONFIG_MPC83xx) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR #else #define CONFIG_SYS_FSL_USB2_ADDR 0 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 481076e9d29..5cae6d81f27 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1223,9 +1223,7 @@ CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB CONFIG_MPC832XEMDS -CONFIG_MPC8349 CONFIG_MPC8349ITX -CONFIG_MPC834x CONFIG_MPC8360 CONFIG_MPC837XEMDS CONFIG_MPC837XERDB -- cgit v1.3.1 From 61abced70fe5abf59b1a906d395b659ad918b8de Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:28 +0100 Subject: mpc83xx: Introduce ARCH_MPC836* Replace CONFIG_MPC836* with proper CONFIG_ARCH_MPC836* Kconfig options. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 4 ++++ arch/powerpc/cpu/mpc83xx/speed.c | 10 +++++----- arch/powerpc/include/asm/fsl_lbc.h | 4 ++-- arch/powerpc/include/asm/global_data.h | 4 ++-- arch/powerpc/include/asm/immap_83xx.h | 2 +- board/keymile/km83xx/km83xx.c | 4 ++-- drivers/ram/mpc83xx_sdram.c | 8 ++++---- include/configs/km8360.h | 1 - include/linux/immap_qe.h | 2 +- include/mpc83xx.h | 10 +++++----- include/post.h | 2 +- scripts/config_whitelist.txt | 1 - 12 files changed, 27 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 6cca45e4026..5f9d036e371 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -80,6 +80,7 @@ config TARGET_IDS8313 config TARGET_KM8360 bool "Support km8360" + select ARCH_MPC8360 imply CMD_CRAMFS imply CMD_DIAG imply FS_CRAMFS @@ -147,6 +148,9 @@ config ARCH_MPC8349 bool select ARCH_MPC834X +config ARCH_MPC8360 + bool + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 7cb6f3727df..ed77675a8ea 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -113,7 +113,7 @@ int get_clocks(void) u32 lbiu_clk; u32 lclk_clk; u32 mem_clk; -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) u32 mem_sec_clk; #endif #if defined(CONFIG_QE) @@ -313,7 +313,7 @@ int get_clocks(void) #if defined(CONFIG_ARCH_MPC834X) i2c1_clk = tsec2_clk; -#elif defined(CONFIG_MPC8360) +#elif defined(CONFIG_ARCH_MPC8360) i2c1_clk = csb_clk; #elif defined(CONFIG_ARCH_MPC832X) i2c1_clk = enc_clk; @@ -407,7 +407,7 @@ int get_clocks(void) (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT)); corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT; -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) mem_sec_clk = csb_clk * (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT)); #endif @@ -476,7 +476,7 @@ int get_clocks(void) gd->arch.lbiu_clk = lbiu_clk; gd->arch.lclk_clk = lclk_clk; gd->mem_clk = mem_clk; -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) gd->arch.mem_sec_clk = mem_sec_clk; #endif #if defined(CONFIG_QE) @@ -536,7 +536,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->arch.lclk_clk)); printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk)); -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->arch.mem_sec_clk)); #endif diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 0ea44560332..3528acd627d 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -43,10 +43,10 @@ void lbc_sdram_init(void); #define BR_MSEL 0x000000E0 #define BR_MSEL_SHIFT 5 #define BR_MS_GPCM 0x00000000 /* GPCM */ -#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_MPC8360) +#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360) #define BR_MS_FCM 0x00000020 /* FCM */ #endif -#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360) #define BR_MS_SDRAM 0x00000060 /* SDRAM */ #elif defined(CONFIG_MPC85xx) #define BR_MS_SDRAM 0x00000000 /* SDRAM */ diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index cd0d76696d2..cf3ba588220 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -61,9 +61,9 @@ struct arch_global_data { # if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; # endif -# if defined(CONFIG_MPC8360) +# if defined(CONFIG_ARCH_MPC8360) u32 mem_sec_clk; -# endif /* CONFIG_MPC8360 */ +# endif /* CONFIG_ARCH_MPC8360 */ #endif #endif #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index bf7a4b9250c..f6721e7b1d5 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -803,7 +803,7 @@ typedef struct immap { rom83xx_t rom; /* On Chip ROM */ } immap_t; -#elif defined(CONFIG_MPC8360) +#elif defined(CONFIG_ARCH_MPC8360) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index ce5126aae6b..12044ee0d70 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -33,7 +33,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; const qe_iop_conf_t qe_iop_conf_tab[] = { /* port pin dir open_drain assign */ -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) /* MDIO */ {0, 1, 3, 0, 2}, /* MDIO */ {0, 2, 1, 0, 1}, /* MDC */ @@ -148,7 +148,7 @@ int board_early_init_r(void) u32 *mxmr = &lbc->mamr; #endif -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) unsigned short svid; /* * Because of errata in the UCCs, we have to write to the reserved diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index 58db7948c15..3e57b13118c 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -169,7 +169,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0); switch (odt_rd_cfg) { case ODT_RD_ONLY_OTHER_DIMM: - if (!IS_ENABLED(CONFIG_MPC8360) && + if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); @@ -181,7 +181,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_RD_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && - !IS_ENABLED(CONFIG_MPC8360) && + !IS_ENABLED(CONFIG_ARCH_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); @@ -200,7 +200,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0); switch (odt_wr_cfg) { case ODT_WR_ONLY_OTHER_DIMM: - if (!IS_ENABLED(CONFIG_MPC8360) && + if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); @@ -212,7 +212,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_WR_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && - !IS_ENABLED(CONFIG_MPC8360) && + !IS_ENABLED(CONFIG_ARCH_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); diff --git a/include/configs/km8360.h b/include/configs/km8360.h index feb8a9a16dc..7857b830551 100644 --- a/include/configs/km8360.h +++ b/include/configs/km8360.h @@ -36,7 +36,6 @@ * High Level Configuration Options */ #define CONFIG_QE /* Has QE */ -#define CONFIG_MPC8360 /* MPC8360 CPU specific */ /* include common defines/options for all 83xx Keymile boards */ #include "km/km83xx-common.h" diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index 6552d0e3c5c..022771fff5d 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -12,7 +12,7 @@ #define __IMMAP_QE_H__ #ifdef CONFIG_MPC83xx -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) #define QE_MURAM_SIZE 0xc000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index feb8fef6018..94b2816a821 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -191,7 +191,7 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001 -#elif defined(CONFIG_MPC8360) +#elif defined(CONFIG_ARCH_MPC8360) /* SICRL bits - MPC8360 specific */ #define SICRL_LDP_A 0xC0000000 #define SICRL_LCLK_1 0x10000000 @@ -593,7 +593,7 @@ #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 -#if defined(CONFIG_MPC8360) || defined(CONFIG_ARCH_MPC832X) +#if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X) #define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 @@ -735,7 +735,7 @@ #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 -#elif defined(CONFIG_MPC8360) +#elif defined(CONFIG_ARCH_MPC8360) #define HRCWH_PCICKDRV_DISABLE 0x00000000 #define HRCWH_PCICKDRV_ENABLE 0x10000000 #endif @@ -801,7 +801,7 @@ #define HRCWH_TSEC2M_IN_TBI 0x00003000 #endif -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 #endif @@ -1129,7 +1129,7 @@ #elif defined(CONFIG_ARCH_MPC832X) #define CSCONFIG_ODT_RD_CFG 0x00400000 #define CSCONFIG_ODT_WR_CFG 0x00040000 -#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_MPC837x) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 diff --git a/include/post.h b/include/post.h index 08a771e4055..eb218acde5f 100644 --- a/include/post.h +++ b/include/post.h @@ -21,7 +21,7 @@ #define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR #else -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) #include #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 5cae6d81f27..7b30903395f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1224,7 +1224,6 @@ CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB CONFIG_MPC832XEMDS CONFIG_MPC8349ITX -CONFIG_MPC8360 CONFIG_MPC837XEMDS CONFIG_MPC837XERDB CONFIG_MPC837x -- cgit v1.3.1 From 8439e99ddb54872f124b86f671d10d8a66cf9693 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:29 +0100 Subject: mpc83xx: Introduce ARCH_MPC837X Replace CONFIG_MPC837x with a proper CONFIG_ARCH_MPC837X Kconfig option. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 5 +++++ arch/powerpc/cpu/mpc83xx/speed.c | 30 ++++++++++++++-------------- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 2 +- arch/powerpc/include/asm/global_data.h | 6 +++--- arch/powerpc/include/asm/immap_83xx.h | 2 +- arch/powerpc/include/asm/mpc8xxx_spi.h | 2 +- drivers/ram/mpc83xx_sdram.c | 8 ++++---- include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/mpc83xx.h | 24 +++++++++++----------- scripts/config_whitelist.txt | 1 - 11 files changed, 42 insertions(+), 40 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 5f9d036e371..e41f4d1f9a3 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -64,12 +64,14 @@ config TARGET_MPC8349ITX config TARGET_MPC837XEMDS bool "Support MPC837XEMDS" + select ARCH_MPC837X select BOARD_EARLY_INIT_F imply CMD_SATA imply FSL_SATA config TARGET_MPC837XERDB bool "Support MPC837XERDB" + select ARCH_MPC837X select BOARD_EARLY_INIT_F config TARGET_IDS8313 @@ -151,6 +153,9 @@ config ARCH_MPC8349 config ARCH_MPC8360 bool +config ARCH_MPC837X + bool + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index ed77675a8ea..668ed27862b 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -86,7 +86,7 @@ int get_clocks(void) u32 csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; @@ -123,11 +123,11 @@ int get_clocks(void) u32 brg_clk; #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) u32 pciexp1_clk; u32 pciexp2_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; #endif @@ -156,7 +156,7 @@ int get_clocks(void) sccr = im->clk.sccr; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -177,7 +177,7 @@ int get_clocks(void) #endif #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: usbdr_clk = 0; @@ -198,7 +198,7 @@ int get_clocks(void) #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: tsec2_clk = 0; @@ -321,7 +321,7 @@ int get_clocks(void) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; -#elif defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC837X) i2c1_clk = enc_clk; #elif defined(CONFIG_ARCH_MPC8309) i2c1_clk = csb_clk; @@ -331,7 +331,7 @@ int get_clocks(void) #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: pciexp1_clk = 0; @@ -369,7 +369,7 @@ int get_clocks(void) } #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { case 0: sata_clk = 0; @@ -449,7 +449,7 @@ int get_clocks(void) gd->arch.csb_clk = csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; gd->arch.usbdr_clk = usbdr_clk; @@ -484,11 +484,11 @@ int get_clocks(void) gd->arch.brg_clk = brg_clk; #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) gd->arch.pciexp1_clk = pciexp1_clk; gd->arch.pciexp2_clk = pciexp2_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) gd->arch.sata_clk = sata_clk; #endif gd->pci_clk = pci_sync_in; @@ -559,7 +559,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.sdhc_clk)); #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->arch.tsec1_clk)); printf(" TSEC2: %-4s MHz\n", @@ -575,13 +575,13 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.usbmph_clk)); #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->arch.pciexp1_clk)); printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->arch.pciexp2_clk)); #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) printf(" SATA: %-4s MHz\n", strmhz(buf, gd->arch.sata_clk)); #endif diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 16997316ff0..b5ec50ba44c 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -9,7 +9,7 @@ #if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8315) #define MPC83XX_GPIO_CTRLRS 1 -#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) #define MPC83XX_GPIO_CTRLRS 2 #else #define MPC83XX_GPIO_CTRLRS 0 diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index cf3ba588220..b6e4dd6c807 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -36,7 +36,7 @@ struct arch_global_data { /* There are other clocks in the MPC83XX */ u32 csb_clk; # if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; @@ -54,11 +54,11 @@ struct arch_global_data { u32 lbiu_clk; u32 lclk_clk; # if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) u32 pciexp1_clk; u32 pciexp2_clk; # endif -# if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; # endif # if defined(CONFIG_ARCH_MPC8360) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index f6721e7b1d5..30bbd5671ba 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -759,7 +759,7 @@ typedef struct immap { u8 res12[0x1CF00]; } immap_t; -#elif defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC837X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 0c2bdb326b2..b583a3269d6 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -14,7 +14,7 @@ defined(CONFIG_ARCH_MPC8313) || \ defined(CONFIG_ARCH_MPC8315) || \ defined(CONFIG_ARCH_MPC834X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) typedef struct spi8xxx { u8 res0[0x20]; /* 0x0-0x01f reserved */ diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index 3e57b13118c..f03d0428b2a 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -170,7 +170,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) switch (odt_rd_cfg) { case ODT_RD_ONLY_OTHER_DIMM: if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_MPC837x)) { + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); return -EINVAL; @@ -182,7 +182,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && !IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_MPC837x)) { + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); return -EINVAL; @@ -201,7 +201,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) switch (odt_wr_cfg) { case ODT_WR_ONLY_OTHER_DIMM: if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_MPC837x)) { + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); return -EINVAL; @@ -213,7 +213,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && !IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_MPC837x)) { + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); return -EINVAL; diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 50f6df5844b..82dcb859736 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -11,7 +11,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ /* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 4ddd62ddbbc..6029d0f21bf 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -12,7 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XERDB 1 #define CONFIG_HWCONFIG diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 94b2816a821..c2a185321ab 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -130,8 +130,8 @@ #define SPCR_TSEC2EP_SHIFT (31-31) #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) -/* SPCR bits - MPC8308, MPC831x and MPC837x specific */ + defined(CONFIG_ARCH_MPC837X) +/* SPCR bits - MPC8308, MPC831x and MPC837X specific */ /* TSEC data priority */ #define SPCR_TSECDP 0x00003000 #define SPCR_TSECDP_SHIFT (31-19) @@ -283,8 +283,8 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001 -#elif defined(CONFIG_MPC837x) -/* SICRL bits - MPC837x specific */ +#elif defined(CONFIG_ARCH_MPC837X) +/* SICRL bits - MPC837X specific */ #define SICRL_USB_A 0xC0000000 #define SICRL_USB_B 0x30000000 #define SICRL_USB_B_SD 0x20000000 @@ -314,7 +314,7 @@ #define SICRL_LDP_A 0x00000002 #define SICRL_LDP_B 0x00000001 -/* SICRH bits - MPC837x specific */ +/* SICRH bits - MPC837X specific */ #define SICRH_DDR 0x80000000 #define SICRH_TSEC1_A 0x10000000 #define SICRH_TSEC1_B 0x08000000 @@ -647,7 +647,7 @@ #define HRCWL_SVCOD_DIV_8 0x20000000 #define HRCWL_SVCOD_DIV_1 0x30000000 -#elif defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC837X) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_4 0x00000000 @@ -758,7 +758,7 @@ #if defined(CONFIG_ARCH_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif -#if defined(CONFIG_MPC837x) +#if defined(CONFIG_ARCH_MPC837X) #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 #endif #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 @@ -766,7 +766,7 @@ #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 @@ -819,7 +819,7 @@ * RSR - Reset Status Register */ #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 #else @@ -1032,8 +1032,8 @@ #define SCCR_TDMCM_2 0x00000020 #define SCCR_TDMCM_3 0x00000030 -#elif defined(CONFIG_MPC837x) -/* SCCR bits - MPC837x specific */ +#elif defined(CONFIG_ARCH_MPC837X) +/* SCCR bits - MPC837X specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC1CM_0 0x00000000 @@ -1129,7 +1129,7 @@ #elif defined(CONFIG_ARCH_MPC832X) #define CSCONFIG_ODT_RD_CFG 0x00400000 #define CSCONFIG_ODT_WR_CFG 0x00040000 -#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 7b30903395f..761cdf6748c 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1226,7 +1226,6 @@ CONFIG_MPC832XEMDS CONFIG_MPC8349ITX CONFIG_MPC837XEMDS CONFIG_MPC837XERDB -CONFIG_MPC837x CONFIG_MPC83XX_GPIO CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN -- cgit v1.3.1 From c2a446048e7682296b8054ed81e12639099d5a56 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:37 +0100 Subject: vme8349: Migrate to CONFIG_TARGET_VME8349 CONFIG_TARGET_VME8349 can replace CONFIG_VME8349. Hence, replace CONFIG_VME8349 with CONFIG_TARGET_VME8349, and remove CONFIG_VME8349. Signed-off-by: Mario Six --- drivers/pci/pci_auto.c | 2 +- drivers/pci/pci_auto_old.c | 2 +- include/configs/vme8349.h | 1 - 3 files changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index a673d8ae136..f5e46842bf6 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -359,7 +359,7 @@ int dm_pciauto_config_device(struct udevice *dev) PCI_DEV(dm_pci_get_bdf(dev))); break; #endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c index 90c22a08cbc..6ab1b3b43fc 100644 --- a/drivers/pci/pci_auto_old.c +++ b/drivers/pci/pci_auto_old.c @@ -376,7 +376,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) PCI_DEV(dev)); break; #endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 56955501309..fe570abf8f7 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -28,7 +28,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_VME8349 1 /* ESD VME8349 board specific */ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -- cgit v1.3.1 From 904c47fc7d09c33fb4e43f30ddf2039fa7a0a168 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:38 +0100 Subject: mpc83xx: Make distinct caddy2 config vme8349.h contains two separate boards: The vme8349 itself, and the caddy2 board. The caddy2 board is chosen by setting certain config variables. Create a proper config file for the caddy2 board to make Kconfig migration easier. Furthermore, simplify the vme8349 and caddy2 configs by keeping only the options necessary for each board. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 4 + board/esd/vme8349/Kconfig | 13 + board/esd/vme8349/vme8349.c | 8 +- configs/caddy2_defconfig | 3 +- drivers/pci/pci_auto.c | 3 +- drivers/pci/pci_auto_old.c | 3 +- include/configs/caddy2.h | 512 +++++++++++++++++++++++++++++++++++++++ include/configs/vme8349.h | 29 --- 8 files changed, 538 insertions(+), 37 deletions(-) create mode 100644 include/configs/caddy2.h (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index ede98c70da7..65f4583ffea 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -24,6 +24,10 @@ config TARGET_VME8349 bool "Support vme8349" select ARCH_MPC8349 +config TARGET_CADDY2 + bool "Support caddy2" + select ARCH_MPC8349 + config TARGET_MPC8308RDB bool "Support MPC8308RDB" select ARCH_MPC8308 diff --git a/board/esd/vme8349/Kconfig b/board/esd/vme8349/Kconfig index b8d9432dcc9..ef2af40f7e8 100644 --- a/board/esd/vme8349/Kconfig +++ b/board/esd/vme8349/Kconfig @@ -10,3 +10,16 @@ config SYS_CONFIG_NAME default "vme8349" endif + +if TARGET_CADDY2 + +config SYS_BOARD + default "vme8349" + +config SYS_VENDOR + default "esd" + +config SYS_CONFIG_NAME + default "caddy2" + +endif diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index 45ad3a83ee8..a46d0b6da63 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -60,7 +60,7 @@ int dram_init(void) int checkboard(void) { -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 puts("Board: esd VME-CADDY/2\n"); #else puts("Board: esd VME-CPU/8349\n"); @@ -69,7 +69,7 @@ int checkboard(void) return 0; } -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 int board_eth_init(bd_t *bis) { return pci_eth_init(bis); @@ -102,7 +102,7 @@ int misc_init_r() * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2 * and VME-CADDY/2) have different SDRAM configurations. */ -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 #define SMALL_RAM 0xff #define LARGE_RAM 0x00 #else @@ -165,7 +165,7 @@ static spd_eeprom_t default_spd_eeprom = { SPD_VAL(0x7e, 0x1d), /* 63 */ { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' }, SPD_VAL(0x00, 0x00), /* 72 */ -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 { "vme-caddy/2 ram " } #else { "vme-cpu/2 ram " } diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 5fec4f8d499..fe0c34fc61a 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_MPC83xx=y -CONFIG_TARGET_VME8349=y +CONFIG_TARGET_CADDY2=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="CADDY2" CONFIG_BOOTDELAY=6 CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index f5e46842bf6..1a3bf708347 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -359,7 +359,8 @@ int dm_pciauto_config_device(struct udevice *dev) PCI_DEV(dm_pci_get_bdf(dev))); break; #endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \ + !defined(CONFIG_TARGET_CADDY2) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c index 6ab1b3b43fc..b566705c9d9 100644 --- a/drivers/pci/pci_auto_old.c +++ b/drivers/pci/pci_auto_old.c @@ -376,7 +376,8 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) PCI_DEV(dev)); break; #endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \ + !defined(CONFIG_TARGET_CADDY2) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h new file mode 100644 index 00000000000..a7bbbbdd0b3 --- /dev/null +++ b/include/configs/caddy2.h @@ -0,0 +1,512 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * esd vme8349 U-Boot configuration file + * Copyright (c) 2008, 2009 esd gmbh Hannover Germany + * + * (C) Copyright 2006-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * reinhard.arlt@esd-electronics.de + * Based on the MPC8349EMDS config. + */ + +/* + * vme8349 board configuration file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ + +/* Don't enable PCI2 on vme834x - it doesn't exist physically. */ +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ + +#define CONFIG_PCI_66M +#ifdef CONFIG_PCI_66M +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_PCI_66M +#define CONFIG_SYS_CLK_FREQ 66000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 +#else +#define CONFIG_SYS_CLK_FREQ 33000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 +#endif +#endif + +#define CONFIG_SYS_IMMR 0xE0000000 + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00100000 + +/* + * DDR Setup + */ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_READ_SPD vme8349_read_spd +#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ + | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) +#define CONFIG_DDR_2T_TIMING +#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x80080001 */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16bit */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) /* valid */ + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xffc06ff7 */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) + +#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ + | BR_PS_32 \ + | BR_MS_GPCM \ + | BR_V) + /* 0xF0001801 */ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ + | OR_GPCM_SETA) + /* 0xfffc0208 */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: no DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ + +#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ + +/* TSEC */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 +#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE +#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define PCI_64BIT +#define PCI_ONE_PCI1 +#if defined(PCI_64BIT) +#undef PCI_ALL_PCI1 +#undef PCI_TWO_PCI1 +#undef PCI_ONE_PCI1 +#endif + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0xFIXME +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_GMII /* MII PHY management */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_PHY_M88E1111 +#define TSEC1_PHY_ADDR 0x08 +#define TSEC2_PHY_ADDR 0x10 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#ifndef CONFIG_SYS_RAMBOOT + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CONFIG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Command line configuration. + */ +#define CONFIG_SYS_RTC_BUS_NUM 0x01 +#define CONFIG_SYS_I2C_RTC_ADDR 0x32 +#define CONFIG_RTC_RX8025 + +/* Pass Ethernet MAC to VxWorks */ +#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) + +#if defined(PCI_64BIT) +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII) +#else +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII) +#endif + +/* System IO Config */ +#define CONFIG_SYS_SICRH 0 +#define CONFIG_SYS_SICRL SICRL_LDP_A + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) + +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_SYS_GPIO1_PRELIM +#define CONFIG_SYS_GPIO1_DIR 0x00100000 +#define CONFIG_SYS_GPIO1_DAT 0x00100000 + +#define CONFIG_SYS_GPIO2_PRELIM +#define CONFIG_SYS_GPIO2_DIR 0x78900000 +#define CONFIG_SYS_GPIO2_DAT 0x70100000 + +#define CONFIG_HIGH_BATS /* High BATs supported */ + +/* DDR @ 0x00000000 */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#else +#define CONFIG_SYS_IBAT1L (0) +#define CONFIG_SYS_IBAT1U (0) +#define CONFIG_SYS_IBAT2L (0) +#define CONFIG_SYS_IBAT2U (0) +#endif + +#ifdef CONFIG_MPC83XX_PCI2 +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#else +#define CONFIG_SYS_IBAT3L (0) +#define CONFIG_SYS_IBAT3U (0) +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) +#endif + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ + BATU_VS | BATU_VP) + +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#if (CONFIG_SYS_DDR_SIZE == 512) +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ + BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ + BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#endif + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_HOSTNAME "VME8349" +#define CONFIG_ROOTPATH "/tftpboot/rootfs" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=vme8349\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ + "update=protect off fff00000 fff3ffff; " \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "upd=run load update\0" \ + "fdtaddr=780000\0" \ + "fdtfile=vme8349.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#ifndef __ASSEMBLY__ +int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index fe570abf8f7..6c3ad76e524 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -17,13 +17,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * Top level Makefile configuration choices - */ -#ifdef CONFIG_CADDY2 -#define VME_CADDY2 -#endif - /* * High Level Configuration Options */ @@ -91,27 +84,6 @@ /* * FLASH on the Local Bus */ -#ifdef VME_CADDY2 -#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16bit */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) /* valid */ - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffc06ff7 */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) -#else #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ @@ -131,7 +103,6 @@ /* 0xf8006ff7 */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) -#endif #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ -- cgit v1.3.1 From fe7d654d04a4ba87813dcf8acb7a17373029770d Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:03 +0100 Subject: mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to Kconfig Migrate the BR/OR settings to Kconfig. These must be known at compile time, so cannot be configured via DT. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 1 + arch/powerpc/cpu/mpc83xx/elbc/Kconfig | 32 ++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 | 733 ++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 | 733 ++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 | 733 ++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 | 733 ++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 | 733 ++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/elbc.h | 186 +++++++ arch/powerpc/cpu/mpc83xx/spl_minimal.c | 1 + arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 4 + board/freescale/mpc8349itx/mpc8349itx.c | 1 + configs/MPC8308RDB_defconfig | 38 ++ configs/MPC8313ERDB_33_defconfig | 50 ++ configs/MPC8313ERDB_66_defconfig | 50 ++ configs/MPC8313ERDB_NAND_33_defconfig | 50 ++ configs/MPC8313ERDB_NAND_66_defconfig | 50 ++ configs/MPC8315ERDB_defconfig | 27 + configs/MPC8323ERDB_defconfig | 14 + configs/MPC832XEMDS_ATM_defconfig | 53 ++ configs/MPC832XEMDS_HOST_33_defconfig | 53 ++ configs/MPC832XEMDS_HOST_66_defconfig | 53 ++ configs/MPC832XEMDS_SLAVE_defconfig | 53 ++ configs/MPC832XEMDS_defconfig | 53 ++ configs/MPC8349EMDS_PCI64_defconfig | 24 + configs/MPC8349EMDS_SDRAM_defconfig | 27 + configs/MPC8349EMDS_SLAVE_defconfig | 24 + configs/MPC8349EMDS_defconfig | 24 + configs/MPC8349ITXGP_defconfig | 47 ++ configs/MPC8349ITX_LOWBOOT_defconfig | 47 ++ configs/MPC8349ITX_defconfig | 47 ++ configs/MPC837XEMDS_HOST_defconfig | 41 ++ configs/MPC837XEMDS_SLAVE_defconfig | 41 ++ configs/MPC837XEMDS_defconfig | 41 ++ configs/MPC837XERDB_SLAVE_defconfig | 36 ++ configs/MPC837XERDB_defconfig | 36 ++ configs/TQM834x_defconfig | 10 + configs/caddy2_defconfig | 21 + configs/hrcon_defconfig | 26 + configs/hrcon_dh_defconfig | 26 + configs/ids8313_defconfig | 45 ++ configs/kmcoge5ne_defconfig | 42 ++ configs/kmeter1_defconfig | 32 ++ configs/kmopti2_defconfig | 42 ++ configs/kmsupx5_defconfig | 34 ++ configs/kmtegr1_defconfig | 30 ++ configs/kmtepr2_defconfig | 42 ++ configs/kmvect1_defconfig | 37 ++ configs/mpc8308_p1m_defconfig | 29 ++ configs/sbc8349_PCI_33_defconfig | 14 + configs/sbc8349_PCI_66_defconfig | 14 + configs/sbc8349_defconfig | 14 + configs/strider_con_defconfig | 23 + configs/strider_con_dp_defconfig | 23 + configs/strider_cpu_defconfig | 23 + configs/strider_cpu_dp_defconfig | 23 + configs/suvd3_defconfig | 37 ++ configs/tuge1_defconfig | 34 ++ configs/tuxx1_defconfig | 45 ++ configs/ve8313_defconfig | 45 ++ configs/vme8349_defconfig | 21 + drivers/mtd/nand/raw/fsl_elbc_spl.c | 4 + include/configs/MPC8308RDB.h | 9 - include/configs/MPC8313ERDB_NAND.h | 14 - include/configs/MPC8313ERDB_NOR.h | 14 - include/configs/MPC8315ERDB.h | 6 - include/configs/MPC8323ERDB.h | 3 - include/configs/MPC832XEMDS.h | 12 - include/configs/MPC8349EMDS.h | 6 - include/configs/MPC8349EMDS_SDRAM.h | 12 - include/configs/MPC8349ITX.h | 12 - include/configs/MPC837XEMDS.h | 9 - include/configs/MPC837XERDB.h | 9 - include/configs/TQM834x.h | 3 - include/configs/caddy2.h | 6 - include/configs/hrcon.h | 6 - include/configs/ids8313.h | 12 - include/configs/kmcoge5ne.h | 12 - include/configs/kmeter1.h | 9 - include/configs/kmopti2.h | 12 - include/configs/kmsupx5.h | 9 - include/configs/kmtegr1.h | 9 - include/configs/kmtepr2.h | 12 - include/configs/kmvect1.h | 12 - include/configs/mpc8308_p1m.h | 9 - include/configs/sbc8349.h | 3 - include/configs/strider.h | 6 - include/configs/suvd3.h | 12 - include/configs/tuge1.h | 9 - include/configs/tuxx1.h | 12 - include/configs/ve8313.h | 12 - include/configs/vme8349.h | 6 - 92 files changed, 5606 insertions(+), 277 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/elbc.h (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 8c84196b978..474572f245e 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -285,6 +285,7 @@ config ARCH_MPC837X source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig" menu "Legacy options" diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 91451e7b304..5ce7b794b26 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -13,6 +13,7 @@ #endif #include "lblaw/lblaw.h" +#include "elbc/elbc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig new file mode 100644 index 00000000000..74c4ff3ed43 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig @@ -0,0 +1,32 @@ +menu "ELBC register setup" + +choice + prompt "OR/BR for NAND SPL" + +config ELBC_BR_OR_NAND_PRELIM_NONE + bool "None" + +config ELBC_BR_OR_NAND_PRELIM_0 + bool "0" + +config ELBC_BR_OR_NAND_PRELIM_1 + bool "1" + +config ELBC_BR_OR_NAND_PRELIM_2 + bool "2" + +config ELBC_BR_OR_NAND_PRELIM_3 + bool "3" + +config ELBC_BR_OR_NAND_PRELIM_4 + bool "4" + +endchoice + +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4" + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 new file mode 100644 index 00000000000..23e81ab0bf9 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR0_OR0 + bool "ELBC BR0/OR0" + +if ELBC_BR0_OR0 + +config BR0_OR0_NAME + string "Identifier" + +config BR0_OR0_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR0_PORTSIZE_8BIT + bool "8-bit" + +config BR0_PORTSIZE_16BIT + depends on !BR0_MACHINE_FCM + bool "16-bit" + + +config BR0_PORTSIZE_32BIT + depends on !BR0_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR0_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR0_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR0_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR0_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR0_WRITE_PROTECT + bool "Write-protect" + +config BR0_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR0_MACHINE_GPCM + bool "GPCM" + +config BR0_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR0_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR0_MACHINE_UPMA + select BR0_MACHINE_UPM + bool "UPM (A)" + +config BR0_MACHINE_UPMB + select BR0_MACHINE_UPM + bool "UPM (B)" + +config BR0_MACHINE_UPMC + select BR0_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR0_ATOMIC_NONE + bool "No atomic operations" + +config BR0_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR0_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR0_MACHINE_GPCM || BR0_MACHINE_FCM || BR0_MACHINE_UPM || BR0_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR0_AM_32_KBYTES + depends on !BR0_MACHINE_SDRAM + bool "32 kb" + +config OR0_AM_64_KBYTES + bool "64 kb" + +config OR0_AM_128_KBYTES + bool "128 kb" + +config OR0_AM_256_KBYTES + bool "256 kb" + +config OR0_AM_512_KBYTES + bool "512 kb" + +config OR0_AM_1_MBYTES + bool "1 mb" + +config OR0_AM_2_MBYTES + bool "2 mb" + +config OR0_AM_4_MBYTES + bool "4 mb" + +config OR0_AM_8_MBYTES + bool "8 mb" + +config OR0_AM_16_MBYTES + bool "16 mb" + +config OR0_AM_32_MBYTES + bool "32 mb" + +config OR0_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR0_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR0_AM_256_MBYTES + bool "256 mb" + +config OR0_AM_512_MBYTES + depends on BR0_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR0_AM_1_GBYTES + bool "1 gb" + +config OR0_AM_2_GBYTES + depends on BR0_MACHINE_FCM + bool "2 gb" + +config OR0_AM_4_GBYTES + depends on BR0_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR0_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR0_BCTLD_ASSERTED + bool "Asserted" + +config OR0_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR0_MACHINE_GPCM || BR0_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR0_SCY_0 + bool "No wait states" + +config OR0_SCY_1 + bool "1 wait state" + +config OR0_SCY_2 + bool "2 wait states" + +config OR0_SCY_3 + bool "3 wait states" + +config OR0_SCY_4 + bool "4 wait states" + +config OR0_SCY_5 + bool "5 wait states" + +config OR0_SCY_6 + bool "6 wait states" + +config OR0_SCY_7 + bool "7 wait states" + +config OR0_SCY_8 + depends on BR0_MACHINE_GPCM + bool "8 wait states" + +config OR0_SCY_9 + depends on BR0_MACHINE_GPCM + bool "9 wait states" + +config OR0_SCY_10 + depends on BR0_MACHINE_GPCM + bool "10 wait states" + +config OR0_SCY_11 + depends on BR0_MACHINE_GPCM + bool "11 wait states" + +config OR0_SCY_12 + depends on BR0_MACHINE_GPCM + bool "12 wait states" + +config OR0_SCY_13 + depends on BR0_MACHINE_GPCM + bool "13 wait states" + +config OR0_SCY_14 + depends on BR0_MACHINE_GPCM + bool "14 wait states" + +config OR0_SCY_15 + depends on BR0_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR0_MACHINE_GPCM || BR0_MACHINE_FCM + +if BR0_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR0_CSNT_NORMAL + bool "Normal" + +config OR0_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR0_ACS_SAME_TIME + bool "At the same time" + +config OR0_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR0_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR0_XACS_NORMAL + bool "Normal" + +config OR0_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR0_SETA_INTERNAL + bool "Access is terminated internally" + +config OR0_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR0_MACHINE_GPCM + +if BR0_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR0_PGS_SMALL + bool "Small page device" + +config OR0_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR0_CSCT_1_CYCLE + depends on OR0_TRLX_NORMAL + bool "1 cycle" + +config OR0_CSCT_2_CYCLE + depends on OR0_TRLX_RELAXED + bool "2 cycles" + +config OR0_CSCT_4_CYCLE + depends on OR0_TRLX_NORMAL + bool "4 cycles" + +config OR0_CSCT_8_CYCLE + depends on OR0_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR0_CST_COINCIDENT + depends on OR0_TRLX_NORMAL + bool "Coincident with any command" + +config OR0_CST_QUARTER_CLOCK + depends on OR0_TRLX_NORMAL + bool "0.25 clocks after" + +config OR0_CST_HALF_CLOCK + depends on OR0_TRLX_RELAXED + bool "0.5 clocks after" + +config OR0_CST_ONE_CLOCK + depends on OR0_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR0_CHT_HALF_CLOCK + depends on OR0_TRLX_NORMAL + bool "0.5 clocks before" + +config OR0_CHT_ONE_CLOCK + depends on OR0_TRLX_NORMAL + bool "1 clock before" + +config OR0_CHT_ONE_HALF_CLOCK + depends on OR0_TRLX_RELAXED + bool "1.5 clocks before" + +config OR0_CHT_TWO_CLOCK + depends on OR0_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR0_RST_THREE_QUARTER_CLOCK + depends on OR0_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR0_RST_ONE_HALF_CLOCK + depends on OR0_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR0_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR0_MACHINE_FCM + +if BR0_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR0_BI_BURSTSUPPORT + bool "Support burst access" + +config OR0_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR0_MACHINE_UPM + +if BR0_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR0_COLS_7 + bool "7" + +config OR0_COLS_8 + bool "8" + +config OR0_COLS_9 + bool "9" + +config OR0_COLS_10 + bool "10" + +config OR0_COLS_11 + bool "11" + +config OR0_COLS_12 + bool "12" + +config OR0_COLS_13 + bool "13" + +config OR0_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR0_ROWS_9 + bool "9" + +config OR0_ROWS_10 + bool "10" + +config OR0_ROWS_11 + bool "11" + +config OR0_ROWS_12 + bool "12" + +config OR0_ROWS_13 + bool "13" + +config OR0_ROWS_14 + bool "14" + +config OR0_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR0_PMSEL_BTB + bool "Back-to-back" + +config OR0_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR0_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR0_TRLX_NORMAL + bool "Normal" + +config OR0_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR0_EHTR_NORMAL + depends on OR0_TRLX_NORMAL + bool "Normal" + +config OR0_EHTR_1_CYCLE + depends on OR0_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR0_EHTR_4_CYCLE + depends on OR0_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR0_EHTR_8_CYCLE + depends on OR0_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR0_EAD_NONE + bool "None" + +config OR0_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR0_OR0 + +config BR0_PORTSIZE + hex + default 0x800 if BR0_PORTSIZE_8BIT + default 0x1000 if BR0_PORTSIZE_16BIT + default 0x1800 if BR0_PORTSIZE_32BIT + +config BR0_ERRORCHECKING + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if BR0_ERRORCHECKING_DISABLED + default 0x200 if BR0_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR0_ERRORCHECKING_BOTH + +config BR0_WRITE_PROTECT_BIT + hex + default 0x0 if !BR0_WRITE_PROTECT + default 0x100 if BR0_WRITE_PROTECT + +config BR0_MACHINE + hex + default 0x0 if BR0_MACHINE_GPCM + default 0x20 if BR0_MACHINE_FCM + default 0x60 if BR0_MACHINE_SDRAM + default 0x80 if BR0_MACHINE_UPMA + default 0xa0 if BR0_MACHINE_UPMB + default 0xc0 if BR0_MACHINE_UPMC + +config BR0_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR0_ATOMIC_NONE + default 0x4 if BR0_ATOMIC_RAWA + default 0x8 if BR0_ATOMIC_WARA + +config BR0_VALID_BIT + hex + default 0x0 if !ELBC_BR0_OR0 + default 0x1 if ELBC_BR0_OR0 + +config OR0_AM + hex + default 0xffff8000 if OR0_AM_32_KBYTES && !BR0_MACHINE_SDRAM + default 0xffff0000 if OR0_AM_64_KBYTES + default 0xfffe0000 if OR0_AM_128_KBYTES + default 0xfffc0000 if OR0_AM_256_KBYTES + default 0xfff80000 if OR0_AM_512_KBYTES + default 0xfff00000 if OR0_AM_1_MBYTES + default 0xffe00000 if OR0_AM_2_MBYTES + default 0xffc00000 if OR0_AM_4_MBYTES + default 0xff800000 if OR0_AM_8_MBYTES + default 0xff000000 if OR0_AM_16_MBYTES + default 0xfe000000 if OR0_AM_32_MBYTES + default 0xfc000000 if OR0_AM_64_MBYTES + default 0xf8000000 if OR0_AM_128_MBYTES + default 0xf0000000 if OR0_AM_256_MBYTES + default 0xe0000000 if OR0_AM_512_MBYTES + default 0xc0000000 if OR0_AM_1_GBYTES + default 0x80000000 if OR0_AM_2_GBYTES + default 0x00000000 if OR0_AM_4_GBYTES + +config OR0_XAM + hex + default 0x0 if !OR0_XAM_SET + default 0x6000 if OR0_XAM_SET + +config OR0_BCTLD + hex + default 0x0 if OR0_BCTLD_ASSERTED + default 0x1000 if OR0_BCTLD_NOT_ASSERTED + +config OR0_BI + hex + default 0x0 if !BR0_MACHINE_UPM + default 0x0 if OR0_BI_BURSTSUPPORT + default 0x100 if OR0_BI_BURSTINHIBIT + +config OR0_COLS + hex + default 0x0 if !BR0_MACHINE_SDRAM + default 0x0 if OR0_COLS_7 + default 0x400 if OR0_COLS_8 + default 0x800 if OR0_COLS_9 + default 0xc00 if OR0_COLS_10 + default 0x1000 if OR0_COLS_11 + default 0x1400 if OR0_COLS_12 + default 0x1800 if OR0_COLS_13 + default 0x1c00 if OR0_COLS_14 + +config OR0_ROWS + hex + default 0x0 if !BR0_MACHINE_SDRAM + default 0x0 if OR0_ROWS_9 + default 0x40 if OR0_ROWS_10 + default 0x80 if OR0_ROWS_11 + default 0xc0 if OR0_ROWS_12 + default 0x100 if OR0_ROWS_13 + default 0x140 if OR0_ROWS_14 + default 0x180 if OR0_ROWS_15 + +config OR0_PMSEL + hex + default 0x0 if !BR0_MACHINE_SDRAM + default 0x0 if OR0_PMSEL_BTB + default 0x20 if OR0_PMSEL_KEPT_OPEN + +config OR0_SCY + hex + default 0x0 if !BR0_MACHINE_GPCM && !BR0_MACHINE_FCM + default 0x0 if OR0_SCY_0 + default 0x10 if OR0_SCY_1 + default 0x20 if OR0_SCY_2 + default 0x30 if OR0_SCY_3 + default 0x40 if OR0_SCY_4 + default 0x50 if OR0_SCY_5 + default 0x60 if OR0_SCY_6 + default 0x70 if OR0_SCY_7 + default 0x80 if OR0_SCY_8 + default 0x90 if OR0_SCY_9 + default 0xa0 if OR0_SCY_10 + default 0xb0 if OR0_SCY_11 + default 0xc0 if OR0_SCY_12 + default 0xd0 if OR0_SCY_13 + default 0xe0 if OR0_SCY_14 + default 0xf0 if OR0_SCY_15 + +config OR0_PGS + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_PGS_SMALL + default 0x400 if OR0_PGS_LARGE + +config OR0_CSCT + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_CSCT_1_CYCLE + default 0x0 if OR0_CSCT_2_CYCLE + default 0x200 if OR0_CSCT_4_CYCLE + default 0x200 if OR0_CSCT_8_CYCLE + +config OR0_CST + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_CST_COINCIDENT + default 0x100 if OR0_CST_QUARTER_CLOCK + default 0x0 if OR0_CST_HALF_CLOCK + default 0x100 if OR0_CST_ONE_CLOCK + +config OR0_CHT + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_CHT_HALF_CLOCK + default 0x80 if OR0_CHT_ONE_CLOCK + default 0x0 if OR0_CHT_ONE_HALF_CLOCK + default 0x80 if OR0_CHT_TWO_CLOCK + +config OR0_RST + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_RST_THREE_QUARTER_CLOCK + default 0x8 if OR0_RST_ONE_CLOCK + default 0x0 if OR0_RST_ONE_HALF_CLOCK + +config OR0_CSNT + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_CSNT_NORMAL + default 0x800 if OR0_CSNT_EARLIER + +config OR0_ACS + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_ACS_SAME_TIME + default 0x400 if OR0_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR0_ACS_HALF_CYCLE_EARLIER + +config OR0_XACS + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_XACS_NORMAL + default 0x100 if OR0_XACS_EXTENDED + +config OR0_SETA + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_SETA_INTERNAL + default 0x8 if OR0_SETA_EXTERNAL + +config OR0_TRLX + hex + default 0x0 if OR0_TRLX_NORMAL + default 0x4 if OR0_TRLX_RELAXED + +config OR0_EHTR + hex + default 0x0 if OR0_EHTR_NORMAL + default 0x2 if OR0_EHTR_1_CYCLE + default 0x0 if OR0_EHTR_4_CYCLE + default 0x2 if OR0_EHTR_8_CYCLE + +config OR0_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR0_EAD_NONE + default 0x1 if OR0_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 new file mode 100644 index 00000000000..08dcc7dd2ba --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR1_OR1 + bool "ELBC BR1/OR1" + +if ELBC_BR1_OR1 + +config BR1_OR1_NAME + string "Identifier" + +config BR1_OR1_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR1_PORTSIZE_8BIT + bool "8-bit" + +config BR1_PORTSIZE_16BIT + depends on !BR1_MACHINE_FCM + bool "16-bit" + + +config BR1_PORTSIZE_32BIT + depends on !BR1_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR1_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR1_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR1_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR1_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR1_WRITE_PROTECT + bool "Write-protect" + +config BR1_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR1_MACHINE_GPCM + bool "GPCM" + +config BR1_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR1_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR1_MACHINE_UPMA + select BR1_MACHINE_UPM + bool "UPM (A)" + +config BR1_MACHINE_UPMB + select BR1_MACHINE_UPM + bool "UPM (B)" + +config BR1_MACHINE_UPMC + select BR1_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR1_ATOMIC_NONE + bool "No atomic operations" + +config BR1_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR1_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR1_MACHINE_GPCM || BR1_MACHINE_FCM || BR1_MACHINE_UPM || BR1_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR1_AM_32_KBYTES + depends on !BR1_MACHINE_SDRAM + bool "32 kb" + +config OR1_AM_64_KBYTES + bool "64 kb" + +config OR1_AM_128_KBYTES + bool "128 kb" + +config OR1_AM_256_KBYTES + bool "256 kb" + +config OR1_AM_512_KBYTES + bool "512 kb" + +config OR1_AM_1_MBYTES + bool "1 mb" + +config OR1_AM_2_MBYTES + bool "2 mb" + +config OR1_AM_4_MBYTES + bool "4 mb" + +config OR1_AM_8_MBYTES + bool "8 mb" + +config OR1_AM_16_MBYTES + bool "16 mb" + +config OR1_AM_32_MBYTES + bool "32 mb" + +config OR1_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR1_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR1_AM_256_MBYTES + bool "256 mb" + +config OR1_AM_512_MBYTES + depends on BR1_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR1_AM_1_GBYTES + bool "1 gb" + +config OR1_AM_2_GBYTES + depends on BR1_MACHINE_FCM + bool "2 gb" + +config OR1_AM_4_GBYTES + depends on BR1_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR1_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR1_BCTLD_ASSERTED + bool "Asserted" + +config OR1_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR1_MACHINE_GPCM || BR1_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR1_SCY_0 + bool "No wait states" + +config OR1_SCY_1 + bool "1 wait state" + +config OR1_SCY_2 + bool "2 wait states" + +config OR1_SCY_3 + bool "3 wait states" + +config OR1_SCY_4 + bool "4 wait states" + +config OR1_SCY_5 + bool "5 wait states" + +config OR1_SCY_6 + bool "6 wait states" + +config OR1_SCY_7 + bool "7 wait states" + +config OR1_SCY_8 + depends on BR1_MACHINE_GPCM + bool "8 wait states" + +config OR1_SCY_9 + depends on BR1_MACHINE_GPCM + bool "9 wait states" + +config OR1_SCY_10 + depends on BR1_MACHINE_GPCM + bool "10 wait states" + +config OR1_SCY_11 + depends on BR1_MACHINE_GPCM + bool "11 wait states" + +config OR1_SCY_12 + depends on BR1_MACHINE_GPCM + bool "12 wait states" + +config OR1_SCY_13 + depends on BR1_MACHINE_GPCM + bool "13 wait states" + +config OR1_SCY_14 + depends on BR1_MACHINE_GPCM + bool "14 wait states" + +config OR1_SCY_15 + depends on BR1_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR1_MACHINE_GPCM || BR1_MACHINE_FCM + +if BR1_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR1_CSNT_NORMAL + bool "Normal" + +config OR1_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR1_ACS_SAME_TIME + bool "At the same time" + +config OR1_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR1_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR1_XACS_NORMAL + bool "Normal" + +config OR1_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR1_SETA_INTERNAL + bool "Access is terminated internally" + +config OR1_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR1_MACHINE_GPCM + +if BR1_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR1_PGS_SMALL + bool "Small page device" + +config OR1_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR1_CSCT_1_CYCLE + depends on OR1_TRLX_NORMAL + bool "1 cycle" + +config OR1_CSCT_2_CYCLE + depends on OR1_TRLX_RELAXED + bool "2 cycles" + +config OR1_CSCT_4_CYCLE + depends on OR1_TRLX_NORMAL + bool "4 cycles" + +config OR1_CSCT_8_CYCLE + depends on OR1_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR1_CST_COINCIDENT + depends on OR1_TRLX_NORMAL + bool "Coincident with any command" + +config OR1_CST_QUARTER_CLOCK + depends on OR1_TRLX_NORMAL + bool "0.25 clocks after" + +config OR1_CST_HALF_CLOCK + depends on OR1_TRLX_RELAXED + bool "0.5 clocks after" + +config OR1_CST_ONE_CLOCK + depends on OR1_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR1_CHT_HALF_CLOCK + depends on OR1_TRLX_NORMAL + bool "0.5 clocks before" + +config OR1_CHT_ONE_CLOCK + depends on OR1_TRLX_NORMAL + bool "1 clock before" + +config OR1_CHT_ONE_HALF_CLOCK + depends on OR1_TRLX_RELAXED + bool "1.5 clocks before" + +config OR1_CHT_TWO_CLOCK + depends on OR1_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR1_RST_THREE_QUARTER_CLOCK + depends on OR1_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR1_RST_ONE_HALF_CLOCK + depends on OR1_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR1_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR1_MACHINE_FCM + +if BR1_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR1_BI_BURSTSUPPORT + bool "Support burst access" + +config OR1_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR1_MACHINE_UPM + +if BR1_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR1_COLS_7 + bool "7" + +config OR1_COLS_8 + bool "8" + +config OR1_COLS_9 + bool "9" + +config OR1_COLS_10 + bool "10" + +config OR1_COLS_11 + bool "11" + +config OR1_COLS_12 + bool "12" + +config OR1_COLS_13 + bool "13" + +config OR1_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR1_ROWS_9 + bool "9" + +config OR1_ROWS_10 + bool "10" + +config OR1_ROWS_11 + bool "11" + +config OR1_ROWS_12 + bool "12" + +config OR1_ROWS_13 + bool "13" + +config OR1_ROWS_14 + bool "14" + +config OR1_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR1_PMSEL_BTB + bool "Back-to-back" + +config OR1_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR1_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR1_TRLX_NORMAL + bool "Normal" + +config OR1_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR1_EHTR_NORMAL + depends on OR1_TRLX_NORMAL + bool "Normal" + +config OR1_EHTR_1_CYCLE + depends on OR1_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR1_EHTR_4_CYCLE + depends on OR1_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR1_EHTR_8_CYCLE + depends on OR1_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR1_EAD_NONE + bool "None" + +config OR1_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR1_OR1 + +config BR1_PORTSIZE + hex + default 0x800 if BR1_PORTSIZE_8BIT + default 0x1000 if BR1_PORTSIZE_16BIT + default 0x1800 if BR1_PORTSIZE_32BIT + +config BR1_ERRORCHECKING + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if BR1_ERRORCHECKING_DISABLED + default 0x200 if BR1_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR1_ERRORCHECKING_BOTH + +config BR1_WRITE_PROTECT_BIT + hex + default 0x0 if !BR1_WRITE_PROTECT + default 0x100 if BR1_WRITE_PROTECT + +config BR1_MACHINE + hex + default 0x0 if BR1_MACHINE_GPCM + default 0x20 if BR1_MACHINE_FCM + default 0x60 if BR1_MACHINE_SDRAM + default 0x80 if BR1_MACHINE_UPMA + default 0xa0 if BR1_MACHINE_UPMB + default 0xc0 if BR1_MACHINE_UPMC + +config BR1_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR1_ATOMIC_NONE + default 0x4 if BR1_ATOMIC_RAWA + default 0x8 if BR1_ATOMIC_WARA + +config BR1_VALID_BIT + hex + default 0x0 if !ELBC_BR1_OR1 + default 0x1 if ELBC_BR1_OR1 + +config OR1_AM + hex + default 0xffff8000 if OR1_AM_32_KBYTES && !BR1_MACHINE_SDRAM + default 0xffff0000 if OR1_AM_64_KBYTES + default 0xfffe0000 if OR1_AM_128_KBYTES + default 0xfffc0000 if OR1_AM_256_KBYTES + default 0xfff80000 if OR1_AM_512_KBYTES + default 0xfff00000 if OR1_AM_1_MBYTES + default 0xffe00000 if OR1_AM_2_MBYTES + default 0xffc00000 if OR1_AM_4_MBYTES + default 0xff800000 if OR1_AM_8_MBYTES + default 0xff000000 if OR1_AM_16_MBYTES + default 0xfe000000 if OR1_AM_32_MBYTES + default 0xfc000000 if OR1_AM_64_MBYTES + default 0xf8000000 if OR1_AM_128_MBYTES + default 0xf0000000 if OR1_AM_256_MBYTES + default 0xe0000000 if OR1_AM_512_MBYTES + default 0xc0000000 if OR1_AM_1_GBYTES + default 0x80000000 if OR1_AM_2_GBYTES + default 0x00000000 if OR1_AM_4_GBYTES + +config OR1_XAM + hex + default 0x0 if !OR1_XAM_SET + default 0x6000 if OR1_XAM_SET + +config OR1_BCTLD + hex + default 0x0 if OR1_BCTLD_ASSERTED + default 0x1000 if OR1_BCTLD_NOT_ASSERTED + +config OR1_BI + hex + default 0x0 if !BR1_MACHINE_UPM + default 0x0 if OR1_BI_BURSTSUPPORT + default 0x100 if OR1_BI_BURSTINHIBIT + +config OR1_COLS + hex + default 0x0 if !BR1_MACHINE_SDRAM + default 0x0 if OR1_COLS_7 + default 0x400 if OR1_COLS_8 + default 0x800 if OR1_COLS_9 + default 0xc00 if OR1_COLS_10 + default 0x1000 if OR1_COLS_11 + default 0x1400 if OR1_COLS_12 + default 0x1800 if OR1_COLS_13 + default 0x1c00 if OR1_COLS_14 + +config OR1_ROWS + hex + default 0x0 if !BR1_MACHINE_SDRAM + default 0x0 if OR1_ROWS_9 + default 0x40 if OR1_ROWS_10 + default 0x80 if OR1_ROWS_11 + default 0xc0 if OR1_ROWS_12 + default 0x100 if OR1_ROWS_13 + default 0x140 if OR1_ROWS_14 + default 0x180 if OR1_ROWS_15 + +config OR1_PMSEL + hex + default 0x0 if !BR1_MACHINE_SDRAM + default 0x0 if OR1_PMSEL_BTB + default 0x20 if OR1_PMSEL_KEPT_OPEN + +config OR1_SCY + hex + default 0x0 if !BR1_MACHINE_GPCM && !BR1_MACHINE_FCM + default 0x0 if OR1_SCY_0 + default 0x10 if OR1_SCY_1 + default 0x20 if OR1_SCY_2 + default 0x30 if OR1_SCY_3 + default 0x40 if OR1_SCY_4 + default 0x50 if OR1_SCY_5 + default 0x60 if OR1_SCY_6 + default 0x70 if OR1_SCY_7 + default 0x80 if OR1_SCY_8 + default 0x90 if OR1_SCY_9 + default 0xa0 if OR1_SCY_10 + default 0xb0 if OR1_SCY_11 + default 0xc0 if OR1_SCY_12 + default 0xd0 if OR1_SCY_13 + default 0xe0 if OR1_SCY_14 + default 0xf0 if OR1_SCY_15 + +config OR1_PGS + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_PGS_SMALL + default 0x400 if OR1_PGS_LARGE + +config OR1_CSCT + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_CSCT_1_CYCLE + default 0x0 if OR1_CSCT_2_CYCLE + default 0x200 if OR1_CSCT_4_CYCLE + default 0x200 if OR1_CSCT_8_CYCLE + +config OR1_CST + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_CST_COINCIDENT + default 0x100 if OR1_CST_QUARTER_CLOCK + default 0x0 if OR1_CST_HALF_CLOCK + default 0x100 if OR1_CST_ONE_CLOCK + +config OR1_CHT + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_CHT_HALF_CLOCK + default 0x80 if OR1_CHT_ONE_CLOCK + default 0x0 if OR1_CHT_ONE_HALF_CLOCK + default 0x80 if OR1_CHT_TWO_CLOCK + +config OR1_RST + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_RST_THREE_QUARTER_CLOCK + default 0x8 if OR1_RST_ONE_CLOCK + default 0x0 if OR1_RST_ONE_HALF_CLOCK + +config OR1_CSNT + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_CSNT_NORMAL + default 0x800 if OR1_CSNT_EARLIER + +config OR1_ACS + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_ACS_SAME_TIME + default 0x400 if OR1_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR1_ACS_HALF_CYCLE_EARLIER + +config OR1_XACS + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_XACS_NORMAL + default 0x100 if OR1_XACS_EXTENDED + +config OR1_SETA + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_SETA_INTERNAL + default 0x8 if OR1_SETA_EXTERNAL + +config OR1_TRLX + hex + default 0x0 if OR1_TRLX_NORMAL + default 0x4 if OR1_TRLX_RELAXED + +config OR1_EHTR + hex + default 0x0 if OR1_EHTR_NORMAL + default 0x2 if OR1_EHTR_1_CYCLE + default 0x0 if OR1_EHTR_4_CYCLE + default 0x2 if OR1_EHTR_8_CYCLE + +config OR1_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR1_EAD_NONE + default 0x1 if OR1_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 new file mode 100644 index 00000000000..298d87f5e0f --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR2_OR2 + bool "ELBC BR2/OR2" + +if ELBC_BR2_OR2 + +config BR2_OR2_NAME + string "Identifier" + +config BR2_OR2_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR2_PORTSIZE_8BIT + bool "8-bit" + +config BR2_PORTSIZE_16BIT + depends on !BR2_MACHINE_FCM + bool "16-bit" + + +config BR2_PORTSIZE_32BIT + depends on !BR2_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR2_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR2_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR2_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR2_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR2_WRITE_PROTECT + bool "Write-protect" + +config BR2_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR2_MACHINE_GPCM + bool "GPCM" + +config BR2_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR2_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR2_MACHINE_UPMA + select BR2_MACHINE_UPM + bool "UPM (A)" + +config BR2_MACHINE_UPMB + select BR2_MACHINE_UPM + bool "UPM (B)" + +config BR2_MACHINE_UPMC + select BR2_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR2_ATOMIC_NONE + bool "No atomic operations" + +config BR2_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR2_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR2_MACHINE_GPCM || BR2_MACHINE_FCM || BR2_MACHINE_UPM || BR2_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR2_AM_32_KBYTES + depends on !BR2_MACHINE_SDRAM + bool "32 kb" + +config OR2_AM_64_KBYTES + bool "64 kb" + +config OR2_AM_128_KBYTES + bool "128 kb" + +config OR2_AM_256_KBYTES + bool "256 kb" + +config OR2_AM_512_KBYTES + bool "512 kb" + +config OR2_AM_1_MBYTES + bool "1 mb" + +config OR2_AM_2_MBYTES + bool "2 mb" + +config OR2_AM_4_MBYTES + bool "4 mb" + +config OR2_AM_8_MBYTES + bool "8 mb" + +config OR2_AM_16_MBYTES + bool "16 mb" + +config OR2_AM_32_MBYTES + bool "32 mb" + +config OR2_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR2_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR2_AM_256_MBYTES + bool "256 mb" + +config OR2_AM_512_MBYTES + depends on BR2_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR2_AM_1_GBYTES + bool "1 gb" + +config OR2_AM_2_GBYTES + depends on BR2_MACHINE_FCM + bool "2 gb" + +config OR2_AM_4_GBYTES + depends on BR2_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR2_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR2_BCTLD_ASSERTED + bool "Asserted" + +config OR2_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR2_MACHINE_GPCM || BR2_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR2_SCY_0 + bool "No wait states" + +config OR2_SCY_1 + bool "1 wait state" + +config OR2_SCY_2 + bool "2 wait states" + +config OR2_SCY_3 + bool "3 wait states" + +config OR2_SCY_4 + bool "4 wait states" + +config OR2_SCY_5 + bool "5 wait states" + +config OR2_SCY_6 + bool "6 wait states" + +config OR2_SCY_7 + bool "7 wait states" + +config OR2_SCY_8 + depends on BR2_MACHINE_GPCM + bool "8 wait states" + +config OR2_SCY_9 + depends on BR2_MACHINE_GPCM + bool "9 wait states" + +config OR2_SCY_10 + depends on BR2_MACHINE_GPCM + bool "10 wait states" + +config OR2_SCY_11 + depends on BR2_MACHINE_GPCM + bool "11 wait states" + +config OR2_SCY_12 + depends on BR2_MACHINE_GPCM + bool "12 wait states" + +config OR2_SCY_13 + depends on BR2_MACHINE_GPCM + bool "13 wait states" + +config OR2_SCY_14 + depends on BR2_MACHINE_GPCM + bool "14 wait states" + +config OR2_SCY_15 + depends on BR2_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR2_MACHINE_GPCM || BR2_MACHINE_FCM + +if BR2_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR2_CSNT_NORMAL + bool "Normal" + +config OR2_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR2_ACS_SAME_TIME + bool "At the same time" + +config OR2_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR2_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR2_XACS_NORMAL + bool "Normal" + +config OR2_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR2_SETA_INTERNAL + bool "Access is terminated internally" + +config OR2_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR2_MACHINE_GPCM + +if BR2_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR2_PGS_SMALL + bool "Small page device" + +config OR2_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR2_CSCT_1_CYCLE + depends on OR2_TRLX_NORMAL + bool "1 cycle" + +config OR2_CSCT_2_CYCLE + depends on OR2_TRLX_RELAXED + bool "2 cycles" + +config OR2_CSCT_4_CYCLE + depends on OR2_TRLX_NORMAL + bool "4 cycles" + +config OR2_CSCT_8_CYCLE + depends on OR2_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR2_CST_COINCIDENT + depends on OR2_TRLX_NORMAL + bool "Coincident with any command" + +config OR2_CST_QUARTER_CLOCK + depends on OR2_TRLX_NORMAL + bool "0.25 clocks after" + +config OR2_CST_HALF_CLOCK + depends on OR2_TRLX_RELAXED + bool "0.5 clocks after" + +config OR2_CST_ONE_CLOCK + depends on OR2_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR2_CHT_HALF_CLOCK + depends on OR2_TRLX_NORMAL + bool "0.5 clocks before" + +config OR2_CHT_ONE_CLOCK + depends on OR2_TRLX_NORMAL + bool "1 clock before" + +config OR2_CHT_ONE_HALF_CLOCK + depends on OR2_TRLX_RELAXED + bool "1.5 clocks before" + +config OR2_CHT_TWO_CLOCK + depends on OR2_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR2_RST_THREE_QUARTER_CLOCK + depends on OR2_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR2_RST_ONE_HALF_CLOCK + depends on OR2_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR2_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR2_MACHINE_FCM + +if BR2_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR2_BI_BURSTSUPPORT + bool "Support burst access" + +config OR2_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR2_MACHINE_UPM + +if BR2_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR2_COLS_7 + bool "7" + +config OR2_COLS_8 + bool "8" + +config OR2_COLS_9 + bool "9" + +config OR2_COLS_10 + bool "10" + +config OR2_COLS_11 + bool "11" + +config OR2_COLS_12 + bool "12" + +config OR2_COLS_13 + bool "13" + +config OR2_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR2_ROWS_9 + bool "9" + +config OR2_ROWS_10 + bool "10" + +config OR2_ROWS_11 + bool "11" + +config OR2_ROWS_12 + bool "12" + +config OR2_ROWS_13 + bool "13" + +config OR2_ROWS_14 + bool "14" + +config OR2_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR2_PMSEL_BTB + bool "Back-to-back" + +config OR2_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR2_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR2_TRLX_NORMAL + bool "Normal" + +config OR2_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR2_EHTR_NORMAL + depends on OR2_TRLX_NORMAL + bool "Normal" + +config OR2_EHTR_1_CYCLE + depends on OR2_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR2_EHTR_4_CYCLE + depends on OR2_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR2_EHTR_8_CYCLE + depends on OR2_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR2_EAD_NONE + bool "None" + +config OR2_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR2_OR2 + +config BR2_PORTSIZE + hex + default 0x800 if BR2_PORTSIZE_8BIT + default 0x1000 if BR2_PORTSIZE_16BIT + default 0x1800 if BR2_PORTSIZE_32BIT + +config BR2_ERRORCHECKING + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if BR2_ERRORCHECKING_DISABLED + default 0x200 if BR2_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR2_ERRORCHECKING_BOTH + +config BR2_WRITE_PROTECT_BIT + hex + default 0x0 if !BR2_WRITE_PROTECT + default 0x100 if BR2_WRITE_PROTECT + +config BR2_MACHINE + hex + default 0x0 if BR2_MACHINE_GPCM + default 0x20 if BR2_MACHINE_FCM + default 0x60 if BR2_MACHINE_SDRAM + default 0x80 if BR2_MACHINE_UPMA + default 0xa0 if BR2_MACHINE_UPMB + default 0xc0 if BR2_MACHINE_UPMC + +config BR2_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR2_ATOMIC_NONE + default 0x4 if BR2_ATOMIC_RAWA + default 0x8 if BR2_ATOMIC_WARA + +config BR2_VALID_BIT + hex + default 0x0 if !ELBC_BR2_OR2 + default 0x1 if ELBC_BR2_OR2 + +config OR2_AM + hex + default 0xffff8000 if OR2_AM_32_KBYTES && !BR2_MACHINE_SDRAM + default 0xffff0000 if OR2_AM_64_KBYTES + default 0xfffe0000 if OR2_AM_128_KBYTES + default 0xfffc0000 if OR2_AM_256_KBYTES + default 0xfff80000 if OR2_AM_512_KBYTES + default 0xfff00000 if OR2_AM_1_MBYTES + default 0xffe00000 if OR2_AM_2_MBYTES + default 0xffc00000 if OR2_AM_4_MBYTES + default 0xff800000 if OR2_AM_8_MBYTES + default 0xff000000 if OR2_AM_16_MBYTES + default 0xfe000000 if OR2_AM_32_MBYTES + default 0xfc000000 if OR2_AM_64_MBYTES + default 0xf8000000 if OR2_AM_128_MBYTES + default 0xf0000000 if OR2_AM_256_MBYTES + default 0xe0000000 if OR2_AM_512_MBYTES + default 0xc0000000 if OR2_AM_1_GBYTES + default 0x80000000 if OR2_AM_2_GBYTES + default 0x00000000 if OR2_AM_4_GBYTES + +config OR2_XAM + hex + default 0x0 if !OR2_XAM_SET + default 0x6000 if OR2_XAM_SET + +config OR2_BCTLD + hex + default 0x0 if OR2_BCTLD_ASSERTED + default 0x1000 if OR2_BCTLD_NOT_ASSERTED + +config OR2_BI + hex + default 0x0 if !BR2_MACHINE_UPM + default 0x0 if OR2_BI_BURSTSUPPORT + default 0x100 if OR2_BI_BURSTINHIBIT + +config OR2_COLS + hex + default 0x0 if !BR2_MACHINE_SDRAM + default 0x0 if OR2_COLS_7 + default 0x400 if OR2_COLS_8 + default 0x800 if OR2_COLS_9 + default 0xc00 if OR2_COLS_10 + default 0x1000 if OR2_COLS_11 + default 0x1400 if OR2_COLS_12 + default 0x1800 if OR2_COLS_13 + default 0x1c00 if OR2_COLS_14 + +config OR2_ROWS + hex + default 0x0 if !BR2_MACHINE_SDRAM + default 0x0 if OR2_ROWS_9 + default 0x40 if OR2_ROWS_10 + default 0x80 if OR2_ROWS_11 + default 0xc0 if OR2_ROWS_12 + default 0x100 if OR2_ROWS_13 + default 0x140 if OR2_ROWS_14 + default 0x180 if OR2_ROWS_15 + +config OR2_PMSEL + hex + default 0x0 if !BR2_MACHINE_SDRAM + default 0x0 if OR2_PMSEL_BTB + default 0x20 if OR2_PMSEL_KEPT_OPEN + +config OR2_SCY + hex + default 0x0 if !BR2_MACHINE_GPCM && !BR2_MACHINE_FCM + default 0x0 if OR2_SCY_0 + default 0x10 if OR2_SCY_1 + default 0x20 if OR2_SCY_2 + default 0x30 if OR2_SCY_3 + default 0x40 if OR2_SCY_4 + default 0x50 if OR2_SCY_5 + default 0x60 if OR2_SCY_6 + default 0x70 if OR2_SCY_7 + default 0x80 if OR2_SCY_8 + default 0x90 if OR2_SCY_9 + default 0xa0 if OR2_SCY_10 + default 0xb0 if OR2_SCY_11 + default 0xc0 if OR2_SCY_12 + default 0xd0 if OR2_SCY_13 + default 0xe0 if OR2_SCY_14 + default 0xf0 if OR2_SCY_15 + +config OR2_PGS + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_PGS_SMALL + default 0x400 if OR2_PGS_LARGE + +config OR2_CSCT + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_CSCT_1_CYCLE + default 0x0 if OR2_CSCT_2_CYCLE + default 0x200 if OR2_CSCT_4_CYCLE + default 0x200 if OR2_CSCT_8_CYCLE + +config OR2_CST + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_CST_COINCIDENT + default 0x100 if OR2_CST_QUARTER_CLOCK + default 0x0 if OR2_CST_HALF_CLOCK + default 0x100 if OR2_CST_ONE_CLOCK + +config OR2_CHT + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_CHT_HALF_CLOCK + default 0x80 if OR2_CHT_ONE_CLOCK + default 0x0 if OR2_CHT_ONE_HALF_CLOCK + default 0x80 if OR2_CHT_TWO_CLOCK + +config OR2_RST + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_RST_THREE_QUARTER_CLOCK + default 0x8 if OR2_RST_ONE_CLOCK + default 0x0 if OR2_RST_ONE_HALF_CLOCK + +config OR2_CSNT + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_CSNT_NORMAL + default 0x800 if OR2_CSNT_EARLIER + +config OR2_ACS + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_ACS_SAME_TIME + default 0x400 if OR2_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR2_ACS_HALF_CYCLE_EARLIER + +config OR2_XACS + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_XACS_NORMAL + default 0x100 if OR2_XACS_EXTENDED + +config OR2_SETA + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_SETA_INTERNAL + default 0x8 if OR2_SETA_EXTERNAL + +config OR2_TRLX + hex + default 0x0 if OR2_TRLX_NORMAL + default 0x4 if OR2_TRLX_RELAXED + +config OR2_EHTR + hex + default 0x0 if OR2_EHTR_NORMAL + default 0x2 if OR2_EHTR_1_CYCLE + default 0x0 if OR2_EHTR_4_CYCLE + default 0x2 if OR2_EHTR_8_CYCLE + +config OR2_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR2_EAD_NONE + default 0x1 if OR2_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 new file mode 100644 index 00000000000..963831bfcbd --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR3_OR3 + bool "ELBC BR3/OR3" + +if ELBC_BR3_OR3 + +config BR3_OR3_NAME + string "Identifier" + +config BR3_OR3_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR3_PORTSIZE_8BIT + bool "8-bit" + +config BR3_PORTSIZE_16BIT + depends on !BR3_MACHINE_FCM + bool "16-bit" + + +config BR3_PORTSIZE_32BIT + depends on !BR3_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR3_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR3_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR3_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR3_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR3_WRITE_PROTECT + bool "Write-protect" + +config BR3_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR3_MACHINE_GPCM + bool "GPCM" + +config BR3_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR3_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR3_MACHINE_UPMA + select BR3_MACHINE_UPM + bool "UPM (A)" + +config BR3_MACHINE_UPMB + select BR3_MACHINE_UPM + bool "UPM (B)" + +config BR3_MACHINE_UPMC + select BR3_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR3_ATOMIC_NONE + bool "No atomic operations" + +config BR3_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR3_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR3_MACHINE_GPCM || BR3_MACHINE_FCM || BR3_MACHINE_UPM || BR3_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR3_AM_32_KBYTES + depends on !BR3_MACHINE_SDRAM + bool "32 kb" + +config OR3_AM_64_KBYTES + bool "64 kb" + +config OR3_AM_128_KBYTES + bool "128 kb" + +config OR3_AM_256_KBYTES + bool "256 kb" + +config OR3_AM_512_KBYTES + bool "512 kb" + +config OR3_AM_1_MBYTES + bool "1 mb" + +config OR3_AM_2_MBYTES + bool "2 mb" + +config OR3_AM_4_MBYTES + bool "4 mb" + +config OR3_AM_8_MBYTES + bool "8 mb" + +config OR3_AM_16_MBYTES + bool "16 mb" + +config OR3_AM_32_MBYTES + bool "32 mb" + +config OR3_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR3_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR3_AM_256_MBYTES + bool "256 mb" + +config OR3_AM_512_MBYTES + depends on BR3_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR3_AM_1_GBYTES + bool "1 gb" + +config OR3_AM_2_GBYTES + depends on BR3_MACHINE_FCM + bool "2 gb" + +config OR3_AM_4_GBYTES + depends on BR3_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR3_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR3_BCTLD_ASSERTED + bool "Asserted" + +config OR3_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR3_MACHINE_GPCM || BR3_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR3_SCY_0 + bool "No wait states" + +config OR3_SCY_1 + bool "1 wait state" + +config OR3_SCY_2 + bool "2 wait states" + +config OR3_SCY_3 + bool "3 wait states" + +config OR3_SCY_4 + bool "4 wait states" + +config OR3_SCY_5 + bool "5 wait states" + +config OR3_SCY_6 + bool "6 wait states" + +config OR3_SCY_7 + bool "7 wait states" + +config OR3_SCY_8 + depends on BR3_MACHINE_GPCM + bool "8 wait states" + +config OR3_SCY_9 + depends on BR3_MACHINE_GPCM + bool "9 wait states" + +config OR3_SCY_10 + depends on BR3_MACHINE_GPCM + bool "10 wait states" + +config OR3_SCY_11 + depends on BR3_MACHINE_GPCM + bool "11 wait states" + +config OR3_SCY_12 + depends on BR3_MACHINE_GPCM + bool "12 wait states" + +config OR3_SCY_13 + depends on BR3_MACHINE_GPCM + bool "13 wait states" + +config OR3_SCY_14 + depends on BR3_MACHINE_GPCM + bool "14 wait states" + +config OR3_SCY_15 + depends on BR3_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR3_MACHINE_GPCM || BR3_MACHINE_FCM + +if BR3_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR3_CSNT_NORMAL + bool "Normal" + +config OR3_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR3_ACS_SAME_TIME + bool "At the same time" + +config OR3_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR3_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR3_XACS_NORMAL + bool "Normal" + +config OR3_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR3_SETA_INTERNAL + bool "Access is terminated internally" + +config OR3_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR3_MACHINE_GPCM + +if BR3_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR3_PGS_SMALL + bool "Small page device" + +config OR3_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR3_CSCT_1_CYCLE + depends on OR3_TRLX_NORMAL + bool "1 cycle" + +config OR3_CSCT_2_CYCLE + depends on OR3_TRLX_RELAXED + bool "2 cycles" + +config OR3_CSCT_4_CYCLE + depends on OR3_TRLX_NORMAL + bool "4 cycles" + +config OR3_CSCT_8_CYCLE + depends on OR3_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR3_CST_COINCIDENT + depends on OR3_TRLX_NORMAL + bool "Coincident with any command" + +config OR3_CST_QUARTER_CLOCK + depends on OR3_TRLX_NORMAL + bool "0.25 clocks after" + +config OR3_CST_HALF_CLOCK + depends on OR3_TRLX_RELAXED + bool "0.5 clocks after" + +config OR3_CST_ONE_CLOCK + depends on OR3_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR3_CHT_HALF_CLOCK + depends on OR3_TRLX_NORMAL + bool "0.5 clocks before" + +config OR3_CHT_ONE_CLOCK + depends on OR3_TRLX_NORMAL + bool "1 clock before" + +config OR3_CHT_ONE_HALF_CLOCK + depends on OR3_TRLX_RELAXED + bool "1.5 clocks before" + +config OR3_CHT_TWO_CLOCK + depends on OR3_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR3_RST_THREE_QUARTER_CLOCK + depends on OR3_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR3_RST_ONE_HALF_CLOCK + depends on OR3_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR3_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR3_MACHINE_FCM + +if BR3_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR3_BI_BURSTSUPPORT + bool "Support burst access" + +config OR3_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR3_MACHINE_UPM + +if BR3_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR3_COLS_7 + bool "7" + +config OR3_COLS_8 + bool "8" + +config OR3_COLS_9 + bool "9" + +config OR3_COLS_10 + bool "10" + +config OR3_COLS_11 + bool "11" + +config OR3_COLS_12 + bool "12" + +config OR3_COLS_13 + bool "13" + +config OR3_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR3_ROWS_9 + bool "9" + +config OR3_ROWS_10 + bool "10" + +config OR3_ROWS_11 + bool "11" + +config OR3_ROWS_12 + bool "12" + +config OR3_ROWS_13 + bool "13" + +config OR3_ROWS_14 + bool "14" + +config OR3_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR3_PMSEL_BTB + bool "Back-to-back" + +config OR3_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR3_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR3_TRLX_NORMAL + bool "Normal" + +config OR3_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR3_EHTR_NORMAL + depends on OR3_TRLX_NORMAL + bool "Normal" + +config OR3_EHTR_1_CYCLE + depends on OR3_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR3_EHTR_4_CYCLE + depends on OR3_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR3_EHTR_8_CYCLE + depends on OR3_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR3_EAD_NONE + bool "None" + +config OR3_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR3_OR3 + +config BR3_PORTSIZE + hex + default 0x800 if BR3_PORTSIZE_8BIT + default 0x1000 if BR3_PORTSIZE_16BIT + default 0x1800 if BR3_PORTSIZE_32BIT + +config BR3_ERRORCHECKING + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if BR3_ERRORCHECKING_DISABLED + default 0x200 if BR3_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR3_ERRORCHECKING_BOTH + +config BR3_WRITE_PROTECT_BIT + hex + default 0x0 if !BR3_WRITE_PROTECT + default 0x100 if BR3_WRITE_PROTECT + +config BR3_MACHINE + hex + default 0x0 if BR3_MACHINE_GPCM + default 0x20 if BR3_MACHINE_FCM + default 0x60 if BR3_MACHINE_SDRAM + default 0x80 if BR3_MACHINE_UPMA + default 0xa0 if BR3_MACHINE_UPMB + default 0xc0 if BR3_MACHINE_UPMC + +config BR3_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR3_ATOMIC_NONE + default 0x4 if BR3_ATOMIC_RAWA + default 0x8 if BR3_ATOMIC_WARA + +config BR3_VALID_BIT + hex + default 0x0 if !ELBC_BR3_OR3 + default 0x1 if ELBC_BR3_OR3 + +config OR3_AM + hex + default 0xffff8000 if OR3_AM_32_KBYTES && !BR3_MACHINE_SDRAM + default 0xffff0000 if OR3_AM_64_KBYTES + default 0xfffe0000 if OR3_AM_128_KBYTES + default 0xfffc0000 if OR3_AM_256_KBYTES + default 0xfff80000 if OR3_AM_512_KBYTES + default 0xfff00000 if OR3_AM_1_MBYTES + default 0xffe00000 if OR3_AM_2_MBYTES + default 0xffc00000 if OR3_AM_4_MBYTES + default 0xff800000 if OR3_AM_8_MBYTES + default 0xff000000 if OR3_AM_16_MBYTES + default 0xfe000000 if OR3_AM_32_MBYTES + default 0xfc000000 if OR3_AM_64_MBYTES + default 0xf8000000 if OR3_AM_128_MBYTES + default 0xf0000000 if OR3_AM_256_MBYTES + default 0xe0000000 if OR3_AM_512_MBYTES + default 0xc0000000 if OR3_AM_1_GBYTES + default 0x80000000 if OR3_AM_2_GBYTES + default 0x00000000 if OR3_AM_4_GBYTES + +config OR3_XAM + hex + default 0x0 if !OR3_XAM_SET + default 0x6000 if OR3_XAM_SET + +config OR3_BCTLD + hex + default 0x0 if OR3_BCTLD_ASSERTED + default 0x1000 if OR3_BCTLD_NOT_ASSERTED + +config OR3_BI + hex + default 0x0 if !BR3_MACHINE_UPM + default 0x0 if OR3_BI_BURSTSUPPORT + default 0x100 if OR3_BI_BURSTINHIBIT + +config OR3_COLS + hex + default 0x0 if !BR3_MACHINE_SDRAM + default 0x0 if OR3_COLS_7 + default 0x400 if OR3_COLS_8 + default 0x800 if OR3_COLS_9 + default 0xc00 if OR3_COLS_10 + default 0x1000 if OR3_COLS_11 + default 0x1400 if OR3_COLS_12 + default 0x1800 if OR3_COLS_13 + default 0x1c00 if OR3_COLS_14 + +config OR3_ROWS + hex + default 0x0 if !BR3_MACHINE_SDRAM + default 0x0 if OR3_ROWS_9 + default 0x40 if OR3_ROWS_10 + default 0x80 if OR3_ROWS_11 + default 0xc0 if OR3_ROWS_12 + default 0x100 if OR3_ROWS_13 + default 0x140 if OR3_ROWS_14 + default 0x180 if OR3_ROWS_15 + +config OR3_PMSEL + hex + default 0x0 if !BR3_MACHINE_SDRAM + default 0x0 if OR3_PMSEL_BTB + default 0x20 if OR3_PMSEL_KEPT_OPEN + +config OR3_SCY + hex + default 0x0 if !BR3_MACHINE_GPCM && !BR3_MACHINE_FCM + default 0x0 if OR3_SCY_0 + default 0x10 if OR3_SCY_1 + default 0x20 if OR3_SCY_2 + default 0x30 if OR3_SCY_3 + default 0x40 if OR3_SCY_4 + default 0x50 if OR3_SCY_5 + default 0x60 if OR3_SCY_6 + default 0x70 if OR3_SCY_7 + default 0x80 if OR3_SCY_8 + default 0x90 if OR3_SCY_9 + default 0xa0 if OR3_SCY_10 + default 0xb0 if OR3_SCY_11 + default 0xc0 if OR3_SCY_12 + default 0xd0 if OR3_SCY_13 + default 0xe0 if OR3_SCY_14 + default 0xf0 if OR3_SCY_15 + +config OR3_PGS + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_PGS_SMALL + default 0x400 if OR3_PGS_LARGE + +config OR3_CSCT + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_CSCT_1_CYCLE + default 0x0 if OR3_CSCT_2_CYCLE + default 0x200 if OR3_CSCT_4_CYCLE + default 0x200 if OR3_CSCT_8_CYCLE + +config OR3_CST + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_CST_COINCIDENT + default 0x100 if OR3_CST_QUARTER_CLOCK + default 0x0 if OR3_CST_HALF_CLOCK + default 0x100 if OR3_CST_ONE_CLOCK + +config OR3_CHT + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_CHT_HALF_CLOCK + default 0x80 if OR3_CHT_ONE_CLOCK + default 0x0 if OR3_CHT_ONE_HALF_CLOCK + default 0x80 if OR3_CHT_TWO_CLOCK + +config OR3_RST + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_RST_THREE_QUARTER_CLOCK + default 0x8 if OR3_RST_ONE_CLOCK + default 0x0 if OR3_RST_ONE_HALF_CLOCK + +config OR3_CSNT + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_CSNT_NORMAL + default 0x800 if OR3_CSNT_EARLIER + +config OR3_ACS + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_ACS_SAME_TIME + default 0x400 if OR3_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR3_ACS_HALF_CYCLE_EARLIER + +config OR3_XACS + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_XACS_NORMAL + default 0x100 if OR3_XACS_EXTENDED + +config OR3_SETA + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_SETA_INTERNAL + default 0x8 if OR3_SETA_EXTERNAL + +config OR3_TRLX + hex + default 0x0 if OR3_TRLX_NORMAL + default 0x4 if OR3_TRLX_RELAXED + +config OR3_EHTR + hex + default 0x0 if OR3_EHTR_NORMAL + default 0x2 if OR3_EHTR_1_CYCLE + default 0x0 if OR3_EHTR_4_CYCLE + default 0x2 if OR3_EHTR_8_CYCLE + +config OR3_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR3_EAD_NONE + default 0x1 if OR3_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 new file mode 100644 index 00000000000..0063dab9622 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR4_OR4 + bool "ELBC BR4/OR4" + +if ELBC_BR4_OR4 + +config BR4_OR4_NAME + string "Identifier" + +config BR4_OR4_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR4_PORTSIZE_8BIT + bool "8-bit" + +config BR4_PORTSIZE_16BIT + depends on !BR4_MACHINE_FCM + bool "16-bit" + + +config BR4_PORTSIZE_32BIT + depends on !BR4_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR4_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR4_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR4_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR4_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR4_WRITE_PROTECT + bool "Write-protect" + +config BR4_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR4_MACHINE_GPCM + bool "GPCM" + +config BR4_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR4_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR4_MACHINE_UPMA + select BR4_MACHINE_UPM + bool "UPM (A)" + +config BR4_MACHINE_UPMB + select BR4_MACHINE_UPM + bool "UPM (B)" + +config BR4_MACHINE_UPMC + select BR4_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR4_ATOMIC_NONE + bool "No atomic operations" + +config BR4_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR4_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR4_MACHINE_GPCM || BR4_MACHINE_FCM || BR4_MACHINE_UPM || BR4_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR4_AM_32_KBYTES + depends on !BR4_MACHINE_SDRAM + bool "32 kb" + +config OR4_AM_64_KBYTES + bool "64 kb" + +config OR4_AM_128_KBYTES + bool "128 kb" + +config OR4_AM_256_KBYTES + bool "256 kb" + +config OR4_AM_512_KBYTES + bool "512 kb" + +config OR4_AM_1_MBYTES + bool "1 mb" + +config OR4_AM_2_MBYTES + bool "2 mb" + +config OR4_AM_4_MBYTES + bool "4 mb" + +config OR4_AM_8_MBYTES + bool "8 mb" + +config OR4_AM_16_MBYTES + bool "16 mb" + +config OR4_AM_32_MBYTES + bool "32 mb" + +config OR4_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR4_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR4_AM_256_MBYTES + bool "256 mb" + +config OR4_AM_512_MBYTES + depends on BR4_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR4_AM_1_GBYTES + bool "1 gb" + +config OR4_AM_2_GBYTES + depends on BR4_MACHINE_FCM + bool "2 gb" + +config OR4_AM_4_GBYTES + depends on BR4_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR4_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR4_BCTLD_ASSERTED + bool "Asserted" + +config OR4_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR4_MACHINE_GPCM || BR4_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR4_SCY_0 + bool "No wait states" + +config OR4_SCY_1 + bool "1 wait state" + +config OR4_SCY_2 + bool "2 wait states" + +config OR4_SCY_3 + bool "3 wait states" + +config OR4_SCY_4 + bool "4 wait states" + +config OR4_SCY_5 + bool "5 wait states" + +config OR4_SCY_6 + bool "6 wait states" + +config OR4_SCY_7 + bool "7 wait states" + +config OR4_SCY_8 + depends on BR4_MACHINE_GPCM + bool "8 wait states" + +config OR4_SCY_9 + depends on BR4_MACHINE_GPCM + bool "9 wait states" + +config OR4_SCY_10 + depends on BR4_MACHINE_GPCM + bool "10 wait states" + +config OR4_SCY_11 + depends on BR4_MACHINE_GPCM + bool "11 wait states" + +config OR4_SCY_12 + depends on BR4_MACHINE_GPCM + bool "12 wait states" + +config OR4_SCY_13 + depends on BR4_MACHINE_GPCM + bool "13 wait states" + +config OR4_SCY_14 + depends on BR4_MACHINE_GPCM + bool "14 wait states" + +config OR4_SCY_15 + depends on BR4_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR4_MACHINE_GPCM || BR4_MACHINE_FCM + +if BR4_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR4_CSNT_NORMAL + bool "Normal" + +config OR4_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR4_ACS_SAME_TIME + bool "At the same time" + +config OR4_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR4_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR4_XACS_NORMAL + bool "Normal" + +config OR4_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR4_SETA_INTERNAL + bool "Access is terminated internally" + +config OR4_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR4_MACHINE_GPCM + +if BR4_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR4_PGS_SMALL + bool "Small page device" + +config OR4_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR4_CSCT_1_CYCLE + depends on OR4_TRLX_NORMAL + bool "1 cycle" + +config OR4_CSCT_2_CYCLE + depends on OR4_TRLX_RELAXED + bool "2 cycles" + +config OR4_CSCT_4_CYCLE + depends on OR4_TRLX_NORMAL + bool "4 cycles" + +config OR4_CSCT_8_CYCLE + depends on OR4_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR4_CST_COINCIDENT + depends on OR4_TRLX_NORMAL + bool "Coincident with any command" + +config OR4_CST_QUARTER_CLOCK + depends on OR4_TRLX_NORMAL + bool "0.25 clocks after" + +config OR4_CST_HALF_CLOCK + depends on OR4_TRLX_RELAXED + bool "0.5 clocks after" + +config OR4_CST_ONE_CLOCK + depends on OR4_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR4_CHT_HALF_CLOCK + depends on OR4_TRLX_NORMAL + bool "0.5 clocks before" + +config OR4_CHT_ONE_CLOCK + depends on OR4_TRLX_NORMAL + bool "1 clock before" + +config OR4_CHT_ONE_HALF_CLOCK + depends on OR4_TRLX_RELAXED + bool "1.5 clocks before" + +config OR4_CHT_TWO_CLOCK + depends on OR4_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR4_RST_THREE_QUARTER_CLOCK + depends on OR4_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR4_RST_ONE_HALF_CLOCK + depends on OR4_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR4_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR4_MACHINE_FCM + +if BR4_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR4_BI_BURSTSUPPORT + bool "Support burst access" + +config OR4_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR4_MACHINE_UPM + +if BR4_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR4_COLS_7 + bool "7" + +config OR4_COLS_8 + bool "8" + +config OR4_COLS_9 + bool "9" + +config OR4_COLS_10 + bool "10" + +config OR4_COLS_11 + bool "11" + +config OR4_COLS_12 + bool "12" + +config OR4_COLS_13 + bool "13" + +config OR4_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR4_ROWS_9 + bool "9" + +config OR4_ROWS_10 + bool "10" + +config OR4_ROWS_11 + bool "11" + +config OR4_ROWS_12 + bool "12" + +config OR4_ROWS_13 + bool "13" + +config OR4_ROWS_14 + bool "14" + +config OR4_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR4_PMSEL_BTB + bool "Back-to-back" + +config OR4_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR4_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR4_TRLX_NORMAL + bool "Normal" + +config OR4_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR4_EHTR_NORMAL + depends on OR4_TRLX_NORMAL + bool "Normal" + +config OR4_EHTR_1_CYCLE + depends on OR4_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR4_EHTR_4_CYCLE + depends on OR4_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR4_EHTR_8_CYCLE + depends on OR4_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR4_EAD_NONE + bool "None" + +config OR4_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR4_OR4 + +config BR4_PORTSIZE + hex + default 0x800 if BR4_PORTSIZE_8BIT + default 0x1000 if BR4_PORTSIZE_16BIT + default 0x1800 if BR4_PORTSIZE_32BIT + +config BR4_ERRORCHECKING + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if BR4_ERRORCHECKING_DISABLED + default 0x200 if BR4_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR4_ERRORCHECKING_BOTH + +config BR4_WRITE_PROTECT_BIT + hex + default 0x0 if !BR4_WRITE_PROTECT + default 0x100 if BR4_WRITE_PROTECT + +config BR4_MACHINE + hex + default 0x0 if BR4_MACHINE_GPCM + default 0x20 if BR4_MACHINE_FCM + default 0x60 if BR4_MACHINE_SDRAM + default 0x80 if BR4_MACHINE_UPMA + default 0xa0 if BR4_MACHINE_UPMB + default 0xc0 if BR4_MACHINE_UPMC + +config BR4_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR4_ATOMIC_NONE + default 0x4 if BR4_ATOMIC_RAWA + default 0x8 if BR4_ATOMIC_WARA + +config BR4_VALID_BIT + hex + default 0x0 if !ELBC_BR4_OR4 + default 0x1 if ELBC_BR4_OR4 + +config OR4_AM + hex + default 0xffff8000 if OR4_AM_32_KBYTES && !BR4_MACHINE_SDRAM + default 0xffff0000 if OR4_AM_64_KBYTES + default 0xfffe0000 if OR4_AM_128_KBYTES + default 0xfffc0000 if OR4_AM_256_KBYTES + default 0xfff80000 if OR4_AM_512_KBYTES + default 0xfff00000 if OR4_AM_1_MBYTES + default 0xffe00000 if OR4_AM_2_MBYTES + default 0xffc00000 if OR4_AM_4_MBYTES + default 0xff800000 if OR4_AM_8_MBYTES + default 0xff000000 if OR4_AM_16_MBYTES + default 0xfe000000 if OR4_AM_32_MBYTES + default 0xfc000000 if OR4_AM_64_MBYTES + default 0xf8000000 if OR4_AM_128_MBYTES + default 0xf0000000 if OR4_AM_256_MBYTES + default 0xe0000000 if OR4_AM_512_MBYTES + default 0xc0000000 if OR4_AM_1_GBYTES + default 0x80000000 if OR4_AM_2_GBYTES + default 0x00000000 if OR4_AM_4_GBYTES + +config OR4_XAM + hex + default 0x0 if !OR4_XAM_SET + default 0x6000 if OR4_XAM_SET + +config OR4_BCTLD + hex + default 0x0 if OR4_BCTLD_ASSERTED + default 0x1000 if OR4_BCTLD_NOT_ASSERTED + +config OR4_BI + hex + default 0x0 if !BR4_MACHINE_UPM + default 0x0 if OR4_BI_BURSTSUPPORT + default 0x100 if OR4_BI_BURSTINHIBIT + +config OR4_COLS + hex + default 0x0 if !BR4_MACHINE_SDRAM + default 0x0 if OR4_COLS_7 + default 0x400 if OR4_COLS_8 + default 0x800 if OR4_COLS_9 + default 0xc00 if OR4_COLS_10 + default 0x1000 if OR4_COLS_11 + default 0x1400 if OR4_COLS_12 + default 0x1800 if OR4_COLS_13 + default 0x1c00 if OR4_COLS_14 + +config OR4_ROWS + hex + default 0x0 if !BR4_MACHINE_SDRAM + default 0x0 if OR4_ROWS_9 + default 0x40 if OR4_ROWS_10 + default 0x80 if OR4_ROWS_11 + default 0xc0 if OR4_ROWS_12 + default 0x100 if OR4_ROWS_13 + default 0x140 if OR4_ROWS_14 + default 0x180 if OR4_ROWS_15 + +config OR4_PMSEL + hex + default 0x0 if !BR4_MACHINE_SDRAM + default 0x0 if OR4_PMSEL_BTB + default 0x20 if OR4_PMSEL_KEPT_OPEN + +config OR4_SCY + hex + default 0x0 if !BR4_MACHINE_GPCM && !BR4_MACHINE_FCM + default 0x0 if OR4_SCY_0 + default 0x10 if OR4_SCY_1 + default 0x20 if OR4_SCY_2 + default 0x30 if OR4_SCY_3 + default 0x40 if OR4_SCY_4 + default 0x50 if OR4_SCY_5 + default 0x60 if OR4_SCY_6 + default 0x70 if OR4_SCY_7 + default 0x80 if OR4_SCY_8 + default 0x90 if OR4_SCY_9 + default 0xa0 if OR4_SCY_10 + default 0xb0 if OR4_SCY_11 + default 0xc0 if OR4_SCY_12 + default 0xd0 if OR4_SCY_13 + default 0xe0 if OR4_SCY_14 + default 0xf0 if OR4_SCY_15 + +config OR4_PGS + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_PGS_SMALL + default 0x400 if OR4_PGS_LARGE + +config OR4_CSCT + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_CSCT_1_CYCLE + default 0x0 if OR4_CSCT_2_CYCLE + default 0x200 if OR4_CSCT_4_CYCLE + default 0x200 if OR4_CSCT_8_CYCLE + +config OR4_CST + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_CST_COINCIDENT + default 0x100 if OR4_CST_QUARTER_CLOCK + default 0x0 if OR4_CST_HALF_CLOCK + default 0x100 if OR4_CST_ONE_CLOCK + +config OR4_CHT + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_CHT_HALF_CLOCK + default 0x80 if OR4_CHT_ONE_CLOCK + default 0x0 if OR4_CHT_ONE_HALF_CLOCK + default 0x80 if OR4_CHT_TWO_CLOCK + +config OR4_RST + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_RST_THREE_QUARTER_CLOCK + default 0x8 if OR4_RST_ONE_CLOCK + default 0x0 if OR4_RST_ONE_HALF_CLOCK + +config OR4_CSNT + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_CSNT_NORMAL + default 0x800 if OR4_CSNT_EARLIER + +config OR4_ACS + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_ACS_SAME_TIME + default 0x400 if OR4_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR4_ACS_HALF_CYCLE_EARLIER + +config OR4_XACS + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_XACS_NORMAL + default 0x100 if OR4_XACS_EXTENDED + +config OR4_SETA + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_SETA_INTERNAL + default 0x8 if OR4_SETA_EXTERNAL + +config OR4_TRLX + hex + default 0x0 if OR4_TRLX_NORMAL + default 0x4 if OR4_TRLX_RELAXED + +config OR4_EHTR + hex + default 0x0 if OR4_EHTR_NORMAL + default 0x2 if OR4_EHTR_1_CYCLE + default 0x0 if OR4_EHTR_4_CYCLE + default 0x2 if OR4_EHTR_8_CYCLE + +config OR4_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR4_EAD_NONE + default 0x1 if OR4_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h new file mode 100644 index 00000000000..245fe7c6fb7 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h @@ -0,0 +1,186 @@ +#ifdef CONFIG_ELBC_BR0_OR0 +#define CONFIG_SYS_BR0_PRELIM (\ + CONFIG_BR0_OR0_BASE |\ + CONFIG_BR0_PORTSIZE |\ + CONFIG_BR0_ERRORCHECKING |\ + CONFIG_BR0_WRITE_PROTECT_BIT |\ + CONFIG_BR0_MACHINE |\ + CONFIG_BR0_ATOMIC |\ + CONFIG_BR0_VALID_BIT \ +) +#define CONFIG_SYS_OR0_PRELIM (\ + CONFIG_OR0_AM |\ + CONFIG_OR0_XAM |\ + CONFIG_OR0_BCTLD |\ + CONFIG_OR0_BI |\ + CONFIG_OR0_COLS |\ + CONFIG_OR0_ROWS |\ + CONFIG_OR0_PMSEL |\ + CONFIG_OR0_SCY |\ + CONFIG_OR0_PGS |\ + CONFIG_OR0_CSCT |\ + CONFIG_OR0_CST |\ + CONFIG_OR0_CHT |\ + CONFIG_OR0_RST |\ + CONFIG_OR0_CSNT |\ + CONFIG_OR0_ACS |\ + CONFIG_OR0_XACS |\ + CONFIG_OR0_SETA |\ + CONFIG_OR0_TRLX |\ + CONFIG_OR0_EHTR |\ + CONFIG_OR0_EAD \ +) +#endif /* CONFIG_ELBC_BR0_OR0 */ + +#ifdef CONFIG_ELBC_BR1_OR1 +#define CONFIG_SYS_BR1_PRELIM (\ + CONFIG_BR1_OR1_BASE |\ + CONFIG_BR1_PORTSIZE |\ + CONFIG_BR1_ERRORCHECKING |\ + CONFIG_BR1_WRITE_PROTECT_BIT |\ + CONFIG_BR1_MACHINE |\ + CONFIG_BR1_ATOMIC |\ + CONFIG_BR1_VALID_BIT \ +) +#define CONFIG_SYS_OR1_PRELIM (\ + CONFIG_OR1_AM |\ + CONFIG_OR1_XAM |\ + CONFIG_OR1_BCTLD |\ + CONFIG_OR1_BI |\ + CONFIG_OR1_COLS |\ + CONFIG_OR1_ROWS |\ + CONFIG_OR1_PMSEL |\ + CONFIG_OR1_SCY |\ + CONFIG_OR1_PGS |\ + CONFIG_OR1_CSCT |\ + CONFIG_OR1_CST |\ + CONFIG_OR1_CHT |\ + CONFIG_OR1_RST |\ + CONFIG_OR1_CSNT |\ + CONFIG_OR1_ACS |\ + CONFIG_OR1_XACS |\ + CONFIG_OR1_SETA |\ + CONFIG_OR1_TRLX |\ + CONFIG_OR1_EHTR |\ + CONFIG_OR1_EAD \ +) +#endif /* CONFIG_ELBC_BR1_OR1 */ + +#ifdef CONFIG_ELBC_BR2_OR2 +#define CONFIG_SYS_BR2_PRELIM (\ + CONFIG_BR2_OR2_BASE |\ + CONFIG_BR2_PORTSIZE |\ + CONFIG_BR2_ERRORCHECKING |\ + CONFIG_BR2_WRITE_PROTECT_BIT |\ + CONFIG_BR2_MACHINE |\ + CONFIG_BR2_ATOMIC |\ + CONFIG_BR2_VALID_BIT \ +) +#define CONFIG_SYS_OR2_PRELIM (\ + CONFIG_OR2_AM |\ + CONFIG_OR2_XAM |\ + CONFIG_OR2_BCTLD |\ + CONFIG_OR2_BI |\ + CONFIG_OR2_COLS |\ + CONFIG_OR2_ROWS |\ + CONFIG_OR2_PMSEL |\ + CONFIG_OR2_SCY |\ + CONFIG_OR2_PGS |\ + CONFIG_OR2_CSCT |\ + CONFIG_OR2_CST |\ + CONFIG_OR2_CHT |\ + CONFIG_OR2_RST |\ + CONFIG_OR2_CSNT |\ + CONFIG_OR2_ACS |\ + CONFIG_OR2_XACS |\ + CONFIG_OR2_SETA |\ + CONFIG_OR2_TRLX |\ + CONFIG_OR2_EHTR |\ + CONFIG_OR2_EAD \ +) +#endif /* CONFIG_ELBC_BR2_OR2 */ + +#ifdef CONFIG_ELBC_BR3_OR3 +#define CONFIG_SYS_BR3_PRELIM (\ + CONFIG_BR3_OR3_BASE |\ + CONFIG_BR3_PORTSIZE |\ + CONFIG_BR3_ERRORCHECKING |\ + CONFIG_BR3_WRITE_PROTECT_BIT |\ + CONFIG_BR3_MACHINE |\ + CONFIG_BR3_ATOMIC |\ + CONFIG_BR3_VALID_BIT \ +) +#define CONFIG_SYS_OR3_PRELIM (\ + CONFIG_OR3_AM |\ + CONFIG_OR3_XAM |\ + CONFIG_OR3_BCTLD |\ + CONFIG_OR3_BI |\ + CONFIG_OR3_COLS |\ + CONFIG_OR3_ROWS |\ + CONFIG_OR3_PMSEL |\ + CONFIG_OR3_SCY |\ + CONFIG_OR3_PGS |\ + CONFIG_OR3_CSCT |\ + CONFIG_OR3_CST |\ + CONFIG_OR3_CHT |\ + CONFIG_OR3_RST |\ + CONFIG_OR3_CSNT |\ + CONFIG_OR3_ACS |\ + CONFIG_OR3_XACS |\ + CONFIG_OR3_SETA |\ + CONFIG_OR3_TRLX |\ + CONFIG_OR3_EHTR |\ + CONFIG_OR3_EAD \ +) +#endif /* CONFIG_ELBC_BR3_OR3 */ + +#ifdef CONFIG_ELBC_BR4_OR4 +#define CONFIG_SYS_BR4_PRELIM (\ + CONFIG_BR4_OR4_BASE |\ + CONFIG_BR4_PORTSIZE |\ + CONFIG_BR4_ERRORCHECKING |\ + CONFIG_BR4_WRITE_PROTECT_BIT |\ + CONFIG_BR4_MACHINE |\ + CONFIG_BR4_ATOMIC |\ + CONFIG_BR4_VALID_BIT \ +) +#define CONFIG_SYS_OR4_PRELIM (\ + CONFIG_OR4_AM |\ + CONFIG_OR4_XAM |\ + CONFIG_OR4_BCTLD |\ + CONFIG_OR4_BI |\ + CONFIG_OR4_COLS |\ + CONFIG_OR4_ROWS |\ + CONFIG_OR4_PMSEL |\ + CONFIG_OR4_SCY |\ + CONFIG_OR4_PGS |\ + CONFIG_OR4_CSCT |\ + CONFIG_OR4_CST |\ + CONFIG_OR4_CHT |\ + CONFIG_OR4_RST |\ + CONFIG_OR4_CSNT |\ + CONFIG_OR4_ACS |\ + CONFIG_OR4_XACS |\ + CONFIG_OR4_SETA |\ + CONFIG_OR4_TRLX |\ + CONFIG_OR4_EHTR |\ + CONFIG_OR4_EAD \ +) +#endif /* CONFIG_ELBC_BR4_OR4 */ + +#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM +#endif diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 75eb65010ec..b4e2fb1119d 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -7,6 +7,7 @@ #include #include "lblaw/lblaw.h" +#include "elbc/elbc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 13545fc6ad6..c43732f7c5c 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -6,6 +6,10 @@ #include #include +#ifdef CONFIG_MPC83xx +#include "../mpc83xx/elbc/elbc.h" +#endif + #ifdef CONFIG_MPC85xx /* Boards should provide their own version of this if they use lbc sdram */ static void __lbc_sdram_init(void) diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index c4bec090be1..62bcf235711 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -20,6 +20,7 @@ #endif #include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h" +#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 38c5d8d5327..c38ac328d2a 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -86,3 +86,41 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385_BASE" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 5783165e5d1..1588adf3d66 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -103,3 +103,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE2800000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index 2395b8e3978..2425256ee30 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -102,3 +102,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE2800000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index ce979149346..8ee257a54ec 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -111,3 +111,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="NAND" +CONFIG_BR0_OR0_BASE=0xE2800000 +CONFIG_BR0_ERRORCHECKING_BOTH=y +CONFIG_BR0_MACHINE_FCM=y +CONFIG_BR0_PORTSIZE_8BIT=y +CONFIG_OR0_AM_32_KBYTES=y +CONFIG_OR0_SCY_1=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_CHT_TWO_CLOCK=y +CONFIG_OR0_CSCT_8_CYCLE=y +CONFIG_OR0_CST_ONE_CLOCK=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FLASH" +CONFIG_BR1_OR1_BASE=0xFE000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_8_MBYTES=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_9=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index 92d33b07db2..baca3d799da 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -110,3 +110,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="NAND" +CONFIG_BR0_OR0_BASE=0xE2800000 +CONFIG_BR0_ERRORCHECKING_BOTH=y +CONFIG_BR0_MACHINE_FCM=y +CONFIG_BR0_PORTSIZE_8BIT=y +CONFIG_OR0_AM_32_KBYTES=y +CONFIG_OR0_SCY_1=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_CHT_TWO_CLOCK=y +CONFIG_OR0_CSCT_8_CYCLE=y +CONFIG_OR0_CST_ONE_CLOCK=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FLASH" +CONFIG_BR1_OR1_BASE=0xFE000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_8_MBYTES=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_9=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index b6e43b66aac..b9539893ff7 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -109,3 +109,30 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 7243cf67f96..64e6f58f38c 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -88,3 +88,17 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 8cbc14022b6..ffc82260ec3 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -87,3 +87,56 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 487d1d85442..911f62de653 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -107,3 +107,56 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 10ea03422c7..7dd02a95c92 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -107,3 +107,56 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index b1afa2fa474..3e3c82b2ef5 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -104,3 +104,56 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index a9bb8a77139..4cfa01074d1 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -86,3 +86,56 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index 28779bbeb74..a29d3268f79 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -73,3 +73,27 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index a157066968d..e3058f0b5e8 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -57,6 +57,33 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xF0000000 CONFIG_LBLAW2_NAME="SDRAM" CONFIG_LBLAW2_LENGTH_64_MBYTES=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="SDRAM" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_PORTSIZE_32BIT=y +CONFIG_BR2_MACHINE_SDRAM=y +CONFIG_OR2_COLS_9=y +CONFIG_OR2_ROWS_13=y +CONFIG_OR2_EAD_EXTRA=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 588d9420f16..d45b6489b47 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -73,3 +73,27 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index a38edb52939..e3ca6811ccf 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -76,3 +76,27 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 844b8973295..cf4ce83307a 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -125,3 +125,50 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="VSC7385" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="LED" +CONFIG_BR2_OR2_BASE=0xF9000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_2_MBYTES=y +CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_9=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CF" +CONFIG_BR3_OR3_BASE=0xF0000000 +CONFIG_BR3_MACHINE_UPMA=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BI_BURSTINHIBIT=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 91ed6686f81..e0185191bc7 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -133,3 +133,50 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="VSC7385" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="LED" +CONFIG_BR2_OR2_BASE=0xF9000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_2_MBYTES=y +CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_9=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CF" +CONFIG_BR3_OR3_BASE=0xF0000000 +CONFIG_BR3_MACHINE_UPMA=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BI_BURSTINHIBIT=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index cfa31c72307..0187f4f1280 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -132,3 +132,50 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="VSC7385" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="LED" +CONFIG_BR2_OR2_BASE=0xF9000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_2_MBYTES=y +CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_9=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CF" +CONFIG_BR3_OR3_BASE=0xF0000000 +CONFIG_BR3_MACHINE_UPMA=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BI_BURSTINHIBIT=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 4cc36a5c7fb..b048d5b5d00 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -131,3 +131,44 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="NAND" +CONFIG_BR3_OR3_BASE=0xE0600000 +CONFIG_BR3_ERRORCHECKING_BOTH=y +CONFIG_BR3_MACHINE_FCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BCTLD_NOT_ASSERTED=y +CONFIG_OR3_RST_ONE_CLOCK=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_CHT_TWO_CLOCK=y +CONFIG_OR3_CST_ONE_CLOCK=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index ba58e49ba24..9e2966b371f 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -84,3 +84,44 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="NAND" +CONFIG_BR3_OR3_BASE=0xE0600000 +CONFIG_BR3_ERRORCHECKING_BOTH=y +CONFIG_BR3_MACHINE_FCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BCTLD_NOT_ASSERTED=y +CONFIG_OR3_RST_ONE_CLOCK=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_CHT_TWO_CLOCK=y +CONFIG_OR3_CST_ONE_CLOCK=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index b3c1c87824a..9256aac17cd 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -107,3 +107,44 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="NAND" +CONFIG_BR3_OR3_BASE=0xE0600000 +CONFIG_BR3_ERRORCHECKING_BOTH=y +CONFIG_BR3_MACHINE_FCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BCTLD_NOT_ASSERTED=y +CONFIG_OR3_RST_ONE_CLOCK=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_CHT_TWO_CLOCK=y +CONFIG_OR3_CST_ONE_CLOCK=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 07016936d62..95400114f2f 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -90,3 +90,39 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 59d591fa05b..a8c69eb6bcb 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -133,3 +133,39 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index fdaded29704..49f0916663d 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -134,3 +134,13 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0x80000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_32BIT=y +CONFIG_OR0_AM_1_GBYTES=y +CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 12721f8db42..e2ea71d11a7 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -92,3 +92,24 @@ CONFIG_E1000=y CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFFC00000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_4_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="WINDOW1" +CONFIG_BR1_OR1_BASE=0xF0000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_32BIT=y +CONFIG_OR1_AM_256_KBYTES=y +CONFIG_OR1_SETA_EXTERNAL=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index f1aa24683c0..7b17f602b6d 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -89,3 +89,29 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 22689ef0aca..9a20a0d0690 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -87,3 +87,29 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 168564606c0..14104a441bf 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -119,3 +119,48 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_8BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_10=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE1000000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_PGS_LARGE=y +CONFIG_OR1_RST_ONE_CLOCK=y +CONFIG_OR1_SCY_4=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="MRAM" +CONFIG_BR2_OR2_BASE=0xE2000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_SCY_7=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CPLD" +CONFIG_BR3_OR3_BASE=0xE3000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 088dee63ba0..6740c4c8a97 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -143,3 +143,45 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_BCH=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_64_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PAXE" +CONFIG_BR3_OR3_BASE=0xA0000000 +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_ELBC_BR4_OR4=y +CONFIG_BR4_OR4_NAME="BFTIC3" +CONFIG_BR4_OR4_BASE=0xB0000000 +CONFIG_BR4_PORTSIZE_8BIT=y +CONFIG_OR4_AM_256_MBYTES=y +CONFIG_OR4_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR4_CSNT_EARLIER=y +CONFIG_OR4_EAD_EXTRA=y +CONFIG_OR4_SCY_2=y +CONFIG_OR4_TRLX_RELAXED=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 64ea83fd128..182fa477f88 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -115,3 +115,35 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_64_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PAXE" +CONFIG_BR3_OR3_BASE=0xA0000000 +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 3a88b6a0276..678900d05ce 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -130,3 +130,45 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_SCY_4=y +CONFIG_OR3_EHTR_NORMAL=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index c818d7e4a12..49780b4b19b 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -116,3 +116,37 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 640e0c7c3c3..9a57e43d784 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -120,3 +120,33 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_BCH=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_SCY_5=y +CONFIG_OR3_EHTR_NORMAL=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 81579c6b02f..78f7de9899a 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -130,3 +130,45 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_SCY_4=y +CONFIG_OR3_EHTR_NORMAL=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 709947b5391..7256750ea0b 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -133,3 +133,40 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_UPMA=y +CONFIG_BR2_PORTSIZE_16BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_3=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index b44e04e1ae2..ec2e30709ca 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -78,3 +78,32 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFC000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_64_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_4=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="SJA1000" +CONFIG_BR1_OR1_BASE=0xFBFF0000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="CPLD" +CONFIG_BR2_OR2_BASE=0xFBFF8000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_SCY_4=y +CONFIG_OR2_EHTR_1_CYCLE=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 6f407d56d56..453f85a0e33 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -89,3 +89,17 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 9c0b30f446c..b3046156302 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -89,3 +89,17 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 05361f76fcb..4ec51af9f2e 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -67,3 +67,17 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 196c44470a2..a806e9957f7 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index c407bed189d..3687a28fc3a 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 1128950ace2..4231a431b88 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index f0b2c44efb1..afb991ce1e2 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 10a32178f13..2b16ceb5242 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -131,3 +131,40 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_UPMA=y +CONFIG_BR2_PORTSIZE_16BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_3=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 6fada9bdf70..07666c3b50b 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -116,3 +116,37 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 1eb21e0e5af..627bf2febf3 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -130,3 +130,48 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_4_CYCLE=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 1df5195e977..365c4ea8587 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -95,3 +95,48 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0x61000000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_BCTLD_NOT_ASSERTED=y +CONFIG_OR1_RST_ONE_CLOCK=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="NVRAM" +CONFIG_BR2_OR2_BASE=0x60000000 +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_3=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="SRAM" +CONFIG_BR3_OR3_BASE=0x62000000 +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_MBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 9336dfac5cb..072674cbeb6 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -94,3 +94,24 @@ CONFIG_TSEC_ENET=y CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF8000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_128_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="WINDOW1" +CONFIG_BR1_OR1_BASE=0xF0000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_32BIT=y +CONFIG_OR1_AM_256_KBYTES=y +CONFIG_OR1_SETA_EXTERNAL=y diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c index 30c3308940e..099d86427c5 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_spl.c +++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c @@ -14,6 +14,10 @@ #include #include +#ifdef CONFIG_MPC83xx +#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h" +#endif + #define WINDOW_SIZE 8192 static void nand_wait(void) diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 185f6490d7c..cd78836bcd5 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -175,9 +175,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ @@ -191,9 +188,6 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* 0xFFFF8396 */ #ifdef CONFIG_VSC7385_ENET @@ -201,9 +195,6 @@ /* VSC7385 Base address on CS2 */ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385_BASE */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) /* 0xFFFE09FF */ /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 40b0264dbe4..93b553c9050 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -219,14 +219,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) -/* NAND */ -#define CONFIG_SYS_BR0_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) - -/* FLASH */ -#define CONFIG_SYS_BR1_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM @@ -235,9 +227,6 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -/* BCSR */ -#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ @@ -247,9 +236,6 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 390ee4eb265..18e056e1b24 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -188,14 +188,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) -/* FLASH*/ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) - /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM @@ -204,9 +196,6 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -/* BCSR */ -#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ #ifdef CONFIG_VSC7385_ENET @@ -215,9 +204,6 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 97b66415c9b..708829dae80 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -177,13 +177,7 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index fd884a1e654..c66e33a247e 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 41b02231352..ed47bcd5b42 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -133,9 +133,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ @@ -148,9 +145,6 @@ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Windows to access PIB via local bus @@ -163,17 +157,11 @@ * CS2 on Local Bus, to PIB */ -/* PIB1 */ -#define CONFIG_SYS_BR2_PRELIM (0xF8008000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * CS3 on Local Bus, to PIB */ -/* PIB2 */ -#define CONFIG_SYS_BR3_PRELIM (0xF8010000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Serial Port diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 4cda1589b67..3e0907dae4e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -123,9 +123,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -148,9 +145,6 @@ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 7f906c38d89..e401c29d6b7 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -123,10 +123,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -147,10 +143,6 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) - #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ @@ -192,10 +184,6 @@ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 */ -/* SDRAM */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_SDRAM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_SDRAM_XAM | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) | OR_SDRAM_EAD) - /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index e90d497f5ef..cc62fc32135 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -211,9 +211,6 @@ boards, we say we have two, but don't display a message if we find only one. */ * BRx, ORx, LBLAWBARx, and LBLAWARx */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ @@ -221,18 +218,12 @@ boards, we say we have two, but don't display a message if we find only one. */ #ifdef CONFIG_VSC7385_ENET -/* VSC7385 */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif #define CONFIG_SYS_LED_BASE 0xF9000000 -/* LED */ -#define CONFIG_SYS_BR2_PRELIM (0xF9000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Compact Flash */ @@ -240,9 +231,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_CF_BASE 0xF0000000 -/* CF */ -#define CONFIG_SYS_BR3_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_UPM_BI) #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e569e63741f..a244ae87a22 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -162,9 +162,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -178,9 +175,6 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * NAND Flash on the Local Bus @@ -190,9 +184,6 @@ #define CONFIG_SYS_NAND_BASE 0xE0600000 -/* NAND */ -#define CONFIG_SYS_BR3_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST | OR_FCM_TRLX | OR_FCM_EHTR) /* * Serial Port diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index c1898a53a6c..006279a58c3 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -188,9 +188,6 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -204,9 +201,6 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* Vitesse 7385 */ @@ -214,9 +208,6 @@ #ifdef CONFIG_VSC7385_ENET -/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c76df2847d2..af03c037865 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -76,9 +76,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0x80000000 | BR_MS_GPCM | BR_PS_32 | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_1GB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET) /* disable remaining mappings */ #define CONFIG_SYS_BR1_PRELIM 0x00000000 diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index a7eb5f52953..e9cfeae64d8 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -70,15 +70,9 @@ #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFFC00000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_4MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 -/* WINDOW1 */ -#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 3fe72db188c..9318e6252ae 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -169,9 +169,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -185,9 +182,6 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ -/* FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 61f64ebbbc0..d86dda18fb1 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8 -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_SCY_10 | OR_GPCM_EHTR_SET | OR_GPCM_TRLX_SET | OR_GPCM_CSNT | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 @@ -163,9 +160,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64 -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE1000000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_4 | OR_FCM_TRLX | OR_FCM_EHTR | OR_FCM_RST) /* * MRAM setup @@ -175,9 +169,6 @@ #define CONFIG_SYS_OR_TIMING_MRAM -/* MRAM */ -#define CONFIG_SYS_BR2_PRELIM (0xE2000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET) /* * CPLD setup @@ -187,9 +178,6 @@ #define CONFIG_SYS_OR_TIMING_MRAM -/* CPLD */ -#define CONFIG_SYS_BR3_PRELIM (0xE3000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET) /* * HW-Watchdog diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 5027073d6e9..ede8ae6ba5f 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -108,9 +108,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -120,9 +117,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -336,9 +330,6 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -/* PAXE */ -#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * BFTIC3 on the local bus CS4 @@ -346,9 +337,6 @@ #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 #define CONFIG_SYS_BFTIC3_SIZE 256 -/* BFTIC3 */ -#define CONFIG_SYS_BR4_PRELIM (0xB0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR4_PRELIM (OR_AM_256MB| OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 84516bb9bb7..728c9b199f2 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -93,9 +93,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -105,9 +102,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -316,8 +310,5 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -/* PAXE */ -#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #endif /* CONFIG */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 678cb6a7cc7..f39dbe05b7e 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -351,16 +345,10 @@ * Configuration for C2 on the local bus */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) /* * Configuration for C3 on the local bus */ -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 3e2e425c34b..19e415619a5 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -345,8 +339,5 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) #endif /* __CONFIG_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index ed221e23019..fe4763ce8ad 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -120,9 +120,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -132,9 +129,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -400,9 +394,6 @@ * */ -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) /* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index c1ed71e2afe..9302d35949d 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -347,12 +341,6 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 406b6e78244..06c5923ae1d 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -112,9 +112,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -124,9 +121,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -389,13 +383,7 @@ * */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 31bf9971ab2..cb7dabd9321 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -179,9 +179,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFC000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_4 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 @@ -196,18 +193,12 @@ */ #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 -/* SJA1000 */ -#define CONFIG_SYS_BR1_PRELIM (0xFBFF0000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_SCY_5 | OR_GPCM_EHTR_SET) /* * CPLD on Local Bus */ #define CONFIG_SYS_CPLD_BASE 0xFBFF8000 -/* CPLD */ -#define CONFIG_SYS_BR2_PRELIM (0xFBFF8000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_SCY_4 | OR_GPCM_EHTR_SET) /* * Serial Port diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 42a1e1682d2..98770ca0a64 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -98,9 +98,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ diff --git a/include/configs/strider.h b/include/configs/strider.h index 1519dad3217..dd89ee8c815 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -167,9 +167,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -183,9 +180,6 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ -/* FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 6aacbc2077e..a65b61bfbf8 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -110,9 +110,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -122,9 +119,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -342,13 +336,7 @@ * */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index b11d49629ac..6084e8af605 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -345,8 +339,5 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) #endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 1bff8371980..86aec93ee96 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -347,13 +341,7 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 3a5bcf9c62f..4c5dad9dc26 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -153,25 +153,13 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0x61000000 | BR_PS_8 | BR_DECC_CHK_GEN | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CHT | OR_FCM_SCY_2 | OR_FCM_RST | OR_FCM_TRLX) /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM -/* NVRAM */ -#define CONFIG_SYS_BR2_PRELIM (0x60000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) -/* SRAM */ -#define CONFIG_SYS_BR3_PRELIM (0x62000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Serial Port diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index dd8aae51173..9b9c1ff54e2 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -70,15 +70,9 @@ #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF8000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 -/* WINDOW1 */ -#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ -- cgit v1.3.1 From 133ec602846d28a7915a7b3149d05d1c8a270873 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:18:16 +0100 Subject: mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six --- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- board/freescale/mpc8308rdb/sdram.c | 4 ++-- board/freescale/mpc8313erdb/sdram.c | 8 ++++---- board/freescale/mpc8315erdb/sdram.c | 2 +- board/freescale/mpc8349emds/mpc8349emds.c | 8 ++++---- board/freescale/mpc8349itx/mpc8349itx.c | 8 ++++---- board/freescale/mpc837xemds/mpc837xemds.c | 2 +- board/freescale/mpc837xerdb/mpc837xerdb.c | 2 +- board/gdsys/mpc8308/sdram.c | 4 ++-- board/ids/ids8313/ids8313.c | 2 +- board/mpc8308_p1m/sdram.c | 4 ++-- board/sbc8349/sbc8349.c | 8 ++++---- board/ve8313/ve8313.c | 8 ++++---- drivers/ddr/fsl/main.c | 4 ++++ include/configs/MPC8308RDB.h | 1 - include/configs/MPC8313ERDB_NAND.h | 1 - include/configs/MPC8313ERDB_NOR.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8323ERDB.h | 1 - include/configs/MPC832XEMDS.h | 1 - include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349EMDS_SDRAM.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/configs/TQM834x.h | 1 - include/configs/caddy2.h | 1 - include/configs/hrcon.h | 1 - include/configs/ids8313.h | 1 - include/configs/kmcoge5ne.h | 1 - include/configs/kmeter1.h | 1 - include/configs/kmopti2.h | 1 - include/configs/kmsupx5.h | 1 - include/configs/kmtegr1.h | 1 - include/configs/kmtepr2.h | 1 - include/configs/kmvect1.h | 1 - include/configs/mpc8308_p1m.h | 1 - include/configs/sbc8349.h | 1 - include/configs/strider.h | 1 - include/configs/suvd3.h | 1 - include/configs/tuge1.h | 1 - include/configs/tuxx1.h | 1 - include/configs/ve8313.h | 1 - include/configs/vme8349.h | 1 - 44 files changed, 35 insertions(+), 61 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index b3cbf9f8823..5ca307ca583 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -281,7 +281,7 @@ long int spd_sdram() /* * Set up LAWBAR for all of DDR. */ - ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); debug("DDR:bar=0x%08x\n", ecm->bar); debug("DDR:ar=0x%08x\n", ecm->ar); diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c index e64b3107b5f..317e63ea6a1 100644 --- a/board/freescale/mpc8308rdb/sdram.c +++ b/board/freescale/mpc8308rdb/sdram.c @@ -33,7 +33,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -61,7 +61,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync(); - return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); } int dram_init(void) diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 5e074e3d87b..090412d4b6c 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -47,7 +47,7 @@ static long fixed_sdram(void) volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; @@ -57,12 +57,12 @@ static long fixed_sdram(void) */ __udelay(50000); -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index b9f94c83324..2f0f29a0e57 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -44,7 +44,7 @@ static long fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index ea018e5d201..f14276f6a87 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -91,7 +91,7 @@ int fixed_sdram(void) u32 ddr_size = msize << 20; /* DDR size in bytes */ u32 ddr_size_log2 = __ilog2(ddr_size); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); #if (CONFIG_SYS_DDR_SIZE != 256) @@ -112,12 +112,12 @@ int fixed_sdram(void) im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index aaaea7ce89f..81b3f00b56e 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -37,14 +37,14 @@ int fixed_sdram(void) im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 09a046dff8d..16922087c01 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -252,7 +252,7 @@ int fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); #if (CONFIG_SYS_DDR_SIZE != 512) diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index d9a47b90b2f..18f396aac8b 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -95,7 +95,7 @@ int fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 5ced8eb0819..3eb0e37b7b5 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -34,7 +34,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -62,7 +62,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync(); - return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); } int dram_init(void) diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index a37ca8a2f44..a66234aa857 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -57,7 +57,7 @@ int fixed_sdram(unsigned long config) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); sync(); diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c index 4118c019ccf..baf70d8807b 100644 --- a/board/mpc8308_p1m/sdram.c +++ b/board/mpc8308_p1m/sdram.c @@ -29,7 +29,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -57,7 +57,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync(); - return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); } int dram_init(void) diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 5584b3d1796..e51eeae065d 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -79,19 +79,19 @@ int fixed_sdram(void) u32 ddr_size = msize << 20; /* DDR size in bytes */ u32 ddr_size_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); #if (CONFIG_SYS_DDR_SIZE != 256) #warning Currently any ddr size other than 256 is not supported #endif -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index 609585bc653..f4148a21e3b 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -38,7 +38,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1))); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -48,12 +48,12 @@ static long fixed_sdram(void) */ __udelay(50000); -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif out_be32(&im->ddr.csbnds[0].csbnds, - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA)); out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 6d018fde2b2..e1f69a1d25c 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -23,8 +23,12 @@ * 0x80_8000_0000 ~ 0xff_ffff_ffff */ #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY +#ifdef CONFIG_MPC83xx +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE +#else #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE #endif +#endif #ifdef CONFIG_PPC #include diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index d9361fd8a03..5d31d4a0b6b 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -37,7 +37,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 08c83996c73..6f100fc7e7b 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -87,7 +87,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 169cc09d06b..0f246dc5186 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -59,7 +59,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index c5a229deb4c..0b94b0c5cf9 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -35,7 +35,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 3e6febfc9d3..a90a9a86f8d 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -24,7 +24,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #undef CONFIG_SPD_EEPROM #if defined(CONFIG_SPD_EEPROM) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 4b3f70c916c..88b6f873978 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -21,7 +21,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ #undef CONFIG_SPD_EEPROM diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 1a96be0895c..fdbd15ea93e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -53,7 +53,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 311f87b5b3c..1e0e297351e 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -53,7 +53,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index bb3bcfcc448..388910ac38d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -143,7 +143,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x2000 diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e34a36cadd8..61f9eaf7150 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -36,7 +36,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 33d4ced92f7..07b206ff9f9 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -59,7 +59,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 #define CONFIG_SYS_83XX_DDR_USES_CS0 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 53fac4d675a..0da34d05afc 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -25,7 +25,6 @@ */ /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index f14e5faafa6..928136f325f 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -52,7 +52,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index ae3fcfd3d79..d73e848b0c7 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -25,7 +25,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 504a136daab..155815a8815 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -52,7 +52,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 5c4df18ca64..847996f9a49 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -46,7 +46,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2e8affb6180..290108d4fc4 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -31,7 +31,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 3be53285dbc..0759604810a 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 74e719cc79f..319e3bc1ece 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index c6913838ce7..85e9101b054 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -58,7 +58,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 4af86195c5e..6ec944f9429 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index d8f4d269ed4..d7cbdde215d 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -50,7 +50,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 8836b70b762..0392c3e8b40 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -40,7 +40,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 709387ecf79..b4ae7b75543 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -47,7 +47,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/strider.h b/include/configs/strider.h index c01531c3ca2..e92bd1e8f10 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -25,7 +25,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 3521de8d2ee..8b3b45416da 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -48,7 +48,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 86e402ae233..5dc9e8997e5 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index ec1ac399a0c..9f8c855fb81 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index cd6c686b890..2116d6bbcf8 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -35,7 +35,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE /* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 14a84fabc97..1bce6c732d9 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -52,7 +52,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING -- cgit v1.3.1 From 487bb2bc85a51ce14bb27c183c9ab51090b632d0 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:40:36 +0100 Subject: mpc83xx_clk: Add enable method Some DM drivers have hardcoded clk_enable calls when handling clocks (for example the fsl_esdhc driver). To work with these drivers, add an enable method to the MCP83xx clock driver (which does nothing, because the clocks are always enabled). Signed-off-by: Mario Six --- drivers/clk/mpc83xx_clk.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c index 489004190eb..32d2db9edad 100644 --- a/drivers/clk/mpc83xx_clk.c +++ b/drivers/clk/mpc83xx_clk.c @@ -275,6 +275,12 @@ static ulong mpc83xx_clk_get_rate(struct clk *clk) return priv->speed[clk->id]; } +static int mpc83xx_clk_enable(struct clk *clk) +{ + /* MPC83xx clocks are always enabled */ + return 0; +} + int get_clocks(void) { /* Empty implementation to keep the prototype in common.h happy */ @@ -301,6 +307,7 @@ int get_serial_clock(void) const struct clk_ops mpc83xx_clk_ops = { .request = mpc83xx_clk_request, .get_rate = mpc83xx_clk_get_rate, + .enable = mpc83xx_clk_enable, }; static const struct udevice_id mpc83xx_clk_match[] = { -- cgit v1.3.1 From 98e4249f97ab5784c5f9e281519c7277c0b7588c Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:45:57 +0100 Subject: i2c: ihs: Get rid of fpgamap Since the IHS I2C driver want upstream, the surrounding infrastructure has changed quite a bit (notably, the fpgamap driver was replaced with a regmap driver). Update the driver to work with these changes. Signed-off-by: Mario Six Reviewed-by: Heiko Schocher --- drivers/i2c/ihs_i2c.c | 57 +++++++++++++++++++++------------------------------ 1 file changed, 23 insertions(+), 34 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c index 0922fe9bb10..5313490bf3a 100644 --- a/drivers/i2c/ihs_i2c.c +++ b/drivers/i2c/ihs_i2c.c @@ -8,8 +8,7 @@ #include #ifdef CONFIG_DM_I2C #include -#include -#include "../misc/gdsys_soc.h" +#include #else #include #endif @@ -18,18 +17,24 @@ #ifdef CONFIG_DM_I2C struct ihs_i2c_priv { uint speed; - phys_addr_t addr; + struct regmap *map; }; -enum { - REG_INTERRUPT_STATUS = 0x00, - REG_INTERRUPT_ENABLE_CONTROL = 0x02, - REG_WRITE_MAILBOX_EXT = 0x04, - REG_WRITE_MAILBOX = 0x06, - REG_READ_MAILBOX_EXT = 0x08, - REG_READ_MAILBOX = 0x0A, +struct ihs_i2c_regs { + u16 interrupt_status; + u16 interrupt_enable_control; + u16 write_mailbox_ext; + u16 write_mailbox; + u16 read_mailbox_ext; + u16 read_mailbox; }; +#define ihs_i2c_set(map, member, val) \ + regmap_set(map, struct ihs_i2c_regs, member, val) + +#define ihs_i2c_get(map, member, valp) \ + regmap_get(map, struct ihs_i2c_regs, member, valp) + #else /* !CONFIG_DM_I2C */ DECLARE_GLOBAL_DATA_PTR; @@ -92,14 +97,10 @@ static int wait_for_int(bool read) uint ctr = 0; #ifdef CONFIG_DM_I2C struct ihs_i2c_priv *priv = dev_get_priv(dev); - struct udevice *fpga; - - gdsys_soc_get_fpga(dev, &fpga); #endif #ifdef CONFIG_DM_I2C - fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, - FPGAMAP_SIZE_16); + ihs_i2c_get(priv->map, interrupt_status, &val); #else I2C_GET_REG(interrupt_status, &val); #endif @@ -110,8 +111,7 @@ static int wait_for_int(bool read) if (ctr++ > 5000) return 1; #ifdef CONFIG_DM_I2C - fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, - FPGAMAP_SIZE_16); + ihs_i2c_get(priv->map, interrupt_status, &val); #else I2C_GET_REG(interrupt_status, &val); #endif @@ -132,18 +132,13 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, u16 data; #ifdef CONFIG_DM_I2C struct ihs_i2c_priv *priv = dev_get_priv(dev); - struct udevice *fpga; - - gdsys_soc_get_fpga(dev, &fpga); #endif /* Clear interrupt status */ data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV; #ifdef CONFIG_DM_I2C - fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data, - FPGAMAP_SIZE_16); - fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, - FPGAMAP_SIZE_16); + ihs_i2c_set(priv->map, interrupt_status, data); + ihs_i2c_get(priv->map, interrupt_status, &val); #else I2C_SET_REG(interrupt_status, data); I2C_GET_REG(interrupt_status, &val); @@ -156,8 +151,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, if (len > 1) val |= buffer[1] << 8; #ifdef CONFIG_DM_I2C - fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val, - FPGAMAP_SIZE_16); + ihs_i2c_set(priv->map, write_mailbox_ext, val); #else I2C_SET_REG(write_mailbox_ext, val); #endif @@ -170,8 +164,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, | (is_last ? 0 : I2CMB_HOLD_BUS); #ifdef CONFIG_DM_I2C - fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data, - FPGAMAP_SIZE_16); + ihs_i2c_set(priv->map, write_mailbox, data); #else I2C_SET_REG(write_mailbox, data); #endif @@ -186,8 +179,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, /* If we want to read, get the bytes from the mailbox */ if (read) { #ifdef CONFIG_DM_I2C - fpgamap_read(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val, - FPGAMAP_SIZE_16); + ihs_i2c_get(priv->map, read_mailbox_ext, &val); #else I2C_GET_REG(read_mailbox_ext, &val); #endif @@ -270,11 +262,8 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, int ihs_i2c_probe(struct udevice *bus) { struct ihs_i2c_priv *priv = dev_get_priv(bus); - int addr; - - addr = dev_read_u32_default(bus, "reg", -1); - priv->addr = addr; + regmap_init_mem(dev_ofnode(bus), &priv->map); return 0; } -- cgit v1.3.1 From 482c76e7c386da683e2fc5b6f939fc8d80a0f186 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:45:58 +0100 Subject: i2c: ihs: Improve error handling Improve the error handling and reporting of the IHS I2C driver. Signed-off-by: Mario Six Reviewed-by: Heiko Schocher --- drivers/i2c/ihs_i2c.c | 67 +++++++++++++++++++++++++++++++++------------------ 1 file changed, 43 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c index 5313490bf3a..f7b59d36f98 100644 --- a/drivers/i2c/ihs_i2c.c +++ b/drivers/i2c/ihs_i2c.c @@ -108,8 +108,10 @@ static int wait_for_int(bool read) while (!(val & (I2CINT_ERROR_EV | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { udelay(10); - if (ctr++ > 5000) - return 1; + if (ctr++ > 5000) { + debug("%s: timed out\n", __func__); + return -ETIMEDOUT; + } #ifdef CONFIG_DM_I2C ihs_i2c_get(priv->map, interrupt_status, &val); #else @@ -117,7 +119,7 @@ static int wait_for_int(bool read) #endif } - return (val & I2CINT_ERROR_EV) ? 1 : 0; + return (val & I2CINT_ERROR_EV) ? -EIO : 0; } #ifdef CONFIG_DM_I2C @@ -130,6 +132,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, { u16 val; u16 data; + int res; #ifdef CONFIG_DM_I2C struct ihs_i2c_priv *priv = dev_get_priv(dev); #endif @@ -170,11 +173,16 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, #endif #ifdef CONFIG_DM_I2C - if (wait_for_int(dev, read)) + res = wait_for_int(dev, read); #else - if (wait_for_int(read)) + res = wait_for_int(read); #endif - return 1; + if (res) { + if (res == -ETIMEDOUT) + debug("%s: time out while waiting for event\n", __func__); + + return res; + } /* If we want to read, get the bytes from the mailbox */ if (read) { @@ -198,19 +206,21 @@ static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus, int read) #endif { + int res; + while (len) { int transfer = min(len, 2); bool is_last = len <= transfer; #ifdef CONFIG_DM_I2C - if (ihs_i2c_transfer(dev, chip, data, transfer, read, - hold_bus ? false : is_last)) - return 1; + res = ihs_i2c_transfer(dev, chip, data, transfer, read, + hold_bus ? false : is_last); #else - if (ihs_i2c_transfer(chip, data, transfer, read, - hold_bus ? false : is_last)) - return 1; + res = ihs_i2c_transfer(chip, data, transfer, read, + hold_bus ? false : is_last); #endif + if (res) + return res; data += transfer; len -= transfer; @@ -241,14 +251,19 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, int alen, uchar *buffer, int len, int read) #endif { + int res; + /* Don't hold the bus if length of data to send/receive is zero */ + if (len <= 0) + return -EINVAL; + #ifdef CONFIG_DM_I2C - if (len <= 0 || ihs_i2c_address(dev, chip, addr, alen, len)) - return 1; + res = ihs_i2c_address(dev, chip, addr, alen, len); #else - if (len <= 0 || ihs_i2c_address(chip, addr, alen, len)) - return 1; + res = ihs_i2c_address(chip, addr, alen, len); #endif + if (res) + return res; #ifdef CONFIG_DM_I2C return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read); @@ -273,7 +288,7 @@ static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed) struct ihs_i2c_priv *priv = dev_get_priv(bus); if (speed != priv->speed && priv->speed != 0) - return 1; + return -EINVAL; priv->speed = speed; @@ -290,8 +305,8 @@ static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) * actucal data) or one message (just data) */ if (nmsgs > 2 || nmsgs == 0) { - debug("%s: Only one or two messages are supported.", __func__); - return -1; + debug("%s: Only one or two messages are supported\n", __func__); + return -ENOTSUPP; } omsg = nmsgs == 1 ? &dummy : msg; @@ -311,9 +326,11 @@ static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr, u32 chip_flags) { uchar buffer[2]; + int res; - if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true)) - return 1; + res = ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true); + if (res) + return res; return 0; } @@ -355,9 +372,11 @@ static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip) { uchar buffer[2]; + int res; - if (ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true)) - return 1; + res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true); + if (res) + return res; return 0; } @@ -388,7 +407,7 @@ static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap, unsigned int speed) { if (speed != adap->speed) - return 1; + return -EINVAL; return speed; } -- cgit v1.3.1 From ca0eab2dcfe5e742a2e663dc10829679879f7b98 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:47:41 +0100 Subject: gdsys_rxaui_ctrl: Return old state Make the gdsys_rxaui_ctrl polarity setting function return the old state to comply with the API requirements. Signed-off-by: Mario Six --- drivers/misc/gdsys_rxaui_ctrl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/misc/gdsys_rxaui_ctrl.c b/drivers/misc/gdsys_rxaui_ctrl.c index 9a63c329bcd..f2c955b13d7 100644 --- a/drivers/misc/gdsys_rxaui_ctrl.c +++ b/drivers/misc/gdsys_rxaui_ctrl.c @@ -29,6 +29,7 @@ struct gdsys_rxaui_ctrl_regs { struct gdsys_rxaui_ctrl_priv { struct regmap *map; + bool state; }; int gdsys_rxaui_set_polarity_inversion(struct udevice *dev, bool val) @@ -36,6 +37,8 @@ int gdsys_rxaui_set_polarity_inversion(struct udevice *dev, bool val) struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev); u16 state; + priv->state = !priv->state; + rxaui_ctrl_get(priv->map, ctrl_1, &state); if (val) @@ -45,7 +48,7 @@ int gdsys_rxaui_set_polarity_inversion(struct udevice *dev, bool val) rxaui_ctrl_set(priv->map, ctrl_1, state); - return 0; + return !priv->state; } static const struct misc_ops gdsys_rxaui_ctrl_ops = { @@ -58,6 +61,8 @@ int gdsys_rxaui_ctrl_probe(struct udevice *dev) regmap_init_mem(dev, &priv->map); + priv->state = false; + return 0; } -- cgit v1.3.1 From 935a89241c97cdd671326c98c43f3833dba96a5b Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 28 Jan 2019 09:47:42 +0100 Subject: gdsys_rxaui_ctrl: Use new regmap interface For the DM case, use the proper parameter for the regmap_init_mem call (which is the ofnode, not the udevice). Signed-off-by: Mario Six --- drivers/misc/gdsys_rxaui_ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/misc/gdsys_rxaui_ctrl.c b/drivers/misc/gdsys_rxaui_ctrl.c index f2c955b13d7..c56abce4d4c 100644 --- a/drivers/misc/gdsys_rxaui_ctrl.c +++ b/drivers/misc/gdsys_rxaui_ctrl.c @@ -59,7 +59,7 @@ int gdsys_rxaui_ctrl_probe(struct udevice *dev) { struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev); - regmap_init_mem(dev, &priv->map); + regmap_init_mem(dev_ofnode(dev), &priv->map); priv->state = false; -- cgit v1.3.1 From 9638879cba99a3736bbae5ba5987e526b7a430d4 Mon Sep 17 00:00:00 2001 From: Mario Six Date: Fri, 29 Mar 2019 10:18:16 +0100 Subject: board: gazerbeam: Fix SC detection The single channel detection in the gazerbeam board driver was not implemented correctly. Fix the detection. Signed-off-by: Mario Six --- drivers/board/gazerbeam.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/board/gazerbeam.c b/drivers/board/gazerbeam.c index 481cce8e809..85de4e440ce 100644 --- a/drivers/board/gazerbeam.c +++ b/drivers/board/gazerbeam.c @@ -61,7 +61,7 @@ static int _read_board_variant_data(struct udevice *dev) struct udevice *i2c_bus; struct udevice *dummy; char *listname; - int mc4, mc2, sc, con; + int mc4, mc2, sc, mc2_sc, con; int gpio_num; int res; @@ -78,16 +78,16 @@ static int _read_board_variant_data(struct udevice *dev) return -EIO; } - mc2 = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy); + mc2_sc = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy); mc4 = !dm_i2c_probe(i2c_bus, MC4_EXPANDER_ADDR, 0, &dummy); - if (mc2 && mc4) { + if (mc2_sc && mc4) { debug("%s: Board hardware configuration inconsistent.\n", dev->name); return -EINVAL; } - listname = mc2 ? "var-gpios-mc2" : "var-gpios-mc4"; + listname = mc2_sc ? "var-gpios-mc2" : "var-gpios-mc4"; gpio_num = gpio_request_list_by_name(dev, listname, priv->var_gpios, ARRAY_SIZE(priv->var_gpios), @@ -105,12 +105,7 @@ static int _read_board_variant_data(struct udevice *dev) return sc; } - con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]); - if (con < 0) { - debug("%s: Error while reading 'con' GPIO (err = %d)", - dev->name, con); - return con; - } + mc2 = mc2_sc ? (sc ? 0 : 1) : 0; if ((sc && mc2) || (sc && mc4) || (!sc && !mc2 && !mc4)) { debug("%s: Board hardware configuration inconsistent.\n", @@ -118,6 +113,13 @@ static int _read_board_variant_data(struct udevice *dev) return -EINVAL; } + con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]); + if (con < 0) { + debug("%s: Error while reading 'con' GPIO (err = %d)", + dev->name, con); + return con; + } + priv->variant = con ? VAR_CON : VAR_CPU; priv->multichannel = mc4 ? 4 : (mc2 ? 2 : (sc ? 1 : 0)); -- cgit v1.3.1