From 89d8c56f44c11d65237c39fced33f95138cd4062 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Wed, 17 May 2023 13:41:24 +0300 Subject: net: rtl8169: add depends on PCI The rtl8169 driver uses calls to dm_pci_bus_to_phys, which are compiled under CONFIG_PCI. Without CONFIG_PCI, this happens: drivers/net/rtl8169.o: in function `rtl_recv_common': drivers/net/rtl8169.c:555: undefined reference to `dm_pci_bus_to_phys' It is only natural that this driver depends on CONFIG_PCI then. The device does not work connected in another way anyway, and the driver does not assume anything else at this moment. Signed-off-by: Eugen Hristev Reviewed-by: Ramon Fried --- drivers/net/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 09039a283eb..39eee98ca79 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -633,6 +633,7 @@ config RTL8139 config RTL8169 bool "Realtek 8169 series Ethernet controller driver" + depends on PCI help This driver supports Realtek 8169 series gigabit ethernet family of PCI/PCIe chipsets/adapters. -- cgit v1.3.1 From 9c9454ac2e4ffd9a8b30744329029f1676d2e7be Mon Sep 17 00:00:00 2001 From: Teik Heng Chong Date: Wed, 21 Jun 2023 11:13:58 +0800 Subject: usb: dwc2: Fix the write to W1C fields in HPRT register Fix the write to the HPRT register which treat W1C fields as if they were mere RW. This leads to unintended clearing of such fields This bug was found during the testing on Simics model. Referring to specification DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG) Databook (3.30a)"5.3.4.8 Host Port Control and Status Register (HPRT)", the HPRT.PrtPwr is cleared by this mistake. In the Linux driver (contrary to U-Boot), HPRT is always read using dwc2_read_hprt0 helper function which clears W1C bits. So after write back those bits are zeroes. Signed-off-by: Teik Heng Chong --- drivers/usb/host/dwc2.c | 34 ++++++++-------------------------- drivers/usb/host/dwc2.h | 4 ++++ 2 files changed, 12 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 23060fc369c..9818f9be94e 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -315,9 +315,7 @@ static void dwc_otg_core_host_init(struct udevice *dev, /* Turn on the vbus power. */ if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { - hprt0 = readl(®s->hprt0); - hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); - hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); + hprt0 = readl(®s->hprt0) & ~DWC2_HPRT0_W1C_MASK; if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { hprt0 |= DWC2_HPRT0_PRTPWR; writel(hprt0, ®s->hprt0); @@ -748,7 +746,7 @@ static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: switch (wValue) { case USB_PORT_FEAT_C_CONNECTION: - setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); + clrsetbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTCONNDET); break; } break; @@ -759,21 +757,13 @@ static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, break; case USB_PORT_FEAT_RESET: - clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | - DWC2_HPRT0_PRTCONNDET | - DWC2_HPRT0_PRTENCHNG | - DWC2_HPRT0_PRTOVRCURRCHNG, - DWC2_HPRT0_PRTRST); + clrsetbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTRST); mdelay(50); - clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); + clrbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK | DWC2_HPRT0_PRTRST); break; case USB_PORT_FEAT_POWER: - clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | - DWC2_HPRT0_PRTCONNDET | - DWC2_HPRT0_PRTENCHNG | - DWC2_HPRT0_PRTOVRCURRCHNG, - DWC2_HPRT0_PRTRST); + clrsetbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTRST); break; case USB_PORT_FEAT_ENABLE: @@ -1213,14 +1203,9 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) dwc_otg_core_host_init(dev, regs); } - clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | - DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | - DWC2_HPRT0_PRTOVRCURRCHNG, - DWC2_HPRT0_PRTRST); + clrsetbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTRST); mdelay(50); - clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | - DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | - DWC2_HPRT0_PRTRST); + clrbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK | DWC2_HPRT0_PRTRST); for (i = 0; i < MAX_DEVICE; i++) { for (j = 0; j < MAX_ENDPOINT; j++) { @@ -1246,10 +1231,7 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) static void dwc2_uninit_common(struct dwc2_core_regs *regs) { /* Put everything in reset. */ - clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | - DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | - DWC2_HPRT0_PRTOVRCURRCHNG, - DWC2_HPRT0_PRTRST); + clrsetbits_le32(®s->hprt0, DWC2_HPRT0_W1C_MASK, DWC2_HPRT0_PRTRST); } #if !CONFIG_IS_ENABLED(DM_USB) diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h index a6f562fe60e..6f022e33a19 100644 --- a/drivers/usb/host/dwc2.h +++ b/drivers/usb/host/dwc2.h @@ -543,6 +543,10 @@ struct dwc2_core_regs { #define DWC2_HPRT0_PRTSPD_LOW (2 << 17) #define DWC2_HPRT0_PRTSPD_MASK (0x3 << 17) #define DWC2_HPRT0_PRTSPD_OFFSET 17 +#define DWC2_HPRT0_W1C_MASK (DWC2_HPRT0_PRTCONNDET | \ + DWC2_HPRT0_PRTENA | \ + DWC2_HPRT0_PRTENCHNG | \ + DWC2_HPRT0_PRTOVRCURRCHNG) #define DWC2_HAINT_CH0 (1 << 0) #define DWC2_HAINT_CH0_OFFSET 0 #define DWC2_HAINT_CH1 (1 << 1) -- cgit v1.3.1 From 3cc537842fefde785cee5dc62fc0b9866c730ae5 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 22 May 2023 11:39:58 +0300 Subject: phy: rockchip: inno-usb2: fix phy reg=0 case The support for #address-cells=2 has a loophole: if the reg is actually 0, but the #address-cells is actually 1, like in such case below: syscon { #address-cells = <1>; phy { reg = <0 0x10>; }; }; then the second u32 of the 'reg' is the size, not the address. The code should check for the parent's #address-cells value, and not assume that if the first u32 is 0, then the #address-cells is 2, and the reg property is something like reg = <0 0xff00 0x10>; Fixed this by looking for the #address-cells value and retrieving the reg address only if this is ==2. To avoid breaking anything I also kept the check `if reg==0` as some DT's may have a wrong #address-cells as parent and even if this commit is correct, it might break the existing wrong device-trees. Fixes: d538efb9adcf ("phy: rockchip: inno-usb2: Add support #address_cells = 2") Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index e43a5ba9b5f..8d6f27735c2 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -259,7 +259,7 @@ static int rockchip_usb2phy_probe(struct udevice *dev) } /* support address_cells=2 */ - if (reg == 0) { + if (dev_read_addr_cells(dev) == 2 && reg == 0) { if (ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, ®)) { dev_err(dev, "%s must have reg[1]\n", ofnode_get_name(dev_ofnode(dev))); -- cgit v1.3.1 From 63348d61a878187a368c0638833efbaf76fc89f9 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 8 Jun 2023 10:59:38 +0000 Subject: pinctrl: rockchip: Fix Data Abort exception in SPL Using CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y and CONFIG_OF_LIVE=y triggers a Data Abort exception from unaligned memory access when the pinctrl driver iterate node properties, e.g. for UART2 on RK3568. setting mux of GPIO0-24 to 1 setting mux of GPIO0-24 to 1 "Synchronous Abort" handler, esr 0x96000021 elr: 000000000000e554 lr : 000000000000e54c x 0: 0000000000000a5c x 1: 0000000000000a5c x 2: 0000000000000007 x 3: 0000000000000065 x 4: 0000000000000007 x 5: 0000000000022d4e x 6: 0000000000000a7c x 7: 00000000000227a4 x 8: 0000000000021cf0 x 9: 0000000000000a7c x10: 0000000000021cf0 x11: 0000000000021cf0 x12: 00000000003fda1c x13: 0000000000000007 x14: 00000000003fd9ec x15: 000000000001c0ff x16: 0000000007000000 x17: 00000000fdccd028 x18: 00000000003fde20 x19: 0000000000000018 x20: 0000000000020670 x21: 0000000000000000 x22: 00000000003fdb00 x23: 00000000003fef90 x24: 0000000000020688 x25: 0000000000000000 x26: 0000000000000001 x27: 00000000003ffc50 x28: 0000000000000000 x29: 00000000003fda60 Code: b94083e1 97ffd508 93407c01 37f81260 (f9401038) Resetting CPU ... Fix this by replacing the loop to access node properties with use of ofnode_for_each_prop instead of the current ifdef. Also continue to next prop instead of aborting at first sign of an unknown property. This fixes the Data Abort exception and also pinconf of e.g. pull and drive in SPL, e.g. for UART2 on RK3568. setting mux of GPIO0-24 to 1 setting mux of GPIO0-24 to 1 setting pull of GPIO0-24 to 5 setting mux of GPIO0-25 to 1 setting mux of GPIO0-25 to 1 setting pull of GPIO0-25 to 5 Fixes: e7ae4cf27a6d ("pinctrl: rockchip: Add common rockchip pinctrl driver") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 28 +++++------------------- 1 file changed, 6 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index d9d61fdb726..8ef089994f4 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -12,7 +12,6 @@ #include #include #include -#include #include "pinctrl-rockchip.h" @@ -433,13 +432,7 @@ static int rockchip_pinctrl_set_state(struct udevice *dev, int prop_len, param; const u32 *data; ofnode node; -#ifdef CONFIG_OF_LIVE - const struct device_node *np; - struct property *pp; -#else - int property_offset, pcfg_node; - const void *blob = gd->fdt_blob; -#endif + struct ofprop prop; data = dev_read_prop(config, "rockchip,pins", &count); if (count < 0) { debug("%s: bad array size %d\n", __func__, count); @@ -473,24 +466,15 @@ static int rockchip_pinctrl_set_state(struct udevice *dev, node = ofnode_get_by_phandle(conf); if (!ofnode_valid(node)) return -ENODEV; -#ifdef CONFIG_OF_LIVE - np = ofnode_to_np(node); - for (pp = np->properties; pp; pp = pp->next) { - prop_name = pp->name; - prop_len = pp->length; - value = pp->value; -#else - pcfg_node = ofnode_to_offset(node); - fdt_for_each_property_offset(property_offset, blob, pcfg_node) { - value = fdt_getprop_by_offset(blob, property_offset, - &prop_name, &prop_len); + ofnode_for_each_prop(prop, node) { + value = ofprop_get_property(&prop, &prop_name, &prop_len); if (!value) - return -ENOENT; -#endif + continue; + param = rockchip_pinconf_prop_name_to_param(prop_name, &default_val); if (param < 0) - break; + continue; if (prop_len >= sizeof(fdt32_t)) arg = fdt32_to_cpu(*(fdt32_t *)value); -- cgit v1.3.1