From 1155d8d853ff8639062651a903ae3062f483dc70 Mon Sep 17 00:00:00 2001
From: Rotariu Marian-Cristian <marian.rotariu@freescale.com>
Date: Mon, 19 May 2014 10:59:52 +0300
Subject: net/fm: call fm_port_to_index() with proper checks

Some of the fm_port_to_index() callers did not check for -1 return value and
used -1 as an array index.

Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---
 drivers/net/fm/fm.h   | 3 ++-
 drivers/net/fm/init.c | 6 ++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 43de114b529..316e06e17e4 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -143,6 +143,7 @@ struct fm_eth {
 #define MAX_RXBUF_LOG2		11
 #define MAX_RXBUF_LEN		(1 << MAX_RXBUF_LOG2)
 
-#define PORT_IS_ENABLED(port)	fm_info[fm_port_to_index(port)].enabled
+#define PORT_IS_ENABLED(port)	(fm_port_to_index(port) == -1 ? \
+	0 : fm_info[fm_port_to_index(port)].enabled)
 
 #endif /* __FM_H__ */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index cd787f4eeda..ff04695c323 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -147,6 +147,9 @@ void fm_disable_port(enum fm_port port)
 {
 	int i = fm_port_to_index(port);
 
+	if (i == -1)
+		return;
+
 	fm_info[i].enabled = 0;
 	fman_disable_port(port);
 }
@@ -155,6 +158,9 @@ void fm_enable_port(enum fm_port port)
 {
 	int i = fm_port_to_index(port);
 
+	if (i == -1)
+		return;
+
 	fm_info[i].enabled = 1;
 	fman_enable_port(port);
 }
-- 
cgit v1.3.1


From 38d67a4e552ac991f21c2d3e442a38fb0098fda6 Mon Sep 17 00:00:00 2001
From: Zhao Qiang <B45475@freescale.com>
Date: Tue, 3 Jun 2014 16:27:07 +0800
Subject: qe: move immap_qe.h from arch directory into common directory

ls1021 is arm-core and supports qe too.
Move immap_qe.h into common directory for both arm and powerpc.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc83xx/cpu.c      |   2 +-
 arch/powerpc/cpu/mpc83xx/fdt.c      |   2 +-
 arch/powerpc/include/asm/immap_qe.h | 582 ------------------------------------
 drivers/bootcount/bootcount.c       |   2 +-
 drivers/qe/qe.c                     |   2 +-
 drivers/qe/uccf.c                   |   2 +-
 drivers/qe/uccf.h                   |   2 +-
 drivers/qe/uec.c                    |   2 +-
 drivers/qe/uec_phy.c                |   2 +-
 include/linux/immap_qe.h            | 582 ++++++++++++++++++++++++++++++++++++
 include/post.h                      |   2 +-
 11 files changed, 591 insertions(+), 591 deletions(-)
 delete mode 100644 arch/powerpc/include/asm/immap_qe.h
 create mode 100644 include/linux/immap_qe.h

(limited to 'drivers')

diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index e41988d5fad..38093097e47 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -20,7 +20,7 @@
 #include <netdev.h>
 #include <fsl_esdhc.h>
 #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
-#include <asm/immap_qe.h>
+#include <linux/immap_qe.h>
 #include <asm/io.h>
 #endif
 
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c
index 450a9704e5b..f249a585edf 100644
--- a/arch/powerpc/cpu/mpc83xx/fdt.c
+++ b/arch/powerpc/cpu/mpc83xx/fdt.c
@@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_BOOTCOUNT_LIMIT) && \
 	(defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
-#include <asm/immap_qe.h>
+#include <linux/immap_qe.h>
 
 void fdt_fixup_muram (void *blob)
 {
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
deleted file mode 100644
index b317dcb5fe8..00000000000
--- a/arch/powerpc/include/asm/immap_qe.h
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * QUICC Engine (QE) Internal Memory Map.
- * The Internal Memory Map for devices with QE on them. This
- * is the superset of all QE devices (8360, etc.).
- *
- * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc.
- * Author: Shlomi Gridih <gridish@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __IMMAP_QE_H__
-#define __IMMAP_QE_H__
-
-#ifdef CONFIG_MPC83xx
-#if defined(CONFIG_MPC8360)
-#define QE_MURAM_SIZE		0xc000UL
-#define MAX_QE_RISC		2
-#define QE_NUM_OF_SNUM		28
-#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
-#define QE_MURAM_SIZE		0x4000UL
-#define MAX_QE_RISC		1
-#define QE_NUM_OF_SNUM		28
-#endif
-#endif
-
-/* QE I-RAM */
-typedef struct qe_iram {
-	u32 iadd;		/* I-RAM Address Register */
-	u32 idata;		/* I-RAM Data Register    */
-	u8 res0[0x4];
-	u32 iready;
-	u8 res1[0x70];
-} __attribute__ ((packed)) qe_iram_t;
-
-/* QE Interrupt Controller */
-typedef struct qe_ic {
-	u32 qicr;
-	u32 qivec;
-	u32 qripnr;
-	u32 qipnr;
-	u32 qipxcc;
-	u32 qipycc;
-	u32 qipwcc;
-	u32 qipzcc;
-	u32 qimr;
-	u32 qrimr;
-	u32 qicnr;
-	u8 res0[0x4];
-	u32 qiprta;
-	u32 qiprtb;
-	u8 res1[0x4];
-	u32 qricr;
-	u8 res2[0x20];
-	u32 qhivec;
-	u8 res3[0x1C];
-} __attribute__ ((packed)) qe_ic_t;
-
-/* Communications Processor */
-typedef struct cp_qe {
-	u32 cecr;		/* QE command register */
-	u32 ceccr;		/* QE controller configuration register */
-	u32 cecdr;		/* QE command data register */
-	u8 res0[0xA];
-	u16 ceter;		/* QE timer event register */
-	u8 res1[0x2];
-	u16 cetmr;		/* QE timers mask register */
-	u32 cetscr;		/* QE time-stamp timer control register */
-	u32 cetsr1;		/* QE time-stamp register 1 */
-	u32 cetsr2;		/* QE time-stamp register 2 */
-	u8 res2[0x8];
-	u32 cevter;		/* QE virtual tasks event register */
-	u32 cevtmr;		/* QE virtual tasks mask register */
-	u16 cercr;		/* QE RAM control register */
-	u8 res3[0x2];
-	u8 res4[0x24];
-	u16 ceexe1;		/* QE external request 1 event register */
-	u8 res5[0x2];
-	u16 ceexm1;		/* QE external request 1 mask register */
-	u8 res6[0x2];
-	u16 ceexe2;		/* QE external request 2 event register */
-	u8 res7[0x2];
-	u16 ceexm2;		/* QE external request 2 mask register */
-	u8 res8[0x2];
-	u16 ceexe3;		/* QE external request 3 event register */
-	u8 res9[0x2];
-	u16 ceexm3;		/* QE external request 3 mask register */
-	u8 res10[0x2];
-	u16 ceexe4;		/* QE external request 4 event register */
-	u8 res11[0x2];
-	u16 ceexm4;		/* QE external request 4 mask register */
-	u8 res12[0x2];
-	u8 res13[0x280];
-} __attribute__ ((packed)) cp_qe_t;
-
-/* QE Multiplexer */
-typedef struct qe_mux {
-	u32 cmxgcr;		/* CMX general clock route register    */
-	u32 cmxsi1cr_l;		/* CMX SI1 clock route low register    */
-	u32 cmxsi1cr_h;		/* CMX SI1 clock route high register   */
-	u32 cmxsi1syr;		/* CMX SI1 SYNC route register         */
-	u32 cmxucr1;		/* CMX UCC1, UCC3 clock route register */
-	u32 cmxucr2;		/* CMX UCC5, UCC7 clock route register */
-	u32 cmxucr3;		/* CMX UCC2, UCC4 clock route register */
-	u32 cmxucr4;		/* CMX UCC6, UCC8 clock route register */
-	u32 cmxupcr;		/* CMX UPC clock route register        */
-	u8 res0[0x1C];
-} __attribute__ ((packed)) qe_mux_t;
-
-/* QE Timers */
-typedef struct qe_timers {
-	u8 gtcfr1;		/* Timer 1 2 global configuration register */
-	u8 res0[0x3];
-	u8 gtcfr2;		/* Timer 3 4 global configuration register */
-	u8 res1[0xB];
-	u16 gtmdr1;		/* Timer 1 mode register */
-	u16 gtmdr2;		/* Timer 2 mode register */
-	u16 gtrfr1;		/* Timer 1 reference register */
-	u16 gtrfr2;		/* Timer 2 reference register */
-	u16 gtcpr1;		/* Timer 1 capture register */
-	u16 gtcpr2;		/* Timer 2 capture register */
-	u16 gtcnr1;		/* Timer 1 counter */
-	u16 gtcnr2;		/* Timer 2 counter */
-	u16 gtmdr3;		/* Timer 3 mode register */
-	u16 gtmdr4;		/* Timer 4 mode register */
-	u16 gtrfr3;		/* Timer 3 reference register */
-	u16 gtrfr4;		/* Timer 4 reference register */
-	u16 gtcpr3;		/* Timer 3 capture register */
-	u16 gtcpr4;		/* Timer 4 capture register */
-	u16 gtcnr3;		/* Timer 3 counter */
-	u16 gtcnr4;		/* Timer 4 counter */
-	u16 gtevr1;		/* Timer 1 event register */
-	u16 gtevr2;		/* Timer 2 event register */
-	u16 gtevr3;		/* Timer 3 event register */
-	u16 gtevr4;		/* Timer 4 event register */
-	u16 gtps;		/* Timer 1 prescale register */
-	u8 res2[0x46];
-} __attribute__ ((packed)) qe_timers_t;
-
-/* BRG */
-typedef struct qe_brg {
-	u32 brgc1;		/* BRG1 configuration register  */
-	u32 brgc2;		/* BRG2 configuration register  */
-	u32 brgc3;		/* BRG3 configuration register  */
-	u32 brgc4;		/* BRG4 configuration register  */
-	u32 brgc5;		/* BRG5 configuration register  */
-	u32 brgc6;		/* BRG6 configuration register  */
-	u32 brgc7;		/* BRG7 configuration register  */
-	u32 brgc8;		/* BRG8 configuration register  */
-	u32 brgc9;		/* BRG9 configuration register  */
-	u32 brgc10;		/* BRG10 configuration register */
-	u32 brgc11;		/* BRG11 configuration register */
-	u32 brgc12;		/* BRG12 configuration register */
-	u32 brgc13;		/* BRG13 configuration register */
-	u32 brgc14;		/* BRG14 configuration register */
-	u32 brgc15;		/* BRG15 configuration register */
-	u32 brgc16;		/* BRG16 configuration register */
-	u8 res0[0x40];
-} __attribute__ ((packed)) qe_brg_t;
-
-/* SPI */
-typedef struct spi {
-	u8 res0[0x20];
-	u32 spmode;		/* SPI mode register */
-	u8 res1[0x2];
-	u8 spie;		/* SPI event register */
-	u8 res2[0x1];
-	u8 res3[0x2];
-	u8 spim;		/* SPI mask register */
-	u8 res4[0x1];
-	u8 res5[0x1];
-	u8 spcom;		/* SPI command register  */
-	u8 res6[0x2];
-	u32 spitd;		/* SPI transmit data register (cpu mode) */
-	u32 spird;		/* SPI receive data register (cpu mode) */
-	u8 res7[0x8];
-} __attribute__ ((packed)) spi_t;
-
-/* SI */
-typedef struct si1 {
-	u16 siamr1;		/* SI1 TDMA mode register */
-	u16 sibmr1;		/* SI1 TDMB mode register */
-	u16 sicmr1;		/* SI1 TDMC mode register */
-	u16 sidmr1;		/* SI1 TDMD mode register */
-	u8 siglmr1_h;		/* SI1 global mode register high */
-	u8 res0[0x1];
-	u8 sicmdr1_h;		/* SI1 command register high */
-	u8 res2[0x1];
-	u8 sistr1_h;		/* SI1 status register high */
-	u8 res3[0x1];
-	u16 sirsr1_h;		/* SI1 RAM shadow address register high */
-	u8 sitarc1;		/* SI1 RAM counter Tx TDMA */
-	u8 sitbrc1;		/* SI1 RAM counter Tx TDMB */
-	u8 sitcrc1;		/* SI1 RAM counter Tx TDMC */
-	u8 sitdrc1;		/* SI1 RAM counter Tx TDMD */
-	u8 sirarc1;		/* SI1 RAM counter Rx TDMA */
-	u8 sirbrc1;		/* SI1 RAM counter Rx TDMB */
-	u8 sircrc1;		/* SI1 RAM counter Rx TDMC */
-	u8 sirdrc1;		/* SI1 RAM counter Rx TDMD */
-	u8 res4[0x8];
-	u16 siemr1;		/* SI1 TDME mode register 16 bits */
-	u16 sifmr1;		/* SI1 TDMF mode register 16 bits */
-	u16 sigmr1;		/* SI1 TDMG mode register 16 bits */
-	u16 sihmr1;		/* SI1 TDMH mode register 16 bits */
-	u8 siglmg1_l;		/* SI1 global mode register low 8 bits */
-	u8 res5[0x1];
-	u8 sicmdr1_l;		/* SI1 command register low 8 bits */
-	u8 res6[0x1];
-	u8 sistr1_l;		/* SI1 status register low 8 bits */
-	u8 res7[0x1];
-	u16 sirsr1_l;		/* SI1 RAM shadow address register low 16 bits */
-	u8 siterc1;		/* SI1 RAM counter Tx TDME 8 bits */
-	u8 sitfrc1;		/* SI1 RAM counter Tx TDMF 8 bits */
-	u8 sitgrc1;		/* SI1 RAM counter Tx TDMG 8 bits */
-	u8 sithrc1;		/* SI1 RAM counter Tx TDMH 8 bits */
-	u8 sirerc1;		/* SI1 RAM counter Rx TDME 8 bits */
-	u8 sirfrc1;		/* SI1 RAM counter Rx TDMF 8 bits */
-	u8 sirgrc1;		/* SI1 RAM counter Rx TDMG 8 bits */
-	u8 sirhrc1;		/* SI1 RAM counter Rx TDMH 8 bits */
-	u8 res8[0x8];
-	u32 siml1;		/* SI1 multiframe limit register */
-	u8 siedm1;		/* SI1 extended diagnostic mode register */
-	u8 res9[0xBB];
-} __attribute__ ((packed)) si1_t;
-
-/* SI Routing Tables */
-typedef struct sir {
-	u8 tx[0x400];
-	u8 rx[0x400];
-	u8 res0[0x800];
-} __attribute__ ((packed)) sir_t;
-
-/* USB Controller.  */
-typedef struct usb_ctlr {
-	u8 usb_usmod;
-	u8 usb_usadr;
-	u8 usb_uscom;
-	u8 res1[1];
-	u16 usb_usep1;
-	u16 usb_usep2;
-	u16 usb_usep3;
-	u16 usb_usep4;
-	u8 res2[4];
-	u16 usb_usber;
-	u8 res3[2];
-	u16 usb_usbmr;
-	u8 res4[1];
-	u8 usb_usbs;
-	u16 usb_ussft;
-	u8 res5[2];
-	u16 usb_usfrn;
-	u8 res6[0x22];
-} __attribute__ ((packed)) usb_t;
-
-/* MCC */
-typedef struct mcc {
-	u32 mcce;		/* MCC event register */
-	u32 mccm;		/* MCC mask register */
-	u32 mccf;		/* MCC configuration register */
-	u32 merl;		/* MCC emergency request level register */
-	u8 res0[0xF0];
-} __attribute__ ((packed)) mcc_t;
-
-/* QE UCC Slow */
-typedef struct ucc_slow {
-	u32 gumr_l;		/* UCCx general mode register (low) */
-	u32 gumr_h;		/* UCCx general mode register (high) */
-	u16 upsmr;		/* UCCx protocol-specific mode register */
-	u8 res0[0x2];
-	u16 utodr;		/* UCCx transmit on demand register */
-	u16 udsr;		/* UCCx data synchronization register */
-	u16 ucce;		/* UCCx event register */
-	u8 res1[0x2];
-	u16 uccm;		/* UCCx mask register */
-	u8 res2[0x1];
-	u8 uccs;		/* UCCx status register */
-	u8 res3[0x24];
-	u16 utpt;
-	u8 guemr;		/* UCC general extended mode register */
-	u8 res4[0x200 - 0x091];
-} __attribute__ ((packed)) ucc_slow_t;
-
-typedef struct ucc_mii_mng {
-	u32 miimcfg;		/* MII management configuration reg    */
-	u32 miimcom;		/* MII management command reg          */
-	u32 miimadd;		/* MII management address reg          */
-	u32 miimcon;		/* MII management control reg          */
-	u32 miimstat;		/* MII management status reg           */
-	u32 miimind;		/* MII management indication reg       */
-	u32 ifctl;		/* interface control reg               */
-	u32 ifstat;		/* interface statux reg                */
-} __attribute__ ((packed))uec_mii_t;
-
-typedef struct ucc_ethernet {
-	u32 maccfg1;		/* mac configuration reg. 1            */
-	u32 maccfg2;		/* mac configuration reg. 2            */
-	u32 ipgifg;		/* interframe gap reg.                 */
-	u32 hafdup;		/* half-duplex reg.                    */
-	u8 res1[0x10];
-	u32 miimcfg;		/* MII management configuration reg    */
-	u32 miimcom;		/* MII management command reg          */
-	u32 miimadd;		/* MII management address reg          */
-	u32 miimcon;		/* MII management control reg          */
-	u32 miimstat;		/* MII management status reg           */
-	u32 miimind;		/* MII management indication reg       */
-	u32 ifctl;		/* interface control reg               */
-	u32 ifstat;		/* interface statux reg                */
-	u32 macstnaddr1;	/* mac station address part 1 reg      */
-	u32 macstnaddr2;	/* mac station address part 2 reg      */
-	u8 res2[0x8];
-	u32 uempr;		/* UCC Ethernet Mac parameter reg      */
-	u32 utbipar;		/* UCC tbi address reg                 */
-	u16 uescr;		/* UCC Ethernet statistics control reg */
-	u8 res3[0x180 - 0x15A];
-	u32 tx64;		/* Total number of frames (including bad
-				 * frames) transmitted that were exactly
-				 * of the minimal length (64 for un tagged,
-				 * 68 for tagged, or with length exactly
-				 * equal to the parameter MINLength */
-	u32 tx127;		/* Total number of frames (including bad
-				 * frames) transmitted that were between
-				 * MINLength (Including FCS length==4)
-				 * and 127 octets */
-	u32 tx255;		/* Total number of frames (including bad
-				 * frames) transmitted that were between
-				 * 128 (Including FCS length==4) and 255
-				 * octets */
-	u32 rx64;		/* Total number of frames received including
-				 * bad frames that were exactly of the
-				 * mninimal length (64 bytes) */
-	u32 rx127;		/* Total number of frames (including bad
-				 * frames) received that were between
-				 * MINLength (Including FCS length==4)
-				 * and 127 octets */
-	u32 rx255;		/* Total number of frames (including
-				 * bad frames) received that were between
-				 * 128 (Including FCS length==4) and 255
-				 * octets */
-	u32 txok;		/* Total number of octets residing in frames
-				 * that where involved in succesfull
-				 * transmission */
-	u16 txcf;		/* Total number of PAUSE control frames
-				 *  transmitted by this MAC */
-	u8 res4[0x2];
-	u32 tmca;		/* Total number of frames that were transmitted
-				 * succesfully with the group address bit set
-				 * that are not broadcast frames */
-	u32 tbca;		/* Total number of frames transmitted
-				 * succesfully that had destination address
-				 * field equal to the broadcast address */
-	u32 rxfok;		/* Total number of frames received OK */
-	u32 rxbok;		/* Total number of octets received OK */
-	u32 rbyt;		/* Total number of octets received including
-				 * octets in bad frames. Must be implemented
-				 * in HW because it includes octets in frames
-				 * that never even reach the UCC */
-	u32 rmca;		/* Total number of frames that were received
-				 * succesfully with the group address bit set
-				 * that are not broadcast frames */
-	u32 rbca;		/* Total number of frames received succesfully
-				 * that had destination address equal to the
-				 * broadcast address */
-	u32 scar;		/* Statistics carry register */
-	u32 scam;		/* Statistics caryy mask register */
-	u8 res5[0x200 - 0x1c4];
-} __attribute__ ((packed)) uec_t;
-
-/* QE UCC Fast */
-typedef struct ucc_fast {
-	u32 gumr;		/* UCCx general mode register */
-	u32 upsmr;		/* UCCx protocol-specific mode register  */
-	u16 utodr;		/* UCCx transmit on demand register  */
-	u8 res0[0x2];
-	u16 udsr;		/* UCCx data synchronization register  */
-	u8 res1[0x2];
-	u32 ucce;		/* UCCx event register */
-	u32 uccm;		/* UCCx mask register.  */
-	u8 uccs;		/* UCCx status register */
-	u8 res2[0x7];
-	u32 urfb;		/* UCC receive FIFO base */
-	u16 urfs;		/* UCC receive FIFO size */
-	u8 res3[0x2];
-	u16 urfet;		/* UCC receive FIFO emergency threshold */
-	u16 urfset;		/* UCC receive FIFO special emergency
-				 * threshold */
-	u32 utfb;		/* UCC transmit FIFO base */
-	u16 utfs;		/* UCC transmit FIFO size */
-	u8 res4[0x2];
-	u16 utfet;		/* UCC transmit FIFO emergency threshold */
-	u8 res5[0x2];
-	u16 utftt;		/* UCC transmit FIFO transmit threshold */
-	u8 res6[0x2];
-	u16 utpt;		/* UCC transmit polling timer */
-	u8 res7[0x2];
-	u32 urtry;		/* UCC retry counter register */
-	u8 res8[0x4C];
-	u8 guemr;		/* UCC general extended mode register */
-	u8 res9[0x100 - 0x091];
-	uec_t ucc_eth;
-} __attribute__ ((packed)) ucc_fast_t;
-
-/* QE UCC */
-typedef struct ucc_common {
-	u8 res1[0x90];
-	u8 guemr;
-	u8 res2[0x200 - 0x091];
-} __attribute__ ((packed)) ucc_common_t;
-
-typedef struct ucc {
-	union {
-		ucc_slow_t slow;
-		ucc_fast_t fast;
-		ucc_common_t common;
-	};
-} __attribute__ ((packed)) ucc_t;
-
-/* MultiPHY UTOPIA POS Controllers (UPC) */
-typedef struct upc {
-	u32 upgcr;		/* UTOPIA/POS general configuration register */
-	u32 uplpa;		/* UTOPIA/POS last PHY address */
-	u32 uphec;		/* ATM HEC register */
-	u32 upuc;		/* UTOPIA/POS UCC configuration */
-	u32 updc1;		/* UTOPIA/POS device 1 configuration */
-	u32 updc2;		/* UTOPIA/POS device 2 configuration  */
-	u32 updc3;		/* UTOPIA/POS device 3 configuration */
-	u32 updc4;		/* UTOPIA/POS device 4 configuration  */
-	u32 upstpa;		/* UTOPIA/POS STPA threshold  */
-	u8 res0[0xC];
-	u32 updrs1_h;		/* UTOPIA/POS device 1 rate select  */
-	u32 updrs1_l;		/* UTOPIA/POS device 1 rate select  */
-	u32 updrs2_h;		/* UTOPIA/POS device 2 rate select  */
-	u32 updrs2_l;		/* UTOPIA/POS device 2 rate select */
-	u32 updrs3_h;		/* UTOPIA/POS device 3 rate select */
-	u32 updrs3_l;		/* UTOPIA/POS device 3 rate select */
-	u32 updrs4_h;		/* UTOPIA/POS device 4 rate select */
-	u32 updrs4_l;		/* UTOPIA/POS device 4 rate select */
-	u32 updrp1;		/* UTOPIA/POS device 1 receive priority low  */
-	u32 updrp2;		/* UTOPIA/POS device 2 receive priority low  */
-	u32 updrp3;		/* UTOPIA/POS device 3 receive priority low  */
-	u32 updrp4;		/* UTOPIA/POS device 4 receive priority low  */
-	u32 upde1;		/* UTOPIA/POS device 1 event */
-	u32 upde2;		/* UTOPIA/POS device 2 event */
-	u32 upde3;		/* UTOPIA/POS device 3 event */
-	u32 upde4;		/* UTOPIA/POS device 4 event */
-	u16 uprp1;
-	u16 uprp2;
-	u16 uprp3;
-	u16 uprp4;
-	u8 res1[0x8];
-	u16 uptirr1_0;		/* Device 1 transmit internal rate 0 */
-	u16 uptirr1_1;		/* Device 1 transmit internal rate 1 */
-	u16 uptirr1_2;		/* Device 1 transmit internal rate 2 */
-	u16 uptirr1_3;		/* Device 1 transmit internal rate 3 */
-	u16 uptirr2_0;		/* Device 2 transmit internal rate 0 */
-	u16 uptirr2_1;		/* Device 2 transmit internal rate 1 */
-	u16 uptirr2_2;		/* Device 2 transmit internal rate 2 */
-	u16 uptirr2_3;		/* Device 2 transmit internal rate 3 */
-	u16 uptirr3_0;		/* Device 3 transmit internal rate 0 */
-	u16 uptirr3_1;		/* Device 3 transmit internal rate 1 */
-	u16 uptirr3_2;		/* Device 3 transmit internal rate 2 */
-	u16 uptirr3_3;		/* Device 3 transmit internal rate 3 */
-	u16 uptirr4_0;		/* Device 4 transmit internal rate 0 */
-	u16 uptirr4_1;		/* Device 4 transmit internal rate 1 */
-	u16 uptirr4_2;		/* Device 4 transmit internal rate 2 */
-	u16 uptirr4_3;		/* Device 4 transmit internal rate 3 */
-	u32 uper1;		/* Device 1 port enable register */
-	u32 uper2;		/* Device 2 port enable register */
-	u32 uper3;		/* Device 3 port enable register */
-	u32 uper4;		/* Device 4 port enable register */
-	u8 res2[0x150];
-} __attribute__ ((packed)) upc_t;
-
-/* SDMA */
-typedef struct sdma {
-	u32 sdsr;		/* Serial DMA status register */
-	u32 sdmr;		/* Serial DMA mode register */
-	u32 sdtr1;		/* SDMA system bus threshold register */
-	u32 sdtr2;		/* SDMA secondary bus threshold register */
-	u32 sdhy1;		/* SDMA system bus hysteresis register */
-	u32 sdhy2;		/* SDMA secondary bus hysteresis register */
-	u32 sdta1;		/* SDMA system bus address register */
-	u32 sdta2;		/* SDMA secondary bus address register */
-	u32 sdtm1;		/* SDMA system bus MSNUM register */
-	u32 sdtm2;		/* SDMA secondary bus MSNUM register */
-	u8 res0[0x10];
-	u32 sdaqr;		/* SDMA address bus qualify register */
-	u32 sdaqmr;		/* SDMA address bus qualify mask register */
-	u8 res1[0x4];
-	u32 sdwbcr;		/* SDMA CAM entries base register */
-	u8 res2[0x38];
-} __attribute__ ((packed)) sdma_t;
-
-/* Debug Space */
-typedef struct dbg {
-	u32 bpdcr;		/* Breakpoint debug command register */
-	u32 bpdsr;		/* Breakpoint debug status register */
-	u32 bpdmr;		/* Breakpoint debug mask register */
-	u32 bprmrr0;		/* Breakpoint request mode risc register 0 */
-	u32 bprmrr1;		/* Breakpoint request mode risc register 1 */
-	u8 res0[0x8];
-	u32 bprmtr0;		/* Breakpoint request mode trb register 0 */
-	u32 bprmtr1;		/* Breakpoint request mode trb register 1 */
-	u8 res1[0x8];
-	u32 bprmir;		/* Breakpoint request mode immediate register */
-	u32 bprmsr;		/* Breakpoint request mode serial register */
-	u32 bpemr;		/* Breakpoint exit mode register */
-	u8 res2[0x48];
-} __attribute__ ((packed)) dbg_t;
-
-/*
- * RISC Special Registers (Trap and Breakpoint).  These are described in
- * the QE Developer's Handbook.
-*/
-typedef struct rsp {
-	u32 tibcr[16];	/* Trap/instruction breakpoint control regs */
-	u8 res0[64];
-	u32 ibcr0;
-	u32 ibs0;
-	u32 ibcnr0;
-	u8 res1[4];
-	u32 ibcr1;
-	u32 ibs1;
-	u32 ibcnr1;
-	u32 npcr;
-	u32 dbcr;
-	u32 dbar;
-	u32 dbamr;
-	u32 dbsr;
-	u32 dbcnr;
-	u8 res2[12];
-	u32 dbdr_h;
-	u32 dbdr_l;
-	u32 dbdmr_h;
-	u32 dbdmr_l;
-	u32 bsr;
-	u32 bor;
-	u32 bior;
-	u8 res3[4];
-	u32 iatr[4];
-	u32 eccr;		/* Exception control configuration register */
-	u32 eicr;
-	u8 res4[0x100-0xf8];
-} __attribute__ ((packed)) rsp_t;
-
-typedef struct qe_immap {
-	qe_iram_t iram;		/* I-RAM */
-	qe_ic_t ic;		/* Interrupt Controller */
-	cp_qe_t cp;		/* Communications Processor */
-	qe_mux_t qmx;		/* QE Multiplexer */
-	qe_timers_t qet;	/* QE Timers */
-	spi_t spi[0x2];		/* spi  */
-	mcc_t mcc;		/* mcc */
-	qe_brg_t brg;		/* brg */
-	usb_t usb;		/* USB */
-	si1_t si1;		/* SI */
-	u8 res11[0x800];
-	sir_t sir;		/* SI Routing Tables  */
-	ucc_t ucc1;		/* ucc1 */
-	ucc_t ucc3;		/* ucc3 */
-	ucc_t ucc5;		/* ucc5 */
-	ucc_t ucc7;		/* ucc7 */
-	u8 res12[0x600];
-	upc_t upc1;		/* MultiPHY UTOPIA POS Controller 1 */
-	ucc_t ucc2;		/* ucc2 */
-	ucc_t ucc4;		/* ucc4 */
-	ucc_t ucc6;		/* ucc6 */
-	ucc_t ucc8;		/* ucc8 */
-	u8 res13[0x600];
-	upc_t upc2;		/* MultiPHY UTOPIA POS Controller 2 */
-	sdma_t sdma;		/* SDMA */
-	dbg_t dbg;		/* Debug Space */
-	rsp_t rsp[0x2];		/* RISC Special Registers
-				 * (Trap and Breakpoint) */
-	u8 res14[0x300];
-	u8 res15[0x3A00];
-	u8 res16[0x8000];	/* 0x108000 -  0x110000 */
-	u8 muram[QE_MURAM_SIZE];
-} __attribute__ ((packed)) qe_map_t;
-
-extern qe_map_t *qe_immr;
-
-#endif				/* __IMMAP_QE_H__ */
diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c
index 3ad441393e1..e0343f71d7f 100644
--- a/drivers/bootcount/bootcount.c
+++ b/drivers/bootcount/bootcount.c
@@ -36,7 +36,7 @@
 #endif /* defined(CONFIG_MPC8260) */
 
 #if defined(CONFIG_QE)
-#include <asm/immap_qe.h>
+#include <linux/immap_qe.h>
 
 #define CONFIG_SYS_BOOTCOUNT_ADDR	(CONFIG_SYS_IMMR + 0x110000 + \
 					 QE_MURAM_SIZE - 2 * sizeof(u32))
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 9c5fbd1d694..be09a17297c 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -11,7 +11,7 @@
 #include <command.h>
 #include "asm/errno.h"
 #include "asm/io.h"
-#include "asm/immap_qe.h"
+#include "linux/immap_qe.h"
 #include "qe.h"
 
 #define MPC85xx_DEVDISR_QE_DISABLE	0x1
diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c
index 593d96d1a26..85386bfc708 100644
--- a/drivers/qe/uccf.c
+++ b/drivers/qe/uccf.c
@@ -11,7 +11,7 @@
 #include "malloc.h"
 #include "asm/errno.h"
 #include "asm/io.h"
-#include "asm/immap_qe.h"
+#include "linux/immap_qe.h"
 #include "qe.h"
 #include "uccf.h"
 
diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h
index 0b57e2f4228..55941e4601a 100644
--- a/drivers/qe/uccf.h
+++ b/drivers/qe/uccf.h
@@ -12,7 +12,7 @@
 
 #include "common.h"
 #include "qe.h"
-#include "asm/immap_qe.h"
+#include "linux/immap_qe.h"
 
 /* Fast or Giga ethernet
 */
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 68045733b8b..c91f084a7c7 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -11,7 +11,7 @@
 #include "malloc.h"
 #include "asm/errno.h"
 #include "asm/io.h"
-#include "asm/immap_qe.h"
+#include "linux/immap_qe.h"
 #include "qe.h"
 #include "uccf.h"
 #include "uec.h"
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 5dc4641bf6b..e701787c41a 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -14,7 +14,7 @@
 #include "net.h"
 #include "malloc.h"
 #include "asm/errno.h"
-#include "asm/immap_qe.h"
+#include "linux/immap_qe.h"
 #include "asm/io.h"
 #include "qe.h"
 #include "uccf.h"
diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h
new file mode 100644
index 00000000000..b317dcb5fe8
--- /dev/null
+++ b/include/linux/immap_qe.h
@@ -0,0 +1,582 @@
+/*
+ * QUICC Engine (QE) Internal Memory Map.
+ * The Internal Memory Map for devices with QE on them. This
+ * is the superset of all QE devices (8360, etc.).
+ *
+ * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc.
+ * Author: Shlomi Gridih <gridish@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IMMAP_QE_H__
+#define __IMMAP_QE_H__
+
+#ifdef CONFIG_MPC83xx
+#if defined(CONFIG_MPC8360)
+#define QE_MURAM_SIZE		0xc000UL
+#define MAX_QE_RISC		2
+#define QE_NUM_OF_SNUM		28
+#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
+#define QE_MURAM_SIZE		0x4000UL
+#define MAX_QE_RISC		1
+#define QE_NUM_OF_SNUM		28
+#endif
+#endif
+
+/* QE I-RAM */
+typedef struct qe_iram {
+	u32 iadd;		/* I-RAM Address Register */
+	u32 idata;		/* I-RAM Data Register    */
+	u8 res0[0x4];
+	u32 iready;
+	u8 res1[0x70];
+} __attribute__ ((packed)) qe_iram_t;
+
+/* QE Interrupt Controller */
+typedef struct qe_ic {
+	u32 qicr;
+	u32 qivec;
+	u32 qripnr;
+	u32 qipnr;
+	u32 qipxcc;
+	u32 qipycc;
+	u32 qipwcc;
+	u32 qipzcc;
+	u32 qimr;
+	u32 qrimr;
+	u32 qicnr;
+	u8 res0[0x4];
+	u32 qiprta;
+	u32 qiprtb;
+	u8 res1[0x4];
+	u32 qricr;
+	u8 res2[0x20];
+	u32 qhivec;
+	u8 res3[0x1C];
+} __attribute__ ((packed)) qe_ic_t;
+
+/* Communications Processor */
+typedef struct cp_qe {
+	u32 cecr;		/* QE command register */
+	u32 ceccr;		/* QE controller configuration register */
+	u32 cecdr;		/* QE command data register */
+	u8 res0[0xA];
+	u16 ceter;		/* QE timer event register */
+	u8 res1[0x2];
+	u16 cetmr;		/* QE timers mask register */
+	u32 cetscr;		/* QE time-stamp timer control register */
+	u32 cetsr1;		/* QE time-stamp register 1 */
+	u32 cetsr2;		/* QE time-stamp register 2 */
+	u8 res2[0x8];
+	u32 cevter;		/* QE virtual tasks event register */
+	u32 cevtmr;		/* QE virtual tasks mask register */
+	u16 cercr;		/* QE RAM control register */
+	u8 res3[0x2];
+	u8 res4[0x24];
+	u16 ceexe1;		/* QE external request 1 event register */
+	u8 res5[0x2];
+	u16 ceexm1;		/* QE external request 1 mask register */
+	u8 res6[0x2];
+	u16 ceexe2;		/* QE external request 2 event register */
+	u8 res7[0x2];
+	u16 ceexm2;		/* QE external request 2 mask register */
+	u8 res8[0x2];
+	u16 ceexe3;		/* QE external request 3 event register */
+	u8 res9[0x2];
+	u16 ceexm3;		/* QE external request 3 mask register */
+	u8 res10[0x2];
+	u16 ceexe4;		/* QE external request 4 event register */
+	u8 res11[0x2];
+	u16 ceexm4;		/* QE external request 4 mask register */
+	u8 res12[0x2];
+	u8 res13[0x280];
+} __attribute__ ((packed)) cp_qe_t;
+
+/* QE Multiplexer */
+typedef struct qe_mux {
+	u32 cmxgcr;		/* CMX general clock route register    */
+	u32 cmxsi1cr_l;		/* CMX SI1 clock route low register    */
+	u32 cmxsi1cr_h;		/* CMX SI1 clock route high register   */
+	u32 cmxsi1syr;		/* CMX SI1 SYNC route register         */
+	u32 cmxucr1;		/* CMX UCC1, UCC3 clock route register */
+	u32 cmxucr2;		/* CMX UCC5, UCC7 clock route register */
+	u32 cmxucr3;		/* CMX UCC2, UCC4 clock route register */
+	u32 cmxucr4;		/* CMX UCC6, UCC8 clock route register */
+	u32 cmxupcr;		/* CMX UPC clock route register        */
+	u8 res0[0x1C];
+} __attribute__ ((packed)) qe_mux_t;
+
+/* QE Timers */
+typedef struct qe_timers {
+	u8 gtcfr1;		/* Timer 1 2 global configuration register */
+	u8 res0[0x3];
+	u8 gtcfr2;		/* Timer 3 4 global configuration register */
+	u8 res1[0xB];
+	u16 gtmdr1;		/* Timer 1 mode register */
+	u16 gtmdr2;		/* Timer 2 mode register */
+	u16 gtrfr1;		/* Timer 1 reference register */
+	u16 gtrfr2;		/* Timer 2 reference register */
+	u16 gtcpr1;		/* Timer 1 capture register */
+	u16 gtcpr2;		/* Timer 2 capture register */
+	u16 gtcnr1;		/* Timer 1 counter */
+	u16 gtcnr2;		/* Timer 2 counter */
+	u16 gtmdr3;		/* Timer 3 mode register */
+	u16 gtmdr4;		/* Timer 4 mode register */
+	u16 gtrfr3;		/* Timer 3 reference register */
+	u16 gtrfr4;		/* Timer 4 reference register */
+	u16 gtcpr3;		/* Timer 3 capture register */
+	u16 gtcpr4;		/* Timer 4 capture register */
+	u16 gtcnr3;		/* Timer 3 counter */
+	u16 gtcnr4;		/* Timer 4 counter */
+	u16 gtevr1;		/* Timer 1 event register */
+	u16 gtevr2;		/* Timer 2 event register */
+	u16 gtevr3;		/* Timer 3 event register */
+	u16 gtevr4;		/* Timer 4 event register */
+	u16 gtps;		/* Timer 1 prescale register */
+	u8 res2[0x46];
+} __attribute__ ((packed)) qe_timers_t;
+
+/* BRG */
+typedef struct qe_brg {
+	u32 brgc1;		/* BRG1 configuration register  */
+	u32 brgc2;		/* BRG2 configuration register  */
+	u32 brgc3;		/* BRG3 configuration register  */
+	u32 brgc4;		/* BRG4 configuration register  */
+	u32 brgc5;		/* BRG5 configuration register  */
+	u32 brgc6;		/* BRG6 configuration register  */
+	u32 brgc7;		/* BRG7 configuration register  */
+	u32 brgc8;		/* BRG8 configuration register  */
+	u32 brgc9;		/* BRG9 configuration register  */
+	u32 brgc10;		/* BRG10 configuration register */
+	u32 brgc11;		/* BRG11 configuration register */
+	u32 brgc12;		/* BRG12 configuration register */
+	u32 brgc13;		/* BRG13 configuration register */
+	u32 brgc14;		/* BRG14 configuration register */
+	u32 brgc15;		/* BRG15 configuration register */
+	u32 brgc16;		/* BRG16 configuration register */
+	u8 res0[0x40];
+} __attribute__ ((packed)) qe_brg_t;
+
+/* SPI */
+typedef struct spi {
+	u8 res0[0x20];
+	u32 spmode;		/* SPI mode register */
+	u8 res1[0x2];
+	u8 spie;		/* SPI event register */
+	u8 res2[0x1];
+	u8 res3[0x2];
+	u8 spim;		/* SPI mask register */
+	u8 res4[0x1];
+	u8 res5[0x1];
+	u8 spcom;		/* SPI command register  */
+	u8 res6[0x2];
+	u32 spitd;		/* SPI transmit data register (cpu mode) */
+	u32 spird;		/* SPI receive data register (cpu mode) */
+	u8 res7[0x8];
+} __attribute__ ((packed)) spi_t;
+
+/* SI */
+typedef struct si1 {
+	u16 siamr1;		/* SI1 TDMA mode register */
+	u16 sibmr1;		/* SI1 TDMB mode register */
+	u16 sicmr1;		/* SI1 TDMC mode register */
+	u16 sidmr1;		/* SI1 TDMD mode register */
+	u8 siglmr1_h;		/* SI1 global mode register high */
+	u8 res0[0x1];
+	u8 sicmdr1_h;		/* SI1 command register high */
+	u8 res2[0x1];
+	u8 sistr1_h;		/* SI1 status register high */
+	u8 res3[0x1];
+	u16 sirsr1_h;		/* SI1 RAM shadow address register high */
+	u8 sitarc1;		/* SI1 RAM counter Tx TDMA */
+	u8 sitbrc1;		/* SI1 RAM counter Tx TDMB */
+	u8 sitcrc1;		/* SI1 RAM counter Tx TDMC */
+	u8 sitdrc1;		/* SI1 RAM counter Tx TDMD */
+	u8 sirarc1;		/* SI1 RAM counter Rx TDMA */
+	u8 sirbrc1;		/* SI1 RAM counter Rx TDMB */
+	u8 sircrc1;		/* SI1 RAM counter Rx TDMC */
+	u8 sirdrc1;		/* SI1 RAM counter Rx TDMD */
+	u8 res4[0x8];
+	u16 siemr1;		/* SI1 TDME mode register 16 bits */
+	u16 sifmr1;		/* SI1 TDMF mode register 16 bits */
+	u16 sigmr1;		/* SI1 TDMG mode register 16 bits */
+	u16 sihmr1;		/* SI1 TDMH mode register 16 bits */
+	u8 siglmg1_l;		/* SI1 global mode register low 8 bits */
+	u8 res5[0x1];
+	u8 sicmdr1_l;		/* SI1 command register low 8 bits */
+	u8 res6[0x1];
+	u8 sistr1_l;		/* SI1 status register low 8 bits */
+	u8 res7[0x1];
+	u16 sirsr1_l;		/* SI1 RAM shadow address register low 16 bits */
+	u8 siterc1;		/* SI1 RAM counter Tx TDME 8 bits */
+	u8 sitfrc1;		/* SI1 RAM counter Tx TDMF 8 bits */
+	u8 sitgrc1;		/* SI1 RAM counter Tx TDMG 8 bits */
+	u8 sithrc1;		/* SI1 RAM counter Tx TDMH 8 bits */
+	u8 sirerc1;		/* SI1 RAM counter Rx TDME 8 bits */
+	u8 sirfrc1;		/* SI1 RAM counter Rx TDMF 8 bits */
+	u8 sirgrc1;		/* SI1 RAM counter Rx TDMG 8 bits */
+	u8 sirhrc1;		/* SI1 RAM counter Rx TDMH 8 bits */
+	u8 res8[0x8];
+	u32 siml1;		/* SI1 multiframe limit register */
+	u8 siedm1;		/* SI1 extended diagnostic mode register */
+	u8 res9[0xBB];
+} __attribute__ ((packed)) si1_t;
+
+/* SI Routing Tables */
+typedef struct sir {
+	u8 tx[0x400];
+	u8 rx[0x400];
+	u8 res0[0x800];
+} __attribute__ ((packed)) sir_t;
+
+/* USB Controller.  */
+typedef struct usb_ctlr {
+	u8 usb_usmod;
+	u8 usb_usadr;
+	u8 usb_uscom;
+	u8 res1[1];
+	u16 usb_usep1;
+	u16 usb_usep2;
+	u16 usb_usep3;
+	u16 usb_usep4;
+	u8 res2[4];
+	u16 usb_usber;
+	u8 res3[2];
+	u16 usb_usbmr;
+	u8 res4[1];
+	u8 usb_usbs;
+	u16 usb_ussft;
+	u8 res5[2];
+	u16 usb_usfrn;
+	u8 res6[0x22];
+} __attribute__ ((packed)) usb_t;
+
+/* MCC */
+typedef struct mcc {
+	u32 mcce;		/* MCC event register */
+	u32 mccm;		/* MCC mask register */
+	u32 mccf;		/* MCC configuration register */
+	u32 merl;		/* MCC emergency request level register */
+	u8 res0[0xF0];
+} __attribute__ ((packed)) mcc_t;
+
+/* QE UCC Slow */
+typedef struct ucc_slow {
+	u32 gumr_l;		/* UCCx general mode register (low) */
+	u32 gumr_h;		/* UCCx general mode register (high) */
+	u16 upsmr;		/* UCCx protocol-specific mode register */
+	u8 res0[0x2];
+	u16 utodr;		/* UCCx transmit on demand register */
+	u16 udsr;		/* UCCx data synchronization register */
+	u16 ucce;		/* UCCx event register */
+	u8 res1[0x2];
+	u16 uccm;		/* UCCx mask register */
+	u8 res2[0x1];
+	u8 uccs;		/* UCCx status register */
+	u8 res3[0x24];
+	u16 utpt;
+	u8 guemr;		/* UCC general extended mode register */
+	u8 res4[0x200 - 0x091];
+} __attribute__ ((packed)) ucc_slow_t;
+
+typedef struct ucc_mii_mng {
+	u32 miimcfg;		/* MII management configuration reg    */
+	u32 miimcom;		/* MII management command reg          */
+	u32 miimadd;		/* MII management address reg          */
+	u32 miimcon;		/* MII management control reg          */
+	u32 miimstat;		/* MII management status reg           */
+	u32 miimind;		/* MII management indication reg       */
+	u32 ifctl;		/* interface control reg               */
+	u32 ifstat;		/* interface statux reg                */
+} __attribute__ ((packed))uec_mii_t;
+
+typedef struct ucc_ethernet {
+	u32 maccfg1;		/* mac configuration reg. 1            */
+	u32 maccfg2;		/* mac configuration reg. 2            */
+	u32 ipgifg;		/* interframe gap reg.                 */
+	u32 hafdup;		/* half-duplex reg.                    */
+	u8 res1[0x10];
+	u32 miimcfg;		/* MII management configuration reg    */
+	u32 miimcom;		/* MII management command reg          */
+	u32 miimadd;		/* MII management address reg          */
+	u32 miimcon;		/* MII management control reg          */
+	u32 miimstat;		/* MII management status reg           */
+	u32 miimind;		/* MII management indication reg       */
+	u32 ifctl;		/* interface control reg               */
+	u32 ifstat;		/* interface statux reg                */
+	u32 macstnaddr1;	/* mac station address part 1 reg      */
+	u32 macstnaddr2;	/* mac station address part 2 reg      */
+	u8 res2[0x8];
+	u32 uempr;		/* UCC Ethernet Mac parameter reg      */
+	u32 utbipar;		/* UCC tbi address reg                 */
+	u16 uescr;		/* UCC Ethernet statistics control reg */
+	u8 res3[0x180 - 0x15A];
+	u32 tx64;		/* Total number of frames (including bad
+				 * frames) transmitted that were exactly
+				 * of the minimal length (64 for un tagged,
+				 * 68 for tagged, or with length exactly
+				 * equal to the parameter MINLength */
+	u32 tx127;		/* Total number of frames (including bad
+				 * frames) transmitted that were between
+				 * MINLength (Including FCS length==4)
+				 * and 127 octets */
+	u32 tx255;		/* Total number of frames (including bad
+				 * frames) transmitted that were between
+				 * 128 (Including FCS length==4) and 255
+				 * octets */
+	u32 rx64;		/* Total number of frames received including
+				 * bad frames that were exactly of the
+				 * mninimal length (64 bytes) */
+	u32 rx127;		/* Total number of frames (including bad
+				 * frames) received that were between
+				 * MINLength (Including FCS length==4)
+				 * and 127 octets */
+	u32 rx255;		/* Total number of frames (including
+				 * bad frames) received that were between
+				 * 128 (Including FCS length==4) and 255
+				 * octets */
+	u32 txok;		/* Total number of octets residing in frames
+				 * that where involved in succesfull
+				 * transmission */
+	u16 txcf;		/* Total number of PAUSE control frames
+				 *  transmitted by this MAC */
+	u8 res4[0x2];
+	u32 tmca;		/* Total number of frames that were transmitted
+				 * succesfully with the group address bit set
+				 * that are not broadcast frames */
+	u32 tbca;		/* Total number of frames transmitted
+				 * succesfully that had destination address
+				 * field equal to the broadcast address */
+	u32 rxfok;		/* Total number of frames received OK */
+	u32 rxbok;		/* Total number of octets received OK */
+	u32 rbyt;		/* Total number of octets received including
+				 * octets in bad frames. Must be implemented
+				 * in HW because it includes octets in frames
+				 * that never even reach the UCC */
+	u32 rmca;		/* Total number of frames that were received
+				 * succesfully with the group address bit set
+				 * that are not broadcast frames */
+	u32 rbca;		/* Total number of frames received succesfully
+				 * that had destination address equal to the
+				 * broadcast address */
+	u32 scar;		/* Statistics carry register */
+	u32 scam;		/* Statistics caryy mask register */
+	u8 res5[0x200 - 0x1c4];
+} __attribute__ ((packed)) uec_t;
+
+/* QE UCC Fast */
+typedef struct ucc_fast {
+	u32 gumr;		/* UCCx general mode register */
+	u32 upsmr;		/* UCCx protocol-specific mode register  */
+	u16 utodr;		/* UCCx transmit on demand register  */
+	u8 res0[0x2];
+	u16 udsr;		/* UCCx data synchronization register  */
+	u8 res1[0x2];
+	u32 ucce;		/* UCCx event register */
+	u32 uccm;		/* UCCx mask register.  */
+	u8 uccs;		/* UCCx status register */
+	u8 res2[0x7];
+	u32 urfb;		/* UCC receive FIFO base */
+	u16 urfs;		/* UCC receive FIFO size */
+	u8 res3[0x2];
+	u16 urfet;		/* UCC receive FIFO emergency threshold */
+	u16 urfset;		/* UCC receive FIFO special emergency
+				 * threshold */
+	u32 utfb;		/* UCC transmit FIFO base */
+	u16 utfs;		/* UCC transmit FIFO size */
+	u8 res4[0x2];
+	u16 utfet;		/* UCC transmit FIFO emergency threshold */
+	u8 res5[0x2];
+	u16 utftt;		/* UCC transmit FIFO transmit threshold */
+	u8 res6[0x2];
+	u16 utpt;		/* UCC transmit polling timer */
+	u8 res7[0x2];
+	u32 urtry;		/* UCC retry counter register */
+	u8 res8[0x4C];
+	u8 guemr;		/* UCC general extended mode register */
+	u8 res9[0x100 - 0x091];
+	uec_t ucc_eth;
+} __attribute__ ((packed)) ucc_fast_t;
+
+/* QE UCC */
+typedef struct ucc_common {
+	u8 res1[0x90];
+	u8 guemr;
+	u8 res2[0x200 - 0x091];
+} __attribute__ ((packed)) ucc_common_t;
+
+typedef struct ucc {
+	union {
+		ucc_slow_t slow;
+		ucc_fast_t fast;
+		ucc_common_t common;
+	};
+} __attribute__ ((packed)) ucc_t;
+
+/* MultiPHY UTOPIA POS Controllers (UPC) */
+typedef struct upc {
+	u32 upgcr;		/* UTOPIA/POS general configuration register */
+	u32 uplpa;		/* UTOPIA/POS last PHY address */
+	u32 uphec;		/* ATM HEC register */
+	u32 upuc;		/* UTOPIA/POS UCC configuration */
+	u32 updc1;		/* UTOPIA/POS device 1 configuration */
+	u32 updc2;		/* UTOPIA/POS device 2 configuration  */
+	u32 updc3;		/* UTOPIA/POS device 3 configuration */
+	u32 updc4;		/* UTOPIA/POS device 4 configuration  */
+	u32 upstpa;		/* UTOPIA/POS STPA threshold  */
+	u8 res0[0xC];
+	u32 updrs1_h;		/* UTOPIA/POS device 1 rate select  */
+	u32 updrs1_l;		/* UTOPIA/POS device 1 rate select  */
+	u32 updrs2_h;		/* UTOPIA/POS device 2 rate select  */
+	u32 updrs2_l;		/* UTOPIA/POS device 2 rate select */
+	u32 updrs3_h;		/* UTOPIA/POS device 3 rate select */
+	u32 updrs3_l;		/* UTOPIA/POS device 3 rate select */
+	u32 updrs4_h;		/* UTOPIA/POS device 4 rate select */
+	u32 updrs4_l;		/* UTOPIA/POS device 4 rate select */
+	u32 updrp1;		/* UTOPIA/POS device 1 receive priority low  */
+	u32 updrp2;		/* UTOPIA/POS device 2 receive priority low  */
+	u32 updrp3;		/* UTOPIA/POS device 3 receive priority low  */
+	u32 updrp4;		/* UTOPIA/POS device 4 receive priority low  */
+	u32 upde1;		/* UTOPIA/POS device 1 event */
+	u32 upde2;		/* UTOPIA/POS device 2 event */
+	u32 upde3;		/* UTOPIA/POS device 3 event */
+	u32 upde4;		/* UTOPIA/POS device 4 event */
+	u16 uprp1;
+	u16 uprp2;
+	u16 uprp3;
+	u16 uprp4;
+	u8 res1[0x8];
+	u16 uptirr1_0;		/* Device 1 transmit internal rate 0 */
+	u16 uptirr1_1;		/* Device 1 transmit internal rate 1 */
+	u16 uptirr1_2;		/* Device 1 transmit internal rate 2 */
+	u16 uptirr1_3;		/* Device 1 transmit internal rate 3 */
+	u16 uptirr2_0;		/* Device 2 transmit internal rate 0 */
+	u16 uptirr2_1;		/* Device 2 transmit internal rate 1 */
+	u16 uptirr2_2;		/* Device 2 transmit internal rate 2 */
+	u16 uptirr2_3;		/* Device 2 transmit internal rate 3 */
+	u16 uptirr3_0;		/* Device 3 transmit internal rate 0 */
+	u16 uptirr3_1;		/* Device 3 transmit internal rate 1 */
+	u16 uptirr3_2;		/* Device 3 transmit internal rate 2 */
+	u16 uptirr3_3;		/* Device 3 transmit internal rate 3 */
+	u16 uptirr4_0;		/* Device 4 transmit internal rate 0 */
+	u16 uptirr4_1;		/* Device 4 transmit internal rate 1 */
+	u16 uptirr4_2;		/* Device 4 transmit internal rate 2 */
+	u16 uptirr4_3;		/* Device 4 transmit internal rate 3 */
+	u32 uper1;		/* Device 1 port enable register */
+	u32 uper2;		/* Device 2 port enable register */
+	u32 uper3;		/* Device 3 port enable register */
+	u32 uper4;		/* Device 4 port enable register */
+	u8 res2[0x150];
+} __attribute__ ((packed)) upc_t;
+
+/* SDMA */
+typedef struct sdma {
+	u32 sdsr;		/* Serial DMA status register */
+	u32 sdmr;		/* Serial DMA mode register */
+	u32 sdtr1;		/* SDMA system bus threshold register */
+	u32 sdtr2;		/* SDMA secondary bus threshold register */
+	u32 sdhy1;		/* SDMA system bus hysteresis register */
+	u32 sdhy2;		/* SDMA secondary bus hysteresis register */
+	u32 sdta1;		/* SDMA system bus address register */
+	u32 sdta2;		/* SDMA secondary bus address register */
+	u32 sdtm1;		/* SDMA system bus MSNUM register */
+	u32 sdtm2;		/* SDMA secondary bus MSNUM register */
+	u8 res0[0x10];
+	u32 sdaqr;		/* SDMA address bus qualify register */
+	u32 sdaqmr;		/* SDMA address bus qualify mask register */
+	u8 res1[0x4];
+	u32 sdwbcr;		/* SDMA CAM entries base register */
+	u8 res2[0x38];
+} __attribute__ ((packed)) sdma_t;
+
+/* Debug Space */
+typedef struct dbg {
+	u32 bpdcr;		/* Breakpoint debug command register */
+	u32 bpdsr;		/* Breakpoint debug status register */
+	u32 bpdmr;		/* Breakpoint debug mask register */
+	u32 bprmrr0;		/* Breakpoint request mode risc register 0 */
+	u32 bprmrr1;		/* Breakpoint request mode risc register 1 */
+	u8 res0[0x8];
+	u32 bprmtr0;		/* Breakpoint request mode trb register 0 */
+	u32 bprmtr1;		/* Breakpoint request mode trb register 1 */
+	u8 res1[0x8];
+	u32 bprmir;		/* Breakpoint request mode immediate register */
+	u32 bprmsr;		/* Breakpoint request mode serial register */
+	u32 bpemr;		/* Breakpoint exit mode register */
+	u8 res2[0x48];
+} __attribute__ ((packed)) dbg_t;
+
+/*
+ * RISC Special Registers (Trap and Breakpoint).  These are described in
+ * the QE Developer's Handbook.
+*/
+typedef struct rsp {
+	u32 tibcr[16];	/* Trap/instruction breakpoint control regs */
+	u8 res0[64];
+	u32 ibcr0;
+	u32 ibs0;
+	u32 ibcnr0;
+	u8 res1[4];
+	u32 ibcr1;
+	u32 ibs1;
+	u32 ibcnr1;
+	u32 npcr;
+	u32 dbcr;
+	u32 dbar;
+	u32 dbamr;
+	u32 dbsr;
+	u32 dbcnr;
+	u8 res2[12];
+	u32 dbdr_h;
+	u32 dbdr_l;
+	u32 dbdmr_h;
+	u32 dbdmr_l;
+	u32 bsr;
+	u32 bor;
+	u32 bior;
+	u8 res3[4];
+	u32 iatr[4];
+	u32 eccr;		/* Exception control configuration register */
+	u32 eicr;
+	u8 res4[0x100-0xf8];
+} __attribute__ ((packed)) rsp_t;
+
+typedef struct qe_immap {
+	qe_iram_t iram;		/* I-RAM */
+	qe_ic_t ic;		/* Interrupt Controller */
+	cp_qe_t cp;		/* Communications Processor */
+	qe_mux_t qmx;		/* QE Multiplexer */
+	qe_timers_t qet;	/* QE Timers */
+	spi_t spi[0x2];		/* spi  */
+	mcc_t mcc;		/* mcc */
+	qe_brg_t brg;		/* brg */
+	usb_t usb;		/* USB */
+	si1_t si1;		/* SI */
+	u8 res11[0x800];
+	sir_t sir;		/* SI Routing Tables  */
+	ucc_t ucc1;		/* ucc1 */
+	ucc_t ucc3;		/* ucc3 */
+	ucc_t ucc5;		/* ucc5 */
+	ucc_t ucc7;		/* ucc7 */
+	u8 res12[0x600];
+	upc_t upc1;		/* MultiPHY UTOPIA POS Controller 1 */
+	ucc_t ucc2;		/* ucc2 */
+	ucc_t ucc4;		/* ucc4 */
+	ucc_t ucc6;		/* ucc6 */
+	ucc_t ucc8;		/* ucc8 */
+	u8 res13[0x600];
+	upc_t upc2;		/* MultiPHY UTOPIA POS Controller 2 */
+	sdma_t sdma;		/* SDMA */
+	dbg_t dbg;		/* Debug Space */
+	rsp_t rsp[0x2];		/* RISC Special Registers
+				 * (Trap and Breakpoint) */
+	u8 res14[0x300];
+	u8 res15[0x3A00];
+	u8 res16[0x8000];	/* 0x108000 -  0x110000 */
+	u8 muram[QE_MURAM_SIZE];
+} __attribute__ ((packed)) qe_map_t;
+
+extern qe_map_t *qe_immr;
+
+#endif				/* __IMMAP_QE_H__ */
diff --git a/include/post.h b/include/post.h
index 24ca728b404..5ebd5358232 100644
--- a/include/post.h
+++ b/include/post.h
@@ -38,7 +38,7 @@
 #define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
 
 #elif defined(CONFIG_MPC8360)
-#include <asm/immap_qe.h>
+#include <linux/immap_qe.h>
 #define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
 
 #elif defined (CONFIG_MPC85xx)
-- 
cgit v1.3.1


From 3bab3d8324874604501ff9154e68732fb986057a Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar@freescale.com>
Date: Thu, 12 Jun 2014 09:13:08 +0530
Subject: driver/nand:Define MAX_BANKS same as SoC defined for IFC

The number of chip select used by IFC controller vary from one SoC to other.
For eg. P1010 has 4, T4240 has 8.

Update MAX_BANKS same as SoC defined

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---
 drivers/mtd/nand/fsl_ifc_nand.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index be5a16a1ba9..27f5177d71e 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -19,8 +19,12 @@
 #include <asm/errno.h>
 #include <fsl_ifc.h>
 
+#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
+#endif
+
 #define FSL_IFC_V1_1_0	0x01010000
-#define MAX_BANKS	4
+#define MAX_BANKS	CONFIG_SYS_FSL_IFC_BANK_COUNT
 #define ERR_BYTE	0xFF /* Value returned for read bytes
 				when read failed */
 #define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
-- 
cgit v1.3.1


From 04818bbdc34cb02b2590af8e5f77118ed8a8d755 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar@freescale.com>
Date: Thu, 12 Jun 2014 12:14:00 +0530
Subject: driver/nand: Update SRAM initialize logic for IFC.

IFC controller v1.1.0 requires internal SRAM initialize by reading
NAND flash. Higher controller versions have provided "SRAM init" bit in
NCFGR register space.

update SRAM initialize logic to reflect the same.

Also print error message in case of Page read error.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---
 drivers/mtd/nand/fsl_ifc_nand.c | 35 +++++++++++++++++++++++++++++++----
 include/fsl_ifc.h               |  2 ++
 2 files changed, 33 insertions(+), 4 deletions(-)

(limited to 'drivers')

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 27f5177d71e..280e14e24a0 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -806,12 +806,30 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 {
 }
 
-static void fsl_ifc_sram_init(void)
+static int fsl_ifc_sram_init(uint32_t ver)
 {
 	struct fsl_ifc *ifc = ifc_ctrl->regs;
 	uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
+	uint32_t ncfgr = 0;
 	long long end_tick;
 
+	if (ver > FSL_IFC_V1_1_0) {
+		ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
+		ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
+
+		/* wait for  SRAM_INIT bit to be clear or timeout */
+		end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
+		while (end_tick > get_ticks()) {
+			ifc_ctrl->status =
+				ifc_in32(&ifc->ifc_nand.nand_evter_stat);
+
+			if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
+				return 0;
+		}
+		printf("fsl-ifc: Failed to Initialise SRAM\n");
+		return 1;
+	}
+
 	cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
 
 	/* Save CSOR and CSOR_ext */
@@ -854,11 +872,18 @@ static void fsl_ifc_sram_init(void)
 			break;
 	}
 
+	if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
+		printf("fsl-ifc: Failed to Initialise SRAM\n");
+		return 1;
+	}
+
 	ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
 
 	/* Restore CSOR and CSOR_ext */
 	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
 	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
+
+	return 0;
 }
 
 static int fsl_ifc_chip_init(int devnum, u8 *addr)
@@ -868,7 +893,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	struct fsl_ifc_mtd *priv;
 	struct nand_ecclayout *layout;
 	uint32_t cspr = 0, csor = 0, ver = 0;
-	int ret;
+	int ret = 0;
 
 	if (!ifc_ctrl) {
 		fsl_ifc_ctrl_init();
@@ -1010,8 +1035,10 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	}
 
 	ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
-	if (ver == FSL_IFC_V1_1_0)
-		fsl_ifc_sram_init();
+	if (ver >= FSL_IFC_V1_1_0)
+		ret = fsl_ifc_sram_init(ver);
+	if (ret)
+		return ret;
 
 	ret = nand_scan_ident(mtd, 1, NULL);
 	if (ret)
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
index 630e4b4999b..b353b04c469 100644
--- a/include/fsl_ifc.h
+++ b/include/fsl_ifc.h
@@ -367,6 +367,8 @@
  */
 /* Auto Boot Mode */
 #define IFC_NAND_NCFGR_BOOT		0x80000000
+/* SRAM INIT EN */
+#define IFC_NAND_SRAM_INIT_EN		0x20000000
 /* Addressing Mode-ROW0+n/COL0 */
 #define IFC_NAND_NCFGR_ADDR_MODE_RC0	0x00000000
 /* Addressing Mode-ROW0+n/COL0+n */
-- 
cgit v1.3.1


From 32514d259bf37cc92872aeb0624b75f600e7fb3a Mon Sep 17 00:00:00 2001
From: Zang Roy-R61911 <tie-fei.zang@freescale.com>
Date: Thu, 12 Jun 2014 14:49:23 -0500
Subject: fsl/pcie: Change 'no link' to 'undetermined' for pcie endpoint

Even u-boot boots up, the pcie link may not setup correctly when
Freescale SOC acts as endpoint.
So change the link status from 'no link' to 'undetermined' to
reduce the confusion.
The link status can check from host side eventually.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---
 drivers/pci/fsl_pci_init.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

(limited to 'drivers')

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 3a41b0ec173..231b07573f5 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -504,8 +504,14 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 		}
 #endif
 		if (!enabled) {
-			/* Let the user know there's no PCIe link */
-			printf("no link, regs @ 0x%lx\n", pci_info->regs);
+			/* Let the user know there's no PCIe link for root
+			 * complex. for endpoint, the link may not setup, so
+			 * print undetermined.
+			 */
+			if (fsl_is_pci_agent(hose))
+				printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
+			else
+				printf("no link, regs @ 0x%lx\n", pci_info->regs);
 			hose->last_busno = hose->first_busno;
 			return;
 		}
-- 
cgit v1.3.1


From 591dd192307d81cf8f8705b06854e973c53d4c4d Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar@freescale.com>
Date: Sat, 14 Jun 2014 08:48:19 +0530
Subject: driver/nand: Add support of 16K SRAM for IFC 2.0

Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0.

Update the page offset calculation logic to support the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---
 drivers/mtd/nand/fsl_ifc_nand.c | 4 +++-
 drivers/mtd/nand/fsl_ifc_spl.c  | 6 +++++-
 include/fsl_ifc.h               | 2 ++
 3 files changed, 10 insertions(+), 2 deletions(-)

(limited to 'drivers')

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 280e14e24a0..8b453cb383c 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -23,7 +23,6 @@
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #endif
 
-#define FSL_IFC_V1_1_0	0x01010000
 #define MAX_BANKS	CONFIG_SYS_FSL_IFC_BANK_COUNT
 #define ERR_BYTE	0xFF /* Value returned for read bytes
 				when read failed */
@@ -1040,6 +1039,9 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	if (ret)
 		return ret;
 
+	if (ver >= FSL_IFC_V2_0_0)
+		priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
+
 	ret = nand_scan_ident(mtd, 1, NULL);
 	if (ret)
 		return ret;
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 510077282cd..e336cb1c94b 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -97,7 +97,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
 	int pages_per_blk;
 	int blk_size;
 	int bad_marker = 0;
-	int bufnum_mask, bufnum;
+	int bufnum_mask, bufnum, ver = 0;
 
 	int csor, cspr;
 	int pos = 0;
@@ -130,6 +130,10 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
 			bad_marker = 5;
 	}
 
+	ver = ifc_in32(&ifc->ifc_rev);
+	if (ver >= FSL_IFC_V2_0_0)
+		bufnum_mask = (bufnum_mask * 2) + 1;
+
 	pages_per_blk =
 		32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
 
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
index b353b04c469..11474b757c3 100644
--- a/include/fsl_ifc.h
+++ b/include/fsl_ifc.h
@@ -12,6 +12,8 @@
 #include <config.h>
 #include <common.h>
 
+#define FSL_IFC_V1_1_0	0x01010000
+#define FSL_IFC_V2_0_0	0x02000000
 
 #ifdef CONFIG_SYS_FSL_IFC_LE
 #define ifc_in32(a)       in_le32(a)
-- 
cgit v1.3.1


From 8340e7ac86ad3c59956e8f0bd627b741e5209439 Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Mon, 23 Jun 2014 15:36:44 -0700
Subject: driver/ddr: Fix DDR4 driver for ARM

Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/arm/include/asm/arch-fsl-lsch3/config.h | 4 ++++
 arch/arm/include/asm/io.h                    | 1 +
 arch/powerpc/include/asm/io.h                | 3 +++
 drivers/ddr/fsl/fsl_ddr_gen4.c               | 7 +++++--
 4 files changed, 13 insertions(+), 2 deletions(-)

(limited to 'drivers')

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index c1c718ecd4b..b17410a58a7 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -43,7 +43,11 @@
 /* DDR */
 #define CONFIG_SYS_FSL_DDR_LE
 #define CONFIG_VERY_BIG_RAM
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#else
 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3	/* Enable Freescale ARM DDR3 driver */
+#endif
 #define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 214f3ea51f4..6d18eb330a9 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -136,6 +136,7 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
  * TODO: The kernel offers some more advanced versions of barriers, it might
  * have some advantages to use them instead of the simple one here.
  */
+#define mb()		asm volatile("dsb sy" : : : "memory")
 #define dmb()		__asm__ __volatile__ ("" : : : "memory")
 #define __iormb()	dmb()
 #define __iowmb()	dmb()
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index d8b7b974d41..a5257e9b624 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -123,6 +123,9 @@ static inline void isync(void)
 #define iobarrier_r()  eieio()
 #define iobarrier_w()  eieio()
 
+#define mb()	sync()
+#define isb()	isync()
+
 /*
  * Non ordered and non-swapping "raw" accessors
  */
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 7cd878aeecb..bfc76b34857 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -8,6 +8,7 @@
 #include <asm/io.h>
 #include <fsl_ddr_sdram.h>
 #include <asm/processor.h>
+#include <fsl_immap.h>
 #include <fsl_ddr.h>
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
@@ -183,12 +184,14 @@ step2:
 	 * we choose the max, that is 500 us for all of case.
 	 */
 	udelay(500);
-	asm volatile("sync;isync");
+	mb();
+	isb();
 
 	/* Let the controller go */
 	temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 	ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
-	asm volatile("sync;isync");
+	mb();
+	isb();
 
 	total_gb_size_per_controller = 0;
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-- 
cgit v1.3.1


From 3d75ec95f57224995210db5c5dea8d458cf862fb Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Thu, 26 Jun 2014 11:14:44 -0700
Subject: driver/ddr: Fix DDR register timing_cfg_8

The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 drivers/ddr/fsl/ctrl_regs.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'drivers')

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index dcf6287f663..04e4178b15d 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1857,6 +1857,9 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
 
 	acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
 	wrtord_bg = max(4, picos_to_mclk(7500));
+	if (popts->otf_burst_chop_en)
+		wrtord_bg += 2;
+
 	pre_all_rec = 0;
 
 	ddr->timing_cfg_8 = (0
-- 
cgit v1.3.1


From a6e50a88d8d3724fc75f1c6959b80a6c7c69cbad Mon Sep 17 00:00:00 2001
From: Ian Campbell <ijc@hellion.org.uk>
Date: Fri, 18 Jul 2014 20:38:41 +0100
Subject: ahci: provide sunxi SATA driver using AHCI platform framework

This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done
for sun7i only since I don't have access to any other sunxi platforms
with sata included.

The PHY setup is derived from the Alwinner releases and Linux, but is mostly
undocumented.

The Allwinner AHCI controller also requires some magic (and, again,
undocumented) DMA initialisation when starting a port.  This is added under a
suitable ifdef.

This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on
contents of Linux DTS files, including SATA power pin config taken from the
DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/cpu/armv7/sunxi/clock_sun4i.c        |  4 ++
 arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 11 ++--
 board/sunxi/Makefile                          |  1 +
 board/sunxi/ahci.c                            | 84 +++++++++++++++++++++++++++
 configs/Cubieboard2_FEL_defconfig             |  2 +-
 configs/Cubieboard2_defconfig                 |  2 +-
 configs/Cubieboard_defconfig                  |  2 +-
 configs/Cubietruck_FEL_defconfig              |  2 +-
 configs/Cubietruck_defconfig                  |  2 +-
 drivers/block/ahci.c                          | 16 +++++
 include/ahci.h                                |  4 ++
 include/configs/sunxi-common.h                | 12 ++++
 12 files changed, 133 insertions(+), 9 deletions(-)
 create mode 100644 board/sunxi/ahci.c

(limited to 'drivers')

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index b8b16cff951..ecbdb0162b2 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -39,6 +39,10 @@ void clock_init_safe(void)
 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
 #endif
 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+#ifdef CONFIG_SUNXI_AHCI
+	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
+	setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
+#endif
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 928f3f26709..2531cbdcd59 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -218,10 +218,13 @@ struct sunxi_ccm_reg {
 #define CCM_PLL5_CTRL_BYPASS (0x1 << 30)
 #define CCM_PLL5_CTRL_EN (0x1 << 31)
 
-#define CCM_PLL6_CTRL_N_SHIFT	8
-#define CCM_PLL6_CTRL_N_MASK	(0x1f << CCM_PLL6_CTRL_N_SHIFT)
-#define CCM_PLL6_CTRL_K_SHIFT	4
-#define CCM_PLL6_CTRL_K_MASK	(0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL6_CTRL_EN		31
+#define CCM_PLL6_CTRL_BYPASS_EN		30
+#define CCM_PLL6_CTRL_SATA_EN_SHIFT	14
+#define CCM_PLL6_CTRL_N_SHIFT		8
+#define CCM_PLL6_CTRL_N_MASK		(0x1f << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT		4
+#define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
 
 #define CCM_GPS_CTRL_RESET (0x1 << 0)
 #define CCM_GPS_CTRL_GATE (0x1 << 1)
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 62acb8ff27a..03f55cc49d1 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -10,6 +10,7 @@
 #
 obj-y	+= board.o
 obj-$(CONFIG_SUNXI_GMAC)	+= gmac.o
+obj-$(CONFIG_SUNXI_AHCI)	+= ahci.o
 obj-$(CONFIG_A13_OLINUXINOM)	+= dram_a13_oli_micro.o
 obj-$(CONFIG_CUBIEBOARD)	+= dram_cubieboard.o
 obj-$(CONFIG_CUBIEBOARD2)	+= dram_cubieboard2.o
diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c
new file mode 100644
index 00000000000..0c262eabb75
--- /dev/null
+++ b/board/sunxi/ahci.c
@@ -0,0 +1,84 @@
+#include <common.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define AHCI_PHYCS0R 0x00c0
+#define AHCI_PHYCS1R 0x00c4
+#define AHCI_PHYCS2R 0x00c8
+#define AHCI_RWCR    0x00fc
+
+/* This magic PHY initialisation was taken from the Allwinner releases
+ * and Linux driver, but is completely undocumented.
+ */
+static int sunxi_ahci_phy_init(u32 base)
+{
+	u8 *reg_base = (u8 *)base;
+	u32 reg_val;
+	int timeout;
+
+	writel(0, reg_base + AHCI_RWCR);
+	mdelay(5);
+
+	setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
+	clrsetbits_le32(reg_base + AHCI_PHYCS0R,
+			(0x7 << 24),
+			(0x5 << 24) | (0x1 << 23) | (0x1 << 18));
+	clrsetbits_le32(reg_base + AHCI_PHYCS1R,
+			(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
+			(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
+	setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
+	clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
+	clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
+	clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
+	mdelay(5);
+
+	setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
+
+	timeout = 250; /* Power up takes approx 50 us */
+	for (;;) {
+		reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);
+		if (reg_val == (0x2 << 28))
+			break;
+		if (--timeout == 0) {
+			printf("AHCI PHY power up failed.\n");
+			return -EIO;
+		}
+		udelay(1);
+	};
+
+	setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
+
+	timeout = 100; /* Calibration takes approx 10 us */
+	for (;;) {
+		reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);
+		if (reg_val == 0x0)
+			break;
+		if (--timeout == 0) {
+			printf("AHCI PHY calibration failed.\n");
+			return -EIO;
+		}
+		udelay(1);
+	}
+
+	mdelay(15);
+
+	writel(0x7, reg_base + AHCI_RWCR);
+
+	return 0;
+}
+
+void scsi_init(void)
+{
+	printf("SUNXI SCSI INIT\n");
+#ifdef CONFIG_SATAPWR
+	gpio_direction_output(CONFIG_SATAPWR, 1);
+#endif
+
+	if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
+		return;
+
+	ahci_init(SUNXI_SATA_BASE);
+}
diff --git a/configs/Cubieboard2_FEL_defconfig b/configs/Cubieboard2_FEL_defconfig
index 08f31591c2a..4eddd089691 100644
--- a/configs/Cubieboard2_FEL_defconfig
+++ b/configs/Cubieboard2_FEL_defconfig
@@ -1,4 +1,4 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,SPL_FEL,SUNXI_GMAC"
+CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,SPL_FEL,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SUN7I=y
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 122dac94fb4..ce06fe9ab13 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -1,4 +1,4 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,SPL,SUNXI_GMAC"
+CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,SPL,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SUN7I=y
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index 29bf8361e1b..7646ea4a37a 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -1,4 +1,4 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC"
+CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SUN4I=y
diff --git a/configs/Cubietruck_FEL_defconfig b/configs/Cubietruck_FEL_defconfig
index b95c5fab28b..73867f725fa 100644
--- a/configs/Cubietruck_FEL_defconfig
+++ b/configs/Cubietruck_FEL_defconfig
@@ -1,4 +1,4 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII"
+CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SUN7I=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 4c1e9a3987b..eb460ac9b1b 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -1,4 +1,4 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII"
+CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SUN7I=y
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 4df804671a8..dce99adc6b5 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -129,6 +129,14 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
 	return 1;
 }
 
+#ifdef CONFIG_SUNXI_AHCI
+/* The sunxi AHCI controller requires this undocumented setup */
+static void sunxi_dma_init(volatile u8 *port_mmio)
+{
+	clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
+}
+#endif
+
 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
 {
 #ifndef CONFIG_SCSI_AHCI_PLAT
@@ -213,6 +221,10 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
 			msleep(500);
 		}
 
+#ifdef CONFIG_SUNXI_AHCI
+		sunxi_dma_init(port_mmio);
+#endif
+
 		/* Add the spinup command to whatever mode bits may
 		 * already be on in the command register.
 		 */
@@ -545,6 +557,10 @@ static int ahci_port_start(u8 port)
 
 	writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
 
+#ifdef CONFIG_SUNXI_AHCI
+	sunxi_dma_init(port_mmio);
+#endif
+
 	writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
 			  PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
 			  PORT_CMD_START, port_mmio + PORT_CMD);
diff --git a/include/ahci.h b/include/ahci.h
index 90e850929b7..35b8a8c09b1 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -58,6 +58,10 @@
 #define PORT_SCR_ERR		0x30 /* SATA phy register: SError */
 #define PORT_SCR_ACT		0x34 /* SATA phy register: SActive */
 
+#ifdef CONFIG_SUNXI_AHCI
+#define PORT_P0DMACR		0x70 /* SUNXI specific "DMA register" */
+#endif
+
 /* PORT_IRQ_{STAT,MASK} bits */
 #define PORT_IRQ_COLD_PRES	(1 << 31) /* cold presence detect */
 #define PORT_IRQ_TF_ERR		(1 << 30) /* task file error */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 8ab6429e482..1505510cda8 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -57,6 +57,18 @@
 #define PHYS_SDRAM_0			CONFIG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_0_SIZE		0x80000000 /* 2 GiB */
 
+#ifdef CONFIG_AHCI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SUNXI_AHCI
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					 CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_CMD_SCSI
+#endif
+
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_SETEXPR
 
-- 
cgit v1.3.1


From 8d154002f30979c4ef911a3f93e41859bd3beabf Mon Sep 17 00:00:00 2001
From: Roman Byshko <rbyshko@gmail.com>
Date: Sun, 27 Jul 2014 19:32:44 +0200
Subject: sunxi: add USB EHCI driver

The Allwinner aka sunxi SoCs have one or more USB host controllers.
This adds a driver for their EHCI.

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/usb/host/Makefile     |   1 +
 drivers/usb/host/ehci-sunxi.c | 201 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 202 insertions(+)
 create mode 100644 drivers/usb/host/ehci-sunxi.c

(limited to 'drivers')

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 04c1a642a3f..c4f5157a843 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
 obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
 obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
+obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
 obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
new file mode 100644
index 00000000000..23617b7adc1
--- /dev/null
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2014 Roman Byshko
+ *
+ * Roman Byshko <rbyshko@gmail.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <common.h>
+#include "ehci.h"
+
+#define SUNXI_USB1_IO_BASE		0x01c14000
+#define SUNXI_USB2_IO_BASE		0x01c1c000
+
+#define SUNXI_USB_PMU_IRQ_ENABLE	0x800
+#define SUNXI_USB_CSR			0x01c13404
+#define SUNXI_USB_PASSBY_EN		1
+
+#define SUNXI_EHCI_AHB_ICHR8_EN		(1 << 10)
+#define SUNXI_EHCI_AHB_INCR4_BURST_EN	(1 << 9)
+#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN	(1 << 8)
+#define SUNXI_EHCI_ULPI_BYPASS_EN	(1 << 0)
+
+static struct sunxi_ehci_hcd {
+	struct usb_hcd *hcd;
+	int usb_rst_mask;
+	int ahb_clk_mask;
+	int gpio_vbus;
+	void *csr;
+	int irq;
+	int id;
+} sunxi_echi_hcd[] = {
+	{
+		.usb_rst_mask = CCM_USB_CTRL_PHY1_RST,
+		.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0,
+		.gpio_vbus = CONFIG_SUNXI_USB_VBUS0_GPIO,
+		.csr = (void *)SUNXI_USB_CSR,
+		.irq = 39,
+		.id = 1,
+	},
+#if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1)
+	{
+		.usb_rst_mask = CCM_USB_CTRL_PHY2_RST,
+		.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1,
+		.gpio_vbus = CONFIG_SUNXI_USB_VBUS1_GPIO,
+		.csr = (void *)SUNXI_USB_CSR,
+		.irq = 40,
+		.id = 2,
+	}
+#endif
+};
+
+static int enabled_hcd_count;
+
+static void *get_io_base(int hcd_id)
+{
+	if (hcd_id == 1)
+		return (void *)SUNXI_USB1_IO_BASE;
+	else if (hcd_id == 2)
+		return (void *)SUNXI_USB2_IO_BASE;
+	else
+		return NULL;
+}
+
+static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr,
+			  int data, int len)
+{
+	int j = 0, usbc_bit = 0;
+	void *dest = sunxi_ehci->csr;
+
+	usbc_bit = 1 << (sunxi_ehci->id * 2);
+	for (j = 0; j < len; j++) {
+		/* set the bit address to be written */
+		clrbits_le32(dest, 0xff << 8);
+		setbits_le32(dest, (addr + j) << 8);
+
+		clrbits_le32(dest, usbc_bit);
+		/* set data bit */
+		if (data & 0x1)
+			setbits_le32(dest, 1 << 7);
+		else
+			clrbits_le32(dest, 1 << 7);
+
+		setbits_le32(dest, usbc_bit);
+
+		clrbits_le32(dest, usbc_bit);
+
+		data >>= 1;
+	}
+}
+
+static void sunxi_usb_phy_init(struct sunxi_ehci_hcd *sunxi_ehci)
+{
+	/* The following comments are machine
+	 * translated from Chinese, you have been warned!
+	 */
+
+	/* adjust PHY's magnitude and rate */
+	usb_phy_write(sunxi_ehci, 0x20, 0x14, 5);
+
+	/* threshold adjustment disconnect */
+#ifdef CONFIG_SUN4I
+	usb_phy_write(sunxi_ehci, 0x2a, 3, 2);
+#else
+	usb_phy_write(sunxi_ehci, 0x2a, 2, 2);
+#endif
+
+	return;
+}
+
+static void sunxi_usb_passby(struct sunxi_ehci_hcd *sunxi_ehci, int enable)
+{
+	unsigned long bits = 0;
+	void *addr = get_io_base(sunxi_ehci->id) + SUNXI_USB_PMU_IRQ_ENABLE;
+
+	bits = SUNXI_EHCI_AHB_ICHR8_EN |
+		SUNXI_EHCI_AHB_INCR4_BURST_EN |
+		SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
+		SUNXI_EHCI_ULPI_BYPASS_EN;
+
+	if (enable)
+		setbits_le32(addr, bits);
+	else
+		clrbits_le32(addr, bits);
+
+	return;
+}
+
+static void sunxi_ehci_enable(struct sunxi_ehci_hcd *sunxi_ehci)
+{
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	setbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask);
+	setbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask);
+
+	sunxi_usb_phy_init(sunxi_ehci);
+
+	sunxi_usb_passby(sunxi_ehci, SUNXI_USB_PASSBY_EN);
+
+	gpio_direction_output(sunxi_ehci->gpio_vbus, 1);
+}
+
+static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci)
+{
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	gpio_direction_output(sunxi_ehci->gpio_vbus, 0);
+
+	sunxi_usb_passby(sunxi_ehci, !SUNXI_USB_PASSBY_EN);
+
+	clrbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask);
+	clrbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask);
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
+		struct ehci_hcor **hcor)
+{
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
+
+	/* enable common PHY only once */
+	if (index == 0)
+		setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
+
+	sunxi_ehci_enable(sunxi_ehci);
+
+	*hccr = get_io_base(sunxi_ehci->id);
+
+	*hcor = (struct ehci_hcor *)((uint32_t) *hccr
+				+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+
+	debug("sunxi-ehci: init hccr %x and hcor %x hc_length %d\n",
+	      (uint32_t)*hccr, (uint32_t)*hcor,
+	      (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+
+	enabled_hcd_count++;
+
+	return 0;
+}
+
+int ehci_hcd_stop(int index)
+{
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
+
+	sunxi_ehci_disable(sunxi_ehci);
+
+	/* disable common PHY only once, for the last enabled hcd */
+	if (enabled_hcd_count == 1)
+		clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
+
+	enabled_hcd_count--;
+
+	return 0;
+}
-- 
cgit v1.3.1


From 3fe3b4fb1c5adb00502276312696e38e9a7e9b5b Mon Sep 17 00:00:00 2001
From: DrEagle <dreagle@doukki.net>
Date: Fri, 25 Jul 2014 21:07:30 +0200
Subject: ARM: kirkwood: add mvsdio driver

This patch add Marvell kirkwood MVSDIO/MMC driver
and enable it for Sheevaplugs and OpenRD boards.

Signed-off-by: Gerald Kerma <drEagle@doukki.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
---
 arch/arm/cpu/arm926ejs/kirkwood/cpu.c         |   9 +
 arch/arm/include/asm/arch-kirkwood/kirkwood.h |   1 +
 drivers/mmc/Makefile                          |   1 +
 drivers/mmc/mvebu_mmc.c                       | 361 ++++++++++++++++++++++++++
 include/configs/openrd.h                      |   8 +
 include/configs/sheevaplug.h                  |  11 +
 include/mvebu_mmc.h                           | 278 ++++++++++++++++++++
 7 files changed, 669 insertions(+)
 create mode 100644 drivers/mmc/mvebu_mmc.c
 create mode 100644 include/mvebu_mmc.h

(limited to 'drivers')

diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index da802400526..881e2de81b3 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -13,6 +13,7 @@
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
+#include <mvebu_mmc.h>
 
 #define BUFLEN	16
 
@@ -377,3 +378,11 @@ int cpu_eth_init(bd_t *bis)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_MVEBU_MMC
+int board_mmc_init(bd_t *bis)
+{
+	mvebu_mmc_init(bis);
+	return 0;
+}
+#endif /* CONFIG_MVEBU_MMC */
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
index bc207f536ca..3ea51d7848c 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -39,6 +39,7 @@
 #define KW_EGIGA0_BASE			(KW_REGISTER(0x72000))
 #define KW_EGIGA1_BASE			(KW_REGISTER(0x76000))
 #define KW_SATA_BASE			(KW_REGISTER(0x80000))
+#define KW_SDIO_BASE			(KW_REGISTER(0x90000))
 
 /* Kirkwood Sata controller has two ports */
 #define KW_SATA_PORT0_OFFSET		0x2000
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 34febf52f0e..f5be96f5e51 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
 else
 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
+obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c
new file mode 100644
index 00000000000..97591983d23
--- /dev/null
+++ b/drivers/mmc/mvebu_mmc.c
@@ -0,0 +1,361 @@
+/*
+ * Marvell MMC/SD/SDIO driver
+ *
+ * (C) Copyright 2012
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Maen Suleiman, Gerald Kerma
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <part.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <mvebu_mmc.h>
+
+#define DRIVER_NAME "MVEBU_MMC"
+
+static void mvebu_mmc_write(u32 offs, u32 val)
+{
+	writel(val, CONFIG_SYS_MMC_BASE + (offs));
+}
+
+static u32 mvebu_mmc_read(u32 offs)
+{
+	return readl(CONFIG_SYS_MMC_BASE + (offs));
+}
+
+static int mvebu_mmc_setup_data(struct mmc_data *data)
+{
+	u32 ctrl_reg;
+
+	debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
+	      (data->flags & MMC_DATA_READ) ? "read" : "write",
+	      data->blocks, data->blocksize);
+
+	/* default to maximum timeout */
+	ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
+	ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
+	mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
+
+	if (data->flags & MMC_DATA_READ) {
+		mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
+		mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
+	} else {
+		mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
+		mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
+	}
+
+	mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);
+	mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);
+
+	return 0;
+}
+
+static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+			      struct mmc_data *data)
+{
+	int timeout = 10;
+	ushort waittype = 0;
+	ushort resptype = 0;
+	ushort xfertype = 0;
+	ushort resp_indx = 0;
+
+	debug("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
+	      cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
+
+	udelay(10*1000);
+
+	debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
+	      cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
+
+	/* Checking if card is busy */
+	while ((mvebu_mmc_read(SDIO_HW_STATE) & CARD_BUSY)) {
+		if (timeout == 0) {
+			printf("%s: card busy!\n", DRIVER_NAME);
+			return -1;
+		}
+		timeout--;
+		udelay(1000);
+	}
+
+	/* Set up for a data transfer if we have one */
+	if (data) {
+		int err = mvebu_mmc_setup_data(data);
+
+		if (err)
+			return err;
+	}
+
+	resptype = SDIO_CMD_INDEX(cmd->cmdidx);
+
+	/* Analyzing resptype/xfertype/waittype for the command */
+	if (cmd->resp_type & MMC_RSP_BUSY)
+		resptype |= SDIO_CMD_RSP_48BUSY;
+	else if (cmd->resp_type & MMC_RSP_136)
+		resptype |= SDIO_CMD_RSP_136;
+	else if (cmd->resp_type & MMC_RSP_PRESENT)
+		resptype |= SDIO_CMD_RSP_48;
+	else
+		resptype |= SDIO_CMD_RSP_NONE;
+
+	if (cmd->resp_type & MMC_RSP_CRC)
+		resptype |= SDIO_CMD_CHECK_CMDCRC;
+
+	if (cmd->resp_type & MMC_RSP_OPCODE)
+		resptype |= SDIO_CMD_INDX_CHECK;
+
+	if (cmd->resp_type & MMC_RSP_PRESENT) {
+		resptype |= SDIO_UNEXPECTED_RESP;
+		waittype |= SDIO_NOR_UNEXP_RSP;
+	}
+
+	if (data) {
+		resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
+		xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
+		if (data->flags & MMC_DATA_READ) {
+			xfertype |= SDIO_XFER_MODE_TO_HOST;
+			waittype = SDIO_NOR_DMA_INI;
+		} else {
+			waittype |= SDIO_NOR_XFER_DONE;
+		}
+	} else {
+		waittype |= SDIO_NOR_CMD_DONE;
+	}
+
+	/* Setting cmd arguments */
+	mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
+	mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
+
+	/* Setting Xfer mode */
+	mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
+
+	mvebu_mmc_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT);
+	mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
+
+	/* Sending command */
+	mvebu_mmc_write(SDIO_CMD, resptype);
+
+	mvebu_mmc_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK);
+	mvebu_mmc_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK);
+
+	/* Waiting for completion */
+	timeout = 1000000;
+
+	while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
+		if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
+			debug("%s: error! cmdidx : %d, err reg: %04x\n",
+			      DRIVER_NAME, cmd->cmdidx,
+			      mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
+			if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
+				(SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
+				return TIMEOUT;
+			return COMM_ERR;
+		}
+
+		timeout--;
+		udelay(1);
+		if (timeout <= 0) {
+			printf("%s: command timed out\n", DRIVER_NAME);
+			return TIMEOUT;
+		}
+	}
+
+	/* Handling response */
+	if (cmd->resp_type & MMC_RSP_136) {
+		uint response[8];
+
+		for (resp_indx = 0; resp_indx < 8; resp_indx++)
+			response[resp_indx]
+				= mvebu_mmc_read(SDIO_RSP(resp_indx));
+
+		cmd->response[0] =	((response[0] & 0x03ff) << 22) |
+					((response[1] & 0xffff) << 6) |
+					((response[2] & 0xfc00) >> 10);
+		cmd->response[1] =	((response[2] & 0x03ff) << 22) |
+					((response[3] & 0xffff) << 6) |
+					((response[4] & 0xfc00) >> 10);
+		cmd->response[2] =	((response[4] & 0x03ff) << 22) |
+					((response[5] & 0xffff) << 6) |
+					((response[6] & 0xfc00) >> 10);
+		cmd->response[3] =	((response[6] & 0x03ff) << 22) |
+					((response[7] & 0x3fff) << 8);
+	} else if (cmd->resp_type & MMC_RSP_PRESENT) {
+		uint response[3];
+
+		for (resp_indx = 0; resp_indx < 3; resp_indx++)
+			response[resp_indx]
+				= mvebu_mmc_read(SDIO_RSP(resp_indx));
+
+		cmd->response[0] =	((response[2] & 0x003f) << (8 - 8)) |
+					((response[1] & 0xffff) << (14 - 8)) |
+					((response[0] & 0x03ff) << (30 - 8));
+		cmd->response[1] =	((response[0] & 0xfc00) >> 10);
+		cmd->response[2] =	0;
+		cmd->response[3] =	0;
+	}
+
+	debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
+	debug("[0x%x] ", cmd->response[0]);
+	debug("[0x%x] ", cmd->response[1]);
+	debug("[0x%x] ", cmd->response[2]);
+	debug("[0x%x] ", cmd->response[3]);
+	debug("\n");
+
+	return 0;
+}
+
+static void mvebu_mmc_power_up(void)
+{
+	debug("%s: power up\n", DRIVER_NAME);
+
+	/* disable interrupts */
+	mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
+	mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
+
+	/* SW reset */
+	mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
+
+	mvebu_mmc_write(SDIO_XFER_MODE, 0);
+
+	/* enable status */
+	mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
+	mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
+
+	/* enable interrupts status */
+	mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
+	mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
+}
+
+static void mvebu_mmc_set_clk(unsigned int clock)
+{
+	unsigned int m;
+
+	if (clock == 0) {
+		debug("%s: clock off\n", DRIVER_NAME);
+		mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
+		mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
+	} else {
+		m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
+		if (m > MVEBU_MMC_BASE_DIV_MAX)
+			m = MVEBU_MMC_BASE_DIV_MAX;
+		mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
+	}
+
+	udelay(10*1000);
+}
+
+static void mvebu_mmc_set_bus(unsigned int bus)
+{
+	u32 ctrl_reg = 0;
+
+	ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
+	ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
+
+	switch (bus) {
+	case 4:
+		ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
+		break;
+	case 1:
+	default:
+		ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
+	}
+
+	/* default transfer mode */
+	ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
+	ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
+
+	/* default to maximum timeout */
+	ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
+
+	ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
+
+	ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
+
+	debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
+	      (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
+	      "push-pull" : "open-drain",
+	      (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
+	      "4bit-width" : "1bit-width",
+	      (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
+	      "high-speed" : "");
+
+	mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
+	udelay(10*1000);
+}
+
+static void mvebu_mmc_set_ios(struct mmc *mmc)
+{
+	debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,
+	      mmc->bus_width, mmc->clock);
+	mvebu_mmc_set_bus(mmc->bus_width);
+	mvebu_mmc_set_clk(mmc->clock);
+}
+
+static int mvebu_mmc_initialize(struct mmc *mmc)
+{
+	debug("%s: mvebu_mmc_initialize", DRIVER_NAME);
+
+	/*
+	 * Setting host parameters
+	 * Initial Host Ctrl : Timeout : max , Normal Speed mode,
+	 * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
+	 */
+	mvebu_mmc_write(SDIO_HOST_CTRL,
+			SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
+			SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
+			SDIO_HOST_CTRL_BIG_ENDIAN |
+			SDIO_HOST_CTRL_PUSH_PULL_EN |
+			SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
+
+	mvebu_mmc_write(SDIO_CLK_CTRL, 0);
+
+	/* enable status */
+	mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
+	mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
+
+	/* disable interrupts */
+	mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
+	mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
+
+	/* SW reset */
+	mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
+
+	udelay(10*1000);
+
+	return 0;
+}
+
+static const struct mmc_ops mvebu_mmc_ops = {
+	.send_cmd	= mvebu_mmc_send_cmd,
+	.set_ios	= mvebu_mmc_set_ios,
+	.init		= mvebu_mmc_initialize,
+};
+
+static struct mmc_config mvebu_mmc_cfg = {
+	.name		= DRIVER_NAME,
+	.ops		= &mvebu_mmc_ops,
+	.f_min		= MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
+	.f_max		= MVEBU_MMC_CLOCKRATE_MAX,
+	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.host_caps	= MMC_MODE_4BIT | MMC_MODE_HS,
+	.part_type	= PART_TYPE_DOS,
+	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+
+int mvebu_mmc_init(bd_t *bis)
+{
+	struct mmc *mmc;
+
+	mvebu_mmc_power_up();
+
+	mmc = mmc_create(&mvebu_mmc_cfg, bis);
+	if (mmc == NULL)
+		return -1;
+
+	return 0;
+}
diff --git a/include/configs/openrd.h b/include/configs/openrd.h
index 8fab6e63e3b..3eb408f004b 100644
--- a/include/configs/openrd.h
+++ b/include/configs/openrd.h
@@ -49,6 +49,7 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_USB
@@ -123,4 +124,11 @@
 #define CONFIG_SYS_ATA_IDE1_OFFSET	MV_SATA_PORT1_OFFSET
 #endif /*CONFIG_MVSATA_IDE*/
 
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MVEBU_MMC
+#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
+#endif /* CONFIG_CMD_MMC */
+
 #endif /* _CONFIG_OPENRD_BASE_H */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index ecc93bc539d..3d6ff09cb01 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -31,6 +31,7 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_USB
@@ -81,6 +82,16 @@
 #define CONFIG_PHY_BASE_ADR	0
 #endif /* CONFIG_CMD_NET */
 
+/*
+ * SDIO/MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MVEBU_MMC
+#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
+#endif /* CONFIG_CMD_MMC */
+
 /*
  * File system
  */
diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h
new file mode 100644
index 00000000000..28d98fe148a
--- /dev/null
+++ b/include/mvebu_mmc.h
@@ -0,0 +1,278 @@
+/*
+ * Marvell MMC/SD/SDIO driver
+ *
+ * (C) Copyright 2012
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Maen Suleiman, Gerald Kerma
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MVEBU_MMC_H__
+#define __MVEBU_MMC_H__
+
+/* needed for the mmc_cfg definition */
+#include <mmc.h>
+
+#define MMC_BLOCK_SIZE				512
+
+/*
+ * Clock rates
+ */
+
+#define MVEBU_MMC_CLOCKRATE_MAX			50000000
+#define MVEBU_MMC_BASE_DIV_MAX			0x7ff
+#define MVEBU_MMC_BASE_FAST_CLOCK		CONFIG_SYS_TCLK
+#define MVEBU_MMC_BASE_FAST_CLK_100		100000000
+#define MVEBU_MMC_BASE_FAST_CLK_200		200000000
+
+/* SDIO register */
+#define SDIO_SYS_ADDR_LOW			0x000
+#define SDIO_SYS_ADDR_HI			0x004
+#define SDIO_BLK_SIZE				0x008
+#define SDIO_BLK_COUNT				0x00c
+#define SDIO_ARG_LOW				0x010
+#define SDIO_ARG_HI				0x014
+#define SDIO_XFER_MODE				0x018
+#define SDIO_CMD				0x01c
+#define SDIO_RSP(i)				(0x020 + ((i)<<2))
+#define SDIO_RSP0				0x020
+#define SDIO_RSP1				0x024
+#define SDIO_RSP2				0x028
+#define SDIO_RSP3				0x02c
+#define SDIO_RSP4				0x030
+#define SDIO_RSP5				0x034
+#define SDIO_RSP6				0x038
+#define SDIO_RSP7				0x03c
+#define SDIO_BUF_DATA_PORT			0x040
+#define SDIO_RSVED				0x044
+#define SDIO_HW_STATE				0x048
+#define SDIO_PRESENT_STATE0			0x048
+#define SDIO_PRESENT_STATE1			0x04c
+#define SDIO_HOST_CTRL				0x050
+#define SDIO_BLK_GAP_CTRL			0x054
+#define SDIO_CLK_CTRL				0x058
+#define SDIO_SW_RESET				0x05c
+#define SDIO_NOR_INTR_STATUS			0x060
+#define SDIO_ERR_INTR_STATUS			0x064
+#define SDIO_NOR_STATUS_EN			0x068
+#define SDIO_ERR_STATUS_EN			0x06c
+#define SDIO_NOR_INTR_EN			0x070
+#define SDIO_ERR_INTR_EN			0x074
+#define SDIO_AUTOCMD12_ERR_STATUS		0x078
+#define SDIO_CURR_BYTE_LEFT			0x07c
+#define SDIO_CURR_BLK_LEFT			0x080
+#define SDIO_AUTOCMD12_ARG_LOW			0x084
+#define SDIO_AUTOCMD12_ARG_HI			0x088
+#define SDIO_AUTOCMD12_INDEX			0x08c
+#define SDIO_AUTO_RSP(i)			(0x090 + ((i)<<2))
+#define SDIO_AUTO_RSP0				0x090
+#define SDIO_AUTO_RSP1				0x094
+#define SDIO_AUTO_RSP2				0x098
+#define SDIO_CLK_DIV				0x128
+
+#define WINDOW_CTRL(i)				(0x108 + ((i) << 3))
+#define WINDOW_BASE(i)				(0x10c + ((i) << 3))
+
+/* SDIO_PRESENT_STATE */
+#define CARD_BUSY				(1 << 1)
+#define CMD_INHIBIT				(1 << 0)
+#define CMD_TXACTIVE				(1 << 8)
+#define CMD_RXACTIVE				(1 << 9)
+#define CMD_AUTOCMD12ACTIVE			(1 << 14)
+#define CMD_BUS_BUSY				(CMD_AUTOCMD12ACTIVE |	\
+						CMD_RXACTIVE |	\
+						CMD_TXACTIVE |	\
+						CMD_INHIBIT |	\
+						CARD_BUSY)
+
+/*
+ * SDIO_CMD
+ */
+
+#define SDIO_CMD_RSP_NONE			(0 << 0)
+#define SDIO_CMD_RSP_136			(1 << 0)
+#define SDIO_CMD_RSP_48				(2 << 0)
+#define SDIO_CMD_RSP_48BUSY			(3 << 0)
+
+#define SDIO_CMD_CHECK_DATACRC16		(1 << 2)
+#define SDIO_CMD_CHECK_CMDCRC			(1 << 3)
+#define SDIO_CMD_INDX_CHECK			(1 << 4)
+#define SDIO_CMD_DATA_PRESENT			(1 << 5)
+#define SDIO_UNEXPECTED_RESP			(1 << 7)
+
+#define SDIO_CMD_INDEX(x)			((x) << 8)
+
+/*
+ * SDIO_XFER_MODE
+ */
+
+#define SDIO_XFER_MODE_STOP_CLK			(1 << 5)
+#define SDIO_XFER_MODE_HW_WR_DATA_EN		(1 << 1)
+#define SDIO_XFER_MODE_AUTO_CMD12		(1 << 2)
+#define SDIO_XFER_MODE_INT_CHK_EN		(1 << 3)
+#define SDIO_XFER_MODE_TO_HOST			(1 << 4)
+#define SDIO_XFER_MODE_DMA			(0 << 6)
+
+/*
+ * SDIO_HOST_CTRL
+ */
+
+#define SDIO_HOST_CTRL_PUSH_PULL_EN		(1 << 0)
+
+#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY	(0 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY	(1 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO	(2 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC		(3 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_MASK		(3 << 1)
+
+#define SDIO_HOST_CTRL_BIG_ENDIAN		(1 << 3)
+#define SDIO_HOST_CTRL_LSB_FIRST		(1 << 4)
+#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT		(0 << 9)
+#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS	(1 << 9)
+#define SDIO_HOST_CTRL_HI_SPEED_EN		(1 << 10)
+
+#define SDIO_HOST_CTRL_TMOUT_MAX		0xf
+#define SDIO_HOST_CTRL_TMOUT_MASK		(0xf << 11)
+#define SDIO_HOST_CTRL_TMOUT(x)			((x) << 11)
+#define SDIO_HOST_CTRL_TMOUT_EN			(1 << 15)
+
+/*
+ * SDIO_SW_RESET
+ */
+
+#define SDIO_SW_RESET_NOW			(1 << 8)
+
+/*
+ * Normal interrupt status bits
+ */
+
+#define SDIO_NOR_ERROR				(1 << 15)
+#define SDIO_NOR_UNEXP_RSP			(1 << 14)
+#define SDIO_NOR_AUTOCMD12_DONE			(1 << 13)
+#define SDIO_NOR_SUSPEND_ON			(1 << 12)
+#define SDIO_NOR_LMB_FF_8W_AVAIL		(1 << 11)
+#define SDIO_NOR_LMB_FF_8W_FILLED		(1 << 10)
+#define SDIO_NOR_READ_WAIT_ON			(1 << 9)
+#define SDIO_NOR_CARD_INT			(1 << 8)
+#define SDIO_NOR_READ_READY			(1 << 5)
+#define SDIO_NOR_WRITE_READY			(1 << 4)
+#define SDIO_NOR_DMA_INI			(1 << 3)
+#define SDIO_NOR_BLK_GAP_EVT			(1 << 2)
+#define SDIO_NOR_XFER_DONE			(1 << 1)
+#define SDIO_NOR_CMD_DONE			(1 << 0)
+
+/*
+ * Error status bits
+ */
+
+#define SDIO_ERR_CRC_STATUS			(1 << 14)
+#define SDIO_ERR_CRC_STARTBIT			(1 << 13)
+#define SDIO_ERR_CRC_ENDBIT			(1 << 12)
+#define SDIO_ERR_RESP_TBIT			(1 << 11)
+#define SDIO_ERR_XFER_SIZE			(1 << 10)
+#define SDIO_ERR_CMD_STARTBIT			(1 << 9)
+#define SDIO_ERR_AUTOCMD12			(1 << 8)
+#define SDIO_ERR_DATA_ENDBIT			(1 << 6)
+#define SDIO_ERR_DATA_CRC			(1 << 5)
+#define SDIO_ERR_DATA_TIMEOUT			(1 << 4)
+#define SDIO_ERR_CMD_INDEX			(1 << 3)
+#define SDIO_ERR_CMD_ENDBIT			(1 << 2)
+#define SDIO_ERR_CMD_CRC			(1 << 1)
+#define SDIO_ERR_CMD_TIMEOUT			(1 << 0)
+/* enable all for polling */
+#define SDIO_POLL_MASK				0xffff
+
+/*
+ * CMD12 error status bits
+ */
+
+#define SDIO_AUTOCMD12_ERR_NOTEXE		(1 << 0)
+#define SDIO_AUTOCMD12_ERR_TIMEOUT		(1 << 1)
+#define SDIO_AUTOCMD12_ERR_CRC			(1 << 2)
+#define SDIO_AUTOCMD12_ERR_ENDBIT		(1 << 3)
+#define SDIO_AUTOCMD12_ERR_INDEX		(1 << 4)
+#define SDIO_AUTOCMD12_ERR_RESP_T_BIT		(1 << 5)
+#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT	(1 << 6)
+
+#define MMC_RSP_PRESENT				(1 << 0)
+/* 136 bit response */
+#define MMC_RSP_136				(1 << 1)
+/* expect valid crc */
+#define MMC_RSP_CRC				(1 << 2)
+/* card may send busy */
+#define MMC_RSP_BUSY				(1 << 3)
+/* response contains opcode */
+#define MMC_RSP_OPCODE				(1 << 4)
+
+#define MMC_BUSMODE_OPENDRAIN			1
+#define MMC_BUSMODE_PUSHPULL			2
+
+#define MMC_BUS_WIDTH_1				0
+#define MMC_BUS_WIDTH_4				2
+#define MMC_BUS_WIDTH_8				3
+
+/* Can the host do 4 bit transfers */
+#define MMC_CAP_4_BIT_DATA			(1 << 0)
+/* Can do MMC high-speed timing */
+#define MMC_CAP_MMC_HIGHSPEED			(1 << 1)
+/* Can do SD high-speed timing */
+#define MMC_CAP_SD_HIGHSPEED			(1 << 2)
+/* Can signal pending SDIO IRQs */
+#define MMC_CAP_SDIO_IRQ			(1 << 3)
+/* Talks only SPI protocols */
+#define MMC_CAP_SPI				(1 << 4)
+/* Needs polling for card-detection */
+#define MMC_CAP_NEEDS_POLL			(1 << 5)
+/* Can the host do 8 bit transfers */
+#define MMC_CAP_8_BIT_DATA			(1 << 6)
+
+/* Nonremovable e.g. eMMC */
+#define MMC_CAP_NONREMOVABLE			(1 << 8)
+/* Waits while card is busy */
+#define MMC_CAP_WAIT_WHILE_BUSY			(1 << 9)
+/* Allow erase/trim commands */
+#define MMC_CAP_ERASE				(1 << 10)
+/* can support DDR mode at 1.8V */
+#define MMC_CAP_1_8V_DDR			(1 << 11)
+/* can support DDR mode at 1.2V */
+#define MMC_CAP_1_2V_DDR			(1 << 12)
+/* Can power off after boot */
+#define MMC_CAP_POWER_OFF_CARD			(1 << 13)
+/* CMD14/CMD19 bus width ok */
+#define MMC_CAP_BUS_WIDTH_TEST			(1 << 14)
+/* Host supports UHS SDR12 mode */
+#define MMC_CAP_UHS_SDR12			(1 << 15)
+/* Host supports UHS SDR25 mode */
+#define MMC_CAP_UHS_SDR25			(1 << 16)
+/* Host supports UHS SDR50 mode */
+#define MMC_CAP_UHS_SDR50			(1 << 17)
+/* Host supports UHS SDR104 mode */
+#define MMC_CAP_UHS_SDR104			(1 << 18)
+/* Host supports UHS DDR50 mode */
+#define MMC_CAP_UHS_DDR50			(1 << 19)
+/* Host supports Driver Type A */
+#define MMC_CAP_DRIVER_TYPE_A			(1 << 23)
+/* Host supports Driver Type C */
+#define MMC_CAP_DRIVER_TYPE_C			(1 << 24)
+/* Host supports Driver Type D */
+#define MMC_CAP_DRIVER_TYPE_D			(1 << 25)
+/* CMD23 supported. */
+#define MMC_CAP_CMD23				(1 << 30)
+/* Hardware reset */
+#define MMC_CAP_HW_RESET			(1 << 31)
+
+struct mvebu_mmc_cfg {
+	u32	mvebu_mmc_base;
+	u32	mvebu_mmc_clk;
+	u8	max_bus_width;
+	struct mmc_config cfg;
+};
+
+/*
+ * Functions prototypes
+ */
+
+int mvebu_mmc_init(bd_t *bis);
+
+#endif /* __MVEBU_MMC_H__ */
-- 
cgit v1.3.1


From 64973023df4f31e72ecc56005f123da5841f7066 Mon Sep 17 00:00:00 2001
From: Lubomir Rintel <lkundrak@v3.sk>
Date: Tue, 10 Jun 2014 20:46:43 +0200
Subject: bcm2835_sdhci: Add SDHCI_QUIRK_NO_HISPD_BIT flag

Seems like the controller doesn't support the flag. None of the hi-speed cards
I've tried could be read, while they successfully worked with the quirk enabled.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
---
 drivers/mmc/bcm2835_sdhci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
index 54cfabfb91e..82079d67cd8 100644
--- a/drivers/mmc/bcm2835_sdhci.c
+++ b/drivers/mmc/bcm2835_sdhci.c
@@ -179,7 +179,7 @@ int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq)
 	host->name = "bcm2835_sdhci";
 	host->ioaddr = (void *)regbase;
 	host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
-		SDHCI_QUIRK_WAIT_SEND_CMD;
+		SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
 	host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 	host->ops = &bcm2835_ops;
 
-- 
cgit v1.3.1


From dae0f5c644c0f76e67306bd49c09d95373b7357a Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 22 Jul 2014 02:34:52 +0200
Subject: mmc: s3c: Add SD driver

Implement SD driver for the S3C24xx family. This implementation
is currently only capable of using the PIO transfers, DMA is not
supported.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
---
 arch/arm/include/asm/arch-s3c24x0/s3c24x0.h |   6 +
 drivers/mmc/Makefile                        |   1 +
 drivers/mmc/s3c_sdi.c                       | 321 ++++++++++++++++++++++++++++
 3 files changed, 328 insertions(+)
 create mode 100644 drivers/mmc/s3c_sdi.c

(limited to 'drivers')

diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index c122eb90927..ed9df34c690 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -700,4 +700,10 @@ struct s3c24x0_sdi {
 #endif
 };
 
+#ifdef CONFIG_CMD_MMC
+#include <mmc.h>
+int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *),
+		      int (*getwp)(struct mmc *));
+#endif
+
 #endif /*__S3C24X0_H__*/
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index f5be96f5e51..464cee16d11 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
 obj-$(CONFIG_SDHCI) += sdhci.o
 obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
 obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
+obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
 obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
diff --git a/drivers/mmc/s3c_sdi.c b/drivers/mmc/s3c_sdi.c
new file mode 100644
index 00000000000..1b5b70512d1
--- /dev/null
+++ b/drivers/mmc/s3c_sdi.c
@@ -0,0 +1,321 @@
+/*
+ * S3C24xx SD/MMC driver
+ *
+ * Based on OpenMoko S3C24xx driver by Harald Welte <laforge@openmoko.org>
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <errno.h>
+#include <asm/arch/s3c24x0_cpu.h>
+#include <asm/io.h>
+#include <asm/unaligned.h>
+
+#define S3C2440_SDICON_SDRESET		(1 << 8)
+#define S3C2410_SDICON_FIFORESET	(1 << 1)
+#define S3C2410_SDICON_CLOCKTYPE	(1 << 0)
+
+#define S3C2410_SDICMDCON_LONGRSP	(1 << 10)
+#define S3C2410_SDICMDCON_WAITRSP	(1 << 9)
+#define S3C2410_SDICMDCON_CMDSTART	(1 << 8)
+#define S3C2410_SDICMDCON_SENDERHOST	(1 << 6)
+#define S3C2410_SDICMDCON_INDEX		0x3f
+
+#define S3C2410_SDICMDSTAT_CRCFAIL	(1 << 12)
+#define S3C2410_SDICMDSTAT_CMDSENT	(1 << 11)
+#define S3C2410_SDICMDSTAT_CMDTIMEOUT	(1 << 10)
+#define S3C2410_SDICMDSTAT_RSPFIN	(1 << 9)
+
+#define S3C2440_SDIDCON_DS_WORD		(2 << 22)
+#define S3C2410_SDIDCON_TXAFTERRESP	(1 << 20)
+#define S3C2410_SDIDCON_RXAFTERCMD	(1 << 19)
+#define S3C2410_SDIDCON_BLOCKMODE	(1 << 17)
+#define S3C2410_SDIDCON_WIDEBUS		(1 << 16)
+#define S3C2440_SDIDCON_DATSTART	(1 << 14)
+#define S3C2410_SDIDCON_XFER_RXSTART	(2 << 12)
+#define S3C2410_SDIDCON_XFER_TXSTART	(3 << 12)
+#define S3C2410_SDIDCON_BLKNUM		0x7ff
+
+#define S3C2410_SDIDSTA_FIFOFAIL	(1 << 8)
+#define S3C2410_SDIDSTA_CRCFAIL		(1 << 7)
+#define S3C2410_SDIDSTA_RXCRCFAIL	(1 << 6)
+#define S3C2410_SDIDSTA_DATATIMEOUT	(1 << 5)
+#define S3C2410_SDIDSTA_XFERFINISH	(1 << 4)
+
+#define S3C2410_SDIFSTA_TFHALF		(1 << 11)
+#define S3C2410_SDIFSTA_COUNTMASK	0x7f
+
+/*
+ * WARNING: We only support one SD IP block.
+ * NOTE: It's not likely there will ever exist an S3C24xx with two,
+ *       at least not in this universe all right.
+ */
+static int wide_bus;
+
+static int
+s3cmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+	struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
+	uint32_t sdiccon, sdicsta, sdidcon, sdidsta, sdidat, sdifsta;
+	uint32_t sdicsta_wait_bit = S3C2410_SDICMDSTAT_CMDSENT;
+	unsigned int timeout = 100000;
+	int ret = 0, xfer_len, data_offset = 0;
+	const uint32_t sdidsta_err_mask = S3C2410_SDIDSTA_FIFOFAIL |
+		S3C2410_SDIDSTA_CRCFAIL | S3C2410_SDIDSTA_RXCRCFAIL |
+		S3C2410_SDIDSTA_DATATIMEOUT;
+
+
+	writel(0xffffffff, &sdi_regs->sdicsta);
+	writel(0xffffffff, &sdi_regs->sdidsta);
+	writel(0xffffffff, &sdi_regs->sdifsta);
+
+	/* Set up data transfer (if applicable). */
+	if (data) {
+		writel(data->blocksize, &sdi_regs->sdibsize);
+
+		sdidcon = data->blocks & S3C2410_SDIDCON_BLKNUM;
+		sdidcon |= S3C2410_SDIDCON_BLOCKMODE;
+#if defined(CONFIG_S3C2440)
+		sdidcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART;
+#endif
+		if (wide_bus)
+			sdidcon |= S3C2410_SDIDCON_WIDEBUS;
+
+		if (data->flags & MMC_DATA_READ) {
+			sdidcon |= S3C2410_SDIDCON_RXAFTERCMD;
+			sdidcon |= S3C2410_SDIDCON_XFER_RXSTART;
+		} else {
+			sdidcon |= S3C2410_SDIDCON_TXAFTERRESP;
+			sdidcon |= S3C2410_SDIDCON_XFER_TXSTART;
+		}
+
+		writel(sdidcon, &sdi_regs->sdidcon);
+	}
+
+	/* Write CMD arg. */
+	writel(cmd->cmdarg, &sdi_regs->sdicarg);
+
+	/* Write CMD index. */
+	sdiccon = cmd->cmdidx & S3C2410_SDICMDCON_INDEX;
+	sdiccon |= S3C2410_SDICMDCON_SENDERHOST;
+	sdiccon |= S3C2410_SDICMDCON_CMDSTART;
+
+	/* Command with short response. */
+	if (cmd->resp_type & MMC_RSP_PRESENT) {
+		sdiccon |= S3C2410_SDICMDCON_WAITRSP;
+		sdicsta_wait_bit = S3C2410_SDICMDSTAT_RSPFIN;
+	}
+
+	/* Command with long response. */
+	if (cmd->resp_type & MMC_RSP_136)
+		sdiccon |= S3C2410_SDICMDCON_LONGRSP;
+
+	/* Start the command. */
+	writel(sdiccon, &sdi_regs->sdiccon);
+
+	/* Wait for the command to complete or for response. */
+	for (timeout = 100000; timeout; timeout--) {
+		sdicsta = readl(&sdi_regs->sdicsta);
+		if (sdicsta & sdicsta_wait_bit)
+			break;
+
+		if (sdicsta & S3C2410_SDICMDSTAT_CMDTIMEOUT)
+			timeout = 1;
+	}
+
+	/* Clean the status bits. */
+	setbits_le32(&sdi_regs->sdicsta, 0xf << 9);
+
+	if (!timeout) {
+		puts("S3C SDI: Command timed out!\n");
+		ret = TIMEOUT;
+		goto error;
+	}
+
+	/* Read out the response. */
+	if (cmd->resp_type & MMC_RSP_136) {
+		cmd->response[0] = readl(&sdi_regs->sdirsp0);
+		cmd->response[1] = readl(&sdi_regs->sdirsp1);
+		cmd->response[2] = readl(&sdi_regs->sdirsp2);
+		cmd->response[3] = readl(&sdi_regs->sdirsp3);
+	} else {
+		cmd->response[0] = readl(&sdi_regs->sdirsp0);
+	}
+
+	/* If there are no data, we're done. */
+	if (!data)
+		return 0;
+
+	xfer_len = data->blocksize * data->blocks;
+
+	while (xfer_len > 0) {
+		sdidsta = readl(&sdi_regs->sdidsta);
+		sdifsta = readl(&sdi_regs->sdifsta);
+
+		if (sdidsta & sdidsta_err_mask) {
+			printf("S3C SDI: Data error (sdta=0x%08x)\n", sdidsta);
+			ret = -EIO;
+			goto error;
+		}
+
+		if (data->flags & MMC_DATA_READ) {
+			if ((sdifsta & S3C2410_SDIFSTA_COUNTMASK) < 4)
+				continue;
+			sdidat = readl(&sdi_regs->sdidat);
+			put_unaligned_le32(sdidat, data->dest + data_offset);
+		} else {	/* Write */
+			/* TX FIFO half full. */
+			if (!(sdifsta & S3C2410_SDIFSTA_TFHALF))
+				continue;
+
+			/* TX FIFO is below 32b full, write. */
+			sdidat = get_unaligned_le32(data->src + data_offset);
+			writel(sdidat, &sdi_regs->sdidat);
+		}
+		data_offset += 4;
+		xfer_len -= 4;
+	}
+
+	/* Wait for the command to complete or for response. */
+	for (timeout = 100000; timeout; timeout--) {
+		sdidsta = readl(&sdi_regs->sdidsta);
+		if (sdidsta & S3C2410_SDIDSTA_XFERFINISH)
+			break;
+
+		if (sdidsta & S3C2410_SDIDSTA_DATATIMEOUT)
+			timeout = 1;
+	}
+
+	/* Clear status bits. */
+	writel(0x6f8, &sdi_regs->sdidsta);
+
+	if (!timeout) {
+		puts("S3C SDI: Command timed out!\n");
+		ret = TIMEOUT;
+		goto error;
+	}
+
+	writel(0, &sdi_regs->sdidcon);
+
+	return 0;
+error:
+	return ret;
+}
+
+static void s3cmmc_set_ios(struct mmc *mmc)
+{
+	struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
+	uint32_t divider = 0;
+
+	wide_bus = (mmc->bus_width == 4);
+
+	if (!mmc->clock)
+		return;
+
+	divider = DIV_ROUND_UP(get_PCLK(), mmc->clock);
+	if (divider)
+		divider--;
+
+	writel(divider, &sdi_regs->sdipre);
+	mdelay(125);
+}
+
+static int s3cmmc_init(struct mmc *mmc)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+	struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
+
+	/* Start the clock. */
+	setbits_le32(&clk_power->clkcon, 1 << 9);
+
+#if defined(CONFIG_S3C2440)
+	writel(S3C2440_SDICON_SDRESET, &sdi_regs->sdicon);
+	mdelay(10);
+	writel(0x7fffff, &sdi_regs->sdidtimer);
+#else
+	writel(0xffff, &sdi_regs->sdidtimer);
+#endif
+	writel(MMC_MAX_BLOCK_LEN, &sdi_regs->sdibsize);
+	writel(0x0, &sdi_regs->sdiimsk);
+
+	writel(S3C2410_SDICON_FIFORESET | S3C2410_SDICON_CLOCKTYPE,
+	       &sdi_regs->sdicon);
+
+	mdelay(125);
+
+	return 0;
+}
+
+struct s3cmmc_priv {
+	struct mmc_config	cfg;
+	int (*getcd)(struct mmc *);
+	int (*getwp)(struct mmc *);
+};
+
+static int s3cmmc_getcd(struct mmc *mmc)
+{
+	struct s3cmmc_priv *priv = mmc->priv;
+	if (priv->getcd)
+		return priv->getcd(mmc);
+	else
+		return 0;
+}
+
+static int s3cmmc_getwp(struct mmc *mmc)
+{
+	struct s3cmmc_priv *priv = mmc->priv;
+	if (priv->getwp)
+		return priv->getwp(mmc);
+	else
+		return 0;
+}
+
+static const struct mmc_ops s3cmmc_ops = {
+	.send_cmd	= s3cmmc_send_cmd,
+	.set_ios	= s3cmmc_set_ios,
+	.init		= s3cmmc_init,
+	.getcd		= s3cmmc_getcd,
+	.getwp		= s3cmmc_getwp,
+};
+
+int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *),
+		      int (*getwp)(struct mmc *))
+{
+	struct s3cmmc_priv	*priv;
+	struct mmc		*mmc;
+	struct mmc_config	*cfg;
+
+	priv = calloc(1, sizeof(*priv));
+	if (!priv)
+		return -ENOMEM;
+	cfg = &priv->cfg;
+
+	cfg->name = "S3C MMC";
+	cfg->ops = &s3cmmc_ops;
+	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+	cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HC | MMC_MODE_HS;
+	cfg->f_min = 400000;
+	cfg->f_max = get_PCLK() / 2;
+	cfg->b_max = 0x80;
+
+#if defined(CONFIG_S3C2410)
+	/*
+	 * S3C2410 has some bug that prevents reliable
+	 * operation at higher speed
+	 */
+	cfg->f_max /= 2;
+#endif
+
+	mmc = mmc_create(cfg, priv);
+	if (!mmc) {
+		free(priv);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
-- 
cgit v1.3.1


From 6ace153d130f528b88117b1edcfe017ea1852d67 Mon Sep 17 00:00:00 2001
From: Chin Liang See <clsee@altera.com>
Date: Tue, 10 Jun 2014 01:26:52 -0500
Subject: mmc/dw_mmc: Fix clock divider calculation error for bypass mode

To fix the clock divider calculation error when the controller
clock same as the operating frequency. This is known as bypass
mode. In this mode, the divider should be 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Mischa Jonker <mjonker@synopsys.com>
---
 drivers/mmc/dw_mmc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 5bf36a0309d..0df30bc0453 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -245,7 +245,10 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 		return -EINVAL;
 	}
 
-	div = DIV_ROUND_UP(sclk, 2 * freq);
+	if (sclk == freq)
+		div = 0;	/* bypass mode */
+	else
+		div = DIV_ROUND_UP(sclk, 2 * freq);
 
 	dwmci_writel(host, DWMCI_CLKENA, 0);
 	dwmci_writel(host, DWMCI_CLKSRC, 0);
-- 
cgit v1.3.1


From cd60ebd430ab0aa5e2ed6afeb28c1ed4b2d01388 Mon Sep 17 00:00:00 2001
From: Bo Shen <voice.shen@atmel.com>
Date: Thu, 31 Jul 2014 14:39:30 +0800
Subject: MMC: atmel_mci: refactor setting the mode register

The mode register is different between MCI IP version.
So, according to MCI IP version to set the mode register.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
---
 drivers/mmc/gen_atmel_mci.c | 56 +++++++++++++++++++++++++++++++++------------
 include/atmel_mci.h         |  4 ++++
 2 files changed, 46 insertions(+), 14 deletions(-)

(limited to 'drivers')

diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index a57a9b1faff..8778a4d8128 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -58,30 +58,58 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
 	atmel_mci_t *mci = mmc->priv;
 	u32 bus_hz = get_mci_clk_rate();
 	u32 clkdiv = 255;
+	unsigned int version = atmel_mci_get_version(mci);
+	u32 clkodd = 0;
+	u32 mr;
 
 	debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
 		bus_hz, hz, blklen);
 	if (hz > 0) {
-		/* find lowest clkdiv yielding a rate <= than requested */
-		for (clkdiv=0; clkdiv<255; clkdiv++) {
-			if ((bus_hz / (clkdiv+1) / 2) <= hz)
-				break;
+		if (version >= 0x500) {
+			clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2;
+			if (clkdiv > 511)
+				clkdiv = 511;
+
+			clkodd = clkdiv & 1;
+			clkdiv >>= 1;
+
+			printf("mci: setting clock %u Hz, block size %u\n",
+			       bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
+		} else {
+			/* find clkdiv yielding a rate <= than requested */
+			for (clkdiv = 0; clkdiv < 255; clkdiv++) {
+				if ((bus_hz / (clkdiv + 1) / 2) <= hz)
+					break;
+			}
+			printf("mci: setting clock %u Hz, block size %u\n",
+			       (bus_hz / (clkdiv + 1)) / 2, blklen);
+
 		}
 	}
-	printf("mci: setting clock %u Hz, block size %u\n",
-		(bus_hz / (clkdiv+1)) / 2, blklen);
 
 	blklen &= 0xfffc;
-	/* On some platforms RDPROOF and WRPROOF are ignored */
-	writel((MMCI_BF(CLKDIV, clkdiv)
-		 | MMCI_BF(BLKLEN, blklen)
-		 | MMCI_BIT(RDPROOF)
-		 | MMCI_BIT(WRPROOF)), &mci->mr);
+
+	mr = MMCI_BF(CLKDIV, clkdiv);
+
+	/* MCI IP version >= 0x200 has R/WPROOF */
+	if (version >= 0x200)
+		mr |= MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF);
+
 	/*
-	 * On some new platforms BLKLEN in mci->mr is ignored.
-	 * Should use the BLKLEN in the block register.
+	 * MCI IP version >= 0x500 use bit 16 as clkodd.
+	 * MCI IP version < 0x500 use upper 16 bits for blklen.
 	 */
-	writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
+	if (version >= 0x500)
+		mr |= MMCI_BF(CLKODD, clkodd);
+	else
+		mr |= MMCI_BF(BLKLEN, blklen);
+
+	writel(mr, &mci->mr);
+
+	/* MCI IP version >= 0x200 has blkr */
+	if (version >= 0x200)
+		writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
+
 	initialized = 1;
 }
 
diff --git a/include/atmel_mci.h b/include/atmel_mci.h
index 090574d8c29..3d2870fc9cb 100644
--- a/include/atmel_mci.h
+++ b/include/atmel_mci.h
@@ -67,6 +67,10 @@ typedef struct atmel_mci {
 #define MMCI_PDCPADV_SIZE			1
 #define MMCI_PDCMODE_OFFSET			15
 #define MMCI_PDCMODE_SIZE			1
+/* MCI IP version >= 0x500, MR bit 16 used for CLKODD */
+#define MMCI_CLKODD_OFFSET			16
+#define MMCI_CLKODD_SIZE			1
+/* MCI IP version < 0x200, MR higher 16bits for BLKLEN */
 #define MMCI_BLKLEN_OFFSET			16
 #define MMCI_BLKLEN_SIZE			16
 
-- 
cgit v1.3.1


From da55c66ec92c962435175cf0b4f4d61732ca3ebf Mon Sep 17 00:00:00 2001
From: Bo Shen <voice.shen@atmel.com>
Date: Thu, 31 Jul 2014 14:39:32 +0800
Subject: MMC: atmel_mci: enable high speed mode support

If the MCI IP version >= 0x300, it supports hight speed mode
option, this patch enable it.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
---
 drivers/mmc/gen_atmel_mci.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'drivers')

diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 8778a4d8128..45bcffb6b20 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -110,6 +110,9 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
 	if (version >= 0x200)
 		writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
 
+	if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
+		writel(MMCI_BIT(HSMODE), &mci->cfg);
+
 	initialized = 1;
 }
 
@@ -404,8 +407,10 @@ int atmel_mci_init(void *regs)
 	/* need to be able to pass these in on a board by board basis */
 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 	version = atmel_mci_get_version(mci);
-	if ((version & 0xf00) >= 0x300)
+	if ((version & 0xf00) >= 0x300) {
 		cfg->host_caps = MMC_MODE_8BIT;
+		cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+	}
 
 	cfg->host_caps |= MMC_MODE_4BIT;
 
-- 
cgit v1.3.1


From a52a178f0b4dce6a85a45ccea348be92fc7f1b6d Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sat, 12 Jul 2014 18:11:31 +0530
Subject: sf: sf_ops: Stop leaking memory

It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 drivers/mtd/spi/sf_ops.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'drivers')

diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index ef91b924d7d..85cf22d42ec 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -421,6 +421,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 		data += read_len;
 	}
 
+	free(cmd);
 	return ret;
 }
 
-- 
cgit v1.3.1


From 2001b9a64165658e14f5afbe16874e0c55ddd04f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 7 Jul 2014 10:16:37 -0600
Subject: cros_ec: Fix two bugs in the SPI implementation

An incorrect message version is passed to the EC in some cases and the
parameters of one function are switched.

Fix these problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 drivers/misc/cros_ec_spi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'drivers')

diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
index 7df709cc714..015333f139a 100644
--- a/drivers/misc/cros_ec_spi.c
+++ b/drivers/misc/cros_ec_spi.c
@@ -98,7 +98,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 	}
 
 	out = dev->dout;
-	out[0] = cmd_version;
+	out[0] = EC_CMD_VERSION0 + cmd_version;
 	out[1] = cmd;
 	out[2] = (uint8_t)dout_len;
 	memcpy(out + 3, dout, dout_len);
@@ -165,7 +165,7 @@ int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob)
  */
 int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob)
 {
-	dev->spi = spi_setup_slave_fdt(blob, dev->parent_node, dev->node);
+	dev->spi = spi_setup_slave_fdt(blob, dev->node, dev->parent_node);
 	if (!dev->spi) {
 		debug("%s: Could not setup SPI slave\n", __func__);
 		return -1;
-- 
cgit v1.3.1


From a4e29db2571144a05ad09380b3674fe5b492f693 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 7 Jul 2014 10:16:38 -0600
Subject: exynos: spi: Fix calculation of SPI transaction start time

The SPI transaction delay is supposed to be measured from the end of one
transaction to the start of the next. The code does not work that way, so
fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 drivers/spi/exynos_spi.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'drivers')

diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index c92276fdf71..2969184ee87 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -428,10 +428,6 @@ void spi_cs_activate(struct spi_slave *slave)
 	clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
 	debug("Activate CS, bus %d\n", spi_slave->slave.bus);
 	spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
-
-	/* Remember time of this transaction so we can honour the bus delay */
-	if (spi_slave->bus->deactivate_delay_us)
-		spi_slave->last_transaction_us = timer_get_us();
 }
 
 /**
@@ -445,6 +441,11 @@ void spi_cs_deactivate(struct spi_slave *slave)
 	struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
 
 	setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
+
+	/* Remember time of this transaction so we can honour the bus delay */
+	if (spi_slave->bus->deactivate_delay_us)
+		spi_slave->last_transaction_us = timer_get_us();
+
 	debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
 }
 
-- 
cgit v1.3.1


From 22052c6236cbebc446ffd51ac69271fe063c654a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 7 Jul 2014 10:16:39 -0600
Subject: spi: Support half-duplex mode in FDT decode

This parameter should also be supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 doc/device-tree-bindings/spi/spi-bus.txt | 2 ++
 drivers/spi/spi.c                        | 2 ++
 2 files changed, 4 insertions(+)

(limited to 'drivers')

diff --git a/doc/device-tree-bindings/spi/spi-bus.txt b/doc/device-tree-bindings/spi/spi-bus.txt
index 800dafe5b01..5c8720a820a 100644
--- a/doc/device-tree-bindings/spi/spi-bus.txt
+++ b/doc/device-tree-bindings/spi/spi-bus.txt
@@ -59,6 +59,8 @@ contain the following properties.
                       used for MOSI. Defaults to 1 if not present.
 - spi-rx-bus-width - (optional) The bus width(number of data wires) that
                       used for MISO. Defaults to 1 if not present.
+- spi-half-duplex  - (optional) Indicates that the SPI bus should wait for
+		      a header byte before reading data from the slave.
 
 Some SPI controllers and devices support Dual and Quad SPI transfer mode.
 It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD).
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 7ddea9b026a..7d81fbd7f8f 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -53,6 +53,8 @@ struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum,
 		mode |= SPI_CPHA;
 	if (fdtdec_get_bool(blob, node, "spi-cs-high"))
 		mode |= SPI_CS_HIGH;
+	if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
+		mode |= SPI_PREAMBLE;
 	return spi_setup_slave(busnum, cs, max_hz, mode);
 }
 #endif
-- 
cgit v1.3.1


From f659b57361c4a351ef2a5fc23b9197428e2e67f0 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Mon, 14 Jul 2014 10:22:11 +0200
Subject: spi, spi_mxc: do not hang in spi_xchg_single

if status register do never set MXC_CSPICTRL_TC, spi_xchg_single
endless loops. Add a timeout here to prevent endless hang.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Dirk Behme <dirk.behme@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
 README                |  4 ++++
 drivers/spi/mxc_spi.c | 17 +++++++++++++++--
 2 files changed, 19 insertions(+), 2 deletions(-)

(limited to 'drivers')

diff --git a/README b/README
index f704eb37800..c52ffd97583 100644
--- a/README
+++ b/README
@@ -2597,6 +2597,10 @@ CBFS (Coreboot Filesystem) support
 		Enables the driver for the SPI controllers on i.MX and MXC
 		SoCs. Currently i.MX31/35/51 are supported.
 
+		CONFIG_SYS_SPI_MXC_WAIT
+		Timeout for waiting until spi transfer completed.
+		default: (CONFIG_SYS_HZ/100)     /* 10 ms */
+
 - FPGA Support: CONFIG_FPGA
 
 		Enables FPGA subsystem.
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index f3f029d634a..2d5f3850da8 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -30,6 +30,10 @@ static unsigned long spi_bases[] = {
 #define reg_read readl
 #define reg_write(a, v) writel(v, a)
 
+#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
+#define CONFIG_SYS_SPI_MXC_WAIT		(CONFIG_SYS_HZ/100)	/* 10 ms */
+#endif
+
 struct mxc_spi_slave {
 	struct spi_slave slave;
 	unsigned long	base;
@@ -212,6 +216,8 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
 	int nbytes = DIV_ROUND_UP(bitlen, 8);
 	u32 data, cnt, i;
 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
+	u32 ts;
+	int status;
 
 	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
 		__func__, bitlen, (u32)dout, (u32)din);
@@ -272,9 +278,16 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
 	reg_write(&regs->ctrl, mxcs->ctrl_reg |
 		MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
 
+	ts = get_timer(0);
+	status = reg_read(&regs->stat);
 	/* Wait until the TC (Transfer completed) bit is set */
-	while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)
-		;
+	while ((status & MXC_CSPICTRL_TC) == 0) {
+		if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
+			printf("spi_xchg_single: Timeout!\n");
+			return -1;
+		}
+		status = reg_read(&regs->stat);
+	}
 
 	/* Transfer completed, clear any pending request */
 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
-- 
cgit v1.3.1


From b21f87a3e02461c600f1c172b053f1530a532d90 Mon Sep 17 00:00:00 2001
From: Andy Fleming <afleming@gmail.com>
Date: Fri, 25 Jul 2014 17:39:08 -0500
Subject: Change Andy Fleming's email address

Messages to afleming@freescale.com now bounce, and should be
directed to my personal address at afleming@gmail.com

Signed-off-by: Andy Fleming <afleming@gmail.com>
---
 doc/feature-removal-schedule.txt | 2 +-
 doc/git-mailrc                   | 2 +-
 drivers/net/fm/memac_phy.c       | 2 +-
 drivers/net/fm/tgec_phy.c        | 2 +-
 include/phy.h                    | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'drivers')

diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt
index 16819c77544..4ed30df707e 100644
--- a/doc/feature-removal-schedule.txt
+++ b/doc/feature-removal-schedule.txt
@@ -26,7 +26,7 @@ Why:	We now have a PHY library, which allows everyone to share PHY
 	drivers. All new drivers should use this infrastructure, and
 	all old drivers should get converted to use it.
 
-Who:	Andy Fleming <afleming@freescale.com> and driver maintainers
+Who:	Andy Fleming <afleming@gmail.com> and driver maintainers
 
 ---------------------------
 
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 5b188551488..09857912935 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -12,7 +12,7 @@ alias u-boot uboot
 # things simple and easy to look up/coordinate.
 alias aaribaud       Albert Aribaud <albert.u.boot@aribaud.net>
 alias abiessmann     Andreas Bießmann <andreas.devel@googlemail.com>
-alias afleming       Andy Fleming <afleming@freescale.com>
+alias afleming       Andy Fleming <afleming@gmail.com>
 alias ag             Anatolij Gustschin <agust@denx.de>
 alias galak          Kumar Gala <galak@kernel.crashing.org>
 alias gruss          Graeme Russ <graeme.russ@gmail.com>
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index de9c0e9cd28..5f910c2cdd3 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -1,6 +1,6 @@
 /*
  * Copyright 2012 Freescale Semiconductor, Inc.
- *	Andy Fleming <afleming@freescale.com>
+ *	Andy Fleming <afleming@gmail.com>
  *	Roy Zang <tie-fei.zang@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c
index faec317a0a5..095f00cf976 100644
--- a/drivers/net/fm/tgec_phy.c
+++ b/drivers/net/fm/tgec_phy.c
@@ -1,6 +1,6 @@
 /*
  * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *	Andy Fleming <afleming@freescale.com>
+ *	Andy Fleming <afleming@gmail.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  * Some part is taken from tsec.c
diff --git a/include/phy.h b/include/phy.h
index d3ecd6378b3..2fcc328d5bc 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -1,6 +1,6 @@
 /*
  * Copyright 2011 Freescale Semiconductor, Inc.
- *	Andy Fleming <afleming@freescale.com>
+ *	Andy Fleming <afleming@gmail.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
-- 
cgit v1.3.1