From 4ef201e607ebed2432ee929446e3fb9b57c53a54 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 21 Apr 2026 09:54:38 +0200 Subject: drivers/core: use memdup() instead of malloc()+memcpy() Use memdup() instead of open-coding it. In the dm_setup_inst() case, there was never any reason to use calloc(), as the whole allocation is definitely initialized via the immediately following memcpy(). Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- drivers/core/acpi.c | 3 +-- drivers/core/ofnode.c | 3 +-- drivers/core/root.c | 3 +-- 3 files changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index 4763963914b..6a431171c8d 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -154,10 +154,9 @@ static int add_item(struct acpi_ctx *ctx, struct udevice *dev, if (!item->size) return 0; if (type != TYPE_OTHER) { - item->buf = malloc(item->size); + item->buf = memdup(start, item->size); if (!item->buf) return log_msg_ret("mem", -ENOMEM); - memcpy(item->buf, start, item->size); } item_count++; log_debug("* %s: Added type %d, %p, size %x\n", diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 3a36b6fdd03..12511f10aa9 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -1750,10 +1750,9 @@ int ofnode_write_prop(ofnode node, const char *propname, const void *value, void *newval; if (copy) { - newval = malloc(len); + newval = memdup(value, len); if (!newval) return log_ret(-ENOMEM); - memcpy(newval, value, len); value = newval; } ret = of_write_prop(ofnode_to_np(node), propname, len, value); diff --git a/drivers/core/root.c b/drivers/core/root.c index d43645f34dd..1f32f33b295 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -81,10 +81,9 @@ static int dm_setup_inst(void) /* Now allocate space for the priv/plat data, and copy it in */ size = __priv_data_end - __priv_data_start; - base = calloc(1, size); + base = memdup(__priv_data_start, size); if (!base) return log_msg_ret("priv", -ENOMEM); - memcpy(base, __priv_data_start, size); gd_set_dm_priv_base(base); } -- cgit v1.3.1 From 46606025225274b065490daf50bd58defb6b6659 Mon Sep 17 00:00:00 2001 From: Ronan Dalton Date: Tue, 5 May 2026 16:25:31 +1200 Subject: rtc: ds1307: Handle oscillator stop flag set on ds1339 chip Currently the oscillator stop flag (OSF) bit is never checked or cleared on the DS1339 RTC chip. On getting the time from the RTC, check if the OSF bit is set, log a warning, and clear the flag. This matches the behavior of the DS1337 chip. Note that the `date` command always reads from the RTC even when setting or resetting the date, so the OSF flag is cleared in those cases as well. Signed-off-by: Ronan Dalton Cc: Tom Rini Cc: Simon Glass Cc: Francesco Dolcini Cc: Mark Tomlinson Cc: Chris Packham Reviewed-by: Simon Glass --- drivers/rtc/ds1307.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 34d8f8c5276..4176ab3701e 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -116,9 +116,9 @@ static int ds1307_rtc_get(struct udevice *dev, struct rtc_time *tm) if (ret < 0) return ret; - if (type == ds_1337 || type == ds_1340) { - uint reg = (type == ds_1337) ? DS1337_STAT_REG_ADDR : - DS1340_STAT_REG_ADDR; + if (type == ds_1337 || type == ds_1339 || type == ds_1340) { + uint reg = (type == ds_1340) ? DS1340_STAT_REG_ADDR : + DS1337_STAT_REG_ADDR; int status = dm_i2c_reg_read(dev, reg); if (status >= 0 && (status & RTC_STAT_BIT_OSF)) { -- cgit v1.3.1 From 88338f9d147397c42bb996937b1ce31bca096626 Mon Sep 17 00:00:00 2001 From: Charles Perry Date: Thu, 7 May 2026 11:51:22 -0700 Subject: gpio: Correct dependencies for MCP230xx This driver depends on DM_I2C and DM_SPI, add it. Fixes: 3b639f643889 ("gpio: mcp230xx: Add support for models with SPI interface.") Signed-off-by: Charles Perry Reviewed-by: Quentin Schulz --- drivers/gpio/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 0b5466b39b8..5084af23269 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -309,9 +309,9 @@ config MAX77663_GPIO config MCP230XX_GPIO bool "MCP230XX GPIO driver" - depends on DM + depends on DM && DM_I2C && DM_SPI help - Support for Microchip's MCP230XX I2C connected GPIO devices. + Support for Microchip's MCP230XX I2C and SPI connected GPIO devices. The following chips are supported: - MCP23008 - MCP23017 -- cgit v1.3.1 From 731a875ae768a04282adf79a7144782ed12c04d6 Mon Sep 17 00:00:00 2001 From: Tanmay Kathpalia Date: Sat, 9 May 2026 23:29:32 +0530 Subject: mmc: sdhci: Start status timeout after command issue The status polling timeout in sdhci_send_command() should measure the time spent waiting for the command interrupt after the command has been issued. Do not initialize the timer at function entry, since the command inhibit wait and setup path can consume time before SDHCI_COMMAND is written. Start the timer immediately after issuing the command instead. Signed-off-by: Tanmay Kathpalia Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/mmc/sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 648dfa4b5ef..08594e10266 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -215,7 +215,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, u32 mask, flags, mode = 0; unsigned int time = 0; int mmc_dev = mmc_get_blk_desc(mmc)->devnum; - ulong start = get_timer(0); + ulong start; host->start_addr = 0; /* Timeout unit - ms */ -- cgit v1.3.1 From b487d05633a6614da425f9c3b7707e7d5fee97de Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:07:48 +0200 Subject: mmc: bootstd: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/mmc/mmc_bootdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/mmc_bootdev.c b/drivers/mmc/mmc_bootdev.c index 5a1688b75d0..b382521fdeb 100644 --- a/drivers/mmc/mmc_bootdev.c +++ b/drivers/mmc/mmc_bootdev.c @@ -19,7 +19,7 @@ static int mmc_bootdev_bind(struct udevice *dev) return 0; } -struct bootdev_ops mmc_bootdev_ops = { +static const struct bootdev_ops mmc_bootdev_ops = { }; static const struct udevice_id mmc_bootdev_ids[] = { -- cgit v1.3.1 From 993c405ed7ef097f60e4c58ba33379268861eb1e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:23:58 +0200 Subject: power: pmic: emul: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/pmic/i2c_pmic_emul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/pmic/i2c_pmic_emul.c b/drivers/power/pmic/i2c_pmic_emul.c index 6e81b9c3427..b5c8efd427a 100644 --- a/drivers/power/pmic/i2c_pmic_emul.c +++ b/drivers/power/pmic/i2c_pmic_emul.c @@ -146,7 +146,7 @@ static int sandbox_i2c_pmic_probe(struct udevice *emul) return 0; } -struct dm_i2c_ops sandbox_i2c_pmic_emul_ops = { +static const struct dm_i2c_ops sandbox_i2c_pmic_emul_ops = { .xfer = sandbox_i2c_pmic_xfer, }; -- cgit v1.3.1 From 3a4a8963aace2eb04610af6d944d002f146af55f Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Thu, 7 May 2026 20:48:36 -0300 Subject: mmc: cv1800b_sdhci: honor 'no-1-8-v' DT property CV1800B SDHCI controller does support 1.8V, however, boards like MilkV-Duo 256M do not have a VCCIO 1.8V regulator (the bus is wired for 3.3V only). These boards set 'no-1-8-v' in their device tree, and mmc_of_parse() does respect this property. Later, when sdhci_setup_cfg() is called, it reads SDHCI_CAPABILITIES_1 from the hardware and unconditionally adds the UHS caps again based on what the controller advertises. Since the board cannot switch to 1.8V, the host issues CMD11 (voltage switch request), the card transitions, but the bus stays at 3.3V. The SD card stops responding until the next power cycle. Before calling sdhci_setup_cfg(), set the SDHCI_QUIRK_NO_1_8_V quirk when 'no-1-8-v' is present. The quirk causes the SDR104/SDR50/DDR50 bits to be masked out of the caps, allowing the card to initialize properly. This matches the pattern used by zynq_sdhci. Fixes: eb36f28ff721 ("mmc: cv1800b: Add sdhci driver support for cv1800b SoC") Signed-off-by: Hiago De Franco Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/mmc/cv1800b_sdhci.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/cv1800b_sdhci.c b/drivers/mmc/cv1800b_sdhci.c index 036e798f374..72c5bfc6f35 100644 --- a/drivers/mmc/cv1800b_sdhci.c +++ b/drivers/mmc/cv1800b_sdhci.c @@ -94,6 +94,9 @@ static int cv1800b_sdhci_probe(struct udevice *dev) host->ops = &cv1800b_sdhci_sd_ops; host->max_clk = MMC_MAX_CLOCK; + if (dev_read_bool(dev, "no-1-8-v")) + host->quirks |= SDHCI_QUIRK_NO_1_8_V; + ret = mmc_of_parse(dev, &plat->cfg); if (ret) return ret; -- cgit v1.3.1 From 0e7a86e0cf818c781b2e476f0527e16ba7932770 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:01 +0200 Subject: power: domain: apple: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/apple-pmgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/power/domain/apple-pmgr.c b/drivers/power/domain/apple-pmgr.c index bf9940621ee..37fac815242 100644 --- a/drivers/power/domain/apple-pmgr.c +++ b/drivers/power/domain/apple-pmgr.c @@ -67,7 +67,7 @@ static int apple_reset_deassert(struct reset_ctl *reset_ctl) return 0; } -struct reset_ops apple_reset_ops = { +static const struct reset_ops apple_reset_ops = { .of_xlate = apple_reset_of_xlate, .rst_assert = apple_reset_assert, .rst_deassert = apple_reset_deassert, @@ -138,7 +138,7 @@ static int apple_pmgr_probe(struct udevice *dev) return 0; } -struct power_domain_ops apple_pmgr_ops = { +static const struct power_domain_ops apple_pmgr_ops = { .on = apple_pmgr_on, .of_xlate = apple_pmgr_of_xlate, }; -- cgit v1.3.1 From e6c69731c988238e4f55d046b9c500dce8f89698 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:02 +0200 Subject: power: domain: bcm6328: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/bcm6328-power-domain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/bcm6328-power-domain.c b/drivers/power/domain/bcm6328-power-domain.c index 36b5a933748..5b449f4c29d 100644 --- a/drivers/power/domain/bcm6328-power-domain.c +++ b/drivers/power/domain/bcm6328-power-domain.c @@ -57,7 +57,7 @@ static const struct udevice_id bcm6328_power_domain_ids[] = { { /* sentinel */ } }; -struct power_domain_ops bcm6328_power_domain_ops = { +static const struct power_domain_ops bcm6328_power_domain_ops = { .off = bcm6328_power_domain_off, .on = bcm6328_power_domain_on, .request = bcm6328_power_domain_request, -- cgit v1.3.1 From 2e8078e5d545cb09933e95f692a57a70fcc6091c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:03 +0200 Subject: power: domain: imx8-legacy: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/imx8-power-domain-legacy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c index 713a51d7807..a646f667039 100644 --- a/drivers/power/domain/imx8-power-domain-legacy.c +++ b/drivers/power/domain/imx8-power-domain-legacy.c @@ -347,7 +347,7 @@ static const struct udevice_id imx8_power_domain_ids[] = { { } }; -struct power_domain_ops imx8_power_domain_ops = { +static const struct power_domain_ops imx8_power_domain_ops = { .on = imx8_power_domain_on, .off = imx8_power_domain_off, .of_xlate = imx8_power_domain_of_xlate, -- cgit v1.3.1 From 77a8a30ef8b64b239afa3e4c04e606c51cfc56e9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:04 +0200 Subject: power: domain: imx8: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/imx8-power-domain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/imx8-power-domain.c b/drivers/power/domain/imx8-power-domain.c index e8dcc057fee..5740cd686db 100644 --- a/drivers/power/domain/imx8-power-domain.c +++ b/drivers/power/domain/imx8-power-domain.c @@ -51,7 +51,7 @@ static const struct udevice_id imx8_power_domain_ids[] = { { } }; -struct power_domain_ops imx8_power_domain_ops_v2 = { +static const struct power_domain_ops imx8_power_domain_ops_v2 = { .on = imx8_power_domain_on, .off = imx8_power_domain_off, }; -- cgit v1.3.1 From 10c5b89e217e114f6dc57933ddbb269e4b708eed Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:05 +0200 Subject: power: domain: imx8m: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/imx8m-power-domain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index 1c731b897cc..5fdb95fb6a7 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -558,7 +558,7 @@ static const struct udevice_id imx8m_power_domain_ids[] = { { } }; -struct power_domain_ops imx8m_power_domain_ops = { +static const struct power_domain_ops imx8m_power_domain_ops = { .on = imx8m_power_domain_on, .off = imx8m_power_domain_off, .of_xlate = imx8m_power_domain_of_xlate, -- cgit v1.3.1 From f82c349b9159738aba5193943cfbbe53eac8d050 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:06 +0200 Subject: power: domain: imx8mp-mediamix: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/imx8mp-mediamix.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/imx8mp-mediamix.c b/drivers/power/domain/imx8mp-mediamix.c index 504c22f7d36..66ea5d8e60c 100644 --- a/drivers/power/domain/imx8mp-mediamix.c +++ b/drivers/power/domain/imx8mp-mediamix.c @@ -194,7 +194,7 @@ static const struct udevice_id imx8mp_mediamix_ids[] = { { } }; -struct power_domain_ops imx8mp_mediamix_ops = { +static const struct power_domain_ops imx8mp_mediamix_ops = { .on = imx8mp_mediamix_on, .off = imx8mp_mediamix_off, .of_xlate = imx8mp_mediamix_of_xlate, -- cgit v1.3.1 From ad9ca3e7766310b20dde93826b05b42b4f0ab43f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:07 +0200 Subject: power: domain: meson-ee-pwrc: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/meson-ee-pwrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/meson-ee-pwrc.c b/drivers/power/domain/meson-ee-pwrc.c index 4d9f3bba644..6361f3a6c59 100644 --- a/drivers/power/domain/meson-ee-pwrc.c +++ b/drivers/power/domain/meson-ee-pwrc.c @@ -386,7 +386,7 @@ static int meson_ee_pwrc_of_xlate(struct power_domain *power_domain, return 0; } -struct power_domain_ops meson_ee_pwrc_ops = { +static const struct power_domain_ops meson_ee_pwrc_ops = { .off = meson_ee_pwrc_off, .on = meson_ee_pwrc_on, .of_xlate = meson_ee_pwrc_of_xlate, -- cgit v1.3.1 From 4f87439ed46ef860cf886875d0c23fdaa60d7b43 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:08 +0200 Subject: power: domain: meson-gx-pwrc: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/meson-gx-pwrc-vpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/meson-gx-pwrc-vpu.c b/drivers/power/domain/meson-gx-pwrc-vpu.c index 1c56e8508c3..325296b0dd7 100644 --- a/drivers/power/domain/meson-gx-pwrc-vpu.c +++ b/drivers/power/domain/meson-gx-pwrc-vpu.c @@ -262,7 +262,7 @@ static int meson_pwrc_vpu_of_xlate(struct power_domain *power_domain, return 0; } -struct power_domain_ops meson_gx_pwrc_vpu_ops = { +static const struct power_domain_ops meson_gx_pwrc_vpu_ops = { .off = meson_pwrc_vpu_off, .on = meson_pwrc_vpu_on, .of_xlate = meson_pwrc_vpu_of_xlate, -- cgit v1.3.1 From 2e59c9fa4ff0011a4f3584f0781ae3f4c80cf801 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:09 +0200 Subject: power: domain: meson-secure-pwrc: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/meson-secure-pwrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/meson-secure-pwrc.c b/drivers/power/domain/meson-secure-pwrc.c index f70f8e02423..1b82b58f3e5 100644 --- a/drivers/power/domain/meson-secure-pwrc.c +++ b/drivers/power/domain/meson-secure-pwrc.c @@ -120,7 +120,7 @@ static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = { SEC_PD(RSA), }; -struct power_domain_ops meson_secure_pwrc_ops = { +static const struct power_domain_ops meson_secure_pwrc_ops = { .on = meson_secure_pwrc_on, .off = meson_secure_pwrc_off, .of_xlate = meson_secure_pwrc_of_xlate, -- cgit v1.3.1 From b51735a38a17cf9be3ac8629a5ed22b2820d0339 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:10 +0200 Subject: power: domain: mtk: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: David Lechner Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/mtk-power-domain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c index 2d1ba1855a5..24dd540897d 100644 --- a/drivers/power/domain/mtk-power-domain.c +++ b/drivers/power/domain/mtk-power-domain.c @@ -392,7 +392,7 @@ static const struct udevice_id mtk_power_domain_ids[] = { { /* sentinel */ } }; -struct power_domain_ops mtk_power_domain_ops = { +static const struct power_domain_ops mtk_power_domain_ops = { .off = scpsys_power_off, .on = scpsys_power_on, .request = scpsys_power_request, -- cgit v1.3.1 From d82d49e1a6d10d7e92dd8448429f2c2e2c8af2c4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:11 +0200 Subject: power: domain: sandbox: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/sandbox-power-domain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/sandbox-power-domain.c b/drivers/power/domain/sandbox-power-domain.c index a8031657638..a30826a3b4d 100644 --- a/drivers/power/domain/sandbox-power-domain.c +++ b/drivers/power/domain/sandbox-power-domain.c @@ -78,7 +78,7 @@ static const struct udevice_id sandbox_power_domain_ids[] = { { } }; -struct power_domain_ops sandbox_power_domain_ops = { +static const struct power_domain_ops sandbox_power_domain_ops = { .request = sandbox_power_domain_request, .rfree = sandbox_power_domain_free, .on = sandbox_power_domain_on, -- cgit v1.3.1 From 1aea809ba2da6ad3af16d50166d94b7b376e017c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:12 +0200 Subject: power: domain: scmi: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/scmi-power-domain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/scmi-power-domain.c b/drivers/power/domain/scmi-power-domain.c index e8c0ba8878e..6dcc259ad8f 100644 --- a/drivers/power/domain/scmi-power-domain.c +++ b/drivers/power/domain/scmi-power-domain.c @@ -179,7 +179,7 @@ static int scmi_power_domain_probe(struct udevice *dev) return 0; } -struct power_domain_ops scmi_power_domain_ops = { +static const struct power_domain_ops scmi_power_domain_ops = { .on = scmi_power_domain_on, .off = scmi_power_domain_off, }; -- cgit v1.3.1 From f89d17c360836c0b47f3bf21dec8bc79dbc4f854 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:13 +0200 Subject: power: domain: tegra186: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/tegra186-power-domain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/tegra186-power-domain.c b/drivers/power/domain/tegra186-power-domain.c index 334c460c805..3865cd4cf47 100644 --- a/drivers/power/domain/tegra186-power-domain.c +++ b/drivers/power/domain/tegra186-power-domain.c @@ -55,7 +55,7 @@ static int tegra186_power_domain_off(struct power_domain *power_domain) return tegra186_power_domain_common(power_domain, false); } -struct power_domain_ops tegra186_power_domain_ops = { +static const struct power_domain_ops tegra186_power_domain_ops = { .on = tegra186_power_domain_on, .off = tegra186_power_domain_off, }; -- cgit v1.3.1 From 77fa442ff51551dfb1bf558b6bf4a8ea2b2ff200 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:22:14 +0200 Subject: power: domain: zynqmp: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Michal Simek Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/zynqmp-power-domain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/domain/zynqmp-power-domain.c b/drivers/power/domain/zynqmp-power-domain.c index a54de5c1439..0acfc54e787 100644 --- a/drivers/power/domain/zynqmp-power-domain.c +++ b/drivers/power/domain/zynqmp-power-domain.c @@ -57,7 +57,7 @@ static int zynqmp_power_domain_off(struct power_domain *power_domain) return 0; } -struct power_domain_ops zynqmp_power_domain_ops = { +static const struct power_domain_ops zynqmp_power_domain_ops = { .request = zynqmp_power_domain_request, .rfree = zynqmp_power_domain_free, .on = zynqmp_power_domain_on, -- cgit v1.3.1 From 39f52b7c29e64233dae21c5aebd559b946665c77 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 28 Apr 2026 16:37:33 +0800 Subject: net: phy: nxp-c45-tja11xx: Fix incorrect usage of devm_kzalloc devm_kzalloc needs to pass udevice for first parameter, this phy driver wrongly pass the priv in phy_device. And because the dev in phy_device is only valid after phy_connect, in probe phase this dev is NULL, so we can't use devm_kzalloc, replace it with kzalloc. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- drivers/net/phy/nxp-c45-tja11xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index a1e4c3d053b..9814ac498ed 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -343,7 +343,7 @@ static int nxp_c45_probe(struct phy_device *phydev) { struct nxp_c45_phy *priv; - priv = devm_kzalloc(phydev->priv, sizeof(*priv), GFP_KERNEL); + priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; -- cgit v1.3.1 From 6bc840568f48c2f3f562a8cb8dd6c5feddf9130c Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 28 Apr 2026 16:53:12 +0800 Subject: i2c: imx_lpi2c: Fix MSR status check issue in STOP In bus_i2c_stop, the MSR SDF is checked in a loop after stop command is sent. Meanwhile, some error status in MSR is also checked by imx_lpci2c_check_clear_error. But the imx_lpci2c_check_clear_error will clear the MSR. It causes problem in below situation: In current loop, SDF does not set, but error status is found by imx_lpci2c_check_clear_error (for example, NDF), then NDF will be cleared and result has NDF error. However, because SDF does not set in this loop, it goes not next loop. When SDF is set in next loop, imx_lpci2c_check_clear_error is re-executed, but as the MSR is cleared, the result is 0. Then the stop return 0. But it should return NDF error. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- drivers/i2c/imx_lpi2c.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index a309fd6f07c..e2b4fd334ec 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -239,7 +239,6 @@ static int bus_i2c_stop(struct udevice *bus) start_time = get_timer(0); while (1) { status = readl(®s->msr); - result = imx_lpci2c_check_clear_error(regs); /* stop detect flag */ if (status & LPI2C_MSR_SDF_MASK) { /* clear stop flag */ @@ -250,10 +249,13 @@ static int bus_i2c_stop(struct udevice *bus) if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) { debug("stop timeout\n"); + result = imx_lpci2c_check_clear_error(regs); return -ETIMEDOUT; } } + result = imx_lpci2c_check_clear_error(regs); + return result; } -- cgit v1.3.1 From c9a8f673e0b8dc30bd575faae34e0b1f1e42a706 Mon Sep 17 00:00:00 2001 From: Simona Toaca Date: Thu, 30 Apr 2026 11:33:30 +0300 Subject: imx9: Add support for saving DDR training data to NVM DDR training data can be saved to NVM and be available to OEI at boot time, which will trigger QuickBoot flow. U-Boot only checks for data integrity (CRC32), while OEI is in charge of authentication when it tries to load the data from NVM. On iMX95 A0/A1, 'authentication' is done via another CRC32. On the other SoCs, authentication is done by using ELE to check the MAC stored in the ddrphy_qb_state structure. Supported platforms: iMX94, iMX95, iMX952 (using OEI) Supported storage types: eMMC, SD, SPI flash. Signed-off-by: Viorel Suman Signed-off-by: Ye Li Signed-off-by: Simona Toaca --- arch/arm/include/asm/arch-imx9/ddr.h | 48 ++++- arch/arm/include/asm/mach-imx/qb.h | 15 ++ arch/arm/mach-imx/Kconfig | 9 + arch/arm/mach-imx/imx9/Makefile | 6 +- arch/arm/mach-imx/imx9/qb.c | 403 +++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/imx9/scmi/soc.c | 7 + drivers/ddr/imx/imx9/Kconfig | 7 + 7 files changed, 492 insertions(+), 3 deletions(-) create mode 100644 arch/arm/include/asm/mach-imx/qb.h create mode 100644 arch/arm/mach-imx/imx9/qb.c (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h index a8e3f7354c7..bba12369f06 100644 --- a/arch/arm/include/asm/arch-imx9/ddr.h +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2022 NXP + * Copyright 2022-2026 NXP */ #ifndef __ASM_ARCH_IMX8M_DDR_H @@ -100,6 +100,52 @@ struct dram_timing_info { extern struct dram_timing_info dram_timing; +/* Quick Boot related */ +#define DDRPHY_QB_CSR_SIZE 5168 +#define DDRPHY_QB_ACSM_SIZE (4 * 1024) +#define DDRPHY_QB_MSB_SIZE 0x200 +#define DDRPHY_QB_PSTATES 0 +#define DDRPHY_QB_PST_SIZE (DDRPHY_QB_PSTATES * 4 * 1024) + +/** + * This structure needs to be aligned with the one in OEI. + */ +struct ddrphy_qb_state { + u32 crc; /* Used for ensuring integrity in DRAM */ +#define MAC_LENGTH 8 /* 256 bits, 32-bit aligned */ + u32 mac[MAC_LENGTH]; /* For 95A0/1 use mac[0] to keep CRC32 value */ + u8 trained_vrefca_a0; + u8 trained_vrefca_a1; + u8 trained_vrefca_b0; + u8 trained_vrefca_b1; + u8 trained_vrefdq_a0; + u8 trained_vrefdq_a1; + u8 trained_vrefdq_b0; + u8 trained_vrefdq_b1; + u8 trained_vrefdqu_a0; + u8 trained_vrefdqu_a1; + u8 trained_vrefdqu_b0; + u8 trained_vrefdqu_b1; + u8 trained_dramdfe_a0; + u8 trained_dramdfe_a1; + u8 trained_dramdfe_b0; + u8 trained_dramdfe_b1; + u8 trained_dramdca_a0; + u8 trained_dramdca_a1; + u8 trained_dramdca_b0; + u8 trained_dramdca_b1; + u16 qb_pll_upll_prog0; + u16 qb_pll_upll_prog1; + u16 qb_pll_upll_prog2; + u16 qb_pll_upll_prog3; + u16 qb_pll_ctrl1; + u16 qb_pll_ctrl4; + u16 qb_pll_ctrl5; + u16 csr[DDRPHY_QB_CSR_SIZE]; + u16 acsm[DDRPHY_QB_ACSM_SIZE]; + u16 pst[DDRPHY_QB_PST_SIZE]; +}; + void ddr_load_train_firmware(enum fw_type type); int ddr_init(struct dram_timing_info *timing_info); int ddr_cfg_phy(struct dram_timing_info *timing_info); diff --git a/arch/arm/include/asm/mach-imx/qb.h b/arch/arm/include/asm/mach-imx/qb.h new file mode 100644 index 00000000000..a874c9c5e36 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/qb.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2026 NXP + */ + +#ifndef __IMX_QB_H__ +#define __IMX_QB_H__ + +#include + +bool imx_qb_check(void); +int imx_qb(const char *ifname, const char *dev, bool save); +void spl_imx_qb_save(void); + +#endif diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 259f4a4ce99..bb62a0cf2f6 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -71,6 +71,15 @@ config CSF_SIZE Define the maximum size for Command Sequence File (CSF) binary this information is used to define the image boot data. +config IMX_QB + bool "Support Quickboot flow for Synopsis DDR PHY on iMX platforms" + default y + depends on IMX94 || IMX95 || IMX952 + help + Enable the logic for saving DDR training data from volatile + memory to non-volatile storage. OEI uses the saved data to + run Quickboot flow and skip re-training the DDR PHY. + config CMD_BMODE bool "Support the 'bmode' command" default y diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile index 53cc97c6b47..80b697396ea 100644 --- a/arch/arm/mach-imx/imx9/Makefile +++ b/arch/arm/mach-imx/imx9/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright 2022 NXP +# Copyright 2022,2026 NXP obj-y += lowlevel_init.o @@ -12,4 +12,6 @@ endif ifneq ($(CONFIG_SPL_BUILD),y) obj-y += imx_bootaux.o -endif \ No newline at end of file +endif + +obj-$(CONFIG_$(PHASE_)IMX_QB) += qb.o diff --git a/arch/arm/mach-imx/imx9/qb.c b/arch/arm/mach-imx/imx9/qb.c new file mode 100644 index 00000000000..1a0a12de3d4 --- /dev/null +++ b/arch/arm/mach-imx/imx9/qb.c @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * Copyright 2024-2026 NXP + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define QB_STATE_LOAD_SIZE SZ_64K + +#define BLK_DEV 0 +#define SPI_DEV 1 + +#define IMG_FLAGS_IMG_TYPE_MASK 0xF +#define IMG_FLAGS_IMG_TYPE(x) FIELD_GET(IMG_FLAGS_IMG_TYPE_MASK, (x)) + +#define IMG_TYPE_DDR_TDATA_DUMMY 0xD /* dummy DDR training data image */ + +static const struct { + const char *ifname; + const char *dev; +} imx_boot_devs[] = { + [BOOT_DEVICE_MMC1] = { "mmc", "0" }, + [BOOT_DEVICE_MMC2] = { "mmc", "1" }, + [BOOT_DEVICE_SPI] = { "spi", "" }, +}; + +static int imx_qb_get_board_boot_device(void) +{ + switch (get_boot_device()) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_NONE; + } +} + +static int imx_qb_get_boot_dev_str(const char **ifname, const char **dev) +{ + int boot_dev; + + if (IS_ENABLED(CONFIG_XPL_BUILD)) + boot_dev = spl_boot_device(); + else + boot_dev = imx_qb_get_board_boot_device(); + + if (boot_dev == BOOT_DEVICE_NONE || boot_dev == BOOT_DEVICE_BOARD) + return -EINVAL; + + *ifname = imx_boot_devs[boot_dev].ifname; + *dev = imx_boot_devs[boot_dev].dev; + + return 0; +} + +bool imx_qb_check(void) +{ + struct ddrphy_qb_state *qb_state; + u32 size, crc; + + /** + * Ensure CRC is not empty, the reason is that + * the data is invalidated after first save run + * or after it is overwritten. + */ + qb_state = (struct ddrphy_qb_state *)CONFIG_QB_SAVED_STATE_BASE; + size = sizeof(struct ddrphy_qb_state) - sizeof(qb_state->crc); + crc = crc32(0, (u8 *)qb_state->mac, size); + + if (!qb_state->crc || crc != qb_state->crc) + return false; + + return true; +} + +static int imx_qb_get_blk_boot_part(const char * const ifname, + const char * const dev, + struct blk_desc **bdesc) +{ + struct udevice *udev; + struct disk_partition info; + struct mmc *mmc; + int part; + int ret; + + if (!IS_ENABLED(CONFIG_XPL_BUILD)) + return blk_get_device_part_str(ifname, dev, bdesc, &info, 1); + + /** + * SPL does not have access to part_get_info, + * so get the partition manually. Currently only + * supporting MMC devices. + */ + ret = blk_get_device_by_str(ifname, dev, bdesc); + + if (ret < 0) + return -ENODEV; + + if ((*bdesc)->uclass_id != UCLASS_MMC) + return -EOPNOTSUPP; + + udev = dev_get_parent((*bdesc)->bdev); + mmc = mmc_get_mmc_dev(udev); + + if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) + return 0; + + part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + + if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) + return part; + + return 0; +} + +static ulong imx_qb_get_boot_device_offset(void *dev, int dev_type) +{ + struct blk_desc *bdesc; + + switch (dev_type) { + case BLK_DEV: + bdesc = dev; + + /* eMMC boot partition */ + if (bdesc->hwpart) + return CONTAINER_HDR_EMMC_OFFSET; + + return CONTAINER_HDR_MMCSD_OFFSET; + case SPI_DEV: + return CONTAINER_HDR_QSPI_OFFSET; + default: + return -EOPNOTSUPP; + } +} + +static int imx_qb_parse_container(void *addr, u64 *qb_data_off) +{ + struct container_hdr *phdr; + struct boot_img_t *img_entry; + u32 img_type, img_end; + int i; + + phdr = addr; + if (phdr->tag != 0x87 || (phdr->version != 0x0 && phdr->version != 0x2)) + return -EINVAL; + + img_entry = addr + sizeof(struct container_hdr); + for (i = 0; i < phdr->num_images; i++) { + img_type = IMG_FLAGS_IMG_TYPE(img_entry->hab_flags); + if (img_type == IMG_TYPE_DDR_TDATA_DUMMY && img_entry->size == 0) { + /* Image entry pointing to DDR Training Data */ + *qb_data_off = img_entry->offset; + return 0; + } + + img_end = img_entry->offset + img_entry->size; + if (i + 1 < phdr->num_images) { + img_entry++; + if (img_end + QB_STATE_LOAD_SIZE == img_entry->offset) { + /* hole detected */ + *qb_data_off = img_end; + return 0; + } + } + } + + return -EINVAL; +} + +static int imx_qb_get_dev_qbdata_offset(void *dev, int dev_type, ulong offset, + u64 *qbdata_offset) +{ + struct blk_desc *bdesc; + u8 *buf; + ulong count; + int ret; + + buf = malloc(CONTAINER_HDR_ALIGNMENT); + if (!buf) + return -ENOMEM; + + switch (dev_type) { + case BLK_DEV: + bdesc = dev; + + count = blk_dread(bdesc, + offset / bdesc->blksz, + CONTAINER_HDR_ALIGNMENT / bdesc->blksz, + buf); + if (count == 0) { + printf("Read container image from MMC/SD failed\n"); + ret = -EIO; + goto imx_qb_get_dev_qbdata_offset_exit; + } + break; + case SPI_DEV: + if (!CONFIG_IS_ENABLED(SPI)) { + ret = -EOPNOTSUPP; + goto imx_qb_get_dev_qbdata_offset_exit; + } + + ret = spi_flash_read_dm(dev, offset, + CONTAINER_HDR_ALIGNMENT, buf); + if (ret) { + printf("Read container header from SPI failed\n"); + ret = -EIO; + goto imx_qb_get_dev_qbdata_offset_exit; + } + break; + default: + printf("Support for device %d not enabled\n", dev_type); + ret = -EOPNOTSUPP; + goto imx_qb_get_dev_qbdata_offset_exit; + } + + ret = imx_qb_parse_container(buf, qbdata_offset); + +imx_qb_get_dev_qbdata_offset_exit: + free(buf); + + return ret; +} + +static int imx_qb_get_qbdata_offset(void *dev, int dev_type, + u64 *qbdata_offset) +{ + u64 cont_offset; + int ret, i; + + cont_offset = imx_qb_get_boot_device_offset(dev, dev_type); + + for (i = 0; i < 3; i++) { + ret = imx_qb_get_dev_qbdata_offset(dev, dev_type, cont_offset, + qbdata_offset); + if (ret == 0) { + (*qbdata_offset) += cont_offset; + break; + } + + cont_offset += CONTAINER_HDR_ALIGNMENT; + } + + return ret; +} + +static int imx_qb_blk(const char * const ifname, + const char * const dev, bool save) +{ + struct blk_desc *bdesc; + u64 offset; + u64 load_size; + int part, orig_part; + int ret; + + part = imx_qb_get_blk_boot_part(ifname, dev, &bdesc); + + if (part < 0) { + printf("Failed to find %s %s\n", ifname, dev); + return -ENODEV; + } + + orig_part = bdesc->hwpart; + + ret = blk_dselect_hwpart(bdesc, part); + if (ret && ret != -EMEDIUMTYPE) { + printf("Failed to select hwpart, ret %d\n", ret); + return ret; + } + + ret = imx_qb_get_qbdata_offset(bdesc, BLK_DEV, &offset); + if (ret) { + printf("get_qbdata_offset failed, ret = %d\n", ret); + return ret; + } + + offset /= bdesc->blksz; + load_size = QB_STATE_LOAD_SIZE / bdesc->blksz; + + if (save) { + /* QB data is stored in DDR -> can use it as buf */ + ret = blk_dwrite(bdesc, offset, load_size, + (const void *)CONFIG_QB_SAVED_STATE_BASE); + } else { + /* erase */ + ret = blk_derase(bdesc, offset, load_size); + } + + if (!ret) { + printf("Failed to write to block device\n"); + return -EIO; + } + + /* Return to original partition */ + ret = blk_dselect_hwpart(bdesc, orig_part); + if (ret && ret != -EMEDIUMTYPE) { + printf("Failed to select hwpart, ret %d\n", ret); + return ret; + } + + return 0; +} + +static int imx_qb_spi(bool save) +{ + struct udevice *flash; + u64 offset; + int ret; + + if (!CONFIG_IS_ENABLED(SPI)) { + printf("SPI not enabled\n"); + return -EOPNOTSUPP; + } + + ret = uclass_first_device_err(UCLASS_SPI_FLASH, &flash); + if (ret) { + printf("SPI flash not found.\n"); + return -ENODEV; + } + + ret = imx_qb_get_qbdata_offset(flash, SPI_DEV, &offset); + if (ret) { + printf("get_qbdata_offset failed, ret = %d\n", ret); + return ret; + } + + ret = spi_flash_erase_dm(flash, offset, QB_STATE_LOAD_SIZE); + + if (ret) + return ret; + + if (!save) + return 0; + + /* QB data is stored in DDR -> can use it as buf */ + ret = spi_flash_write_dm(flash, offset, + QB_STATE_LOAD_SIZE, + (const void *)CONFIG_QB_SAVED_STATE_BASE); + + return ret; +} + +int imx_qb(const char *ifname, const char *dev, bool save) +{ + int ret; + + ret = 0; + + /* Try to use boot device */ + if (!strcmp(ifname, "auto")) + ret = imx_qb_get_boot_dev_str(&ifname, &dev); + + if (ret) + return ret; + + if (save && !imx_qb_check()) + return -EINVAL; + + if (!strcmp(ifname, "spi")) + ret = imx_qb_spi(save); + else + ret = imx_qb_blk(ifname, dev, save); + + if (ret) + return ret; + + if (!save) + return 0; + + /** + * invalidate qb_state mem so that at next boot + * the check function will fail and save won't happen + */ + memset((void *)CONFIG_QB_SAVED_STATE_BASE, 0, + sizeof(struct ddrphy_qb_state)); + + return 0; +} + +void spl_imx_qb_save(void) +{ + /* Save QB data on current boot device */ + if (imx_qb("auto", "", true)) + printf("QB save failed\n"); +} diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 60fdd577f55..7c107c88bb4 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -310,6 +310,13 @@ static struct mm_region imx9_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* QB data */ + .virt = CONFIG_QB_SAVED_STATE_BASE, + .phys = CONFIG_QB_SAVED_STATE_BASE, + .size = 0x200000UL, /* 2M */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE }, { /* empty entry to split table entry 5 if needed when TEEs are used */ 0, diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig index b953bca4f06..7b3dbf53dff 100644 --- a/drivers/ddr/imx/imx9/Kconfig +++ b/drivers/ddr/imx/imx9/Kconfig @@ -29,4 +29,11 @@ config SAVED_DRAM_TIMING_BASE after DRAM is trained, need to save the dram related timming info into memory for low power use. +config QB_SAVED_STATE_BASE + hex "Define the base address for saved QuickBoot state" + default 0x8fe00000 + help + Once DRAM is trained, the resulted training info is + saved into memory in order to be reachable from U-Boot. + endmenu -- cgit v1.3.1 From 1b0c1407d8fac31bfe6a4244218352a68d313ef8 Mon Sep 17 00:00:00 2001 From: Francois Berder Date: Fri, 8 May 2026 22:11:35 +0200 Subject: power: regulator: pfuze100: Fix unchecked pmic_reg_read, return value pmic_reg_read returns a negative value if an error occurs. This commit adds a missing check after calling pmic_reg_read. Signed-off-by: Francois Berder Reviewed-by: Peng Fan --- drivers/power/regulator/pfuze100.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c index 77c82a00b65..57af16cfbb9 100644 --- a/drivers/power/regulator/pfuze100.c +++ b/drivers/power/regulator/pfuze100.c @@ -550,6 +550,8 @@ static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV) return -EINVAL; } val = pmic_reg_read(dev->parent, desc->vsel_reg); + if (val < 0) + return val; if (desc->high_volt_mask && (val & desc->high_volt_mask)) { min_uV = desc->high_volt_desc->min_uV; uV_step = desc->high_volt_desc->uV_step; -- cgit v1.3.1 From 11af22cd1e201882a7e5fa4a346f04b449f463d1 Mon Sep 17 00:00:00 2001 From: Clark Wang Date: Tue, 12 May 2026 11:26:30 +0800 Subject: net: fsl_enetc: fix the duplex setting on the iMX platform The iMX and LS platforms use different bits in the same register to set duplex, but their logics are opposite. The current settings will result in unexpected configurations in RGMII mode. Fixes: e6df2f5e22c6 ("net: fsl_enetc: Update enetc driver to support i.MX95") Signed-off-by: Clark Wang Signed-off-by: Alice Guo Reviewed-by: Tim Harvey --- drivers/net/fsl_enetc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 206f1a381bb..b07193e4e83 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -396,7 +397,7 @@ static int enetc_init_sgmii(struct udevice *dev) /* set up MAC for RGMII */ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) { - u32 old_val, val, dpx = 0; + u32 old_val, val = 0; old_val = val = enetc_read_mac_port(dev, ENETC_PM_IF_MODE); @@ -416,15 +417,14 @@ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) val |= ENETC_PM_IFM_SSP_10; } - if (enetc_is_imx95(dev)) - dpx = ENETC_PM_IFM_FULL_DPX_IMX; + if (enetc_is_imx95(dev)) + val = u32_replace_bits(val, + phydev->duplex == DUPLEX_FULL ? 0 : 1, + ENETC_PM_IFM_FULL_DPX_IMX); else if (enetc_is_ls1028a(dev)) - dpx = ENETC_PM_IFM_FULL_DPX_LS; - - if (phydev->duplex == DUPLEX_FULL) - val |= dpx; - else - val &= ~dpx; + val = u32_replace_bits(val, + phydev->duplex == DUPLEX_FULL ? 1 : 0, + ENETC_PM_IFM_FULL_DPX_LS); if (val == old_val) return; -- cgit v1.3.1 From 9e46861a01dd0a011616bf219f393303580dcd8b Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 12 May 2026 11:49:46 +0800 Subject: net: fsl_enetc: Add support for i.MX952 Extend ENETC driver to support i.MX952 platform where 2 ENETC controllers are located on different PCIe buses. Key changes: - Add enetc_dev_id_imx() to derive device ID from device tree "reg" property for i.MX952, mapping bus_devfn values 0x0 and 0x100 to device IDs 0 and 1 respectively - Implement imx952_netcmix_init() to configure MII protocol and PCS settings based on PHY mode parsed from device tree - Add i.MX952 to FSL_ENETC_NETC_BLK_CTRL Kconfig dependencies Signed-off-by: Ye Li Signed-off-by: Alice Guo Reviewed-by: Peng Fan --- drivers/net/Kconfig | 4 +- drivers/net/fsl_enetc.c | 28 +++++++++++++- drivers/net/fsl_enetc_netc_blk_ctrl.c | 72 +++++++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 666618681df..f2e838b84de 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1018,8 +1018,8 @@ config FSL_ENETC config FSL_ENETC_NETC_BLK_CTRL bool "NXP ENETC NETC blocks control driver" depends on FSL_ENETC - depends on IMX95 || IMX94 - default y if IMX95 || IMX94 + depends on IMX95 || IMX94 || IMX952 + default y if IMX95 || IMX94 || IMX952 help This driver configures Integrated Endpoint Register Block (IERB) and Privileged Register Block (PRB) of NETC. For i.MX platforms, it also diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index b07193e4e83..f393af40e27 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -75,10 +75,36 @@ static int enetc_is_ls1028a(struct udevice *dev) pplat->vendor == PCI_VENDOR_ID_FREESCALE; } +static int enetc_dev_id_imx(struct udevice *dev) +{ + if (IS_ENABLED(CONFIG_IMX952)) { + int bus_devfn; + u32 reg[5]; + int error; + + error = dev_read_u32_array(dev, "reg", reg, ARRAY_SIZE(reg)); + if (error) + return error; + + bus_devfn = (reg[0] >> 8) & 0xffff; + + switch (bus_devfn) { + case 0: + return 0; + case 0x100: + return 1; + default: + return -EINVAL; + } + } + + return PCI_DEV(pci_get_devfn(dev)) >> 3; +} + static int enetc_dev_id(struct udevice *dev) { if (enetc_is_imx95(dev)) - return PCI_DEV(pci_get_devfn(dev)) >> 3; + return enetc_dev_id_imx(dev); if (enetc_is_ls1028a(dev)) return PCI_FUNC(pci_get_devfn(dev)); diff --git a/drivers/net/fsl_enetc_netc_blk_ctrl.c b/drivers/net/fsl_enetc_netc_blk_ctrl.c index 8577bb75632..0c87d80ea5c 100644 --- a/drivers/net/fsl_enetc_netc_blk_ctrl.c +++ b/drivers/net/fsl_enetc_netc_blk_ctrl.c @@ -35,6 +35,7 @@ #define MII_PROT_RGMII 0x2 #define MII_PROT_SERIAL 0x3 #define MII_PROT(port, prot) (((prot) & 0xf) << ((port) << 2)) +#define MII_PROT_GET(reg, port) (((reg) >> ((port) << 2)) & 0xf) #define IMX95_CFG_LINK_PCS_PROT(a) (0x8 + (a) * 4) #define PCS_PROT_1G_SGMII BIT(0) @@ -97,6 +98,9 @@ #define IMX94_TIMER1_ID 1 #define IMX94_TIMER2_ID 2 +#define IMX952_ENETC0_BUS_DEVFN 0x0 +#define IMX952_ENETC1_BUS_DEVFN 0x100 + /* Flags for different platforms */ #define NETC_HAS_NETCMIX BIT(0) @@ -567,6 +571,69 @@ static int netc_prb_check_error(struct netc_blk_ctrl *priv) return 0; } +static int imx952_netcmix_init(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + ofnode child, gchild; + phy_interface_t interface; + int bus_devfn, mii_proto; + u32 val; + + /* Default setting */ + val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII); + + /* Update the link MII protocol through parsing phy-mode */ + dev_for_each_subnode(child, dev) { + if (!ofnode_is_enabled(child)) + continue; + + ofnode_for_each_subnode(gchild, child) { + if (!ofnode_is_enabled(gchild)) + continue; + + if (!ofnode_device_is_compatible(gchild, "pci1131,e101")) + continue; + + bus_devfn = netc_of_pci_get_bus_devfn(gchild); + if (bus_devfn < 0) + return -EINVAL; + + interface = ofnode_read_phy_mode(gchild); + if (interface == -1) + continue; + + mii_proto = netc_get_link_mii_protocol(interface); + if (mii_proto < 0) + return -EINVAL; + + switch (bus_devfn) { + case IMX952_ENETC0_BUS_DEVFN: + val &= ~CFG_LINK_MII_PORT_0; + val |= FIELD_PREP(CFG_LINK_MII_PORT_0, mii_proto); + break; + case IMX952_ENETC1_BUS_DEVFN: + val &= ~CFG_LINK_MII_PORT_1; + val |= FIELD_PREP(CFG_LINK_MII_PORT_1, mii_proto); + break; + default: + return -EINVAL; + } + } + } + + if (MII_PROT_GET(val, 1) == MII_PROT_SERIAL) { + /* Configure Link I/O variant */ + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR, + IO_VAR(1, IO_VAR_16FF_16G_SERDES)); + /* Configure Link 2 PCS protocol */ + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(1), + PCS_PROT_2500M_SGMII); + } + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val); + + return 0; +} + static const struct netc_devinfo imx95_devinfo = { .netcmix_init = imx95_netcmix_init, .ierb_init = imx95_ierb_init, @@ -578,9 +645,14 @@ static const struct netc_devinfo imx94_devinfo = { .xpcs_port_init = imx94_netc_xpcs_port_init, }; +static const struct netc_devinfo imx952_devinfo = { + .netcmix_init = imx952_netcmix_init, +}; + static const struct udevice_id netc_blk_ctrl_match[] = { { .compatible = "nxp,imx95-netc-blk-ctrl", .data = (ulong)&imx95_devinfo }, { .compatible = "nxp,imx94-netc-blk-ctrl", .data = (ulong)&imx94_devinfo }, + { .compatible = "nxp,imx952-netc-blk-ctrl", .data = (ulong)&imx952_devinfo }, {}, }; -- cgit v1.3.1 From 40b43c94d29e91a023d6690eaa4fb9720a0ed1a1 Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:05 +0530 Subject: clk: stub: Sort compatible strings alphabetically Reorder compatible strings in stub_clk_ids to maintain alphabetical order for easier maintenance. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-1-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/clk/clk-stub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c index 117266ac778..ddcaaa00d91 100644 --- a/drivers/clk/clk-stub.c +++ b/drivers/clk/clk-stub.c @@ -50,10 +50,10 @@ static struct clk_ops stub_clk_ops = { static const struct udevice_id stub_clk_ids[] = { { .compatible = "qcom,rpmcc" }, - { .compatible = "qcom,sdm670-rpmh-clk" }, - { .compatible = "qcom,sdm845-rpmh-clk" }, { .compatible = "qcom,sc7180-rpmh-clk" }, { .compatible = "qcom,sc7280-rpmh-clk" }, + { .compatible = "qcom,sdm670-rpmh-clk" }, + { .compatible = "qcom,sdm845-rpmh-clk" }, { .compatible = "qcom,sm6350-rpmh-clk" }, { .compatible = "qcom,sm8150-rpmh-clk" }, { .compatible = "qcom,sm8250-rpmh-clk" }, -- cgit v1.3.1 From be1dc88b4a15b10df5a446f7219da58b3795d70d Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:06 +0530 Subject: clk: qcom: clk-stub: Add compatibles for QCS615/SA8775P Add RPMH clock compatible strings for QCS615 and SA8775P SoCs to enable clock framework support on these platforms. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-2-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/clk/clk-stub.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c index ddcaaa00d91..4a6c71016da 100644 --- a/drivers/clk/clk-stub.c +++ b/drivers/clk/clk-stub.c @@ -49,7 +49,9 @@ static struct clk_ops stub_clk_ops = { }; static const struct udevice_id stub_clk_ids[] = { + { .compatible = "qcom,qcs615-rpmh-clk" }, { .compatible = "qcom,rpmcc" }, + { .compatible = "qcom,sa8775p-rpmh-clk" }, { .compatible = "qcom,sc7180-rpmh-clk" }, { .compatible = "qcom,sc7280-rpmh-clk" }, { .compatible = "qcom,sdm670-rpmh-clk" }, -- cgit v1.3.1 From 4b1580e060847ce63b38a1f87bd482b60ec6523f Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:07 +0530 Subject: clk: qcom: sa8775p: Add UFS clock support Add UFS clock support for SA8775P including register definitions, rate configuration, and gate clocks. Reviewed-by: Sumit Garg Signed-off-by: Balaji Selvanathan Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-sa8775p.c | 63 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c index 4957abf6f58..7eec4aeae48 100644 --- a/drivers/clk/qcom/clock-sa8775p.c +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -19,6 +19,11 @@ #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0x1b028 #define USB3_PRIM_PHY_AUX_CMD_RCGR 0x1b06c +#define UFS_PHY_AXI_CLK_CMD_RCGR 0x8302c +#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x83074 +#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x830a8 +#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x8308c + #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10) #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11) #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12) @@ -44,9 +49,35 @@ #define GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT BIT(25) +/* UFS AXI clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0), + { } +}; + +/* UFS ICE CORE clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0), + { } +}; + +/* UFS UNIPRO CORE clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0), + { } +}; + static ulong sa8775p_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; if (clk->id < priv->data->num_clks) debug("%s: %s, requested rate=%ld\n", __func__, @@ -63,6 +94,24 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate) 5, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0); return rate; + case GCC_UFS_PHY_AXI_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_UNIPRO_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_ICE_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_PHY_AUX_CLK: + clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); + return 19200000; default: return 0; } @@ -106,6 +155,20 @@ static const struct gate_clk sa8775p_clks[] = { /* QUP Wrapper 3 clocks */ GATE_CLK(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT), + + /* UFS PHY clocks */ + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, 1), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, 1), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, 1), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, 1), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, 1), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, 1), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, 1), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, 1), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, 1), + + /* EDP reference clock (used by UFS PHY) */ + GATE_CLK(GCC_EDP_REF_CLKREF_EN, 0x97448, 1), }; static int sa8775p_enable(struct clk *clk) -- cgit v1.3.1 From 213edfd64501fca1c9e62640b4b1b362a2fd486a Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:08 +0530 Subject: clk: qcom: qcs615: Add UFS clock support Add UFS clock support for qcs615 including register definitions, rate configuration, and gate clocks. Reviewed-by: Sumit Garg Signed-off-by: Balaji Selvanathan Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-qcs615.c | 63 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c index 2087fc38f63..7b3fe49de9c 100644 --- a/drivers/clk/qcom/clock-qcs615.c +++ b/drivers/clk/qcom/clock-qcs615.c @@ -19,6 +19,11 @@ #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf01c #define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf060 +#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77020 +#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x77048 +#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77060 +#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x7707c + #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10) #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11) #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12) @@ -33,9 +38,37 @@ #define GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT BIT(26) #define GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT BIT(27) +/* UFS PHY AXI clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0), + F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0), + { } +}; + +/* UFS PHY ICE CORE clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0), + { } +}; + +/* UFS PHY UNIPRO CORE clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0), + F(75000000, CFG_CLK_SRC_GPLL0, 8, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + { } +}; + static ulong qcs615_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; if (clk->id < priv->data->num_clks) debug("%s: %s, requested rate=%ld\n", __func__, @@ -52,6 +85,24 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate) 5, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0); return rate; + case GCC_UFS_PHY_AXI_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_UNIPRO_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_ICE_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_PHY_AUX_CLK: + clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); + return 19200000; default: return 0; } @@ -81,7 +132,17 @@ static const struct gate_clk qcs615_clks[] = { GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT), GATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0)), - GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)) + GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)), + /* UFS clocks */ + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770c0, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77014, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77040, BIT(0)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77044, BIT(0)), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7701c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x77078, BIT(0)), + GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)), }; static int qcs615_enable(struct clk *clk) -- cgit v1.3.1 From 7e670b7d6e10e5e072dfe05f425e635acec2524c Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:09 +0530 Subject: clk: qcom: sc7280: Add UFS clock support Add UFS clock support for sc7280 including register definitions, rate configuration, and gate clocks. Reviewed-by: Sumit Garg Signed-off-by: Balaji Selvanathan Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-sc7280.c | 52 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c index 01c8587ac39..91e3fcc27cb 100644 --- a/drivers/clk/qcom/clock-sc7280.c +++ b/drivers/clk/qcom/clock-sc7280.c @@ -23,6 +23,10 @@ #define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058 #define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c #define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054 +#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77024 +#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x7706c +#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x770a0 +#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77084 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0), @@ -54,6 +58,33 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0), + { } +}; + static ulong sc7280_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -103,6 +134,26 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate) case GCC_PCIE1_PHY_RCHNG_CLK: clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN); return 100000000; + case GCC_UFS_PHY_AXI_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_ICE_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_PHY_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_phy_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_UNIPRO_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; default: return rate; } @@ -148,6 +199,7 @@ static const struct gate_clk sc7280_clks[] = { GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)), GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)), GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, BIT(0)), GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)), GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)), GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)), -- cgit v1.3.1 From 83edbe9426a4f4b22d118c9b11d82dfb3cb472ee Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:10 +0530 Subject: drivers: ufs: qcom: Initialize and enable clocks before hardware access Move UFS clock initialization and enabling before hardware setup to ensure clocks are running when accessing UFS registers. Previously, U-Boot depended on earlier bootloader stages to initialize UFS clocks. When these bootloaders failed to do so, UFS registers became inaccessible, causing initialization to fail. This change makes U-Boot initialize and enable UFS clocks early in the init sequence, removing the dependency on previous bootloaders. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-6-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/ufs/ufs-qcom.c | 53 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c index dc40ee62daf..ae33f62fbee 100644 --- a/drivers/ufs/ufs-qcom.c +++ b/drivers/ufs/ufs-qcom.c @@ -30,6 +30,7 @@ #define UFS_CPU_MAX_BANDWIDTH 819200 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable); +static u32 ufs_qcom_get_core_clk_unipro_max_freq(struct ufs_hba *hba); static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv) { @@ -47,17 +48,6 @@ static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv) return 0; } -static int ufs_qcom_init_clks(struct ufs_qcom_priv *priv) -{ - int err; - struct udevice *dev = priv->hba->dev; - - err = clk_get_bulk(dev, &priv->clks); - if (err) - return err; - - return 0; -} static int ufs_qcom_check_hibern8(struct ufs_hba *hba) { @@ -557,10 +547,45 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable) static int ufs_qcom_init(struct ufs_hba *hba) { struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + struct udevice *dev = hba->dev; + struct clk clk; + u32 max_freq; + long rate; int err; priv->hba = hba; + /* Get maximum frequency for core_clk_unipro from device tree */ + max_freq = ufs_qcom_get_core_clk_unipro_max_freq(hba); + + /* Get and configure core_clk_unipro */ + err = clk_get_by_name(dev, "core_clk_unipro", &clk); + if (err) { + dev_err(dev, "Failed to get core_clk_unipro: %d\n", err); + return err; + } + + rate = clk_set_rate(&clk, max_freq); + if (rate < 0) { + dev_err(dev, "Failed to set core_clk_unipro rate to %u Hz: %ld\n", + max_freq, rate); + } + + /* Get all clocks */ + err = clk_get_bulk(dev, &priv->clks); + if (err) { + dev_err(dev, "clk_get_bulk failed: %d\n", err); + return err; + } + + /* Enable clocks */ + err = ufs_qcom_enable_clks(priv); + if (err) { + dev_err(dev, "failed to enable clocks: %d\n", err); + clk_release_bulk(&priv->clks); + return err; + } + /* setup clocks */ ufs_qcom_setup_clocks(hba, true, PRE_CHANGE); @@ -579,12 +604,6 @@ static int ufs_qcom_init(struct ufs_hba *hba) priv->hw_ver.minor, priv->hw_ver.step); - err = ufs_qcom_init_clks(priv); - if (err) { - dev_err(hba->dev, "failed to initialize clocks, err:%d\n", err); - return err; - } - ufs_qcom_advertise_quirks(hba); ufs_qcom_setup_clocks(hba, true, POST_CHANGE); -- cgit v1.3.1 From 6d2bcb6398cf3b7caa9e80add7c49e28a1e9a6c6 Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:11 +0530 Subject: ufs: qcom: Remove redundant POST_CHANGE clock setup call The ufs_qcom_init() function was calling ufs_qcom_setup_clocks() with POST_CHANGE twice. The first call after setting PA_TXHSADAPTTYPE correctly enables the device reference clock. The second call after ufs_qcom_advertise_quirks() is redundant as the clock is already enabled. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Neha Malcom Francis Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-7-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/ufs/ufs-qcom.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c index ae33f62fbee..f5f5a6eb110 100644 --- a/drivers/ufs/ufs-qcom.c +++ b/drivers/ufs/ufs-qcom.c @@ -605,7 +605,6 @@ static int ufs_qcom_init(struct ufs_hba *hba) priv->hw_ver.step); ufs_qcom_advertise_quirks(hba); - ufs_qcom_setup_clocks(hba, true, POST_CHANGE); return 0; } -- cgit v1.3.1 From 8fce24a418bdd498ae478fa381023db2f8565f44 Mon Sep 17 00:00:00 2001 From: Timple Raj M Date: Tue, 21 Apr 2026 10:15:55 +0530 Subject: serial: msm-geni: configure RX watermark register The SE_GENI_RX_WATERMARK_REG was not being programmed in the RX setup paths. Set it to DEF_RX_WM (2) in qcom_geni_serial_start_rx(), msm_geni_serial_setup_rx() and _debug_uart_init() to align with the Linux kernel driver behaviour. Without this, the RX FIFO watermark interrupt threshold is left at its hardware reset value, which may differ from the expected value and can cause RX data loss or missed watermark interrupts. Link: https://lore.kernel.org/all/20200227132223.864425794@linuxfoundation.org/ Signed-off-by: Timple Raj M Signed-off-by: Gurumoorthy Santhakumar Reviewed-by: Simon Glass Reviewed-by: Sumit Garg Reviewed-by: Csey Connolly Link: https://patch.msgid.link/20260421044555.368486-1-gurumoorthy.santhakumar@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/serial/serial_msm_geni.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index 3dca581f68f..ae4015e0fdc 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -55,6 +55,7 @@ #define SE_UART_RX_PARITY_CFG 0x2a8 #define DEF_TX_WM 2 +#define DEF_RX_WM 2 /* GENI_FORCE_DEFAULT_REG fields */ #define UART_START_READ 0x1 @@ -345,6 +346,7 @@ static void qcom_geni_serial_start_rx(struct udevice *dev) geni_se_setup_s_cmd(priv->base, UART_START_READ, 0); + writel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG); setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); } @@ -373,6 +375,7 @@ static void msm_geni_serial_setup_rx(struct udevice *dev) geni_se_setup_s_cmd(priv->base, UART_START_READ, 0); + writel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG); setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); } @@ -616,6 +619,7 @@ static inline void _debug_uart_init(void) phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); geni_serial_init(&init_dev); + writel(DEF_RX_WM, base + SE_GENI_RX_WATERMARK_REG); geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE); qcom_geni_serial_start_tx(base); } -- cgit v1.3.1 From 140f248556f48e595480e207af13aa48629566a3 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Wed, 4 Feb 2026 16:10:52 +0000 Subject: clk/qcom: Add SM6125 clock driver Add clock driver for the GCC block found in the SM6125 SoC. Signed-off-by: Biswapriyo Nath Reviewed-by: Casey Connolly soc98: input: 1 [x] mmc@4784000.cd-gpios soc98: input: 0 [x] mmc@4784000.cd-gpios Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-1-9cf4c556557a@gmail.com Signed-off-by: Casey Connolly --- drivers/clk/qcom/Kconfig | 8 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-sm6125.c | 260 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 269 insertions(+) create mode 100644 drivers/clk/qcom/clock-sm6125.c (limited to 'drivers') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 0a2ce55aaa2..9ad233c83ac 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -111,6 +111,14 @@ config CLK_QCOM_SM6115 on the Snapdragon SM6115 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_SM6125 + bool "Qualcomm SM6125 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon SM6125 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_SM6350 bool "Qualcomm SM6350 GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b96d61b603e..c0d95a6300e 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_CLK_QCOM_QCS615) += clock-qcs615.o obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o +obj-$(CONFIG_CLK_QCOM_SM6125) += clock-sm6125.o obj-$(CONFIG_CLK_QCOM_SM6350) += clock-sm6350.o obj-$(CONFIG_CLK_QCOM_SM7150) += clock-sm7150.o obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o diff --git a/drivers/clk/qcom/clock-sm6125.c b/drivers/clk/qcom/clock-sm6125.c new file mode 100644 index 00000000000..1fd72d55e88 --- /dev/null +++ b/drivers/clk/qcom/clock-sm6125.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm sm6125 + * + * (C) Copyright 2026 Biswapriyo Nath + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clock-qcom.h" + +#define GCC_BASE 0x01400000 + +#define QUPV3_WRAP0_S4_CMD_RCGR 0x1f608 +#define SDCC1_APPS_CLK_CMD_RCGR 0x38028 +#define SDCC2_APPS_CLK_CMD_RCGR 0x1e00c + +#define GCC_GPLL0_MODE 0x0 +#define GCC_GPLL3_MODE 0x3000 +#define GCC_GPLL4_MODE 0x4000 +#define GCC_GPLL5_MODE 0x5000 +#define GCC_GPLL6_MODE 0x6000 +#define GCC_GPLL7_MODE 0x7000 +#define GCC_GPLL8_MODE 0x8000 +#define GCC_GPLL9_MODE 0x9000 + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_AUX2, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_AUX2, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_AUX2, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 16, 75), + F(75000000, CFG_CLK_SRC_GPLL0_AUX2, 4, 0, 0), + F(80000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + F(102400000, CFG_CLK_SRC_GPLL0_AUX2, 1, 128, 375), + F(112000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 28, 75), + F(117964800, CFG_CLK_SRC_GPLL0_AUX2, 1, 6144, 15625), + F(120000000, CFG_CLK_SRC_GPLL0_AUX2, 2.5, 0, 0), + F(128000000, CFG_CLK_SRC_GPLL6, 3, 0, 0), + {} +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0), + {} +}; + +static const struct pll_vote_clk gpll0_clk = { + .status = 0, + .status_bit = BIT(31), + .ena_vote = 0x79000, + .vote_bit = BIT(0), +}; + +static const struct gate_clk sm6125_clks[] = { + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1a084, BIT(0)), + GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x7900c, BIT(9)), + GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x7900c, BIT(8)), + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x7900c, BIT(10)), + GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x7900c, BIT(11)), + GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x7900c, BIT(12)), + GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x7900c, BIT(13)), + GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x7900c, BIT(14)), + GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x7900c, BIT(15)), + GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x7900c, BIT(6)), + GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x7900c, BIT(7)), + GATE_CLK(GCC_SDCC1_AHB_CLK, 0x38008, BIT(0)), + GATE_CLK(GCC_SDCC1_APPS_CLK, 0x38004, BIT(0)), + GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x3800c, BIT(0)), + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x1e008, BIT(0)), + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x1e004, BIT(0)), + GATE_CLK(GCC_SYS_NOC_CPUSS_AHB_CLK, 0x79004, BIT(0)), + GATE_CLK(GCC_SYS_NOC_UFS_PHY_AXI_CLK, 0x45098, BIT(0)), + GATE_CLK(GCC_SYS_NOC_USB3_PRIM_AXI_CLK, 0x1a080, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x45014, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x45010, BIT(0)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x45044, BIT(0)), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x45078, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x4501c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x45018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x45040, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1a010, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1a018, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1a014, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x80278, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1a054, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1a058, BIT(0)), + GATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, BIT(0)), + GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)), +}; + +static ulong sm6125_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + debug("%s: clk %s rate %lu\n", __func__, sm6125_clks[clk->id].name, + rate); + + switch (clk->id) { + case GCC_QUPV3_WRAP0_S4_CLK: + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, + 16); + return 0; + case GCC_SDCC2_APPS_CLK: + clk_enable_gpll0(priv->base, &gpll0_clk); + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + WARN(freq->src != CFG_CLK_SRC_GPLL0, + "SDCC2_APPS_CLK_SRC not set to GPLL0, requested rate %lu\n", + rate); + clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, + 8); + return freq->freq; + case GCC_SDCC1_APPS_CLK: + /* The firmware turns this on for us and always sets it to this rate */ + return 384000000; + default: + return rate; + } +} + +static int sm6125_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %s\n", __func__, sm6125_clks[clk->id].name); + + switch (clk->id) { + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK); + break; + } + + return qcom_gate_clk_en(priv, clk->id); +} + +static const struct qcom_reset_map sm6125_gcc_resets[] = { + [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, + [GCC_UFS_PHY_BCR] = { 0x45000 }, + [GCC_USB30_PRIM_BCR] = { 0x1a000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, + [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, + [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, + [GCC_CAMSS_MICRO_BCR] = { 0x560ac }, +}; + +static const struct qcom_power_map sm6125_gdscs[] = { + [USB30_PRIM_GDSC] = { 0x1a004 }, + [UFS_PHY_GDSC] = { 0x45004 }, + [CAMSS_VFE0_GDSC] = { 0x54004 }, + [CAMSS_VFE1_GDSC] = { 0x5403c }, + [CAMSS_TOP_GDSC] = { 0x5607c }, + [CAM_CPP_GDSC] = { 0x560bc }, + [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = { 0x7d060 }, + [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = { 0x80074 }, + [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = { 0x80084 }, + [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = { 0x80094 }, +}; + +static const phys_addr_t sm6125_gpll_addrs[] = { + GCC_BASE + GCC_GPLL0_MODE, GCC_BASE + GCC_GPLL3_MODE, + GCC_BASE + GCC_GPLL4_MODE, GCC_BASE + GCC_GPLL5_MODE, + GCC_BASE + GCC_GPLL6_MODE, GCC_BASE + GCC_GPLL7_MODE, + GCC_BASE + GCC_GPLL8_MODE, GCC_BASE + GCC_GPLL9_MODE, +}; + +static const phys_addr_t sm6125_rcg_addrs[] = { + 0x0141a01c, // GCC_USB30_PRIM_MASTER_CMD_RCGR + 0x0141a034, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR + 0x0141a060, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR + 0x01438028, // GCC_SDCC1_APPS_CMD_RCGR + 0x0141e00c, // GCC_SDCC2_APPS_CMD_RCGR + 0x0141f148, // GCC_QUPV3_WRAP0_S0_CMD_RCGR + 0x0141f278, // GCC_QUPV3_WRAP0_S1_CMD_RCGR + 0x0141f3a8, // GCC_QUPV3_WRAP0_S2_CMD_RCGR + 0x0141f4d8, // GCC_QUPV3_WRAP0_S3_CMD_RCGR + 0x0141f608, // GCC_QUPV3_WRAP0_S4_CMD_RCGR + 0x0141f738, // GCC_QUPV3_WRAP0_S5_CMD_RCGR + 0x01445020, // GCC_UFS_PHY_AXI_CMD_RCGR + 0x01445048, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR + 0x01445060, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR + 0x0144507c, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR +}; + +static const char *const sm6125_rcg_names[] = { + "GCC_USB30_PRIM_MASTER_CMD_RCGR", + "GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR", + "GCC_USB3_PRIM_PHY_AUX_CMD_RCGR", + "GCC_SDCC1_APPS_CMD_RCGR", + "GCC_SDCC2_APPS_CMD_RCGR", + "GCC_QUPV3_WRAP0_S0_CMD_RCGR", + "GCC_QUPV3_WRAP0_S1_CMD_RCGR", + "GCC_QUPV3_WRAP0_S2_CMD_RCGR", + "GCC_QUPV3_WRAP0_S3_CMD_RCGR", + "GCC_QUPV3_WRAP0_S4_CMD_RCGR", + "GCC_QUPV3_WRAP0_S5_CMD_RCGR", + "GCC_UFS_PHY_AXI_CMD_RCGR", + "GCC_UFS_PHY_ICE_CORE_CMD_RCGR", + "GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR", + "GCC_UFS_PHY_PHY_AUX_CMD_RCGR", +}; + +static struct msm_clk_data sm6125_gcc_data = { + .resets = sm6125_gcc_resets, + .num_resets = ARRAY_SIZE(sm6125_gcc_resets), + .clks = sm6125_clks, + .num_clks = ARRAY_SIZE(sm6125_clks), + .power_domains = sm6125_gdscs, + .num_power_domains = ARRAY_SIZE(sm6125_gdscs), + + .enable = sm6125_enable, + .set_rate = sm6125_set_rate, + + .dbg_pll_addrs = sm6125_gpll_addrs, + .num_plls = ARRAY_SIZE(sm6125_gpll_addrs), + .dbg_rcg_addrs = sm6125_rcg_addrs, + .num_rcgs = ARRAY_SIZE(sm6125_rcg_addrs), + .dbg_rcg_names = sm6125_rcg_names, +}; + +static const struct udevice_id gcc_sm6125_of_match[] = { + { + .compatible = "qcom,gcc-sm6125", + .data = (ulong)&sm6125_gcc_data, + }, + {} +}; + +U_BOOT_DRIVER(gcc_sm6125) = { + .name = "gcc_sm6125", + .id = UCLASS_NOP, + .of_match = gcc_sm6125_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v1.3.1 From 60bc1eb8c2f17ee53b566b27da1d11c5cdc25e76 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Wed, 4 Feb 2026 16:10:54 +0000 Subject: drivers: pinctrl: Add Qualcomm SM6125 TLMM driver Add support for TLMM pin controller block (Top Level Mode Multiplexer) on SM6125 SoC, with support for special pins. Signed-off-by: Biswapriyo Nath Reviewed-by: Casey Connolly soc98: input: 1 [x] mmc@4784000.cd-gpios soc98: input: 0 [x] mmc@4784000.cd-gpios Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-3-9cf4c556557a@gmail.com Signed-off-by: Casey Connolly --- drivers/pinctrl/qcom/Kconfig | 8 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm6125.c | 147 ++++++++++++++++++++++++++++++++++ 3 files changed, 156 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm6125.c (limited to 'drivers') diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 11e6763b5f3..43100d5d981 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -133,6 +133,14 @@ config PINCTRL_QCOM_SM6115 Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC, as well as the associated GPIO driver. +config PINCTRL_QCOM_SM6125 + bool "Qualcomm SM6125 Pinctrl" + default y if PINCTRL_QCOM_GENERIC + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM6125 SoC, + as well as the associated GPIO driver. + config PINCTRL_QCOM_SM6350 bool "Qualcomm SM6350 Pinctrl" default y if PINCTRL_QCOM_GENERIC diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4096c1aa491..87cb128c4d4 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_QCOM_SDM670) += pinctrl-sdm670.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o +obj-$(CONFIG_PINCTRL_QCOM_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_QCOM_SM6350) += pinctrl-sm6350.o obj-$(CONFIG_PINCTRL_QCOM_SM7150) += pinctrl-sm7150.o obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c new file mode 100644 index 00000000000..82f8972ff5b --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Pinctrl driver for Qualcomm SM6125 + * + * (C) Copyright 2026 Biswapriyo Nath + * + * Based on Linux Kernel driver + */ + +#include + +#include "pinctrl-qcom.h" + +#define TLMM_BASE 0x00500000 +#define WEST (0x00500000 - TLMM_BASE) /* 0x0 */ +#define SOUTH (0x00900000 - TLMM_BASE) /* 0x400000 */ +#define EAST (0x00d00000 - TLMM_BASE) /* 0x800000 */ + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + { "qup04", 1 }, + { "gpio", 0 }, +}; + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = pg_name, \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = pg_name, \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + } + +static const struct msm_special_pin_data msm_special_pins_data[] = { + [0] = UFS_RESET("ufs_reset", 0x190000), + [1] = SDC_QDSD_PINGROUP("sdc1_rclk", WEST + 0x18d000, 15, 0), + [2] = SDC_QDSD_PINGROUP("sdc1_clk", WEST + 0x18d000, 13, 6), + [3] = SDC_QDSD_PINGROUP("sdc1_cmd", WEST + 0x18d000, 11, 3), + [4] = SDC_QDSD_PINGROUP("sdc1_data", WEST + 0x18d000, 9, 0), + [5] = SDC_QDSD_PINGROUP("sdc2_clk", SOUTH + 0x58b000, 14, 6), + [6] = SDC_QDSD_PINGROUP("sdc2_cmd", SOUTH + 0x58b000, 11, 3), + [7] = SDC_QDSD_PINGROUP("sdc2_data", SOUTH + 0x58b000, 9, 0), +}; + +static const unsigned int sm6125_pin_offsets[] = { + [0] = WEST, [1] = WEST, [2] = WEST, [3] = WEST, + [4] = WEST, [5] = WEST, [6] = WEST, [7] = WEST, + [8] = WEST, [9] = WEST, [10] = EAST, [11] = EAST, + [12] = EAST, [13] = EAST, [14] = WEST, [15] = WEST, + [16] = WEST, [17] = WEST, [18] = EAST, [19] = EAST, + [20] = EAST, [21] = EAST, [22] = WEST, [23] = WEST, + [24] = WEST, [25] = WEST, [26] = WEST, [27] = WEST, + [28] = WEST, [29] = WEST, [30] = WEST, [31] = WEST, + [32] = WEST, [33] = WEST, [34] = SOUTH, [35] = SOUTH, + [36] = SOUTH, [37] = SOUTH, [38] = EAST, [39] = EAST, + [40] = EAST, [41] = EAST, [42] = EAST, [43] = EAST, + [44] = SOUTH, [45] = SOUTH, [46] = SOUTH, [47] = SOUTH, + [48] = SOUTH, [49] = SOUTH, [50] = SOUTH, [51] = SOUTH, + [52] = SOUTH, [53] = SOUTH, [54] = SOUTH, [55] = SOUTH, + [56] = SOUTH, [57] = SOUTH, [58] = SOUTH, [59] = SOUTH, + [60] = SOUTH, [61] = SOUTH, [62] = SOUTH, [63] = SOUTH, + [64] = SOUTH, [65] = SOUTH, [66] = SOUTH, [67] = SOUTH, + [68] = SOUTH, [69] = SOUTH, [70] = SOUTH, [71] = SOUTH, + [72] = SOUTH, [73] = SOUTH, [74] = SOUTH, [75] = SOUTH, + [76] = SOUTH, [77] = SOUTH, [78] = SOUTH, [79] = SOUTH, + [80] = SOUTH, [81] = SOUTH, [82] = SOUTH, [83] = SOUTH, + [84] = SOUTH, [85] = SOUTH, [86] = SOUTH, [87] = WEST, + [88] = WEST, [89] = WEST, [90] = WEST, [91] = WEST, + [92] = WEST, [93] = WEST, [94] = SOUTH, [95] = SOUTH, + [96] = SOUTH, [97] = SOUTH, [98] = SOUTH, [99] = SOUTH, + [100] = SOUTH, [101] = SOUTH, [102] = SOUTH, [103] = SOUTH, + [104] = EAST, [105] = EAST, [106] = EAST, [107] = EAST, + [108] = EAST, [109] = EAST, [110] = EAST, [111] = EAST, + [112] = EAST, [113] = EAST, [114] = EAST, [115] = EAST, + [116] = EAST, [117] = SOUTH, [118] = SOUTH, [119] = SOUTH, + [120] = SOUTH, [121] = EAST, [122] = EAST, [123] = EAST, + [124] = EAST, [125] = EAST, [126] = EAST, [127] = EAST, + [128] = EAST, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH, + [132] = SOUTH, +}; + +static const char *sm6125_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm6125_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector >= 133 && selector <= 140) + snprintf(pin_name, MAX_PIN_NAME_LEN, + msm_special_pins_data[selector - 133].name); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static int sm6125_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data sm6125_data = { + .pin_data = { + .pin_offsets = sm6125_pin_offsets, + .pin_count = 141, + .special_pins_start = 133, + .special_pins_data = msm_special_pins_data, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm6125_get_function_name, + .get_function_mux = sm6125_get_function_mux, + .get_pin_name = sm6125_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,sm6125-tlmm", .data = (ulong)&sm6125_data }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(pinctrl_sm6125) = { + .name = "pinctrl_sm6125", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; -- cgit v1.3.1 From 246b0f185ac08cca335a983235eb8978d6b74113 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:05:31 +0200 Subject: gpio: qcom_pmic: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260507220549.209113-1-marek.vasut+renesas@mailbox.org Signed-off-by: Casey Connolly --- drivers/gpio/qcom_pmic_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 4458c55cd3d..3cabb7df88c 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -410,7 +410,7 @@ static int qcom_pmic_pinctrl_generic_pinmux_set_mux(struct udevice *dev, unsigne return 0; } -struct pinctrl_ops qcom_pmic_pinctrl_ops = { +static const struct pinctrl_ops qcom_pmic_pinctrl_ops = { .get_pins_count = qcom_pmic_pinctrl_get_pins_count, .get_pin_name = qcom_pmic_pinctrl_get_pin_name, .set_state = pinctrl_generic_set_state, -- cgit v1.3.1 From bc2811928806bf74d1cd2e24da34d9d6d169e1fd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:05:32 +0200 Subject: gpio: qcom: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260507220549.209113-2-marek.vasut+renesas@mailbox.org Signed-off-by: Casey Connolly --- drivers/gpio/qcom_spmi_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/qcom_spmi_gpio.c b/drivers/gpio/qcom_spmi_gpio.c index 77a69140213..ae75a4e151d 100644 --- a/drivers/gpio/qcom_spmi_gpio.c +++ b/drivers/gpio/qcom_spmi_gpio.c @@ -1020,7 +1020,7 @@ static int qcom_spmi_pmic_pinctrl_pinmux_set_mux(struct udevice *dev, unsigned i return spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_EN_CTL, val); } -struct pinctrl_ops qcom_spmi_pmic_pinctrl_ops = { +static const struct pinctrl_ops qcom_spmi_pmic_pinctrl_ops = { .get_pins_count = qcom_spmi_pmic_pinctrl_get_pins_count, .get_pin_name = qcom_spmi_pmic_pinctrl_get_pin_name, .set_state = pinctrl_generic_set_state, -- cgit v1.3.1 From 5a995c2fe0b17dbff46fd7b3ed26a8338fd55404 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:21:37 +0200 Subject: pci: pcie_dw_qcom: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260508122144.512818-1-marek.vasut+renesas@mailbox.org Signed-off-by: Casey Connolly --- drivers/pci/pcie_dw_qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci/pcie_dw_qcom.c b/drivers/pci/pcie_dw_qcom.c index 10c45aaba20..ce6b4d97d1d 100644 --- a/drivers/pci/pcie_dw_qcom.c +++ b/drivers/pci/pcie_dw_qcom.c @@ -22,7 +22,7 @@ struct qcom_pcie; -struct qcom_pcie_ops { +static const struct qcom_pcie_ops { int (*config_sid)(struct qcom_pcie *priv); }; -- cgit v1.3.1 From d54d2ec651e2a98a0fe84f3f176005205fa4bdf6 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Fri, 15 May 2026 18:10:02 +0000 Subject: phy: qcom: Add SM6115 and SM6125 to QMP UFS PHY driver The UFS on SM6125 can reuse SM6115 configuration, just like Linux. Reviewed-by: Neil Armstrong Signed-off-by: Biswapriyo Nath Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-1-0a35d083d2da@gmail.com Signed-off-by: Casey Connolly --- drivers/phy/qcom/phy-qcom-qmp-ufs.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c index 80eba734a63..3df88189a90 100644 --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c @@ -1741,6 +1741,8 @@ static const struct udevice_id qmp_ufs_ids[] = { { .compatible = "qcom,milos-qmp-ufs-phy", .data = (ulong)&milos_ufsphy_cfg, }, { .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg, }, { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg }, + { .compatible = "qcom,sm6115-qmp-ufs-phy", .data = (ulong)&sm6115_ufsphy_cfg, }, + { .compatible = "qcom,sm6125-qmp-ufs-phy", .data = (ulong)&sm6115_ufsphy_cfg, }, { .compatible = "qcom,sm6350-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg }, { .compatible = "qcom,sm7150-qmp-ufs-phy", .data = (ulong)&sm7150_ufsphy_cfg }, { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg }, -- cgit v1.3.1 From bf6de8136737c4362a442d810deeadadab3d7948 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Fri, 15 May 2026 18:10:03 +0000 Subject: clk/qcom: qcm2290: Fix vote_bit of gpll6 clock This changes the vote_bit same as enable_mask in Linux clock driver. Fixes: 3ddc67573fab ("clk/qcom: qcm2290: Add SDCC1 apps clock frequency table") Signed-off-by: Biswapriyo Nath Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-2-0a35d083d2da@gmail.com Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-qcm2290.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c index 5a599085b50..c38ff1a1e4a 100644 --- a/drivers/clk/qcom/clock-qcm2290.c +++ b/drivers/clk/qcom/clock-qcm2290.c @@ -73,7 +73,7 @@ static const struct pll_vote_clk gpll6_clk = { .status = 0x6000, .status_bit = BIT(31), .ena_vote = 0x79000, - .vote_bit = BIT(7), + .vote_bit = BIT(6), }; static const struct gate_clk qcm2290_clks[] = { -- cgit v1.3.1 From 06bf459570bad2dcdbd944c70e08084a815c00df Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 7 May 2026 18:42:06 +0200 Subject: ata: fsl_sata: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/ata/fsl_sata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ata/fsl_sata.c b/drivers/ata/fsl_sata.c index 4990148388b..a29735f7609 100644 --- a/drivers/ata/fsl_sata.c +++ b/drivers/ata/fsl_sata.c @@ -960,7 +960,7 @@ static int sata_fsl_scan(struct udevice *dev) return 0; } -struct ahci_ops sata_fsl_ahci_ops = { +static const struct ahci_ops sata_fsl_ahci_ops = { .scan = sata_fsl_scan, }; -- cgit v1.3.1 From 2908a3f35b087d754dad04f746b45a5ed2c40972 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 7 May 2026 18:42:08 +0200 Subject: ata: sata_mv: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass Reviewed-by: Stefan Roese --- drivers/ata/sata_mv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index b8c73b4a9dd..3fb1a245698 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -1122,7 +1122,7 @@ static const struct udevice_id sata_mv_ids[] = { { } }; -struct ahci_ops sata_mv_ahci_ops = { +static const struct ahci_ops sata_mv_ahci_ops = { .scan = sata_mv_scan, }; -- cgit v1.3.1 From 64abe3cfcc1e86f3f1957622ad6b6732daf59c01 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 7 May 2026 18:42:40 +0200 Subject: block: rockchip: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Acked-by: Quentin Schulz Reviewed-by: Simon Glass --- drivers/block/rkmtd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/block/rkmtd.c b/drivers/block/rkmtd.c index f84cacd7ead..9334ab24a61 100644 --- a/drivers/block/rkmtd.c +++ b/drivers/block/rkmtd.c @@ -935,7 +935,7 @@ int rkmtd_detach_mtd(struct udevice *dev) return 0; } -struct rkmtd_ops rkmtd_ops = { +static const struct rkmtd_ops rkmtd_ops = { .attach_mtd = rkmtd_attach_mtd, .detach_mtd = rkmtd_detach_mtd, }; -- cgit v1.3.1 From a8f49cc1938476486a800e23f410737a0701b5ad Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 7 May 2026 18:42:57 +0200 Subject: clk: ast2500: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/clk/aspeed/clk_ast2500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index a330dcda4dc..b07d7cd419c 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -534,7 +534,7 @@ static int ast2500_clk_enable(struct clk *clk) return 0; } -struct clk_ops ast2500_clk_ops = { +static const struct clk_ops ast2500_clk_ops = { .get_rate = ast2500_clk_get_rate, .set_rate = ast2500_clk_set_rate, .enable = ast2500_clk_enable, -- cgit v1.3.1 From f23324e49ef15bcd1aa317f8555cd38aa01f1548 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 7 May 2026 18:42:58 +0200 Subject: clk: ast2600: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/clk/aspeed/clk_ast2600.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index 535010b7941..4530053bc6b 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -1161,7 +1161,7 @@ static void ast2600_clk_dump(struct udevice *dev) } #endif -struct clk_ops ast2600_clk_ops = { +static const struct clk_ops ast2600_clk_ops = { .get_rate = ast2600_clk_get_rate, .set_rate = ast2600_clk_set_rate, .enable = ast2600_clk_enable, -- cgit v1.3.1 From 31df5fc7d4c3a6588354d38f05fc5d20f22391d8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 7 May 2026 18:43:00 +0200 Subject: clk: sunxi: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/clk/sunxi/clk_sunxi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index 842a0541bd6..046d5d1605a 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -64,7 +64,7 @@ static int sunxi_clk_disable(struct clk *clk) return sunxi_set_gate(clk, false); } -struct clk_ops sunxi_clk_ops = { +static const struct clk_ops sunxi_clk_ops = { .enable = sunxi_clk_enable, .disable = sunxi_clk_disable, }; -- cgit v1.3.1 From 499cb93dec85fbdff60c3a6c626db46caccc24e6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:06:28 +0200 Subject: mailbox: apple: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Acked-by: Mark Kettenis --- drivers/mailbox/apple-mbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mailbox/apple-mbox.c b/drivers/mailbox/apple-mbox.c index 2ee49734f40..39a7edc0285 100644 --- a/drivers/mailbox/apple-mbox.c +++ b/drivers/mailbox/apple-mbox.c @@ -59,7 +59,7 @@ static int apple_mbox_recv(struct mbox_chan *chan, void *data) return 0; } -struct mbox_ops apple_mbox_ops = { +static const struct mbox_ops apple_mbox_ops = { .of_xlate = apple_mbox_of_xlate, .send = apple_mbox_send, .recv = apple_mbox_recv, -- cgit v1.3.1 From 44f6ca49e9d3c1c7bc77139fbb3968afd587f891 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:06:29 +0200 Subject: mailbox: imx: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan --- drivers/mailbox/imx-mailbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index c7eaa3de96f..fd0fce21d78 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -387,7 +387,7 @@ int imx_mu_of_xlate(struct mbox_chan *chan, struct ofnode_phandle_args *args) return plat->dcfg->of_xlate(chan, args); } -struct mbox_ops imx_mu_ops = { +static const struct mbox_ops imx_mu_ops = { .of_xlate = imx_mu_of_xlate, .request = imx_mu_chan_request, .rfree = imx_mu_chan_free, -- cgit v1.3.1 From b2961202a7a7bad23a470f7df3de2005786edccc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:06:30 +0200 Subject: mailbox: k3-sec-proxy: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/mailbox/k3-sec-proxy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c index 6f5ad37919f..6eebfcd3601 100644 --- a/drivers/mailbox/k3-sec-proxy.c +++ b/drivers/mailbox/k3-sec-proxy.c @@ -293,7 +293,7 @@ static int k3_sec_proxy_recv(struct mbox_chan *chan, void *data) return 0; } -struct mbox_ops k3_sec_proxy_mbox_ops = { +static const struct mbox_ops k3_sec_proxy_mbox_ops = { .of_xlate = k3_sec_proxy_of_xlate, .request = k3_sec_proxy_request, .rfree = k3_sec_proxy_free, -- cgit v1.3.1 From 85f4b086911c9a9601d703a06d91846f22ce3e33 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:06:31 +0200 Subject: mailbox: renesas: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/mailbox/renesas-mfis.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mailbox/renesas-mfis.c b/drivers/mailbox/renesas-mfis.c index 1e9e8285974..19b801e56a6 100644 --- a/drivers/mailbox/renesas-mfis.c +++ b/drivers/mailbox/renesas-mfis.c @@ -29,7 +29,7 @@ static int mfis_send(struct mbox_chan *chan, const void *data) return 0; } -struct mbox_ops mfis_mbox_ops = { +static const struct mbox_ops mfis_mbox_ops = { .send = mfis_send, }; -- cgit v1.3.1 From 0a1347f0a1d8660676668b5a58670dd5846cc5b6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:06:32 +0200 Subject: mailbox: sandbox: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/mailbox/sandbox-mbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mailbox/sandbox-mbox.c b/drivers/mailbox/sandbox-mbox.c index 87e06e492fe..d6ac758c4d8 100644 --- a/drivers/mailbox/sandbox-mbox.c +++ b/drivers/mailbox/sandbox-mbox.c @@ -86,7 +86,7 @@ static const struct udevice_id sandbox_mbox_ids[] = { { } }; -struct mbox_ops sandbox_mbox_mbox_ops = { +static const struct mbox_ops sandbox_mbox_mbox_ops = { .request = sandbox_mbox_request, .rfree = sandbox_mbox_free, .send = sandbox_mbox_send, -- cgit v1.3.1 From e253640e3ffa9dff8a0b5c3f8735039552fba5e9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:06:33 +0200 Subject: mailbox: stm32-ipcc: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- drivers/mailbox/stm32-ipcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c index dda108735fc..49f7795b3cd 100644 --- a/drivers/mailbox/stm32-ipcc.c +++ b/drivers/mailbox/stm32-ipcc.c @@ -147,7 +147,7 @@ static const struct udevice_id stm32_ipcc_ids[] = { { } }; -struct mbox_ops stm32_ipcc_mbox_ops = { +static const struct mbox_ops stm32_ipcc_mbox_ops = { .request = stm32_ipcc_request, .rfree = stm32_ipcc_free, .send = stm32_ipcc_send, -- cgit v1.3.1 From 0bda59b1fac580accda9e810cebead29585e6a5c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:07:14 +0200 Subject: misc: cros_ec: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass Acked-by: Quentin Schulz --- drivers/misc/cros_ec_sandbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index 432b1fbb0c4..5b9c6354bef 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -726,7 +726,7 @@ int cros_ec_probe(struct udevice *dev) return cros_ec_register(dev); } -struct dm_cros_ec_ops cros_ec_ops = { +static const struct dm_cros_ec_ops cros_ec_ops = { .packet = cros_ec_sandbox_packet, .get_switches = cros_ec_sandbox_get_switches, }; -- cgit v1.3.1 From d6a87d042e55d989751fa70f45d44dc230eedefb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:07:15 +0200 Subject: misc: i2c: eeprom-emul: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/misc/i2c_eeprom_emul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/misc/i2c_eeprom_emul.c b/drivers/misc/i2c_eeprom_emul.c index 3ad2e047ee3..40f34ad03a4 100644 --- a/drivers/misc/i2c_eeprom_emul.c +++ b/drivers/misc/i2c_eeprom_emul.c @@ -144,7 +144,7 @@ static int sandbox_i2c_eeprom_xfer(struct udevice *emul, struct i2c_msg *msg, return 0; } -struct dm_i2c_ops sandbox_i2c_emul_ops = { +static const struct dm_i2c_ops sandbox_i2c_emul_ops = { .xfer = sandbox_i2c_eeprom_xfer, }; -- cgit v1.3.1 From 9ef7c13308f685ebc701f1f0e3e686034ddda87e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:07:16 +0200 Subject: misc: x86: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/misc/qfw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index 0e002ac25f4..8a11637ca7f 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -152,7 +152,7 @@ UCLASS_DRIVER(qfw) = { .per_device_auto = sizeof(struct qfw_dev), }; -struct bootdev_ops qfw_bootdev_ops = { +static const struct bootdev_ops qfw_bootdev_ops = { .get_bootflow = qfw_get_bootflow, }; -- cgit v1.3.1 From da1ac763c9819a4326582bb048082ea8250a4077 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:08:10 +0200 Subject: mtd: spi: bootstd: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass Reviewed-by: Takahiro Kuwano --- drivers/mtd/spi/sf_bootdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/spi/sf_bootdev.c b/drivers/mtd/spi/sf_bootdev.c index 017a74a3016..6ace4ee0aed 100644 --- a/drivers/mtd/spi/sf_bootdev.c +++ b/drivers/mtd/spi/sf_bootdev.c @@ -57,7 +57,7 @@ static int sf_bootdev_bind(struct udevice *dev) return 0; } -struct bootdev_ops sf_bootdev_ops = { +static const struct bootdev_ops sf_bootdev_ops = { .get_bootflow = sf_get_bootflow, }; -- cgit v1.3.1 From 1f1ec618f2a9129714fdb30d8120d7b3808947a2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 15:50:53 +0200 Subject: cpu: armv8: Staticize driver ops Set the ops structure as static. The structure is not accessible from outside of this driver. Signed-off-by: Marek Vasut --- drivers/cpu/armv8_cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/cpu/armv8_cpu.c b/drivers/cpu/armv8_cpu.c index 4eedfe5e2c5..ed87841b723 100644 --- a/drivers/cpu/armv8_cpu.c +++ b/drivers/cpu/armv8_cpu.c @@ -124,7 +124,7 @@ int armv8_cpu_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -struct acpi_ops armv8_cpu_acpi_ops = { +static struct acpi_ops armv8_cpu_acpi_ops = { .fill_ssdt = armv8_cpu_fill_ssdt, .fill_madt = armv8_cpu_fill_madt, }; -- cgit v1.3.1 From c2912fa76b663cc7621080f5dbdf134758c27de0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:24 +0200 Subject: reset: ast2500: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/reset/reset-ast2500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c index f3543fa8cc1..39b3d025713 100644 --- a/drivers/reset/reset-ast2500.c +++ b/drivers/reset/reset-ast2500.c @@ -91,7 +91,7 @@ static const struct udevice_id ast2500_reset_ids[] = { { } }; -struct reset_ops ast2500_reset_ops = { +static const struct reset_ops ast2500_reset_ops = { .rst_assert = ast2500_reset_assert, .rst_deassert = ast2500_reset_deassert, .rst_status = ast2500_reset_status, -- cgit v1.3.1 From cecdc51a4665705e9689b6780d9e0ff9dbd13421 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:25 +0200 Subject: reset: ast2600: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/reset/reset-ast2600.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c index ec7b9b6625d..9b77f6c2b71 100644 --- a/drivers/reset/reset-ast2600.c +++ b/drivers/reset/reset-ast2600.c @@ -90,7 +90,7 @@ static const struct udevice_id ast2600_reset_ids[] = { { } }; -struct reset_ops ast2600_reset_ops = { +static const struct reset_ops ast2600_reset_ops = { .rst_assert = ast2600_reset_assert, .rst_deassert = ast2600_reset_deassert, .rst_status = ast2600_reset_status, -- cgit v1.3.1 From 432749b1a3f7be53cc8b3c6156b0c6cf6612634b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:26 +0200 Subject: reset: at91: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/reset/reset-at91.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/reset-at91.c b/drivers/reset/reset-at91.c index 165c87acdc4..ebbfae1469b 100644 --- a/drivers/reset/reset-at91.c +++ b/drivers/reset/reset-at91.c @@ -79,7 +79,7 @@ static int at91_rst_deassert(struct reset_ctl *reset_ctl) return at91_rst_update(reset, reset_ctl->id, false); } -struct reset_ops at91_reset_ops = { +static const struct reset_ops at91_reset_ops = { .of_xlate = at91_reset_of_xlate, .rst_assert = at91_rst_assert, .rst_deassert = at91_rst_deassert, -- cgit v1.3.1 From 6333bec332e87668a8a5b6b2745c81d958570e97 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:27 +0200 Subject: reset: bcm6345: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/reset/reset-bcm6345.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c index 6f140574216..161d00d1b0c 100644 --- a/drivers/reset/reset-bcm6345.c +++ b/drivers/reset/reset-bcm6345.c @@ -49,7 +49,7 @@ static int bcm6345_reset_request(struct reset_ctl *rst) return bcm6345_reset_assert(rst); } -struct reset_ops bcm6345_reset_reset_ops = { +static const struct reset_ops bcm6345_reset_reset_ops = { .request = bcm6345_reset_request, .rst_assert = bcm6345_reset_assert, .rst_deassert = bcm6345_reset_deassert, -- cgit v1.3.1 From 1fe34ada73ae056b8260106618a6c217f38f6b44 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:28 +0200 Subject: reset: dra7: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/reset/reset-dra7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/reset-dra7.c b/drivers/reset/reset-dra7.c index 2f0ec4c042f..6b570d87d23 100644 --- a/drivers/reset/reset-dra7.c +++ b/drivers/reset/reset-dra7.c @@ -51,7 +51,7 @@ static int dra7_reset_assert(struct reset_ctl *reset_ctl) return 0; } -struct reset_ops dra7_reset_ops = { +static const struct reset_ops dra7_reset_ops = { .rst_assert = dra7_reset_assert, .rst_deassert = dra7_reset_deassert, }; -- cgit v1.3.1 From 85be3b92879a2b3e2707eff9eea05977a6bb4f05 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:29 +0200 Subject: reset: mediatek: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/reset/reset-mediatek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/reset-mediatek.c b/drivers/reset/reset-mediatek.c index 4b3afab92ea..66bcf7c29b6 100644 --- a/drivers/reset/reset-mediatek.c +++ b/drivers/reset/reset-mediatek.c @@ -47,7 +47,7 @@ static int mediatek_reset_deassert(struct reset_ctl *reset_ctl) priv->regofs + ((id / 32) << 2), BIT(id % 32), 0); } -struct reset_ops mediatek_reset_ops = { +static const struct reset_ops mediatek_reset_ops = { .rst_assert = mediatek_reset_assert, .rst_deassert = mediatek_reset_deassert, }; -- cgit v1.3.1 From 4020549f9bbc00ba84af0dfc53ae9b859da67f4c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:30 +0200 Subject: reset: meson: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/reset/reset-meson.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index 6337cdaaffa..8c27563ce23 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -66,7 +66,7 @@ static int meson_reset_deassert(struct reset_ctl *reset_ctl) return meson_reset_level(reset_ctl, false); } -struct reset_ops meson_reset_ops = { +static const struct reset_ops meson_reset_ops = { .request = meson_reset_request, .rst_assert = meson_reset_assert, .rst_deassert = meson_reset_deassert, -- cgit v1.3.1 From 35cd9d8636c25a7e9bc908db2fe8adcd87e6afc0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:31 +0200 Subject: reset: npcm: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/reset/reset-npcm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c index a3b85a42250..66b541f09e6 100644 --- a/drivers/reset/reset-npcm.c +++ b/drivers/reset/reset-npcm.c @@ -126,7 +126,7 @@ static const struct udevice_id npcm_reset_ids[] = { { } }; -struct reset_ops npcm_reset_ops = { +static const struct reset_ops npcm_reset_ops = { .request = npcm_reset_request, .rfree = npcm_reset_free, .rst_assert = npcm_reset_assert, -- cgit v1.3.1 From 2a7e739c040bbeb34c39fb38d159609079109f51 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:32 +0200 Subject: reset: raspberrypi: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/reset/reset-raspberrypi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/reset-raspberrypi.c b/drivers/reset/reset-raspberrypi.c index 1792f0813f7..73acd301e3d 100644 --- a/drivers/reset/reset-raspberrypi.c +++ b/drivers/reset/reset-raspberrypi.c @@ -28,7 +28,7 @@ static int raspberrypi_reset_assert(struct reset_ctl *reset_ctl) } } -struct reset_ops raspberrypi_reset_ops = { +static const struct reset_ops raspberrypi_reset_ops = { .request = raspberrypi_reset_request, .rst_assert = raspberrypi_reset_assert, }; -- cgit v1.3.1 From ce830106bf3b2d830e971ff622663a9c7516380b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:33 +0200 Subject: reset: sunxi: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/reset/reset-sunxi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c index fd47e1f9e37..6195edd5b2f 100644 --- a/drivers/reset/reset-sunxi.c +++ b/drivers/reset/reset-sunxi.c @@ -67,7 +67,7 @@ static int sunxi_reset_deassert(struct reset_ctl *reset_ctl) return sunxi_set_reset(reset_ctl, true); } -struct reset_ops sunxi_reset_ops = { +static const struct reset_ops sunxi_reset_ops = { .request = sunxi_reset_request, .rst_assert = sunxi_reset_assert, .rst_deassert = sunxi_reset_deassert, -- cgit v1.3.1 From 1e38a363c2ae5db7f4a64fb10051ff2321891e3e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:34 +0200 Subject: reset: sandbox: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut --- drivers/reset/sandbox-reset.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c index adf9eedcba6..1c0ea7390df 100644 --- a/drivers/reset/sandbox-reset.c +++ b/drivers/reset/sandbox-reset.c @@ -85,7 +85,7 @@ static const struct udevice_id sandbox_reset_ids[] = { { } }; -struct reset_ops sandbox_reset_reset_ops = { +static const struct reset_ops sandbox_reset_reset_ops = { .request = sandbox_reset_request, .rfree = sandbox_reset_free, .rst_assert = sandbox_reset_assert, -- cgit v1.3.1 From 9c631c5dbb0758753fda452f3c5c8516f986e59a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:35 +0200 Subject: reset: sti: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- drivers/reset/sti-reset.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c index 412a0c5b452..37a37a72fd3 100644 --- a/drivers/reset/sti-reset.c +++ b/drivers/reset/sti-reset.c @@ -290,7 +290,7 @@ static int sti_reset_deassert(struct reset_ctl *reset_ctl) return sti_reset_program_hw(reset_ctl, false); } -struct reset_ops sti_reset_ops = { +static const struct reset_ops sti_reset_ops = { .rst_assert = sti_reset_assert, .rst_deassert = sti_reset_deassert, }; -- cgit v1.3.1 From 6f69da0d0fd7775f77df7ff64f761d07c901d39c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:36 +0200 Subject: reset: tegra-car: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Acked-by: Svyatoslav Ryhel --- drivers/reset/tegra-car-reset.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/tegra-car-reset.c b/drivers/reset/tegra-car-reset.c index e3ecc8d3735..63f148cf3d9 100644 --- a/drivers/reset/tegra-car-reset.c +++ b/drivers/reset/tegra-car-reset.c @@ -42,7 +42,7 @@ static int tegra_car_reset_deassert(struct reset_ctl *reset_ctl) return 0; } -struct reset_ops tegra_car_reset_ops = { +static const struct reset_ops tegra_car_reset_ops = { .request = tegra_car_reset_request, .rst_assert = tegra_car_reset_assert, .rst_deassert = tegra_car_reset_deassert, -- cgit v1.3.1 From c97fbda5fab8e42ce34d75b3a61800b9fe5162d0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:12:37 +0200 Subject: reset: tegra186: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Acked-by: Svyatoslav Ryhel --- drivers/reset/tegra186-reset.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/reset/tegra186-reset.c b/drivers/reset/tegra186-reset.c index 89624227c29..1d8f40acaef 100644 --- a/drivers/reset/tegra186-reset.c +++ b/drivers/reset/tegra186-reset.c @@ -43,7 +43,7 @@ static int tegra186_reset_deassert(struct reset_ctl *reset_ctl) return tegra186_reset_common(reset_ctl, CMD_RESET_DEASSERT); } -struct reset_ops tegra186_reset_ops = { +static const struct reset_ops tegra186_reset_ops = { .rst_assert = tegra186_reset_assert, .rst_deassert = tegra186_reset_deassert, }; -- cgit v1.3.1 From a504ad9e685a5711d894b8759dcfb1b6e3127d82 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 May 2026 17:13:32 +0200 Subject: rtc: emul: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/rtc/i2c_rtc_emul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/rtc/i2c_rtc_emul.c b/drivers/rtc/i2c_rtc_emul.c index ea11c72c964..41bdf275f1e 100644 --- a/drivers/rtc/i2c_rtc_emul.c +++ b/drivers/rtc/i2c_rtc_emul.c @@ -191,7 +191,7 @@ static int sandbox_i2c_rtc_xfer(struct udevice *emul, struct i2c_msg *msg, return 0; } -struct dm_i2c_ops sandbox_i2c_rtc_emul_ops = { +static const struct dm_i2c_ops sandbox_i2c_rtc_emul_ops = { .xfer = sandbox_i2c_rtc_xfer, }; -- cgit v1.3.1 From 50e6cda6b6b50b43940687b32c40b7cdd8d707dc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:15:52 +0200 Subject: scsi: sandbox: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/scsi/sandbox_scsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/scsi/sandbox_scsi.c b/drivers/scsi/sandbox_scsi.c index 544a0247083..5f0b01d86d5 100644 --- a/drivers/scsi/sandbox_scsi.c +++ b/drivers/scsi/sandbox_scsi.c @@ -128,7 +128,7 @@ static int sandbox_scsi_remove(struct udevice *dev) return 0; } -struct scsi_ops sandbox_scsi_ops = { +static const struct scsi_ops sandbox_scsi_ops = { .exec = sandbox_scsi_exec, .bus_reset = sandbox_scsi_bus_reset, }; -- cgit v1.3.1 From 05f76ca898b4fa98b9f875013447a3533d627ca3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:16:17 +0200 Subject: spi: apple: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Acked-by: Mark Kettenis --- drivers/spi/apple_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/apple_spi.c b/drivers/spi/apple_spi.c index 5f94e9f7a74..acb74886708 100644 --- a/drivers/spi/apple_spi.c +++ b/drivers/spi/apple_spi.c @@ -228,7 +228,7 @@ static int apple_spi_set_mode(struct udevice *bus, uint mode) return 0; } -struct dm_spi_ops apple_spi_ops = { +static const struct dm_spi_ops apple_spi_ops = { .xfer = apple_spi_xfer, .set_speed = apple_spi_set_speed, .set_mode = apple_spi_set_mode, -- cgit v1.3.1 From 83cf74a01a836d662db2413b80d50264fa7bdcfb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 18 May 2026 15:49:52 -0600 Subject: block: ide: Drop empty bootdev_ops structure We don't need to provide an empty struct here now that the caller can handle this being empty. Signed-off-by: Tom Rini --- drivers/block/ide.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/block/ide.c b/drivers/block/ide.c index cab5e1bc92b..c1a46dd2a94 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -969,9 +969,6 @@ static int ide_bootdev_hunt(struct bootdev_hunter *info, bool show) return 0; } -struct bootdev_ops ide_bootdev_ops = { -}; - static const struct udevice_id ide_bootdev_ids[] = { { .compatible = "u-boot,bootdev-ide" }, { } @@ -980,7 +977,6 @@ static const struct udevice_id ide_bootdev_ids[] = { U_BOOT_DRIVER(ide_bootdev) = { .name = "ide_bootdev", .id = UCLASS_BOOTDEV, - .ops = &ide_bootdev_ops, .bind = ide_bootdev_bind, .of_match = ide_bootdev_ids, }; -- cgit v1.3.1 From ce12ad70b8b7984cceeaa236ad61498bdcfdc5bd Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 19 May 2026 07:53:14 -0600 Subject: ata: sata: Drop empty bootdev_ops structure We don't need to provide an empty struct here now that the caller can handle this being empty. Signed-off-by: Tom Rini --- drivers/ata/sata_bootdev.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/ata/sata_bootdev.c b/drivers/ata/sata_bootdev.c index a5ca6f6fd5b..7d5ef3c94bf 100644 --- a/drivers/ata/sata_bootdev.c +++ b/drivers/ata/sata_bootdev.c @@ -37,9 +37,6 @@ static int sata_bootdev_hunt(struct bootdev_hunter *info, bool show) return 0; } -struct bootdev_ops sata_bootdev_ops = { -}; - static const struct udevice_id sata_bootdev_ids[] = { { .compatible = "u-boot,bootdev-sata" }, { } @@ -48,7 +45,6 @@ static const struct udevice_id sata_bootdev_ids[] = { U_BOOT_DRIVER(sata_bootdev) = { .name = "sata_bootdev", .id = UCLASS_BOOTDEV, - .ops = &sata_bootdev_ops, .bind = sata_bootdev_bind, .of_match = sata_bootdev_ids, }; -- cgit v1.3.1 From e84d147bd3e60ae1bce6b6f4bd50f088521a7da1 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 19 May 2026 07:53:19 -0600 Subject: scsi: Drop empty bootdev_ops structure We don't need to provide an empty struct here now that the caller can handle this being empty. Signed-off-by: Tom Rini --- drivers/scsi/scsi_bootdev.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/scsi/scsi_bootdev.c b/drivers/scsi/scsi_bootdev.c index 28e4612f337..541b021b732 100644 --- a/drivers/scsi/scsi_bootdev.c +++ b/drivers/scsi/scsi_bootdev.c @@ -37,9 +37,6 @@ static int scsi_bootdev_hunt(struct bootdev_hunter *info, bool show) return 0; } -struct bootdev_ops scsi_bootdev_ops = { -}; - static const struct udevice_id scsi_bootdev_ids[] = { { .compatible = "u-boot,bootdev-scsi" }, { } @@ -48,7 +45,6 @@ static const struct udevice_id scsi_bootdev_ids[] = { U_BOOT_DRIVER(scsi_bootdev) = { .name = "scsi_bootdev", .id = UCLASS_BOOTDEV, - .ops = &scsi_bootdev_ops, .bind = scsi_bootdev_bind, .of_match = scsi_bootdev_ids, }; -- cgit v1.3.1 From e81c552171d8793f872f2ff2de1e07bd1d9949cf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 19 May 2026 07:53:26 -0600 Subject: virtio: Drop empty bootdev_ops structure We don't need to provide an empty struct here now that the caller can handle this being empty. Signed-off-by: Tom Rini --- drivers/virtio/virtio-uclass.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c index c36e9e9b3a7..a871a1439d4 100644 --- a/drivers/virtio/virtio-uclass.c +++ b/drivers/virtio/virtio-uclass.c @@ -400,9 +400,6 @@ UCLASS_DRIVER(virtio) = { .per_device_auto = sizeof(struct virtio_dev_priv), }; -struct bootdev_ops virtio_bootdev_ops = { -}; - static const struct udevice_id virtio_bootdev_ids[] = { { .compatible = "u-boot,bootdev-virtio" }, { } @@ -411,7 +408,6 @@ static const struct udevice_id virtio_bootdev_ids[] = { U_BOOT_DRIVER(virtio_bootdev) = { .name = "virtio_bootdev", .id = UCLASS_BOOTDEV, - .ops = &virtio_bootdev_ops, .bind = virtio_bootdev_bind, .of_match = virtio_bootdev_ids, }; -- cgit v1.3.1 From ccec4ce2ee8ae7c95a00b16da0b5dbd88615a8e2 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Sat, 16 May 2026 16:39:53 +0900 Subject: sysreset: qemu virt: Use map_sysmem() In the platform data there is a phys_addr_t (an integer) for the address of the register and we pass that as-is into writel() which is fine in most places because we don't need to do any mapping and the macro for writel() does a cast to a pointer. If writel() is a static inline function the address argument is a pointer so passing it in as an integer without casting it first causes warnings or build failure. map_sysmem() handles the casting part and if phys_addr_t is 32bits when on a 64bit machine. Signed-off-by: Daniel Palmer Acked-by: Kuan-Wei Chiu --- drivers/sysreset/sysreset_qemu_virt_ctrl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/sysreset/sysreset_qemu_virt_ctrl.c b/drivers/sysreset/sysreset_qemu_virt_ctrl.c index e7cacc9b6e9..61b38d507fc 100644 --- a/drivers/sysreset/sysreset_qemu_virt_ctrl.c +++ b/drivers/sysreset/sysreset_qemu_virt_ctrl.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -24,6 +25,7 @@ static int qemu_virt_ctrl_request(struct udevice *dev, enum sysreset_t type) { struct qemu_virt_ctrl_plat *plat = dev_get_plat(dev); + void __iomem *reg = map_sysmem(plat->reg + VIRT_CTRL_REG_CMD, 0x4); u32 val; switch (type) { @@ -38,7 +40,7 @@ static int qemu_virt_ctrl_request(struct udevice *dev, enum sysreset_t type) return -EPROTONOSUPPORT; } - writel(val, plat->reg + VIRT_CTRL_REG_CMD); + writel(val, reg); return -EINPROGRESS; } -- cgit v1.3.1 From 0bcd158db30aa14aa6add56060626388079c50cf Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Sat, 16 May 2026 16:39:54 +0900 Subject: sysreset: qemu virt: Use __raw_writel() The virt ctrl register seems to be native endian, currently this driver uses writel(), which works by luck because its currently broken on m68k. Use __raw_writel() instead to avoid breaking this driver when the endianness of writel() is fixed. Acked-by: Kuan-Wei Chiu Reviewed-by: Angelo Dureghello Reviewed-by: Simon Glass Signed-off-by: Daniel Palmer --- drivers/sysreset/sysreset_qemu_virt_ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/sysreset/sysreset_qemu_virt_ctrl.c b/drivers/sysreset/sysreset_qemu_virt_ctrl.c index 61b38d507fc..ce15e776f8f 100644 --- a/drivers/sysreset/sysreset_qemu_virt_ctrl.c +++ b/drivers/sysreset/sysreset_qemu_virt_ctrl.c @@ -40,7 +40,7 @@ static int qemu_virt_ctrl_request(struct udevice *dev, enum sysreset_t type) return -EPROTONOSUPPORT; } - writel(val, reg); + __raw_writel(val, reg); return -EINPROGRESS; } -- cgit v1.3.1 From 5116fed77dee99a513f17f18be0dbf2e63363eef Mon Sep 17 00:00:00 2001 From: Kuan-Wei Chiu Date: Sat, 16 May 2026 16:39:55 +0900 Subject: rtc: goldfish: Use __raw_readl() and __raw_writel() In QEMU, the Goldfish RTC is explicitly instantiated as a big-endian device on the m68k virt machine (via the 'big-endian=true' property). Currently, this driver uses ioread32() and iowrite32(), which works by luck because the underlying readl() and writel() are currently broken on m68k. Use __raw_readl() and __raw_writel() instead to avoid breaking this driver when the endianness of readl() and writel() is fixed. Signed-off-by: Kuan-Wei Chiu Tested-by: Daniel Palmer Reviewed-by: Simon Glass Signed-off-by: Daniel Palmer --- drivers/rtc/goldfish_rtc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/goldfish_rtc.c b/drivers/rtc/goldfish_rtc.c index d2991ca6719..4892a63f8d8 100644 --- a/drivers/rtc/goldfish_rtc.c +++ b/drivers/rtc/goldfish_rtc.c @@ -40,8 +40,8 @@ static int goldfish_rtc_get(struct udevice *dev, struct rtc_time *time) u64 time_low; u64 now; - time_low = ioread32(base + GOLDFISH_TIME_LOW); - time_high = ioread32(base + GOLDFISH_TIME_HIGH); + time_low = __raw_readl(base + GOLDFISH_TIME_LOW); + time_high = __raw_readl(base + GOLDFISH_TIME_HIGH); now = (time_high << 32) | time_low; do_div(now, 1000000000U); @@ -62,8 +62,8 @@ static int goldfish_rtc_set(struct udevice *dev, const struct rtc_time *time) return -EINVAL; now = rtc_mktime(time) * 1000000000ULL; - iowrite32(now >> 32, base + GOLDFISH_TIME_HIGH); - iowrite32(now, base + GOLDFISH_TIME_LOW); + __raw_writel(now >> 32, base + GOLDFISH_TIME_HIGH); + __raw_writel(now, base + GOLDFISH_TIME_LOW); if (time->tm_isdst > 0) priv->isdst = 1; -- cgit v1.3.1 From 75a1d7280a72d587d54b6af653234a96210f7177 Mon Sep 17 00:00:00 2001 From: Kuan-Wei Chiu Date: Sat, 16 May 2026 16:39:56 +0900 Subject: timer: goldfish: Use __raw_readl() The Goldfish timer registers are native endian, so they act as big-endian on the m68k virt machine. Currently, this driver uses readl(), which works by luck because it's currently broken on m68k. Use __raw_readl() instead to avoid breaking this driver when the endianness of readl() is fixed. Signed-off-by: Kuan-Wei Chiu Tested-by: Daniel Palmer Reviewed-by: Simon Glass Signed-off-by: Daniel Palmer --- drivers/timer/goldfish_timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/timer/goldfish_timer.c b/drivers/timer/goldfish_timer.c index 70673bbd93c..91277d7932a 100644 --- a/drivers/timer/goldfish_timer.c +++ b/drivers/timer/goldfish_timer.c @@ -31,8 +31,8 @@ static u64 goldfish_timer_get_count(struct udevice *dev) * We must read LOW before HIGH to latch the high 32-bit value * and ensure a consistent 64-bit timestamp. */ - low = readl(priv->base + TIMER_TIME_LOW); - high = readl(priv->base + TIMER_TIME_HIGH); + low = __raw_readl(priv->base + TIMER_TIME_LOW); + high = __raw_readl(priv->base + TIMER_TIME_HIGH); time = ((u64)high << 32) | low; -- cgit v1.3.1 From 009cd5b56dbc2d0f7675e4262347a1a6b6a55cb2 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Sat, 16 May 2026 16:39:58 +0900 Subject: virtio: mmio: Allow instantiation via platform data The m68k QEMU virt machine doesn't use devicetree, yet, so allow it to create virtio-mmio instances via platform data. Reviewed-by: Simon Glass Reviewed-by: Kuan-Wei Chiu Reviewed-by: Angelo Dureghello Signed-off-by: Daniel Palmer --- drivers/virtio/virtio_mmio.c | 27 ++++++++++++++++++--------- include/virtio_mmio.h | 12 ++++++++++++ 2 files changed, 30 insertions(+), 9 deletions(-) create mode 100644 include/virtio_mmio.h (limited to 'drivers') diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index d90d8309f99..975f98cd9e5 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -335,21 +336,28 @@ static int virtio_mmio_notify(struct udevice *udev, struct virtqueue *vq) static int virtio_mmio_of_to_plat(struct udevice *udev) { - struct virtio_mmio_priv *priv = dev_get_priv(udev); + struct virtio_mmio_plat *plat = dev_get_plat(udev); + fdt_addr_t addr; + + addr = dev_read_addr(udev); - priv->base = (void __iomem *)(ulong)dev_read_addr(udev); - if (priv->base == (void __iomem *)FDT_ADDR_T_NONE) + if (addr == FDT_ADDR_T_NONE) return -EINVAL; + plat->base = addr; + return 0; } static int virtio_mmio_probe(struct udevice *udev) { + struct virtio_mmio_plat *plat = dev_get_plat(udev); struct virtio_mmio_priv *priv = dev_get_priv(udev); struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); u32 magic; + priv->base = (void __iomem *)(uintptr_t)plat->base; + /* Check magic value */ magic = readl(priv->base + VIRTIO_MMIO_MAGIC_VALUE); if (magic != ('v' | 'i' << 8 | 'r' << 16 | 't' << 24)) { @@ -405,11 +413,12 @@ static const struct udevice_id virtio_mmio_ids[] = { }; U_BOOT_DRIVER(virtio_mmio) = { - .name = "virtio-mmio", - .id = UCLASS_VIRTIO, - .of_match = virtio_mmio_ids, - .ops = &virtio_mmio_ops, - .probe = virtio_mmio_probe, + .name = "virtio-mmio", + .id = UCLASS_VIRTIO, + .of_match = virtio_mmio_ids, + .ops = &virtio_mmio_ops, + .probe = virtio_mmio_probe, .of_to_plat = virtio_mmio_of_to_plat, - .priv_auto = sizeof(struct virtio_mmio_priv), + .priv_auto = sizeof(struct virtio_mmio_priv), + .plat_auto = sizeof(struct virtio_mmio_plat), }; diff --git a/include/virtio_mmio.h b/include/virtio_mmio.h new file mode 100644 index 00000000000..8c072826db5 --- /dev/null +++ b/include/virtio_mmio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __VIRTIO_MMIO_H__ +#define __VIRTIO_MMIO_H__ + +#include + +struct virtio_mmio_plat { + phys_addr_t base; +}; + +#endif /* __VIRTIO_MMIO_H__ */ -- cgit v1.3.1 From ddba15ab72df5a01fd483a0f4fc40f9ae4d2475c Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Sat, 16 May 2026 16:40:00 +0900 Subject: virtio: blk: Fix converting the vendor id to a string Currently we are trying to work out if the vendor id is from a virtio-mmio device and then casting a u32 to a char* and using it as a C-string. By chance there is usually a zero after the u32 and it works. Since the vendor id we are trying to convert to a string is QEMU's just define a value for the QEMU vendor id, check if the vendor id matches and then use a predefined string for "QEMU". I don't think we should have been assumming all virtio-mmio vendor ids are printable ASCII chars in the first place so do this special casing just for QEMU. If the vendor id isn't QEMU print the hex value of it. Reviewed-by: Simon Glass Reviewed-by: Kuan-Wei Chiu Signed-off-by: Daniel Palmer --- drivers/virtio/virtio_blk.c | 11 ++++------- include/virtio.h | 3 +++ 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c index 45fb596a330..94968ef1c75 100644 --- a/drivers/virtio/virtio_blk.c +++ b/drivers/virtio/virtio_blk.c @@ -231,14 +231,11 @@ static int virtio_blk_bind(struct udevice *dev) return devnum; desc->devnum = devnum; desc->part_type = PART_TYPE_UNKNOWN; - /* - * virtio mmio transport supplies string identification for us, - * while pci trnasport uses a 2-byte subvendor value. - */ - if (uc_priv->vendor >> 16) - sprintf(desc->vendor, "%s", (char *)&uc_priv->vendor); + + if (uc_priv->vendor == VIRTIO_VENDOR_QEMU) + strcpy(desc->vendor, "QEMU"); else - sprintf(desc->vendor, "%04x", uc_priv->vendor); + sprintf(desc->vendor, "%08x", uc_priv->vendor); desc->bdev = dev; /* Indicate what driver features we support */ diff --git a/include/virtio.h b/include/virtio.h index 17f894a79e3..3edf023463d 100644 --- a/include/virtio.h +++ b/include/virtio.h @@ -25,6 +25,9 @@ #include #include #include + +#define VIRTIO_VENDOR_QEMU 0x554d4551 + #define VIRTIO_ID_NET 1 /* virtio net */ #define VIRTIO_ID_BLOCK 2 /* virtio block */ #define VIRTIO_ID_RNG 4 /* virtio rng */ -- cgit v1.3.1 From ed5d719bc25b3cc9121992d1ffa845ba8cd6a548 Mon Sep 17 00:00:00 2001 From: Vincent Jardin Date: Sun, 10 May 2026 23:28:18 +0200 Subject: gpio: uclass: show DT gpio-line-names gpio status -a does not have labels: the existing path walks the per-bank requested label table. Issue: The boards that populate the standard gpio-line-names property in their device tree end up with anonymous entries, which is not logic with the purpose of having those names in the DT. No impact with boards that does not set gpio-line-names. Signed-off-by: Vincent Jardin --- drivers/gpio/gpio-uclass.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 7651d5360d6..4d40738e5aa 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -877,8 +877,19 @@ static int get_function(struct udevice *dev, int offset, bool skip_unused, return -ENODEV; if (offset < 0 || offset >= uc_priv->gpio_count) return -EINVAL; - if (namep) + if (namep) { *namep = uc_priv->name[offset]; + /* Fall back to DT "gpio-line-names" for unrequested pins. */ + if (CONFIG_IS_ENABLED(DM_GPIO_LOOKUP_LINE_NAME) && + (!*namep || !**namep)) { + const char *dt_name = NULL; + + if (!dev_read_string_index(dev, "gpio-line-names", + offset, &dt_name) && + dt_name && *dt_name) + *namep = dt_name; + } + } if (skip_unused && !gpio_is_claimed(uc_priv, offset)) return GPIOF_UNUSED; if (ops->get_function) { -- cgit v1.3.1 From 422024172f3b989d575dc5b2951899439c59d3f2 Mon Sep 17 00:00:00 2001 From: Francois Berder Date: Sat, 9 May 2026 19:30:53 +0200 Subject: led: Fix toggling LED on initial SW blink If the LED is in the ON state, it is briefly set to OFF then to ON immediately due to falling-through in the default case. This commit ensures that no fall-through occurs and thus a LED initially in the ON state is turned off before blinking. Signed-off-by: Francois Berder Fixes: 9e3d83301e4f ("led: toggle LED on initial SW blink") Acked-by: Quentin Schulz Reviewed-by: Simon Glass --- drivers/led/led_sw_blink.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/led/led_sw_blink.c b/drivers/led/led_sw_blink.c index ee1546d02d4..4190fde8f0f 100644 --- a/drivers/led/led_sw_blink.c +++ b/drivers/led/led_sw_blink.c @@ -114,9 +114,11 @@ bool led_sw_on_state_change(struct udevice *dev, enum led_state_t state) case LEDST_ON: ops->set_state(dev, LEDST_OFF); sw_blink->state = LED_SW_BLINK_ST_OFF; + break; default: ops->set_state(dev, LEDST_ON); sw_blink->state = LED_SW_BLINK_ST_ON; + break; } return true; -- cgit v1.3.1 From a219f64c2794135b44ab9aa9b808c5c25d18262c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 8 May 2026 10:22:32 -0600 Subject: cros_ec: Sync ec_commands.h from upstream Chrome OS EC Sync include/ec_commands.h from upstream commit 4f3d17aa34 ("skywalker: set SLEEP_TIMEOUT_MS to 50 seconds"). The new file makes two build assumptions that do not hold for U-Boot. It hides '' from __KERNEL__ builds, leaving UINT16_MAX (used by EC_RES_MAX) undefined for U-Boot; widen the gate to '!defined(__KERNEL__) || defined(__UBOOT__)' It gates '' on '#ifdef __KERNEL__'; the matching '#else' branch defines BIT()/BIT_ULL()/GENMASK()/GENMASK_ULL() locally, assuming kernel headers provide those macros otherwise. U-Boot defines __KERNEL__ too but has no . Nest a '!defined(__UBOOT__)' check around the include so the __UBOOT__ path stays in the __KERNEL__ branch (no local BIT/GENMASK defines), which avoids redefinition warnings against U-Boot's linux/bitops.h. Pull in linux/bitops.h up front for U-Boot so the file's own BIT() and GENMASK() uses still resolve. Adapt callers to two interface changes. The 'ec_current_image' enum tag is now 'ec_image' (EC_IMAGE_* constants unchanged); rename it in affected files to match. The VBNV-context interface was dropped upstream, but it still used in lab Chromebooks; keep those constants and structs in cros_ec.h Likewise, MEC_EMI_BASE and MEC_EMI_SIZE are a U-Boot-local addition to ec_commands.h that the upstream sync removes; preserve them in cros_ec.h next to the VBNV block, and switch the only consumer (arch/x86/cpu/apollolake/cpu_spl.c) to include cros_ec.h Signed-off-by: Simon Glass --- arch/x86/cpu/apollolake/cpu_spl.c | 2 +- cmd/cros_ec.c | 4 +- drivers/misc/cros_ec.c | 2 +- drivers/misc/cros_ec_sandbox.c | 2 +- include/cros_ec.h | 36 +- include/ec_commands.h | 7784 +++++++++++++++++++++++++++++-------- 6 files changed, 6299 insertions(+), 1531 deletions(-) (limited to 'drivers') diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c index 8198667fa50..080c5a58575 100644 --- a/arch/x86/cpu/apollolake/cpu_spl.c +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -6,7 +6,7 @@ */ #include -#include +#include #include #include #include diff --git a/cmd/cros_ec.c b/cmd/cros_ec.c index 7b60e415b6c..66a5f6d5210 100644 --- a/cmd/cros_ec.c +++ b/cmd/cros_ec.c @@ -13,7 +13,7 @@ #include #include -/* Note: depends on enum ec_current_image */ +/* Note: depends on enum ec_image */ static const char * const ec_current_image_name[] = {"unknown", "RO", "RW"}; /** @@ -312,7 +312,7 @@ static int do_cros_ec(struct cmd_tbl *cmdtp, int flag, int argc, if (ret) printf("Error: %d\n", ret); } else if (0 == strcmp("curimage", cmd)) { - enum ec_current_image image; + enum ec_image image; if (cros_ec_read_current_image(dev, &image)) { debug("%s: Could not read KBC image\n", __func__); diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index fabe4964a33..c3e647edfac 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -487,7 +487,7 @@ int cros_ec_read_build_info(struct udevice *dev, char **strp) } int cros_ec_read_current_image(struct udevice *dev, - enum ec_current_image *image) + enum ec_image *image) { struct ec_response_get_version *r; diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index 5b9c6354bef..9fedca4e6b6 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -100,7 +100,7 @@ struct ec_state { struct fdt_cros_ec ec_config; uint8_t *flash_data; int flash_data_len; - enum ec_current_image current_image; + enum ec_image current_image; int matrix_count; struct ec_keymatrix_entry *matrix; /* the key matrix info */ uint8_t keyscan[KEYBOARD_COLS]; diff --git a/include/cros_ec.h b/include/cros_ec.h index 94c988a7d65..4ef34815e35 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -14,6 +14,40 @@ #include #include +/* + * Verified-boot NVRAM context interface the EC exposes via + * EC_CMD_VBNV_CONTEXT. Upstream cros_ec_commands.h dropped the + * whole vbnvcontext machinery, so keep the constants and request / + * response structs here for U-Boot. Both 'cros_ec vbnvcontext' and + * cros_ec_{read,write}_vbnvcontext() depend on these. + */ +#define EC_CMD_VBNV_CONTEXT 0x0017 +#define EC_VER_VBNV_CONTEXT 1 +#define EC_VBNV_BLOCK_SIZE 16 +#define EC_VBNV_BLOCK_SIZE_V2 64 + +enum ec_vbnvcontext_op { + EC_VBNV_CONTEXT_OP_READ, + EC_VBNV_CONTEXT_OP_WRITE, +}; + +struct __ec_align4 ec_params_vbnvcontext { + uint32_t op; + uint8_t block[EC_VBNV_BLOCK_SIZE_V2]; +}; + +struct __ec_align4 ec_response_vbnvcontext { + uint8_t block[EC_VBNV_BLOCK_SIZE_V2]; +}; + +/* + * EMI register window used by Microchip MEC-style EC LPC interfaces. + * Upstream cros_ec_commands.h does not carry these, but apollolake's + * SPL needs them to set up the EC ioport range. + */ +#define MEC_EMI_BASE 0x800 +#define MEC_EMI_SIZE 8 + /* Our configuration information */ struct cros_ec_dev { struct udevice *dev; /* Transport device */ @@ -101,7 +135,7 @@ int cros_ec_get_next_event(struct udevice *dev, * Return: 0 if ok, <0 on error */ int cros_ec_read_current_image(struct udevice *dev, - enum ec_current_image *image); + enum ec_image *image); /** * Read the hash of the CROS-EC device firmware. diff --git a/include/ec_commands.h b/include/ec_commands.h index 23597d28b2c..cedc34dd0fc 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -1,31 +1,97 @@ -/* Copyright (c) 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2014 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Host communication command constants for Chrome EC */ -#ifndef __CROS_EC_COMMANDS_H -#define __CROS_EC_COMMANDS_H +#ifndef __CROS_EC_EC_COMMANDS_H +#define __CROS_EC_EC_COMMANDS_H +#if !defined(__ACPI__) && (!defined(__KERNEL__) || defined(__UBOOT__)) +#include +#endif + +#ifdef __UBOOT__ +#include +#endif + +#ifdef CHROMIUM_EC /* - * Protocol overview - * - * request: CMD [ P0 P1 P2 ... Pn S ] - * response: ERR [ P0 P1 P2 ... Pn S ] - * - * where the bytes are defined as follow : - * - CMD is the command code. (defined by EC_CMD_ constants) - * - ERR is the error code. (defined by EC_RES_ constants) - * - Px is the optional payload. - * it is not sent if the error code is not success. - * (defined by ec_params_ and ec_response_ structures) - * - S is the checksum which is the sum of all payload bytes. - * - * On LPC, CMD and ERR are sent/received at EC_LPC_ADDR_KERNEL|USER_CMD - * and the payloads are sent/received at EC_LPC_ADDR_KERNEL|USER_PARAM. - * On I2C, all bytes are sent serially in the same message. + * CHROMIUM_EC is defined by the Makefile system of Chromium EC repository. + * It is used to not include macros that may cause conflicts in foreign + * projects (refer to crbug.com/984623). + */ + +/* + * Include common.h for CONFIG_HOSTCMD_ALIGNED, if it's defined. This + * generates more efficient code for accessing request/response structures on + * ARM Cortex-M if the structures are guaranteed 32-bit aligned. + */ +#include "common.h" +#include "compile_time_macros.h" + +#else +/* If BUILD_ASSERT isn't already defined, make it a no-op */ +#ifndef BUILD_ASSERT +#define BUILD_ASSERT(_cond) +#endif /* !BUILD_ASSERT */ +#endif /* CHROMIUM_EC */ + +#if defined(__KERNEL__) +#if !defined(__UBOOT__) +#include +#endif +#else +/* + * Defines macros that may be needed but are for sure defined by the linux + * kernel. This section is removed when cros_ec_commands.h is generated (by + * util/make_linux_ec_commands_h.sh). + * cros_ec_commands.h looks more integrated to the kernel. + */ + +#ifndef BIT +#define BIT(nr) (1UL << (nr)) +#endif + +#ifndef BIT_ULL +#define BIT_ULL(nr) (1ULL << (nr)) +#endif + +/* + * When building Zephyr, this file ends up being included before Zephyr's + * include/sys/util.h so causes a warning there. We don't want to add an #ifdef + * in that file since it won't be accepted upstream. So work around it here. + */ +#ifndef CONFIG_ZEPHYR +#ifndef GENMASK +#define GENMASK(h, l) (((BIT(h) << 1) - 1) ^ (BIT(l) - 1)) +#endif + +#ifndef GENMASK_ULL +#define GENMASK_ULL(h, l) (((BIT_ULL(h) << 1) - 1) ^ (BIT_ULL(l) - 1)) +#endif +#endif + +#endif /* __KERNEL__ */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Constant for creation of flexible array members that work in both C and + * C++. Flexible array members were added in C99 and are not part of the C++ + * standard. However, clang++ supports them for C++. + * When compiling with gcc, flexible array members are not allowed to appear + * in an otherwise empty struct, so we use the GCC zero-length array + * extension that works with both clang/gcc/g++. */ +#if defined(__cplusplus) && defined(__clang__) +#define FLEXIBLE_ARRAY_MEMBER_SIZE +#else +#define FLEXIBLE_ARRAY_MEMBER_SIZE 0 +#endif /* * Current version of this protocol @@ -34,91 +100,111 @@ * determined in other ways. Remove this once the kernel code no longer * depends on it. */ -#define EC_PROTO_VERSION 0x00000002 +#define EC_PROTO_VERSION 0x00000002 /* Command version mask */ -#define EC_VER_MASK(version) (1UL << (version)) +#define EC_VER_MASK(version) BIT(version) /* I/O addresses for ACPI commands */ -#define EC_LPC_ADDR_ACPI_DATA 0x62 -#define EC_LPC_ADDR_ACPI_CMD 0x66 +#define EC_LPC_ADDR_ACPI_DATA 0x62 +#define EC_LPC_ADDR_ACPI_CMD 0x66 /* I/O addresses for host command */ -#define EC_LPC_ADDR_HOST_DATA 0x200 -#define EC_LPC_ADDR_HOST_CMD 0x204 +#define EC_LPC_ADDR_HOST_DATA 0x200 +#define EC_LPC_ADDR_HOST_CMD 0x204 /* I/O addresses for host command args and params */ /* Protocol version 2 */ -#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ -#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is - * EC_PROTO2_MAX_PARAM_SIZE */ +#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ +/* For version 2 params; size is EC_PROTO2_MAX_PARAM_SIZE */ +#define EC_LPC_ADDR_HOST_PARAM 0x804 + /* Protocol version 3 */ -#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ -#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ +#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ +#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ -/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff - * and they tell the kernel that so we have to think of it as two parts. */ -#define EC_HOST_CMD_REGION0 0x800 -#define EC_HOST_CMD_REGION1 0x880 +/* + * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff + * and they tell the kernel that so we have to think of it as two parts. + * + * Other BIOSes report only the I/O port region spanned by the Microchip + * MEC series EC; an attempt to address a larger region may fail. + */ +#define EC_HOST_CMD_REGION0 0x800 +#define EC_HOST_CMD_REGION1 0x880 #define EC_HOST_CMD_REGION_SIZE 0x80 +#define EC_HOST_CMD_MEC_REGION_SIZE 0x8 /* EC command register bit functions */ -#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */ -#define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */ -#define EC_LPC_CMDR_BUSY (1 << 2) /* EC is busy processing a command */ -#define EC_LPC_CMDR_CMD (1 << 3) /* Last host write was a command */ -#define EC_LPC_CMDR_ACPI_BRST (1 << 4) /* Burst mode (not used) */ -#define EC_LPC_CMDR_SCI (1 << 5) /* SCI event is pending */ -#define EC_LPC_CMDR_SMI (1 << 6) /* SMI event is pending */ - -/* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource */ -#define MEC_EMI_BASE 0x800 -#define MEC_EMI_SIZE 8 - -#define EC_LPC_ADDR_MEMMAP 0x900 -#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ -#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ +#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ +#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ +#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ +#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ +#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ +#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ +#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */ + +#define EC_LPC_ADDR_MEMMAP 0x900 +#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ +#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ + +#define EC_LPC_ADDR_MEMMAP_INDEXED_IO 0x380 /* The offset address of each type of data in mapped memory. */ -#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */ -#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */ -#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */ -#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */ -#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ -#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ -#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ +#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */ +#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */ +#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */ +#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */ +#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ +#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ +#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ #define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */ -#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ -#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */ +#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ +#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */ /* Unused 0x28 - 0x2f */ -#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */ +#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */ /* Unused 0x31 - 0x33 */ -#define EC_MEMMAP_HOST_EVENTS 0x34 /* 32 bits */ -/* Reserve 0x38 - 0x3f for additional host event-related stuff */ -/* Battery values are all 32 bits */ -#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ -#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ -#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ -#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, defined below */ -#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ -#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ -#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ -#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ +#define EC_MEMMAP_HOST_EVENTS 0x34 /* 64 bits */ +/* Battery values are all 32 bits, unless otherwise noted. */ +#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ +#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ +#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ +#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, see below (8-bit) */ +#define EC_MEMMAP_BATT_COUNT 0x4d /* Battery Count (8-bit) */ +#define EC_MEMMAP_BATT_INDEX 0x4e /* Current Battery Data Index (8-bit) */ +/* Unused 0x4f */ +#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ +#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ +#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ +#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ /* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */ -#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ -#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ -#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ -#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ -#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */ +#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ +#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ +#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ +#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ +#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */ /* Unused 0x84 - 0x8f */ -#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ +#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ /* Unused 0x91 */ -#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */ +#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */ /* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */ /* 0x94 - 0x99: 1st Accelerometer */ /* 0x9a - 0x9f: 2nd Accelerometer */ -#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ -/* Unused 0xa6 - 0xdf */ + +#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ +#define EC_MEMMAP_GPU 0xa6 /* GPU-specific, 8 bits */ + +/* + * Bit fields for EC_MEMMAP_GPU + * 0:2: D-Notify level (0:D1, ... 4:D5) + * 3: Over temperature + */ +#define EC_MEMMAP_GPU_D_NOTIFY_MASK GENMASK(2, 0) +#define EC_MEMMAP_GPU_OVERT_BIT BIT(3) + +/* Power Participant related components */ +#define EC_MEMMAP_PWR_SRC 0xa7 /* Power source (8-bit) */ +/* Unused 0xa8 - 0xdf */ /* * ACPI is unable to access memory mapped data at or above this offset due to @@ -128,76 +214,101 @@ #define EC_MEMMAP_NO_ACPI 0xe0 /* Define the format of the accelerometer mapped memory status byte. */ -#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f -#define EC_MEMMAP_ACC_STATUS_BUSY_BIT (1 << 4) -#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT (1 << 7) +#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f +#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4) +#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7) /* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ -#define EC_TEMP_SENSOR_ENTRIES 16 +#define EC_TEMP_SENSOR_ENTRIES 16 /* * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B. * * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2. */ -#define EC_TEMP_SENSOR_B_ENTRIES 8 +#define EC_TEMP_SENSOR_B_ENTRIES 8 + +/* Max temp sensor entries for host commands */ +#define EC_MAX_TEMP_SENSOR_ENTRIES \ + (EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES) /* Special values for mapped temperature sensors */ -#define EC_TEMP_SENSOR_NOT_PRESENT 0xff -#define EC_TEMP_SENSOR_ERROR 0xfe -#define EC_TEMP_SENSOR_NOT_POWERED 0xfd +#define EC_TEMP_SENSOR_NOT_PRESENT 0xff +#define EC_TEMP_SENSOR_ERROR 0xfe +#define EC_TEMP_SENSOR_NOT_POWERED 0xfd #define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc /* * The offset of temperature value stored in mapped memory. This allows * reporting a temperature range of 200K to 454K = -73C to 181C. */ -#define EC_TEMP_SENSOR_OFFSET 200 +#define EC_TEMP_SENSOR_OFFSET 200 /* * Number of ALS readings at EC_MEMMAP_ALS */ -#define EC_ALS_ENTRIES 2 +#define EC_ALS_ENTRIES 2 /* * The default value a temperature sensor will return when it is present but * has not been read this boot. This is a reasonable number to avoid * triggering alarms on the host. */ -#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET) +#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET) -#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ -#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ -#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ +#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ +#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ + +/* Report 0 for fan stalled so userspace applications can take + * an appropriate action based on this value to control the fan. + */ +#define EC_FAN_SPEED_STALLED 0x0 +/* This should be used only for ectool to support old ECs. */ +#define EC_FAN_SPEED_STALLED_DEPRECATED 0xfffe /* Battery bit flags at EC_MEMMAP_BATT_FLAG. */ -#define EC_BATT_FLAG_AC_PRESENT 0x01 +#define EC_BATT_FLAG_AC_PRESENT 0x01 #define EC_BATT_FLAG_BATT_PRESENT 0x02 -#define EC_BATT_FLAG_DISCHARGING 0x04 -#define EC_BATT_FLAG_CHARGING 0x08 +#define EC_BATT_FLAG_DISCHARGING 0x04 +#define EC_BATT_FLAG_CHARGING 0x08 #define EC_BATT_FLAG_LEVEL_CRITICAL 0x10 +/* Set if some of the static/dynamic data is invalid (or outdated). */ +#define EC_BATT_FLAG_INVALID_DATA 0x20 +#define EC_BATT_FLAG_CUT_OFF 0x40 + +/* + * Value written to EC_MEMMAP_BATT_DCAP, EC_MEMMAP_BATT_DVLT, EC_MEMMAP_CCNT, + * EC_MEMMAP_BATT_VOLT, EC_MEMMAP_BATT_RATE, EC_MEMMAP_BATT_CAP, and + * EC_MEMMAP_BATT_LFCC if the actual value is unknown. + * + * This corresponds with the unknown value specified by ACPI release 6.5 + * Section 10.2.2 (and earlier versions), to match expectations of ACPI + * firmware. + */ +#define EC_MEMMAP_BATT_UNKNOWN_VALUE (-1) /* Switch flags at EC_MEMMAP_SWITCHES */ -#define EC_SWITCH_LID_OPEN 0x01 -#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 -#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 +#define EC_SWITCH_LID_OPEN 0x01 +#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 +/* Was write protect disabled; now unused. */ +#define EC_SWITCH_IGNORE2 0x04 /* Was recovery requested via keyboard; now unused. */ -#define EC_SWITCH_IGNORE1 0x08 +#define EC_SWITCH_IGNORE1 0x08 /* Recovery requested via dedicated signal (from servo board) */ -#define EC_SWITCH_DEDICATED_RECOVERY 0x10 +#define EC_SWITCH_DEDICATED_RECOVERY 0x10 /* Was fake developer mode switch; now unused. Remove in next refactor. */ -#define EC_SWITCH_IGNORE0 0x20 +#define EC_SWITCH_IGNORE0 0x20 /* Host command interface flags */ /* Host command interface supports LPC args (LPC interface only) */ -#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 +#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 /* Host command interface supports version 3 protocol */ -#define EC_HOST_CMD_FLAG_VERSION_3 0x02 +#define EC_HOST_CMD_FLAG_VERSION_3 0x02 /* Wireless switch flags */ -#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */ -#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */ -#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */ -#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ -#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ +#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */ +#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */ +#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */ +#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ +#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ /*****************************************************************************/ /* @@ -265,19 +376,19 @@ /* Valid addresses in ACPI memory space, for read/write commands */ /* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ -#define EC_ACPI_MEM_VERSION 0x00 +#define EC_ACPI_MEM_VERSION 0x00 /* * Test location; writing value here updates test compliment byte to (0xff - * value). */ -#define EC_ACPI_MEM_TEST 0x01 +#define EC_ACPI_MEM_TEST 0x01 /* Test compliment; writes here are ignored. */ -#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 +#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 /* Keyboard backlight brightness percent (0 - 100) */ #define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03 /* DPTF Target Fan Duty (0-100, 0xff for auto/none) */ -#define EC_ACPI_MEM_FAN_DUTY 0x04 +#define EC_ACPI_MEM_FAN_DUTY 0x04 /* * DPTF temp thresholds. Any of the EC's temp sensors can have up to two @@ -294,17 +405,17 @@ * have tripped". Setting or enabling the thresholds for a sensor will clear * the unread event count for that sensor. */ -#define EC_ACPI_MEM_TEMP_ID 0x05 -#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 -#define EC_ACPI_MEM_TEMP_COMMIT 0x07 +#define EC_ACPI_MEM_TEMP_ID 0x05 +#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 +#define EC_ACPI_MEM_TEMP_COMMIT 0x07 /* * Here are the bits for the COMMIT register: * bit 0 selects the threshold index for the chosen sensor (0/1) * bit 1 enables/disables the selected threshold (0 = off, 1 = on) * Each write to the commit register affects one threshold. */ -#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK (1 << 0) -#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK (1 << 1) +#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK BIT(0) +#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK BIT(1) /* * Example: * @@ -321,26 +432,179 @@ */ /* DPTF battery charging current limit */ -#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 +#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 /* Charging limit is specified in 64 mA steps */ -#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 +#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 /* Value to disable DPTF battery charging limit */ -#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff +#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff /* * Report device orientation - * bit 0 device is tablet mode + * Bits Definition + * 4 Off Body/On Body status: 0 = Off Body. + * 3:1 Device DPTF Profile Number (DDPN) + * 0 = Reserved for backward compatibility (indicates no valid + * profile number. Host should fall back to using TBMD). + * 1..7 = DPTF Profile number to indicate to host which table needs + * to be loaded. + * 0 Tablet Mode Device Indicator (TBMD) */ #define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09 -#define EC_ACPI_MEM_DEVICE_TABLET_MODE 0x01 +#define EC_ACPI_MEM_TBMD_SHIFT 0 +#define EC_ACPI_MEM_TBMD_MASK 0x1 +#define EC_ACPI_MEM_DDPN_SHIFT 1 +#define EC_ACPI_MEM_DDPN_MASK 0x7 +#define EC_ACPI_MEM_STTB_SHIFT 4 +#define EC_ACPI_MEM_STTB_MASK 0x1 + +/* + * Report device features. Uses the same format as the host command, except: + * + * bit 0 (EC_FEATURE_LIMITED) changes meaning from "EC code has a limited set + * of features", which is of limited interest when the system is already + * interpreting ACPI bytecode, to "EC_FEATURES[0-7] is not supported". Since + * these are supported, it defaults to 0. + * This allows detecting the presence of this field since older versions of + * the EC codebase would simply return 0xff to that unknown address. Check + * FEATURES0 != 0xff (or FEATURES0[0] == 0) to make sure that the other bits + * are valid. + */ +#define EC_ACPI_MEM_DEVICE_FEATURES0 0x0a +#define EC_ACPI_MEM_DEVICE_FEATURES1 0x0b +#define EC_ACPI_MEM_DEVICE_FEATURES2 0x0c +#define EC_ACPI_MEM_DEVICE_FEATURES3 0x0d +#define EC_ACPI_MEM_DEVICE_FEATURES4 0x0e +#define EC_ACPI_MEM_DEVICE_FEATURES5 0x0f +#define EC_ACPI_MEM_DEVICE_FEATURES6 0x10 +#define EC_ACPI_MEM_DEVICE_FEATURES7 0x11 + +#define EC_ACPI_MEM_BATTERY_INDEX 0x12 + +/* + * USB Port Power. Each bit indicates whether the corresponding USB ports' power + * is enabled (1) or disabled (0). + * bit 0 USB port ID 0 + * ... + * bit 7 USB port ID 7 + */ +#define EC_ACPI_MEM_USB_PORT_POWER 0x13 + +/* + * USB Retimer firmware update. + * Read: + * Result of last operation AP requested + * Write: + * bits[3:0]: USB-C port number + * bits[7:4]: Operation requested by AP + * + * NDA (no device attached) case: + * To update retimer firmware, AP needs set up TBT Alt mode. + * AP requests operations in this sequence: + * 1. Get port information about which ports support retimer firmware update. + * In the query result, each bit represents one port. + * 2. Get current MUX mode, it's NDA. + * 3. Suspend specified PD port's task. + * 4. AP requests EC to enter USB mode -> enter Safe mode -> enter TBT mode -> + * update firmware -> disconnect MUX -> resume PD task. + * + * DA (device attached) cases: + * Retimer firmware update is not supported in DA cases. + * 1. Get port information about which ports support retimer firmware update + * 2. Get current MUX mode, it's DA. + * 3. AP continues. No more retimer firmware update activities. + * + */ +#define EC_ACPI_MEM_USB_RETIMER_FW_UPDATE 0x14 + +#define USB_RETIMER_FW_UPDATE_OP_SHIFT 4 +#define USB_RETIMER_FW_UPDATE_ERR 0xfe +#define USB_RETIMER_FW_UPDATE_INVALID_MUX 0xff +/* Mask to clear unused MUX bits in retimer firmware update */ +#define USB_RETIMER_FW_UPDATE_MUX_MASK \ + (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \ + USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \ + USB_PD_MUX_USB4_ENABLED) + +/* Retimer firmware update operations */ +#define USB_RETIMER_FW_UPDATE_QUERY_PORT 0 /* Which ports has retimer */ +#define USB_RETIMER_FW_UPDATE_SUSPEND_PD 1 /* Suspend PD port */ +#define USB_RETIMER_FW_UPDATE_RESUME_PD 2 /* Resume PD port */ +#define USB_RETIMER_FW_UPDATE_GET_MUX 3 /* Read current USB MUX */ +#define USB_RETIMER_FW_UPDATE_SET_USB 4 /* Set MUX to USB mode */ +#define USB_RETIMER_FW_UPDATE_SET_SAFE 5 /* Set MUX to Safe mode */ +#define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode */ +#define USB_RETIMER_FW_UPDATE_DISCONNECT 7 /* Set MUX to disconnect */ + +#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x) & 0x0f) +#define EC_ACPI_MEM_USB_RETIMER_OP(x) \ + (((x) & 0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT) + +/* + * Offset 0x15 is reserved for PBOK, added to coreboot in + * https://crrev.com/c/3840943 and proposed for inclusion here + * in https://crrev.com/c/3547317. + */ + +/* + * Get extended strings from the EC. + * Write: + * String index, or 0 to probe for EC support. + * Read: + * String bytes, following by repeating null bytes. + * + * Writing a byte (EC_ACPI_MEM_STRINGS_FIFO_ID_*) selects a string, and the + * following reads return the non-null bytes of the string in sequence until + * the end of the string is reached. After the end of the string, reads 0 until + * another byte is written. This interface allows ACPI firmware to read longer + * strings from the EC than can reasonably fit into the shared memory region. + * + * To probe for EC support, write FIFO_ID_VERSION and read will return at least + * one nonzero (MEM_STRINGS_FIFO_V1 for example) if MEM_STRINGS_FIFO is + * supported. Returned values will indicate which strings are supported. If the + * first byte is 0xff, the strings FIFO is unsupported. + */ +#define EC_ACPI_MEM_STRINGS_FIFO 0x16 + +/* String index to probe EC support. */ +#define EC_ACPI_MEM_STRINGS_FIFO_ID_VERSION 0 +#define EC_ACPI_MEM_STRINGS_FIFO_V1 1 +/* + * 0xff is the value the EC returns for unimplemented reads, indicating + * the current EC firmware does not implement this command. + */ +#define EC_ACPI_MEM_STRINGS_FIFO_UNSUPPORTED 0xff + +/* + * Battery model number for the selected battery. Supported since V1. + * Presents the same data as EC_MEMMAP_BATT_MODEL, but can provide more + * than 8 bytes. + * + * This and the other FIFO_ID_BATTERY strings can select one of multiple + * batteries by changing the value at EC_MEMMAP_BATT_INDEX. Once that index + * is changed, reads of these strings will return information for the + * corresponding battery, if present. + */ +#define EC_ACPI_MEM_STRINGS_FIFO_ID_BATTERY_MODEL 1 +/* + * Battery serial number for the selected battery. Supported since V1. + * Presents the same data as EC_MEMMAP_BATT_SERIAL, but can provide more + * than 8 bytes. + */ +#define EC_ACPI_MEM_STRINGS_FIFO_ID_BATTERY_SERIAL 2 +/* + * Battery manufacturer for the selected battery. Supported since V1. + * Presents the same data as EC_MEMMAP_BATT_MFGR, but can provide more + * than 8 bytes. + */ +#define EC_ACPI_MEM_STRINGS_FIFO_ID_BATTERY_MANUFACTURER 3 /* * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf. This data * is read-only from the AP. Added in EC_ACPI_MEM_VERSION 2. */ -#define EC_ACPI_MEM_MAPPED_BEGIN 0x20 -#define EC_ACPI_MEM_MAPPED_SIZE 0xe0 +#define EC_ACPI_MEM_MAPPED_BEGIN 0x20 +#define EC_ACPI_MEM_MAPPED_SIZE 0xe0 /* Current version of ACPI memory address space */ #define EC_ACPI_MEM_VERSION_CURRENT 2 @@ -352,6 +616,7 @@ */ #ifndef __ACPI__ +#ifndef __KERNEL__ /* * Define __packed if someone hasn't beat us to it. Linux kernel style * checking prefers __packed over __attribute__((packed)). @@ -363,6 +628,7 @@ #ifndef __aligned #define __aligned(x) __attribute__((aligned(x))) #endif +#endif /* __KERNEL__ */ /* * Attributes for EC request and response packets. Just defining __packed @@ -376,7 +642,7 @@ * parent structure that the alignment will still be true given the packing of * the parent structure. This is particularly important if the sub-structure * will be passed as a pointer to another function, since that function will - * not know about the misaligment caused by the parent structure's packing. + * not know about the misalignment caused by the parent structure's packing. * * Also be very careful using __packed - particularly when nesting non-packed * structures inside packed ones. In fact, DO NOT use __packed directly; @@ -429,7 +695,7 @@ #define __ec_todo_packed __packed #define __ec_todo_unpacked -#else /* !CONFIG_HOSTCMD_ALIGNED */ +#else /* !CONFIG_HOSTCMD_ALIGNED */ /* * Packed structures make no assumption about alignment, so they do inefficient @@ -444,25 +710,25 @@ #define __ec_todo_packed __packed #define __ec_todo_unpacked -#endif /* !CONFIG_HOSTCMD_ALIGNED */ +#endif /* !CONFIG_HOSTCMD_ALIGNED */ /* LPC command status byte masks */ /* EC has written a byte in the data register and host hasn't read it yet */ -#define EC_LPC_STATUS_TO_HOST 0x01 +#define EC_LPC_STATUS_TO_HOST 0x01 /* Host has written a command/data byte and the EC hasn't read it yet */ -#define EC_LPC_STATUS_FROM_HOST 0x02 +#define EC_LPC_STATUS_FROM_HOST 0x02 /* EC is processing a command */ -#define EC_LPC_STATUS_PROCESSING 0x04 +#define EC_LPC_STATUS_PROCESSING 0x04 /* Last write to EC was a command, not data */ -#define EC_LPC_STATUS_LAST_CMD 0x08 +#define EC_LPC_STATUS_LAST_CMD 0x08 /* EC is in burst mode */ -#define EC_LPC_STATUS_BURST_MODE 0x10 +#define EC_LPC_STATUS_BURST_MODE 0x10 /* SCI event is pending (requesting SCI query) */ #define EC_LPC_STATUS_SCI_PENDING 0x20 /* SMI event is pending (requesting SMI query) */ #define EC_LPC_STATUS_SMI_PENDING 0x40 /* (reserved) */ -#define EC_LPC_STATUS_RESERVED 0x80 +#define EC_LPC_STATUS_RESERVED 0x80 /* * EC is busy. This covers both the EC processing a command, and the host has @@ -471,8 +737,8 @@ #define EC_LPC_STATUS_BUSY_MASK \ (EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING) -/* Host command response codes (16-bit). Note that response codes should be - * stored in a uint16_t rather than directly in a value of this type. +/* + * Host command response codes (16-bit). */ enum ec_status { EC_RES_SUCCESS = 0, @@ -483,25 +749,112 @@ enum ec_status { EC_RES_INVALID_RESPONSE = 5, EC_RES_INVALID_VERSION = 6, EC_RES_INVALID_CHECKSUM = 7, - EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */ - EC_RES_UNAVAILABLE = 9, /* No response available */ - EC_RES_TIMEOUT = 10, /* We got a timeout */ - EC_RES_OVERFLOW = 11, /* Table / data overflow */ - EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ - EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ - EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */ - EC_RES_BUS_ERROR = 15, /* Communications bus error */ - EC_RES_BUSY = 16 /* Up but too busy. Should retry */ -}; + EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */ + EC_RES_UNAVAILABLE = 9, /* No response available */ + EC_RES_TIMEOUT = 10, /* We got a timeout */ + EC_RES_OVERFLOW = 11, /* Table / data overflow */ + EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ + EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ + EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */ + EC_RES_BUS_ERROR = 15, /* Communications bus error */ + EC_RES_BUSY = 16, /* Up but too busy. Should retry */ + EC_RES_INVALID_HEADER_VERSION = 17, /* Header version invalid */ + EC_RES_INVALID_HEADER_CRC = 18, /* Header CRC invalid */ + EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */ + EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */ + + EC_RES_COUNT, + + EC_RES_MAX = UINT16_MAX, /**< Force enum to be 16 bits */ +} __packed; +BUILD_ASSERT(sizeof(enum ec_status) == sizeof(uint16_t)); +#ifdef CONFIG_EC_HOST_CMD +#ifdef CONFIG_ZEPHYR +/* + * Make sure Zephyre uses the same status codes. + */ +#include +#endif + +BUILD_ASSERT((uint16_t)EC_RES_SUCCESS == (uint16_t)EC_HOST_CMD_SUCCESS); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_COMMAND == + (uint16_t)EC_HOST_CMD_INVALID_COMMAND); +BUILD_ASSERT((uint16_t)EC_RES_ERROR == (uint16_t)EC_HOST_CMD_ERROR); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_PARAM == + (uint16_t)EC_HOST_CMD_INVALID_PARAM); +BUILD_ASSERT((uint16_t)EC_RES_ACCESS_DENIED == + (uint16_t)EC_HOST_CMD_ACCESS_DENIED); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_RESPONSE == + (uint16_t)EC_HOST_CMD_INVALID_RESPONSE); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_VERSION == + (uint16_t)EC_HOST_CMD_INVALID_VERSION); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_CHECKSUM == + (uint16_t)EC_HOST_CMD_INVALID_CHECKSUM); +BUILD_ASSERT((uint16_t)EC_RES_IN_PROGRESS == (uint16_t)EC_HOST_CMD_IN_PROGRESS); +BUILD_ASSERT((uint16_t)EC_RES_UNAVAILABLE == (uint16_t)EC_HOST_CMD_UNAVAILABLE); +BUILD_ASSERT((uint16_t)EC_RES_TIMEOUT == (uint16_t)EC_HOST_CMD_TIMEOUT); +BUILD_ASSERT((uint16_t)EC_RES_OVERFLOW == (uint16_t)EC_HOST_CMD_OVERFLOW); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_HEADER == + (uint16_t)EC_HOST_CMD_INVALID_HEADER); +BUILD_ASSERT((uint16_t)EC_RES_REQUEST_TRUNCATED == + (uint16_t)EC_HOST_CMD_REQUEST_TRUNCATED); +BUILD_ASSERT((uint16_t)EC_RES_RESPONSE_TOO_BIG == + (uint16_t)EC_HOST_CMD_RESPONSE_TOO_BIG); +BUILD_ASSERT((uint16_t)EC_RES_BUS_ERROR == (uint16_t)EC_HOST_CMD_BUS_ERROR); +BUILD_ASSERT((uint16_t)EC_RES_BUSY == (uint16_t)EC_HOST_CMD_BUSY); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_HEADER_VERSION == + (uint16_t)EC_HOST_CMD_INVALID_HEADER_VERSION); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_HEADER_CRC == + (uint16_t)EC_HOST_CMD_INVALID_HEADER_CRC); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_DATA_CRC == + (uint16_t)EC_HOST_CMD_INVALID_DATA_CRC); +BUILD_ASSERT((uint16_t)EC_RES_DUP_UNAVAILABLE == + (uint16_t)EC_HOST_CMD_DUP_UNAVAILABLE); +BUILD_ASSERT((uint16_t)EC_RES_MAX == (uint16_t)EC_HOST_CMD_MAX); + +#endif + +/* clang-format off */ +#define EC_STATUS_TEXT \ + { \ + EC_MAP_ITEM(EC_RES_SUCCESS, SUCCESS), \ + EC_MAP_ITEM(EC_RES_INVALID_COMMAND, INVALID_COMMAND), \ + EC_MAP_ITEM(EC_RES_ERROR, ERROR), \ + EC_MAP_ITEM(EC_RES_INVALID_PARAM, INVALID_PARAM), \ + EC_MAP_ITEM(EC_RES_ACCESS_DENIED, ACCESS_DENIED), \ + EC_MAP_ITEM(EC_RES_INVALID_RESPONSE, INVALID_RESPONSE), \ + EC_MAP_ITEM(EC_RES_INVALID_VERSION, INVALID_VERSION), \ + EC_MAP_ITEM(EC_RES_INVALID_CHECKSUM, INVALID_CHECKSUM), \ + EC_MAP_ITEM(EC_RES_IN_PROGRESS, IN_PROGRESS), \ + EC_MAP_ITEM(EC_RES_UNAVAILABLE, UNAVAILABLE), \ + EC_MAP_ITEM(EC_RES_TIMEOUT, TIMEOUT), \ + EC_MAP_ITEM(EC_RES_OVERFLOW, OVERFLOW), \ + EC_MAP_ITEM(EC_RES_INVALID_HEADER, INVALID_HEADER), \ + EC_MAP_ITEM(EC_RES_REQUEST_TRUNCATED, REQUEST_TRUNCATED), \ + EC_MAP_ITEM(EC_RES_RESPONSE_TOO_BIG, RESPONSE_TOO_BIG), \ + EC_MAP_ITEM(EC_RES_BUS_ERROR, BUS_ERROR), \ + EC_MAP_ITEM(EC_RES_BUSY, BUSY), \ + EC_MAP_ITEM(EC_RES_INVALID_HEADER_VERSION, INVALID_HEADER_VERSION), \ + EC_MAP_ITEM(EC_RES_INVALID_HEADER_CRC, INVALID_HEADER_CRC), \ + EC_MAP_ITEM(EC_RES_INVALID_DATA_CRC, INVALID_DATA_CRC), \ + EC_MAP_ITEM(EC_RES_DUP_UNAVAILABLE, DUP_UNAVAILABLE), \ + } +/* clang-format on */ + +#ifndef __cplusplus +#define EC_MAP_ITEM(k, v) [k] = #v +BUILD_ASSERT(ARRAY_SIZE(((const char *[])EC_STATUS_TEXT)) == EC_RES_COUNT); +#undef EC_MAP_ITEM +#endif /* - * Host event codes. Note these are 1-based, not 0-based, because ACPI query - * EC command uses code 0 to mean "no event pending". We explicitly specify - * each value in the enum listing so they won't change if we delete/insert an - * item or rearrange the list (it needs to be stable across platforms, not - * just within a single compiled instance). + * Host event codes. ACPI query EC command uses code 0 to mean "no event + * pending". We explicitly specify each value in the enum listing so they won't + * change if we delete/insert an item or rearrange the list (it needs to be + * stable across platforms, not just within a single compiled instance). */ enum host_event_code { + EC_HOST_EVENT_NONE = 0, EC_HOST_EVENT_LID_CLOSED = 1, EC_HOST_EVENT_LID_OPEN = 2, EC_HOST_EVENT_POWER_BUTTON = 3, @@ -514,7 +867,8 @@ enum host_event_code { /* Event generated by a device attached to the EC */ EC_HOST_EVENT_DEVICE = 10, EC_HOST_EVENT_THERMAL = 11, - EC_HOST_EVENT_USB_CHARGER = 12, + /* GPU related event. Formerly named EC_HOST_EVENT_USB_CHARGER. */ + EC_HOST_EVENT_GPU = 12, EC_HOST_EVENT_KEY_PRESSED = 13, /* * EC has finished initializing the host interface. The host can check @@ -561,17 +915,20 @@ enum host_event_code { /* EC desires to change state of host-controlled USB mux */ EC_HOST_EVENT_USB_MUX = 28, - /* TABLET/LAPTOP mode event*/ + /* + * The device has changed "modes". This can be one of the following: + * + * - TABLET/LAPTOP mode + * - detachable base attach/detach event + * - on body/off body transition event + */ EC_HOST_EVENT_MODE_CHANGE = 29, /* Keyboard recovery combo with hardware reinitialization */ EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT = 30, - /* - * Reserve this last bit to indicate that at least one bit in a - * secondary host event word is set. See crbug.com/633646. - */ - EC_HOST_EVENT_EXTENDED = 31, + /* WoV */ + EC_HOST_EVENT_WOV = 31, /* * The high bit of the event mask is not used as a host event code. If @@ -580,22 +937,79 @@ enum host_event_code { * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is * not initialized on the EC, or improperly configured on the host. */ - EC_HOST_EVENT_INVALID = 32 + EC_HOST_EVENT_INVALID = 32, + + /* Body detect (lap/desk) change event */ + EC_HOST_EVENT_BODY_DETECT_CHANGE = 33, + + /* New console logs since last snapshot */ + EC_HOST_EVENT_CONSOLE_LOGS = 34, + + /* + * Only 64 host events are supported. This enum uses 1-based counting so + * it can skip 0 (NONE), so the last legal host event number is 64. + */ }; -/* Host event mask */ -#define EC_HOST_EVENT_MASK(event_code) (1ULL << ((event_code) - 1)) -/* Arguments at EC_LPC_ADDR_HOST_ARGS */ -struct __ec_align4 ec_lpc_host_args { +/* Host event mask */ +#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1) + +/* clang-format off */ +#define HOST_EVENT_TEXT \ + { \ + [EC_HOST_EVENT_NONE] = "NONE", \ + [EC_HOST_EVENT_LID_CLOSED] = "LID_CLOSED", \ + [EC_HOST_EVENT_LID_OPEN] = "LID_OPEN", \ + [EC_HOST_EVENT_POWER_BUTTON] = "POWER_BUTTON", \ + [EC_HOST_EVENT_AC_CONNECTED] = "AC_CONNECTED", \ + [EC_HOST_EVENT_AC_DISCONNECTED] = "AC_DISCONNECTED", \ + [EC_HOST_EVENT_BATTERY_LOW] = "BATTERY_LOW", \ + [EC_HOST_EVENT_BATTERY_CRITICAL] = "BATTERY_CRITICAL", \ + [EC_HOST_EVENT_BATTERY] = "BATTERY", \ + [EC_HOST_EVENT_THERMAL_THRESHOLD] = "THERMAL_THRESHOLD", \ + [EC_HOST_EVENT_DEVICE] = "DEVICE", \ + [EC_HOST_EVENT_THERMAL] = "THERMAL", \ + [EC_HOST_EVENT_GPU] = "GPU", \ + [EC_HOST_EVENT_KEY_PRESSED] = "KEY_PRESSED", \ + [EC_HOST_EVENT_INTERFACE_READY] = "INTERFACE_READY", \ + [EC_HOST_EVENT_KEYBOARD_RECOVERY] = "KEYBOARD_RECOVERY", \ + [EC_HOST_EVENT_THERMAL_SHUTDOWN] = "THERMAL_SHUTDOWN", \ + [EC_HOST_EVENT_BATTERY_SHUTDOWN] = "BATTERY_SHUTDOWN", \ + [EC_HOST_EVENT_THROTTLE_START] = "THROTTLE_START", \ + [EC_HOST_EVENT_THROTTLE_STOP] = "THROTTLE_STOP", \ + [EC_HOST_EVENT_HANG_DETECT] = "HANG_DETECT", \ + [EC_HOST_EVENT_HANG_REBOOT] = "HANG_REBOOT", \ + [EC_HOST_EVENT_PD_MCU] = "PD_MCU", \ + [EC_HOST_EVENT_BATTERY_STATUS] = "BATTERY_STATUS", \ + [EC_HOST_EVENT_PANIC] = "PANIC", \ + [EC_HOST_EVENT_KEYBOARD_FASTBOOT] = "KEYBOARD_FASTBOOT", \ + [EC_HOST_EVENT_RTC] = "RTC", \ + [EC_HOST_EVENT_MKBP] = "MKBP", \ + [EC_HOST_EVENT_USB_MUX] = "USB_MUX", \ + [EC_HOST_EVENT_MODE_CHANGE] = "MODE_CHANGE", \ + [EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT] = \ + "KEYBOARD_RECOVERY_HW_REINIT", \ + [EC_HOST_EVENT_WOV] = "WOV", \ + [EC_HOST_EVENT_INVALID] = "INVALID", \ + [EC_HOST_EVENT_BODY_DETECT_CHANGE] = "BODY_DETECT_CHANGE", \ + [EC_HOST_EVENT_CONSOLE_LOGS] = "CONSOLE_LOGS", \ + } +/* clang-format on */ + +/** + * struct ec_lpc_host_args - Arguments at EC_LPC_ADDR_HOST_ARGS + * @flags: The host argument flags. + * @command_version: Command version. + * @data_size: The length of data. + * @checksum: Checksum; sum of command + flags + command_version + data_size + + * all params/response data bytes. + */ +struct ec_lpc_host_args { uint8_t flags; uint8_t command_version; uint8_t data_size; - /* - * Checksum; sum of command + flags + command_version + data_size + - * all params/response data bytes. - */ uint8_t checksum; -}; +} __ec_align4; /* Flags for ec_lpc_host_args.flags */ /* @@ -615,7 +1029,7 @@ struct __ec_align4 ec_lpc_host_args { * response. Command version is 0 and response data from EC is at * EC_LPC_ADDR_OLD_PARAM with unknown length. */ -#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 +#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 /*****************************************************************************/ /* @@ -657,48 +1071,52 @@ struct __ec_align4 ec_lpc_host_args { * request, the AP will clock in bytes until it sees the framing byte, then * clock in the response packet. */ -#define EC_SPI_FRAME_START 0xec +#define EC_SPI_FRAME_START 0xec /* * Padding bytes which are clocked out after the end of a response packet. */ -#define EC_SPI_PAST_END 0xed +#define EC_SPI_PAST_END 0xed /* - * EC is ready to receive, and has ignored the byte sent by the AP. EC expects + * EC is ready to receive, and has ignored the byte sent by the AP. EC expects * that the AP will send a valid packet header (starting with * EC_COMMAND_PROTOCOL_3) in the next 32 bytes. + * + * NOTE: Some SPI configurations place the Most Significant Bit on SDO when + * CS goes low. This macro has the Most Significant Bit set to zero, + * so SDO will not be driven high when CS goes low. */ -#define EC_SPI_RX_READY 0xf8 +#define EC_SPI_RX_READY 0x78 /* * EC has started receiving the request from the AP, but hasn't started * processing it yet. */ -#define EC_SPI_RECEIVING 0xf9 +#define EC_SPI_RECEIVING 0xf9 /* EC has received the entire request from the AP and is processing it. */ -#define EC_SPI_PROCESSING 0xfa +#define EC_SPI_PROCESSING 0xfa /* * EC received bad data from the AP, such as a packet header with an invalid * length. EC will ignore all data until chip select deasserts. */ -#define EC_SPI_RX_BAD_DATA 0xfb +#define EC_SPI_RX_BAD_DATA 0xfb /* * EC received data from the AP before it was ready. That is, the AP asserted * chip select and started clocking data before the EC was ready to receive it. * EC will ignore all data until chip select deasserts. */ -#define EC_SPI_NOT_READY 0xfc +#define EC_SPI_NOT_READY 0xfc /* * EC was ready to receive a request from the AP. EC has treated the byte sent * by the AP as part of a request packet, or (for old-style ECs) is processing * a fully received packet but is not ready to respond yet. */ -#define EC_SPI_OLD_READY 0xfd +#define EC_SPI_OLD_READY 0xfd /*****************************************************************************/ @@ -720,22 +1138,22 @@ struct __ec_align4 ec_lpc_host_args { */ #define EC_PROTO2_REQUEST_HEADER_BYTES 3 #define EC_PROTO2_REQUEST_TRAILER_BYTES 1 -#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \ - EC_PROTO2_REQUEST_TRAILER_BYTES) +#define EC_PROTO2_REQUEST_OVERHEAD \ + (EC_PROTO2_REQUEST_HEADER_BYTES + EC_PROTO2_REQUEST_TRAILER_BYTES) #define EC_PROTO2_RESPONSE_HEADER_BYTES 2 #define EC_PROTO2_RESPONSE_TRAILER_BYTES 1 -#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \ - EC_PROTO2_RESPONSE_TRAILER_BYTES) +#define EC_PROTO2_RESPONSE_OVERHEAD \ + (EC_PROTO2_RESPONSE_HEADER_BYTES + EC_PROTO2_RESPONSE_TRAILER_BYTES) /* Parameter length was limited by the LPC interface */ #define EC_PROTO2_MAX_PARAM_SIZE 0xfc /* Maximum request and response packet sizes for protocol version 2 */ -#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \ - EC_PROTO2_MAX_PARAM_SIZE) -#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \ - EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_REQUEST_SIZE \ + (EC_PROTO2_REQUEST_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_RESPONSE_SIZE \ + (EC_PROTO2_RESPONSE_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE) /*****************************************************************************/ @@ -747,56 +1165,175 @@ struct __ec_align4 ec_lpc_host_args { #define EC_HOST_REQUEST_VERSION 3 -/* Version 3 request from host */ -struct __ec_align4 ec_host_request { - /* Structure version (=3) - * - * EC will return EC_RES_INVALID_HEADER if it receives a header with a - * version it doesn't know how to parse. - */ +/** + * struct ec_host_request - Version 3 request from host. + * @struct_version: Should be 3. The EC will return EC_RES_INVALID_HEADER if it + * receives a header with a version it doesn't know how to + * parse. + * @checksum: Checksum of request and data; sum of all bytes including checksum + * should total to 0. + * @command: Command to send (EC_CMD_...) + * @command_version: Command version. + * @reserved: Unused byte in current protocol version; set to 0. + * @data_len: Length of data which follows this header. + */ +struct ec_host_request { uint8_t struct_version; + uint8_t checksum; + uint16_t command; + uint8_t command_version; + uint8_t reserved; + uint16_t data_len; +} __ec_align4; + +#define EC_HOST_RESPONSE_VERSION 3 + +/** + * struct ec_host_response - Version 3 response from EC. + * @struct_version: Struct version (=3). + * @checksum: Checksum of response and data; sum of all bytes including + * checksum should total to 0. + * @result: EC's response to the command (separate from communication failure) + * @data_len: Length of data which follows this header. + * @reserved: Unused bytes in current protocol version; set to 0. + */ +struct ec_host_response { + uint8_t struct_version; + uint8_t checksum; + uint16_t result; + uint16_t data_len; + uint16_t reserved; +} __ec_align4; +/*****************************************************************************/ + +/* + * Host command protocol V4. + * + * Packets always start with a request or response header. They are followed + * by data_len bytes of data. If the data_crc_present flag is set, the data + * bytes are followed by a CRC-8 of that data, using x^8 + x^2 + x + 1 + * polynomial. + * + * Host algorithm when sending a request q: + * + * 101) tries_left=(some value, e.g. 3); + * 102) q.seq_num++ + * 103) q.seq_dup=0 + * 104) Calculate q.header_crc. + * 105) Send request q to EC. + * 106) Wait for response r. Go to 201 if received or 301 if timeout. + * + * 201) If r.struct_version != 4, go to 301. + * 202) If r.header_crc mismatches calculated CRC for r header, go to 301. + * 203) If r.data_crc_present and r.data_crc mismatches, go to 301. + * 204) If r.seq_num != q.seq_num, go to 301. + * 205) If r.seq_dup == q.seq_dup, return success. + * 207) If r.seq_dup == 1, go to 301. + * 208) Return error. + * + * 301) If --tries_left <= 0, return error. + * 302) If q.seq_dup == 1, go to 105. + * 303) q.seq_dup = 1 + * 304) Go to 104. + * + * EC algorithm when receiving a request q. + * EC has response buffer r, error buffer e. + * + * 101) If q.struct_version != 4, set e.result = EC_RES_INVALID_HEADER_VERSION + * and go to 301 + * 102) If q.header_crc mismatches calculated CRC, set e.result = + * EC_RES_INVALID_HEADER_CRC and go to 301 + * 103) If q.data_crc_present, calculate data CRC. If that mismatches the CRC + * byte at the end of the packet, set e.result = EC_RES_INVALID_DATA_CRC + * and go to 301. + * 104) If q.seq_dup == 0, go to 201. + * 105) If q.seq_num != r.seq_num, go to 201. + * 106) If q.seq_dup == r.seq_dup, go to 205, else go to 203. + * + * 201) Process request q into response r. + * 202) r.seq_num = q.seq_num + * 203) r.seq_dup = q.seq_dup + * 204) Calculate r.header_crc + * 205) If r.data_len > 0 and data is no longer available, set e.result = + * EC_RES_DUP_UNAVAILABLE and go to 301. + * 206) Send response r. + * + * 301) e.seq_num = q.seq_num + * 302) e.seq_dup = q.seq_dup + * 303) Calculate e.header_crc. + * 304) Send error response e. + */ + +/* Version 4 request from host */ +struct ec_host_request4 { /* - * Checksum of request and data; sum of all bytes including checksum - * should total to 0. + * bits 0-3: struct_version: Structure version (=4) + * bit 4: is_response: Is response (=0) + * bits 5-6: seq_num: Sequence number + * bit 7: seq_dup: Sequence duplicate flag */ - uint8_t checksum; + uint8_t fields0; + + /* + * bits 0-4: command_version: Command version + * bits 5-6: Reserved (set 0, ignore on read) + * bit 7: data_crc_present: Is data CRC present after data + */ + uint8_t fields1; - /* Command code */ + /* Command code (EC_CMD_*) */ uint16_t command; - /* Command version */ - uint8_t command_version; + /* Length of data which follows this header (not including data CRC) */ + uint16_t data_len; - /* Unused byte in current protocol version; set to 0 */ + /* Reserved (set 0, ignore on read) */ uint8_t reserved; - /* Length of data which follows this header */ - uint16_t data_len; -}; - -#define EC_HOST_RESPONSE_VERSION 3 + /* CRC-8 of above fields, using x^8 + x^2 + x + 1 polynomial */ + uint8_t header_crc; +} __ec_align4; -/* Version 3 response from EC */ -struct __ec_align4 ec_host_response { - /* Structure version (=3) */ - uint8_t struct_version; +/* Version 4 response from EC */ +struct ec_host_response4 { + /* + * bits 0-3: struct_version: Structure version (=4) + * bit 4: is_response: Is response (=1) + * bits 5-6: seq_num: Sequence number + * bit 7: seq_dup: Sequence duplicate flag + */ + uint8_t fields0; /* - * Checksum of response and data; sum of all bytes including checksum - * should total to 0. + * bits 0-6: Reserved (set 0, ignore on read) + * bit 7: data_crc_present: Is data CRC present after data */ - uint8_t checksum; + uint8_t fields1; /* Result code (EC_RES_*) */ uint16_t result; - /* Length of data which follows this header */ + /* Length of data which follows this header (not including data CRC) */ uint16_t data_len; - /* Unused bytes in current protocol version; set to 0 */ - uint16_t reserved; -}; + /* Reserved (set 0, ignore on read) */ + uint8_t reserved; + + /* CRC-8 of above fields, using x^8 + x^2 + x + 1 polynomial */ + uint8_t header_crc; +} __ec_align4; + +/* Fields in fields0 byte */ +#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f +#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10 +#define EC_PACKET4_0_SEQ_NUM_SHIFT 5 +#define EC_PACKET4_0_SEQ_NUM_MASK 0x60 +#define EC_PACKET4_0_SEQ_DUP_MASK 0x80 + +/* Fields in fields1 byte */ +#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f /* (request only) */ +#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80 /*****************************************************************************/ /* @@ -822,9 +1359,13 @@ struct __ec_align4 ec_host_response { */ #define EC_CMD_PROTO_VERSION 0x0000 -struct __ec_align4 ec_response_proto_version { +/** + * struct ec_response_proto_version - Response to the proto version command. + * @version: The protocol version. + */ +struct ec_response_proto_version { uint32_t version; -}; +} __ec_align4; /* * Hello. This is a simple command to test the EC is responsive to @@ -832,43 +1373,72 @@ struct __ec_align4 ec_response_proto_version { */ #define EC_CMD_HELLO 0x0001 -struct __ec_align4 ec_params_hello { - uint32_t in_data; /* Pass anything here */ -}; +/** + * struct ec_params_hello - Parameters to the hello command. + * @in_data: Pass anything here. + */ +struct ec_params_hello { + uint32_t in_data; +} __ec_align4; -struct __ec_align4 ec_response_hello { - uint32_t out_data; /* Output will be in_data + 0x01020304 */ -}; +/** + * struct ec_response_hello - Response to the hello command. + * @out_data: Output will be in_data + 0x01020304. + */ +struct ec_response_hello { + uint32_t out_data; +} __ec_align4; /* Get version number */ #define EC_CMD_GET_VERSION 0x0002 -enum ec_current_image { +enum ec_image { EC_IMAGE_UNKNOWN = 0, EC_IMAGE_RO, - EC_IMAGE_RW -}; + EC_IMAGE_RW, + EC_IMAGE_RW_A = EC_IMAGE_RW, + EC_IMAGE_RO_B, + EC_IMAGE_RW_B, +}; + +/** + * struct ec_response_get_version - Response to the v0 get version command. + * @version_string_ro: Null-terminated RO firmware version string. + * @version_string_rw: Null-terminated RW firmware version string. + * @reserved: Unused bytes; was previously RW-B firmware version string. + * @current_image: One of ec_image. + */ +struct ec_response_get_version { + char version_string_ro[32]; + char version_string_rw[32]; + char reserved[32]; /* Changed to cros_fwid_ro in version 1 */ + uint32_t current_image; +} __ec_align4; -struct __ec_align4 ec_response_get_version { - /* Null-terminated version strings for RO, RW */ +/** + * struct ec_response_get_version_v1 - Response to the v1 get version command. + * + * ec_response_get_version_v1 is a strict superset of ec_response_get_version. + * The v1 response changes the semantics of one field (reserved to cros_fwid_ro) + * and adds one additional field (cros_fwid_rw). + * + * @version_string_ro: Null-terminated RO firmware version string. + * @version_string_rw: Null-terminated RW firmware version string. + * @cros_fwid_ro: Null-terminated RO CrOS FWID string. + * @current_image: One of ec_image. + * @cros_fwid_rw: Null-terminated RW CrOS FWID string. + */ +struct ec_response_get_version_v1 { char version_string_ro[32]; char version_string_rw[32]; - char reserved[32]; /* Was previously RW-B string */ - uint32_t current_image; /* One of ec_current_image */ -}; + char cros_fwid_ro[32]; /* Added in version 1 (Used to be reserved) */ + uint32_t current_image; + char cros_fwid_rw[32]; /* Added in version 1 */ +} __ec_align4; -/* Read test */ +/* Read test - OBSOLETE */ #define EC_CMD_READ_TEST 0x0003 -struct __ec_align4 ec_params_read_test { - uint32_t offset; /* Starting value for read buffer */ - uint32_t size; /* Size to read in bytes */ -}; - -struct __ec_align4 ec_response_read_test { - uint32_t data[32]; -}; - /* * Get build information * @@ -879,19 +1449,28 @@ struct __ec_align4 ec_response_read_test { /* Get chip info */ #define EC_CMD_GET_CHIP_INFO 0x0005 -struct __ec_align4 ec_response_get_chip_info { - /* Null-terminated strings */ +/** + * struct ec_response_get_chip_info - Response to the get chip info command. + * @vendor: Null-terminated string for chip vendor. + * @name: Null-terminated string for chip name. + * @revision: Null-terminated string for chip mask version. + */ +struct ec_response_get_chip_info { char vendor[32]; char name[32]; - char revision[32]; /* Mask version */ -}; + char revision[32]; +} __ec_align4; /* Get board HW version */ #define EC_CMD_GET_BOARD_VERSION 0x0006 -struct __ec_align2 ec_response_board_version { - uint16_t board_version; /* A monotonously incrementing number. */ -}; +/** + * struct ec_response_board_version - Response to the board version command. + * @board_version: A monotonously incrementing number. + */ +struct ec_response_board_version { + uint16_t board_version; +} __ec_align2; /* * Read memory-mapped data. @@ -903,29 +1482,44 @@ struct __ec_align2 ec_response_board_version { */ #define EC_CMD_READ_MEMMAP 0x0007 -struct __ec_align1 ec_params_read_memmap { - uint8_t offset; /* Offset in memmap (EC_MEMMAP_*) */ - uint8_t size; /* Size to read in bytes */ -}; +/** + * struct ec_params_read_memmap - Parameters for the read memory map command. + * @offset: Offset in memmap (EC_MEMMAP_*). + * @size: Size to read in bytes. + */ +struct ec_params_read_memmap { + uint8_t offset; + uint8_t size; +} __ec_align1; /* Read versions supported for a command */ #define EC_CMD_GET_CMD_VERSIONS 0x0008 -struct __ec_align1 ec_params_get_cmd_versions { - uint8_t cmd; /* Command to check */ -}; - -struct __ec_align2 ec_params_get_cmd_versions_v1 { - uint16_t cmd; /* Command to check */ -}; +/** + * struct ec_params_get_cmd_versions - Parameters for the get command versions. + * @cmd: Command to check. + */ +struct ec_params_get_cmd_versions { + uint8_t cmd; +} __ec_align1; -struct __ec_align4 ec_response_get_cmd_versions { - /* - * Mask of supported versions; use EC_VER_MASK() to compare with a - * desired version. - */ +/** + * struct ec_params_get_cmd_versions_v1 - Parameters for the get command + * versions (v1) + * @cmd: Command to check. + */ +struct ec_params_get_cmd_versions_v1 { + uint16_t cmd; +} __ec_align2; + +/** + * struct ec_response_get_cmd_version - Response to the get command versions. + * @version_mask: Mask of supported versions; use EC_VER_MASK() to compare with + * a desired version. + */ +struct ec_response_get_cmd_versions { uint32_t version_mask; -}; +} __ec_align4; /* * Check EC communications status (busy). This is needed on i2c/spi but not @@ -934,81 +1528,88 @@ struct __ec_align4 ec_response_get_cmd_versions { * lpc must read the status from the command register. Attempting this on * lpc will overwrite the args/parameter space and corrupt its data. */ -#define EC_CMD_GET_COMMS_STATUS 0x0009 +#define EC_CMD_GET_COMMS_STATUS 0x0009 /* Avoid using ec_status which is for return values */ enum ec_comms_status { - EC_COMMS_STATUS_PROCESSING = 1 << 0, /* Processing cmd */ + EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */ }; -struct __ec_align4 ec_response_get_comms_status { - uint32_t flags; /* Mask of enum ec_comms_status */ -}; +/** + * struct ec_response_get_comms_status - Response to the get comms status + * command. + * @flags: Mask of enum ec_comms_status. + */ +struct ec_response_get_comms_status { + uint32_t flags; /* Mask of enum ec_comms_status */ +} __ec_align4; /* Fake a variety of responses, purely for testing purposes. */ -#define EC_CMD_TEST_PROTOCOL 0x000A +#define EC_CMD_TEST_PROTOCOL 0x000A /* Tell the EC what to send back to us. */ -struct __ec_align4 ec_params_test_protocol { +struct ec_params_test_protocol { uint32_t ec_result; uint32_t ret_len; uint8_t buf[32]; -}; +} __ec_align4; /* Here it comes... */ -struct __ec_align4 ec_response_test_protocol { +struct ec_response_test_protocol { uint8_t buf[32]; -}; +} __ec_align4; /* Get protocol information */ -#define EC_CMD_GET_PROTOCOL_INFO 0x000B +#define EC_CMD_GET_PROTOCOL_INFO 0x000B /* Flags for ec_response_get_protocol_info.flags */ /* EC_RES_IN_PROGRESS may be returned if a command is slow */ -#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0) - -struct __ec_align4 ec_response_get_protocol_info { +#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED BIT(0) + +/** + * struct ec_response_get_protocol_info - Response to the get protocol info. + * @protocol_versions: Bitmask of protocol versions supported (1 << n means + * version n). + * @max_request_packet_size: Maximum request packet size in bytes. + * @max_response_packet_size: Maximum response packet size in bytes. + * @flags: see EC_PROTOCOL_INFO_* + */ +struct ec_response_get_protocol_info { /* Fields which exist if at least protocol version 3 supported */ - - /* Bitmask of protocol versions supported (1 << n means version n)*/ uint32_t protocol_versions; - - /* Maximum request packet size, in bytes */ uint16_t max_request_packet_size; - - /* Maximum response packet size, in bytes */ uint16_t max_response_packet_size; - - /* Flags; see EC_PROTOCOL_INFO_* */ uint32_t flags; -}; +} __ec_align4; /*****************************************************************************/ /* Get/Set miscellaneous values */ /* The upper byte of .flags tells what to do (nothing means "get") */ -#define EC_GSV_SET 0x80000000 +#define EC_GSV_SET 0x80000000 -/* The lower three bytes of .flags identifies the parameter, if that has - meaning for an individual command. */ +/* + * The lower three bytes of .flags identifies the parameter, if that has + * meaning for an individual command. + */ #define EC_GSV_PARAM_MASK 0x00ffffff -struct __ec_align4 ec_params_get_set_value { +struct ec_params_get_set_value { uint32_t flags; uint32_t value; -}; +} __ec_align4; -struct __ec_align4 ec_response_get_set_value { +struct ec_response_get_set_value { uint32_t flags; uint32_t value; -}; +} __ec_align4; /* More than one command can use these structs to get/set parameters. */ -#define EC_CMD_GSV_PAUSE_IN_S5 0x000C +#define EC_CMD_GSV_PAUSE_IN_S5 0x000C /*****************************************************************************/ /* List the features supported by the firmware */ -#define EC_CMD_GET_FEATURES 0x000D +#define EC_CMD_GET_FEATURES 0x000D /* Supported features */ enum ec_feature_code { @@ -1135,66 +1736,143 @@ enum ec_feature_code { * mux. */ EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43, -}; - -#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) -#define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32) - -struct ec_response_get_features { - uint32_t flags[2]; -} __ec_align4; - -/*****************************************************************************/ -/* Get the board's SKU ID from EC */ -#define EC_CMD_GET_SKU_ID 0x000E - -/* Set SKU ID from AP */ -#define EC_CMD_SET_SKU_ID 0x000F - -struct __ec_align4 ec_sku_id_info { - uint32_t sku_id; -}; - -/*****************************************************************************/ -/* Flash commands */ - -/* Get flash info */ -#define EC_CMD_FLASH_INFO 0x0010 -#define EC_VER_FLASH_INFO 2 - -/* Version 0 returns these fields */ -struct __ec_align4 ec_response_flash_info { - /* Usable flash size, in bytes */ - uint32_t flash_size; /* - * Write block size. Write offset and size must be a multiple - * of this. + * The EC supports entering and residing in S4. */ - uint32_t write_block_size; + EC_FEATURE_S4_RESIDENCY = 44, /* - * Erase block size. Erase offset and size must be a multiple - * of this. + * The EC supports the AP directing mux sets for the board. */ - uint32_t erase_block_size; + EC_FEATURE_TYPEC_AP_MUX_SET = 45, /* - * Protection block size. Protection offset and size must be a - * multiple of this. + * The EC supports the AP composing VDMs for us to send. */ - uint32_t protect_block_size; + EC_FEATURE_TYPEC_AP_VDM_SEND = 46, + /* + * The EC supports system safe mode panic recovery. + */ + EC_FEATURE_SYSTEM_SAFE_MODE = 47, + /* + * The EC will reboot on runtime assertion failures. + */ + EC_FEATURE_ASSERT_REBOOTS = 48, + /* + * The EC image is built with tokenized logging enabled. + */ + EC_FEATURE_TOKENIZED_LOGGING = 49, + /* + * The EC supports triggering an STB dump. + */ + EC_FEATURE_AMD_STB_DUMP = 50, + /* + * The EC supports memory dump commands. + */ + EC_FEATURE_MEMORY_DUMP = 51, + /* + * The EC supports DP2.1 capability + */ + EC_FEATURE_TYPEC_DP2_1 = 52, + /* + * The MCU is System Companion Processor Core 1 + */ + EC_FEATURE_SCP_C1 = 53, + /* + * The EC supports UCSI PPM. + */ + EC_FEATURE_UCSI_PPM = 54, + /* + * The EC supports Strauss keyboard. + */ + EC_FEATURE_STRAUSS = 55, + /* + * The EC supports PoE. + */ + EC_FEATURE_POE = 56, + /* + * The EC supports a hybrid boost charger + */ + EC_FEATURE_CHARGER_HYBRID_POWER_BOOST = 57, + /* + * Support signaling new console logs via host event + */ + EC_FEATURE_CONSOLE_LOG_EVENT = 58, }; -/* Flags for version 1+ flash info command */ -/* EC flash erases bits to 0 instead of 1 */ -#define EC_FLASH_INFO_ERASE_TO_0 (1 << 0) +#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) +#define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32) + +struct ec_response_get_features { + uint32_t flags[2]; +} __ec_align4; + +/*****************************************************************************/ +/* Get the board's SKU ID from EC */ +#define EC_CMD_GET_SKU_ID 0x000E + +/* Set SKU ID from AP */ +#define EC_CMD_SET_SKU_ID 0x000F + +struct ec_sku_id_info { + uint32_t sku_id; +} __ec_align4; + +/*****************************************************************************/ +/* Flash commands */ + +/* Get flash info */ +#define EC_CMD_FLASH_INFO 0x0010 +#define EC_VER_FLASH_INFO 2 + +/** + * struct ec_response_flash_info - Response to the flash info command. + * @flash_size: Usable flash size in bytes. + * @write_block_size: Write block size. Write offset and size must be a + * multiple of this. + * @erase_block_size: Erase block size. Erase offset and size must be a + * multiple of this. + * @protect_block_size: Protection block size. Protection offset and size + * must be a multiple of this. + * + * Version 0 returns these fields. + */ +struct ec_response_flash_info { + uint32_t flash_size; + uint32_t write_block_size; + uint32_t erase_block_size; + uint32_t protect_block_size; +} __ec_align4; + +/* + * Flags for version 1+ flash info command + * EC flash erases bits to 0 instead of 1. + */ +#define EC_FLASH_INFO_ERASE_TO_0 BIT(0) -/* Flash must be selected for read/write/erase operations to succeed. This may +/* + * Flash must be selected for read/write/erase operations to succeed. This may * be necessary on a chip where write/erase can be corrupted by other board * activity, or where the chip needs to enable some sort of programming voltage, * or where the read/write/erase operations require cleanly suspending other - * chip functionality. */ -#define EC_FLASH_INFO_SELECT_REQUIRED (1 << 1) - -/* + * chip functionality. + */ +#define EC_FLASH_INFO_SELECT_REQUIRED BIT(1) + +/** + * struct ec_response_flash_info_1 - Response to the flash info v1 command. + * @flash_size: Usable flash size in bytes. + * @write_block_size: Write block size. Write offset and size must be a + * multiple of this. + * @erase_block_size: Erase block size. Erase offset and size must be a + * multiple of this. + * @protect_block_size: Protection block size. Protection offset and size + * must be a multiple of this. + * @write_ideal_size: Ideal write size in bytes. Writes will be fastest if + * size is exactly this and offset is a multiple of this. + * For example, an EC may have a write buffer which can do + * half-page operations if data is aligned, and a slower + * word-at-a-time write mode. + * @flags: Flags; see EC_FLASH_INFO_* + * * Version 1 returns the same initial fields as version 0, with additional * fields following. * @@ -1208,7 +1886,7 @@ struct __ec_align4 ec_response_flash_info { * The EC returns the number of banks describing the flash memory. * It adds banks descriptions up to num_banks_desc. */ -struct __ec_align4 ec_response_flash_info_1 { +struct ec_response_flash_info_1 { /* Version 0 fields; see above for description */ uint32_t flash_size; uint32_t write_block_size; @@ -1216,24 +1894,16 @@ struct __ec_align4 ec_response_flash_info_1 { uint32_t protect_block_size; /* Version 1 adds these fields: */ - /* - * Ideal write size in bytes. Writes will be fastest if size is - * exactly this and offset is a multiple of this. For example, an EC - * may have a write buffer which can do half-page operations if data is - * aligned, and a slower word-at-a-time write mode. - */ uint32_t write_ideal_size; - - /* Flags; see EC_FLASH_INFO_* */ uint32_t flags; -}; +} __ec_align4; -struct __ec_align4 ec_params_flash_info_2 { +struct ec_params_flash_info_2 { /* Number of banks to describe */ uint16_t num_banks_desc; /* Reserved; set 0; ignore on read */ uint8_t reserved[2]; -}; +} __ec_align4; struct ec_flash_bank { /* Number of sector is in this bank. */ @@ -1250,7 +1920,7 @@ struct ec_flash_bank { uint8_t reserved[2]; }; -struct __ec_align4 ec_response_flash_info_2 { +struct ec_response_flash_info_2 { /* Total flash in the EC. */ uint32_t flash_size; /* Flags; see EC_FLASH_INFO_* */ @@ -1261,8 +1931,8 @@ struct __ec_align4 ec_response_flash_info_2 { uint16_t num_banks_total; /* Number of banks described in banks array. */ uint16_t num_banks_desc; - struct ec_flash_bank banks[0]; -}; + struct ec_flash_bank banks[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; /* * Read flash @@ -1271,10 +1941,15 @@ struct __ec_align4 ec_response_flash_info_2 { */ #define EC_CMD_FLASH_READ 0x0011 -struct __ec_align4 ec_params_flash_read { - uint32_t offset; /* Byte offset to read */ - uint32_t size; /* Size to read in bytes */ -}; +/** + * struct ec_params_flash_read - Parameters for the flash read command. + * @offset: Byte offset to read. + * @size: Size to read in bytes. + */ +struct ec_params_flash_read { + uint32_t offset; + uint32_t size; +} __ec_align4; /* Write flash */ #define EC_CMD_FLASH_WRITE 0x0012 @@ -1283,23 +1958,42 @@ struct __ec_align4 ec_params_flash_read { /* Version 0 of the flash command supported only 64 bytes of data */ #define EC_FLASH_WRITE_VER0_SIZE 64 -struct __ec_align4 ec_params_flash_write { - uint32_t offset; /* Byte offset to write */ - uint32_t size; /* Size to write in bytes */ - /* Followed by data to write */ -}; +/** + * struct ec_params_flash_write - Parameters for the flash write command. + * @offset: Byte offset to write. + * @size: Size to write in bytes. + * @data: Data to write. + * @data.words32: uint32_t data to write. + * @data.bytes: uint8_t data to write. + */ +struct ec_params_flash_write { + uint32_t offset; + uint32_t size; + /* Followed by data to write. This union allows accessing an + * underlying buffer as uint32s or uint8s for convenience. + */ + union { + uint32_t words32[FLEXIBLE_ARRAY_MEMBER_SIZE]; + uint8_t bytes[FLEXIBLE_ARRAY_MEMBER_SIZE]; + } data; +} __ec_align4; +BUILD_ASSERT(member_size(struct ec_params_flash_write, data) == 0); /* Erase flash */ #define EC_CMD_FLASH_ERASE 0x0013 -/* v0 */ -struct __ec_align4 ec_params_flash_erase { - uint32_t offset; /* Byte offset to erase */ - uint32_t size; /* Size to erase in bytes */ -}; +/** + * struct ec_params_flash_erase - Parameters for the flash erase command, v0. + * @offset: Byte offset to erase. + * @size: Size to erase in bytes. + */ +struct ec_params_flash_erase { + uint32_t offset; + uint32_t size; +} __ec_align4; -#define EC_VER_FLASH_WRITE 1 -/* v1 add async erase: +/* + * v1 add async erase: * subcommands can returns: * EC_RES_SUCCESS : erased (see ERASE_SECTOR_ASYNC case below). * EC_RES_INVALID_PARAM : offset/size are not aligned on a erase boundary. @@ -1316,21 +2010,24 @@ struct __ec_align4 ec_params_flash_erase { * permitted while erasing. (For instance, STM32F4). */ enum ec_flash_erase_cmd { - FLASH_ERASE_SECTOR, /* Erase and wait for result */ - FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */ - FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ + FLASH_ERASE_SECTOR, /* Erase and wait for result */ + FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */ + FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ }; -struct __ec_align4 ec_params_flash_erase_v1 { - /* One of ec_flash_erase_cmd. */ - uint8_t cmd; - /* Pad byte; currently always contains 0 */ - uint8_t reserved; - /* No flags defined yet; set to 0 */ +/** + * struct ec_params_flash_erase_v1 - Parameters for the flash erase command, v1. + * @cmd: One of ec_flash_erase_cmd. + * @reserved: Pad byte; currently always contains 0. + * @flag: No flags defined yet; set to 0. + * @params: Same as v0 parameters. + */ +struct ec_params_flash_erase_v1 { + uint8_t cmd; + uint8_t reserved; uint16_t flag; - /* Same as v0 parameters. */ struct ec_params_flash_erase params; -}; +} __ec_align4; /* * Get/set flash protection. @@ -1343,56 +2040,78 @@ struct __ec_align4 ec_params_flash_erase_v1 { * If mask=0, simply returns the current flags state. */ #define EC_CMD_FLASH_PROTECT 0x0015 -#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */ +#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */ /* Flags for flash protection */ /* RO flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RO_AT_BOOT (1 << 0) +#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0) /* * RO flash code protected now. If this bit is set, at-boot status cannot * be changed. */ -#define EC_FLASH_PROTECT_RO_NOW (1 << 1) +#define EC_FLASH_PROTECT_RO_NOW BIT(1) /* Entire flash code protected now, until reboot. */ -#define EC_FLASH_PROTECT_ALL_NOW (1 << 2) +#define EC_FLASH_PROTECT_ALL_NOW BIT(2) /* Flash write protect GPIO is asserted now */ -#define EC_FLASH_PROTECT_GPIO_ASSERTED (1 << 3) +#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3) /* Error - at least one bank of flash is stuck locked, and cannot be unlocked */ -#define EC_FLASH_PROTECT_ERROR_STUCK (1 << 4) +#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4) /* * Error - flash protection is in inconsistent state. At least one bank of * flash which should be protected is not protected. Usually fixed by * re-requesting the desired flags, or by a hard reset if that fails. */ -#define EC_FLASH_PROTECT_ERROR_INCONSISTENT (1 << 5) +#define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5) /* Entire flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_ALL_AT_BOOT (1 << 6) +#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6) /* RW flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RW_AT_BOOT (1 << 7) +#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7) /* RW flash code protected now. */ -#define EC_FLASH_PROTECT_RW_NOW (1 << 8) +#define EC_FLASH_PROTECT_RW_NOW BIT(8) /* Rollback information flash region protected when the EC boots */ -#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT (1 << 9) +#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9) /* Rollback information flash region protected now */ -#define EC_FLASH_PROTECT_ROLLBACK_NOW (1 << 10) +#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) +/* Error - Unknown error */ +#define EC_FLASH_PROTECT_ERROR_UNKNOWN BIT(11) + +/** + * struct ec_params_flash_protect - Parameters for the flash protect command. + * @mask: Bits in flags to apply. + * @flags: New flags to apply. + */ +struct ec_params_flash_protect { + uint32_t mask; + uint32_t flags; +} __ec_align4; -struct __ec_align4 ec_params_flash_protect { - uint32_t mask; /* Bits in flags to apply */ - uint32_t flags; /* New flags to apply */ +enum flash_protect_action { + FLASH_PROTECT_ASYNC = 0, + FLASH_PROTECT_GET_RESULT = 1, }; -struct __ec_align4 ec_response_flash_protect { - /* Current value of flash protect flags */ +/* Version 2 of the command is "asynchronous". */ +struct ec_params_flash_protect_v2 { + uint8_t action; /**< enum flash_protect_action */ + uint8_t reserved[3]; /**< padding for alignment */ + uint32_t mask; + uint32_t flags; +} __ec_align4; + +/** + * struct ec_response_flash_protect - Response to the flash protect command. + * @flags: Current value of flash protect flags. + * @valid_flags: Flags which are valid on this platform. This allows the + * caller to distinguish between flags which aren't set vs. flags + * which can't be set on this platform. + * @writable_flags: Flags which can be changed given the current protection + * state. + */ +struct ec_response_flash_protect { uint32_t flags; - /* - * Flags which are valid on this platform. This allows the caller - * to distinguish between flags which aren't set vs. flags which can't - * be set on this platform. - */ uint32_t valid_flags; - /* Flags which can be changed given the current protection state */ uint32_t writable_flags; -}; +} __ec_align4; /* * Note: commands 0x14 - 0x19 version 0 were old commands to get/set flash @@ -1406,52 +2125,50 @@ struct __ec_align4 ec_response_flash_protect { enum ec_flash_region { /* Region which holds read-only EC image */ EC_FLASH_REGION_RO = 0, - /* Region which holds active rewritable EC image */ + /* + * Region which holds active RW image. 'Active' is different from + * 'running'. Active means 'scheduled-to-run'. Since RO image always + * scheduled to run, active/non-active applies only to RW images (for + * the same reason 'update' applies only to RW images. It's a state of + * an image on a flash. Running image can be RO, RW_A, RW_B but active + * image can only be RW_A or RW_B. In recovery mode, an active RW image + * doesn't enter 'running' state but it's still active on a flash. + */ EC_FLASH_REGION_ACTIVE, /* * Region which should be write-protected in the factory (a superset of * EC_FLASH_REGION_RO) */ EC_FLASH_REGION_WP_RO, - /* Region which holds updatable image */ + /* Region which holds updatable (non-active) RW image */ EC_FLASH_REGION_UPDATE, /* Number of regions */ EC_FLASH_REGION_COUNT, }; +/* + * 'RW' is vague if there are multiple RW images; we mean the active one, + * so the old constant is deprecated. + */ +#define EC_FLASH_REGION_RW EC_FLASH_REGION_ACTIVE -struct __ec_align4 ec_params_flash_region_info { - uint32_t region; /* enum ec_flash_region */ -}; +/** + * struct ec_params_flash_region_info - Parameters for the flash region info + * command. + * @region: Flash region; see EC_FLASH_REGION_* + */ +struct ec_params_flash_region_info { + uint32_t region; +} __ec_align4; -struct __ec_align4 ec_response_flash_region_info { +struct ec_response_flash_region_info { uint32_t offset; uint32_t size; -}; - -/* Read/write VbNvContext */ -#define EC_CMD_VBNV_CONTEXT 0x0017 -#define EC_VER_VBNV_CONTEXT 1 -#define EC_VBNV_BLOCK_SIZE 16 -#define EC_VBNV_BLOCK_SIZE_V2 64 - -enum ec_vbnvcontext_op { - EC_VBNV_CONTEXT_OP_READ, - EC_VBNV_CONTEXT_OP_WRITE, -}; - -struct __ec_align4 ec_params_vbnvcontext { - uint32_t op; - uint8_t block[EC_VBNV_BLOCK_SIZE_V2]; -}; - -struct __ec_align4 ec_response_vbnvcontext { - uint8_t block[EC_VBNV_BLOCK_SIZE_V2]; -}; +} __ec_align4; /* Get SPI flash information */ #define EC_CMD_FLASH_SPI_INFO 0x0018 -struct __ec_align1 ec_response_flash_spi_info { +struct ec_response_flash_spi_info { /* JEDEC info from command 0x9F (manufacturer, memory type, size) */ uint8_t jedec[3]; @@ -1463,70 +2180,163 @@ struct __ec_align1 ec_response_flash_spi_info { /* Status registers from command 0x05 and 0x35 */ uint8_t sr1, sr2; -}; +} __ec_align1; /* Select flash during flash operations */ #define EC_CMD_FLASH_SELECT 0x0019 -struct __ec_align4 ec_params_flash_select { - /* 1 to select flash, 0 to deselect flash */ +/** + * struct ec_params_flash_select - Parameters for the flash select command. + * @select: 1 to select flash, 0 to deselect flash + */ +struct ec_params_flash_select { uint8_t select; +} __ec_align4; + +/** + * Request random numbers to be generated and returned. + * Can be used to test the random number generator is truly random. + * See https://csrc.nist.gov/publications/detail/sp/800-22/rev-1a/final and + * https://webhome.phy.duke.edu/~rgb/General/dieharder.php. + */ +#define EC_CMD_RAND_NUM 0x001A +#define EC_VER_RAND_NUM 0 + +struct ec_params_rand_num { + uint16_t num_rand_bytes; /**< num random bytes to generate */ +} __ec_align4; + +struct ec_response_rand_num { + /** + * generated random numbers in the range of 1 to EC_MAX_INSIZE. The true + * size of rand is determined by ec_params_rand_num's num_rand_bytes. + */ + uint8_t rand[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align1; +BUILD_ASSERT(sizeof(struct ec_response_rand_num) == 0); + +/** + * Get information about the key used to sign the RW firmware. + * For more details on the fields, see "struct vb21_packed_key". + */ +#define EC_CMD_RWSIG_INFO 0x001B +#define EC_VER_RWSIG_INFO 0 + +#define VBOOT2_KEY_ID_BYTES 20 + +#ifdef CHROMIUM_EC +/* Don't force external projects to depend on the vboot headers. */ +#include "vb21_struct.h" +BUILD_ASSERT(sizeof(struct vb2_id) == VBOOT2_KEY_ID_BYTES); +#endif + +struct ec_response_rwsig_info { + /** + * Signature algorithm used by the key + * (enum vb2_signature_algorithm). + */ + uint16_t sig_alg; + + /** + * Hash digest algorithm used with the key + * (enum vb2_hash_algorithm). + */ + uint16_t hash_alg; + + /** Key version. */ + uint32_t key_version; + + /** Key ID (struct vb2_id). */ + uint8_t key_id[VBOOT2_KEY_ID_BYTES]; + + uint8_t key_is_valid; + + /** Alignment padding. */ + uint8_t reserved[3]; +} __ec_align4; + +BUILD_ASSERT(sizeof(struct ec_response_rwsig_info) == 32); + +/** + * Get information about the system, such as reset flags, locked state, etc. + */ +#define EC_CMD_SYSINFO 0x001C +#define EC_VER_SYSINFO 0 + +enum sysinfo_flags { + SYSTEM_IS_LOCKED = BIT(0), + SYSTEM_IS_FORCE_LOCKED = BIT(1), + SYSTEM_JUMP_ENABLED = BIT(2), + SYSTEM_JUMPED_TO_CURRENT_IMAGE = BIT(3), + SYSTEM_REBOOT_AT_SHUTDOWN = BIT(4), + /* + * Used internally. It's set when EC_HOST_EVENT_KEYBOARD_RECOVERY is + * set and cleared when the system shuts down (not when the host event + * flag is cleared). + */ + SYSTEM_IN_MANUAL_RECOVERY = BIT(5), }; +struct ec_response_sysinfo { + uint32_t reset_flags; /**< EC_RESET_FLAG_* flags */ + uint32_t current_image; /**< enum ec_image */ + uint32_t flags; /**< enum sysinfo_flags */ +} __ec_align4; + /*****************************************************************************/ /* PWM commands */ /* Get fan target RPM */ #define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x0020 -struct __ec_align4 ec_response_pwm_get_fan_rpm { +struct ec_response_pwm_get_fan_rpm { uint32_t rpm; -}; +} __ec_align4; /* Set target fan RPM */ #define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x0021 /* Version 0 of input params */ -struct __ec_align4 ec_params_pwm_set_fan_target_rpm_v0 { +struct ec_params_pwm_set_fan_target_rpm_v0 { uint32_t rpm; -}; +} __ec_align4; /* Version 1 of input params */ -struct __ec_align_size1 ec_params_pwm_set_fan_target_rpm_v1 { +struct ec_params_pwm_set_fan_target_rpm_v1 { uint32_t rpm; uint8_t fan_idx; -}; +} __ec_align_size1; /* Get keyboard backlight */ /* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ #define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x0022 -struct __ec_align1 ec_response_pwm_get_keyboard_backlight { +struct ec_response_pwm_get_keyboard_backlight { uint8_t percent; uint8_t enabled; -}; +} __ec_align1; /* Set keyboard backlight */ /* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */ #define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x0023 -struct __ec_align1 ec_params_pwm_set_keyboard_backlight { +struct ec_params_pwm_set_keyboard_backlight { uint8_t percent; -}; +} __ec_align1; /* Set target fan PWM duty cycle */ #define EC_CMD_PWM_SET_FAN_DUTY 0x0024 /* Version 0 of input params */ -struct __ec_align4 ec_params_pwm_set_fan_duty_v0 { +struct ec_params_pwm_set_fan_duty_v0 { uint32_t percent; -}; +} __ec_align4; /* Version 1 of input params */ -struct __ec_align_size1 ec_params_pwm_set_fan_duty_v1 { +struct ec_params_pwm_set_fan_duty_v1 { uint32_t percent; uint8_t fan_idx; -}; +} __ec_align_size1; #define EC_CMD_PWM_SET_DUTY 0x0025 /* 16 bit duty cycle, 0xffff = 100% */ @@ -1542,22 +2352,32 @@ enum ec_pwm_type { EC_PWM_TYPE_COUNT, }; -struct __ec_align4 ec_params_pwm_set_duty { - uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ - uint8_t pwm_type; /* ec_pwm_type */ - uint8_t index; /* Type-specific index, or 0 if unique */ -}; +struct ec_params_pwm_set_duty { + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ +} __ec_align4; #define EC_CMD_PWM_GET_DUTY 0x0026 -struct __ec_align1 ec_params_pwm_get_duty { - uint8_t pwm_type; /* ec_pwm_type */ - uint8_t index; /* Type-specific index, or 0 if unique */ -}; +struct ec_params_pwm_get_duty { + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ +} __ec_align1; -struct __ec_align2 ec_response_pwm_get_duty { - uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ -}; +struct ec_response_pwm_get_duty { + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ +} __ec_align2; + +#define EC_CMD_PWM_GET_FAN_DUTY 0x0027 + +struct ec_params_pwm_get_fan_duty { + uint8_t fan_idx; +} __ec_align1; + +struct ec_response_pwm_get_fan_duty { + uint32_t percent; /* Percentage of duty cycle, ranging from 0 ~ 100 */ +} __ec_align4; /*****************************************************************************/ /* @@ -1568,21 +2388,23 @@ struct __ec_align2 ec_response_pwm_get_duty { */ #define EC_CMD_LIGHTBAR_CMD 0x0028 -struct __ec_todo_unpacked rgb_s { +struct rgb_s { uint8_t r, g, b; -}; +} __ec_todo_unpacked; #define LB_BATTERY_LEVELS 4 -/* List of tweakable parameters. NOTE: It's __packed so it can be sent in a + +/* + * List of tweakable parameters. NOTE: It's __packed so it can be sent in a * host command, but the alignment is the same regardless. Keep it that way. */ -struct __ec_todo_packed lightbar_params_v0 { +struct lightbar_params_v0 { /* Timing */ int32_t google_ramp_up; int32_t google_ramp_down; int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ int32_t s0s3_ramp_down; int32_t s3_sleep_for; int32_t s3_ramp_up; @@ -1590,33 +2412,33 @@ struct __ec_todo_packed lightbar_params_v0 { /* Oscillation */ uint8_t new_s0; - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ /* Battery level thresholds */ uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ -}; + struct rgb_s color[8]; /* 0-3 are Google colors */ +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v1 { +struct lightbar_params_v1 { /* Timing */ int32_t google_ramp_up; int32_t google_ramp_down; int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ int32_t s0s3_ramp_down; int32_t s3_sleep_for; int32_t s3_ramp_up; @@ -1636,28 +2458,28 @@ struct __ec_todo_packed lightbar_params_v1 { uint8_t tap_idx[3]; /* Oscillation */ - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ /* Battery level thresholds */ uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ /* s5: single color pulse on inhibited power-up */ uint8_t s5_idx; /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ -}; + struct rgb_s color[8]; /* 0-3 are Google colors */ +} __ec_todo_packed; /* Lightbar command params v2 * crbug.com/467716 @@ -1668,13 +2490,13 @@ struct __ec_todo_packed lightbar_params_v1 { * NOTE: Each of these groups must be less than 120 bytes. */ -struct __ec_todo_packed lightbar_params_v2_timing { +struct lightbar_params_v2_timing { /* Timing */ int32_t google_ramp_up; int32_t google_ramp_down; int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ int32_t s0s3_ramp_down; int32_t s3_sleep_for; int32_t s3_ramp_up; @@ -1684,9 +2506,9 @@ struct __ec_todo_packed lightbar_params_v2_timing { int32_t tap_tick_delay; int32_t tap_gate_delay; int32_t tap_display_time; -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_tap { +struct lightbar_params_v2_tap { /* Tap-for-battery params */ uint8_t tap_pct_red; uint8_t tap_pct_green; @@ -1694,56 +2516,79 @@ struct __ec_todo_packed lightbar_params_v2_tap { uint8_t tap_seg_max_on; uint8_t tap_seg_osc; uint8_t tap_idx[3]; -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_oscillation { +struct lightbar_params_v2_oscillation { /* Oscillation */ - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ -}; + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_brightness { +struct lightbar_params_v2_brightness { /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ -}; + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_thresholds { +struct lightbar_params_v2_thresholds { /* Battery level thresholds */ uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; -}; +} __ec_todo_packed; -struct __ec_todo_packed lightbar_params_v2_colors { +struct lightbar_params_v2_colors { /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ /* s5: single color pulse on inhibited power-up */ uint8_t s5_idx; /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ -}; + struct rgb_s color[8]; /* 0-3 are Google colors */ +} __ec_todo_packed; + +struct lightbar_params_v3 { + /* + * Number of LEDs reported by the EC. + * May be less than the actual number of LEDs in the lightbar. + */ + uint8_t reported_led_num; +} __ec_todo_packed; -/* Lightbyte program. */ +/* Lightbar program. */ #define EC_LB_PROG_LEN 192 -struct __ec_todo_unpacked lightbar_program { +struct lightbar_program { uint8_t size; uint8_t data[EC_LB_PROG_LEN]; -}; +} __ec_todo_unpacked; + +/* + * Lightbar program for large sequences. Sequences are sent in pieces, with + * increasing offset. The sequences are still limited by the amount reserved in + * EC RAM. + */ +struct lightbar_program_ex { + uint8_t size; + uint16_t offset; + uint8_t data[0]; +} __ec_todo_packed; -struct __ec_todo_packed ec_params_lightbar { - uint8_t cmd; /* Command (see enum lightbar_command) */ +struct ec_params_lightbar { + uint8_t cmd; /* Command (see enum lightbar_command) */ union { - struct __ec_todo_unpacked { - /* no args */ - } dump, off, on, init, get_seq, get_params_v0, get_params_v1, - version, get_brightness, get_demo, suspend, resume, - get_params_v2_timing, get_params_v2_tap, - get_params_v2_osc, get_params_v2_bright, - get_params_v2_thlds, get_params_v2_colors; + /* + * The following commands have no args: + * + * dump, off, on, init, get_seq, get_params_v0, get_params_v1, + * version, get_brightness, get_demo, suspend, resume, + * get_params_v2_timing, get_params_v2_tap, get_params_v2_osc, + * get_params_v2_bright, get_params_v2_thlds, + * get_params_v2_colors + * + * Don't use an empty struct, because C++ hates that. + */ struct __ec_todo_unpacked { uint8_t num; @@ -1776,10 +2621,11 @@ struct __ec_todo_packed ec_params_lightbar { struct lightbar_params_v2_colors set_v2par_colors; struct lightbar_program set_program; + struct lightbar_program_ex set_program_ex; }; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_lightbar { +struct ec_response_lightbar { union { struct __ec_todo_unpacked { struct __ec_todo_unpacked { @@ -1803,6 +2649,8 @@ struct __ec_todo_packed ec_response_lightbar { struct lightbar_params_v2_thresholds get_params_v2_thlds; struct lightbar_params_v2_colors get_params_v2_colors; + struct lightbar_params_v3 get_params_v3; + struct __ec_todo_unpacked { uint32_t num; uint32_t flags; @@ -1812,16 +2660,17 @@ struct __ec_todo_packed ec_response_lightbar { uint8_t red, green, blue; } get_rgb; - struct __ec_todo_unpacked { - /* no return params */ - } off, on, init, set_brightness, seq, reg, set_rgb, - demo, set_params_v0, set_params_v1, - set_program, manual_suspend_ctrl, suspend, resume, - set_v2par_timing, set_v2par_tap, - set_v2par_osc, set_v2par_bright, set_v2par_thlds, - set_v2par_colors; + /* + * The following commands have no response: + * + * off, on, init, set_brightness, seq, reg, set_rgb, demo, + * set_params_v0, set_params_v1, set_program, + * manual_suspend_ctrl, suspend, resume, set_v2par_timing, + * set_v2par_tap, set_v2par_osc, set_v2par_bright, + * set_v2par_thlds, set_v2par_colors + */ }; -}; +} __ec_todo_packed; /* Lightbar commands */ enum lightbar_command { @@ -1859,7 +2708,9 @@ enum lightbar_command { LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31, LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32, LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33, - LIGHTBAR_NUM_CMDS + LIGHTBAR_CMD_GET_PARAMS_V3 = 34, + LIGHTBAR_CMD_SET_PROGRAM_EX = 35, + LIGHTBAR_NUM_CMDS, }; /*****************************************************************************/ @@ -1885,33 +2736,37 @@ enum ec_led_id { EC_LED_ID_RECOVERY_HW_REINIT_LED, /* LED to indicate sysrq debug mode. */ EC_LED_ID_SYSRQ_DEBUG_LED, + /* LED strip for advanced patterns. */ + EC_LED_ID_LIGHTBAR_LED, - EC_LED_ID_COUNT + EC_LED_ID_COUNT, }; /* LED control flags */ -#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */ -#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */ +#define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */ +#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */ enum ec_led_colors { + EC_LED_COLOR_INVALID = -1, EC_LED_COLOR_RED = 0, EC_LED_COLOR_GREEN, EC_LED_COLOR_BLUE, EC_LED_COLOR_YELLOW, EC_LED_COLOR_WHITE, EC_LED_COLOR_AMBER, + EC_LED_COLOR_MAGENTA, - EC_LED_COLOR_COUNT + EC_LED_COLOR_COUNT, }; -struct __ec_align1 ec_params_led_control { - uint8_t led_id; /* Which LED to control */ - uint8_t flags; /* Control flags */ +struct ec_params_led_control { + uint8_t led_id; /* Which LED to control */ + uint8_t flags; /* Control flags */ uint8_t brightness[EC_LED_COLOR_COUNT]; -}; +} __ec_align1; -struct __ec_align1 ec_response_led_control { +struct ec_response_led_control { /* * Available brightness value range. * @@ -1920,7 +2775,7 @@ struct __ec_align1 ec_response_led_control { * Other values means the LED is control by PWM. */ uint8_t brightness_range[EC_LED_COLOR_COUNT]; -}; +} __ec_align1; /*****************************************************************************/ /* Verified boot commands */ @@ -1933,31 +2788,31 @@ struct __ec_align1 ec_response_led_control { /* Verified boot hash command */ #define EC_CMD_VBOOT_HASH 0x002A -struct __ec_align4 ec_params_vboot_hash { - uint8_t cmd; /* enum ec_vboot_hash_cmd */ - uint8_t hash_type; /* enum ec_vboot_hash_type */ - uint8_t nonce_size; /* Nonce size; may be 0 */ - uint8_t reserved0; /* Reserved; set 0 */ - uint32_t offset; /* Offset in flash to hash */ - uint32_t size; /* Number of bytes to hash */ - uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ -}; - -struct __ec_align4 ec_response_vboot_hash { - uint8_t status; /* enum ec_vboot_hash_status */ - uint8_t hash_type; /* enum ec_vboot_hash_type */ - uint8_t digest_size; /* Size of hash digest in bytes */ - uint8_t reserved0; /* Ignore; will be 0 */ - uint32_t offset; /* Offset in flash which was hashed */ - uint32_t size; /* Number of bytes hashed */ +struct ec_params_vboot_hash { + uint8_t cmd; /* enum ec_vboot_hash_cmd */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t nonce_size; /* Nonce size; may be 0 */ + uint8_t reserved0; /* Reserved; set 0 */ + uint32_t offset; /* Offset in flash to hash */ + uint32_t size; /* Number of bytes to hash */ + uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ +} __ec_align4; + +struct ec_response_vboot_hash { + uint8_t status; /* enum ec_vboot_hash_status */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t digest_size; /* Size of hash digest in bytes */ + uint8_t reserved0; /* Ignore; will be 0 */ + uint32_t offset; /* Offset in flash which was hashed */ + uint32_t size; /* Number of bytes hashed */ uint8_t hash_digest[64]; /* Hash digest data */ -}; +} __ec_align4; enum ec_vboot_hash_cmd { - EC_VBOOT_HASH_GET = 0, /* Get current hash status */ - EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */ - EC_VBOOT_HASH_START = 2, /* Start computing a new hash */ - EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */ + EC_VBOOT_HASH_GET = 0, /* Get current hash status */ + EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */ + EC_VBOOT_HASH_START = 2, /* Start computing a new hash */ + EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */ }; enum ec_vboot_hash_type { @@ -1975,9 +2830,15 @@ enum ec_vboot_hash_status { * If one of these is specified, the EC will automatically update offset and * size to the correct values for the specified image (RO or RW). */ -#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe -#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd -#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc +#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe +#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd +#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc + +/* + * 'RW' is vague if there are multiple RW images; we mean the active one, + * so the old constant is deprecated. + */ +#define EC_VBOOT_HASH_OFFSET_RW EC_VBOOT_HASH_OFFSET_ACTIVE /*****************************************************************************/ /* @@ -2063,7 +2924,7 @@ enum motionsense_command { /* * Sensor Offset command is a setter/getter command for the offset - * used for calibration. + * used for factory calibration. * The offsets can be calculated by the host, or via * PERFORM_CALIB command. */ @@ -2099,8 +2960,28 @@ enum motionsense_command { */ MOTIONSENSE_CMD_SPOOF = 16, + /* Set lid angle for tablet mode detection. */ + MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE = 17, + + /* + * Sensor Scale command is a setter/getter command for the calibration + * scale. + */ + MOTIONSENSE_CMD_SENSOR_SCALE = 18, + + /* + * Read the current online calibration values (if available). + */ + MOTIONSENSE_CMD_ONLINE_CALIB_READ = 19, + + /* + * Activity management + * Retrieve current status of given activity. + */ + MOTIONSENSE_CMD_GET_ACTIVITY = 20, + /* Number of motionsense sub-commands. */ - MOTIONSENSE_NUM_CMDS + MOTIONSENSE_NUM_CMDS, }; /* List of motion sensor types. */ @@ -2112,6 +2993,8 @@ enum motionsensor_type { MOTIONSENSE_TYPE_LIGHT = 4, MOTIONSENSE_TYPE_ACTIVITY = 5, MOTIONSENSE_TYPE_BARO = 6, + MOTIONSENSE_TYPE_SYNC = 7, + MOTIONSENSE_TYPE_LIGHT_RGB = 8, MOTIONSENSE_TYPE_MAX, }; @@ -2119,6 +3002,7 @@ enum motionsensor_type { enum motionsensor_location { MOTIONSENSE_LOC_BASE = 0, MOTIONSENSE_LOC_LID = 1, + MOTIONSENSE_LOC_CAMERA = 2, MOTIONSENSE_LOC_MAX, }; @@ -2135,76 +3019,127 @@ enum motionsensor_chip { MOTIONSENSE_CHIP_BMA255 = 8, MOTIONSENSE_CHIP_BMP280 = 9, MOTIONSENSE_CHIP_OPT3001 = 10, -}; + MOTIONSENSE_CHIP_BH1730 = 11, + MOTIONSENSE_CHIP_GPIO = 12, + MOTIONSENSE_CHIP_LIS2DH = 13, + MOTIONSENSE_CHIP_LSM6DSM = 14, + MOTIONSENSE_CHIP_LIS2DE = 15, + MOTIONSENSE_CHIP_LIS2MDL = 16, + MOTIONSENSE_CHIP_LSM6DS3 = 17, + MOTIONSENSE_CHIP_LSM6DSO = 18, + MOTIONSENSE_CHIP_LNG2DM = 19, + MOTIONSENSE_CHIP_TCS3400 = 20, + MOTIONSENSE_CHIP_LIS2DW12 = 21, + MOTIONSENSE_CHIP_LIS2DWL = 22, + MOTIONSENSE_CHIP_LIS2DS = 23, + MOTIONSENSE_CHIP_BMI260 = 24, + MOTIONSENSE_CHIP_ICM426XX = 25, + MOTIONSENSE_CHIP_ICM42607 = 26, + MOTIONSENSE_CHIP_BMA422 = 27, + MOTIONSENSE_CHIP_BMI323 = 28, + MOTIONSENSE_CHIP_BMI220 = 29, + MOTIONSENSE_CHIP_CM32183 = 30, + MOTIONSENSE_CHIP_VEML3328 = 31, + MOTIONSENSE_CHIP_CM36781 = 32, + MOTIONSENSE_CHIP_MAX, +}; + +/* List of orientation positions */ +enum motionsensor_orientation { + MOTIONSENSE_ORIENTATION_LANDSCAPE = 0, + MOTIONSENSE_ORIENTATION_PORTRAIT = 1, + MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT = 2, + MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE = 3, + MOTIONSENSE_ORIENTATION_UNKNOWN = 4, +}; + +struct ec_response_activity_data { + uint8_t activity; /* motionsensor_activity */ + uint8_t state; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_motion_sensor_data { +struct ec_response_motion_sensor_data { /* Flags for each sensor. */ uint8_t flags; - /* sensor number the data comes from */ + /* Sensor number the data comes from. */ uint8_t sensor_num; /* Each sensor is up to 3-axis. */ union { - int16_t data[3]; + int16_t data[3]; + /* for sensors using unsigned data */ + uint16_t udata[3]; struct __ec_todo_packed { - uint16_t reserved; - uint32_t timestamp; + uint16_t reserved; + uint32_t timestamp; }; struct __ec_todo_unpacked { - uint8_t activity; /* motionsensor_activity */ - uint8_t state; - int16_t add_info[2]; + struct ec_response_activity_data activity_data; + int16_t add_info[2]; }; }; +} __ec_todo_packed; + +/* Response to AP reporting calibration data for a given sensor. */ +struct ec_response_online_calibration_data { + /** The calibration values. */ + int16_t data[3]; }; /* Note: used in ec_response_get_next_data */ -struct __ec_todo_packed ec_response_motion_sense_fifo_info { +struct ec_response_motion_sense_fifo_info { /* Size of the fifo */ uint16_t size; /* Amount of space used in the fifo */ uint16_t count; - /* Timestamp recorded in us */ + /* Timestamp recorded in us. + * aka accurate timestamp when host event was triggered. + */ uint32_t timestamp; /* Total amount of vector lost */ uint16_t total_lost; /* Lost events since the last fifo_info, per sensors */ uint16_t lost[0]; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_motion_sense_fifo_data { +struct ec_response_motion_sense_fifo_data { uint32_t number_data; struct ec_response_motion_sensor_data data[0]; -}; +} __ec_todo_packed; /* List supported activity recognition */ enum motionsensor_activity { MOTIONSENSE_ACTIVITY_RESERVED = 0, MOTIONSENSE_ACTIVITY_SIG_MOTION = 1, MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2, + MOTIONSENSE_ACTIVITY_ORIENTATION = 3, + MOTIONSENSE_ACTIVITY_BODY_DETECTION = 4, }; -struct __ec_todo_unpacked ec_motion_sense_activity { +struct ec_motion_sense_activity { uint8_t sensor_num; uint8_t activity; /* one of enum motionsensor_activity */ - uint8_t enable; /* 1: enable, 0: disable */ + uint8_t enable; /* 1: enable, 0: disable */ uint8_t reserved; - uint16_t parameters[3]; /* activity dependent parameters */ -}; + uint16_t parameters[4]; /* activity dependent parameters */ +} __ec_todo_packed; /* Module flag masks used for the dump sub-command. */ -#define MOTIONSENSE_MODULE_FLAG_ACTIVE (1<<0) +#define MOTIONSENSE_MODULE_FLAG_ACTIVE BIT(0) /* Sensor flag masks used for the dump sub-command. */ -#define MOTIONSENSE_SENSOR_FLAG_PRESENT (1<<0) +#define MOTIONSENSE_SENSOR_FLAG_PRESENT BIT(0) /* * Flush entry for synchronization. * data contains time stamp */ -#define MOTIONSENSE_SENSOR_FLAG_FLUSH (1<<0) -#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP (1<<1) -#define MOTIONSENSE_SENSOR_FLAG_WAKEUP (1<<2) -#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE (1<<3) +#define MOTIONSENSE_SENSOR_FLAG_FLUSH BIT(0) +#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP BIT(1) +#define MOTIONSENSE_SENSOR_FLAG_WAKEUP BIT(2) +#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE BIT(3) +#define MOTIONSENSE_SENSOR_FLAG_ODR BIT(4) + +#define MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO BIT(7) /* * Send this value for the data element to only perform a read. If you @@ -2213,11 +3148,14 @@ struct __ec_todo_unpacked ec_motion_sense_activity { */ #define EC_MOTION_SENSE_NO_VALUE -1 -#define EC_MOTION_SENSE_INVALID_CALIB_TEMP 0x8000 +#define EC_MOTION_SENSE_INVALID_CALIB_TEMP INT16_MIN /* MOTIONSENSE_CMD_SENSOR_OFFSET subcommand flag */ /* Set Calibration information */ -#define MOTION_SENSE_SET_OFFSET 1 +#define MOTION_SENSE_SET_OFFSET BIT(0) + +/* Default Scale value, factor 1. */ +#define MOTION_SENSE_DEFAULT_SCALE BIT(15) #define LID_ANGLE_UNRELIABLE 500 @@ -2235,10 +3173,10 @@ enum motionsense_spoof_mode { MOTIONSENSE_SPOOF_MODE_QUERY, }; -struct __ec_todo_packed ec_params_motion_sense { +struct ec_params_motion_sense { uint8_t cmd; union { - /* Used for MOTIONSENSE_CMD_DUMP */ + /* Used for MOTIONSENSE_CMD_DUMP. */ struct __ec_todo_unpacked { /* * Maximal number of sensor the host is expecting. @@ -2253,17 +3191,26 @@ struct __ec_todo_packed ec_params_motion_sense { */ struct __ec_todo_unpacked { /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. - * kb_wake_angle: angle to wakup AP. + * kb_wake_angle: angle to wakeup AP. */ int16_t data; } kb_wake_angle; - /* Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA - * and MOTIONSENSE_CMD_PERFORM_CALIB. */ + /* + * Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + } info, info_3, info_4, data, fifo_flush, list_activities; + + /* + * Used for MOTIONSENSE_CMD_PERFORM_CALIB: + * Allow entering/exiting the calibration mode. + */ struct __ec_todo_unpacked { uint8_t sensor_num; - } info, info_3, data, fifo_flush, perform_calib, - list_activities; + uint8_t enable; + } perform_calib; /* * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR @@ -2310,24 +3257,52 @@ struct __ec_todo_packed ec_params_motion_sense { int16_t offset[3]; } sensor_offset; - /* Used for MOTIONSENSE_CMD_FIFO_INFO */ - struct __ec_todo_unpacked { - } fifo_info; + /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ + struct __ec_todo_packed { + uint8_t sensor_num; - /* Used for MOTIONSENSE_CMD_FIFO_READ */ - struct __ec_todo_unpacked { /* - * Number of expected vector to return. - * EC may return less or 0 if none available. - */ + * bit 0: If set (MOTION_SENSE_SET_OFFSET), set + * the calibration information in the EC. + * If unset, just retrieve calibration information. + */ + uint16_t flags; + + /* + * Temperature at calibration, in units of 0.01 C + * 0x8000: invalid / unknown. + * 0x0: 0C + * 0x7fff: +327.67C + */ + int16_t temp; + + /* + * Scale for calibration: + * By default scale is 1, it is encoded on 16bits: + * 1 = BIT(15) + * ~2 = 0xFFFF + * ~0 = 0. + */ + uint16_t scale[3]; + } sensor_scale; + + /* Used for MOTIONSENSE_CMD_FIFO_INFO */ + /* (no params) */ + + /* Used for MOTIONSENSE_CMD_FIFO_READ */ + struct __ec_todo_unpacked { + /* + * Number of expected vector to return. + * EC may return less or 0 if none available. + */ uint32_t max_data_vector; } fifo_read; + /* Used for MOTIONSENSE_CMD_SET_ACTIVITY */ struct ec_motion_sense_activity set_activity; /* Used for MOTIONSENSE_CMD_LID_ANGLE */ - struct __ec_todo_unpacked { - } lid_angle; + /* (no params) */ /* Used for MOTIONSENSE_CMD_FIFO_INT_ENABLE */ struct __ec_todo_unpacked { @@ -2348,24 +3323,74 @@ struct __ec_todo_packed ec_params_motion_sense { /* Ignored, used for alignment. */ uint8_t reserved; - /* Individual component values to spoof. */ - int16_t components[3]; + union { + /* Individual component values to spoof. */ + int16_t components[3]; + + /* Used when spoofing an activity */ + struct { + /* enum motionsensor_activity */ + uint8_t activity_num; + + /* spoof activity state */ + uint8_t activity_state; + }; + } __ec_todo_packed; } spoof; - }; + + /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ + struct __ec_todo_unpacked { + /* + * Lid angle threshold for switching between tablet and + * clamshell mode. + */ + int16_t lid_angle; + + /* + * Hysteresis degree to prevent fluctuations between + * clamshell and tablet mode if lid angle keeps + * changing around the threshold. Lid motion driver will + * use lid_angle + hys_degree to trigger tablet mode and + * lid_angle - hys_degree to trigger clamshell mode. + */ + int16_t hys_degree; + } tablet_mode_threshold; + + /* + * Used for MOTIONSENSE_CMD_ONLINE_CALIB_READ: + * Allow reading a single sensor's online calibration value. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + } online_calib_read; + + /* + * Used for MOTIONSENSE_CMD_GET_ACTIVITY. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + uint8_t activity; /* enum motionsensor_activity */ + } get_activity; + } __ec_todo_packed; +} __ec_todo_packed; + +enum motion_sense_cmd_info_flags { + /* The sensor supports online calibration */ + MOTION_SENSE_CMD_INFO_FLAG_ONLINE_CALIB = BIT(0), }; -struct __ec_todo_packed ec_response_motion_sense { +struct ec_response_motion_sense { union { /* Used for MOTIONSENSE_CMD_DUMP */ struct __ec_todo_unpacked { /* Flags representing the motion sensor module. */ uint8_t module_flags; - /* Number of sensors managed directly by the EC */ + /* Number of sensors managed directly by the EC. */ uint8_t sensor_count; /* - * sensor data is truncated if response_max is too small + * Sensor data is truncated if response_max is too small * for holding all the data. */ struct ec_response_motion_sensor_data sensor[0]; @@ -2404,6 +3429,33 @@ struct __ec_todo_packed ec_response_motion_sense { uint32_t fifo_max_event_count; } info_3; + /* Used for MOTIONSENSE_CMD_INFO version 4 */ + struct __ec_align4 { + /* Should be element of enum motionsensor_type. */ + uint8_t type; + + /* Should be element of enum motionsensor_location. */ + uint8_t location; + + /* Should be element of enum motionsensor_chip. */ + uint8_t chip; + + /* Minimum sensor sampling frequency */ + uint32_t min_frequency; + + /* Maximum sensor sampling frequency */ + uint32_t max_frequency; + + /* Max number of sensor events that could be in fifo */ + uint32_t fifo_max_event_count; + + /* + * Should be elements of + * enum motion_sense_cmd_info_flags + */ + uint32_t flags; + } info_4; + /* Used for MOTIONSENSE_CMD_DATA */ struct ec_response_motion_sensor_data data; @@ -2418,26 +3470,36 @@ struct __ec_todo_packed ec_response_motion_sense { /* Current value of the parameter queried. */ int32_t ret; } ec_rate, sensor_odr, sensor_range, kb_wake_angle, - fifo_int_enable, spoof; + fifo_int_enable, spoof; - /* Used for MOTIONSENSE_CMD_SENSOR_OFFSET */ - struct __ec_todo_unpacked { + /* + * Used for MOTIONSENSE_CMD_SENSOR_OFFSET, + * PERFORM_CALIB. + */ + struct __ec_todo_unpacked { int16_t temp; int16_t offset[3]; } sensor_offset, perform_calib; + /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ + struct __ec_todo_unpacked { + int16_t temp; + uint16_t scale[3]; + } sensor_scale; + struct ec_response_motion_sense_fifo_info fifo_info, fifo_flush; struct ec_response_motion_sense_fifo_data fifo_read; + struct ec_response_online_calibration_data online_calib_read; + struct __ec_todo_packed { uint16_t reserved; uint32_t enabled; uint32_t disabled; } list_activities; - struct __ec_todo_unpacked { - } set_activity; + /* No params for set activity */ /* Used for MOTIONSENSE_CMD_LID_ANGLE */ struct __ec_todo_unpacked { @@ -2447,8 +3509,25 @@ struct __ec_todo_packed ec_response_motion_sense { */ uint16_t value; } lid_angle; + + /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ + struct __ec_todo_unpacked { + /* + * Lid angle threshold for switching between tablet and + * clamshell mode. + */ + uint16_t lid_angle; + + /* Hysteresis degree. */ + uint16_t hys_degree; + } tablet_mode_threshold; + + /* USED for MOTIONSENSE_CMD_GET_ACTIVITY. */ + struct __ec_todo_unpacked { + uint8_t state; + } get_activity; }; -}; +} __ec_todo_packed; /*****************************************************************************/ /* Force lid open command */ @@ -2456,9 +3535,9 @@ struct __ec_todo_packed ec_response_motion_sense { /* Make lid event always open */ #define EC_CMD_FORCE_LID_OPEN 0x002C -struct __ec_align1 ec_params_force_lid_open { +struct ec_params_force_lid_open { uint8_t enabled; -}; +} __ec_align1; /*****************************************************************************/ /* Configure the behavior of the power button */ @@ -2466,13 +3545,13 @@ struct __ec_align1 ec_params_force_lid_open { enum ec_config_power_button_flags { /* Enable/Disable power button pulses for x86 devices */ - EC_POWER_BUTTON_ENABLE_PULSE = (1 << 0), + EC_POWER_BUTTON_ENABLE_PULSE = BIT(0), }; -struct __ec_align1 ec_params_config_power_button { +struct ec_params_config_power_button { /* See enum ec_config_power_button_flags */ uint8_t flags; -}; +} __ec_align1; /*****************************************************************************/ /* USB charging control commands */ @@ -2480,11 +3559,52 @@ struct __ec_align1 ec_params_config_power_button { /* Set USB port charging mode */ #define EC_CMD_USB_CHARGE_SET_MODE 0x0030 -struct __ec_align1 ec_params_usb_charge_set_mode { +enum usb_charge_mode { + /* Disable USB port. */ + USB_CHARGE_MODE_DISABLED, + /* Set USB port to Standard Downstream Port, USB 2.0 mode. */ + USB_CHARGE_MODE_SDP2, + /* Set USB port to Charging Downstream Port, BC 1.2. */ + USB_CHARGE_MODE_CDP, + /* Set USB port to Dedicated Charging Port, BC 1.2. */ + USB_CHARGE_MODE_DCP_SHORT, + /* Enable USB port (for dumb ports). */ + USB_CHARGE_MODE_ENABLED, + /* Set USB port to CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE. */ + USB_CHARGE_MODE_DEFAULT, + + USB_CHARGE_MODE_COUNT, +}; + +enum usb_suspend_charge { + /* Enable charging in suspend */ + USB_ALLOW_SUSPEND_CHARGE, + /* Disable charging in suspend */ + USB_DISALLOW_SUSPEND_CHARGE, +}; + +struct ec_params_usb_charge_set_mode { uint8_t usb_port_id; - uint8_t mode; + uint8_t mode : 7; /* enum usb_charge_mode */ + uint8_t inhibit_charge : 1; /* enum usb_suspend_charge */ +} __ec_align1; + +/*****************************************************************************/ +/* Tablet mode commands */ + +/* Set tablet mode */ +#define EC_CMD_SET_TABLET_MODE 0x0031 + +enum tablet_mode_override { + TABLET_MODE_DEFAULT, + TABLET_MODE_FORCE_TABLET, + TABLET_MODE_FORCE_CLAMSHELL, }; +struct ec_params_set_tablet_mode { + uint8_t tablet_mode; /* enum tablet_mode_override */ +} __ec_align1; + /*****************************************************************************/ /* Persistent storage for host */ @@ -2494,12 +3614,12 @@ struct __ec_align1 ec_params_usb_charge_set_mode { /* Get persistent storage info */ #define EC_CMD_PSTORE_INFO 0x0040 -struct __ec_align4 ec_response_pstore_info { +struct ec_response_pstore_info { /* Persistent storage size, in bytes */ uint32_t pstore_size; /* Access size; read/write offset and size must be a multiple of this */ uint32_t access_size; -}; +} __ec_align4; /* * Read persistent storage @@ -2508,31 +3628,31 @@ struct __ec_align4 ec_response_pstore_info { */ #define EC_CMD_PSTORE_READ 0x0041 -struct __ec_align4 ec_params_pstore_read { - uint32_t offset; /* Byte offset to read */ - uint32_t size; /* Size to read in bytes */ -}; +struct ec_params_pstore_read { + uint32_t offset; /* Byte offset to read */ + uint32_t size; /* Size to read in bytes */ +} __ec_align4; /* Write persistent storage */ #define EC_CMD_PSTORE_WRITE 0x0042 -struct __ec_align4 ec_params_pstore_write { - uint32_t offset; /* Byte offset to write */ - uint32_t size; /* Size to write in bytes */ +struct ec_params_pstore_write { + uint32_t offset; /* Byte offset to write */ + uint32_t size; /* Size to write in bytes */ uint8_t data[EC_PSTORE_SIZE_MAX]; -}; +} __ec_align4; /*****************************************************************************/ /* Real-time clock */ /* RTC params and response structures */ -struct __ec_align4 ec_params_rtc { +struct ec_params_rtc { uint32_t time; -}; +} __ec_align4; -struct __ec_align4 ec_response_rtc { +struct ec_response_rtc { uint32_t time; -}; +} __ec_align4; /* These use ec_response_rtc */ #define EC_CMD_RTC_GET_VALUE 0x0044 @@ -2560,17 +3680,17 @@ enum ec_port80_subcmd { EC_PORT80_READ_BUFFER, }; -struct __ec_todo_packed ec_params_port80_read { +struct ec_params_port80_read { uint16_t subcmd; union { struct __ec_todo_unpacked { uint32_t offset; uint32_t num_entries; } read_buffer; - }; -}; + } __ec_todo_packed; +} __ec_todo_packed; -struct __ec_todo_packed ec_response_port80_read { +struct ec_response_port80_read { union { struct __ec_todo_unpacked { uint32_t writes; @@ -2581,11 +3701,11 @@ struct __ec_todo_packed ec_response_port80_read { uint16_t codes[EC_PORT80_SIZE_MAX]; } data; }; -}; +} __ec_todo_packed; -struct __ec_align2 ec_response_port80_last_boot { +struct ec_response_port80_last_boot { uint16_t code; -}; +} __ec_align2; /*****************************************************************************/ /* Temporary secure storage for host verified boot use */ @@ -2598,12 +3718,12 @@ struct __ec_align2 ec_response_port80_last_boot { /* Get persistent storage info */ #define EC_CMD_VSTORE_INFO 0x0049 -struct __ec_align_size1 ec_response_vstore_info { +struct ec_response_vstore_info { /* Indicates which slots are locked */ uint32_t slot_locked; /* Total number of slots available */ uint8_t slot_count; -}; +} __ec_align_size1; /* * Read temporary secure storage @@ -2612,23 +3732,23 @@ struct __ec_align_size1 ec_response_vstore_info { */ #define EC_CMD_VSTORE_READ 0x004A -struct __ec_align1 ec_params_vstore_read { +struct ec_params_vstore_read { uint8_t slot; /* Slot to read from */ -}; +} __ec_align1; -struct __ec_align1 ec_response_vstore_read { +struct ec_response_vstore_read { uint8_t data[EC_VSTORE_SLOT_SIZE]; -}; +} __ec_align1; /* * Write temporary secure storage and lock it. */ #define EC_CMD_VSTORE_WRITE 0x004B -struct __ec_align1 ec_params_vstore_write { +struct ec_params_vstore_write { uint8_t slot; /* Slot to write to */ uint8_t data[EC_VSTORE_SLOT_SIZE]; -}; +} __ec_align1; /*****************************************************************************/ /* Thermal engine commands. Note that there are two implementations. We'll @@ -2645,21 +3765,21 @@ struct __ec_align1 ec_params_vstore_write { */ /* Version 0 - set */ -struct __ec_align2 ec_params_thermal_set_threshold { +struct ec_params_thermal_set_threshold { uint8_t sensor_type; uint8_t threshold_id; uint16_t value; -}; +} __ec_align2; /* Version 0 - get */ -struct __ec_align1 ec_params_thermal_get_threshold { +struct ec_params_thermal_get_threshold { uint8_t sensor_type; uint8_t threshold_id; -}; +} __ec_align1; -struct __ec_align2 ec_response_thermal_get_threshold { +struct ec_response_thermal_get_threshold { uint16_t value; -}; +} __ec_align2; /* The version 1 structs are visible. */ enum ec_temp_thresholds { @@ -2667,45 +3787,80 @@ enum ec_temp_thresholds { EC_TEMP_THRESH_HIGH, EC_TEMP_THRESH_HALT, - EC_TEMP_THRESH_COUNT + EC_TEMP_THRESH_COUNT, }; /* * Thermal configuration for one temperature sensor. Temps are in degrees K. * Zero values will be silently ignored by the thermal task. * + * Set 'temp_host' value allows thermal task to trigger some event with 1 degree + * hysteresis. + * For example, + * temp_host[EC_TEMP_THRESH_HIGH] = 300 K + * temp_host_release[EC_TEMP_THRESH_HIGH] = 0 K + * EC will throttle ap when temperature >= 301 K, and release throttling when + * temperature <= 299 K. + * + * Set 'temp_host_release' value allows thermal task has a custom hysteresis. + * For example, + * temp_host[EC_TEMP_THRESH_HIGH] = 300 K + * temp_host_release[EC_TEMP_THRESH_HIGH] = 295 K + * EC will throttle ap when temperature >= 301 K, and release throttling when + * temperature <= 294 K. + * * Note that this structure is a sub-structure of * ec_params_thermal_set_threshold_v1, but maintains its alignment there. */ -struct __ec_align4 ec_thermal_config { +struct ec_thermal_config { uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */ - uint32_t temp_fan_off; /* no active cooling needed */ - uint32_t temp_fan_max; /* max active cooling needed */ -}; + uint32_t temp_host_release[EC_TEMP_THRESH_COUNT]; /* release levels */ + uint32_t temp_fan_off; /* no active cooling needed */ + uint32_t temp_fan_max; /* max active cooling needed */ +} __ec_align4; /* Version 1 - get config for one sensor. */ -struct __ec_align4 ec_params_thermal_get_threshold_v1 { +struct ec_params_thermal_get_threshold_v1 { uint32_t sensor_num; -}; +} __ec_align4; /* This returns a struct ec_thermal_config */ -/* Version 1 - set config for one sensor. - * Use read-modify-write for best results! */ -struct __ec_align4 ec_params_thermal_set_threshold_v1 { +/* + * Version 1 - set config for one sensor. + * Use read-modify-write for best results! + */ +struct ec_params_thermal_set_threshold_v1 { uint32_t sensor_num; struct ec_thermal_config cfg; -}; +} __ec_align4; /* This returns no data */ /****************************************************************************/ -/* Toggle automatic fan control */ +/* Set or get fan control mode */ #define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x0052 +enum ec_auto_fan_ctrl_cmd { + EC_AUTO_FAN_CONTROL_CMD_SET = 0, + EC_AUTO_FAN_CONTROL_CMD_GET, +}; + /* Version 1 of input params */ -struct __ec_align1 ec_params_auto_fan_ctrl_v1 { +struct ec_params_auto_fan_ctrl_v1 { uint8_t fan_idx; -}; +} __ec_align1; + +/* Version 2 of input params */ +struct ec_params_auto_fan_ctrl_v2 { + uint8_t fan_idx; + uint8_t cmd; /* enum ec_auto_fan_ctrl_cmd */ + uint8_t set_auto; /* only used with EC_AUTO_FAN_CONTROL_CMD_SET - bool + */ +} __ec_align4; + +struct ec_response_auto_fan_control { + uint8_t is_auto; /* bool */ +} __ec_align1; /* Get/Set TMP006 calibration data */ #define EC_CMD_TMP006_GET_CALIBRATION 0x0053 @@ -2721,54 +3876,54 @@ struct __ec_align1 ec_params_auto_fan_ctrl_v1 { */ /* This is the same struct for both v0 and v1. */ -struct __ec_align1 ec_params_tmp006_get_calibration { +struct ec_params_tmp006_get_calibration { uint8_t index; -}; +} __ec_align1; /* Version 0 */ -struct __ec_align4 ec_response_tmp006_get_calibration_v0 { +struct ec_response_tmp006_get_calibration_v0 { float s0; float b0; float b1; float b2; -}; +} __ec_align4; -struct __ec_align4 ec_params_tmp006_set_calibration_v0 { +struct ec_params_tmp006_set_calibration_v0 { uint8_t index; uint8_t reserved[3]; float s0; float b0; float b1; float b2; -}; +} __ec_align4; /* Version 1 */ -struct __ec_align4 ec_response_tmp006_get_calibration_v1 { +struct ec_response_tmp006_get_calibration_v1 { uint8_t algorithm; uint8_t num_params; uint8_t reserved[2]; - float val[0]; -}; + float val[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; -struct __ec_align4 ec_params_tmp006_set_calibration_v1 { +struct ec_params_tmp006_set_calibration_v1 { uint8_t index; uint8_t algorithm; uint8_t num_params; uint8_t reserved; - float val[0]; -}; + float val[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; /* Read raw TMP006 data */ #define EC_CMD_TMP006_GET_RAW 0x0055 -struct __ec_align1 ec_params_tmp006_get_raw { +struct ec_params_tmp006_get_raw { uint8_t index; -}; +} __ec_align1; -struct __ec_align4 ec_response_tmp006_get_raw { - int32_t t; /* In 1/100 K */ - int32_t v; /* In nV */ -}; +struct ec_response_tmp006_get_raw { + int32_t t; /* In 1/100 K */ + int32_t v; /* In nV */ +} __ec_align4; /*****************************************************************************/ /* MKBP - Matrix KeyBoard Protocol */ @@ -2790,17 +3945,17 @@ struct __ec_align4 ec_response_tmp006_get_raw { */ #define EC_CMD_MKBP_INFO 0x0061 -struct __ec_align_size1 ec_response_mkbp_info { +struct ec_response_mkbp_info { uint32_t rows; uint32_t cols; /* Formerly "switches", which was 0. */ uint8_t reserved; -}; +} __ec_align_size1; -struct __ec_align1 ec_params_mkbp_info { +struct ec_params_mkbp_info { uint8_t info_type; uint8_t event_type; -}; +} __ec_align1; enum ec_mkbp_info_type { /* @@ -2844,11 +3999,11 @@ enum ec_mkbp_info_type { /* Simulate key press */ #define EC_CMD_MKBP_SIMULATE_KEY 0x0062 -struct __ec_align1 ec_params_mkbp_simulate_key { +struct ec_params_mkbp_simulate_key { uint8_t col; uint8_t row; uint8_t pressed; -}; +} __ec_align1; /* Configure keyboard scanning */ #define EC_CMD_MKBP_SET_CONFIG 0x0064 @@ -2856,17 +4011,17 @@ struct __ec_align1 ec_params_mkbp_simulate_key { /* flags */ enum mkbp_config_flags { - EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ + EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ }; enum mkbp_config_valid { - EC_MKBP_VALID_SCAN_PERIOD = 1 << 0, - EC_MKBP_VALID_POLL_TIMEOUT = 1 << 1, - EC_MKBP_VALID_MIN_POST_SCAN_DELAY = 1 << 3, - EC_MKBP_VALID_OUTPUT_SETTLE = 1 << 4, - EC_MKBP_VALID_DEBOUNCE_DOWN = 1 << 5, - EC_MKBP_VALID_DEBOUNCE_UP = 1 << 6, - EC_MKBP_VALID_FIFO_MAX_DEPTH = 1 << 7, + EC_MKBP_VALID_SCAN_PERIOD = BIT(0), + EC_MKBP_VALID_POLL_TIMEOUT = BIT(1), + EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3), + EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4), + EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5), + EC_MKBP_VALID_DEBOUNCE_UP = BIT(6), + EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7), }; /* @@ -2875,11 +4030,11 @@ enum mkbp_config_valid { * Note that this is used as a sub-structure of * ec_{params/response}_mkbp_get_config. */ -struct __ec_align_size1 ec_mkbp_config { - uint32_t valid_mask; /* valid fields */ - uint8_t flags; /* some flags (enum mkbp_config_flags) */ - uint8_t valid_flags; /* which flags are valid */ - uint16_t scan_period_us; /* period between start of scans */ +struct ec_mkbp_config { + uint32_t valid_mask; /* valid fields */ + uint8_t flags; /* some flags (enum mkbp_config_flags) */ + uint8_t valid_flags; /* which flags are valid */ + uint16_t scan_period_us; /* period between start of scans */ /* revert to interrupt mode after no activity for this long */ uint32_t poll_timeout_us; /* @@ -2890,29 +4045,29 @@ struct __ec_align_size1 ec_mkbp_config { uint16_t min_post_scan_delay_us; /* delay between setting up output and waiting for it to settle */ uint16_t output_settle_us; - uint16_t debounce_down_us; /* time for debounce on key down */ - uint16_t debounce_up_us; /* time for debounce on key up */ + uint16_t debounce_down_us; /* time for debounce on key down */ + uint16_t debounce_up_us; /* time for debounce on key up */ /* maximum depth to allow for fifo (0 = no keyscan output) */ uint8_t fifo_max_depth; -}; +} __ec_align_size1; -struct __ec_align_size1 ec_params_mkbp_set_config { +struct ec_params_mkbp_set_config { struct ec_mkbp_config config; -}; +} __ec_align_size1; -struct __ec_align_size1 ec_response_mkbp_get_config { +struct ec_response_mkbp_get_config { struct ec_mkbp_config config; -}; +} __ec_align_size1; /* Run the key scan emulation */ #define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066 enum ec_keyscan_seq_cmd { - EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */ - EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */ - EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */ - EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */ - EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */ + EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */ + EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */ + EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */ + EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */ + EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */ }; enum ec_collect_flags { @@ -2920,19 +4075,19 @@ enum ec_collect_flags { * Indicates this scan was processed by the EC. Due to timing, some * scans may be skipped. */ - EC_KEYSCAN_SEQ_FLAG_DONE = 1 << 0, + EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0), }; -struct __ec_align1 ec_collect_item { - uint8_t flags; /* some flags (enum ec_collect_flags) */ -}; +struct ec_collect_item { + uint8_t flags; /* some flags (enum ec_collect_flags) */ +} __ec_align1; -struct __ec_todo_packed ec_params_keyscan_seq_ctrl { - uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ +struct ec_params_keyscan_seq_ctrl { + uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ union { struct __ec_align1 { - uint8_t active; /* still active */ - uint8_t num_items; /* number of items */ + uint8_t active; /* still active */ + uint8_t num_items; /* number of items */ /* Current item being presented */ uint8_t cur_item; } status; @@ -2942,32 +4097,49 @@ struct __ec_todo_packed ec_params_keyscan_seq_ctrl { * start of the sequence. */ uint32_t time_us; - uint8_t scan[0]; /* keyscan data */ + /* keyscan data */ + uint8_t scan[FLEXIBLE_ARRAY_MEMBER_SIZE]; } add; struct __ec_align1 { - uint8_t start_item; /* First item to return */ - uint8_t num_items; /* Number of items to return */ + uint8_t start_item; /* First item to return */ + uint8_t num_items; /* Number of items to return */ } collect; }; -}; +} __ec_todo_packed; -struct __ec_todo_packed ec_result_keyscan_seq_ctrl { +struct ec_result_keyscan_seq_ctrl { union { struct __ec_todo_unpacked { - uint8_t num_items; /* Number of items */ + uint8_t num_items; /* Number of items */ /* Data for each item */ - struct ec_collect_item item[0]; + struct ec_collect_item item[FLEXIBLE_ARRAY_MEMBER_SIZE]; } collect; }; -}; +} __ec_todo_packed; /* * Get the next pending MKBP event. * * Returns EC_RES_UNAVAILABLE if there is no event pending. + * + * V0: ec_response_get_next_data + * V1: ec_response_get_next_data_v1. Increased key_matrix size from 13 -> 16. + * V2: Added EC_MKBP_HAS_MORE_EVENTS. + * V3: ec_response_get_next_data_v3. Increased key_matrix size from 16 -> 18. */ #define EC_CMD_GET_NEXT_EVENT 0x0067 +#define EC_MKBP_HAS_MORE_EVENTS_SHIFT 7 + +/* + * We use the most significant bit of the event type to indicate to the host + * that the EC has more MKBP events available to provide. + */ +#define EC_MKBP_HAS_MORE_EVENTS BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) + +/* The mask to apply to get the raw event type */ +#define EC_MKBP_EVENT_TYPE_MASK (BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) - 1) + enum ec_mkbp_event { /* Keyboard matrix changed. The event data is the new matrix state. */ EC_MKBP_EVENT_KEY_MATRIX = 0, @@ -2993,15 +4165,110 @@ enum ec_mkbp_event { */ EC_MKBP_EVENT_SYSRQ = 6, + /* + * New 64-bit host event. + * The event data is 8 bytes of host event flags. + */ + EC_MKBP_EVENT_HOST_EVENT64 = 7, + + /* Notify the AP that something happened on CEC */ + EC_MKBP_EVENT_CEC_EVENT = 8, + + /* Send an incoming CEC message to the AP */ + EC_MKBP_EVENT_CEC_MESSAGE = 9, + + /* We have entered DisplayPort Alternate Mode on a Type-C port. */ + EC_MKBP_EVENT_DP_ALT_MODE_ENTERED = 10, + + /* New online calibration values are available. */ + EC_MKBP_EVENT_ONLINE_CALIBRATION = 11, + + /* Peripheral device charger event */ + EC_MKBP_EVENT_PCHG = 12, + /* Number of MKBP events */ EC_MKBP_EVENT_COUNT, }; +BUILD_ASSERT(EC_MKBP_EVENT_COUNT <= EC_MKBP_EVENT_TYPE_MASK); + +/* clang-format off */ +#define EC_MKBP_EVENT_TEXT \ + { \ + [EC_MKBP_EVENT_KEY_MATRIX] = "KEY_MATRIX", \ + [EC_MKBP_EVENT_HOST_EVENT] = "HOST_EVENT", \ + [EC_MKBP_EVENT_SENSOR_FIFO] = "SENSOR_FIFO", \ + [EC_MKBP_EVENT_BUTTON] = "BUTTON", \ + [EC_MKBP_EVENT_SWITCH] = "SWITCH", \ + [EC_MKBP_EVENT_FINGERPRINT] = "FINGERPRINT", \ + [EC_MKBP_EVENT_SYSRQ] = "SYSRQ", \ + [EC_MKBP_EVENT_HOST_EVENT64] = "HOST_EVENT64", \ + [EC_MKBP_EVENT_CEC_EVENT] = "CEC_EVENT", \ + [EC_MKBP_EVENT_CEC_MESSAGE] = "CEC_MESSAGE", \ + [EC_MKBP_EVENT_DP_ALT_MODE_ENTERED] = "DP_ALT_MODE_ENTERED", \ + [EC_MKBP_EVENT_ONLINE_CALIBRATION] = "ONLINE_CALIBRATION", \ + [EC_MKBP_EVENT_PCHG] = "PCHG", \ + } +/* clang-format on */ union __ec_align_offset1 ec_response_get_next_data { uint8_t key_matrix[13]; /* Unaligned */ uint32_t host_event; + uint64_t host_event64; + + struct __ec_todo_unpacked { + /* For aligning the fifo_info */ + uint8_t reserved[3]; + struct ec_response_motion_sense_fifo_info info; + } sensor_fifo; + + uint32_t buttons; + + uint32_t switches; + + uint32_t fp_events; + + uint32_t sysrq; + + /* CEC events from enum mkbp_cec_event */ + uint32_t cec_events; +}; + +union __ec_align_offset1 ec_response_get_next_data_v1 { + uint8_t key_matrix[16]; + + /* Unaligned */ + uint32_t host_event; + uint64_t host_event64; + + struct __ec_todo_unpacked { + /* For aligning the fifo_info */ + uint8_t reserved[3]; + struct ec_response_motion_sense_fifo_info info; + } sensor_fifo; + + uint32_t buttons; + + uint32_t switches; + + uint32_t fp_events; + + uint32_t sysrq; + + /* CEC events from enum mkbp_cec_event */ + uint32_t cec_events; + + uint8_t cec_message[16]; +}; +BUILD_ASSERT(sizeof(union ec_response_get_next_data_v1) == 16); + +union __ec_align_offset1 ec_response_get_next_data_v3 { + uint8_t key_matrix[18]; + + /* Unaligned */ + uint32_t host_event; + uint64_t host_event64; struct __ec_todo_unpacked { /* For aligning the fifo_info */ @@ -3016,37 +4283,136 @@ union __ec_align_offset1 ec_response_get_next_data { uint32_t fp_events; uint32_t sysrq; + + /* CEC events from enum mkbp_cec_event */ + uint32_t cec_events; + + uint8_t cec_message[16]; }; +BUILD_ASSERT(sizeof(union ec_response_get_next_data_v3) == 18); -struct __ec_align1 ec_response_get_next_event { +struct ec_response_get_next_event { uint8_t event_type; /* Followed by event data if any */ union ec_response_get_next_data data; -}; +} __ec_align1; + +struct ec_response_get_next_event_v1 { + uint8_t event_type; + /* Followed by event data if any */ + union ec_response_get_next_data_v1 data; +} __ec_align1; + +struct ec_response_get_next_event_v3 { + uint8_t event_type; + /* Followed by event data if any */ + union ec_response_get_next_data_v3 data; +} __ec_align1; /* Bit indices for buttons and switches.*/ /* Buttons */ -#define EC_MKBP_POWER_BUTTON 0 -#define EC_MKBP_VOL_UP 1 -#define EC_MKBP_VOL_DOWN 2 -#define EC_MKBP_RECOVERY 3 +#define EC_MKBP_POWER_BUTTON 0 +#define EC_MKBP_VOL_UP 1 +#define EC_MKBP_VOL_DOWN 2 +#define EC_MKBP_RECOVERY 3 /* Switches */ -#define EC_MKBP_LID_OPEN 0 -#define EC_MKBP_TABLET_MODE 1 +#define EC_MKBP_LID_OPEN 0 +#define EC_MKBP_TABLET_MODE 1 +#define EC_MKBP_BASE_ATTACHED 2 +#define EC_MKBP_FRONT_PROXIMITY 3 /* Run keyboard factory test scanning */ #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 -struct __ec_align2 ec_response_keyboard_factory_test { - uint16_t shorted; /* Keyboard pins are shorted */ -}; +struct ec_response_keyboard_factory_test { + uint16_t shorted; /* Keyboard pins are shorted */ +} __ec_align2; /* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */ #define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF) -#define EC_MKBP_FP_FINGER_DOWN (1 << 29) -#define EC_MKBP_FP_FINGER_UP (1 << 30) -#define EC_MKBP_FP_IMAGE_READY (1 << 31) +#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events) & 0x0000000F) +#define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4 +#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) \ + (((fpe) & 0x00000FF0) >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET) +#define EC_MKBP_FP_MATCH_IDX_OFFSET 12 +#define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000 +#define EC_MKBP_FP_MATCH_IDX(fpe) \ + (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) >> EC_MKBP_FP_MATCH_IDX_OFFSET) +#define EC_MKBP_FP_ENROLL BIT(27) +#define EC_MKBP_FP_MATCH BIT(28) +#define EC_MKBP_FP_FINGER_DOWN BIT(29) +#define EC_MKBP_FP_FINGER_UP BIT(30) +#define EC_MKBP_FP_IMAGE_READY BIT(31) +/* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_ENROLL is set */ +#define EC_MKBP_FP_ERR_ENROLL_OK 0 +#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1 +#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2 +#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3 +#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5 +/* Can be used to detect if image was usable for enrollment or not. */ +#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1 +/* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_MATCH is set */ +#define EC_MKBP_FP_ERR_MATCH_NO 0 +#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6 +#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7 +#define EC_MKBP_FP_ERR_MATCH_NO_AUTH_FAIL 8 +#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2 +#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4 +#define EC_MKBP_FP_ERR_MATCH_YES 1 +#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3 +#define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5 + +#define EC_CMD_MKBP_WAKE_MASK 0x0069 +enum ec_mkbp_event_mask_action { + /* Retrieve the value of a wake mask. */ + GET_WAKE_MASK = 0, + + /* Set the value of a wake mask. */ + SET_WAKE_MASK, +}; + +enum ec_mkbp_mask_type { + /* + * These are host events sent via MKBP. + * + * Some examples are: + * EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) + * EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) + * + * The only things that should be in this mask are: + * EC_HOST_EVENT_MASK(EC_HOST_EVENT_*) + */ + EC_MKBP_HOST_EVENT_WAKE_MASK = 0, + + /* + * These are MKBP events. Some examples are: + * + * EC_MKBP_EVENT_KEY_MATRIX + * EC_MKBP_EVENT_SWITCH + * + * The only things that should be in this mask are EC_MKBP_EVENT_*. + */ + EC_MKBP_EVENT_WAKE_MASK, +}; + +struct ec_params_mkbp_event_wake_mask { + /* One of enum ec_mkbp_event_mask_action */ + uint8_t action; + + /* + * Which MKBP mask are you interested in acting upon? This is one of + * ec_mkbp_mask_type. + */ + uint8_t mask_type; + + /* If setting a new wake mask, this contains the mask to set. */ + uint32_t new_wake_mask; +}; + +struct ec_response_mkbp_event_wake_mask { + uint32_t wake_mask; +}; /*****************************************************************************/ /* Temperature sensor commands */ @@ -3054,14 +4420,14 @@ struct __ec_align2 ec_response_keyboard_factory_test { /* Read temperature sensor info */ #define EC_CMD_TEMP_SENSOR_GET_INFO 0x0070 -struct __ec_align1 ec_params_temp_sensor_get_info { +struct ec_params_temp_sensor_get_info { uint8_t id; -}; +} __ec_align1; -struct __ec_align1 ec_response_temp_sensor_get_info { +struct ec_response_temp_sensor_get_info { char sensor_name[32]; uint8_t sensor_type; -}; +} __ec_align1; /*****************************************************************************/ @@ -3074,39 +4440,42 @@ struct __ec_align1 ec_response_temp_sensor_get_info { /*****************************************************************************/ /* Host event commands */ -/* Obsolete. New implementation should use EC_CMD_PROGRAM_HOST_EVENT instead */ +/* Obsolete. New implementation should use EC_CMD_HOST_EVENT instead */ /* * Host event mask params and response structures, shared by all of the host * event commands below. */ -struct __ec_align4 ec_params_host_event_mask { +struct ec_params_host_event_mask { uint32_t mask; -}; +} __ec_align4; -struct __ec_align4 ec_response_host_event_mask { +struct ec_response_host_event_mask { uint32_t mask; -}; +} __ec_align4; /* These all use ec_response_host_event_mask */ -#define EC_CMD_HOST_EVENT_GET_B 0x0087 -#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088 -#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089 +#define EC_CMD_HOST_EVENT_GET_B 0x0087 +#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088 +#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089 #define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D /* These all use ec_params_host_event_mask */ -#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A -#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B -#define EC_CMD_HOST_EVENT_CLEAR 0x008C +#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A +#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B +#define EC_CMD_HOST_EVENT_CLEAR 0x008C #define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E -#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F +#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F /* * Unified host event programming interface - Should be used by newer versions * of BIOS/OS to program host events and masks + * + * EC returns: + * - EC_RES_INVALID_PARAM: Action or mask type is unknown. + * - EC_RES_ACCESS_DENIED: Action is prohibited for specified mask type. */ -struct __ec_align4 ec_params_host_event { - +struct ec_params_host_event { /* Action requested by host - one of enum ec_host_event_action. */ uint8_t action; @@ -3121,18 +4490,17 @@ struct __ec_align4 ec_params_host_event { /* Value to be used in case of set operations. */ uint64_t value; -}; +} __ec_align4; /* * Response structure returned by EC_CMD_HOST_EVENT. * Update the value on a GET request. Set to 0 on GET/CLEAR */ -struct __ec_align4 ec_response_host_event { - +struct ec_response_host_event { /* Mask value in case of get operation */ uint64_t value; -}; +} __ec_align4; enum ec_host_event_action { /* @@ -3178,7 +4546,7 @@ enum ec_host_event_mask_type { EC_HOST_EVENT_LAZY_WAKE_MASK_S5, }; -#define EC_CMD_HOST_EVENT 0x00A4 +#define EC_CMD_HOST_EVENT 0x00A4 /*****************************************************************************/ /* Switch commands */ @@ -3186,21 +4554,21 @@ enum ec_host_event_mask_type { /* Enable/disable LCD backlight */ #define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x0090 -struct __ec_align1 ec_params_switch_enable_backlight { +struct ec_params_switch_enable_backlight { uint8_t enabled; -}; +} __ec_align1; /* Enable/disable WLAN/Bluetooth */ #define EC_CMD_SWITCH_ENABLE_WIRELESS 0x0091 #define EC_VER_SWITCH_ENABLE_WIRELESS 1 /* Version 0 params; no response */ -struct __ec_align1 ec_params_switch_enable_wireless_v0 { +struct ec_params_switch_enable_wireless_v0 { uint8_t enabled; -}; +} __ec_align1; /* Version 1 params */ -struct __ec_align1 ec_params_switch_enable_wireless_v1 { +struct ec_params_switch_enable_wireless_v1 { /* Flags to enable now */ uint8_t now_flags; @@ -3216,16 +4584,16 @@ struct __ec_align1 ec_params_switch_enable_wireless_v1 { /* Which flags to copy from suspend_flags */ uint8_t suspend_mask; -}; +} __ec_align1; /* Version 1 response */ -struct __ec_align1 ec_response_switch_enable_wireless_v1 { +struct ec_response_switch_enable_wireless_v1 { /* Flags to enable now */ uint8_t now_flags; /* Flags to leave enabled in S3 */ uint8_t suspend_flags; -}; +} __ec_align1; /*****************************************************************************/ /* GPIO commands. Only available on EC if write protect has been disabled. */ @@ -3233,25 +4601,25 @@ struct __ec_align1 ec_response_switch_enable_wireless_v1 { /* Set GPIO output value */ #define EC_CMD_GPIO_SET 0x0092 -struct __ec_align1 ec_params_gpio_set { +struct ec_params_gpio_set { char name[32]; uint8_t val; -}; +} __ec_align1; /* Get GPIO value */ #define EC_CMD_GPIO_GET 0x0093 /* Version 0 of input params and response */ -struct __ec_align1 ec_params_gpio_get { +struct ec_params_gpio_get { char name[32]; -}; +} __ec_align1; -struct __ec_align1 ec_response_gpio_get { +struct ec_response_gpio_get { uint8_t val; -}; +} __ec_align1; /* Version 1 of input params and response */ -struct __ec_align1 ec_params_gpio_get_v1 { +struct ec_params_gpio_get_v1 { uint8_t subcmd; union { struct __ec_align1 { @@ -3261,9 +4629,9 @@ struct __ec_align1 ec_params_gpio_get_v1 { uint8_t index; } get_info; }; -}; +} __ec_align1; -struct __ec_todo_packed ec_response_gpio_get_v1 { +struct ec_response_gpio_get_v1 { union { struct __ec_align1 { uint8_t val; @@ -3274,7 +4642,7 @@ struct __ec_todo_packed ec_response_gpio_get_v1 { uint32_t flags; } get_info; }; -}; +} __ec_todo_packed; enum gpio_get_subcmd { EC_GPIO_GET_BY_NAME = 0, @@ -3295,27 +4663,27 @@ enum gpio_get_subcmd { /* Read I2C bus */ #define EC_CMD_I2C_READ 0x0094 -struct __ec_align_size1 ec_params_i2c_read { +struct ec_params_i2c_read { uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t read_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; -}; +} __ec_align_size1; -struct __ec_align2 ec_response_i2c_read { +struct ec_response_i2c_read { uint16_t data; -}; +} __ec_align2; /* Write I2C bus */ #define EC_CMD_I2C_WRITE 0x0095 -struct __ec_align_size1 ec_params_i2c_write { +struct ec_params_i2c_write { uint16_t data; uint16_t addr; /* 8-bit address (7-bit shifted << 1) */ uint8_t write_size; /* Either 8 or 16. */ uint8_t port; uint8_t offset; -}; +} __ec_align_size1; /*****************************************************************************/ /* Charge state commands. Only available when flash write protect unlocked. */ @@ -3324,20 +4692,64 @@ struct __ec_align_size1 ec_params_i2c_write { * discharge the battery. */ #define EC_CMD_CHARGE_CONTROL 0x0096 -#define EC_VER_CHARGE_CONTROL 1 +#define EC_VER_CHARGE_CONTROL 3 enum ec_charge_control_mode { CHARGE_CONTROL_NORMAL = 0, CHARGE_CONTROL_IDLE, CHARGE_CONTROL_DISCHARGE, + /* Add no more entry below. */ + CHARGE_CONTROL_COUNT, +}; + +#define EC_CHARGE_MODE_TEXT \ + { \ + [CHARGE_CONTROL_NORMAL] = "NORMAL", \ + [CHARGE_CONTROL_IDLE] = "IDLE", \ + [CHARGE_CONTROL_DISCHARGE] = "DISCHARGE", \ + } + +enum ec_charge_control_cmd { + EC_CHARGE_CONTROL_CMD_SET = 0, + EC_CHARGE_CONTROL_CMD_GET, }; -struct __ec_align4 ec_params_charge_control { - uint32_t mode; /* enum charge_control_mode */ +enum ec_charge_control_flag { + EC_CHARGE_CONTROL_FLAG_NO_IDLE = BIT(0), }; +struct ec_params_charge_control { + uint32_t mode; /* enum charge_control_mode */ + + /* Below are the fields added in V2. */ + uint8_t cmd; /* enum ec_charge_control_cmd. */ + uint8_t flags; /* enum ec_charge_control_flag (v3+) */ + /* + * Lower and upper thresholds for battery sustainer. This struct isn't + * named to avoid tainting foreign projects' name spaces. + * + * If charge mode is explicitly set (e.g. DISCHARGE), battery sustainer + * will be disabled. To disable battery sustainer, set mode=NORMAL, + * lower=-1, upper=-1. + */ + struct { + int8_t lower; /* Display SoC in percentage. */ + int8_t upper; /* Display SoC in percentage. */ + } sustain_soc; +} __ec_align4; + +/* Added in v2 */ +struct ec_response_charge_control { + uint32_t mode; /* enum charge_control_mode */ + struct { /* Battery sustainer thresholds */ + int8_t lower; + int8_t upper; + } sustain_soc; + uint8_t flags; /* enum ec_charge_control_flag (v3+) */ + uint8_t reserved; +} __ec_align4; + /*****************************************************************************/ -/* Console commands. Only available when flash write protect is unlocked. */ /* Snapshot console output buffer for use by EC_CMD_CONSOLE_READ. */ #define EC_CMD_CONSOLE_SNAPSHOT 0x0097 @@ -3358,12 +4770,15 @@ struct __ec_align4 ec_params_charge_control { enum ec_console_read_subcmd { CONSOLE_READ_NEXT = 0, - CONSOLE_READ_RECENT + CONSOLE_READ_RECENT, }; -struct __ec_align1 ec_params_console_read_v1 { +struct ec_params_console_read_v1 { uint8_t subcmd; /* enum ec_console_read_subcmd */ -}; +} __ec_align1; + +/* Print directly to EC console from host. */ +#define EC_CMD_CONSOLE_PRINT 0x00AC /*****************************************************************************/ @@ -3376,11 +4791,11 @@ struct __ec_align1 ec_params_console_read_v1 { */ #define EC_CMD_BATTERY_CUT_OFF 0x0099 -#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN (1 << 0) +#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0) -struct __ec_align1 ec_params_battery_cutoff { +struct ec_params_battery_cutoff { uint8_t flags; -}; +} __ec_align1; /*****************************************************************************/ /* USB port mux control. */ @@ -3390,16 +4805,16 @@ struct __ec_align1 ec_params_battery_cutoff { */ #define EC_CMD_USB_MUX 0x009A -struct __ec_align1 ec_params_usb_mux { +struct ec_params_usb_mux { uint8_t mux; -}; +} __ec_align1; /*****************************************************************************/ /* LDOs / FETs control. */ enum ec_ldo_state { - EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */ - EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */ + EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */ + EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */ }; /* @@ -3407,39 +4822,92 @@ enum ec_ldo_state { */ #define EC_CMD_LDO_SET 0x009B -struct __ec_align1 ec_params_ldo_set { +struct ec_params_ldo_set { uint8_t index; uint8_t state; -}; +} __ec_align1; /* * Get LDO state. */ #define EC_CMD_LDO_GET 0x009C -struct __ec_align1 ec_params_ldo_get { +struct ec_params_ldo_get { uint8_t index; -}; +} __ec_align1; -struct __ec_align1 ec_response_ldo_get { +struct ec_response_ldo_get { uint8_t state; -}; +} __ec_align1; /*****************************************************************************/ /* Power info. */ /* * Get power info. + * + * Note: v0 of this command is deprecated */ #define EC_CMD_POWER_INFO 0x009D -struct __ec_align4 ec_response_power_info { - uint32_t usb_dev_type; - uint16_t voltage_ac; - uint16_t voltage_system; - uint16_t current_system; - uint16_t usb_current_limit; -}; +/* + * v1 of EC_CMD_POWER_INFO + */ +enum system_power_source { + /* + * Haven't established which power source is used yet, + * or no presence signals are available + */ + POWER_SOURCE_UNKNOWN = 0, + /* System is running on battery alone */ + POWER_SOURCE_BATTERY = 1, + /* System is running on A/C alone */ + POWER_SOURCE_AC = 2, + /* System is running on A/C and battery */ + POWER_SOURCE_AC_BATTERY = 3, +}; + +struct ec_response_power_info_v1 { + /* enum system_power_source */ + uint8_t system_power_source; + /* Battery state-of-charge, 0-100, 0 if not present */ + uint8_t battery_soc; + /* AC Adapter 100% rating, Watts */ + uint8_t ac_adapter_100pct; + /* AC Adapter 10ms rating, Watts */ + uint8_t ac_adapter_10ms; + /* Battery 1C rating, derated */ + uint8_t battery_1cd; + /* Rest of Platform average, Watts */ + uint8_t rop_avg; + /* Rest of Platform peak, Watts */ + uint8_t rop_peak; + /* Nominal charger efficiency, % */ + uint8_t nominal_charger_eff; + /* Rest of Platform VR Average Efficiency, % */ + uint8_t rop_avg_eff; + /* Rest of Platform VR Peak Efficiency, % */ + uint8_t rop_peak_eff; + /* SoC VR Efficiency at Average level, % */ + uint8_t soc_avg_eff; + /* SoC VR Efficiency at Peak level, % */ + uint8_t soc_peak_eff; + /* Intel-specific items */ + struct { + /* Battery's level of DBPT support: 0, 2 */ + uint8_t batt_dbpt_support_level; + /* + * Maximum peak power from battery (10ms), Watts + * If DBPT is not supported, this is 0 + */ + uint8_t batt_dbpt_max_peak_power; + /* + * Sustained peak power from battery, Watts + * If DBPT is not supported, this is 0 + */ + uint8_t batt_dbpt_sus_peak_power; + } intel; +} __ec_align1; /*****************************************************************************/ /* I2C passthru command */ @@ -3447,90 +4915,81 @@ struct __ec_align4 ec_response_power_info { #define EC_CMD_I2C_PASSTHRU 0x009E /* Read data; if not present, message is a write */ -#define EC_I2C_FLAG_READ (1 << 15) +#define EC_I2C_FLAG_READ BIT(15) /* Mask for address */ -#define EC_I2C_ADDR_MASK 0x3ff +#define EC_I2C_ADDR_MASK 0x3ff -#define EC_I2C_STATUS_NAK (1 << 0) /* Transfer was not acknowledged */ -#define EC_I2C_STATUS_TIMEOUT (1 << 1) /* Timeout during transfer */ +#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */ +#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */ /* Any error */ -#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) +#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) -struct __ec_align2 ec_params_i2c_passthru_msg { - uint16_t addr_flags; /* I2C slave address (7 or 10 bits) and flags */ - uint16_t len; /* Number of bytes to read or write */ -}; +struct ec_params_i2c_passthru_msg { + uint16_t addr_flags; /* I2C peripheral address and flags */ + uint16_t len; /* Number of bytes to read or write */ +} __ec_align2; -struct __ec_align2 ec_params_i2c_passthru { - uint8_t port; /* I2C port number */ - uint8_t num_msgs; /* Number of messages */ - struct ec_params_i2c_passthru_msg msg[]; +struct ec_params_i2c_passthru { + uint8_t port; /* I2C port number */ + uint8_t num_msgs; /* Number of messages */ + struct ec_params_i2c_passthru_msg msg[FLEXIBLE_ARRAY_MEMBER_SIZE]; /* Data to write for all messages is concatenated here */ -}; +} __ec_align2; -struct __ec_align1 ec_response_i2c_passthru { - uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ - uint8_t num_msgs; /* Number of messages processed */ - uint8_t data[]; /* Data read by messages concatenated here */ -}; +struct ec_response_i2c_passthru { + uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ + uint8_t num_msgs; /* Number of messages processed */ + /* Data read by messages concatenated here */ + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align1; /*****************************************************************************/ -/* Power button hang detect */ - +/* AP hang detect */ #define EC_CMD_HANG_DETECT 0x009F -/* Reasons to start hang detection timer */ -/* Power button pressed */ -#define EC_HANG_START_ON_POWER_PRESS (1 << 0) - -/* Lid closed */ -#define EC_HANG_START_ON_LID_CLOSE (1 << 1) +#define EC_HANG_DETECT_MIN_TIMEOUT 5 - /* Lid opened */ -#define EC_HANG_START_ON_LID_OPEN (1 << 2) +/* EC hang detect commands */ +enum ec_hang_detect_cmds { + /* Reload AP hang detect timer. */ + EC_HANG_DETECT_CMD_RELOAD = 0x0, -/* Start of AP S3->S0 transition (booting or resuming from suspend) */ -#define EC_HANG_START_ON_RESUME (1 << 3) + /* Stop AP hang detect timer. */ + EC_HANG_DETECT_CMD_CANCEL = 0x1, -/* Reasons to cancel hang detection */ - -/* Power button released */ -#define EC_HANG_STOP_ON_POWER_RELEASE (1 << 8) + /* Configure watchdog with given reboot timeout and + * cancel currently running AP hand detect timer. + */ + EC_HANG_DETECT_CMD_SET_TIMEOUT = 0x2, -/* Any host command from AP received */ -#define EC_HANG_STOP_ON_HOST_COMMAND (1 << 9) + /* Get last hang status - whether the AP boot was clear or not */ + EC_HANG_DETECT_CMD_GET_STATUS = 0x3, -/* Stop on end of AP S0->S3 transition (suspending or shutting down) */ -#define EC_HANG_STOP_ON_SUSPEND (1 << 10) + /* Clear last hang status. Called when AP is rebooting/shutting down + * gracefully. + */ + EC_HANG_DETECT_CMD_CLEAR_STATUS = 0x4 +}; -/* - * If this flag is set, all the other fields are ignored, and the hang detect - * timer is started. This provides the AP a way to start the hang timer - * without reconfiguring any of the other hang detect settings. Note that - * you must previously have configured the timeouts. - */ -#define EC_HANG_START_NOW (1 << 30) +struct ec_params_hang_detect { + uint16_t command; /* enum ec_hang_detect_cmds */ + /* Timeout in seconds before generating reboot */ + uint16_t reboot_timeout_sec; +} __ec_align2; -/* - * If this flag is set, all the other fields are ignored (including - * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer - * without reconfiguring any of the other hang detect settings. +/* Status codes that describe whether AP has boot normally or the hang has been + * detected and EC has reset AP */ -#define EC_HANG_STOP_NOW (1 << 31) - -struct __ec_align4 ec_params_hang_detect { - /* Flags; see EC_HANG_* */ - uint32_t flags; - - /* Timeout in msec before generating host event, if enabled */ - uint16_t host_event_timeout_msec; - - /* Timeout in msec before generating warm reboot, if enabled */ - uint16_t warm_reboot_timeout_msec; -}; - +enum ec_hang_detect_status { + EC_HANG_DETECT_AP_BOOT_NORMAL = 0x0, + EC_HANG_DETECT_AP_BOOT_EC_WDT = 0x1, + EC_HANG_DETECT_AP_BOOT_COUNT, +}; +struct ec_response_hang_detect { + uint8_t status; /* enum ec_hang_detect_status */ +} __ec_align1; /*****************************************************************************/ /* Commands for battery charging */ @@ -3545,7 +5004,7 @@ enum charge_state_command { CHARGE_STATE_CMD_GET_STATE, CHARGE_STATE_CMD_GET_PARAM, CHARGE_STATE_CMD_SET_PARAM, - CHARGE_STATE_NUM_CMDS + CHARGE_STATE_NUM_CMDS, }; /* @@ -3553,16 +5012,62 @@ enum charge_state_command { * params, which are handled by the particular implementations. */ enum charge_state_params { - CS_PARAM_CHG_VOLTAGE, /* charger voltage limit */ - CS_PARAM_CHG_CURRENT, /* charger current limit */ - CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */ - CS_PARAM_CHG_STATUS, /* charger-specific status */ - CS_PARAM_CHG_OPTION, /* charger-specific options */ - CS_PARAM_LIMIT_POWER, /* - * Check if power is limited due to - * low battery and / or a weak external - * charger. READ ONLY. - */ + /* charger voltage limit */ + CS_PARAM_CHG_VOLTAGE, + + /* charger current limit */ + CS_PARAM_CHG_CURRENT, + + /* charger input current limit */ + CS_PARAM_CHG_INPUT_CURRENT, + + /* charger-specific status */ + CS_PARAM_CHG_STATUS, + + /* charger-specific options */ + CS_PARAM_CHG_OPTION, + + /* + * Check if power is limited due to low battery and / or a + * weak external charger. READ ONLY. + */ + CS_PARAM_LIMIT_POWER, + + /* min value of charger voltage limit (READ ONLY) */ + CS_PARAM_CHG_VOLTAGE_MIN, + + /* max value of charger voltage limit (READ ONLY) */ + CS_PARAM_CHG_VOLTAGE_MAX, + + /* step value of charger voltage limit (READ ONLY) */ + CS_PARAM_CHG_VOLTAGE_STEP, + + /* min value of charger current limit (READ ONLY) */ + CS_PARAM_CHG_CURRENT_MIN, + + /* max value of charger current limit (READ ONLY) */ + CS_PARAM_CHG_CURRENT_MAX, + + /* step value of charger current limit (READ ONLY) */ + CS_PARAM_CHG_CURRENT_STEP, + + /* min value of charger input current limit (READ ONLY) */ + CS_PARAM_CHG_INPUT_CURRENT_MIN, + + /* max value of charger input current limit (READ ONLY) */ + CS_PARAM_CHG_INPUT_CURRENT_MAX, + + /* step value of charger input current limit (READ ONLY) */ + CS_PARAM_CHG_INPUT_CURRENT_STEP, + + /* Minimum required voltage for hybrid boost chargers (READ ONLY) */ + CS_PARAM_CHG_MIN_REQUIRED_MV, + + /* For hybrid boost chargers returns !=0 when attached charger is + * capable of charging the battery + */ + CS_PARAM_CHG_IS_ADAPTER_SUFFICIENT, + /* How many so far? */ CS_NUM_BASE_PARAMS, @@ -3570,28 +5075,38 @@ enum charge_state_params { CS_PARAM_CUSTOM_PROFILE_MIN = 0x10000, CS_PARAM_CUSTOM_PROFILE_MAX = 0x1ffff, + /* Range for CONFIG_CHARGE_STATE_DEBUG params */ + CS_PARAM_DEBUG_MIN = 0x20000, + CS_PARAM_DEBUG_CTL_MODE = 0x20000, + CS_PARAM_DEBUG_MANUAL_MODE, + CS_PARAM_DEBUG_SEEMS_DEAD, + CS_PARAM_DEBUG_SEEMS_DISCONNECTED, + CS_PARAM_DEBUG_BATT_REMOVED, /* Deprecated */ + CS_PARAM_DEBUG_MANUAL_CURRENT, + CS_PARAM_DEBUG_MANUAL_VOLTAGE, + CS_PARAM_DEBUG_MAX = 0x2ffff, + /* Other custom param ranges go here... */ }; -struct __ec_todo_packed ec_params_charge_state { - uint8_t cmd; /* enum charge_state_command */ +struct ec_params_charge_state { + uint8_t cmd; /* enum charge_state_command */ union { - struct __ec_align1 { - /* no args */ - } get_state; + /* get_state has no args */ struct __ec_todo_unpacked { - uint32_t param; /* enum charge_state_param */ + uint32_t param; /* enum charge_state_param */ } get_param; struct __ec_todo_unpacked { - uint32_t param; /* param to set */ - uint32_t value; /* value to set */ + uint32_t param; /* param to set */ + uint32_t value; /* value to set */ } set_param; - }; -}; + } __ec_todo_packed; + uint8_t chgnum; /* Version 1 supports chgnum */ +} __ec_todo_packed; -struct __ec_align4 ec_response_charge_state { +struct ec_response_charge_state { union { struct __ec_align4 { int ac; @@ -3604,20 +5119,30 @@ struct __ec_align4 ec_response_charge_state { struct __ec_align4 { uint32_t value; } get_param; - struct __ec_align4 { - /* no return values */ - } set_param; + + /* set_param returns no args */ }; -}; +} __ec_align4; /* * Set maximum battery charging current. */ #define EC_CMD_CHARGE_CURRENT_LIMIT 0x00A1 +#define EC_VER_CHARGE_CURRENT_LIMIT 1 -struct __ec_align4 ec_params_current_limit { +struct ec_params_current_limit { uint32_t limit; /* in mA */ -}; +} __ec_align4; + +struct ec_params_current_limit_v1 { + uint32_t limit; /* in mA */ + /* + * Battery state of charge is the minimum charge percentage at which + * the battery charge current limit will apply. + * When not set, the limit will apply regardless of state of charge. + */ + uint8_t battery_soc; /* battery state of charge, 0-100 */ +} __ec_align4; /* * Set maximum external voltage / current. @@ -3625,10 +5150,10 @@ struct __ec_align4 ec_params_current_limit { #define EC_CMD_EXTERNAL_POWER_LIMIT 0x00A2 /* Command v0 is used only on Spring and is obsolete + unsupported */ -struct __ec_align2 ec_params_external_power_limit_v1 { +struct ec_params_external_power_limit_v1 { uint16_t current_lim; /* in mA, or EC_POWER_LIMIT_NONE to clear limit */ uint16_t voltage_lim; /* in mV, or EC_POWER_LIMIT_NONE to clear limit */ -}; +} __ec_align2; #define EC_POWER_LIMIT_NONE 0xffff @@ -3637,9 +5162,42 @@ struct __ec_align2 ec_params_external_power_limit_v1 { */ #define EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT 0x00A3 -struct __ec_align2 ec_params_dedicated_charger_limit { +struct ec_params_dedicated_charger_limit { uint16_t current_lim; /* in mA */ uint16_t voltage_lim; /* in mV */ +} __ec_align2; + +/* + * Get and set charging splashscreen variables + */ +#define EC_CMD_CHARGESPLASH 0x00A5 + +enum ec_chargesplash_cmd { + /* Get the current state variables */ + EC_CHARGESPLASH_GET_STATE = 0, + + /* Indicate initialization of the display loop */ + EC_CHARGESPLASH_DISPLAY_READY, + + /* Manually put the EC into the requested state */ + EC_CHARGESPLASH_REQUEST, + + /* Reset all state variables */ + EC_CHARGESPLASH_RESET, + + /* Manually trigger a lockout */ + EC_CHARGESPLASH_LOCKOUT, +}; + +struct __ec_align1 ec_params_chargesplash { + /* enum ec_chargesplash_cmd */ + uint8_t cmd; +}; + +struct __ec_align1 ec_response_chargesplash { + uint8_t requested; + uint8_t display_initialized; + uint8_t locked_out; }; /*****************************************************************************/ @@ -3648,15 +5206,15 @@ struct __ec_align2 ec_params_dedicated_charger_limit { /* Set the delay before going into hibernation. */ #define EC_CMD_HIBERNATION_DELAY 0x00A8 -struct __ec_align4 ec_params_hibernation_delay { +struct ec_params_hibernation_delay { /* * Seconds to wait in G3 before hibernate. Pass in 0 to read the * current settings without changing them. */ uint32_t seconds; -}; +} __ec_align4; -struct __ec_align4 ec_response_hibernation_delay { +struct ec_response_hibernation_delay { /* * The current time in seconds in which the system has been in the G3 * state. This value is reset if the EC transitions out of G3. @@ -3674,21 +5232,80 @@ struct __ec_align4 ec_response_hibernation_delay { * hibernating. */ uint32_t hibernate_delay; -}; +} __ec_align4; /* Inform the EC when entering a sleep state */ #define EC_CMD_HOST_SLEEP_EVENT 0x00A9 enum host_sleep_event { - HOST_SLEEP_EVENT_S3_SUSPEND = 1, - HOST_SLEEP_EVENT_S3_RESUME = 2, + HOST_SLEEP_EVENT_S3_SUSPEND = 1, + HOST_SLEEP_EVENT_S3_RESUME = 2, HOST_SLEEP_EVENT_S0IX_SUSPEND = 3, - HOST_SLEEP_EVENT_S0IX_RESUME = 4 + HOST_SLEEP_EVENT_S0IX_RESUME = 4, + /* S3 suspend with additional enabled wake sources */ + HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5, }; -struct __ec_align1 ec_params_host_sleep_event { +struct ec_params_host_sleep_event { uint8_t sleep_event; -}; +} __ec_align1; + +/* + * Use a default timeout value (CONFIG_SLEEP_TIMEOUT_MS) for detecting sleep + * transition failures + */ +#define EC_HOST_SLEEP_TIMEOUT_DEFAULT 0 + +/* Disable timeout detection for this sleep transition */ +#define EC_HOST_SLEEP_TIMEOUT_INFINITE 0xFFFF + +struct ec_params_host_sleep_event_v1 { + /* The type of sleep being entered or exited. */ + uint8_t sleep_event; + + /* Padding */ + uint8_t reserved; + union { + /* Parameters that apply for suspend messages. */ + struct { + /* + * The timeout in milliseconds between when this message + * is received and when the EC will declare sleep + * transition failure if the sleep signal is not + * asserted. + */ + uint16_t sleep_timeout_ms; + } suspend_params; + + /* No parameters for non-suspend messages. */ + }; +} __ec_align2; + +/* A timeout occurred when this bit is set */ +#define EC_HOST_RESUME_SLEEP_TIMEOUT 0x80000000 + +/* + * The mask defining which bits correspond to the number of sleep transitions, + * as well as the maximum number of suspend line transitions that will be + * reported back to the host. + */ +#define EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK 0x7FFFFFFF + +struct ec_response_host_sleep_event_v1 { + union { + /* Response fields that apply for resume messages. */ + struct { + /* + * The number of sleep power signal transitions that + * occurred since the suspend message. The high bit + * indicates a timeout occurred. + */ + uint32_t sleep_transitions; + } resume_response; + + /* No response fields for non-resume messages. */ + }; +} __ec_align4; /*****************************************************************************/ /* Device events */ @@ -3698,6 +5315,7 @@ enum ec_device_event { EC_DEVICE_EVENT_TRACKPAD, EC_DEVICE_EVENT_DSP, EC_DEVICE_EVENT_WIFI, + EC_DEVICE_EVENT_WLC, }; enum ec_device_event_param { @@ -3709,51 +5327,57 @@ enum ec_device_event_param { EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS, }; -#define EC_DEVICE_EVENT_MASK(event_code) (1UL << (event_code % 32)) +#define EC_DEVICE_EVENT_MASK(event_code) BIT(event_code % 32) -struct __ec_align_size1 ec_params_device_event { +struct ec_params_device_event { uint32_t event_mask; uint8_t param; -}; +} __ec_align_size1; -struct __ec_align4 ec_response_device_event { +struct ec_response_device_event { uint32_t event_mask; -}; +} __ec_align4; /*****************************************************************************/ -/* Smart battery pass-through */ +/* Get s0ix counter */ +#define EC_CMD_GET_S0IX_COUNTER 0x00AB -/* Get / Set 16-bit smart battery registers */ -#define EC_CMD_SB_READ_WORD 0x00B0 -#define EC_CMD_SB_WRITE_WORD 0x00B1 +/* Flag use to reset the counter */ +#define EC_S0IX_COUNTER_RESET 0x1 -/* Get / Set string smart battery parameters - * formatted as SMBUS "block". - */ -#define EC_CMD_SB_READ_BLOCK 0x00B2 -#define EC_CMD_SB_WRITE_BLOCK 0x00B3 +struct ec_params_s0ix_cnt { + /* If EC_S0IX_COUNTER_RESET then reset otherwise get the counter */ + uint32_t flags; +} __ec_align4; -struct __ec_align1 ec_params_sb_rd { - uint8_t reg; -}; +struct ec_response_s0ix_cnt { + /* Value of the s0ix_counter */ + uint32_t s0ix_counter; +} __ec_align4; -struct __ec_align2 ec_response_sb_rd_word { - uint16_t value; -}; +/*****************************************************************************/ +/* Ask the EC for sleep_signal_transitions without needing to send a + * HOST_SLEEP_EVENT command, which this command is related to. + * Note: EC_CMD_CONSOLE_PRINT has value 0x00AC, so skip over it. + */ +#define EC_CMD_HOST_SLEEP_SIGNAL_TRANSITIONS 0x00AD -struct __ec_align1 ec_params_sb_wr_word { - uint8_t reg; - uint16_t value; -}; +struct ec_response_host_sleep_signal_transitions { + uint32_t sleep_signal_transitions; +} __ec_align4; -struct __ec_align1 ec_response_sb_rd_block { - uint8_t data[32]; -}; +/*****************************************************************************/ +/* Smart battery pass-through */ -struct __ec_align1 ec_params_sb_wr_block { - uint8_t reg; - uint16_t data[32]; -}; +/* Get / Set 16-bit smart battery registers - OBSOLETE */ +#define EC_CMD_SB_READ_WORD 0x00B0 +#define EC_CMD_SB_WRITE_WORD 0x00B1 + +/* Get / Set string smart battery parameters + * formatted as SMBUS "block". - OBSOLETE + */ +#define EC_CMD_SB_READ_BLOCK 0x00B2 +#define EC_CMD_SB_WRITE_BLOCK 0x00B3 /*****************************************************************************/ /* Battery vendor parameters @@ -3771,90 +5395,39 @@ enum ec_battery_vendor_param_mode { BATTERY_VENDOR_PARAM_MODE_SET, }; -struct __ec_align_size1 ec_params_battery_vendor_param { +struct ec_params_battery_vendor_param { uint32_t param; uint32_t value; uint8_t mode; -}; +} __ec_align_size1; -struct __ec_align4 ec_response_battery_vendor_param { +struct ec_response_battery_vendor_param { uint32_t value; -}; +} __ec_align4; /*****************************************************************************/ /* - * Smart Battery Firmware Update Commands + * Smart Battery Firmware Update Command - OBSOLETE */ #define EC_CMD_SB_FW_UPDATE 0x00B5 -enum ec_sb_fw_update_subcmd { - EC_SB_FW_UPDATE_PREPARE = 0x0, - EC_SB_FW_UPDATE_INFO = 0x1, /*query sb info */ - EC_SB_FW_UPDATE_BEGIN = 0x2, /*check if protected */ - EC_SB_FW_UPDATE_WRITE = 0x3, /*check if protected */ - EC_SB_FW_UPDATE_END = 0x4, - EC_SB_FW_UPDATE_STATUS = 0x5, - EC_SB_FW_UPDATE_PROTECT = 0x6, - EC_SB_FW_UPDATE_MAX = 0x7, -}; - -#define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32 -#define SB_FW_UPDATE_CMD_STATUS_SIZE 2 -#define SB_FW_UPDATE_CMD_INFO_SIZE 8 - -struct __ec_align4 ec_sb_fw_update_header { - uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */ - uint16_t fw_id; /* firmware id */ -}; - -struct __ec_align4 ec_params_sb_fw_update { - struct ec_sb_fw_update_header hdr; - union { - /* EC_SB_FW_UPDATE_PREPARE = 0x0 */ - /* EC_SB_FW_UPDATE_INFO = 0x1 */ - /* EC_SB_FW_UPDATE_BEGIN = 0x2 */ - /* EC_SB_FW_UPDATE_END = 0x4 */ - /* EC_SB_FW_UPDATE_STATUS = 0x5 */ - /* EC_SB_FW_UPDATE_PROTECT = 0x6 */ - struct __ec_align4 { - /* no args */ - } dummy; - - /* EC_SB_FW_UPDATE_WRITE = 0x3 */ - struct __ec_align4 { - uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE]; - } write; - }; -}; - -struct __ec_align1 ec_response_sb_fw_update { - union { - /* EC_SB_FW_UPDATE_INFO = 0x1 */ - struct __ec_align1 { - uint8_t data[SB_FW_UPDATE_CMD_INFO_SIZE]; - } info; - - /* EC_SB_FW_UPDATE_STATUS = 0x5 */ - struct __ec_align1 { - uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE]; - } status; - }; -}; - /* * Entering Verified Boot Mode Command * Default mode is VBOOT_MODE_NORMAL if EC did not receive this command. * Valid Modes are: normal, developer, and recovery. + * + * EC no longer needs to know what mode vboot has entered, + * so this command is deprecated. (See chromium:1014379.) */ #define EC_CMD_ENTERING_MODE 0x00B6 -struct __ec_align4 ec_params_entering_mode { +struct ec_params_entering_mode { int vboot_mode; -}; +} __ec_align4; -#define VBOOT_MODE_NORMAL 0 +#define VBOOT_MODE_NORMAL 0 #define VBOOT_MODE_DEVELOPER 1 -#define VBOOT_MODE_RECOVERY 2 +#define VBOOT_MODE_RECOVERY 2 /*****************************************************************************/ /* @@ -3864,578 +5437,2978 @@ struct __ec_align4 ec_params_entering_mode { #define EC_CMD_I2C_PASSTHRU_PROTECT 0x00B7 enum ec_i2c_passthru_protect_subcmd { - EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0x0, - EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 0x1, + EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0, + EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 1, + EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE_TCPCS = 2, }; -struct __ec_align1 ec_params_i2c_passthru_protect { +struct ec_params_i2c_passthru_protect { uint8_t subcmd; - uint8_t port; /* I2C port number */ -}; + uint8_t port; /* I2C port number */ +} __ec_align1; -struct __ec_align1 ec_response_i2c_passthru_protect { - uint8_t status; /* Status flags (0: unlocked, 1: locked) */ -}; +struct ec_response_i2c_passthru_protect { + uint8_t status; /* Status flags (0: unlocked, 1: locked) */ +} __ec_align1; /*****************************************************************************/ -/* System commands */ - /* - * TODO(crosbug.com/p/23747): This is a confusing name, since it doesn't - * necessarily reboot the EC. Rename to "image" or something similar? + * HDMI CEC commands + * + * These commands are for sending and receiving message via HDMI CEC */ -#define EC_CMD_REBOOT_EC 0x00D2 - -/* Command */ -enum ec_reboot_cmd { - EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ - EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ - EC_REBOOT_JUMP_RW = 2, /* Jump to RW without rebooting */ - /* (command 3 was jump to RW-B) */ - EC_REBOOT_COLD = 4, /* Cold-reboot */ - EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ - EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ - EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_OFF flag */ -}; -/* Flags for ec_params_reboot_ec.reboot_flags */ -#define EC_REBOOT_FLAG_RESERVED0 (1 << 0) /* Was recovery request */ -#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN (1 << 1) /* Reboot after AP shutdown */ -#define EC_REBOOT_FLAG_SWITCH_RW_SLOT (1 << 2) /* Switch RW slot */ +#define EC_CEC_MAX_PORTS 16 -struct __ec_align1 ec_params_reboot_ec { - uint8_t cmd; /* enum ec_reboot_cmd */ - uint8_t flags; /* See EC_REBOOT_FLAG_* */ -}; +#define MAX_CEC_MSG_LEN 16 /* - * Get information on last EC panic. - * - * Returns variable-length platform-dependent panic information. See panic.h - * for details. + * Helper macros for packing/unpacking cec_events. + * bits[27:0] : bitmask of events from enum mkbp_cec_event + * bits[31:28]: port number */ -#define EC_CMD_GET_PANIC_INFO 0x00D3 +#define EC_MKBP_EVENT_CEC_PACK(events, port) \ + (((events) & GENMASK(27, 0)) | (((port) & 0xf) << 28)) +#define EC_MKBP_EVENT_CEC_GET_EVENTS(event) ((event) & GENMASK(27, 0)) +#define EC_MKBP_EVENT_CEC_GET_PORT(event) (((event) >> 28) & 0xf) -/*****************************************************************************/ -/* - * Special commands - * - * These do not follow the normal rules for commands. See each command for - * details. +/* CEC message from the AP to be written on the CEC bus */ +#define EC_CMD_CEC_WRITE_MSG 0x00B8 + +/** + * struct ec_params_cec_write - Message to write to the CEC bus + * @msg: message content to write to the CEC bus + */ +struct ec_params_cec_write { + uint8_t msg[MAX_CEC_MSG_LEN]; +} __ec_align1; + +/** + * struct ec_params_cec_write_v1 - Message to write to the CEC bus + * @port: CEC port to write the message on + * @msg_len: length of msg in bytes + * @msg: message content to write to the CEC bus */ +struct ec_params_cec_write_v1 { + uint8_t port; + uint8_t msg_len; + uint8_t msg[MAX_CEC_MSG_LEN]; +} __ec_align1; -/* - * Reboot NOW - * - * This command will work even when the EC LPC interface is busy, because the - * reboot command is processed at interrupt level. Note that when the EC - * reboots, the host will reboot too, so there is no response to this command. - * - * Use EC_CMD_REBOOT_EC to reboot the EC more politely. +/* CEC message read from a CEC bus reported back to the AP */ +#define EC_CMD_CEC_READ_MSG 0x00B9 + +/** + * struct ec_params_cec_read - Read a message from the CEC bus + * @port: CEC port to read a message on */ -#define EC_CMD_REBOOT 0x00D1 /* Think "die" */ +struct ec_params_cec_read { + uint8_t port; +} __ec_align1; -/* - * Resend last response (not supported on LPC). - * - * Returns EC_RES_UNAVAILABLE if there is no response available - for example, - * there was no previous command, or the previous command's response was too - * big to save. +/** + * struct ec_response_cec_read - Message read from the CEC bus + * @msg_len: length of msg in bytes + * @msg: message content read from the CEC bus */ -#define EC_CMD_RESEND_RESPONSE 0x00DB +struct ec_response_cec_read { + uint8_t msg_len; + uint8_t msg[MAX_CEC_MSG_LEN]; +} __ec_align1; + +/* Set various CEC parameters */ +#define EC_CMD_CEC_SET 0x00BA + +/** + * struct ec_params_cec_set - CEC parameters set + * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS + * @port: CEC port to set the parameter on + * @val: in case cmd is CEC_CMD_ENABLE, this field can be 0 to disable CEC + * or 1 to enable CEC functionality, in case cmd is + * CEC_CMD_LOGICAL_ADDRESS, this field encodes the requested logical + * address between 0 and 15 or 0xff to unregister + */ +struct ec_params_cec_set { + uint8_t cmd : 4; /* enum cec_command */ + uint8_t port : 4; + uint8_t val; +} __ec_align1; -/* - * This header byte on a command indicate version 0. Any header byte less - * than this means that we are talking to an old EC which doesn't support - * versioning. In that case, we assume version 0. - * - * Header bytes greater than this indicate a later version. For example, - * EC_CMD_VERSION0 + 1 means we are using version 1. - * - * The old EC interface must not use commands 0xdc or higher. +/* Read various CEC parameters */ +#define EC_CMD_CEC_GET 0x00BB + +/** + * struct ec_params_cec_get - CEC parameters get + * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS + * @port: CEC port to get the parameter on */ -#define EC_CMD_VERSION0 0x00DC +struct ec_params_cec_get { + uint8_t cmd : 4; /* enum cec_command */ + uint8_t port : 4; +} __ec_align1; + +/** + * struct ec_response_cec_get - CEC parameters get response + * @val: in case cmd was CEC_CMD_ENABLE, this field will 0 if CEC is + * disabled or 1 if CEC functionality is enabled, + * in case cmd was CEC_CMD_LOGICAL_ADDRESS, this will encode the + * configured logical address between 0 and 15 or 0xff if unregistered + */ +struct ec_response_cec_get { + uint8_t val; +} __ec_align1; -/*****************************************************************************/ -/* - * PD commands - * - * These commands are for PD MCU communication. - */ +/* Get the number of CEC ports */ +#define EC_CMD_CEC_PORT_COUNT 0x00C1 -/* EC to PD MCU exchange status command */ -#define EC_CMD_PD_EXCHANGE_STATUS 0x0100 -#define EC_VER_PD_EXCHANGE_STATUS 2 +/** + * struct ec_response_cec_port_count - CEC port count response + * @port_count: number of CEC ports + */ +struct ec_response_cec_port_count { + uint8_t port_count; +} __ec_align1; -enum pd_charge_state { - PD_CHARGE_NO_CHANGE = 0, /* Don't change charge state */ - PD_CHARGE_NONE, /* No charging allowed */ - PD_CHARGE_5V, /* 5V charging only */ - PD_CHARGE_MAX /* Charge at max voltage */ +/* CEC parameters command */ +enum cec_command { + /* CEC reading, writing and events enable */ + CEC_CMD_ENABLE, + /* CEC logical address */ + CEC_CMD_LOGICAL_ADDRESS, }; -/* Status of EC being sent to PD */ -#define EC_STATUS_HIBERNATING (1 << 0) - -struct __ec_align1 ec_params_pd_status { - uint8_t status; /* EC status */ - int8_t batt_soc; /* battery state of charge */ - uint8_t charge_state; /* charging state (from enum pd_charge_state) */ +/* Events from CEC to AP */ +enum mkbp_cec_event { + /* Outgoing message was acknowledged by a follower */ + EC_MKBP_CEC_SEND_OK = BIT(0), + /* Outgoing message was not acknowledged */ + EC_MKBP_CEC_SEND_FAILED = BIT(1), + /* Incoming message can be read out by AP */ + EC_MKBP_CEC_HAVE_DATA = BIT(2), }; -/* Status of PD being sent back to EC */ -#define PD_STATUS_HOST_EVENT (1 << 0) /* Forward host event to AP */ -#define PD_STATUS_IN_RW (1 << 1) /* Running RW image */ -#define PD_STATUS_JUMPED_TO_IMAGE (1 << 2) /* Current image was jumped to */ -#define PD_STATUS_TCPC_ALERT_0 (1 << 3) /* Alert active in port 0 TCPC */ -#define PD_STATUS_TCPC_ALERT_1 (1 << 4) /* Alert active in port 1 TCPC */ -#define PD_STATUS_TCPC_ALERT_2 (1 << 5) /* Alert active in port 2 TCPC */ -#define PD_STATUS_TCPC_ALERT_3 (1 << 6) /* Alert active in port 3 TCPC */ -#define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \ - PD_STATUS_TCPC_ALERT_1 | \ - PD_STATUS_HOST_EVENT) -struct __ec_align_size1 ec_response_pd_status { - uint32_t curr_lim_ma; /* input current limit */ - uint16_t status; /* PD MCU status */ - int8_t active_charge_port; /* active charging port */ -}; +/*****************************************************************************/ -/* AP to PD MCU host event status command, cleared on read */ -#define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 +/* Commands for audio codec. */ +#define EC_CMD_EC_CODEC 0x00BC -/* PD MCU host event status bits */ -#define PD_EVENT_UPDATE_DEVICE (1 << 0) -#define PD_EVENT_POWER_CHANGE (1 << 1) -#define PD_EVENT_IDENTITY_RECEIVED (1 << 2) -#define PD_EVENT_DATA_SWAP (1 << 3) -struct __ec_align4 ec_response_host_event_status { - uint32_t status; /* PD MCU host event status */ +enum ec_codec_subcmd { + EC_CODEC_GET_CAPABILITIES = 0x0, + EC_CODEC_GET_SHM_ADDR = 0x1, + EC_CODEC_SET_SHM_ADDR = 0x2, + EC_CODEC_SUBCMD_COUNT, }; -/* Set USB type-C port role and muxes */ -#define EC_CMD_USB_PD_CONTROL 0x0101 - -enum usb_pd_control_role { - USB_PD_CTRL_ROLE_NO_CHANGE = 0, - USB_PD_CTRL_ROLE_TOGGLE_ON = 1, /* == AUTO */ - USB_PD_CTRL_ROLE_TOGGLE_OFF = 2, - USB_PD_CTRL_ROLE_FORCE_SINK = 3, - USB_PD_CTRL_ROLE_FORCE_SOURCE = 4, - USB_PD_CTRL_ROLE_COUNT +enum ec_codec_cap { + EC_CODEC_CAP_WOV_AUDIO_SHM = 0, + EC_CODEC_CAP_WOV_LANG_SHM = 1, + EC_CODEC_CAP_LAST = 32, }; -enum usb_pd_control_mux { - USB_PD_CTRL_MUX_NO_CHANGE = 0, - USB_PD_CTRL_MUX_NONE = 1, - USB_PD_CTRL_MUX_USB = 2, - USB_PD_CTRL_MUX_DP = 3, - USB_PD_CTRL_MUX_DOCK = 4, - USB_PD_CTRL_MUX_AUTO = 5, - USB_PD_CTRL_MUX_COUNT +enum ec_codec_shm_id { + EC_CODEC_SHM_ID_WOV_AUDIO = 0x0, + EC_CODEC_SHM_ID_WOV_LANG = 0x1, + EC_CODEC_SHM_ID_LAST, }; -enum usb_pd_control_swap { - USB_PD_CTRL_SWAP_NONE = 0, - USB_PD_CTRL_SWAP_DATA = 1, - USB_PD_CTRL_SWAP_POWER = 2, - USB_PD_CTRL_SWAP_VCONN = 3, - USB_PD_CTRL_SWAP_COUNT +enum ec_codec_shm_type { + EC_CODEC_SHM_TYPE_EC_RAM = 0x0, + EC_CODEC_SHM_TYPE_SYSTEM_RAM = 0x1, }; -struct __ec_align1 ec_params_usb_pd_control { - uint8_t port; - uint8_t role; - uint8_t mux; - uint8_t swap; +struct __ec_align1 ec_param_ec_codec_get_shm_addr { + uint8_t shm_id; + uint8_t reserved[3]; }; -#define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */ -#define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */ -#define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */ +struct __ec_align4 ec_param_ec_codec_set_shm_addr { + uint64_t phys_addr; + uint32_t len; + uint8_t shm_id; + uint8_t reserved[3]; +}; -#define PD_CTRL_RESP_ROLE_POWER (1 << 0) /* 0=SNK/1=SRC */ -#define PD_CTRL_RESP_ROLE_DATA (1 << 1) /* 0=UFP/1=DFP */ -#define PD_CTRL_RESP_ROLE_VCONN (1 << 2) /* Vconn status */ -#define PD_CTRL_RESP_ROLE_DR_POWER (1 << 3) /* Partner is dualrole power */ -#define PD_CTRL_RESP_ROLE_DR_DATA (1 << 4) /* Partner is dualrole data */ -#define PD_CTRL_RESP_ROLE_USB_COMM (1 << 5) /* Partner USB comm capable */ -#define PD_CTRL_RESP_ROLE_EXT_POWERED (1 << 6) /* Partner externally powerd */ +struct __ec_align4 ec_param_ec_codec { + uint8_t cmd; /* enum ec_codec_subcmd */ + uint8_t reserved[3]; -struct __ec_align1 ec_response_usb_pd_control { - uint8_t enabled; - uint8_t role; - uint8_t polarity; - uint8_t state; + union { + struct ec_param_ec_codec_get_shm_addr get_shm_addr_param; + struct ec_param_ec_codec_set_shm_addr set_shm_addr_param; + }; }; -struct __ec_align1 ec_response_usb_pd_control_v1 { - uint8_t enabled; - uint8_t role; - uint8_t polarity; - char state[32]; +struct __ec_align4 ec_response_ec_codec_get_capabilities { + uint32_t capabilities; }; -#define EC_CMD_USB_PD_PORTS 0x0102 - -/* Maximum number of PD ports on a device, num_ports will be <= this */ -#define EC_USB_PD_MAX_PORTS 8 - -struct __ec_align1 ec_response_usb_pd_ports { - uint8_t num_ports; +struct __ec_align4 ec_response_ec_codec_get_shm_addr { + uint64_t phys_addr; + uint32_t len; + uint8_t type; + uint8_t reserved[3]; }; -#define EC_CMD_USB_PD_POWER_INFO 0x0103 +/*****************************************************************************/ -#define PD_POWER_CHARGING_PORT 0xff -struct __ec_align1 ec_params_usb_pd_power_info { - uint8_t port; -}; +/* Commands for DMIC on audio codec. */ +#define EC_CMD_EC_CODEC_DMIC 0x00BD -enum usb_chg_type { - USB_CHG_TYPE_NONE, - USB_CHG_TYPE_PD, - USB_CHG_TYPE_C, - USB_CHG_TYPE_PROPRIETARY, - USB_CHG_TYPE_BC12_DCP, - USB_CHG_TYPE_BC12_CDP, - USB_CHG_TYPE_BC12_SDP, - USB_CHG_TYPE_OTHER, - USB_CHG_TYPE_VBUS, - USB_CHG_TYPE_UNKNOWN, +enum ec_codec_dmic_subcmd { + EC_CODEC_DMIC_GET_MAX_GAIN = 0x0, + EC_CODEC_DMIC_SET_GAIN_IDX = 0x1, + EC_CODEC_DMIC_GET_GAIN_IDX = 0x2, + EC_CODEC_DMIC_SUBCMD_COUNT, }; -enum usb_power_roles { - USB_PD_PORT_POWER_DISCONNECTED, - USB_PD_PORT_POWER_SOURCE, - USB_PD_PORT_POWER_SINK, - USB_PD_PORT_POWER_SINK_NOT_CHARGING, + +enum ec_codec_dmic_channel { + EC_CODEC_DMIC_CHANNEL_0 = 0x0, + EC_CODEC_DMIC_CHANNEL_1 = 0x1, + EC_CODEC_DMIC_CHANNEL_2 = 0x2, + EC_CODEC_DMIC_CHANNEL_3 = 0x3, + EC_CODEC_DMIC_CHANNEL_4 = 0x4, + EC_CODEC_DMIC_CHANNEL_5 = 0x5, + EC_CODEC_DMIC_CHANNEL_6 = 0x6, + EC_CODEC_DMIC_CHANNEL_7 = 0x7, + EC_CODEC_DMIC_CHANNEL_COUNT, }; -struct __ec_align2 usb_chg_measures { - uint16_t voltage_max; - uint16_t voltage_now; - uint16_t current_max; - uint16_t current_lim; +struct __ec_align1 ec_param_ec_codec_dmic_set_gain_idx { + uint8_t channel; /* enum ec_codec_dmic_channel */ + uint8_t gain; + uint8_t reserved[2]; }; -struct __ec_align4 ec_response_usb_pd_power_info { - uint8_t role; - uint8_t type; - uint8_t dualrole; - uint8_t reserved1; - struct usb_chg_measures meas; - uint32_t max_power; +struct __ec_align1 ec_param_ec_codec_dmic_get_gain_idx { + uint8_t channel; /* enum ec_codec_dmic_channel */ + uint8_t reserved[3]; }; -/* Write USB-PD device FW */ -#define EC_CMD_USB_PD_FW_UPDATE 0x0110 +struct __ec_align4 ec_param_ec_codec_dmic { + uint8_t cmd; /* enum ec_codec_dmic_subcmd */ + uint8_t reserved[3]; -enum usb_pd_fw_update_cmds { - USB_PD_FW_REBOOT, - USB_PD_FW_FLASH_ERASE, - USB_PD_FW_FLASH_WRITE, - USB_PD_FW_ERASE_SIG, + union { + struct ec_param_ec_codec_dmic_set_gain_idx set_gain_idx_param; + struct ec_param_ec_codec_dmic_get_gain_idx get_gain_idx_param; + }; }; -struct __ec_align4 ec_params_usb_pd_fw_update { - uint16_t dev_id; - uint8_t cmd; - uint8_t port; - uint32_t size; /* Size to write in bytes */ - /* Followed by data to write */ +struct __ec_align1 ec_response_ec_codec_dmic_get_max_gain { + uint8_t max_gain; }; -/* Write USB-PD Accessory RW_HASH table entry */ -#define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111 -/* RW hash is first 20 bytes of SHA-256 of RW section */ -#define PD_RW_HASH_SIZE 20 -struct __ec_align1 ec_params_usb_pd_rw_hash_entry { - uint16_t dev_id; - uint8_t dev_rw_hash[PD_RW_HASH_SIZE]; - uint8_t reserved; /* For alignment of current_image - * TODO(rspangler) but it's not aligned! - * Should have been reserved[2]. */ - uint32_t current_image; /* One of ec_current_image */ +struct __ec_align1 ec_response_ec_codec_dmic_get_gain_idx { + uint8_t gain; }; -/* Read USB-PD Accessory info */ -#define EC_CMD_USB_PD_DEV_INFO 0x0112 +/*****************************************************************************/ -struct __ec_align1 ec_params_usb_pd_info_request { - uint8_t port; +/* Commands for I2S RX on audio codec. */ + +#define EC_CMD_EC_CODEC_I2S_RX 0x00BE + +enum ec_codec_i2s_rx_subcmd { + EC_CODEC_I2S_RX_ENABLE = 0x0, + EC_CODEC_I2S_RX_DISABLE = 0x1, + EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH = 0x2, + EC_CODEC_I2S_RX_SET_DAIFMT = 0x3, + EC_CODEC_I2S_RX_SET_BCLK = 0x4, + EC_CODEC_I2S_RX_RESET = 0x5, + EC_CODEC_I2S_RX_SUBCMD_COUNT, }; -/* Read USB-PD Device discovery info */ -#define EC_CMD_USB_PD_DISCOVERY 0x0113 -struct __ec_align_size1 ec_params_usb_pd_discovery_entry { - uint16_t vid; /* USB-IF VID */ - uint16_t pid; /* USB-IF PID */ - uint8_t ptype; /* product type (hub,periph,cable,ama) */ +enum ec_codec_i2s_rx_sample_depth { + EC_CODEC_I2S_RX_SAMPLE_DEPTH_16 = 0x0, + EC_CODEC_I2S_RX_SAMPLE_DEPTH_24 = 0x1, + EC_CODEC_I2S_RX_SAMPLE_DEPTH_COUNT, }; -/* Override default charge behavior */ -#define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114 +enum ec_codec_i2s_rx_daifmt { + EC_CODEC_I2S_RX_DAIFMT_I2S = 0x0, + EC_CODEC_I2S_RX_DAIFMT_RIGHT_J = 0x1, + EC_CODEC_I2S_RX_DAIFMT_LEFT_J = 0x2, + EC_CODEC_I2S_RX_DAIFMT_COUNT, +}; -/* Negative port parameters have special meaning */ -enum usb_pd_override_ports { - OVERRIDE_DONT_CHARGE = -2, - OVERRIDE_OFF = -1, - /* [0, CONFIG_USB_PD_PORT_COUNT): Port# */ +struct __ec_align1 ec_param_ec_codec_i2s_rx_set_sample_depth { + uint8_t depth; + uint8_t reserved[3]; }; -struct __ec_align2 ec_params_charge_port_override { - int16_t override_port; /* Override port# */ +struct __ec_align1 ec_param_ec_codec_i2s_rx_set_gain { + uint8_t left; + uint8_t right; + uint8_t reserved[2]; }; -/* Read (and delete) one entry of PD event log */ -#define EC_CMD_PD_GET_LOG_ENTRY 0x0115 +struct __ec_align1 ec_param_ec_codec_i2s_rx_set_daifmt { + uint8_t daifmt; + uint8_t reserved[3]; +}; -struct __ec_align4 ec_response_pd_log { - uint32_t timestamp; /* relative timestamp in milliseconds */ - uint8_t type; /* event type : see PD_EVENT_xx below */ - uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ - uint16_t data; /* type-defined data payload */ - uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */ +struct __ec_align4 ec_param_ec_codec_i2s_rx_set_bclk { + uint32_t bclk; }; -/* The timestamp is the microsecond counter shifted to get about a ms. */ -#define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ +struct __ec_align4 ec_param_ec_codec_i2s_rx { + uint8_t cmd; /* enum ec_codec_i2s_rx_subcmd */ + uint8_t reserved[3]; -#define PD_LOG_SIZE_MASK 0x1f -#define PD_LOG_PORT_MASK 0xe0 -#define PD_LOG_PORT_SHIFT 5 -#define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \ - ((size) & PD_LOG_SIZE_MASK)) -#define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT) -#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK) + union { + struct ec_param_ec_codec_i2s_rx_set_sample_depth + set_sample_depth_param; + struct ec_param_ec_codec_i2s_rx_set_daifmt set_daifmt_param; + struct ec_param_ec_codec_i2s_rx_set_bclk set_bclk_param; + }; +}; -/* PD event log : entry types */ -/* PD MCU events */ -#define PD_EVENT_MCU_BASE 0x00 -#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE+0) -#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE+1) -/* Reserved for custom board event */ -#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE+2) -/* PD generic accessory events */ -#define PD_EVENT_ACC_BASE 0x20 -#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE+0) -#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE+1) -/* PD power supply events */ -#define PD_EVENT_PS_BASE 0x40 -#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE+0) -/* PD video dongles events */ -#define PD_EVENT_VIDEO_BASE 0x60 -#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0) -#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE+1) -/* Returned in the "type" field, when there is no entry available */ -#define PD_EVENT_NO_ENTRY 0xff +/*****************************************************************************/ +/* Commands for WoV on audio codec. */ -/* - * PD_EVENT_MCU_CHARGE event definition : - * the payload is "struct usb_chg_measures" - * the data field contains the port state flags as defined below : - */ -/* Port partner is a dual role device */ -#define CHARGE_FLAGS_DUAL_ROLE (1 << 15) -/* Port is the pending override port */ -#define CHARGE_FLAGS_DELAYED_OVERRIDE (1 << 14) -/* Port is the override port */ -#define CHARGE_FLAGS_OVERRIDE (1 << 13) -/* Charger type */ -#define CHARGE_FLAGS_TYPE_SHIFT 3 -#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) -/* Power delivery role */ -#define CHARGE_FLAGS_ROLE_MASK (7 << 0) +#define EC_CMD_EC_CODEC_WOV 0x00BF -/* - * PD_EVENT_PS_FAULT data field flags definition : - */ -#define PS_FAULT_OCP 1 -#define PS_FAULT_FAST_OCP 2 -#define PS_FAULT_OVP 3 -#define PS_FAULT_DISCH 4 +enum ec_codec_wov_subcmd { + EC_CODEC_WOV_SET_LANG = 0x0, + EC_CODEC_WOV_SET_LANG_SHM = 0x1, + EC_CODEC_WOV_GET_LANG = 0x2, + EC_CODEC_WOV_ENABLE = 0x3, + EC_CODEC_WOV_DISABLE = 0x4, + EC_CODEC_WOV_READ_AUDIO = 0x5, + EC_CODEC_WOV_READ_AUDIO_SHM = 0x6, + EC_CODEC_WOV_SUBCMD_COUNT, +}; /* - * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info". + * @hash is SHA256 of the whole language model. + * @total_len indicates the length of whole language model. + * @offset is the cursor from the beginning of the model. + * @buf is the packet buffer. + * @len denotes how many bytes in the buf. */ -struct __ec_align4 mcdp_version { - uint8_t major; - uint8_t minor; - uint16_t build; +struct __ec_align4 ec_param_ec_codec_wov_set_lang { + uint8_t hash[32]; + uint32_t total_len; + uint32_t offset; + uint8_t buf[128]; + uint32_t len; }; -struct __ec_align4 mcdp_info { - uint8_t family[2]; - uint8_t chipid[2]; - struct mcdp_version irom; - struct mcdp_version fw; +struct __ec_align4 ec_param_ec_codec_wov_set_lang_shm { + uint8_t hash[32]; + uint32_t total_len; }; -/* struct mcdp_info field decoding */ -#define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1]) -#define MCDP_FAMILY(family) ((family[0] << 8) | family[1]) +struct __ec_align4 ec_param_ec_codec_wov { + uint8_t cmd; /* enum ec_codec_wov_subcmd */ + uint8_t reserved[3]; -/* Get/Set USB-PD Alternate mode info */ -#define EC_CMD_USB_PD_GET_AMODE 0x0116 -struct __ec_align_size1 ec_params_usb_pd_get_mode_request { - uint16_t svid_idx; /* SVID index to get */ - uint8_t port; /* port */ + union { + struct ec_param_ec_codec_wov_set_lang set_lang_param; + struct ec_param_ec_codec_wov_set_lang_shm set_lang_shm_param; + }; }; -struct __ec_align4 ec_params_usb_pd_get_mode_response { - uint16_t svid; /* SVID */ - uint16_t opos; /* Object Position */ - uint32_t vdo[6]; /* Mode VDOs */ +struct __ec_align4 ec_response_ec_codec_wov_get_lang { + uint8_t hash[32]; }; -#define EC_CMD_USB_PD_SET_AMODE 0x0117 - -enum pd_mode_cmd { - PD_EXIT_MODE = 0, - PD_ENTER_MODE = 1, - /* Not a command. Do NOT remove. */ - PD_MODE_CMD_COUNT, +struct __ec_align4 ec_response_ec_codec_wov_read_audio { + uint8_t buf[128]; + uint32_t len; }; -struct __ec_align4 ec_params_usb_pd_set_mode_request { - uint32_t cmd; /* enum pd_mode_cmd */ - uint16_t svid; /* SVID to set */ - uint8_t opos; /* Object Position */ - uint8_t port; /* port */ +struct __ec_align4 ec_response_ec_codec_wov_read_audio_shm { + uint32_t offset; + uint32_t len; }; -/* Ask the PD MCU to record a log of a requested type */ -#define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118 - -struct __ec_align1 ec_params_pd_write_log_entry { - uint8_t type; /* event type : see PD_EVENT_xx above */ - uint8_t port; /* port#, or 0 for events unrelated to a given port */ -}; +/*****************************************************************************/ +/* Commands for PoE PSE controller */ -/* Control USB-PD chip */ -#define EC_CMD_PD_CONTROL 0x0119 +#define EC_CMD_PSE 0x00C0 -enum ec_pd_control_cmd { - PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */ - PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */ - PD_RESET, /* Force reset the PD chip */ - PD_CONTROL_DISABLE /* Disable further calls to this command */ +enum ec_pse_subcmd { + EC_PSE_STATUS = 0x0, + EC_PSE_ENABLE = 0x1, + EC_PSE_DISABLE = 0x2, + EC_PSE_SUBCMD_COUNT, }; -struct __ec_align1 ec_params_pd_control { - uint8_t chip; /* chip id (should be 0) */ - uint8_t subcmd; +struct __ec_align1 ec_params_pse { + uint8_t cmd; /* enum ec_pse_subcmd */ + uint8_t port; /* PSE port */ }; -/* Get info about USB-C SS muxes */ -#define EC_CMD_USB_PD_MUX_INFO 0x011A - -struct __ec_align1 ec_params_usb_pd_mux_info { - uint8_t port; /* USB-C port number */ +enum ec_pse_status { + EC_PSE_STATUS_DISABLED = 0x0, + EC_PSE_STATUS_ENABLED = 0x1, + EC_PSE_STATUS_POWERED = 0x2, }; -/* Flags representing mux state */ -#define USB_PD_MUX_USB_ENABLED (1 << 0) -#define USB_PD_MUX_DP_ENABLED (1 << 1) -#define USB_PD_MUX_POLARITY_INVERTED (1 << 2) -#define USB_PD_MUX_HPD_IRQ (1 << 3) - -struct __ec_align1 ec_response_usb_pd_mux_info { - uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ +struct __ec_align1 ec_response_pse_status { + uint8_t status; /* enum ec_pse_status */ }; -#define EC_CMD_PD_CHIP_INFO 0x011B +/*****************************************************************************/ +/* System commands */ -struct __ec_align1 ec_params_pd_chip_info { - uint8_t port; /* USB-C port number */ - uint8_t renew; /* Force renewal */ -}; +/* + * TODO(crosbug.com/p/23747): This is a confusing name, since it doesn't + * necessarily reboot the EC. Rename to "image" or something similar? + */ +#define EC_CMD_REBOOT_EC 0x00D2 -struct __ec_align2 ec_response_pd_chip_info { - uint16_t vendor_id; - uint16_t product_id; - uint16_t device_id; - union { - uint8_t fw_version_string[8]; - uint64_t fw_version_number; - }; +/* Command */ +enum ec_reboot_cmd { + EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ + EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ + EC_REBOOT_JUMP_RW = 2, /* Jump to active RW without rebooting */ + /* (command 3 was jump to RW-B) */ + EC_REBOOT_COLD = 4, /* Cold-reboot */ + EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ + EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ + /* + * DEPRECATED: Hibernate EC and clears AP_IDLE flag. + * Use EC_REBOOT_HIBERNATE and EC_REBOOT_FLAG_CLEAR_AP_IDLE, instead. + */ + EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, + EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */ + EC_REBOOT_NO_OP = 9, /* Do nothing but apply the flags. */ }; -/* Run RW signature verification and get status */ -#define EC_CMD_RWSIG_CHECK_STATUS 0x011C - -struct __ec_align4 ec_response_rwsig_check_status { - uint32_t status; -}; +/* Flags for ec_params_reboot_ec.reboot_flags */ +#define EC_REBOOT_FLAG_IMMEDIATE 0 /* Trigger Cold Reset */ +#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */ +#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */ +#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */ +#define EC_REBOOT_FLAG_CLEAR_AP_IDLE BIT(3) /* Clear AP_IDLE flag */ -/* For controlling RWSIG task */ -#define EC_CMD_RWSIG_ACTION 0x011D +struct ec_params_reboot_ec { + uint8_t cmd; /* enum ec_reboot_cmd */ + uint8_t flags; /* See EC_REBOOT_FLAG_* */ +} __ec_align1; -enum rwsig_action { - RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */ - RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ -}; +/* + * Get information on last EC panic. + * + * Returns variable-length platform-dependent panic information. See panic.h + * for details. + */ +#define EC_CMD_GET_PANIC_INFO 0x00D3 -struct __ec_align4 ec_params_rwsig_action { - uint32_t action; -}; +struct ec_params_get_panic_info_v1 { + /* Do not modify PANIC_DATA_FLAG_OLD_HOSTCMD when reading panic info */ + uint8_t preserve_old_hostcmd_flag; +} __ec_align1; -/* Run verification on a slot */ -#define EC_CMD_EFS_VERIFY 0x011E +struct ec_params_get_panic_info_v2 { + /* Do not modify PANIC_DATA_FLAG_OLD_HOSTCMD when reading panic info */ + uint8_t preserve_old_hostcmd_flag; -struct __ec_align1 ec_params_efs_verify { - uint8_t region; /* enum ec_flash_region */ -}; + /* Read panic_data struct from this offset. + * Signal end of data with empty success. + */ + uint16_t read_offset; +} __ec_align1; + +/*****************************************************************************/ +/* + * Special commands + * + * These do not follow the normal rules for commands. See each command for + * details. + */ + +/* + * Reboot NOW + * + * This command will work even when the EC LPC interface is busy, because the + * reboot command is processed at interrupt level. Note that when the EC + * reboots, the host will reboot too, so there is no response to this command. + * + * Use EC_CMD_REBOOT_EC to reboot the EC more politely. + */ +#define EC_CMD_REBOOT 0x00D1 /* Think "die" */ + +/* + * Resend last response (not supported on LPC). + * + * Returns EC_RES_UNAVAILABLE if there is no response available - for example, + * there was no previous command, or the previous command's response was too + * big to save. + */ +#define EC_CMD_RESEND_RESPONSE 0x00DB + +/* + * This header byte on a command indicate version 0. Any header byte less + * than this means that we are talking to an old EC which doesn't support + * versioning. In that case, we assume version 0. + * + * Header bytes greater than this indicate a later version. For example, + * EC_CMD_VERSION0 + 1 means we are using version 1. + * + * The old EC interface must not use commands 0xdc or higher. + */ +#define EC_CMD_VERSION0 0x00DC + +/* + * Memory Dump Commands + * + * Since the HOSTCMD response size is limited, depending on the + * protocol, retrieving a memory dump is split into 3 commands. + * + * 1. EC_CMD_MEMORY_DUMP_GET_METADATA returns the number of memory dump entries, + * and the total dump size. + * 2. EC_CMD_MEMORY_DUMP_GET_ENTRY_INFO returns the address and size for a given + * memory dump entry index. + * 3. EC_CMD_MEMORY_DUMP_READ_MEMORY returns the actual memory at a given + * address. The address and size must be within the bounds of the given + * memory dump entry index. Each response is limited to the max response size + * of the host protocol, so this may need to be called repeatedly to retrieve + * the entire memory dump entry. + * + * Memory entries may overlap and may be out of order. + * The host should check for overlaps to optimize transfer rate. + */ +#define EC_CMD_MEMORY_DUMP_GET_METADATA 0x00DD +struct ec_response_memory_dump_get_metadata { + uint16_t memory_dump_entry_count; + uint32_t memory_dump_total_size; +} __ec_align4; + +#define EC_CMD_MEMORY_DUMP_GET_ENTRY_INFO 0x00DE +struct ec_params_memory_dump_get_entry_info { + uint16_t memory_dump_entry_index; +} __ec_align4; + +struct ec_response_memory_dump_get_entry_info { + uint32_t address; + uint32_t size; +} __ec_align4; + +#define EC_CMD_MEMORY_DUMP_READ_MEMORY 0x00DF + +struct ec_params_memory_dump_read_memory { + uint16_t memory_dump_entry_index; + uint32_t address; + uint32_t size; +} __ec_align4; + +#define EC_CMD_PANIC_LOG_INFO 0x00E0 + +/* + * Parameters for configuring the panic log. + * Freeze and unfreeze are mutually exclusive. + */ +struct ec_params_panic_log_info { + /* Reset panic log */ + uint8_t reset; + /* Freeze panic log */ + uint8_t freeze; + /* Unfreeze panic log */ + uint8_t unfreeze; +} __ec_align1; + +/* + * Returns the panic log info before applying the configuration + * in ec_params_panic_log_info. + */ +struct ec_response_panic_log_info { + uint32_t version; + uint32_t capacity; + uint32_t length; + uint8_t valid; + uint8_t frozen; +} __ec_align4; + +#define EC_CMD_PANIC_LOG_READ 0x00E1 + +/* + * Read from panic log at given byte offset. Will read up to the end of the + * panic log or response max. Use EC_CMD_PANIC_LOG_INFO command to freeze + * the log and get the length before reading. + */ +struct ec_params_panic_log_read { + uint32_t offset; +} __ec_align4; + +/* + * EC_CMD_MEMORY_DUMP_READ_MEMORY response buffer is written directly into + * host_cmd_handler_args.response and host_cmd_handler_args.response_size. + */ + +/* + * Enter bootloader mode + * + * This command requests EC to enter bootloader mode. + */ +#define EC_CMD_ENTER_BOOTLOADER 0x00E2 + +struct ec_params_enter_bootloader { + /* Mode to enter bootloader. Chip specific value. Can be unused. */ + uint8_t mode; +} __ec_align1; + +#define EC_CMD_HOSTCMD_WATCHDOG_INFO 0x00E3 + +struct ec_params_hostcmd_watchdog_info { + uint8_t reset_stats; +} __ec_align1; + +struct ec_response_hostcmd_watchdog_info { + /* Static watchdog info */ + int32_t watchdog_period_ms; + int32_t watchdog_warning_period_ms; + int32_t watchdog_reload_period_nominal_ms; + /* Dynamic watchdog stats */ + int32_t watchdog_reload_period_max_ms; + int64_t watchdog_reload_period_max_ts_ms; + uint32_t watchdog_reload_count; + int64_t watchdog_stats_elapsed_ms; +} __ec_align4; + +/*****************************************************************************/ +/* + * PD commands + * + * These commands are for PD MCU communication. + */ + +/* EC to PD MCU exchange status command */ +#define EC_CMD_PD_EXCHANGE_STATUS 0x0100 +#define EC_VER_PD_EXCHANGE_STATUS 2 + +enum pd_charge_state { + /* Don't change charge state */ + PD_CHARGE_NO_CHANGE = 0, + + /* No charging allowed */ + PD_CHARGE_NONE, + + /* 5V charging only */ + PD_CHARGE_5V, + + /* Charge at max voltage */ + PD_CHARGE_MAX, +}; + +/* Status of EC being sent to PD */ +#define EC_STATUS_HIBERNATING BIT(0) + +struct ec_params_pd_status { + /* EC status */ + uint8_t status; + + /* battery state of charge */ + int8_t batt_soc; + + /* charging state (from enum pd_charge_state) */ + uint8_t charge_state; +} __ec_align1; + +/* Status of PD being sent back to EC */ +#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */ +#define PD_STATUS_IN_RW BIT(1) /* Running RW image */ +#define PD_STATUS_JUMPED_TO_IMAGE BIT(2) /* Current image was jumped to */ +#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */ +#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */ +#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */ +#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */ +#define PD_STATUS_EC_INT_ACTIVE \ + (PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1 | PD_STATUS_HOST_EVENT) +struct ec_response_pd_status { + /* input current limit */ + uint32_t curr_lim_ma; + + /* PD MCU status */ + uint16_t status; + + /* active charging port */ + int8_t active_charge_port; +} __ec_align_size1; + +/* AP to PD MCU host event status command, cleared on read */ +#define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 + +/* PD MCU host event status bits */ +#define PD_EVENT_UPDATE_DEVICE BIT(0) +#define PD_EVENT_POWER_CHANGE BIT(1) +#define PD_EVENT_IDENTITY_RECEIVED BIT(2) +#define PD_EVENT_DATA_SWAP BIT(3) +#define PD_EVENT_TYPEC BIT(4) +#define PD_EVENT_PPM BIT(5) +#define PD_EVENT_INIT BIT(6) + +struct ec_response_host_event_status { + uint32_t status; /* PD MCU host event status */ +} __ec_align4; + +/* + * Set USB type-C port role and muxes + * + * Deprecated in favor of TYPEC_STATUS and TYPEC_CONTROL commands. + * + * TODO(b/169771803): TCPMv2: Remove EC_CMD_USB_PD_CONTROL + */ +#define EC_CMD_USB_PD_CONTROL 0x0101 + +enum usb_pd_control_role { + USB_PD_CTRL_ROLE_NO_CHANGE = 0, + USB_PD_CTRL_ROLE_TOGGLE_ON = 1, /* == AUTO */ + USB_PD_CTRL_ROLE_TOGGLE_OFF = 2, + USB_PD_CTRL_ROLE_FORCE_SINK = 3, + USB_PD_CTRL_ROLE_FORCE_SOURCE = 4, + USB_PD_CTRL_ROLE_FREEZE = 5, + USB_PD_CTRL_ROLE_COUNT, +}; + +enum usb_pd_control_mux { + USB_PD_CTRL_MUX_NO_CHANGE = 0, + USB_PD_CTRL_MUX_NONE = 1, + USB_PD_CTRL_MUX_USB = 2, + USB_PD_CTRL_MUX_DP = 3, + USB_PD_CTRL_MUX_DOCK = 4, + USB_PD_CTRL_MUX_AUTO = 5, + USB_PD_CTRL_MUX_COUNT, +}; + +enum usb_pd_control_swap { + USB_PD_CTRL_SWAP_NONE = 0, + USB_PD_CTRL_SWAP_DATA = 1, + USB_PD_CTRL_SWAP_POWER = 2, + USB_PD_CTRL_SWAP_VCONN = 3, + USB_PD_CTRL_SWAP_COUNT, +}; + +struct ec_params_usb_pd_control { + uint8_t port; + uint8_t role; + uint8_t mux; + uint8_t swap; +} __ec_align1; + +#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */ +#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */ +#define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2) /* Partner is PD capable */ + +#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */ +#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */ +#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */ +#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */ +#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */ +#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */ +/* Partner unconstrained power */ +#define PD_CTRL_RESP_ROLE_UNCONSTRAINED BIT(6) + +struct ec_response_usb_pd_control { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + uint8_t state; +} __ec_align1; + +struct ec_response_usb_pd_control_v1 { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + char state[32]; +} __ec_align1; + +/* Possible port partner connections based on CC line states */ +enum pd_cc_states { + PD_CC_NONE = 0, /* No port partner attached */ + + /* From DFP perspective */ + PD_CC_UFP_NONE = 1, /* No UFP accessory connected */ + PD_CC_UFP_AUDIO_ACC = 2, /* UFP Audio accessory connected */ + PD_CC_UFP_DEBUG_ACC = 3, /* UFP Debug accessory connected */ + PD_CC_UFP_ATTACHED = 4, /* Plain UFP attached */ + + /* From UFP perspective */ + PD_CC_DFP_ATTACHED = 5, /* Plain DFP attached */ + PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */ +}; + +/* Active/Passive Cable */ +#define USB_PD_CTRL_ACTIVE_CABLE BIT(0) +/* Optical/Non-optical cable */ +#define USB_PD_CTRL_OPTICAL_CABLE BIT(1) +/* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */ +#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2) +/* Active Link Uni-Direction */ +#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) +/* Retimer/Redriver cable */ +#define USB_PD_CTRL_RETIMER_CABLE BIT(4) + +struct ec_response_usb_pd_control_v2 { + uint8_t enabled; + uint8_t role; + uint8_t polarity; + char state[32]; + uint8_t cc_state; /* enum pd_cc_states representing cc state */ + uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ + uint8_t reserved; /* Reserved for future use */ + uint8_t control_flags; /* USB_PD_CTRL_*flags */ + uint8_t cable_speed; /* TBT_SS_* cable speed */ + uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ +} __ec_align1; + +#define EC_CMD_USB_PD_PORTS 0x0102 + +/* Maximum number of PD ports on a device, num_ports will be <= this */ +#define EC_USB_PD_MAX_PORTS 8 + +struct ec_response_usb_pd_ports { + uint8_t num_ports; +} __ec_align1; + +#define EC_CMD_USB_PD_POWER_INFO 0x0103 + +#define PD_POWER_CHARGING_PORT 0xff +struct ec_params_usb_pd_power_info { + uint8_t port; +} __ec_align1; + +enum usb_chg_type { + USB_CHG_TYPE_NONE, + USB_CHG_TYPE_PD, + USB_CHG_TYPE_C, + USB_CHG_TYPE_PROPRIETARY, + USB_CHG_TYPE_BC12_DCP, + USB_CHG_TYPE_BC12_CDP, + USB_CHG_TYPE_BC12_SDP, + USB_CHG_TYPE_OTHER, + USB_CHG_TYPE_VBUS, + USB_CHG_TYPE_UNKNOWN, + USB_CHG_TYPE_DEDICATED, +}; +enum usb_power_roles { + USB_PD_PORT_POWER_DISCONNECTED, + USB_PD_PORT_POWER_SOURCE, + USB_PD_PORT_POWER_SINK, + USB_PD_PORT_POWER_SINK_NOT_CHARGING, +}; + +struct usb_chg_measures { + uint16_t voltage_max; + uint16_t voltage_now; + uint16_t current_max; + uint16_t current_lim; +} __ec_align2; + +struct ec_response_usb_pd_power_info { + uint8_t role; + uint8_t type; + uint8_t dualrole; + uint8_t reserved1; + struct usb_chg_measures meas; + uint32_t max_power; +} __ec_align4; + +/* + * This command will return the number of USB PD charge port + the number + * of dedicated port present. + * EC_CMD_USB_PD_PORTS does NOT include the dedicated ports + */ +#define EC_CMD_CHARGE_PORT_COUNT 0x0105 +struct ec_response_charge_port_count { + uint8_t port_count; +} __ec_align1; + +/* + * This command enable/disable dynamic PDO selection. + */ +#define EC_CMD_USB_PD_DPS_CONTROL 0x0106 + +struct ec_params_usb_pd_dps_control { + uint8_t enable; +} __ec_align1; + +/* + * This command return the status of dynamic PDO selection. + */ +#define EC_CMD_USB_PD_DPS_STATUS 0x0107 + +struct ec_response_usb_pd_dps_status { + int32_t is_enabled; + int32_t port; + int32_t requested_voltage; + int32_t requested_current; + int32_t input_power; + int32_t input_voltage; + int32_t input_current; + int32_t efficient_voltage; + int32_t battery_voltage; + int32_t max_voltage; +} __ec_align4; + +/* Write USB-PD device FW */ +#define EC_CMD_USB_PD_FW_UPDATE 0x0110 + +enum usb_pd_fw_update_cmds { + USB_PD_FW_REBOOT, + USB_PD_FW_FLASH_ERASE, + USB_PD_FW_FLASH_WRITE, + USB_PD_FW_ERASE_SIG, +}; + +struct ec_params_usb_pd_fw_update { + uint16_t dev_id; + uint8_t cmd; + uint8_t port; + + /* Size to write in bytes */ + uint32_t size; + + /* Followed by data to write */ +} __ec_align4; + +/* Write USB-PD Accessory RW_HASH table entry */ +#define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111 +/* RW hash is first 20 bytes of SHA-256 of RW section */ +#define PD_RW_HASH_SIZE 20 +struct ec_params_usb_pd_rw_hash_entry { + uint16_t dev_id; + uint8_t dev_rw_hash[PD_RW_HASH_SIZE]; + + /* + * Reserved for alignment of current_image + * TODO(rspangler) but it's not aligned! + * Should have been reserved[2]. + */ + uint8_t reserved; + + /* One of ec_image */ + uint32_t current_image; +} __ec_align1; + +/* Read USB-PD Accessory info */ +#define EC_CMD_USB_PD_DEV_INFO 0x0112 + +struct ec_params_usb_pd_info_request { + uint8_t port; +} __ec_align1; + +/* Read USB-PD Device discovery info */ +#define EC_CMD_USB_PD_DISCOVERY 0x0113 +struct ec_params_usb_pd_discovery_entry { + uint16_t vid; /* USB-IF VID */ + uint16_t pid; /* USB-IF PID */ + uint8_t ptype; /* product type (hub,periph,cable,ama) */ +} __ec_align_size1; + +/* Override default charge behavior */ +#define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114 + +/* Negative port parameters have special meaning */ +enum usb_pd_override_ports { + /* + * DONT_CHARGE is for all ports. Thus it's persistent across plug-in + * or plug-out. + */ + OVERRIDE_DONT_CHARGE = -2, + OVERRIDE_OFF = -1, + /* [0, CONFIG_USB_PD_PORT_MAX_COUNT): Port# */ +}; + +struct ec_params_charge_port_override { + int16_t override_port; /* Override port# */ +} __ec_align2; + +/* + * Read (and delete) one entry of PD event log. + * TODO(crbug.com/751742): Make this host command more generic to accommodate + * future non-PD logs that use the same internal EC event_log. + */ +#define EC_CMD_PD_GET_LOG_ENTRY 0x0115 + +struct ec_response_pd_log { + uint32_t timestamp; /* relative timestamp in milliseconds */ + uint8_t type; /* event type : see PD_EVENT_xx below */ + uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ + uint16_t data; /* type-defined data payload */ + /* optional additional data payload: 0..16 bytes */ + uint8_t payload[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; + +/* The timestamp is the microsecond counter shifted to get about a ms. */ +#define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ + +#define PD_LOG_SIZE_MASK 0x1f +#define PD_LOG_PORT_MASK 0xe0 +#define PD_LOG_PORT_SHIFT 5 +#define PD_LOG_PORT_SIZE(port, size) \ + (((port) << PD_LOG_PORT_SHIFT) | ((size) & PD_LOG_SIZE_MASK)) +#define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT) +#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK) + +/* PD event log : entry types */ +/* PD MCU events */ +#define PD_EVENT_MCU_BASE 0x00 +#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE + 0) +#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE + 1) +/* Reserved for custom board event */ +#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE + 2) +/* PD generic accessory events */ +#define PD_EVENT_ACC_BASE 0x20 +#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE + 0) +#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE + 1) +/* PD power supply events */ +#define PD_EVENT_PS_BASE 0x40 +#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE + 0) +/* PD video dongles events */ +#define PD_EVENT_VIDEO_BASE 0x60 +#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE + 0) +#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE + 1) +/* Returned in the "type" field, when there is no entry available */ +#define PD_EVENT_NO_ENTRY 0xff + +/* + * PD_EVENT_MCU_CHARGE event definition : + * the payload is "struct usb_chg_measures" + * the data field contains the port state flags as defined below : + */ +/* Port partner is a dual role device */ +#define CHARGE_FLAGS_DUAL_ROLE BIT(15) +/* Port is the pending override port */ +#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14) +/* Port is the override port */ +#define CHARGE_FLAGS_OVERRIDE BIT(13) +/* Charger type */ +#define CHARGE_FLAGS_TYPE_SHIFT 3 +#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) +/* Power delivery role */ +#define CHARGE_FLAGS_ROLE_MASK (7 << 0) + +/* + * PD_EVENT_PS_FAULT data field flags definition : + */ +#define PS_FAULT_OCP 1 +#define PS_FAULT_FAST_OCP 2 +#define PS_FAULT_OVP 3 +#define PS_FAULT_DISCH 4 + +/* + * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info". + */ +struct mcdp_version { + uint8_t major; + uint8_t minor; + uint16_t build; +} __ec_align4; + +struct mcdp_info { + uint8_t family[2]; + uint8_t chipid[2]; + struct mcdp_version irom; + struct mcdp_version fw; +} __ec_align4; + +/* struct mcdp_info field decoding */ +#define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1]) +#define MCDP_FAMILY(family) ((family[0] << 8) | family[1]) + +/* Get/Set USB-PD Alternate mode info */ +#define EC_CMD_USB_PD_GET_AMODE 0x0116 +struct ec_params_usb_pd_get_mode_request { + uint16_t svid_idx; /* SVID index to get */ + uint8_t port; /* port */ +} __ec_align_size1; + +#define VDO_MAX_SIZE 7 +/* Max number of VDM data objects without VDM header */ +#define VDO_MAX_OBJECTS (VDO_MAX_SIZE - 1) + +struct ec_params_usb_pd_get_mode_response { + uint16_t svid; /* SVID */ + uint16_t opos; /* Object Position */ + uint32_t vdo[VDO_MAX_OBJECTS]; /* Mode VDOs */ +} __ec_align4; + +#define EC_CMD_USB_PD_SET_AMODE 0x0117 + +enum pd_mode_cmd { + PD_EXIT_MODE = 0, + PD_ENTER_MODE = 1, + /* Not a command. Do NOT remove. */ + PD_MODE_CMD_COUNT, +}; + +struct ec_params_usb_pd_set_mode_request { + uint32_t cmd; /* enum pd_mode_cmd */ + uint16_t svid; /* SVID to set */ + uint8_t opos; /* Object Position */ + uint8_t port; /* port */ +} __ec_align4; + +/* Ask the PD MCU to record a log of a requested type */ +#define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118 + +struct ec_params_pd_write_log_entry { + uint8_t type; /* event type : see PD_EVENT_xx above */ + uint8_t port; /* port#, or 0 for events unrelated to a given port */ +} __ec_align1; + +/* Control USB-PD chip */ +#define EC_CMD_PD_CONTROL 0x0119 + +enum ec_pd_control_cmd { + PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */ + PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */ + PD_RESET, /* Force reset the PD chip */ + PD_CONTROL_DISABLE, /* Disable further calls to this command */ + PD_CHIP_ON, /* Power on the PD chip */ +}; + +struct ec_params_pd_control { + uint8_t chip; /* chip id */ + uint8_t subcmd; +} __ec_align1; + +/* Get info about USB-C SS muxes */ +#define EC_CMD_USB_PD_MUX_INFO 0x011A + +struct ec_params_usb_pd_mux_info { + uint8_t port; /* USB-C port number */ +} __ec_align1; + +/* Flags representing mux state */ +#define USB_PD_MUX_NONE 0 /* Open switch */ +#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ +#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ +#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ +#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ +#define USB_PD_MUX_HPD_IRQ_DEASSERTED 0 /* HPD IRQ is deasserted */ +#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ +#define USB_PD_MUX_HPD_LVL_DEASSERTED 0 /* HPD level is deasserted */ +#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */ +#define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */ +#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */ + +/* USB-C Dock connected */ +#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED) + +struct ec_response_usb_pd_mux_info { + uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ +} __ec_align1; + +#define EC_CMD_PD_CHIP_INFO 0x011B + +struct ec_params_pd_chip_info { + uint8_t port; /* USB-C port number */ + /* + * Fetch the live chip info or hard-coded + cached chip info + * 0: hardcoded value for VID/PID, cached value for FW version + * 1: live chip value for VID/PID/FW Version + */ + uint8_t live; +} __ec_align1; + +struct ec_response_pd_chip_info { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + } __ec_align2; +} __ec_align2; + +struct ec_response_pd_chip_info_v1 { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + } __ec_align2; + union { + uint8_t min_req_fw_version_string[8]; + uint64_t min_req_fw_version_number; + } __ec_align2; +} __ec_align2; + +/** Indicates the chip should NOT receive a firmware update, if set. This is + * useful when multiple ports are serviced by a single chip, to avoid + * performing redundant updates. The host command implementation shall ensure + * only one port out of each physical chip has FW updates active. + */ +#define USB_PD_CHIP_INFO_FWUP_FLAG_NO_UPDATE BIT(0) + +/** Maximum length of a project name embedded in a PDC FW image. This length + * does NOT include a NUL-terminator. + */ +#define USB_PD_CHIP_INFO_PROJECT_NAME_LEN 12 + +struct ec_response_pd_chip_info_v2 { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + } __ec_align2; + union { + uint8_t min_req_fw_version_string[8]; + uint64_t min_req_fw_version_number; + } __ec_align2; + /** Flag to control the FW update process for this chip. */ + uint16_t fw_update_flags; + /** Project name string associated with the chip's FW. Add an extra + * byte for a NUL-terminator. + */ + char fw_name_str[USB_PD_CHIP_INFO_PROJECT_NAME_LEN + 1]; +} __ec_align2; + +/** Maximum length of a driver/chip name reported in the pd_chip_info + * response + */ +#define USB_PD_CHIP_INFO_DRIVER_NAME_LEN 24 + +struct ec_response_pd_chip_info_v3 { + uint16_t vendor_id; + uint16_t product_id; + uint16_t device_id; + union { + uint8_t fw_version_string[8]; + uint64_t fw_version_number; + } __ec_align2; + union { + uint8_t min_req_fw_version_string[8]; + uint64_t min_req_fw_version_number; + } __ec_align2; + /** Flag to control the FW update process for this chip. */ + uint16_t fw_update_flags; + /** Project name string associated with the chip's FW. Add an extra + * byte for a NUL-terminator. + */ + char fw_name_str[USB_PD_CHIP_INFO_PROJECT_NAME_LEN + 1]; + /** Driver/chip string, plus room for a NUL-terminator */ + char driver_name[USB_PD_CHIP_INFO_DRIVER_NAME_LEN + 1]; +} __ec_align2; + +/* Run RW signature verification and get status */ +#define EC_CMD_RWSIG_CHECK_STATUS 0x011C + +struct ec_response_rwsig_check_status { + uint32_t status; +} __ec_align4; + +/* For controlling RWSIG task */ +#define EC_CMD_RWSIG_ACTION 0x011D + +enum rwsig_action { + RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */ + RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ +}; + +struct ec_params_rwsig_action { + uint32_t action; +} __ec_align4; + +/* Run verification on a slot */ +#define EC_CMD_EFS_VERIFY 0x011E + +struct ec_params_efs_verify { + uint8_t region; /* enum ec_flash_region */ +} __ec_align1; + +/* + * Retrieve info from Cros Board Info store. Response is based on the data + * type. Integers return a uint32. Strings return a string, using the response + * size to determine how big it is. + */ +#define EC_CMD_GET_CROS_BOARD_INFO 0x011F +/* + * Write info into Cros Board Info on EEPROM. Write fails if the board has + * hardware write-protect enabled. + */ +#define EC_CMD_SET_CROS_BOARD_INFO 0x0120 + +enum cbi_data_tag { + CBI_TAG_BOARD_VERSION = 0, /* uint32_t or smaller */ + CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */ + CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */ + CBI_TAG_DRAM_PART_NUM = 3, /* variable length ascii, nul terminated. */ + CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */ + CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ + CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ + CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ + /* Second Source Factory Cache */ + CBI_TAG_SSFC = 8, /* uint32_t bit field */ + CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */ + CBI_TAG_FACTORY_CALIBRATION_DATA = 10, /* Deprecated */ + CBI_TAG_COMMON_CONTROL = 11, /* Deprecated */ + /* struct board_batt_params */ + CBI_TAG_BATTERY_CONFIG = 12, + /* CBI_TAG_BATTERY_CONFIG_1 ~ 15 will use 13 ~ 27. */ + CBI_TAG_BATTERY_CONFIG_15 = 27, + + /* CBI_TAG_PROVISION_MATRIX_VERSION + * Version of the current provision matrix + */ + CBI_TAG_PROVISION_MATRIX_VERSION = 28, /* uint32_t bit field */ + + /* Unified Firmware and Second-source Config: + * A fixed-size array of 4 uint32_t values. + */ + CBI_TAG_UFSC = 29, + + /* Last entry */ + CBI_TAG_COUNT, +}; + +#define CBI_UFSC_DATA_COUNT 4 + +/* Unified Firmware and Second-source Config (UFSC) data structure */ +struct cbi_ufsc { + uint32_t data[CBI_UFSC_DATA_COUNT]; +}; + +/* + * Flags to control read operation + * + * RELOAD: Invalidate cache and read data from EEPROM. Useful to verify + * write was successful without reboot. + */ +#define CBI_GET_RELOAD BIT(0) + +struct ec_params_get_cbi { + uint32_t tag; /* enum cbi_data_tag */ + uint32_t flag; /* CBI_GET_* */ +} __ec_align4; + +/* + * Flags to control write behavior. + * + * NO_SYNC: Makes EC update data in RAM but skip writing to EEPROM. It's + * useful when writing multiple fields in a row. + * INIT: Need to be set when creating a new CBI from scratch. All fields + * will be initialized to zero first. + */ +#define CBI_SET_NO_SYNC BIT(0) +#define CBI_SET_INIT BIT(1) + +struct ec_params_set_cbi { + uint32_t tag; /* enum cbi_data_tag */ + uint32_t flag; /* CBI_SET_* */ + uint32_t size; /* Data size */ + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; /* For string and raw data */ +} __ec_align1; + +/* + * Retrieve binary from CrOS Board Info primary memory source. + */ +#define EC_CMD_CBI_BIN_READ 0x0504 +/* + * Write binary into CrOS Board Info temporary buffer and then commit it to + * permanent storage once complete. Write fails if the board has hardware + * write-protect enabled. + */ +#define EC_CMD_CBI_BIN_WRITE 0x0505 + +/* + * CBI binary read/write flags + * The default write behavior is to always append any data to the buffer. + * If 'CLEAR' flag is set, buffer is cleared then data is appended. + * If 'WRITE' flag is set, data is appended then buffer is written to memory. + */ +#define EC_CBI_BIN_BUFFER_CLEAR BIT(0) +#define EC_CBI_BIN_BUFFER_WRITE BIT(1) + +struct ec_params_get_cbi_bin { + uint32_t offset; /* Data offset */ + uint32_t size; /* Data size */ +} __ec_align4; + +struct ec_params_set_cbi_bin { + uint32_t offset; /* Data offset */ + uint32_t size; /* Data size */ + uint8_t flags; /* bit field for EC_CBI_BIN_COMMIT_FLAG_* */ + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; /* For string and raw data */ +} __ec_align1; + +/* + * Information about resets of the AP by the EC and the EC's own uptime. + */ +#define EC_CMD_GET_UPTIME_INFO 0x0121 + +/* EC reset causes */ +#define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */ +#define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */ +#define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */ +#define EC_RESET_FLAG_POWER_ON BIT(3) /* Power-on reset */ +#define EC_RESET_FLAG_WATCHDOG BIT(4) /* Watchdog timer reset */ +#define EC_RESET_FLAG_SOFT BIT(5) /* Soft reset trigger by core */ +#define EC_RESET_FLAG_HIBERNATE BIT(6) /* Wake from hibernate */ +#define EC_RESET_FLAG_RTC_ALARM BIT(7) /* RTC alarm wake */ +#define EC_RESET_FLAG_WAKE_PIN BIT(8) /* Wake pin triggered wake */ +#define EC_RESET_FLAG_LOW_BATTERY BIT(9) /* Low battery triggered wake */ +#define EC_RESET_FLAG_SYSJUMP BIT(10) /* Jumped directly to this image */ +#define EC_RESET_FLAG_HARD BIT(11) /* Hard reset from software */ +#define EC_RESET_FLAG_AP_OFF BIT(12) /* Do not power on AP */ +/* Some reset flags preserved from previous boot */ +#define EC_RESET_FLAG_PRESERVED BIT(13) +#define EC_RESET_FLAG_USB_RESUME BIT(14) /* USB resume triggered wake */ +#define EC_RESET_FLAG_RDD BIT(15) /* USB Type-C debug cable */ +#define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */ +#define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */ +/* AP experienced a watchdog reset */ +#define EC_RESET_FLAG_AP_WATCHDOG BIT(18) +/* Do not select RW in EFS. This enables PD in RO for Chromebox. */ +#define EC_RESET_FLAG_STAY_IN_RO BIT(19) +#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */ +#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ +#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ + +/* + * Reason codes used by the AP after a shutdown to figure out why it was reset + * by the EC. These are sent in EC commands. Therefore, to maintain protocol + * compatibility: + * - New entries must be inserted prior to the _COUNT field + * - If an existing entry is no longer in service, it must be replaced with a + * RESERVED entry instead. + * - The semantic meaning of an entry should not change. + * - Do not exceed 2^15 - 1 for reset reasons or 2^16 - 1 for shutdown reasons. + */ +enum chipset_shutdown_reason { + /* + * Beginning of reset reasons. + */ + CHIPSET_RESET_BEGIN = 0, + CHIPSET_RESET_UNKNOWN = CHIPSET_RESET_BEGIN, + /* Custom reason defined by a board.c or baseboard.c file */ + CHIPSET_RESET_BOARD_CUSTOM, + /* Believe that the AP has hung */ + CHIPSET_RESET_HANG_REBOOT, + /* Reset by EC console command */ + CHIPSET_RESET_CONSOLE_CMD, + /* Reset by EC host command */ + CHIPSET_RESET_HOST_CMD, + /* Keyboard module reset key combination */ + CHIPSET_RESET_KB_SYSRESET, + /* Keyboard module warm reboot */ + CHIPSET_RESET_KB_WARM_REBOOT, + /* Debug module warm reboot */ + CHIPSET_RESET_DBG_WARM_REBOOT, + /* I cannot self-terminate. You must lower me into the steel. */ + CHIPSET_RESET_AP_REQ, + /* Reset as side-effect of startup sequence */ + CHIPSET_RESET_INIT, + /* EC detected an AP watchdog event. */ + CHIPSET_RESET_AP_WATCHDOG, + + CHIPSET_RESET_COUNT, /* End of reset reasons. */ + + /* + * Beginning of shutdown reasons. + */ + CHIPSET_SHUTDOWN_BEGIN = BIT(15), + CHIPSET_SHUTDOWN_POWERFAIL = CHIPSET_SHUTDOWN_BEGIN, + /* Forcing a shutdown as part of EC initialization */ + CHIPSET_SHUTDOWN_INIT, + /* Custom reason on a per-board basis. */ + CHIPSET_SHUTDOWN_BOARD_CUSTOM, + /* This is a reason to inhibit startup, not cause shut down. */ + CHIPSET_SHUTDOWN_BATTERY_INHIBIT, + /* A power_wait_signal is being asserted */ + CHIPSET_SHUTDOWN_WAIT, + /* Critical battery level. */ + CHIPSET_SHUTDOWN_BATTERY_CRIT, + /* Because you told me to. */ + CHIPSET_SHUTDOWN_CONSOLE_CMD, + /* Forcing a shutdown to effect entry to G3. */ + CHIPSET_SHUTDOWN_G3, + /* Force shutdown due to over-temperature. */ + CHIPSET_SHUTDOWN_THERMAL, + /* Force a chipset shutdown from the power button through EC */ + CHIPSET_SHUTDOWN_BUTTON, + /* Force a chipset shutdown, because the AP wants to. */ + CHIPSET_SHUTDOWN_HOST_CMD, + + CHIPSET_SHUTDOWN_COUNT, /* End of shutdown reasons. */ +}; + +struct ec_response_uptime_info { + /* + * Number of milliseconds since the last EC boot. Sysjump resets + * typically do not restart the EC's time_since_boot epoch. + * + * WARNING: The EC's sense of time is much less accurate than the AP's + * sense of time, in both phase and frequency. This timebase is similar + * to CLOCK_MONOTONIC_RAW, but with 1% or more frequency error. + */ + uint32_t time_since_ec_boot_ms; + + /* + * Number of times the AP was reset by the EC since the last EC boot. + * Note that the AP may be held in reset by the EC during the initial + * boot sequence, such that the very first AP boot may count as more + * than one here. + */ + uint32_t ap_resets_since_ec_boot; + + /* + * The set of flags which describe the EC's most recent reset. + * See EC_RESET_FLAG_* for details. + */ + uint32_t ec_reset_flags; + + /* Empty log entries have both the cause and timestamp set to zero. */ + struct ap_reset_log_entry { + /* See enum chipset_{reset,shutdown}_reason for details. */ + uint16_t reset_cause; + + /* Reserved for protocol growth. */ + uint16_t reserved; + + /* + * The time of the reset's assertion, in milliseconds since the + * last EC boot, in the same epoch as time_since_ec_boot_ms. + * Set to zero if the log entry is empty. + */ + uint32_t reset_time_ms; + } recent_ap_reset[4]; +} __ec_align4; + +/* + * Add entropy to the device secret (stored in the rollback region). + * + * Depending on the chip, the operation may take a long time (e.g. to erase + * flash), so the commands are asynchronous. + */ +#define EC_CMD_ADD_ENTROPY 0x0122 + +enum add_entropy_action { + /* Add entropy to the current secret. */ + ADD_ENTROPY_ASYNC = 0, + /* + * Add entropy, and also make sure that the previous secret is erased. + * (this can be implemented by adding entropy multiple times until + * all rolback blocks have been overwritten). + */ + ADD_ENTROPY_RESET_ASYNC = 1, + /* Read back result from the previous operation. */ + ADD_ENTROPY_GET_RESULT = 2, +}; + +struct ec_params_rollback_add_entropy { + uint8_t action; +} __ec_align1; + +/* + * Perform a single read of a given ADC channel. + */ +#define EC_CMD_ADC_READ 0x0123 + +struct ec_params_adc_read { + uint8_t adc_channel; +} __ec_align1; + +struct ec_response_adc_read { + int32_t adc_value; +} __ec_align4; + +/* + * Read back rollback info + */ +#define EC_CMD_ROLLBACK_INFO 0x0124 + +struct ec_response_rollback_info { + int32_t id; /* Incrementing number to indicate which region to use. */ + int32_t rollback_min_version; + int32_t rw_rollback_version; +} __ec_align4; + +struct ec_response_rollback_info_v1 { + int32_t id; /* Incrementing number to indicate which region to use. */ + int32_t rollback_min_version; + int32_t rw_rollback_version; + uint8_t is_secret_inited; + uint8_t reserved[3]; +} __ec_align4; + +/* Issue AP reset */ +#define EC_CMD_AP_RESET 0x0125 + +/*****************************************************************************/ +/* Locate peripheral chips + * + * Return values: + * EC_RES_UNAVAILABLE: The chip type is supported but not found on system. + * EC_RES_INVALID_PARAM: The chip type was unrecognized. + * EC_RES_OVERFLOW: The index number exceeded the number of chip instances. + */ +#define EC_CMD_LOCATE_CHIP 0x0126 + +enum ec_chip_type { + EC_CHIP_TYPE_CBI_EEPROM = 0, + EC_CHIP_TYPE_TCPC = 1, + EC_CHIP_TYPE_PDC = 2, + EC_CHIP_TYPE_COUNT, + EC_CHIP_TYPE_MAX = 0xFF, +}; + +enum ec_bus_type { + EC_BUS_TYPE_I2C = 0, + EC_BUS_TYPE_EMBEDDED = 1, + EC_BUS_TYPE_COUNT, + EC_BUS_TYPE_MAX = 0xFF, +}; + +struct ec_i2c_info { + uint16_t port; /* Physical port for device */ + uint16_t addr_flags; /* 7-bit (or 10-bit) address */ +}; + +struct ec_params_locate_chip { + uint8_t type; /* enum ec_chip_type */ + uint8_t index; /* Specifies one instance of chip type */ + /* Used for type specific parameters in future */ + union { + uint16_t reserved; + }; +} __ec_align2; + +struct ec_response_locate_chip { + uint8_t bus_type; /* enum ec_bus_type */ + uint8_t reserved; /* Aligning the following union to 2 bytes */ + union { + struct ec_i2c_info i2c_info; + }; +} __ec_align2; + +/* + * Reboot AP on G3 + * + * This command is used for validation purpose, where the AP needs to be + * returned back to S0 state from G3 state without using the servo to trigger + * wake events. + * - With command version 0: + * AP reboots immediately from G3 + * command usage: ectool reboot_ap_on_g3 && shutdown -h now + * - With command version 1: + * AP reboots after the user specified delay + * command usage: ectool reboot_ap_on_g3 [] && shutdown -h now + */ +#define EC_CMD_REBOOT_AP_ON_G3 0x0127 + +struct ec_params_reboot_ap_on_g3_v1 { + /* configurable delay in seconds in G3 state */ + uint32_t reboot_ap_at_g3_delay; +} __ec_align4; + +/*****************************************************************************/ +/* Get PD port capabilities + * + * Returns the following static *capabilities* of the given port: + * 1) Power role: source, sink, or dual. It is not anticipated that + * future CrOS devices would ever be only a source, so the options are + * sink or dual. + * 2) Try-power role: source, sink, or none (practically speaking, I don't + * believe any CrOS device would support Try.SNK, so this would be source + * or none). + * 3) Data role: dfp, ufp, or dual. This will probably only be DFP or dual + * for CrOS devices. + */ +#define EC_CMD_GET_PD_PORT_CAPS 0x0128 + +enum ec_pd_power_role_caps { + EC_PD_POWER_ROLE_SOURCE = 0, + EC_PD_POWER_ROLE_SINK = 1, + EC_PD_POWER_ROLE_DUAL = 2, +}; + +enum ec_pd_try_power_role_caps { + EC_PD_TRY_POWER_ROLE_NONE = 0, + EC_PD_TRY_POWER_ROLE_SINK = 1, + EC_PD_TRY_POWER_ROLE_SOURCE = 2, +}; + +enum ec_pd_data_role_caps { + EC_PD_DATA_ROLE_DFP = 0, + EC_PD_DATA_ROLE_UFP = 1, + EC_PD_DATA_ROLE_DUAL = 2, +}; + +/* From: power_manager/power_supply_properties.proto */ +enum ec_pd_port_location { + /* The location of the port is unknown, or there's only one port. */ + EC_PD_PORT_LOCATION_UNKNOWN = 0, + + /* + * Various positions on the device. The first word describes the side of + * the device where the port is located while the second clarifies the + * position. For example, LEFT_BACK means the farthest-back port on the + * left side, while BACK_LEFT means the leftmost port on the back of the + * device. + */ + EC_PD_PORT_LOCATION_LEFT = 1, + EC_PD_PORT_LOCATION_RIGHT = 2, + EC_PD_PORT_LOCATION_BACK = 3, + EC_PD_PORT_LOCATION_FRONT = 4, + EC_PD_PORT_LOCATION_LEFT_FRONT = 5, + EC_PD_PORT_LOCATION_LEFT_BACK = 6, + EC_PD_PORT_LOCATION_RIGHT_FRONT = 7, + EC_PD_PORT_LOCATION_RIGHT_BACK = 8, + EC_PD_PORT_LOCATION_BACK_LEFT = 9, + EC_PD_PORT_LOCATION_BACK_RIGHT = 10, +}; + +struct ec_params_get_pd_port_caps { + uint8_t port; /* Which port to interrogate */ +} __ec_align1; + +struct ec_response_get_pd_port_caps { + uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */ + uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */ + uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */ + uint8_t pd_port_location; /* enum ec_pd_port_location */ +} __ec_align1; + +/*****************************************************************************/ +/* + * Button press simulation + * + * This command is used to simulate a button press. + * Supported commands are vup(volume up) vdown(volume down) & rec(recovery) + * Time duration for which button needs to be pressed is an optional parameter. + * + * NOTE: This is only available on unlocked devices for testing purposes only. + */ +#define EC_CMD_BUTTON 0x0129 + +struct ec_params_button { + /* Button mask aligned to enum keyboard_button_type */ + uint32_t btn_mask; + + /* Duration in milliseconds button needs to be pressed */ + uint32_t press_ms; +} __ec_align1; + +enum keyboard_button_type { + KEYBOARD_BUTTON_POWER = 0, + KEYBOARD_BUTTON_VOLUME_DOWN = 1, + KEYBOARD_BUTTON_VOLUME_UP = 2, + KEYBOARD_BUTTON_RECOVERY = 3, + KEYBOARD_BUTTON_CAPSENSE_1 = 4, + KEYBOARD_BUTTON_CAPSENSE_2 = 5, + KEYBOARD_BUTTON_CAPSENSE_3 = 6, + KEYBOARD_BUTTON_CAPSENSE_4 = 7, + KEYBOARD_BUTTON_CAPSENSE_5 = 8, + KEYBOARD_BUTTON_CAPSENSE_6 = 9, + KEYBOARD_BUTTON_CAPSENSE_7 = 10, + KEYBOARD_BUTTON_CAPSENSE_8 = 11, + + KEYBOARD_BUTTON_COUNT, +}; + +/*****************************************************************************/ +/* + * "Get the Keyboard Config". An EC implementing this command is expected to be + * vivaldi capable, i.e. can send action codes for the top row keys. + * Additionally, capability to send function codes for the same keys is + * optional and acceptable. + * + * Note: If the top row can generate both function and action codes by + * using a dedicated Fn key, it does not matter whether the key sends + * "function" or "action" codes by default. In both cases, the response + * for this command will look the same. + */ +#define EC_CMD_GET_KEYBD_CONFIG 0x012A + +/* Possible values for the top row keys */ +enum action_key { + TK_ABSENT = 0, + TK_BACK = 1, + TK_FORWARD = 2, + TK_REFRESH = 3, + TK_FULLSCREEN = 4, + TK_OVERVIEW = 5, + TK_BRIGHTNESS_DOWN = 6, + TK_BRIGHTNESS_UP = 7, + TK_VOL_MUTE = 8, + TK_VOL_DOWN = 9, + TK_VOL_UP = 10, + TK_SNAPSHOT = 11, + TK_PRIVACY_SCRN_TOGGLE = 12, + TK_KBD_BKLIGHT_DOWN = 13, + TK_KBD_BKLIGHT_UP = 14, + TK_PLAY_PAUSE = 15, + TK_NEXT_TRACK = 16, + TK_PREV_TRACK = 17, + TK_KBD_BKLIGHT_TOGGLE = 18, + TK_MICMUTE = 19, + TK_MENU = 20, + TK_DICTATE = 21, + TK_ACCESSIBILITY = 22, + TK_DONOTDISTURB = 23, + TK_HOME = 24, + + TK_COUNT +}; + +/* + * Max & Min number of top row keys, excluding Esc and Screenlock keys. + * If this needs to change, please create a new version of the command. + */ +#define MAX_TOP_ROW_KEYS 15 +#define MIN_TOP_ROW_KEYS 10 + +/* + * Is the keyboard capable of sending function keys *in addition to* + * action keys. This is possible for e.g. if the keyboard has a + * dedicated Fn key. + */ +#define KEYBD_CAP_FUNCTION_KEYS BIT(0) +/* + * Whether the keyboard has a dedicated numeric keyboard. + */ +#define KEYBD_CAP_NUMERIC_KEYPAD BIT(1) +/* + * Whether the keyboard has a screenlock key. + */ +#define KEYBD_CAP_SCRNLOCK_KEY BIT(2) + +/* + * Whether the keyboard has an assistant key. + */ +#define KEYBD_CAP_ASSISTANT_KEY BIT(3) + +struct ec_response_keybd_config { + /* + * Number of top row keys, excluding Esc and Screenlock. + * If this is 0, all Vivaldi keyboard code is disabled. + * (i.e. does not expose any tables to the kernel). + */ + uint8_t num_top_row_keys; + + /* + * The action keys in the top row, in order from left to right. + * The values are filled from enum action_key. Esc and Screenlock + * keys are not considered part of top row keys. + */ + uint8_t action_keys[MAX_TOP_ROW_KEYS]; + + /* Capability flags */ + uint8_t capabilities; + +} __ec_align1; + +/* + * Configure smart discharge + */ +#define EC_CMD_SMART_DISCHARGE 0x012B + +#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0) + +/* Discharge rates when the system is in cutoff or hibernation. */ +struct discharge_rate { + uint16_t cutoff; /* Discharge rate (uA) in cutoff */ + uint16_t hibern; /* Discharge rate (uA) in hibernation */ +}; + +struct smart_discharge_zone { + /* When the capacity (mAh) goes below this, EC cuts off the battery. */ + int cutoff; + /* When the capacity (mAh) is below this, EC stays up. */ + int stayup; +}; + +struct ec_params_smart_discharge { + uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */ + /* + * Desired hours for the battery to survive before reaching 0%. Set to + * zero to disable smart discharging. That is, the system hibernates as + * soon as the G3 idle timer expires. + */ + uint16_t hours_to_zero; + /* Set both to zero to keep the current rates. */ + struct discharge_rate drate; +}; + +struct ec_response_smart_discharge { + uint16_t hours_to_zero; + struct discharge_rate drate; + struct smart_discharge_zone dzone; +}; + +/*****************************************************************************/ +/* Voltage regulator controls */ + +/* + * Get basic info of voltage regulator for given index. + * + * Returns the regulator name and supported voltage list in mV. + */ +#define EC_CMD_REGULATOR_GET_INFO 0x012C + +/* Maximum length of regulator name */ +#define EC_REGULATOR_NAME_MAX_LEN 16 + +/* Maximum length of the supported voltage list. */ +#define EC_REGULATOR_VOLTAGE_MAX_COUNT 16 + +struct ec_params_regulator_get_info { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_get_info { + char name[EC_REGULATOR_NAME_MAX_LEN]; + uint16_t num_voltages; + uint16_t voltages_mv[EC_REGULATOR_VOLTAGE_MAX_COUNT]; +} __ec_align2; + +/* + * Configure the regulator as enabled / disabled. + */ +#define EC_CMD_REGULATOR_ENABLE 0x012D + +struct ec_params_regulator_enable { + uint32_t index; + uint8_t enable; +} __ec_align4; + +/* + * Query if the regulator is enabled. + * + * Returns 1 if the regulator is enabled, 0 if not. + */ +#define EC_CMD_REGULATOR_IS_ENABLED 0x012E + +struct ec_params_regulator_is_enabled { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_is_enabled { + uint8_t enabled; +} __ec_align1; /* - * Retrieve info from Cros Board Info store. Response is based on the data - * type. Integers return a uint32. Strings return a string, using the response - * size to determine how big it is. + * Set voltage for the voltage regulator within the range specified. + * + * The driver should select the voltage in range closest to min_mv. + * + * Also note that this might be called before the regulator is enabled, and the + * setting should be in effect after the regulator is enabled. */ -#define EC_CMD_GET_CROS_BOARD_INFO 0x011F +#define EC_CMD_REGULATOR_SET_VOLTAGE 0x012F + +struct ec_params_regulator_set_voltage { + uint32_t index; + uint32_t min_mv; + uint32_t max_mv; +} __ec_align4; + /* - * Write info into Cros Board Info on EEPROM. Write fails if the board has - * hardware write-protect enabled. + * Get the currently configured voltage for the voltage regulator. + * + * Note that this might be called before the regulator is enabled, and this + * should return the configured output voltage if the regulator is enabled. */ -#define EC_CMD_SET_CROS_BOARD_INFO 0x0120 +#define EC_CMD_REGULATOR_GET_VOLTAGE 0x0130 -enum cbi_data_tag { - CBI_TAG_BOARD_VERSION = 0, /* uint16_t or uint8_t[] = {minor,major} */ - CBI_TAG_OEM_ID = 1, /* uint8_t */ - CBI_TAG_SKU_ID = 2, /* uint8_t */ - CBI_TAG_COUNT, +struct ec_params_regulator_get_voltage { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_get_voltage { + uint32_t voltage_mv; +} __ec_align4; + +/* + * Gather all discovery information for the given port and partner type. + * + * Note that if discovery has not yet completed, only the currently completed + * responses will be filled in. If the discovery data structures are changed + * in the process of the command running, BUSY will be returned. + * + * VDO field sizes are set to the maximum possible number of VDOs a VDM may + * contain, while the number of SVIDs here is selected to fit within the PROTO2 + * maximum parameter size. + */ +#define EC_CMD_TYPEC_DISCOVERY 0x0131 + +enum typec_partner_type { + TYPEC_PARTNER_SOP = 0, + TYPEC_PARTNER_SOP_PRIME = 1, + TYPEC_PARTNER_SOP_PRIME_PRIME = 2, +}; + +struct ec_params_typec_discovery { + uint8_t port; + uint8_t partner_type; /* enum typec_partner_type */ +} __ec_align1; + +struct svid_mode_info { + uint16_t svid; + uint16_t mode_count; /* Number of modes partner sent */ + uint32_t mode_vdo[VDO_MAX_OBJECTS]; +}; + +struct ec_response_typec_discovery { + uint8_t identity_count; /* Number of identity VDOs partner sent */ + uint8_t svid_count; /* Number of SVIDs partner sent */ + uint16_t reserved; + uint32_t discovery_vdo[VDO_MAX_OBJECTS]; + struct svid_mode_info svids[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align1; + +/* USB Type-C commands for AP-controlled device policy. */ +#define EC_CMD_TYPEC_CONTROL 0x0132 + +enum typec_control_command { + TYPEC_CONTROL_COMMAND_EXIT_MODES, + TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, + TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY, + TYPEC_CONTROL_COMMAND_USB_MUX_SET, + TYPEC_CONTROL_COMMAND_BIST_SHARE_MODE, + TYPEC_CONTROL_COMMAND_SEND_VDM_REQ, }; +/* Modes (USB or alternate) that a type-C port may enter. */ +enum typec_mode { + TYPEC_MODE_DP, + TYPEC_MODE_TBT, + TYPEC_MODE_USB4, +}; + +/* Replies the AP may specify to the TBT EnterMode command as a UFP */ +enum typec_tbt_ufp_reply { + TYPEC_TBT_UFP_REPLY_NAK, + TYPEC_TBT_UFP_REPLY_ACK, +}; + +#define TYPEC_USB_MUX_SET_ALL_CHIPS 0xFF + +struct typec_usb_mux_set { + /* Index of the mux to set in the chain */ + uint8_t mux_index; + + /* USB_PD_MUX_*-encoded USB mux state to set */ + uint8_t mux_flags; +} __ec_align1; + +struct typec_vdm_req { + /* VDM data, including VDM header */ + uint32_t vdm_data[VDO_MAX_SIZE]; + /* Number of 32-bit fields filled in */ + uint8_t vdm_data_objects; + /* Partner to address - see enum typec_partner_type */ + uint8_t partner_type; +} __ec_align1; + +struct ec_params_typec_control { + uint8_t port; + uint8_t command; /* enum typec_control_command */ + uint16_t reserved; + + /* + * This section will be interpreted based on |command|. Define a + * placeholder structure to avoid having to increase the size and bump + * the command version when adding new sub-commands. + */ + union { + /* Used for CLEAR_EVENTS */ + uint32_t clear_events_mask; + /* Used for ENTER_MODE - enum typec_mode */ + uint8_t mode_to_enter; + /* Used for TBT_UFP_REPLY - enum typec_tbt_ufp_reply */ + uint8_t tbt_ufp_reply; + /* Used for USB_MUX_SET */ + struct typec_usb_mux_set mux_params; + /* Used for BIST_SHARE_MODE */ + uint8_t bist_share_mode; + /* Used for VMD_REQ */ + struct typec_vdm_req vdm_req_params; + uint8_t placeholder[128]; + }; +} __ec_align1; + /* - * Flags to control read operation + * Gather all status information for a port. * - * RELOAD: Invalidate cache and read data from EEPROM. Useful to verify - * write was successful without reboot. + * Note: this covers many of the return fields from the deprecated + * EC_CMD_USB_PD_CONTROL command, except those that are redundant with the + * discovery data. The "enum pd_cc_states" is defined with the deprecated + * EC_CMD_USB_PD_CONTROL command. + * + * This also combines in the EC_CMD_USB_PD_MUX_INFO flags. + */ +#define EC_CMD_TYPEC_STATUS 0x0133 + +/* + * Power role. + * + * Note this is also used for PD header creation, and values align to those in + * the Power Delivery Specification Revision 3.0 (See + * 6.2.1.1.4 Port Power Role). + */ +enum pd_power_role { + PD_ROLE_SINK = 0, + PD_ROLE_SOURCE = 1, +}; + +/* + * Data role. + * + * Note this is also used for PD header creation, and the first two values + * align to those in the Power Delivery Specification Revision 3.0 (See + * 6.2.1.1.6 Port Data Role). + */ +enum pd_data_role { + PD_ROLE_UFP = 0, + PD_ROLE_DFP = 1, + PD_ROLE_DISCONNECTED = 2, +}; + +enum pd_vconn_role { + PD_ROLE_VCONN_OFF = 0, + PD_ROLE_VCONN_SRC = 1, +}; + +/* + * Note: BIT(0) may be used to determine whether the polarity is CC1 or CC2, + * regardless of whether a debug accessory is connected. + */ +enum tcpc_cc_polarity { + /* + * _CCx: is used to indicate the polarity while not connected to + * a Debug Accessory. Only one CC line will assert a resistor and + * the other will be open. + */ + POLARITY_CC1 = 0, + POLARITY_CC2 = 1, + + /* + * _CCx_DTS is used to indicate the polarity while connected to a + * SRC Debug Accessory. Assert resistors on both lines. + */ + POLARITY_CC1_DTS = 2, + POLARITY_CC2_DTS = 3, + + /* + * The current TCPC code relies on these specific POLARITY values. + * Adding in a check to verify if the list grows for any reason + * that this will give a hint that other places need to be + * adjusted. + */ + POLARITY_COUNT, +}; + +#define MODE_DP_PIN_A BIT(0) +#define MODE_DP_PIN_B BIT(1) +#define MODE_DP_PIN_C BIT(2) +#define MODE_DP_PIN_D BIT(3) +#define MODE_DP_PIN_E BIT(4) +#define MODE_DP_PIN_F BIT(5) +#define MODE_DP_PIN_ALL GENMASK(5, 0) + +#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) +#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) +#define PD_STATUS_EVENT_HARD_RESET BIT(2) +#define PD_STATUS_EVENT_DISCONNECTED BIT(3) +#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4) +#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5) +#define PD_STATUS_EVENT_VDM_REQ_REPLY BIT(6) +#define PD_STATUS_EVENT_VDM_REQ_FAILED BIT(7) +#define PD_STATUS_EVENT_VDM_ATTENTION BIT(8) +#define PD_STATUS_EVENT_COUNT 9 + +/* + * Encode and decode for BCD revision response + * + * Note: the major revision set is written assuming that the value given is the + * Specification Revision from the PD header, which currently only maps to PD + * 1.0-3.0 with the major revision being one greater than the binary value. + */ +#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12) +#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF) +#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF) + +/* + * Encode revision from partner RMDO + * + * Unlike the specification revision given in the PD header, specification and + * version information returned in the revision message data object (RMDO) is + * not offset. + */ +#define PD_STATUS_RMDO_REV_SET_MAJOR(r) (r << 12) +#define PD_STATUS_RMDO_REV_SET_MINOR(r) (r << 8) +#define PD_STATUS_RMDO_VER_SET_MAJOR(r) (r << 4) +#define PD_STATUS_RMDO_VER_SET_MINOR(r) (r) + +/* + * Decode helpers for Source and Sink Capability PDOs + * + * Note: The Power Delivery Specification should be considered the ultimate + * source of truth on the decoding of these PDOs + */ +#define PDO_TYPE_FIXED (0 << 30) +#define PDO_TYPE_BATTERY (1 << 30) +#define PDO_TYPE_VARIABLE (2 << 30) +#define PDO_TYPE_AUGMENTED (3 << 30) +#define PDO_TYPE_MASK (3 << 30) + +/* + * From Table 6-9 and Table 6-14 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Fixed Supply + * <29> : Dual-Role Power + * <28> : SNK/SRC dependent + * <27> : Unconstrained Power + * <26> : USB Communications Capable + * <25> : Dual-Role Data + * <24:20> : SNK/SRC dependent + * <19:10> : Voltage in 50mV Units + * <9:0> : Maximum Current in 10mA units + */ +#define PDO_FIXED_DUAL_ROLE BIT(29) +#define PDO_FIXED_UNCONSTRAINED BIT(27) +#define PDO_FIXED_COMM_CAP BIT(26) +#define PDO_FIXED_DATA_SWAP BIT(25) +#define PDO_FIXED_FRS_CURR_MASK GENMASK(24, 23) /* Sink Cap only */ +#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10) + +/* + * From Table 6-12 and Table 6-16 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Battery + * <29:20> : Maximum Voltage in 50mV units + * <19:10> : Minimum Voltage in 50mV units + * <9:0> : Maximum Allowable Power in 250mW units + */ +#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250) + +/* + * From Table 6-11 and Table 6-15 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Variable Supply (non-Battery) + * <29:20> : Maximum Voltage in 50mV units + * <19:10> : Minimum Voltage in 50mV units + * <9:0> : Operational Current in 10mA units + */ +#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10) + +/* + * From Table 6-13 and Table 6-17 PD Rev 3.0 Ver 2.0 + * + * Note this type is reserved in PD 2.0, and only one type of APDO is + * supported as of the cited version. + * + * <31:30> : Augmented Power Data Object + * <29:28> : Programmable Power Supply + * <27> : PPS Power Limited + * <26:25> : Reserved + * <24:17> : Maximum Voltage in 100mV increments + * <16> : Reserved + * <15:8> : Minimum Voltage in 100mV increments + * <7> : Reserved + * <6:0> : Maximum Current in 50mA increments + */ +#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100) +#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100) +#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50) + +struct ec_params_typec_status { + uint8_t port; +} __ec_align1; + +/* + * ec_response_typec_status is deprecated. Use ec_response_typec_status_v1. + * If you need to support old ECs who speak only v0, use + * ec_response_typec_status_v0 instead. They're binary-compatible. + */ +struct ec_response_typec_status /* DEPRECATED */ { + uint8_t pd_enabled; /* PD communication enabled - bool */ + uint8_t dev_connected; /* Device connected - bool */ + uint8_t sop_connected; /* Device is SOP PD capable - bool */ + uint8_t source_cap_count; /* Number of Source Cap PDOs */ + + uint8_t power_role; /* enum pd_power_role */ + uint8_t data_role; /* enum pd_data_role */ + uint8_t vconn_role; /* enum pd_vconn_role */ + uint8_t sink_cap_count; /* Number of Sink Cap PDOs */ + + uint8_t polarity; /* enum tcpc_cc_polarity */ + uint8_t cc_state; /* enum pd_cc_states */ + uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ + uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */ + + char tc_state[32]; /* TC state name */ + + uint32_t events; /* PD_STATUS_EVENT bitmask */ + + /* + * BCD PD revisions for partners + * + * The format has the PD major revision in the upper nibble, and the PD + * minor revision in the next nibble. The following two nibbles hold the + * major and minor specification version. If a partner does not support + * the Revision message, only the major revision will be given. + * ex. PD Revision 3.2 Version 1.9 would map to 0x3219 + * + * PD revision/version will be 0 if no PD device is connected. + */ + uint16_t sop_revision; + uint16_t sop_prime_revision; + + uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */ + + uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */ +} __ec_align1; + +struct cros_ec_typec_status { + uint8_t pd_enabled; /* PD communication enabled - bool */ + uint8_t dev_connected; /* Device connected - bool */ + uint8_t sop_connected; /* Device is SOP PD capable - bool */ + uint8_t source_cap_count; /* Number of Source Cap PDOs */ + + uint8_t power_role; /* enum pd_power_role */ + uint8_t data_role; /* enum pd_data_role */ + uint8_t vconn_role; /* enum pd_vconn_role */ + uint8_t sink_cap_count; /* Number of Sink Cap PDOs */ + + uint8_t polarity; /* enum tcpc_cc_polarity */ + uint8_t cc_state; /* enum pd_cc_states */ + uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ + uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */ + + char tc_state[32]; /* TC state name */ + + uint32_t events; /* PD_STATUS_EVENT bitmask */ + + /* + * BCD PD revisions for partners + * + * The format has the PD major revision in the upper nibble, and the PD + * minor revision in the next nibble. The following two nibbles hold the + * major and minor specification version. If a partner does not support + * the Revision message, only the major revision will be given. + * ex. PD Revision 3.2 Version 1.9 would map to 0x3219 + * + * PD revision/version will be 0 if no PD device is connected. + */ + uint16_t sop_revision; + uint16_t sop_prime_revision; +} __ec_align1; + +struct ec_response_typec_status_v0 { + struct cros_ec_typec_status typec_status; + uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */ + uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */ +} __ec_align1; + +struct ec_response_typec_status_v1 { + struct cros_ec_typec_status typec_status; + uint32_t source_cap_pdos[11]; /* Max 11 PDOs can be present */ + uint32_t sink_cap_pdos[11]; /* Max 11 PDOs can be present */ +} __ec_align1; + +/** + * Get the number of peripheral charge ports + */ +#define EC_CMD_PCHG_COUNT 0x0134 + +#define EC_PCHG_MAX_PORTS 8 + +struct ec_response_pchg_count { + uint8_t port_count; +} __ec_align1; + +/** + * Get the status of a peripheral charge port + */ +#define EC_CMD_PCHG 0x0135 + +/* For v1 and v2 */ +struct ec_params_pchg { + uint8_t port; +} __ec_align1; + +struct ec_params_pchg_v3 { + uint8_t port; + /* Below are new in v3. */ + uint8_t reserved1; + uint8_t reserved2; + uint8_t reserved3; + /* Errors acked by the host (thus to be cleared) */ + uint32_t error; +} __ec_align1; + +/* For v1 */ +struct ec_response_pchg { + uint32_t error; /* enum pchg_error */ + uint8_t state; /* enum pchg_state state */ + uint8_t battery_percentage; + uint8_t unused0; + uint8_t unused1; + /* Fields added in version 1 */ + uint32_t fw_version; + uint32_t dropped_event_count; +} __ec_align4; + +/* For v2 and v3 */ +struct ec_response_pchg_v2 { + uint32_t error; /* enum pchg_error */ + uint8_t state; /* enum pchg_state state */ + uint8_t battery_percentage; + uint8_t unused0; + uint8_t unused1; + /* Fields added in version 1 */ + uint32_t fw_version; + uint32_t dropped_event_count; + /* Fields added in version 2 */ + uint32_t dropped_host_event_count; +} __ec_align4; + +enum pchg_state { + /* Charger is reset and not initialized. */ + PCHG_STATE_RESET = 0, + /* Charger is initialized or disabled. */ + PCHG_STATE_INITIALIZED, + /* Charger is enabled and ready to detect a device. */ + PCHG_STATE_ENABLED, + /* Device is in proximity. */ + PCHG_STATE_DETECTED, + /* Device is being charged. */ + PCHG_STATE_CHARGING, + /* Device is fully charged. It implies DETECTED (& not charging). */ + PCHG_STATE_FULL, + /* In download (a.k.a. firmware update) mode */ + PCHG_STATE_DOWNLOAD, + /* In download mode. Ready for receiving data. */ + PCHG_STATE_DOWNLOADING, + /* Device is ready for data communication. */ + PCHG_STATE_CONNECTED, + /* Charger is in Built-In Self Test mode. */ + PCHG_STATE_BIST, + /* Put no more entry below */ + PCHG_STATE_COUNT, +}; + +/* clang-format off */ +#define EC_PCHG_STATE_TEXT \ + { \ + [PCHG_STATE_RESET] = "RESET", \ + [PCHG_STATE_INITIALIZED] = "INITIALIZED", \ + [PCHG_STATE_ENABLED] = "ENABLED", \ + [PCHG_STATE_DETECTED] = "DETECTED", \ + [PCHG_STATE_CHARGING] = "CHARGING", \ + [PCHG_STATE_FULL] = "FULL", \ + [PCHG_STATE_DOWNLOAD] = "DOWNLOAD", \ + [PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \ + [PCHG_STATE_CONNECTED] = "CONNECTED", \ + [PCHG_STATE_BIST] = "BIST", \ + } +/* clang-format on */ + +/** + * Update firmware of peripheral chip + */ +#define EC_CMD_PCHG_UPDATE 0x0136 + +/* Port number is encoded in bit[28:31]. */ +#define EC_MKBP_PCHG_PORT_SHIFT 28 +/* Utility macros for converting MKBP event <-> port number. */ +#define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf) +#define EC_MKBP_PCHG_PORT_TO_EVENT(p) ((p) << EC_MKBP_PCHG_PORT_SHIFT) +/* Utility macro for extracting event bits. */ +#define EC_MKBP_PCHG_EVENT_MASK(e) \ + ((e) & GENMASK(EC_MKBP_PCHG_PORT_SHIFT - 1, 0)) + +#define EC_MKBP_PCHG_UPDATE_OPENED BIT(0) +#define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1) +#define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2) +#define EC_MKBP_PCHG_UPDATE_ERROR BIT(3) +#define EC_MKBP_PCHG_DEVICE_EVENT BIT(4) + +enum ec_pchg_update_cmd { + /* Reset chip to normal mode. */ + EC_PCHG_UPDATE_CMD_RESET_TO_NORMAL = 0, + /* Reset and put a chip in update (a.k.a. download) mode. */ + EC_PCHG_UPDATE_CMD_OPEN, + /* Write a block of data containing FW image. */ + EC_PCHG_UPDATE_CMD_WRITE, + /* Close update session. */ + EC_PCHG_UPDATE_CMD_CLOSE, + /* Reset chip (without mode change). */ + EC_PCHG_UPDATE_CMD_RESET, + /* Enable pass-through mode. */ + EC_PCHG_UPDATE_CMD_ENABLE_PASSTHRU, + /* End of commands */ + EC_PCHG_UPDATE_CMD_COUNT, +}; + +struct ec_params_pchg_update { + /* PCHG port number */ + uint8_t port; + /* enum ec_pchg_update_cmd */ + uint8_t cmd; + /* Padding */ + uint8_t reserved0; + uint8_t reserved1; + /* Version of new firmware */ + uint32_t version; + /* CRC32 of new firmware */ + uint32_t crc32; + /* Address in chip memory where is written to */ + uint32_t addr; + /* Size of */ + uint32_t size; + /* Partial data of new firmware */ + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; + +BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT < + BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd) * 8)); + +struct ec_response_pchg_update { + /* Block size */ + uint32_t block_size; +} __ec_align4; + +#define EC_CMD_DISPLAY_SOC 0x0137 + +struct ec_response_display_soc { + /* Display charge in 10ths of a % (1000=100.0%) */ + int16_t display_soc; + /* Full factor in 10ths of a % (1000=100.0%) */ + int16_t full_factor; + /* Shutdown SoC in 10ths of a % (1000=100.0%) */ + int16_t shutdown_soc; +} __ec_align2; + +#define EC_CMD_SET_BASE_STATE 0x0138 + +struct ec_params_set_base_state { + uint8_t cmd; /* enum ec_set_base_state_cmd */ +} __ec_align1; + +enum ec_set_base_state_cmd { + EC_SET_BASE_STATE_DETACH = 0, + EC_SET_BASE_STATE_ATTACH, + EC_SET_BASE_STATE_RESET, +}; + +#define EC_CMD_I2C_CONTROL 0x0139 + +/* Subcommands for I2C control */ + +enum ec_i2c_control_command { + EC_I2C_CONTROL_GET_SPEED, + EC_I2C_CONTROL_SET_SPEED, +}; + +#define EC_I2C_CONTROL_SPEED_UNKNOWN 0 + +struct ec_params_i2c_control { + uint8_t port; /* I2C port number */ + uint8_t cmd; /* enum ec_i2c_control_command */ + union { + uint16_t speed_khz; + } cmd_params; +} __ec_align_size1; + +struct ec_response_i2c_control { + union { + uint16_t speed_khz; + } cmd_response; +} __ec_align_size1; + +#define EC_CMD_RGBKBD_SET_COLOR 0x013A +#define EC_CMD_RGBKBD 0x013B + +#define EC_RGBKBD_MAX_KEY_COUNT 128 +#define EC_RGBKBD_MAX_RGB_COLOR 0xFFFFFF +#define EC_RGBKBD_MAX_SCALE 0xFF + +enum rgbkbd_state { + /* RGB keyboard is reset and not initialized. */ + RGBKBD_STATE_RESET = 0, + /* RGB keyboard is initialized but not enabled. */ + RGBKBD_STATE_INITIALIZED, + /* RGB keyboard is disabled. */ + RGBKBD_STATE_DISABLED, + /* RGB keyboard is enabled and ready to receive a command. */ + RGBKBD_STATE_ENABLED, + + /* Put no more entry below */ + RGBKBD_STATE_COUNT, +}; + +enum ec_rgbkbd_subcmd { + EC_RGBKBD_SUBCMD_CLEAR = 1, + EC_RGBKBD_SUBCMD_DEMO = 2, + EC_RGBKBD_SUBCMD_SET_SCALE = 3, + EC_RGBKBD_SUBCMD_GET_CONFIG = 4, + EC_RGBKBD_SUBCMD_COUNT +}; + +enum ec_rgbkbd_demo { + EC_RGBKBD_DEMO_OFF = 0, + EC_RGBKBD_DEMO_FLOW = 1, + EC_RGBKBD_DEMO_DOT = 2, + EC_RGBKBD_DEMO_COUNT, +}; + +BUILD_ASSERT(EC_RGBKBD_DEMO_COUNT <= 255); + +enum ec_rgbkbd_type { + EC_RGBKBD_TYPE_UNKNOWN = 0, + EC_RGBKBD_TYPE_PER_KEY = 1, /* e.g. Vell */ + EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS = 2, /* e.g. Taniks */ + EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS = 3, /* e.g. Osiris */ + EC_RGBKBD_TYPE_FOUR_ZONES_4_LEDS = 4, /* e.g. Mithrax */ + EC_RGBKBD_TYPE_COUNT, +}; + +struct ec_rgbkbd_set_scale { + uint8_t key; + struct rgb_s scale; +}; + +struct ec_params_rgbkbd { + uint8_t subcmd; /* Sub-command (enum ec_rgbkbd_subcmd) */ + union { + struct rgb_s color; /* EC_RGBKBD_SUBCMD_CLEAR */ + uint8_t demo; /* EC_RGBKBD_SUBCMD_DEMO */ + struct ec_rgbkbd_set_scale set_scale; + }; +} __ec_align1; + +struct ec_response_rgbkbd { + /* + * RGBKBD type supported by the device. + */ + + uint8_t rgbkbd_type; /* enum ec_rgbkbd_type */ +} __ec_align1; + +struct ec_params_rgbkbd_set_color { + /* Specifies the starting key ID whose color is being changed. */ + uint8_t start_key; + /* Specifies # of elements in . */ + uint8_t length; + /* RGB color data array of length up to MAX_KEY_COUNT. */ + struct rgb_s color[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align1; + +/* + * Gather the response to the most recent VDM REQ from the AP, as well + * as popping the oldest VDM:Attention from the DPM queue + */ +#define EC_CMD_TYPEC_VDM_RESPONSE 0x013C + +struct ec_params_typec_vdm_response { + uint8_t port; +} __ec_align1; + +struct ec_response_typec_vdm_response { + /* Number of 32-bit fields filled in */ + uint8_t vdm_data_objects; + /* Partner to address - see enum typec_partner_type */ + uint8_t partner_type; + /* enum ec_status describing VDM response */ + uint16_t vdm_response_err; + /* VDM data, including VDM header */ + uint32_t vdm_response[VDO_MAX_SIZE]; + /* Number of 32-bit Attention fields filled in */ + uint8_t vdm_attention_objects; + /* Number of remaining messages to consume */ + uint8_t vdm_attention_left; + /* Reserved */ + uint16_t reserved1; + /* VDM:Attention contents */ + uint32_t vdm_attention[2]; +} __ec_align1; + +/* + * Get an active battery config from the EC. + */ +#define EC_CMD_BATTERY_CONFIG 0x013D + +/* Version of struct batt_conf_header and its internals. */ +#define EC_BATTERY_CONFIG_STRUCT_VERSION 0x00 + +/* Number of writes needed to invoke battery cutoff command */ +#define SHIP_MODE_WRITES 2 + +struct ship_mode_info { + uint8_t reg_addr; + uint8_t reserved; + uint16_t reg_data[SHIP_MODE_WRITES]; +} __packed __aligned(2); + +struct sleep_mode_info { + uint8_t reg_addr; + uint8_t reserved; + uint16_t reg_data; +} __packed __aligned(2); + +struct fet_info { + uint8_t reg_addr; + uint8_t reserved; + uint16_t reg_mask; + uint16_t disconnect_val; + uint16_t cfet_mask; /* CHG FET status mask */ + uint16_t cfet_off_val; +} __packed __aligned(2); + +enum fuel_gauge_flags { + /* + * Write Block Support. If enabled, we use a i2c write block command + * instead of a 16-bit write. The effective difference is the i2c + * transaction will prefix the length (2). + */ + FUEL_GAUGE_FLAG_WRITE_BLOCK = BIT(0), + /* Sleep command support. fuel_gauge_info.sleep_mode must be defined. */ + FUEL_GAUGE_FLAG_SLEEP_MODE = BIT(1), + /* + * Manufacturer access command support. If enabled, FET status is read + * from the OperationStatus (0x54) register using the + * ManufacturerBlockAccess (0x44). + */ + FUEL_GAUGE_FLAG_MFGACC = BIT(2), + /* + * SMB block protocol support in manufacturer access command. If + * enabled, FET status is read from the OperationStatus (0x54) register + * using the ManufacturerBlockAccess (0x44). + */ + FUEL_GAUGE_FLAG_MFGACC_SMB_BLOCK = BIT(3), +}; + +struct fuel_gauge_info { + uint32_t flags; + uint32_t board_flags; + struct ship_mode_info ship_mode; + struct sleep_mode_info sleep_mode; + struct fet_info fet; +} __packed __aligned(4); + +/* Battery constants */ +struct battery_info { + /* Operation voltage in mV */ + uint16_t voltage_max; + uint16_t voltage_normal; + uint16_t voltage_min; + /* (TODO(chromium:756700): add desired_charging_current */ + /** + * Pre-charge to fast charge threshold in mV, + * default to voltage_min if not specified. + * This option is only available on isl923x and rt946x. + */ + uint16_t precharge_voltage; + /* Pre-charge current in mA */ + uint16_t precharge_current; + /* Working temperature ranges in degrees C */ + int8_t start_charging_min_c; + int8_t start_charging_max_c; + int8_t charging_min_c; + int8_t charging_max_c; + int8_t discharging_min_c; + int8_t discharging_max_c; + /* Used only if CONFIG_BATTERY_VENDOR_PARAM is defined. */ + uint8_t vendor_param_start; + uint8_t reserved; +} __packed __aligned(2); + +/* + * The 'config' of a battery. + */ +struct board_batt_params { + struct fuel_gauge_info fuel_gauge; + struct battery_info batt_info; +} __packed __aligned(4); + +/* + * The SBS defines a string object as a block of chars, 32 byte maximum, where + * the first byte indicates the number of chars in the block (excluding the + * first byte). + * + * Thus, the actual string length (i.e. the value strlen returns) is limited to + * 31 (=SBS_MAX_STR_SIZE). + * + * SBS_MAX_STR_OBJ_SIZE can be used as the size of a buffer for an SBS string + * object but also as a buffer for a c-lang string because the null terminating + * char also takes one byte. + */ +#define SBS_MAX_STR_SIZE 31 +#define SBS_MAX_STR_OBJ_SIZE (SBS_MAX_STR_SIZE + 1) + +/* + * Header describing a battery config stored in CBI. Only struct_version has + * size and position independent of struct_version. The rest varies as + * struct_version changes. + * + * Version 0 + * Layout: + * +-------------+ + * | header | + * +-------------+ + * | | ^ + * | manuf_name | | manuf_name_size + * | | v + * +-------------+ + * | device_name | ^ + * | | | device_name_size + * | | v + * +-------------+ + * | config | ^ + * | | | + * | | | cbi data size + * | | | - (header_size+manuf_name_size+device_name_size) + * | | | + * | | v + * +-------------+ + * Note: + * - manuf_name and device_name are not null-terminated. + * - The config isn't aligned. It should be copied to struct board_batt_params + * before its contents are accessed. + */ +struct batt_conf_header { + /* Version independent field. It's always here as a uint8_t. */ + uint8_t struct_version; + /* Version 0 members */ + uint8_t manuf_name_size; + uint8_t device_name_size; + uint8_t reserved; + /* manuf_name, device_name, board_batt_params follow after this. */ +} __packed; + +#define BATT_CONF_MAX_SIZE \ + (sizeof(struct batt_conf_header) + SBS_MAX_STR_OBJ_SIZE * 2 + \ + sizeof(struct board_batt_params)) + +/* + * Record the current AP firmware state. This is used to help testing, such as + * with FAFT (Fully-Automated Firmware Test), which likes to know which firmware + * screen is currently displayed. + */ + +#define EC_CMD_AP_FW_STATE 0x013E + +struct ec_params_ap_fw_state { + /* + * Value which indicates the state. This is not decoded by the EC, so + * its meaning is entirely outside this code base. + */ + uint32_t state; +} __ec_align1; + +/* + * UCSI OPM-PPM commands + * + * These commands are used for communication between OPM and PPM. + * Only UCSI3.0 is tested. + */ + +#define EC_CMD_UCSI_PPM_SET 0x0140 + +/* The data size is stored in the host command protocol header. */ +struct ec_params_ucsi_ppm_set { + uint16_t offset; + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align2; + +#define EC_CMD_UCSI_PPM_GET 0x0141 + +/* For 'GET' sub-commands, data will be returned as a raw payload. */ +struct ec_params_ucsi_ppm_get { + uint16_t offset; + uint8_t size; +} __ec_align2; + +#define EC_CMD_SET_ALARM_SLP_S0_DBG 0x0142 + +/* RTC params and response structures */ +struct ec_params_set_alarm_slp_s0_dbg { + uint32_t time; +} __ec_align2; + +/* + * Control PDC tracing. + * EC_PDC_TRACE_MSG_PORT_NONE disable tracing + * EC_PDC_TRACE_MSG_PORT_ALL enable tracing on all ports + * else, enable tracing on a specific port. */ -#define CBI_GET_RELOAD (1 << 0) -struct __ec_align4 ec_params_get_cbi { - uint32_t type; /* enum cbi_data_tag */ - uint32_t flag; /* CBI_GET_* */ +#define EC_CMD_PDC_TRACE_MSG_ENABLE 0x0143 + +#define EC_PDC_TRACE_MSG_PORT_NONE 0xff +#define EC_PDC_TRACE_MSG_PORT_ALL 0xfe + +struct ec_params_pdc_trace_msg_enable { + uint8_t port; }; +struct ec_response_pdc_trace_msg_enable { + /* Previous port value. */ + uint8_t port; + uint8_t reserved; + /* Number of free bytes in FIFO. */ + uint16_t fifo_free; + /* Running total of dropped messages (may wrap). */ + uint32_t dropped_count; +} __ec_align4; + /* - * Flags to control write behavior. + * Fetch multiple PDC trace entries. * - * NO_SYNC: Makes EC update data in RAM but skip writing to EEPROM. It's - * useful when writing multiple fields in a row. - * INIT: Needs to be set when creating a new CBI from scratch. All fields - * will be initialized to zero first. + * If no entries are available, pl_size is 0. + * At most MAX_HC_PDC_TRACE_MSG_GET_PAYLOAD bytes worth of entries + * are returned. Only whole entries are returned. */ -#define CBI_SET_NO_SYNC (1 << 0) -#define CBI_SET_INIT (1 << 1) -struct __ec_align1 ec_params_set_cbi { - uint32_t tag; /* enum cbi_data_tag */ - uint32_t flag; /* CBI_SET_* */ - uint32_t size; /* Data size */ - uint8_t data[]; /* For string and raw data */ +#define EC_CMD_PDC_TRACE_MSG_GET_ENTRIES 0x0144 +#define MAX_HC_PDC_TRACE_MSG_GET_PAYLOAD 240 + +struct ec_response_pdc_trace_msg_get_entries { + /* Total bytes of payload. */ + uint16_t pl_size; + /* Packed array of pdc_trace_msg_entry structs. */ + uint8_t payload[FLEXIBLE_ARRAY_MEMBER_SIZE]; +}; + +enum pdc_trace_msg_direction { + PDC_TRACE_MSG_DIR_IN = 0, + PDC_TRACE_MSG_DIR_OUT = 1, }; +struct pdc_trace_msg_entry { + /* + * Timestamp - least significant 32 bits of EC epoch time + * (microseconds, will wrap around). + */ + uint32_t time32_us; + /* Entry sequence number (wraps around). */ + uint16_t seq_num; + /* Port number associated with this entry. */ + uint8_t port_num; + /* Direction of message (enum pdc_trace_msg_direction) */ + uint8_t direction; + /* Format of pdc_data (PDC chip identifier). */ + uint8_t msg_type; + /* Bytes in pdc_data. */ + uint8_t pdc_data_size; + /* Captured PDC message. */ + uint8_t pdc_data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align1; + +/* Enable/disable Ethernet POE power */ +#define EC_CMD_SWITCH_ENABLE_POE 0x0145 + +struct ec_params_switch_enable_poe { + uint8_t enabled; +} __ec_align1; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ @@ -4449,61 +8422,151 @@ struct __ec_align1 ec_params_set_cbi { /*****************************************************************************/ /* Fingerprint MCU commands: range 0x0400-0x040x */ -/* Fingerprint SPI sensor passthru command: prototyping ONLY */ +/* + * Fingerprint SPI sensor passthru command + * + * This command was used for prototyping and it's now deprecated. + */ #define EC_CMD_FP_PASSTHRU 0x0400 #define EC_FP_FLAG_NOT_COMPLETE 0x1 -struct __ec_align2 ec_params_fp_passthru { - uint16_t len; /* Number of bytes to write then read */ - uint16_t flags; /* EC_FP_FLAG_xxx */ - uint8_t data[]; /* Data to send */ -}; - -/* Fingerprint sensor configuration command: prototyping ONLY */ -#define EC_CMD_FP_SENSOR_CONFIG 0x0401 - -#define EC_FP_SENSOR_CONFIG_MAX_REGS 16 - -struct __ec_align2 ec_params_fp_sensor_config { - uint8_t count; /* Number of setup registers */ - /* - * the value to send to each of the 'count' setup registers - * is stored in the 'data' array for 'len' bytes just after - * the previous one. - */ - uint8_t len[EC_FP_SENSOR_CONFIG_MAX_REGS]; - uint8_t data[]; -}; +struct ec_params_fp_passthru { + uint16_t len; /* Number of bytes to write then read */ + uint16_t flags; /* EC_FP_FLAG_xxx */ + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; /* Data to send */ +} __ec_align2; /* Configure the Fingerprint MCU behavior */ #define EC_CMD_FP_MODE 0x0402 /* Put the sensor in its lowest power mode */ -#define FP_MODE_DEEPSLEEP (1<<0) +#define FP_MODE_DEEPSLEEP BIT(0) /* Wait to see a finger on the sensor */ -#define FP_MODE_FINGER_DOWN (1<<1) +#define FP_MODE_FINGER_DOWN BIT(1) /* Poll until the finger has left the sensor */ -#define FP_MODE_FINGER_UP (1<<2) +#define FP_MODE_FINGER_UP BIT(2) /* Capture the current finger image */ -#define FP_MODE_CAPTURE (1<<3) +#define FP_MODE_CAPTURE BIT(3) +/* Finger enrollment session on-going */ +#define FP_MODE_ENROLL_SESSION BIT(4) +/* Enroll the current finger image */ +#define FP_MODE_ENROLL_IMAGE BIT(5) +/* Try to match the current finger image */ +#define FP_MODE_MATCH BIT(6) +/* Reset and re-initialize the sensor. */ +#define FP_MODE_RESET_SENSOR BIT(7) +/* Sensor maintenance for dead pixels. */ +#define FP_MODE_SENSOR_MAINTENANCE BIT(8) +/* Encrypt template. */ +#define FP_MODE_ENCRYPT_TEMPLATE BIT(9) +/* Decrypt template. */ +#define FP_MODE_DECRYPT_TEMPLATE BIT(10) +/* Disable template update. */ +#define FP_MODE_MATCH_NO_TEMPLATE_UPDATE BIT(11) /* special value: don't change anything just read back current mode */ -#define FP_MODE_DONT_CHANGE (1<<31) +#define FP_MODE_DONT_CHANGE BIT(31) + +#define FP_VALID_MODES \ + (FP_MODE_DEEPSLEEP | FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | \ + FP_MODE_CAPTURE | FP_MODE_ENROLL_SESSION | FP_MODE_ENROLL_IMAGE | \ + FP_MODE_MATCH | FP_MODE_RESET_SENSOR | FP_MODE_SENSOR_MAINTENANCE | \ + FP_MODE_ENCRYPT_TEMPLATE | FP_MODE_DECRYPT_TEMPLATE | \ + FP_MODE_MATCH_NO_TEMPLATE_UPDATE | FP_MODE_DONT_CHANGE) + +#define FP_MODES_WITH_AUTHENTICATION (FP_MODE_ENROLL_SESSION | FP_MODE_MATCH) +#define FP_MODES_CRYPTO_IN_PROGRESS \ + (FP_MODE_ENCRYPT_TEMPLATE | FP_MODE_DECRYPT_TEMPLATE) +#define FP_MODES_TEMPLATE_OPERATION \ + (FP_MODE_ENROLL_SESSION | FP_MODE_ENROLL_IMAGE | FP_MODE_MATCH | \ + FP_MODE_RESET_SENSOR | FP_MODE_ENCRYPT_TEMPLATE | \ + FP_MODE_DECRYPT_TEMPLATE) + +/* Capture types defined in bits [30..26] */ +#define FP_MODE_CAPTURE_TYPE_SHIFT 26 +#define FP_MODE_CAPTURE_TYPE_MASK (0x1F << FP_MODE_CAPTURE_TYPE_SHIFT) +/** + * enum fp_capture_type - Specifies the "mode" when capturing images. + * + * @FP_CAPTURE_TYPE_INVALID: an invalid capture type + * @FP_CAPTURE_VENDOR_FORMAT: Capture 1-3 images and choose the best quality + * image (produces 'frame_size' bytes) + * @FP_CAPTURE_SIMPLE_IMAGE: Simple raw image capture (produces width x height x + * bpp bits) + * @FP_CAPTURE_DEFECT_PXL_TEST: Capture for check defect pixel test + * @FP_CAPTURE_ABNORMAL_TEST: Capture for check abnormal pixel test + * @FP_CAPTURE_NOISE_TEST: Capture for check noise test + * @FP_CAPTURE_PATTERN0: Self test pattern (e.g. checkerboard) + * @FP_CAPTURE_PATTERN1: Self test pattern (e.g. inverted checkerboard) + * @FP_CAPTURE_QUALITY_TEST: Capture for Quality test with fixed contrast + * @FP_CAPTURE_RESET_TEST: Capture for pixel reset value test + * @FP_CAPTURE_TYPE_MAX: End of enum + * + * @note This enum must remain ordered, if you add new values you must ensure + * that FP_CAPTURE_TYPE_MAX is still the last one. + */ +/* LINT.IfChange */ +enum fp_capture_type { + FP_CAPTURE_TYPE_INVALID = -1, + FP_CAPTURE_VENDOR_FORMAT = 0, + FP_CAPTURE_DEFECT_PXL_TEST = 1, + FP_CAPTURE_ABNORMAL_TEST = 2, + FP_CAPTURE_NOISE_TEST = 3, + FP_CAPTURE_SIMPLE_IMAGE = 4, + FP_CAPTURE_PATTERN0 = 8, + FP_CAPTURE_PATTERN1 = 12, + FP_CAPTURE_QUALITY_TEST = 16, + FP_CAPTURE_RESET_TEST = 20, + FP_CAPTURE_TYPE_MAX, +}; +/* LINT.ThenChange(/test/fpsensor_utils.cc, + * /zephyr/test/fingerprint/task/src/fpsensor_debug.cc) + */ + +/* The maximum number of capture types in enum fp_capture_type */ +#define FP_MAX_CAPTURE_TYPES 9 -struct __ec_align4 ec_params_fp_mode { +/* Extracts the capture type from the sensor 'mode' word */ +#define FP_CAPTURE_TYPE(mode) \ + (enum fp_capture_type)(((mode) & FP_MODE_CAPTURE_TYPE_MASK) >> \ + FP_MODE_CAPTURE_TYPE_SHIFT) + +#define FP_MAC_LENGTH 32 + +struct ec_params_fp_mode { uint32_t mode; /* as defined by FP_MODE_ constants */ - /* TBD */ -}; +} __ec_align4; -struct __ec_align4 ec_response_fp_mode { +struct ec_params_fp_mode_v1 { uint32_t mode; /* as defined by FP_MODE_ constants */ - /* TBD */ -}; + uint8_t mac[FP_MAC_LENGTH]; +} __ec_align4; + +struct ec_response_fp_mode { + uint32_t mode; /* as defined by FP_MODE_ constants */ +} __ec_align4; /* Retrieve Fingerprint sensor information */ #define EC_CMD_FP_INFO 0x0403 -struct __ec_align2 ec_response_fp_info { +/* Mask for dead pixels */ +#define FP_ERROR_DEAD_PIXELS_MASK 0x3FF +/* Maximum number of dead pixels */ +#define FP_ERROR_DEAD_PIXELS_MAX (FP_ERROR_DEAD_PIXELS_MASK - 1) +/* Number of dead pixels detected on the last maintenance */ +#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & FP_ERROR_DEAD_PIXELS_MASK) +/* Unknown number of dead pixels detected on the last maintenance */ +#define FP_ERROR_DEAD_PIXELS_UNKNOWN (FP_ERROR_DEAD_PIXELS_MASK) +/* No interrupt from the sensor */ +#define FP_ERROR_NO_IRQ BIT(12) +/* SPI communication error */ +#define FP_ERROR_SPI_COMM BIT(13) +/* Invalid sensor Hardware ID */ +#define FP_ERROR_BAD_HWID BIT(14) +/* Sensor initialization failed */ +#define FP_ERROR_INIT_FAIL BIT(15) + +struct ec_response_fp_info_v0 { /* Sensor identification */ uint32_t vendor_id; uint32_t product_id; @@ -4515,16 +8578,449 @@ struct __ec_align2 ec_response_fp_info { uint16_t width; uint16_t height; uint16_t bpp; -}; + uint16_t errors; /* see FP_ERROR_ flags above */ +} __ec_align4; + +struct ec_response_fp_info { + /* Sensor identification */ + uint32_t vendor_id; + uint32_t product_id; + uint32_t model_id; + uint32_t version; + /* Image frame characteristics */ + uint32_t frame_size; + uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ + uint16_t width; + uint16_t height; + uint16_t bpp; + uint16_t errors; /* see FP_ERROR_ flags above */ + /* Template/finger current information */ + uint32_t template_size; /* max template size in bytes */ + uint16_t template_max; /* maximum number of fingers/templates */ + uint16_t template_valid; /* number of valid fingers/templates */ + uint32_t template_dirty; /* bitmap of templates with MCU side changes */ + uint32_t template_version; /* version of the template format */ +} __ec_align4; + +struct fp_sensor_info { + /* Sensor identification */ + uint32_t vendor_id; + uint32_t product_id; + uint32_t model_id; + uint32_t version; + uint16_t num_capture_types; /* number of image capture types */ + uint16_t errors; /* see FP_ERROR_ flags above */ +} __ec_align4; +BUILD_ASSERT(sizeof(struct fp_sensor_info) == 20); + +struct fp_template_info { + /* Template/finger current information */ + uint32_t template_size; /* max template size in bytes */ + uint16_t template_max; /* maximum number of fingers/templates */ + uint16_t template_valid; /* number of valid fingers/templates */ + uint32_t template_dirty; /* bitmap of templates with MCU side changes */ + uint32_t template_version; /* version of the template format */ +} __ec_align4; +BUILD_ASSERT(sizeof(struct fp_template_info) == 16); + +struct fp_image_frame_params { + /* Image frame characteristics */ + uint32_t frame_size; + uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ + uint16_t width; + uint16_t height; + uint16_t bpp; + /** Type of image capture from enum fp_capture_type. */ + uint8_t fp_capture_type; + uint8_t reserved; /**< padding for alignment */ +} __ec_align4; +BUILD_ASSERT(sizeof(struct fp_image_frame_params) == 16); + +struct ec_response_fp_info_v2 { + /* Sensor identification */ + struct fp_sensor_info sensor_info; + /* Template/finger current information */ + struct fp_template_info template_info; + /* fingerprint image frame parameters */ + struct fp_image_frame_params + image_frame_params[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; +BUILD_ASSERT(sizeof(struct ec_response_fp_info_v2) == 36); + +struct fp_image_frame_params_v2 { + /* Image frame characteristics */ + uint32_t frame_size; + uint32_t image_data_offset_bytes; /**< Byte offset of image buffer */ + uint32_t pixel_format; /* using V4L2_PIX_FMT_ */ + uint16_t width; + uint16_t height; + uint16_t bpp; + /** Type of image capture from enum fp_capture_type. */ + uint8_t fp_capture_type; + uint8_t reserved; /**< padding for alignment */ +} __ec_align4; +BUILD_ASSERT(sizeof(struct fp_image_frame_params_v2) == 20); + +struct ec_response_fp_info_v3 { + /* Sensor identification */ + struct fp_sensor_info sensor_info; + /* Template/finger current information */ + struct fp_template_info template_info; + /* fingerprint image frame parameters */ + struct fp_image_frame_params_v2 + image_frame_params[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; +BUILD_ASSERT(sizeof(struct ec_response_fp_info_v3) == 36); -/* Get the last captured finger frame: TODO: will be AES-encrypted */ +/* Get the last captured finger frame or a template content */ #define EC_CMD_FP_FRAME 0x0404 -struct __ec_align4 ec_params_fp_frame { +/* constants defining the 'offset' field which also contains the frame index */ +#define FP_FRAME_INDEX_SHIFT 28 +/* Frame buffer where the captured image is stored */ +#define FP_FRAME_INDEX_RAW_IMAGE 0 +/* First frame buffer holding a template */ +#define FP_FRAME_INDEX_TEMPLATE 1 +#define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT) +#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF + +/* Version of the format of the encrypted templates. */ +#define FP_TEMPLATE_FORMAT_VERSION 4 + +/* Constants for encryption parameters */ +#define FP_CONTEXT_NONCE_BYTES 12 +#define FP_CONTEXT_USERID_BYTES 32 +#define FP_CONTEXT_USERID_WORDS (FP_CONTEXT_USERID_BYTES / sizeof(uint32_t)) +#define FP_CONTEXT_TAG_BYTES 16 +#define FP_CONTEXT_ENCRYPTION_SALT_BYTES 16 +#define FP_CONTEXT_TPM_BYTES 32 + +/* Constants for positive match parameters. */ +#define FP_POSITIVE_MATCH_SALT_BYTES 16 + +struct ec_fp_template_encryption_metadata { + /* + * Version of the structure format (N=3). + */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* + * The salt is *only* ever used for key derivation. The nonce is unique, + * a different one is used for every message. + */ + uint8_t nonce[FP_CONTEXT_NONCE_BYTES]; + uint8_t encryption_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES]; + uint8_t tag[FP_CONTEXT_TAG_BYTES]; +}; + +struct ec_params_fp_frame { + /* + * The offset contains the template index or FP_FRAME_INDEX_RAW_IMAGE + * in the high nibble, and the real offset within the frame in + * FP_FRAME_OFFSET_MASK. + */ + uint32_t offset; + uint32_t size; +} __ec_align4; + +/* + * FP_FRAME commands: + * + * - FP_FRAME_GET_RAW_IMAGE command can be used to get raw image from sensor. + * This command works only when the system is not locked. The template index + * is ignored. + * - FP_FRAME_ENCRYPT_TEMPLATE command is used to request encryption of the + * template with provided template index. Offset and size are ignored. + * The encryption process is considered as started only after EC_SUCCESS + * was returned. + * - FP_FRAME_GET_ENCRYPTED_TEMPLATE command is used to obtain the encrypted + * template. + */ +enum fp_frame_cmd { + FP_FRAME_GET_RAW_IMAGE = 0, + FP_FRAME_ENCRYPT_TEMPLATE = 1, + FP_FRAME_GET_ENCRYPTED_TEMPLATE = 2, +}; + +struct ec_params_fp_frame_v1 { + uint8_t cmd; + uint8_t reserved; + uint16_t index; + uint32_t offset; + uint32_t size; +} __ec_align4; + +/* Load a template into the MCU */ +#define EC_CMD_FP_TEMPLATE 0x0405 + +/* Flag in the 'size' field indicating that the full template has been sent */ +#define FP_TEMPLATE_COMMIT 0x80000000 + +struct ec_params_fp_template { + uint32_t offset; + uint32_t size; + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; + +/* + * FP_TEMPLATE commands: + * + * - FP_TEMPLATE_LOAD command is used to copy part of the template to FPMCU + * buffer. + * - FP_TEMPLATE_DECRYPT command starts template decryption. + * - FP_TEMPLATE_GET_RESULT command is used to check decryption result. + */ +enum fp_template_cmd { + FP_TEMPLATE_LOAD = 0, + FP_TEMPLATE_DECRYPT = 1, + FP_TEMPLATE_GET_RESULT = 2, +}; + +struct ec_params_fp_template_v1 { uint32_t offset; uint32_t size; + uint8_t cmd; + uint8_t data[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; + +/* Clear the current fingerprint user context and set a new one */ +#define EC_CMD_FP_CONTEXT 0x0406 + +struct ec_params_fp_context { + uint32_t userid[FP_CONTEXT_USERID_WORDS]; +} __ec_align4; + +enum fp_context_action { + FP_CONTEXT_ASYNC = 0, + FP_CONTEXT_GET_RESULT = 1, }; +/* Version 1 of the command is "asynchronous". */ +struct ec_params_fp_context_v1 { + uint8_t action; /**< enum fp_context_action */ + uint8_t reserved[3]; /**< padding for alignment */ + uint32_t userid[FP_CONTEXT_USERID_WORDS]; +} __ec_align4; + +#define EC_CMD_FP_STATS 0x0407 + +#define FPSTATS_CAPTURE_INV BIT(0) +#define FPSTATS_MATCHING_INV BIT(1) + +struct ec_response_fp_stats { + uint32_t capture_time_us; + uint32_t matching_time_us; + uint32_t overall_time_us; + struct { + uint32_t lo; + uint32_t hi; + } overall_t0; + uint8_t timestamps_invalid; + int8_t template_matched; +} __ec_align2; + +#define EC_CMD_FP_SEED 0x0408 +struct ec_params_fp_seed { + /* + * Version of the structure format (N=3). + */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* Seed from the TPM. */ + uint8_t seed[FP_CONTEXT_TPM_BYTES]; +} __ec_align4; + +#define EC_CMD_FP_ENC_STATUS 0x0409 + +/* FP TPM seed has been set or not */ +#define FP_ENC_STATUS_SEED_SET BIT(0) +/* Session was established or not */ +#define FP_CONTEXT_STATUS_SESSION_ESTABLISHED BIT(1) +/* FP session_nonce had been set or not*/ +#define FP_CONTEXT_SESSION_NONCE_SET BIT(2) +/* FP user_id had been set or not*/ +#define FP_CONTEXT_USER_ID_SET BIT(3) +/* The operation authentication challenge was generated */ +#define FP_AUTH_CHALLENGE_SET BIT(4) +/* Encrypted template is available */ +#define FP_ENCRYPTED_TEMPLATE_READY BIT(5) + +struct ec_response_fp_encryption_status { + /* Used bits in encryption engine status */ + uint32_t valid_flags; + /* Encryption engine status */ + uint32_t status; +} __ec_align4; + +#define EC_CMD_FP_READ_MATCH_SECRET 0x040A +struct ec_params_fp_read_match_secret { + uint16_t fgr; +} __ec_align4; + +/* + * Fingerprint vendor defined command. + * + * A custom per fingerprint vendor host command. It can be used to fetch some + * custom data during testing, manufacturing etc. + * + * This command should be handled only if the system is unlocked. + */ +#define EC_CMD_FP_VENDOR 0x040B +struct ec_params_fp_vendor { + /* Parameter to be used by FP vendors. */ + uint32_t param1; +} __ec_align4; + +/* The positive match secret has the length of the SHA256 digest. */ +#define FP_POSITIVE_MATCH_SECRET_BYTES 32 +struct ec_response_fp_read_match_secret { + uint8_t positive_match_secret[FP_POSITIVE_MATCH_SECRET_BYTES]; +} __ec_align4; + +#define FP_ELLIPTIC_CURVE_PUBLIC_KEY_POINT_LEN 32 + +struct fp_elliptic_curve_public_key { + uint8_t x[FP_ELLIPTIC_CURVE_PUBLIC_KEY_POINT_LEN]; + uint8_t y[FP_ELLIPTIC_CURVE_PUBLIC_KEY_POINT_LEN]; +} __ec_align4; + +#define FP_AES_KEY_ENC_METADATA_VERSION 1 +#define FP_AES_KEY_NONCE_BYTES 12 +#define FP_AES_KEY_ENCRYPTION_SALT_BYTES 16 +#define FP_AES_KEY_TAG_BYTES 16 + +struct fp_auth_command_encryption_metadata { + /* Version of the structure format */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* + * The salt is *only* ever used for key derivation. The nonce is unique, + * a different one is used for every message. + */ + uint8_t nonce[FP_AES_KEY_NONCE_BYTES]; + uint8_t encryption_salt[FP_AES_KEY_ENCRYPTION_SALT_BYTES]; + uint8_t tag[FP_AES_KEY_TAG_BYTES]; +} __ec_align4; + +#define FP_ELLIPTIC_CURVE_PRIVATE_KEY_LEN 32 +#define FP_ELLIPTIC_CURVE_PUBLIC_KEY_IV_LEN 16 + +struct fp_encrypted_private_key { + struct fp_auth_command_encryption_metadata info; + uint8_t data[FP_ELLIPTIC_CURVE_PRIVATE_KEY_LEN]; +} __ec_align4; + +#define EC_CMD_FP_ESTABLISH_PAIRING_KEY_KEYGEN 0x0410 + +struct ec_response_fp_establish_pairing_key_keygen { + struct fp_elliptic_curve_public_key pubkey; +} __ec_align4; + +#define FP_PAIRING_KEY_LEN 32 + +struct ec_fp_encrypted_pairing_key { + struct fp_auth_command_encryption_metadata info; + uint8_t data[FP_PAIRING_KEY_LEN]; +} __ec_align4; + +#define EC_CMD_FP_ESTABLISH_PAIRING_KEY_WRAP 0x0411 + +struct ec_params_fp_establish_pairing_key_wrap { + struct fp_elliptic_curve_public_key peers_pubkey; +} __ec_align4; + +struct ec_response_fp_establish_pairing_key_wrap { + struct ec_fp_encrypted_pairing_key encrypted_pairing_key; +} __ec_align4; + +#define EC_CMD_FP_LOAD_PAIRING_KEY 0x0412 + +typedef struct ec_response_fp_establish_pairing_key_wrap + ec_params_fp_load_pairing_key; + +#define FP_CK_SESSION_NONCE_LEN 32 + +#define EC_CMD_FP_GENERATE_NONCE 0x0413 +struct ec_response_fp_generate_nonce { + uint8_t nonce[FP_CK_SESSION_NONCE_LEN]; +} __ec_align4; + +#define EC_CMD_FP_ESTABLISH_SESSION 0x0414 +struct ec_params_fp_establish_session { + uint8_t peer_nonce[FP_CK_SESSION_NONCE_LEN]; + uint8_t enc_tpm_seed[FP_CONTEXT_TPM_BYTES]; + uint8_t nonce[FP_AES_KEY_NONCE_BYTES]; + uint8_t tag[FP_AES_KEY_TAG_BYTES]; +} __ec_align4; + +#define FP_CHALLENGE_SIZE 32 + +#define EC_CMD_FP_GENERATE_CHALLENGE 0x0415 +struct ec_response_fp_generate_challenge { + uint8_t challenge[FP_CHALLENGE_SIZE]; +} __ec_align4; + +#define EC_CMD_FP_CONFIRM_TEMPLATE 0x0416 +struct ec_params_fp_confirm_template { + uint8_t mac[FP_MAC_LENGTH]; +} __ec_align4; + +#define EC_CMD_FP_SIGN_MATCH 0x0417 +struct ec_params_fp_sign_match { + uint8_t challenge[FP_CHALLENGE_SIZE]; +} __ec_align4; + +struct ec_response_fp_sign_match { + uint8_t signature[FP_MAC_LENGTH]; +} __ec_align4; + +/* + * Fingerprint ASCP claim command. + * + */ +#define EC_CMD_FP_ASCP_CLAIM 0x0420 + +/* + * ECC public key with no point compression as defined in + * ANSI X9.62 section 4.3.6 (0x04||x||y), P256v1 curve. + */ +#define FP_ASCP_KEY_SIZE 65 +/* ECC signature, P256v1 curve, P1363 encoding (r||s) */ +#define FP_ASCP_SIGNATURE_SIZE 64 +/* SHA256 */ +#define FP_ASCP_HASH_SIZE 32 + +struct ec_response_fp_ascp_claim { + /* Model public key. */ + uint8_t pk_m[FP_ASCP_KEY_SIZE]; + /* Model public key signature. */ + uint8_t s_goog[FP_ASCP_SIGNATURE_SIZE]; + /* Device public key. */ + uint8_t pk_d[FP_ASCP_KEY_SIZE]; + /* Device public key signature (signed using model key). */ + uint8_t s_m[FP_ASCP_SIGNATURE_SIZE]; + /* Ephemeral public key used in ECDH procedure. */ + uint8_t pk_f[FP_ASCP_KEY_SIZE]; + /* SHA256 hash of the firmware. */ + uint8_t h_f[FP_ASCP_HASH_SIZE]; + /* Signature of the SHA256( 0xC001 || h_f || pk_f) using device key. */ + uint8_t s_d[FP_ASCP_SIGNATURE_SIZE]; +} __ec_align4; + +/* + * Fingerprint ASCP establish command. + * + */ +#define EC_CMD_FP_ASCP_ESTABLISH 0x0421 + +struct ec_params_fp_ascp_establish { + /* TA's ephemeral public key. */ + uint8_t pk_g[FP_ASCP_KEY_SIZE]; +} __ec_align4; + /*****************************************************************************/ /* Touchpad MCU commands: range 0x0500-0x05FF */ @@ -4534,10 +9030,10 @@ struct __ec_align4 ec_params_fp_frame { /* Get number of frame types, and the size of each type */ #define EC_CMD_TP_FRAME_INFO 0x0501 -struct __ec_align4 ec_response_tp_frame_info { +struct ec_response_tp_frame_info { uint32_t n_frames; - uint32_t frame_sizes[0]; -}; + uint32_t frame_sizes[FLEXIBLE_ARRAY_MEMBER_SIZE]; +} __ec_align4; /* Create a snapshot of current frame readings */ #define EC_CMD_TP_FRAME_SNAPSHOT 0x0502 @@ -4545,12 +9041,246 @@ struct __ec_align4 ec_response_tp_frame_info { /* Read the frame */ #define EC_CMD_TP_FRAME_GET 0x0503 -struct __ec_align4 ec_params_tp_frame_get { +struct ec_params_tp_frame_get { uint32_t frame_index; uint32_t offset; uint32_t size; +} __ec_align4; + +/*****************************************************************************/ +/* EC-EC communication commands: range 0x0600-0x06FF */ + +#define EC_COMM_TEXT_MAX 8 + +/* + * Get battery static information, i.e. information that never changes, or + * very infrequently. + */ +#define EC_CMD_BATTERY_GET_STATIC 0x0600 + +/** + * struct ec_params_battery_static_info - Battery static info parameters + * @index: Battery index. + */ +struct ec_params_battery_static_info { + uint8_t index; +} __ec_align_size1; + +/** + * struct ec_response_battery_static_info - Battery static info response + * @design_capacity: Battery Design Capacity (mAh) + * @design_voltage: Battery Design Voltage (mV) + * @manufacturer: Battery Manufacturer String + * @model: Battery Model Number String + * @serial: Battery Serial Number String + * @type: Battery Type String + * @cycle_count: Battery Cycle Count + */ +struct ec_response_battery_static_info { + uint16_t design_capacity; + uint16_t design_voltage; + char manufacturer[EC_COMM_TEXT_MAX]; + char model[EC_COMM_TEXT_MAX]; + char serial[EC_COMM_TEXT_MAX]; + char type[EC_COMM_TEXT_MAX]; + /* TODO(crbug.com/795991): Consider moving to dynamic structure. */ + uint32_t cycle_count; +} __ec_align4; + +/** + * struct ec_response_battery_static_info_v1 - hostcmd v1 battery static info + * Equivalent to struct ec_response_battery_static_info, but with longer + * strings. + * @design_capacity: battery design capacity (in mAh) + * @design_voltage: battery design voltage (in mV) + * @cycle_count: battery cycle count + * @manufacturer_ext: battery manufacturer string + * @model_ext: battery model string + * @serial_ext: battery serial number string + * @type_ext: battery type string + */ +struct ec_response_battery_static_info_v1 { + uint16_t design_capacity; + uint16_t design_voltage; + uint32_t cycle_count; + char manufacturer_ext[12]; + char model_ext[12]; + char serial_ext[12]; + char type_ext[12]; +} __ec_align4; + +/** + * struct ec_response_battery_static_info_v2 - hostcmd v2 battery static info + * + * Equivalent to struct ec_response_battery_static_info, but with strings + * further lengthened (relative to v1) to accommodate the maximum string length + * permitted by the Smart Battery Data Specification revision 1.1 and fields + * renamed to better match that specification. + * + * @design_capacity: battery design capacity (in mAh) + * @design_voltage: battery design voltage (in mV) + * @cycle_count: battery cycle count + * @manufacturer: battery manufacturer string + * @device_name: battery model string + * @serial: battery serial number string + * @chemistry: battery type string + */ +struct ec_response_battery_static_info_v2 { + uint16_t design_capacity; + uint16_t design_voltage; + uint32_t cycle_count; + char manufacturer[SBS_MAX_STR_OBJ_SIZE]; + char device_name[SBS_MAX_STR_OBJ_SIZE]; + char serial[SBS_MAX_STR_OBJ_SIZE]; + char chemistry[SBS_MAX_STR_OBJ_SIZE]; +} __ec_align4; + +/** + * struct ec_response_battery_static_info_v3 - hostcmd v3 battery static info + * + * Extends struct ec_response_battery_static_info_v2 with + * manuf_info. + * + * @design_capacity: battery design capacity (in mAh) + * @design_voltage: battery design voltage (in mV) + * @cycle_count: battery cycle count + * @manufacturer: battery manufacturer string + * @device_name: battery model string + * @serial: battery serial number string + * @chemistry: battery type string + * @manuf_info: battery manufacture info string (vendor specific) + * @manuf_year: battery manufacture year + * @manuf_month: battery manufacture month + * @manuf_day: battery manufacture day + */ +struct ec_response_battery_static_info_v3 { + uint16_t design_capacity; + uint16_t design_voltage; + uint32_t cycle_count; + char manufacturer[SBS_MAX_STR_OBJ_SIZE]; + char device_name[SBS_MAX_STR_OBJ_SIZE]; + char serial[SBS_MAX_STR_OBJ_SIZE]; + char chemistry[SBS_MAX_STR_OBJ_SIZE]; + char manuf_info[SBS_MAX_STR_OBJ_SIZE]; + uint16_t manuf_year; + uint8_t manuf_month; + uint8_t manuf_day; +} __ec_align4; + +/* + * Get battery dynamic information, i.e. information that is likely to change + * every time it is read. + */ +#define EC_CMD_BATTERY_GET_DYNAMIC 0x0601 + +/** + * struct ec_params_battery_dynamic_info - Battery dynamic info parameters + * @index: Battery index. + */ +struct ec_params_battery_dynamic_info { + uint8_t index; +} __ec_align_size1; + +/** + * struct ec_response_battery_dynamic_info - Battery dynamic info response + * @actual_voltage: Battery voltage (mV) + * @actual_current: Battery current (mA); negative=discharging + * @remaining_capacity: Remaining capacity (mAh) + * @full_capacity: Capacity (mAh, might change occasionally) + * @flags: Flags, see EC_BATT_FLAG_* + * @desired_voltage: Charging voltage desired by battery (mV) + * @desired_current: Charging current desired by battery (mA) + */ +struct ec_response_battery_dynamic_info { + int16_t actual_voltage; + int16_t actual_current; + int16_t remaining_capacity; + int16_t full_capacity; + int16_t flags; + int16_t desired_voltage; + int16_t desired_current; +} __ec_align2; + +/** + * struct ec_response_battery_dynamic_info_v1 - Battery dynamic info response + * (v1) + * @actual_voltage: Battery voltage (mV) + * @actual_current: Battery current (mA); negative=discharging + * @remaining_capacity: Remaining capacity (mAh) + * @full_capacity: Capacity (mAh, might change occasionally) + * @flags: Flags, see EC_BATT_FLAG_* + * @desired_voltage: Charging voltage desired by battery (mV) + * @desired_current: Charging current desired by battery (mA) + * @temperature: Battery temperature (dK) + */ +struct ec_response_battery_dynamic_info_v1 { + int16_t actual_voltage; + int16_t actual_current; + int16_t remaining_capacity; + int16_t full_capacity; + int16_t flags; + int16_t desired_voltage; + int16_t desired_current; + uint16_t temperature; +} __ec_align2; + +/* + * Control charger chip. Used to control charger chip on the peripheral. + */ +#define EC_CMD_CHARGER_CONTROL 0x0602 + +/** + * struct ec_params_charger_control - Charger control parameters + * @max_current: Charger current (mA). Positive to allow base to draw up to + * max_current and (possibly) charge battery, negative to request current + * from base (OTG). + * @otg_voltage: Voltage (mV) to use in OTG mode, ignored if max_current is + * >= 0. + * @allow_charging: Allow base battery charging (only makes sense if + * max_current > 0). + */ +struct ec_params_charger_control { + int16_t max_current; + uint16_t otg_voltage; + uint8_t allow_charging; +} __ec_align_size1; + +/* Get ACK from the USB-C SS muxes */ +#define EC_CMD_USB_PD_MUX_ACK 0x0603 + +struct ec_params_usb_pd_mux_ack { + uint8_t port; /* USB-C port number */ +} __ec_align1; + +/* Get boot time */ +#define EC_CMD_GET_BOOT_TIME 0x0604 + +enum boot_time_param { + ARAIL = 0, + RSMRST, + ESPIRST, + PLTRST_LOW, + PLTRST_HIGH, + EC_CUR_TIME, + RESET_CNT, }; +struct ec_response_get_boot_time { + uint64_t timestamp[RESET_CNT]; + uint16_t cnt; +} __ec_align4; + +/* Issue AP shutdown */ +#define EC_CMD_AP_SHUTDOWN 0x0605 + +/** + * Issue AP shutdown using heartbeat wake. + * The AP calls this to enter the low-power G3 state for off-mode charging. + * The EC then monitors battery SoC and wakes the AP when discharged by a + * configured threshold. + */ +#define EC_CMD_ENABLE_OFFMODE_HEARTBEAT 0x0606 + /*****************************************************************************/ /* * Reserve a range of host commands for board-specific, experimental, or @@ -4621,10 +9351,14 @@ struct __ec_align4 ec_params_tp_frame_get { * switch to the new names soon, as the old names may not be carried forward * forever. */ -#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE -#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 -#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE +#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE +#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 +#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE -#endif /* !__ACPI__ && !__KERNEL__ */ +#endif /* !__ACPI__ */ + +#ifdef __cplusplus +} +#endif -#endif /* __CROS_EC_COMMANDS_H */ +#endif /* __CROS_EC_EC_COMMANDS_H */ -- cgit v1.3.1 From 6da8ecc5189d36221211956cb3e7097db7f15267 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:16:56 +0200 Subject: video: bridge: anx6345: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/video/bridge/anx6345.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/bridge/anx6345.c b/drivers/video/bridge/anx6345.c index 8cee4c958bd..a5d2781aa48 100644 --- a/drivers/video/bridge/anx6345.c +++ b/drivers/video/bridge/anx6345.c @@ -403,7 +403,7 @@ static int anx6345_probe(struct udevice *dev) return anx6345_enable(dev); } -struct video_bridge_ops anx6345_ops = { +static const struct video_bridge_ops anx6345_ops = { .attach = anx6345_attach, .set_backlight = anx6345_set_backlight, .read_edid = anx6345_read_edid, -- cgit v1.3.1 From af65e247e7718e7b16d402f3e7d17844e3ccc677 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:16:57 +0200 Subject: video: bridge: ps862x: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/video/bridge/ps862x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/bridge/ps862x.c b/drivers/video/bridge/ps862x.c index efd03752281..a08227f8355 100644 --- a/drivers/video/bridge/ps862x.c +++ b/drivers/video/bridge/ps862x.c @@ -116,7 +116,7 @@ static int ps8622_probe(struct udevice *dev) return 0; } -struct video_bridge_ops ps8622_ops = { +static const struct video_bridge_ops ps8622_ops = { .attach = ps8622_attach, .set_backlight = ps8622_set_backlight, }; -- cgit v1.3.1 From 772ef8b0890565cc9645336d9539b49863e7891b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:16:58 +0200 Subject: video: bridge: ptn3460: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/video/bridge/ptn3460.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/bridge/ptn3460.c b/drivers/video/bridge/ptn3460.c index 5851e1ef15e..ce576c0b282 100644 --- a/drivers/video/bridge/ptn3460.c +++ b/drivers/video/bridge/ptn3460.c @@ -15,7 +15,7 @@ static int ptn3460_attach(struct udevice *dev) return video_bridge_set_active(dev, true); } -struct video_bridge_ops ptn3460_ops = { +static const struct video_bridge_ops ptn3460_ops = { .attach = ptn3460_attach, }; -- cgit v1.3.1 From 3ddd78074e87abc04e662dedc2a0b1a39cb2eb26 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:16:59 +0200 Subject: video: console: normal: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/video/console_normal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index 07db613ac53..6dc0a6eaf9d 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -133,7 +133,7 @@ static int console_set_cursor_visible(struct udevice *dev, bool visible, return 0; } -struct vidconsole_ops console_ops = { +static const struct vidconsole_ops console_ops = { .putc_xy = console_putc_xy, .move_rows = console_move_rows, .set_row = console_set_row, -- cgit v1.3.1 From c6266daa1e22e5f3e27960b4f306f1f0e7006798 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:17:00 +0200 Subject: video: console: rotate: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/video/console_rotate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c index 886b25dcfaf..e478e0ef3bc 100644 --- a/drivers/video/console_rotate.c +++ b/drivers/video/console_rotate.c @@ -284,7 +284,7 @@ static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, int cp) return VID_TO_POS(fontdata->width); } -struct vidconsole_ops console_ops_1 = { +static const struct vidconsole_ops console_ops_1 = { .putc_xy = console_putc_xy_1, .move_rows = console_move_rows_1, .set_row = console_set_row_1, @@ -293,7 +293,7 @@ struct vidconsole_ops console_ops_1 = { .select_font = console_simple_select_font, }; -struct vidconsole_ops console_ops_2 = { +static const struct vidconsole_ops console_ops_2 = { .putc_xy = console_putc_xy_2, .move_rows = console_move_rows_2, .set_row = console_set_row_2, @@ -302,7 +302,7 @@ struct vidconsole_ops console_ops_2 = { .select_font = console_simple_select_font, }; -struct vidconsole_ops console_ops_3 = { +static const struct vidconsole_ops console_ops_3 = { .putc_xy = console_putc_xy_3, .move_rows = console_move_rows_3, .set_row = console_set_row_3, -- cgit v1.3.1 From 8f7717c756652bf7fa168be675a91b55164d4334 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:17:01 +0200 Subject: video: console: truetype: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/video/console_truetype.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index eaf169e8386..b9b6f394fbc 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -1069,7 +1069,7 @@ static int console_truetype_probe(struct udevice *dev) return 0; } -struct vidconsole_ops console_truetype_ops = { +static const struct vidconsole_ops console_truetype_ops = { .putc_xy = console_truetype_putc_xy, .move_rows = console_truetype_move_rows, .set_row = console_truetype_set_row, -- cgit v1.3.1 From b2f7404fd8ad03405aa75ad1bdbbba01e144785e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:17:02 +0200 Subject: video: dw_mipi_dsi: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/video/dw_mipi_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c index c74fe678d12..ec5d4c81812 100644 --- a/drivers/video/dw_mipi_dsi.c +++ b/drivers/video/dw_mipi_dsi.c @@ -837,7 +837,7 @@ static int dw_mipi_dsi_enable(struct udevice *dev) return 0; } -struct dsi_host_ops dw_mipi_dsi_ops = { +static const struct dsi_host_ops dw_mipi_dsi_ops = { .init = dw_mipi_dsi_init, .enable = dw_mipi_dsi_enable, }; -- cgit v1.3.1 From 7e7b3106a50b72ab78e28f81e9ab9f96817b5e47 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:17:03 +0200 Subject: video: imx: ldb: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/video/imx/ldb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/imx/ldb.c b/drivers/video/imx/ldb.c index e918341c0a3..32a327647f8 100644 --- a/drivers/video/imx/ldb.c +++ b/drivers/video/imx/ldb.c @@ -230,7 +230,7 @@ dis_clk: return ret; } -struct video_bridge_ops imx_ldb_ops = { +static const struct video_bridge_ops imx_ldb_ops = { .attach = imx_ldb_attach, .set_backlight = imx_ldb_set_backlight, }; -- cgit v1.3.1 From dd2f4d967f12b896ff976b3b21311c1000aece2a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:17:04 +0200 Subject: video: stm32: Staticize and constify driver ops MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard Reviewed-by: Simon Glass Reviewed-by: Raphaël Gallais-Pou --- drivers/video/stm32/stm32_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c index 5c4d8d2aab5..29c57a4ff89 100644 --- a/drivers/video/stm32/stm32_dsi.c +++ b/drivers/video/stm32/stm32_dsi.c @@ -511,7 +511,7 @@ err_reg: return ret; } -struct video_bridge_ops stm32_dsi_ops = { +static const struct video_bridge_ops stm32_dsi_ops = { .attach = stm32_dsi_attach, .set_backlight = stm32_dsi_set_backlight, }; -- cgit v1.3.1 From 16185d7ff317b0406b6386e67ebbe175377449b0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:17:05 +0200 Subject: video: tda19988: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/video/tda19988.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/tda19988.c b/drivers/video/tda19988.c index ebc8521c6ed..a4cc3a49232 100644 --- a/drivers/video/tda19988.c +++ b/drivers/video/tda19988.c @@ -522,7 +522,7 @@ static int tda19988_enable(struct udevice *dev, int panel_bpp, return 0; } -struct dm_display_ops tda19988_ops = { +static const struct dm_display_ops tda19988_ops = { .read_edid = tda19988_read_edid, .enable = tda19988_enable, }; -- cgit v1.3.1 From 674afbcf6e9f838cc34425972e893e233835364a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:17:06 +0200 Subject: video: tegra: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Acked-by: Svyatoslav Ryhel Reviewed-by: Simon Glass --- drivers/video/tegra/dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/tegra/dsi.c b/drivers/video/tegra/dsi.c index bc308869f4e..f53fabf6fd6 100644 --- a/drivers/video/tegra/dsi.c +++ b/drivers/video/tegra/dsi.c @@ -337,7 +337,7 @@ static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, return count; } -struct mipi_dsi_host_ops tegra_dsi_bridge_host_ops = { +static const struct mipi_dsi_host_ops tegra_dsi_bridge_host_ops = { .transfer = tegra_dsi_host_transfer, }; -- cgit v1.3.1 From 6033096d3c1e09d6aeba456d13e4c7554ca3b871 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 20 Mar 2026 14:53:54 -0600 Subject: video: Correct dependencies of LOGICORE_DP_TX In order to build LOGICORE_DP_TX we must also have enabled AXI, so add that as a dependency as well. Signed-off-by: Tom Rini --- drivers/video/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index c2acc13139c..cf633db02cb 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -865,7 +865,7 @@ source "drivers/video/exynos/Kconfig" config LOGICORE_DP_TX bool "Enable Logicore DP TX driver" - depends on DISPLAY + depends on DISPLAY && AXI help Enable the driver for the transmitter part of the Xilinx LogiCORE DisplayPort, a IP core for Xilinx FPGAs that implements a DisplayPort -- cgit v1.3.1 From ff3bece92fc5e0bdbd49e6b3e87da58fb4129a3c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 23 Mar 2026 13:53:09 -0600 Subject: video: Correct dependencies for VIDEO_LCD_RAYDIUM_RM68200 The VIDEO_LCD_RAYDIUM_RM68200 functionality can only work with BACKLIGHT enabled, so express this dependency in Kconfig. Signed-off-by: Tom Rini --- drivers/video/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index cf633db02cb..508af2805c5 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -602,6 +602,7 @@ config VIDEO_LCD_LG_LH400WV3 config VIDEO_LCD_RAYDIUM_RM68200 bool "RM68200 DSI LCD panel support" + depends on BACKLIGHT select VIDEO_MIPI_DSI help Say Y here if you want to enable support for Raydium RM68200 -- cgit v1.3.1 From df08b27590d5c4bdc1bd644a6bcb8c0dc964780f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 23 Mar 2026 13:53:11 -0600 Subject: video: Correct dependencies for VIDEO_TIDSS The VIDEO_TIDSS functionality can only work with PANEL enabled, so express this dependency in Kconfig for all phases. Signed-off-by: Tom Rini --- drivers/video/tidss/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/video/tidss/Kconfig b/drivers/video/tidss/Kconfig index 3291b3ceb8d..c9849110059 100644 --- a/drivers/video/tidss/Kconfig +++ b/drivers/video/tidss/Kconfig @@ -10,7 +10,7 @@ menuconfig VIDEO_TIDSS bool "Enable TIDSS video support" - depends on VIDEO + depends on VIDEO && PANEL imply VIDEO_DAMAGE help TIDSS supports video output options LVDS and @@ -19,7 +19,7 @@ menuconfig VIDEO_TIDSS config SPL_VIDEO_TIDSS bool "Enable TIDSS video support in SPL Stage" - depends on SPL_VIDEO + depends on SPL_VIDEO && SPL_PANEL help This options enables tidss driver in SPL stage. If you need to use tidss at SPL stage use this config. -- cgit v1.3.1 From 1c8b592611fc7b6bacf10226cfada6620ca19011 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 8 Apr 2026 14:04:28 +0200 Subject: video: simplefb: Map framebuffer region on probe on ARM64 The framebuffer buffer might not be mapped on some devices. This is #ifdef'ed for ARM64 since mmu_map_region() is not defined for any other architecture. Signed-off-by: Luca Weiss Acked-by: Sumit Garg --- drivers/video/simplefb.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers') diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index 8d0772d4e51..4d238b936ac 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include static int simple_video_probe(struct udevice *dev) { @@ -37,6 +39,13 @@ static int simple_video_probe(struct udevice *dev) plat->base = base; plat->size = size; +#ifdef CONFIG_ARM64 + /* The framebuffer buffer might not be mapped on some devices */ + if (plat->base % SZ_4K) + log_warning("Framebuffer base %lx is not 4k aligned!\n", plat->base); + mmu_map_region((phys_addr_t)plat->base, (phys_addr_t)ALIGN(plat->size, SZ_4K), false); +#endif + video_set_flush_dcache(dev, true); debug("%s: Query resolution...\n", __func__); -- cgit v1.3.1 From 258310ab39ab740d302335237d0d7d782cbe9488 Mon Sep 17 00:00:00 2001 From: Aelin Reidel Date: Sun, 3 May 2026 21:34:53 +0200 Subject: video: simplefb: Parse memory region from memory-region property Linux' simplefb driver allows setting the memory-region property to a phandle to a node that describes the memory to be used for the framebuffer. If it is present, it will override the "reg" property. This adds support for parsing the property and prefers it if present. Signed-off-by: Aelin Reidel Reviewed-by: Simon Glass --- drivers/video/simplefb.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index 4d238b936ac..631ae00b1e1 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -22,8 +22,14 @@ static int simple_video_probe(struct udevice *dev) fdt_addr_t base; fdt_size_t size; u32 width, height, stride, rot; + struct ofnode_phandle_args args; + + ret = dev_read_phandle_with_args(dev, "memory-region", NULL, 0, 0, &args); + if (ret) + base = dev_read_addr_size(dev, &size); + else + base = ofnode_get_addr_size(args.node, "reg", &size); - base = dev_read_addr_size(dev, &size); if (base == FDT_ADDR_T_NONE) { debug("%s: Failed to decode memory region\n", __func__); return -EINVAL; -- cgit v1.3.1 From 2be4b2269ee4cef497043e39bfe1e727fd85950f Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 12 May 2026 09:51:40 +0200 Subject: video: Kconfig: fix indentation of help text Fix the indentation of the help text for VIDEO_LCD_NOVATEK_NT35510 and VIDEO_LCD_ORISETECH_OTM8009A to align with the standard Kconfig format. Signed-off-by: Dario Binacchi Reviewed-by: Quentin Schulz Reviewed-by: Heinrich Schuchardt --- drivers/video/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 508af2805c5..fb7c982f46c 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -574,15 +574,15 @@ config VIDEO_LCD_NOVATEK_NT35510 bool "Novatek NT35510 DSI LCD panel support" select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Novatek nt35510 - dsi panel. + Say Y here if you want to enable support for Novatek nt35510 + dsi panel. config VIDEO_LCD_ORISETECH_OTM8009A bool "OTM8009A DSI LCD panel support" select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Orise Technology - otm8009a 480x800 dsi 2dl panel. + Say Y here if you want to enable support for Orise Technology + otm8009a 480x800 dsi 2dl panel. config VIDEO_LCD_LG_LD070WX3 bool "LD070WX3 DSI LCD panel support" -- cgit v1.3.1 From 5f5b8ae2938380babe1843fba4aebc299b811ab8 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 12 May 2026 09:54:01 +0200 Subject: video: kconfig: replace tristate with bool for LCD panel drivers U-Boot does not support loadable modules, therefore using 'tristate' in Kconfig is incorrect since the 'm' option cannot be selected. Replace tristate with bool for the affected LCD panel drivers to reflect the U-Boot build model and avoid misleading configuration options. No functional change intended. Signed-off-by: Dario Binacchi Reviewed-by: Tom Rini Reviewed-by: Svyatoslav Ryhel --- drivers/video/Kconfig | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index fb7c982f46c..25475ef8fd7 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -534,7 +534,7 @@ config VIDEO_BCM2835 that U-Boot can access it with full colour depth. config VIDEO_LCD_ENDEAVORU - tristate "Endeavoru 720x1280 DSI video mode panel" + bool "Endeavoru 720x1280 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -561,7 +561,7 @@ config VIDEO_LCD_ILITEK_ILI9806E is implemented. config VIDEO_LCD_MOT - tristate "Atrix 4G and Droid X2 540x960 DSI video mode panel" + bool "Atrix 4G and Droid X2 540x960 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -609,7 +609,7 @@ config VIDEO_LCD_RAYDIUM_RM68200 720x1280 DSI video mode panel. config VIDEO_LCD_RENESAS_R61307 - tristate "Renesas R61307 DSI video mode panel" + bool "Renesas R61307 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -618,7 +618,7 @@ config VIDEO_LCD_RENESAS_R61307 resolution and uses 24 bit RGB per pixel. config VIDEO_LCD_RENESAS_R69328 - tristate "Renesas R69328 720x1280 DSI video mode panel" + bool "Renesas R69328 720x1280 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -627,7 +627,7 @@ config VIDEO_LCD_RENESAS_R69328 resolution and uses 24 bit RGB per pixel. config VIDEO_LCD_SAMSUNG_LTL106HL02 - tristate "Samsung LTL106HL02 1920x1080 DSI video mode panel" + bool "Samsung LTL106HL02 1920x1080 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -636,7 +636,7 @@ config VIDEO_LCD_SAMSUNG_LTL106HL02 resolution (1920x1080). config VIDEO_LCD_SHARP_LQ079L1SX01 - tristate "Sharp LQ079L1SX01 1536x2048 DSI video mode panel" + bool "Sharp LQ079L1SX01 1536x2048 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -645,7 +645,7 @@ config VIDEO_LCD_SHARP_LQ079L1SX01 resolution (1536x2048). config VIDEO_LCD_SHARP_LQ101R1SX01 - tristate "Sharp LQ101R1SX01 2560x1600 DSI video mode panel" + bool "Sharp LQ101R1SX01 2560x1600 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -689,7 +689,7 @@ config VIDEO_LCD_TDO_TL070WSH30 1024x600 DSI video mode panel. config VIDEO_LCD_HITACHI_TX10D07VM0BAA - tristate "Hitachi TX10D07VM0BAA 480x800 MIPI DSI video mode panel" + bool "Hitachi TX10D07VM0BAA 480x800 MIPI DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -704,7 +704,7 @@ config VIDEO_LCD_HITACHI_TX18D42VM done they work like a regular LVDS panel. config VIDEO_LCD_SONY_L4F00430T01 - tristate "Sony L4F00430T01 480x800 LCD panel support" + bool "Sony L4F00430T01 480x800 LCD panel support" depends on PANEL help Say Y here if you want to enable support for Sony L4F00430T01 @@ -713,7 +713,7 @@ config VIDEO_LCD_SONY_L4F00430T01 data comes from RGB. config VIDEO_LCD_SAMSUNG_S6E63M0 - tristate "Samsung S6E63M0 controller based panel support" + bool "Samsung S6E63M0 controller based panel support" depends on PANEL && BACKLIGHT help Say Y here if you want to enable support for Samsung S6E63M0 -- cgit v1.3.1 From 5cf4b1428485048bed4b53ed600c17bae016dd8c Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Tue, 12 May 2026 23:31:50 +0400 Subject: video console: add 6x8 console font from linux Small screens on the order of 256x144 pixels can't fit much text at 8x16, and 4x6 is virtually illegible, so add an in-between 6x8 font from Linux. Font data obtained from lib/fonts/font_6x8.c in the Linux kernel at commit db65872b38dc ("lib/fonts: Remove internal symbols and macros from public header file") Link: https://github.com/torvalds/linux/blob/db65872b38dc9f18a62669d6ae1e4ec7868a85a9/lib/fonts/font_6x8.c Signed-off-by: Alexey Charkov --- drivers/video/Kconfig | 7 + include/video_font.h | 6 + include/video_font_6x8.h | 2578 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 2591 insertions(+) create mode 100644 include/video_font_6x8.h (limited to 'drivers') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 25475ef8fd7..5a0dfb159c4 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -29,6 +29,13 @@ config VIDEO_FONT_4X6 Provides character bitmap data in header file. When selecting multiple fonts, you may want to enable CMD_SELECT_FONT too. +config VIDEO_FONT_6X8 + bool "6 x 8 font size" + help + Font for video console driver, 6 x 8 pixels. + Provides character bitmap data in header file. + When selecting multiple fonts, you may want to enable CMD_SELECT_FONT too. + config VIDEO_FONT_8X16 bool "8 x 16 font size" default y diff --git a/include/video_font.h b/include/video_font.h index 05d3f989a77..4bfb00eb80f 100644 --- a/include/video_font.h +++ b/include/video_font.h @@ -12,6 +12,9 @@ #if defined(CONFIG_VIDEO_FONT_4X6) #include #endif +#if defined(CONFIG_VIDEO_FONT_6X8) +#include +#endif #if defined(CONFIG_VIDEO_FONT_8X16) #include #endif @@ -29,6 +32,9 @@ static struct video_fontdata __maybe_unused fonts[] = { #if defined(CONFIG_VIDEO_FONT_4X6) FONT_ENTRY(4, 6, 4x6), #endif +#if defined(CONFIG_VIDEO_FONT_6X8) + FONT_ENTRY(6, 8, 6x8), +#endif #if defined(CONFIG_VIDEO_FONT_SUN12X22) FONT_ENTRY(12, 22, 12x22), #endif diff --git a/include/video_font_6x8.h b/include/video_font_6x8.h new file mode 100644 index 00000000000..db5ec4cbe5e --- /dev/null +++ b/include/video_font_6x8.h @@ -0,0 +1,2578 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * 6x8 bitmap font from the Linux kernel adapted for U-boot video console + * + * Original Linux file at lib/fonts/font_6x8.c retrieved at Linux commit + * db65872b38dc ("lib/fonts: Remove internal symbols and macros from public + * header file") + */ + +#ifndef _VIDEO_FONT_6X8_ +#define _VIDEO_FONT_6X8_ + +#include + +static unsigned char video_fontdata_6x8[VIDEO_FONT_SIZE(256, 6, 8)] = { + /* 0 0x00 '^@' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 1 0x01 '^A' */ + 0x78, /* 011110 */ + 0x84, /* 100001 */ + 0xCC, /* 110011 */ + 0x84, /* 100001 */ + 0xCC, /* 110011 */ + 0xB4, /* 101101 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 2 0x02 '^B' */ + 0x78, /* 011110 */ + 0xFC, /* 111111 */ + 0xB4, /* 101101 */ + 0xFC, /* 111111 */ + 0xB4, /* 101101 */ + 0xCC, /* 110011 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 3 0x03 '^C' */ + 0x00, /* 000000 */ + 0x28, /* 001010 */ + 0x7C, /* 011111 */ + 0x7C, /* 011111 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 4 0x04 '^D' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x7C, /* 011111 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 5 0x05 '^E' */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x6C, /* 011011 */ + 0x6C, /* 011011 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 6 0x06 '^F' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x7C, /* 011111 */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 7 0x07 '^G' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x78, /* 011110 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 8 0x08 '^H' */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xCC, /* 110011 */ + 0x84, /* 100001 */ + 0xCC, /* 110011 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + + /* 9 0x09 '^I' */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x48, /* 010010 */ + 0x84, /* 100001 */ + 0x48, /* 010010 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 10 0x0A '^J' */ + 0xFC, /* 111111 */ + 0xCC, /* 110011 */ + 0xB4, /* 101101 */ + 0x78, /* 011110 */ + 0xB4, /* 101101 */ + 0xCC, /* 110011 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + + /* 11 0x0B '^K' */ + 0x3C, /* 001111 */ + 0x14, /* 000101 */ + 0x20, /* 001000 */ + 0x78, /* 011110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 12 0x0C '^L' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 13 0x0D '^M' */ + 0x18, /* 000110 */ + 0x14, /* 000101 */ + 0x14, /* 000101 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x70, /* 011100 */ + 0x60, /* 011000 */ + 0x00, /* 000000 */ + + /* 14 0x0E '^N' */ + 0x3C, /* 001111 */ + 0x24, /* 001001 */ + 0x3C, /* 001111 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x6C, /* 011011 */ + 0x6C, /* 011011 */ + 0x00, /* 000000 */ + + /* 15 0x0F '^O' */ + 0x10, /* 000100 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x6C, /* 011011 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 16 0x10 '^P' */ + 0x40, /* 010000 */ + 0x60, /* 011000 */ + 0x70, /* 011100 */ + 0x78, /* 011110 */ + 0x70, /* 011100 */ + 0x60, /* 011000 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + + /* 17 0x11 '^Q' */ + 0x04, /* 000001 */ + 0x0C, /* 000011 */ + 0x1C, /* 000111 */ + 0x3C, /* 001111 */ + 0x1C, /* 000111 */ + 0x0C, /* 000011 */ + 0x04, /* 000001 */ + 0x00, /* 000000 */ + + /* 18 0x12 '^R' */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x10, /* 000100 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 19 0x13 '^S' */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x00, /* 000000 */ + 0x48, /* 010010 */ + 0x00, /* 000000 */ + + /* 20 0x14 '^T' */ + 0x3C, /* 001111 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x3C, /* 001111 */ + 0x14, /* 000101 */ + 0x14, /* 000101 */ + 0x14, /* 000101 */ + 0x00, /* 000000 */ + + /* 21 0x15 '^U' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x30, /* 001100 */ + 0x28, /* 001010 */ + 0x14, /* 000101 */ + 0x0C, /* 000011 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + + /* 22 0x16 '^V' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xF8, /* 111110 */ + 0xF8, /* 111110 */ + 0xF8, /* 111110 */ + 0x00, /* 000000 */ + + /* 23 0x17 '^W' */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x10, /* 000100 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x7C, /* 011111 */ + + /* 24 0x18 '^X' */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 25 0x19 '^Y' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 26 0x1A '^Z' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x7C, /* 011111 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 27 0x1B '^[' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x7C, /* 011111 */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 28 0x1C '^\' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 29 0x1D '^]' */ + 0x00, /* 000000 */ + 0x48, /* 010010 */ + 0x84, /* 100001 */ + 0xFC, /* 111111 */ + 0x84, /* 100001 */ + 0x48, /* 010010 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 30 0x1E '^^' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x7C, /* 011111 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 31 0x1F '^_' */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x7C, /* 011111 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 32 0x20 ' ' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 33 0x21 '!' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 34 0x22 '"' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 35 0x23 '#' */ + 0x00, /* 000000 */ + 0x28, /* 001010 */ + 0x7C, /* 011111 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x7C, /* 011111 */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + + /* 36 0x24 '$' */ + 0x10, /* 000000 */ + 0x38, /* 001000 */ + 0x40, /* 010000 */ + 0x30, /* 001000 */ + 0x08, /* 000000 */ + 0x70, /* 011000 */ + 0x20, /* 001000 */ + 0x00, /* 000000 */ + + /* 37 0x25 '%' */ + 0x64, /* 011001 */ + 0x64, /* 011001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x4C, /* 010011 */ + 0x4C, /* 010011 */ + 0x00, /* 000000 */ + + /* 38 0x26 '&' */ + 0x30, /* 001100 */ + 0x48, /* 010010 */ + 0x50, /* 010100 */ + 0x20, /* 001000 */ + 0x54, /* 010101 */ + 0x48, /* 010010 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 39 0x27 ''' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 40 0x28 '(' */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x20, /* 001000 */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + + /* 41 0x29 ')' */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x00, /* 000000 */ + + /* 42 0x2A '*' */ + 0x10, /* 000100 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 43 0x2B '+' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 44 0x2C ',' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x30, /* 001100 */ + 0x20, /* 001000 */ + + /* 45 0x2D '-' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 46 0x2E '.' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x18, /* 000110 */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + + /* 47 0x2F '/' */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x20, /* 001000 */ + 0x40, /* 010000 */ + + /* 48 0x30 '0' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x54, /* 010101 */ + 0x64, /* 011001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 49 0x31 '1' */ + 0x10, /* 000100 */ + 0x30, /* 001100 */ + 0x50, /* 010100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 50 0x32 '2' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 51 0x33 '3' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x04, /* 000001 */ + 0x18, /* 000110 */ + 0x04, /* 000001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 52 0x34 '4' */ + 0x08, /* 000010 */ + 0x18, /* 000110 */ + 0x28, /* 001010 */ + 0x48, /* 010010 */ + 0x7C, /* 011111 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + + /* 53 0x35 '5' */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x04, /* 000001 */ + 0x04, /* 000001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 54 0x36 '6' */ + 0x18, /* 000110 */ + 0x20, /* 001000 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 55 0x37 '7' */ + 0x7C, /* 011111 */ + 0x04, /* 000001 */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 56 0x38 '8' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 57 0x39 '9' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + + /* 58 0x3A ':' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x18, /* 000110 */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x18, /* 000110 */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + + /* 59 0x3B ';' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x30, /* 001100 */ + 0x20, /* 001000 */ + + /* 60 0x3C '<' */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x04, /* 000001 */ + 0x00, /* 000000 */ + + /* 61 0x3D '=' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 62 0x3E '>' */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x00, /* 000000 */ + + /* 63 0x3F '?' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 64 0x40 '@' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x5C, /* 010111 */ + 0x54, /* 010101 */ + 0x5C, /* 010111 */ + 0x40, /* 010000 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 65 0x41 'A' */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 66 0x42 'B' */ + 0x78, /* 011110 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x38, /* 001110 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 67 0x43 'C' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 68 0x44 'D' */ + 0x78, /* 011110 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 69 0x45 'E' */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 70 0x46 'F' */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + + /* 71 0x47 'G' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x5C, /* 010111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 72 0x48 'H' */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 73 0x49 'I' */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 74 0x4A 'J' */ + 0x1C, /* 000111 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + + /* 75 0x4B 'K' */ + 0x44, /* 010001 */ + 0x48, /* 010010 */ + 0x50, /* 010100 */ + 0x60, /* 011000 */ + 0x50, /* 010100 */ + 0x48, /* 010010 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 76 0x4C 'L' */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 77 0x4D 'M' */ + 0x44, /* 010001 */ + 0x6C, /* 011011 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 78 0x4E 'N' */ + 0x44, /* 010001 */ + 0x64, /* 011001 */ + 0x54, /* 010101 */ + 0x4C, /* 010011 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 79 0x4F 'O' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 80 0x50 'P' */ + 0x78, /* 011110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x78, /* 011110 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + + /* 81 0x51 'Q' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x54, /* 010101 */ + 0x48, /* 010010 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 82 0x52 'R' */ + 0x78, /* 011110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x78, /* 011110 */ + 0x50, /* 010100 */ + 0x48, /* 010010 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 83 0x53 'S' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 84 0x54 'T' */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 85 0x55 'U' */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 86 0x56 'V' */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 87 0x57 'W' */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x6C, /* 011011 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 88 0x58 'X' */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 89 0x59 'Y' */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 90 0x5A 'Z' */ + 0x7C, /* 011111 */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x40, /* 010000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 91 0x5B '[' */ + 0x18, /* 000110 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + + /* 92 0x5C '\' */ + 0x40, /* 010000 */ + 0x20, /* 001000 */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x04, /* 000001 */ + + /* 93 0x5D ']' */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + + /* 94 0x5E '^' */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 95 0x5F '_' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + + /* 96 0x60 '`' */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 97 0x61 'a' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 98 0x62 'b' */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x58, /* 010110 */ + 0x64, /* 011001 */ + 0x44, /* 010001 */ + 0x64, /* 011001 */ + 0x58, /* 010110 */ + 0x00, /* 000000 */ + + /* 99 0x63 'c' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 100 0x64 'd' */ + 0x04, /* 000001 */ + 0x04, /* 000001 */ + 0x34, /* 001101 */ + 0x4C, /* 010011 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 101 0x65 'e' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 102 0x66 'f' */ + 0x0C, /* 000011 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 103 0x67 'g' */ + 0x00, /* 000000 */ + 0x34, /* 001101 */ + 0x4C, /* 010011 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x04, /* 000001 */ + 0x38, /* 001110 */ + + /* 104 0x68 'h' */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 105 0x69 'i' */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 106 0x6A 'j' */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x60, /* 011000 */ + + /* 107 0x6B 'k' */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x48, /* 010010 */ + 0x50, /* 010100 */ + 0x70, /* 011100 */ + 0x48, /* 010010 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 108 0x6C 'l' */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 109 0x6D 'm' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x68, /* 011010 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x00, /* 000000 */ + + /* 110 0x6E 'n' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x58, /* 010110 */ + 0x64, /* 011001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 111 0x6F 'o' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 112 0x70 'p' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x78, /* 011110 */ + 0x44, /* 010001 */ + 0x64, /* 011001 */ + 0x58, /* 010110 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + + /* 113 0x71 'q' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x04, /* 000001 */ + 0x04, /* 000001 */ + + /* 114 0x72 'r' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x58, /* 010110 */ + 0x64, /* 011001 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + + /* 115 0x73 's' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x3C, /* 001111 */ + 0x40, /* 010000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 116 0x74 't' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x0C, /* 000011 */ + 0x00, /* 000000 */ + + /* 117 0x75 'u' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 118 0x76 'v' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 119 0x77 'w' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + + /* 120 0x78 'x' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 121 0x79 'y' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x04, /* 000001 */ + 0x38, /* 001110 */ + + /* 122 0x7A 'z' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 123 0x7B '{' */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + + /* 124 0x7C '|' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 125 0x7D '}' */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x00, /* 000000 */ + + /* 126 0x7E '~' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x20, /* 001000 */ + 0x54, /* 010101 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 127 0x7F 'DEL' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 128 0x80 '\200' */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + + /* 129 0x81 '\201' */ + 0x00, /* 000000 */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 130 0x82 '\202' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 131 0x83 '\203' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 132 0x84 '\204' */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 133 0x85 '\205' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 134 0x86 '\206' */ + 0x3C, /* 001111 */ + 0x18, /* 000110 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 135 0x87 '\207' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + + /* 136 0x88 '\210' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 137 0x89 '\211' */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 138 0x8A '\212' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 139 0x8B '\213' */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 140 0x8C '\214' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 141 0x8D '\215' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 142 0x8E '\216' */ + 0x44, /* 010001 */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 143 0x8F '\217' */ + 0x30, /* 001100 */ + 0x48, /* 010010 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 144 0x90 '\220' */ + 0x10, /* 000100 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x78, /* 011110 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 145 0x91 '\221' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x78, /* 011110 */ + 0x14, /* 000101 */ + 0x7C, /* 011111 */ + 0x50, /* 010100 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 146 0x92 '\222' */ + 0x3C, /* 001111 */ + 0x50, /* 010100 */ + 0x50, /* 010100 */ + 0x78, /* 011110 */ + 0x50, /* 010100 */ + 0x50, /* 010100 */ + 0x5C, /* 010111 */ + 0x00, /* 000000 */ + + /* 147 0x93 '\223' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 148 0x94 '\224' */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 149 0x95 '\225' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 150 0x96 '\226' */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 151 0x97 '\227' */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 152 0x98 '\230' */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x04, /* 000001 */ + 0x38, /* 001110 */ + + /* 153 0x99 '\231' */ + 0x84, /* 100001 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 154 0x9A '\232' */ + 0x88, /* 100010 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 155 0x9B '\233' */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x50, /* 010100 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 156 0x9C '\234' */ + 0x30, /* 001100 */ + 0x48, /* 010010 */ + 0x40, /* 010000 */ + 0x70, /* 011100 */ + 0x40, /* 010000 */ + 0x44, /* 010001 */ + 0x78, /* 011110 */ + 0x00, /* 000000 */ + + /* 157 0x9D '\235' */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 158 0x9E '\236' */ + 0x70, /* 011100 */ + 0x48, /* 010010 */ + 0x70, /* 011100 */ + 0x48, /* 010010 */ + 0x5C, /* 010111 */ + 0x48, /* 010010 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 159 0x9F '\237' */ + 0x0C, /* 000011 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x60, /* 011000 */ + 0x00, /* 000000 */ + + /* 160 0xA0 '\240' */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 161 0xA1 '\241' */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x30, /* 001100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 162 0xA2 '\242' */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 163 0xA3 '\243' */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x4C, /* 010011 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 164 0xA4 '\244' */ + 0x34, /* 001101 */ + 0x58, /* 010110 */ + 0x00, /* 000000 */ + 0x58, /* 010110 */ + 0x64, /* 011001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 165 0xA5 '\245' */ + 0x58, /* 010110 */ + 0x44, /* 010001 */ + 0x64, /* 011001 */ + 0x54, /* 010101 */ + 0x4C, /* 010011 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 166 0xA6 '\246' */ + 0x38, /* 001110 */ + 0x04, /* 000001 */ + 0x3C, /* 001111 */ + 0x44, /* 010001 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 167 0xA7 '\247' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 168 0xA8 '\250' */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x40, /* 010000 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 169 0xA9 '\251' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 170 0xAA '\252' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x04, /* 000001 */ + 0x04, /* 000001 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 171 0xAB '\253' */ + 0x20, /* 001000 */ + 0x24, /* 001001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x44, /* 010001 */ + 0x08, /* 000010 */ + 0x1C, /* 000111 */ + + /* 172 0xAC '\254' */ + 0x20, /* 001000 */ + 0x24, /* 001001 */ + 0x28, /* 001010 */ + 0x10, /* 000100 */ + 0x28, /* 001010 */ + 0x58, /* 010110 */ + 0x3C, /* 001111 */ + 0x08, /* 000010 */ + + /* 173 0xAD '\255' */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + + /* 174 0xAE '\256' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x24, /* 001001 */ + 0x48, /* 010010 */ + 0x90, /* 100100 */ + 0x48, /* 010010 */ + 0x24, /* 001001 */ + 0x00, /* 000000 */ + + /* 175 0xAF '\257' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x90, /* 100100 */ + 0x48, /* 010010 */ + 0x24, /* 001001 */ + 0x48, /* 010010 */ + 0x90, /* 100100 */ + 0x00, /* 000000 */ + + /* 176 0xB0 '\260' */ + 0x10, /* 000100 */ + 0x44, /* 010001 */ + 0x10, /* 000100 */ + 0x44, /* 010001 */ + 0x10, /* 000100 */ + 0x44, /* 010001 */ + 0x10, /* 000100 */ + 0x44, /* 010001 */ + + /* 177 0xB1 '\261' */ + 0xA8, /* 101010 */ + 0x54, /* 010101 */ + 0xA8, /* 101010 */ + 0x54, /* 010101 */ + 0xA8, /* 101010 */ + 0x54, /* 010101 */ + 0xA8, /* 101010 */ + 0x54, /* 010101 */ + + /* 178 0xB2 '\262' */ + 0xDC, /* 110111 */ + 0x74, /* 011101 */ + 0xDC, /* 110111 */ + 0x74, /* 011101 */ + 0xDC, /* 110111 */ + 0x74, /* 011101 */ + 0xDC, /* 110111 */ + 0x74, /* 011101 */ + + /* 179 0xB3 '\263' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 180 0xB4 '\264' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 181 0xB5 '\265' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 182 0xB6 '\266' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xE8, /* 111010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 183 0xB7 '\267' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xF8, /* 111110 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 184 0xB8 '\270' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 185 0xB9 '\271' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xE8, /* 111010 */ + 0x08, /* 000010 */ + 0xE8, /* 111010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 186 0xBA '\272' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 187 0xBB '\273' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xF8, /* 111110 */ + 0x08, /* 000010 */ + 0xE8, /* 111010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 188 0xBC '\274' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xE8, /* 111010 */ + 0x08, /* 000010 */ + 0xF8, /* 111110 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 189 0xBD '\275' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xF8, /* 111110 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 190 0xBE '\276' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 191 0xBF '\277' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xF0, /* 111100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 192 0xC0 '\300' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 193 0xC1 '\301' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 194 0xC2 '\302' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 195 0xC3 '\303' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 196 0xC4 '\304' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 197 0xC5 '\305' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xFC, /* 111111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 198 0xC6 '\306' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 199 0xC7 '\307' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x2C, /* 001011 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 200 0xC8 '\310' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x2C, /* 001011 */ + 0x20, /* 001000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 201 0xC9 '\311' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x3C, /* 001111 */ + 0x20, /* 001000 */ + 0x2C, /* 001011 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 202 0xCA '\312' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xEC, /* 111011 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 203 0xCB '\313' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0xEC, /* 111011 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 204 0xCC '\314' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x2C, /* 001011 */ + 0x20, /* 001000 */ + 0x2C, /* 001011 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 205 0xCD '\315' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 206 0xCE '\316' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xEC, /* 111011 */ + 0x00, /* 000000 */ + 0xEC, /* 111011 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 207 0xCF '\317' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 208 0xD0 '\320' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 209 0xD1 '\321' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 210 0xD2 '\322' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 211 0xD3 '\323' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 212 0xD4 '\324' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 213 0xD5 '\325' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 214 0xD6 '\326' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x3C, /* 001111 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 215 0xD7 '\327' */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0xFC, /* 111111 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + + /* 216 0xD8 '\330' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xFC, /* 111111 */ + 0x10, /* 000100 */ + 0xFC, /* 111111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 217 0xD9 '\331' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0xF0, /* 111100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 218 0xDA '\332' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x1C, /* 000111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 219 0xDB '\333' */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + + /* 220 0xDC '\334' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + + /* 221 0xDD '\335' */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + 0xE0, /* 111000 */ + + /* 222 0xDE '\336' */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + 0x1C, /* 000111 */ + + /* 223 0xDF '\337' */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 224 0xE0 '\340' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x34, /* 001101 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x34, /* 001101 */ + 0x00, /* 000000 */ + + /* 225 0xE1 '\341' */ + 0x24, /* 001001 */ + 0x44, /* 010001 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x58, /* 010110 */ + 0x40, /* 010000 */ + + /* 226 0xE2 '\342' */ + 0x7C, /* 011111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + + /* 227 0xE3 '\343' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x28, /* 001010 */ + 0x00, /* 000000 */ + + /* 228 0xE4 '\344' */ + 0x7C, /* 011111 */ + 0x24, /* 001001 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x24, /* 001001 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 229 0xE5 '\345' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x3C, /* 001111 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + + /* 230 0xE6 '\346' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x74, /* 011101 */ + 0x40, /* 010000 */ + + /* 231 0xE7 '\347' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x0C, /* 000011 */ + 0x00, /* 000000 */ + + /* 232 0xE8 '\350' */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 233 0xE9 '\351' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x7C, /* 011111 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 234 0xEA '\352' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x28, /* 001010 */ + 0x6C, /* 011011 */ + 0x00, /* 000000 */ + + /* 235 0xEB '\353' */ + 0x18, /* 000110 */ + 0x20, /* 001000 */ + 0x18, /* 000110 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x24, /* 001001 */ + 0x18, /* 000110 */ + 0x00, /* 000000 */ + + /* 236 0xEC '\354' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 237 0xED '\355' */ + 0x00, /* 000000 */ + 0x04, /* 000001 */ + 0x38, /* 001110 */ + 0x54, /* 010101 */ + 0x54, /* 010101 */ + 0x38, /* 001110 */ + 0x40, /* 010000 */ + 0x00, /* 000000 */ + + /* 238 0xEE '\356' */ + 0x3C, /* 001111 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x38, /* 001110 */ + 0x40, /* 010000 */ + 0x40, /* 010000 */ + 0x3C, /* 001111 */ + 0x00, /* 000000 */ + + /* 239 0xEF '\357' */ + 0x38, /* 001110 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x44, /* 010001 */ + 0x00, /* 000000 */ + + /* 240 0xF0 '\360' */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0xFC, /* 111111 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 241 0xF1 '\361' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x7C, /* 011111 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + + /* 242 0xF2 '\362' */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 243 0xF3 '\363' */ + 0x08, /* 000010 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x10, /* 000100 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 244 0xF4 '\364' */ + 0x0C, /* 000011 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + + /* 245 0xF5 '\365' */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x10, /* 000100 */ + 0x60, /* 011000 */ + + /* 246 0xF6 '\366' */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x7C, /* 011111 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 247 0xF7 '\367' */ + 0x00, /* 000000 */ + 0x20, /* 001000 */ + 0x54, /* 010101 */ + 0x08, /* 000010 */ + 0x20, /* 001000 */ + 0x54, /* 010101 */ + 0x08, /* 000010 */ + 0x00, /* 000000 */ + + /* 248 0xF8 '\370' */ + 0x30, /* 001100 */ + 0x48, /* 010010 */ + 0x48, /* 010010 */ + 0x30, /* 001100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 249 0xF9 '\371' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x38, /* 001110 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 250 0xFA '\372' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x10, /* 000100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 251 0xFB '\373' */ + 0x04, /* 000001 */ + 0x08, /* 000010 */ + 0x08, /* 000010 */ + 0x50, /* 010100 */ + 0x50, /* 010100 */ + 0x20, /* 001000 */ + 0x20, /* 001000 */ + 0x00, /* 000000 */ + + /* 252 0xFC '\374' */ + 0x60, /* 011000 */ + 0x50, /* 010100 */ + 0x50, /* 010100 */ + 0x50, /* 010100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 253 0xFD '\375' */ + 0x60, /* 011000 */ + 0x10, /* 000100 */ + 0x20, /* 001000 */ + 0x70, /* 011100 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + + /* 254 0xFE '\376' */ + 0x00, /* 000000 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x38, /* 001110 */ + 0x00, /* 000000 */ + + /* 255 0xFF '\377' */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ + 0x00, /* 000000 */ +}; + +#endif /* _VIDEO_FONT_6X8_ */ + -- cgit v1.3.1 From 9c04852e59699a1653bffad40044eb87387950a5 Mon Sep 17 00:00:00 2001 From: Francois Berder Date: Tue, 19 May 2026 11:41:54 +0200 Subject: timer: sp804: Fix dev_read_addr error check dev_read_addr returns FDT_ADDR_T_NONE (-1) in case of error and not 0. Signed-off-by: Francois Berder --- drivers/timer/sp804_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/timer/sp804_timer.c b/drivers/timer/sp804_timer.c index 05532e3330c..d1a5fc8c5bf 100644 --- a/drivers/timer/sp804_timer.c +++ b/drivers/timer/sp804_timer.c @@ -44,7 +44,7 @@ static int sp804_clk_of_to_plat(struct udevice *dev) struct sp804_timer_plat *plat = dev_get_plat(dev); plat->base = dev_read_addr(dev); - if (!plat->base) + if (plat->base == FDT_ADDR_T_NONE) return -ENOENT; return 0; -- cgit v1.3.1 From d86b3a753fee2068ab59c7c9be3e973b26de535d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:16:31 +0200 Subject: usb: dwc3: am62: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Mattijs Korpershoek --- drivers/usb/dwc3/dwc3-am62.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/dwc3/dwc3-am62.c b/drivers/usb/dwc3/dwc3-am62.c index 99519602eb2..8cb5796b6ad 100644 --- a/drivers/usb/dwc3/dwc3-am62.c +++ b/drivers/usb/dwc3/dwc3-am62.c @@ -105,7 +105,7 @@ static void dwc3_ti_am62_glue_configure(struct udevice *dev, int index, writel(reg, usbss + USBSS_MODE_CONTROL); } -struct dwc3_glue_ops ti_am62_ops = { +static const struct dwc3_glue_ops ti_am62_ops = { .glue_configure = dwc3_ti_am62_glue_configure, }; -- cgit v1.3.1 From f0dccb21eb6ea81883089ca2c063932762267a88 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:16:32 +0200 Subject: usb: dwc3: sti: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Mattijs Korpershoek --- drivers/usb/dwc3/dwc3-generic-sti.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/dwc3/dwc3-generic-sti.c b/drivers/usb/dwc3/dwc3-generic-sti.c index b34f5ceceac..ce195b2553b 100644 --- a/drivers/usb/dwc3/dwc3-generic-sti.c +++ b/drivers/usb/dwc3/dwc3-generic-sti.c @@ -114,7 +114,7 @@ static void dwc3_stih407_glue_configure(struct udevice *dev, int index, setbits_le32(glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N); }; -struct dwc3_glue_ops stih407_ops = { +static const struct dwc3_glue_ops stih407_ops = { .glue_configure = dwc3_stih407_glue_configure, }; -- cgit v1.3.1 From 2e9e8915616b1b323aac37c2073964d7d112e06d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 10 May 2026 19:16:33 +0200 Subject: usb: dwc3: generic: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Mattijs Korpershoek --- drivers/usb/dwc3/dwc3-generic.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 22b9ef0b24e..2356b3bc0aa 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -330,7 +330,7 @@ void dwc3_imx8mp_glue_configure(struct udevice *dev, int index, unmap_physmem(base, MAP_NOCACHE); } -struct dwc3_glue_ops imx8mp_ops = { +static const struct dwc3_glue_ops imx8mp_ops = { .glue_configure = dwc3_imx8mp_glue_configure, }; @@ -414,7 +414,7 @@ enum dwc3_omap_utmi_mode { unmap_physmem(base, MAP_NOCACHE); } -struct dwc3_glue_ops ti_ops = { +static const struct dwc3_glue_ops ti_ops = { .glue_configure = dwc3_ti_glue_configure, }; @@ -506,16 +506,16 @@ static int dwc3_flat_dt_get_ctrl_dev(struct udevice *dev, ofnode *node) return 0; } -struct dwc3_glue_ops qcom_ops = { +static const struct dwc3_glue_ops qcom_ops = { .glue_configure = dwc3_qcom_glue_configure, }; -struct dwc3_glue_ops qcom_flat_dt_ops = { +static const struct dwc3_glue_ops qcom_flat_dt_ops = { .glue_configure = dwc3_qcom_glue_configure, .glue_get_ctrl_dev = dwc3_flat_dt_get_ctrl_dev, }; -struct dwc3_glue_ops rk_ops = { +static const struct dwc3_glue_ops rk_ops = { .glue_get_ctrl_dev = dwc3_flat_dt_get_ctrl_dev, }; -- cgit v1.3.1 From 987b5eabc35f3924fd10c66bb1be64a60c6feb23 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 7 May 2026 12:37:10 +0200 Subject: net: tsec: make tsec_private a private structure Move the definition of tsec_private within the only file that makes use of it. This adds the benefit of include/tsec.h not referencing PKTBUFSRX (which is set to CONFIG_SYS_RX_ETH_BUFFER, which we're trying to move to be under CONFIG_NET dependency) anymore. Considering drivers/net/tsec.c is only built if CONFIG_NET=y, this is fine. Reviewed-by: Simon Glass Signed-off-by: Quentin Schulz --- drivers/net/tsec.c | 17 +++++++++++++++++ include/tsec.h | 17 ----------------- 2 files changed, 17 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index bd4ebdd745a..d03368b9408 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -37,6 +37,23 @@ ) #endif /* CFG_TSEC_TBICR_SETTINGS */ +struct tsec_private { + struct txbd8 __iomem txbd[TX_BUF_CNT]; + struct rxbd8 __iomem rxbd[PKTBUFSRX]; + struct tsec __iomem *regs; + struct tsec_mii_mng __iomem *phyregs_sgmii; + struct phy_device *phydev; + phy_interface_t interface; + struct mii_dev *bus; + uint phyaddr; + uint tbiaddr; + char mii_devname[16]; + u32 flags; + uint rx_idx; /* index of the current RX buffer */ + uint tx_idx; /* index of the current TX buffer */ + struct udevice *dev; +}; + /* Configure the TBI for SGMII operation */ static void tsec_configure_serdes(struct tsec_private *priv) { diff --git a/include/tsec.h b/include/tsec.h index 153337837a9..f5ced38f3fc 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -350,23 +350,6 @@ struct tsec_data { u32 mdio_regs_off; }; -struct tsec_private { - struct txbd8 __iomem txbd[TX_BUF_CNT]; - struct rxbd8 __iomem rxbd[PKTBUFSRX]; - struct tsec __iomem *regs; - struct tsec_mii_mng __iomem *phyregs_sgmii; - struct phy_device *phydev; - phy_interface_t interface; - struct mii_dev *bus; - uint phyaddr; - uint tbiaddr; - char mii_devname[16]; - u32 flags; - uint rx_idx; /* index of the current RX buffer */ - uint tx_idx; /* index of the current TX buffer */ - struct udevice *dev; -}; - struct tsec_info_struct { struct tsec __iomem *regs; struct tsec_mii_mng __iomem *miiregs_sgmii; -- cgit v1.3.1 From 3518bf17ba4435067bd5c7b3eb7148e7182fe6b1 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 13 May 2026 09:11:52 -0500 Subject: phy: Kconfig: use bool instead of tristate Change all uses of tristate in the PHY Kconfigs to bool. U-Boot does not support modules, so tristate does not make sense here. Signed-off-by: David Lechner Reviewed-by: Tom Rini Reviewed-by: Quentin Schulz Reviewed-by: Macpaul Lin Reviewed-by: Anshul Dalal Reviewed-by: Casey Connolly --- drivers/phy/Kconfig | 14 +++++++------- drivers/phy/cadence/Kconfig | 4 ++-- drivers/phy/qcom/Kconfig | 16 ++++++++-------- drivers/phy/renesas/Kconfig | 6 +++--- drivers/phy/rockchip/Kconfig | 2 +- drivers/phy/ti/Kconfig | 2 +- 6 files changed, 22 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 5c8ec2b146f..eafa82fe494 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -114,7 +114,7 @@ config BCM_SR_PCIE_PHY If unsure, say N. config PHY_DA8XX_USB - tristate "TI DA8xx USB PHY Driver" + bool "TI DA8xx USB PHY Driver" depends on PHY && ARCH_DAVINCI help Enable this to support the USB PHY on DA8xx SoCs. @@ -138,7 +138,7 @@ config SPL_PIPE3_PHY and omap5 config AM654_PHY - tristate "TI AM654 SERDES support" + bool "TI AM654 SERDES support" depends on PHY && ARCH_K3 select REGMAP select SYSCON @@ -155,7 +155,7 @@ config STI_USB_PHY STiH407 SoC families. config PHY_RCAR_GEN2 - tristate "Renesas R-Car Gen2 USB PHY" + bool "Renesas R-Car Gen2 USB PHY" depends on PHY && RCAR_GEN2 help Support for the Renesas R-Car Gen2 USB PHY. This driver operates the @@ -163,7 +163,7 @@ config PHY_RCAR_GEN2 allows configuring the module multiplexing. config PHY_RCAR_GEN3 - tristate "Renesas R-Car Gen3 USB PHY" + bool "Renesas R-Car Gen3 USB PHY" depends on PHY && CLK && DM_REGULATOR && (RCAR_GEN3 || RZG2L) default y if (RCAR_GEN3 || RZG2L) help @@ -171,7 +171,7 @@ config PHY_RCAR_GEN3 PHY connected to EHCI USB module and controls USB OTG operation. config PHY_STM32_USBPHYC - tristate "STMicroelectronics STM32 SoC USB HS PHY driver" + bool "STMicroelectronics STM32 SoC USB HS PHY driver" depends on PHY && ARCH_STM32MP help Enable this to support the High-Speed USB transceiver that is part of @@ -283,7 +283,7 @@ config PHY_MTK_TPHY so you can easily distinguish them by banks layout. config PHY_MTK_UFS - tristate "MediaTek UFS M-PHY driver" + bool "MediaTek UFS M-PHY driver" depends on ARCH_MEDIATEK depends on PHY help @@ -337,7 +337,7 @@ config PHY_IMX8M_PCIE This PHY is found on i.MX8M devices supporting PCIe. config PHY_XILINX_ZYNQMP - tristate "Xilinx ZynqMP PHY driver" + bool "Xilinx ZynqMP PHY driver" depends on PHY && ARCH_ZYNQMP help Enable this to support ZynqMP High Speed Gigabit Transceiver diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 8c0ab80fbbc..f5f096889fe 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -1,11 +1,11 @@ config PHY_CADENCE_SIERRA - tristate "Cadence Sierra PHY Driver" + bool "Cadence Sierra PHY Driver" depends on DM_RESET help Enable this to support the Cadence Sierra PHY driver config PHY_CADENCE_TORRENT - tristate "Cadence Torrent PHY Driver" + bool "Cadence Torrent PHY Driver" depends on DM_RESET help Enable this to support the Cadence Torrent PHY driver diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index 49f830abf01..7094903d869 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -7,7 +7,7 @@ config MSM8916_USB_PHY This PHY is found on qualcomm dragonboard410c development board. config PHY_QCOM_IPQ4019_USB - tristate "Qualcomm IPQ4019 USB PHY driver" + bool "Qualcomm IPQ4019 USB PHY driver" depends on PHY && ARCH_IPQ40XX help Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. @@ -21,26 +21,26 @@ config PHY_QCOM_QMP_COMBO PHY (USB3 + DisplayPort). Currently only USB3 mode is supported. config PHY_QCOM_QMP_PCIE - tristate "Qualcomm QMP PCIe PHY driver" + bool "Qualcomm QMP PCIe PHY driver" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the PCIe QMP PHY on various Qualcomm chipsets. config PHY_QCOM_QMP_UFS - tristate "Qualcomm QMP UFS PHY driver" + bool "Qualcomm QMP UFS PHY driver" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the UFS QMP PHY on various Qualcomm chipsets. config PHY_QCOM_QUSB2 - tristate "Qualcomm USB QUSB2 PHY driver" + bool "Qualcomm USB QUSB2 PHY driver" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the Super-Speed USB transceiver on various Qualcomm chipsets. config PHY_QCOM_USB_SNPS_FEMTO_V2 - tristate "Qualcomm SNPS FEMTO USB HS PHY v2" + bool "Qualcomm SNPS FEMTO USB HS PHY v2" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the Qualcomm Synopsys DesignWare Core 7nm @@ -48,7 +48,7 @@ config PHY_QCOM_USB_SNPS_FEMTO_V2 is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. config PHY_QCOM_SNPS_EUSB2 - tristate "Qualcomm Synopsys eUSB2 High-Speed PHY" + bool "Qualcomm Synopsys eUSB2 High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the Qualcomm Synopsys DesignWare eUSB2 @@ -56,7 +56,7 @@ config PHY_QCOM_SNPS_EUSB2 is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. config PHY_QCOM_USB_HS_28NM - tristate "Qualcomm 28nm High-Speed PHY" + bool "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the Qualcomm Synopsys DesignWare Core 28nm @@ -65,7 +65,7 @@ config PHY_QCOM_USB_HS_28NM IPs on MSM SOCs. config PHY_QCOM_USB_SS - tristate "Qualcomm USB Super-Speed PHY driver" + bool "Qualcomm USB Super-Speed PHY driver" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the Super-Speed USB transceiver on various diff --git a/drivers/phy/renesas/Kconfig b/drivers/phy/renesas/Kconfig index affbee0500c..3358d454e59 100644 --- a/drivers/phy/renesas/Kconfig +++ b/drivers/phy/renesas/Kconfig @@ -3,19 +3,19 @@ # Phy drivers for Renesas platforms config PHY_R8A779F0_ETHERNET_SERDES - tristate "Renesas R-Car S4-8 Ethernet SERDES driver" + bool "Renesas R-Car S4-8 Ethernet SERDES driver" depends on RCAR_64 && PHY help Support for Ethernet SERDES found on Renesas R-Car S4-8 SoCs. config PHY_R8A78000_ETHERNET_PCS - tristate "Renesas R-Car X5H Ethernet PCS driver" + bool "Renesas R-Car X5H Ethernet PCS driver" depends on RCAR_64 && PHY help Support for Ethernet PCS found on Renesas R-Car X5H SoCs. config PHY_R8A78000_MP_PHY - tristate "Renesas R-Car X5H Multi-Protocol PHY driver" + bool "Renesas R-Car X5H Multi-Protocol PHY driver" depends on RCAR_64 && PHY help Support for Multi-Protocol PHY on Renesas R-Car X5H SoCs. diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 80128335d52..6f3d7ebe29e 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -49,7 +49,7 @@ config PHY_ROCKCHIP_SNPS_PCIE3 also be able splited into multiple combinations of lanes. config PHY_ROCKCHIP_USBDP - tristate "Rockchip USBDP COMBO PHY Driver" + bool "Rockchip USBDP COMBO PHY Driver" depends on ARCH_ROCKCHIP select PHY help diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig index df750b26d66..fe96eb6806f 100644 --- a/drivers/phy/ti/Kconfig +++ b/drivers/phy/ti/Kconfig @@ -1,5 +1,5 @@ config PHY_J721E_WIZ - tristate "TI J721E WIZ (SERDES Wrapper) support" + bool "TI J721E WIZ (SERDES Wrapper) support" depends on ARCH_K3 help This option enables support for WIZ module present in TI's J721E -- cgit v1.3.1 From 6184a9b10670efac4348735064712aa0e12fdf83 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 14:39:14 +0800 Subject: phy: ti-pipe3: Use device API for DT parsing Replace legacy FDT parsing in get_reg() with the device API dev_read_phandle_with_args() which removes direct access to gd->fdt_blob and aligns the driver with modern U-Boot DT handling. The offset is retrieved from the phandle argument instead of manually parsing the property cells. Add validation for the argument count to avoid out-of-bounds access on malformed DTs. Also switch from devfdt_get_addr_size_index() to dev_read_addr_size_index() for consistency with the DM API. No functional changes. Signed-off-by: Peng Fan Reviewed-by: Stefan Roese --- drivers/phy/ti-pipe3-phy.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c index 62f6cc2bfbf..080016ba417 100644 --- a/drivers/phy/ti-pipe3-phy.c +++ b/drivers/phy/ti-pipe3-phy.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -428,10 +429,10 @@ static int pipe3_exit(struct phy *phy) static void *get_reg(struct udevice *dev, const char *name) { + struct ofnode_phandle_args phandle; struct udevice *syscon; struct regmap *regmap; - const fdt32_t *cell; - int len, err; + int err; void *base; err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, @@ -449,10 +450,14 @@ static void *get_reg(struct udevice *dev, const char *name) return NULL; } - cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name, - &len); - if (len < 2*sizeof(fdt32_t)) { - pr_err("offset not available for %s\n", name); + err = dev_read_phandle_with_args(dev, name, NULL, 0, 0, &phandle); + if (err) { + dev_err(dev, "parse %s failed: %d\n", name, err); + return NULL; + } + + if (phandle.args_count < 1) { + dev_err(dev, "%s: missing args\n", name); return NULL; } @@ -460,7 +465,7 @@ static void *get_reg(struct udevice *dev, const char *name) if (!base) return NULL; - return fdtdec_get_number(cell + 1, 1) + base; + return base + phandle.args[0]; } static int pipe3_phy_probe(struct udevice *dev) @@ -471,7 +476,7 @@ static int pipe3_phy_probe(struct udevice *dev) struct pipe3_data *data; /* PHY_RX */ - addr = devfdt_get_addr_size_index(dev, 0, &sz); + addr = dev_read_addr_size_index(dev, 0, &sz); if (addr == FDT_ADDR_T_NONE) { pr_err("missing phy_rx address\n"); return -EINVAL; @@ -484,7 +489,7 @@ static int pipe3_phy_probe(struct udevice *dev) } /* PLLCTRL */ - addr = devfdt_get_addr_size_index(dev, 2, &sz); + addr = dev_read_addr_size_index(dev, 2, &sz); if (addr == FDT_ADDR_T_NONE) { pr_err("missing pll ctrl address\n"); return -EINVAL; -- cgit v1.3.1 From dde8b3b7e10deea87eed70a6a9078b4d4cbae860 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 14:39:15 +0800 Subject: phy: marvell: comphy: Use dev_read_addr_index_ptr() Use dev_read_addr_index_ptr() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index b074d58f9f6..0ab5f9a3f0a 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -84,11 +84,11 @@ static int comphy_probe(struct udevice *dev) int res; /* Save base addresses for later use */ - chip_cfg->comphy_base_addr = devfdt_get_addr_index_ptr(dev, 0); + chip_cfg->comphy_base_addr = dev_read_addr_index_ptr(dev, 0); if (!chip_cfg->comphy_base_addr) return -EINVAL; - chip_cfg->hpipe3_base_addr = devfdt_get_addr_index_ptr(dev, 1); + chip_cfg->hpipe3_base_addr = dev_read_addr_index_ptr(dev, 1); if (!chip_cfg->hpipe3_base_addr) return -EINVAL; -- cgit v1.3.1 From b9469df60e17fb1168ba0f617b7bb16824951ac3 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 14:39:16 +0800 Subject: phy: cadence: Use device API Use dev_remap_addr_index() and dev_read_addr_size_index() which support both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan Reviewed-by: Stefan Roese --- drivers/phy/cadence/phy-cadence-sierra.c | 4 ++-- drivers/phy/cadence/phy-cadence-torrent.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index bd7ab9d1b77..9f8a6d8d43d 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -1068,12 +1068,12 @@ static int cdns_sierra_phy_probe(struct udevice *dev) sp->dev = dev; - sp->base = devfdt_remap_addr_index(dev, 0); + sp->base = dev_remap_addr_index(dev, 0); if (!sp->base) { dev_err(dev, "unable to map regs\n"); return -ENOMEM; } - devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&sp->size); + dev_read_addr_size_index(dev, 0, (fdt_size_t *)&sp->size); /* Get init data for this PHY */ data = (struct cdns_sierra_data *)dev_get_driver_data(dev); diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 933533b2b0b..814aff15070 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -791,10 +791,10 @@ static int cdns_torrent_phy_probe(struct udevice *dev) return ret; } - cdns_phy->sd_base = devfdt_remap_addr_index(dev, 0); - if (IS_ERR(cdns_phy->sd_base)) - return PTR_ERR(cdns_phy->sd_base); - devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&cdns_phy->size); + cdns_phy->sd_base = dev_remap_addr_index(dev, 0); + if (!cdns_phy->sd_base) + return -EINVAL; + dev_read_addr_size_index(dev, 0, (fdt_size_t *)&cdns_phy->size); dev_for_each_subnode(child, dev) subnodes++; -- cgit v1.3.1 From 45e5625d71e977cef0157240c6ce6298888afb10 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 May 2026 16:00:19 +0800 Subject: net: ethoc: Use dev_read_addr_index() Use dev_read_addr_index() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Reviewed-by: Simon Glass Signed-off-by: Peng Fan --- drivers/net/ethoc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index dc7e6f1929f..87b2b3426c8 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -686,7 +686,7 @@ static int ethoc_of_to_plat(struct udevice *dev) fdt_addr_t addr; pdata->eth_pdata.iobase = dev_read_addr(dev); - addr = devfdt_get_addr_index(dev, 1); + addr = dev_read_addr_index(dev, 1); if (addr != FDT_ADDR_T_NONE) pdata->packet_base = addr; return 0; -- cgit v1.3.1 From c174c1f7f12b5951de657c3f9a7350f8733bf15e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 May 2026 16:00:20 +0800 Subject: net: qe: dm_qe_uec: Use dev_read_addr() Use dev_read_addr() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Reviewed-by: Simon Glass Signed-off-by: Peng Fan Reviewed-by: Heiko Schocher --- drivers/net/qe/dm_qe_uec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/qe/dm_qe_uec.c b/drivers/net/qe/dm_qe_uec.c index ac3aedd8b49..f9bc5d49c8f 100644 --- a/drivers/net/qe/dm_qe_uec.c +++ b/drivers/net/qe/dm_qe_uec.c @@ -1133,7 +1133,7 @@ static int qe_uec_of_to_plat(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); - pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); + pdata->iobase = (phys_addr_t)dev_read_addr(dev); pdata->phy_interface = dev_read_phy_mode(dev); if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) -- cgit v1.3.1 From 0e2ba59bc5a825d494e83028bdd87c40014989b3 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 May 2026 16:00:21 +0800 Subject: net: calxedaxgmac: Use dev_read_addr() Use dev_read_addr() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Reviewed-by: Simon Glass Signed-off-by: Peng Fan --- drivers/net/calxedaxgmac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index 92990fa6d47..df0ed820e06 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -555,7 +555,7 @@ static int xgmac_ofdata_to_platdata(struct udevice *dev) return -ENOMEM; dev_set_priv(dev, priv); - pdata->iobase = devfdt_get_addr(dev); + pdata->iobase = dev_read_addr(dev); if (pdata->iobase == FDT_ADDR_T_NONE) { printf("%s: Cannot find XGMAC base address\n", __func__); return -EINVAL; -- cgit v1.3.1 From 23532fcb7d080eb19c87b3a1e8f459560792a042 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 May 2026 16:00:22 +0800 Subject: net: dc2114x: Use dev_remap_addr() Use dev_remap_addr() to simplify code. dev_remap_addr() does same thing as dev_read_addr() + map_physmem(). And it supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Reviewed-by: Simon Glass Signed-off-by: Peng Fan --- drivers/net/dc2114x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 8fa549280aa..2a21eceac57 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -653,7 +653,7 @@ static int dc2114x_of_to_plat(struct udevice *dev) struct eth_pdata *plat = dev_get_plat(dev); struct dc2114x_priv *priv = dev_get_priv(dev); - plat->iobase = (phys_addr_t)map_physmem((phys_addr_t)devfdt_get_addr(dev), 0, MAP_NOCACHE); + plat->iobase = (phys_addr_t)dev_remap_addr(dev); priv->iobase = (void *)plat->iobase; return 0; -- cgit v1.3.1 From f603d10d72bf6a341b2af238693f17e671e4bc07 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 May 2026 16:00:23 +0800 Subject: net: mvpp2: Use dev_read_addr_index_ptr() Use dev_read_addr_index_ptr() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Reviewed-by: Simon Glass Signed-off-by: Peng Fan --- drivers/net/mvpp2.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index f9e979c4d58..193f82ea07d 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -5296,16 +5296,16 @@ static int mvpp2_base_probe(struct udevice *dev) } /* Save base addresses for later use */ - priv->base = devfdt_get_addr_index_ptr(dev, 0); + priv->base = dev_read_addr_index_ptr(dev, 0); if (!priv->base) return -EINVAL; if (priv->hw_version == MVPP21) { - priv->lms_base = devfdt_get_addr_index_ptr(dev, 1); + priv->lms_base = dev_read_addr_index_ptr(dev, 1); if (!priv->lms_base) return -EINVAL; } else { - priv->iface_base = devfdt_get_addr_index_ptr(dev, 1); + priv->iface_base = dev_read_addr_index_ptr(dev, 1); if (!priv->iface_base) return -EINVAL; @@ -5346,8 +5346,7 @@ static int mvpp2_probe(struct udevice *dev) if (priv->hw_version == MVPP21) { int priv_common_regs_num = 2; - port->base = devfdt_get_addr_index_ptr( - dev->parent, priv_common_regs_num + port->id); + port->base = dev_read_addr_index_ptr(dev->parent, priv_common_regs_num + port->id); if (!port->base) return -EINVAL; } else { -- cgit v1.3.1 From dafa6a36037b516bed3c4f578c69e0c5c8017acb Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 May 2026 16:00:24 +0800 Subject: net: mvpp2: convert FDT access to ofnode API Convert mvpp2 driver from legacy fdtdec/fdt_* APIs to the ofnode-based interfaces. Replace usage of dev_of_offset(), fdtdec_lookup_phandle(), fdtdec_get_int(), fdt_parent_offset(), and related helpers with their ofnode equivalents, including dev_ofnode(), ofnode_parse_phandle(), ofnode_read_s32_default(), ofnode_get_parent(), and ofnode_for_each_subnode(). Remove direct dependencies on gd->fdt_blob. Main changes: - Use ofnode_valid() instead of integer checks for node presence - Switch fixed-link detection to ofnode_find_subnode() - Replace uclass_get_device_by_of_offset() with uclass_get_device_by_ofnode() - Update subnode iteration and device binding to use ofnode No functional changes. Reviewed-by: Simon Glass Signed-off-by: Peng Fan --- drivers/net/mvpp2.c | 47 +++++++++++++++++++++-------------------------- 1 file changed, 21 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 193f82ea07d..fc137df14c4 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4731,33 +4731,32 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) { - int port_node = dev_of_offset(dev); - int phy_node; + ofnode port_node = dev_ofnode(dev); + ofnode phy_node; u32 id; int phyaddr = 0; - int fixed_link = 0; + ofnode fixed_link; int ret; - phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy"); - fixed_link = fdt_subnode_offset(gd->fdt_blob, port_node, "fixed-link"); + phy_node = ofnode_parse_phandle(port_node, "phy", 0); + fixed_link = ofnode_find_subnode(port_node, "fixed-link"); - if (phy_node > 0) { - int parent; + if (ofnode_valid(phy_node)) { + ofnode parent; - if (fixed_link != -FDT_ERR_NOTFOUND) { + if (ofnode_valid(fixed_link)) { /* phy_addr is set to invalid value for fixed links */ phyaddr = PHY_MAX_ADDR; } else { - phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, - "reg", 0); + phyaddr = ofnode_read_s32_default(phy_node, "reg", 0); if (phyaddr < 0) { dev_err(dev, "could not find phy address\n"); return -1; } } - parent = fdt_parent_offset(gd->fdt_blob, phy_node); - ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent, - &port->mdio_dev); + parent = ofnode_get_parent(phy_node); + ret = uclass_get_device_by_ofnode(UCLASS_MDIO, parent, + &port->mdio_dev); if (ret) return ret; } else { @@ -4771,7 +4770,7 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) return -EINVAL; } - id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1); + id = dev_read_s32_default(dev, "port-id", -1); if (id == -1) { dev_err(dev, "missing port-id value\n"); return -EINVAL; @@ -4812,7 +4811,7 @@ static void mvpp2_gpio_init(struct mvpp2_port *port) /* Ports initialization */ static int mvpp2_port_probe(struct udevice *dev, struct mvpp2_port *port, - int port_node, + ofnode port_node, struct mvpp2 *priv) { int err; @@ -5350,8 +5349,7 @@ static int mvpp2_probe(struct udevice *dev) if (!port->base) return -EINVAL; } else { - port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "gop-port-id", -1); + port->gop_id = ofnode_read_s32_default(dev_ofnode(dev), "gop-port-id", -1); if (port->gop_id == -1) { dev_err(dev, "missing gop-port-id value\n"); return -EINVAL; @@ -5375,7 +5373,7 @@ static int mvpp2_probe(struct udevice *dev) priv->probe_done = 1; } - err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv); + err = mvpp2_port_probe(dev, port, dev_ofnode(dev), priv); if (err) return err; @@ -5436,13 +5434,11 @@ static struct driver mvpp2_driver = { */ static int mvpp2_base_bind(struct udevice *parent) { - const void *blob = gd->fdt_blob; - int node = dev_of_offset(parent); struct uclass_driver *drv; struct udevice *dev; struct eth_pdata *plat; char *name; - int subnode; + ofnode subnode; u32 id; int base_id_add; @@ -5455,19 +5451,19 @@ static int mvpp2_base_bind(struct udevice *parent) base_id_add = base_id; - fdt_for_each_subnode(subnode, blob, node) { + dev_for_each_subnode(subnode, parent) { /* Increment base_id for all subnodes, also the disabled ones */ base_id++; /* Skip disabled ports */ - if (!fdtdec_get_is_enabled(blob, subnode)) + if (!ofnode_is_enabled(subnode)) continue; plat = calloc(1, sizeof(*plat)); if (!plat) return -ENOMEM; - id = fdtdec_get_int(blob, subnode, "port-id", -1); + id = ofnode_read_s32_default(subnode, "port-id", -1); id += base_id_add; name = calloc(1, 16); @@ -5478,8 +5474,7 @@ static int mvpp2_base_bind(struct udevice *parent) sprintf(name, "mvpp2-%d", id); /* Create child device UCLASS_ETH and bind it */ - device_bind(parent, &mvpp2_driver, name, plat, - offset_to_ofnode(subnode), &dev); + device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev); } return 0; -- cgit v1.3.1 From 3cacd1b1809d9eecffb8b05a9094e234c7227d4b Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Tue, 19 May 2026 14:22:07 +0800 Subject: watchdog: ulp_wdog: Use driver model for reset_cpu() Replace hardcoded WDOG_BASE_ADDR with driver model based dynamic address lookup from device tree, allowing reset_cpu() to dynamically locate watchdog devices from device tree. This change also enables CONFIG_WDT for relevant boards and ensures the watchdog nodes are available for driver model usage. - Remove hardcoded WDOG_BASE_ADDR from hw_watchdog_* functions - Reimplement reset_cpu() using UCLASS_WDT device iteration - Add ulp_wdt_expire_now() callback for standard WDT interface - Pass wdog register pointer to hw_watchdog_set_timeout() - Enable CONFIG_WDT for boards using ULP watchdog - Remove wdog3 status = "disabled" overrides from U-Boot device tree overlays, as the watchdog device needs to be accessible for driver model based reset functionality. Signed-off-by: Alice Guo Acked-by: Francesco Dolcini # Toradex boards Reviewed-by: Peng Fan --- arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 4 -- arch/arm/dts/imx943-evk-u-boot.dtsi | 4 -- arch/arm/dts/imx95-15x15-evk-u-boot.dtsi | 4 -- arch/arm/dts/imx95-19x19-evk-u-boot.dtsi | 4 -- arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi | 4 -- arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi | 4 -- configs/imx8ulp_evk_defconfig | 1 + configs/imx93-phycore_defconfig | 1 + configs/imx943_evk_defconfig | 1 + configs/imx95_15x15_evk_defconfig | 1 + configs/imx95_evk.config | 1 + configs/mx7ulp_com_defconfig | 1 + configs/toradex-smarc-imx95_defconfig | 1 + configs/verdin-imx95_defconfig | 1 + drivers/watchdog/ulp_wdog.c | 79 +++++++++--------------- 15 files changed, 36 insertions(+), 75 deletions(-) (limited to 'drivers') diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi index 860994129ae..ac130b54738 100644 --- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -26,10 +26,6 @@ status = "disabled"; }; -&wdog3 { - status = "disabled"; -}; - &per_bridge4 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx943-evk-u-boot.dtsi b/arch/arm/dts/imx943-evk-u-boot.dtsi index 247a7ed6838..3b3619d2232 100644 --- a/arch/arm/dts/imx943-evk-u-boot.dtsi +++ b/arch/arm/dts/imx943-evk-u-boot.dtsi @@ -153,10 +153,6 @@ bootph-pre-ram; }; -&wdog3 { - status = "disabled"; -}; - &xspi1 { bootph-pre-ram; pinctrl-names = "default"; diff --git a/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi b/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi index 514dd729be9..34b4073ff35 100644 --- a/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi +++ b/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi @@ -44,10 +44,6 @@ bootph-pre-ram; }; -&wdog3 { - status = "disabled"; -}; - &pinctrl_uart1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi index 8b59831b7ca..1083d863c4d 100644 --- a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi +++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi @@ -28,10 +28,6 @@ bootph-pre-ram; }; -&wdog3 { - status = "disabled"; -}; - &pinctrl_uart1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi b/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi index 24952579a67..e4eda61e5c4 100644 --- a/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi +++ b/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi @@ -103,7 +103,3 @@ &usdhc2 { bootph-pre-ram; }; - -&wdog3 { - status = "disabled"; -}; diff --git a/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi index 45633765c0f..8ab70cf7399 100644 --- a/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi @@ -105,7 +105,3 @@ &usdhc1 { bootph-pre-ram; }; - -&wdog3 { - status = "disabled"; -}; diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index baa8c1e4695..2101532833e 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -92,3 +92,4 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_NXP_FSPI=y CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index 0634378149d..f87581d4ddc 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -156,6 +156,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 CONFIG_CI_UDC=y CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y # CONFIG_RSA is not set # CONFIG_SPL_SHA256 is not set CONFIG_LZO=y diff --git a/configs/imx943_evk_defconfig b/configs/imx943_evk_defconfig index 70265f13bba..b60d39a1fa2 100644 --- a/configs/imx943_evk_defconfig +++ b/configs/imx943_evk_defconfig @@ -151,3 +151,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_SDP_LOADADDR=0x90400000 CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y diff --git a/configs/imx95_15x15_evk_defconfig b/configs/imx95_15x15_evk_defconfig index e9cd289d31f..3c18956ffe9 100644 --- a/configs/imx95_15x15_evk_defconfig +++ b/configs/imx95_15x15_evk_defconfig @@ -147,5 +147,6 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_NXP_FSPI=y CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y CONFIG_LZO=y CONFIG_BZIP2=y diff --git a/configs/imx95_evk.config b/configs/imx95_evk.config index 30ad2e60313..743778d9554 100644 --- a/configs/imx95_evk.config +++ b/configs/imx95_evk.config @@ -151,3 +151,4 @@ CONFIG_NXP_FSPI=y CONFIG_ULP_WATCHDOG=y CONFIG_LZO=y CONFIG_BZIP2=y +CONFIG_WDT=y diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig index d63168fe886..c9c3f6b5f26 100644 --- a/configs/mx7ulp_com_defconfig +++ b/configs/mx7ulp_com_defconfig @@ -63,3 +63,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y diff --git a/configs/toradex-smarc-imx95_defconfig b/configs/toradex-smarc-imx95_defconfig index caf0718fc13..9363eb5cbb6 100644 --- a/configs/toradex-smarc-imx95_defconfig +++ b/configs/toradex-smarc-imx95_defconfig @@ -175,5 +175,6 @@ CONFIG_USB_GADGET_OS_DESCRIPTORS=y CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x90400000 CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y # CONFIG_SPL_SHA1 is not set CONFIG_LZO=y diff --git a/configs/verdin-imx95_defconfig b/configs/verdin-imx95_defconfig index 50515250d17..ea1ebb0c492 100644 --- a/configs/verdin-imx95_defconfig +++ b/configs/verdin-imx95_defconfig @@ -180,5 +180,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_USB_GADGET_OS_DESCRIPTORS=y CONFIG_SDP_LOADADDR=0x90400000 CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y # CONFIG_SPL_SHA1 is not set CONFIG_LZO=y diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index 83f19dc0e86..e3a89031c44 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -7,6 +7,7 @@ #include #include #include +#include #include /* @@ -51,11 +52,9 @@ struct ulp_wdt_priv { #define CLK_RATE_1KHZ 1000 #define CLK_RATE_32KHZ 125 -void hw_watchdog_set_timeout(u16 val) +void hw_watchdog_set_timeout(struct wdog_regs *wdog, u16 val) { /* setting timeout value */ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - writel(val, &wdog->toval); } @@ -89,7 +88,7 @@ void ulp_watchdog_init(struct wdog_regs *wdog, u16 timeout) while (!(readl(&wdog->cs) & WDGCS_ULK)) ; - hw_watchdog_set_timeout(timeout); + hw_watchdog_set_timeout(wdog, timeout); writel(0, &wdog->win); /* setting 1-kHz clock source, enable counter running, and clear interrupt */ @@ -107,57 +106,20 @@ void ulp_watchdog_init(struct wdog_regs *wdog, u16 timeout) ulp_watchdog_reset(wdog); } -void hw_watchdog_reset(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - - ulp_watchdog_reset(wdog); -} - -void hw_watchdog_init(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - - ulp_watchdog_init(wdog, CONFIG_WATCHDOG_TIMEOUT_MSECS); -} - -#if !CONFIG_IS_ENABLED(SYSRESET) +#if !CONFIG_IS_ENABLED(SYSRESET) && CONFIG_IS_ENABLED(WDT) void reset_cpu(void) { - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - u32 cmd32 = 0; - - if (readl(&wdog->cs) & WDGCS_CMD32EN) { - writel(UNLOCK_WORD, &wdog->cnt); - cmd32 = WDGCS_CMD32EN; - } else { - dmb(); - __raw_writel(UNLOCK_WORD0, &wdog->cnt); - __raw_writel(UNLOCK_WORD1, &wdog->cnt); - dmb(); - } + struct udevice *wdt; - /* Wait WDOG Unlock */ - while (!(readl(&wdog->cs) & WDGCS_ULK)) - ; + for (uclass_first_device(UCLASS_WDT, &wdt); + wdt; + uclass_next_device(&wdt)) { + if (!dev_read_enabled(wdt)) + continue; - hw_watchdog_set_timeout(5); /* 5ms timeout for general; 40ms timeout for imx93 */ - writel(0, &wdog->win); - - /* enable counter running */ - if (IS_ENABLED(CONFIG_ARCH_IMX9)) - writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES | - WDGCS_INT), &wdog->cs); - else - writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs); - - /* Wait WDOG reconfiguration */ - while (!(readl(&wdog->cs) & WDGCS_RCS)) - ; - - hw_watchdog_reset(); - - while (1); + wdt_expire_now(wdt, 0); + break; + } } #endif @@ -184,6 +146,20 @@ static int ulp_wdt_reset(struct udevice *dev) return 0; } +static int ulp_wdt_expire_now(struct udevice *dev, ulong flags) +{ + int ret; + + /* 5ms timeout for all others; 40ms timeout for "fsl,imx93-wdt" */ + ret = ulp_wdt_start(dev, 5, flags); + if (ret) + return ret; + + mdelay(50); + + return 0; +} + static int ulp_wdt_probe(struct udevice *dev) { struct ulp_wdt_priv *priv = dev_get_priv(dev); @@ -202,6 +178,7 @@ static int ulp_wdt_probe(struct udevice *dev) static const struct wdt_ops ulp_wdt_ops = { .start = ulp_wdt_start, .reset = ulp_wdt_reset, + .expire_now = ulp_wdt_expire_now, }; static const struct udevice_id ulp_wdt_ids[] = { -- cgit v1.3.1 From dfd83eab76c4ca01732e8782dc815595bd9548fa Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 22 May 2026 21:50:15 +0800 Subject: arm: imx8mp: Add new variant parts support iMX8MP added 4 new variant parts for low cost industrial and HMI. The parts disabled HIFI DSP and ISP while other functions are enabled. Part number: - MIMX8ML2DVNLZAB and MIMX8ML2CVNKZAB (2-core) - MIMX8ML5DVNLZAB and MIMX8ML5CVNKZAB (4-core) Signed-off-by: Ye Li --- arch/arm/include/asm/arch-imx/cpu.h | 2 ++ arch/arm/include/asm/mach-imx/sys_proto.h | 5 ++++- arch/arm/mach-imx/cpu.c | 4 ++++ arch/arm/mach-imx/imx8m/soc.c | 16 ++++++++++++---- drivers/cpu/imx8_cpu.c | 4 ++++ 5 files changed, 26 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 25d0f205fde..bbc4b421a02 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -48,6 +48,8 @@ #define MXC_CPU_IMX8MPL 0x187 /* dummy ID */ #define MXC_CPU_IMX8MPD 0x188 /* dummy ID */ #define MXC_CPU_IMX8MPUL 0x189 /* dummy ID */ +#define MXC_CPU_IMX8MPD2 0x18c /* dummy ID */ +#define MXC_CPU_IMX8MP5 0x18d /* dummy ID */ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index ab573413128..d25c08f8fe7 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -74,9 +74,12 @@ struct bd_info; #define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD)) #define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS)) #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ - is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL)) + is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL) || \ + is_cpu_type(MXC_CPU_IMX8MP5) || is_cpu_type(MXC_CPU_IMX8MPD2)) #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) +#define is_imx8mpd2() (is_cpu_type(MXC_CPU_IMX8MPD2)) #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL)) +#define is_imx8mp5() (is_cpu_type(MXC_CPU_IMX8MP5)) #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6)) #define is_imx8mpul() (is_cpu_type(MXC_CPU_IMX8MPUL)) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 8af45e14707..c49ad44ac2d 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -99,10 +99,14 @@ const char *get_imx_type(u32 imxtype) switch (imxtype) { case MXC_CPU_IMX8MP: return "8MP[8]"; /* Quad-core version of the imx8mp */ + case MXC_CPU_IMX8MPD2: + return "8MP Dual[2]"; /* Dual-core version of the imx8mp, low cost industrial & HMI */ case MXC_CPU_IMX8MPD: return "8MP Dual[3]"; /* Dual-core version of the imx8mp */ case MXC_CPU_IMX8MPL: return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */ + case MXC_CPU_IMX8MP5: + return "8MP[5]"; /* Quad-core version of the imx8mp, low cost industrial & HMI */ case MXC_CPU_IMX8MP6: return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */ case MXC_CPU_IMX8MPUL: diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 1fe083ae94f..498bbe6704f 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -442,7 +442,7 @@ static u32 get_cpu_variant_type(u32 type) u32 flag = 0; if ((value0 & 0xc0000) == 0x80000) - return MXC_CPU_IMX8MPD; + flag |= (1 << 10); /* vpu disabled */ if ((value0 & 0x43000000) == 0x43000000) @@ -475,6 +475,12 @@ static u32 get_cpu_variant_type(u32 type) return MXC_CPU_IMX8MPL; case 2: return MXC_CPU_IMX8MP6; + case 0x400: + return MXC_CPU_IMX8MPD; + case 0x4: + return MXC_CPU_IMX8MP5; + case 0x404: + return MXC_CPU_IMX8MPD2; default: break; } @@ -1433,13 +1439,15 @@ usb_modify_speed: if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6()) disable_npu_nodes(blob); - if (is_imx8mpul() || is_imx8mpl()) + if (is_imx8mpul() || is_imx8mpl() || + is_imx8mpd2() || is_imx8mp5()) disable_isp_nodes(blob); - if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6()) + if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6() || + is_imx8mpd2() || is_imx8mp5()) disable_dsp_nodes(blob); - if (is_imx8mpd()) + if (is_imx8mpd() || is_imx8mpd2()) disable_cpu_nodes(blob, nodes_path, 2, 4); #endif diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 785c299eca5..c6bb938e398 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -63,10 +63,14 @@ static const char *get_imx_type_str(u32 imxtype) return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */ case MXC_CPU_IMX8MP: return "8MP[8]"; /* Quad-core version of the imx8mp */ + case MXC_CPU_IMX8MPD2: + return "8MP Dual[2]"; /* Dual-core version of the imx8mp, low cost industrial & HMI */ case MXC_CPU_IMX8MPD: return "8MP Dual[3]"; /* Dual-core version of the imx8mp */ case MXC_CPU_IMX8MPL: return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */ + case MXC_CPU_IMX8MP5: + return "8MP[5]"; /* Quad-core version of the imx8mp, low cost industrial & HMI */ case MXC_CPU_IMX8MP6: return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */ case MXC_CPU_IMX8MQ: -- cgit v1.3.1 From e80108c966f3ce3b1194a5b43d589cceb4c8ec54 Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Fri, 29 May 2026 18:39:36 +0200 Subject: clk: imx: don't build i.MX/RTxxxx code for all users of CCF When commit 1d7993d1d0ef ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)") introduced the parts of Linux Common Clock Framework, it was done for i.MX6 only and even had "depends on SPL_CLK_IMX6Q" conditions. Since commit ccab06689aa2 ("clk: imx: expose CCF entry for all") the framework can be reused with SoCs of other vendors (say, TI), but NXP SoC-specific code is still being build. It is especially problematic for size-constrained SPL images on TI AM62x. Make the build of the i.MX/RTxxxx code not only dependent on CONFIG_$(PHASE_)CLK_CCF, but also on CONFIG_MACH_IMX options which shall cover the i.MX platform users. This saves 2264 bytes on 32-bit ARM platforms [using CCF]. Reviewed-by: Peng Fan Signed-off-by: Alexander Sverdlin --- drivers/clk/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 5f0c0d8a5c2..c37ef75d420 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_$(PHASE_)CLK_STUB) += clk-stub.o obj-y += adi/ obj-y += airoha/ obj-y += analogbits/ -obj-y += imx/ +obj-$(CONFIG_MACH_IMX) += imx/ obj-$(CONFIG_CLK_JH7110) += starfive/ obj-y += tegra/ obj-y += ti/ -- cgit v1.3.1 From fa03ee371de84b512e6f941395d4e13040eedd17 Mon Sep 17 00:00:00 2001 From: Nora Schiffer Date: Tue, 2 Jun 2026 13:57:49 +0200 Subject: sysinfo: uclass: use sysinfo_priv size for per_device_auto Reference the struct itself for the size as it is more robust, even if it contains just a bool at the moment. Signed-off-by: Nora Schiffer Reviewed-by: Simon Glass Signed-off-by: Alexander Feilke --- drivers/sysinfo/sysinfo-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c index f04998ef8bb..bf0f664e8dc 100644 --- a/drivers/sysinfo/sysinfo-uclass.c +++ b/drivers/sysinfo/sysinfo-uclass.c @@ -152,5 +152,5 @@ UCLASS_DRIVER(sysinfo) = { .id = UCLASS_SYSINFO, .name = "sysinfo", .post_bind = dm_scan_fdt_dev, - .per_device_auto = sizeof(bool), + .per_device_auto = sizeof(struct sysinfo_priv), }; -- cgit v1.3.1 From 0ef21dd37dc1779293a101413a7ce32bd63870bb Mon Sep 17 00:00:00 2001 From: Nora Schiffer Date: Tue, 2 Jun 2026 13:57:50 +0200 Subject: sysinfo: add sysinfo_get_and_detect() helper sysinfo_detect() is commonly called after sysinfo_get(). Make the API a bit more convenient to use by introducing a helper. Signed-off-by: Nora Schiffer Signed-off-by: Alexander Feilke Reviewed-by: Simon Glass --- drivers/sysinfo/sysinfo-uclass.c | 10 ++++++++++ include/sysinfo.h | 17 +++++++++++++++++ test/dm/sysinfo.c | 16 ++++++++++++++++ 3 files changed, 43 insertions(+) (limited to 'drivers') diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c index bf0f664e8dc..d18a168614e 100644 --- a/drivers/sysinfo/sysinfo-uclass.c +++ b/drivers/sysinfo/sysinfo-uclass.c @@ -42,6 +42,16 @@ int sysinfo_detect(struct udevice *dev) return ret; } +int sysinfo_get_and_detect(struct udevice **devp) +{ + int ret = sysinfo_get(devp); + + if (!ret) + ret = sysinfo_detect(*devp); + + return ret; +} + int sysinfo_get_fit_loadable(struct udevice *dev, int index, const char *type, const char **strp) { diff --git a/include/sysinfo.h b/include/sysinfo.h index 54eb64a204a..7ca396b2ee4 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -373,6 +373,18 @@ int sysinfo_get_data_by_index(struct udevice *dev, int id, int index, */ int sysinfo_get(struct udevice **devp); +/** + * sysinfo_get_and_detect() - Get the sysinfo device and detect it. + * + * @devp: Pointer to structure to receive the sysinfo device. + * + * This is a convenience wrapper around sysinfo_get() followed by + * sysinfo_detect() + * + * Return: 0 if OK, -ve on error. + */ +int sysinfo_get_and_detect(struct udevice **devp); + /** * sysinfo_get_fit_loadable - Get the name of an image to load from FIT * This function can be used to provide the image names based on runtime @@ -438,6 +450,11 @@ static inline int sysinfo_get(struct udevice **devp) return -ENOSYS; } +static inline int sysinfo_get_and_detect(struct udevice **devp) +{ + return -ENOSYS; +} + static inline int sysinfo_get_fit_loadable(struct udevice *dev, int index, const char *type, const char **strp) { diff --git a/test/dm/sysinfo.c b/test/dm/sysinfo.c index 14ebe6b42e7..611f2e98d14 100644 --- a/test/dm/sysinfo.c +++ b/test/dm/sysinfo.c @@ -66,3 +66,19 @@ static int dm_test_sysinfo(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_sysinfo, UTF_SCAN_PDATA | UTF_SCAN_FDT); + +static int dm_test_sysinfo_get_and_detect(struct unit_test_state *uts) +{ + struct udevice *sysinfo; + bool called_detect = false; + + ut_assertok(sysinfo_get_and_detect(&sysinfo)); + ut_assert(sysinfo); + + ut_assertok(sysinfo_get_bool(sysinfo, BOOL_CALLED_DETECT, + &called_detect)); + ut_assert(called_detect); + + return 0; +} +DM_TEST(dm_test_sysinfo_get_and_detect, UTF_SCAN_PDATA | UTF_SCAN_FDT); -- cgit v1.3.1 From a30556bc4249b4154f86c9460da740ff86d30807 Mon Sep 17 00:00:00 2001 From: Nora Schiffer Date: Tue, 2 Jun 2026 13:57:51 +0200 Subject: sysinfo: tq_eeprom: new driver Introduce a sysinfo driver that can be instantiated from the device, which will provide information from the EEPROM found on all TQ-Systems SoMs. Signed-off-by: Nora Schiffer Signed-off-by: Max Merchel Reviewed-by: Simon Glass Signed-off-by: Alexander Feilke --- MAINTAINERS | 1 + configs/tqma7_common.config | 1 + .../sysinfo/tq,eeprom-sysinfo.txt | 36 ++++ drivers/sysinfo/Kconfig | 8 + drivers/sysinfo/Makefile | 1 + drivers/sysinfo/tq_eeprom.c | 203 +++++++++++++++++++++ include/sysinfo/tq_eeprom.h | 24 +++ 7 files changed, 274 insertions(+) create mode 100644 doc/device-tree-bindings/sysinfo/tq,eeprom-sysinfo.txt create mode 100644 drivers/sysinfo/tq_eeprom.c create mode 100644 include/sysinfo/tq_eeprom.h (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index a55742a0baf..ec7217f39f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1865,6 +1865,7 @@ S: Maintained W: https://www.tq-group.com/en/products/tq-embedded/ F: board/tq/* F: doc/board/tq/* +F: drivers/sysinfo/tq_eeprom.c F: include/configs/tq*.h F: include/env/tq/* diff --git a/configs/tqma7_common.config b/configs/tqma7_common.config index 7e5e31a14ab..9b055849ad1 100644 --- a/configs/tqma7_common.config +++ b/configs/tqma7_common.config @@ -77,6 +77,7 @@ CONFIG_I2C_DEFAULT_BUS_NUMBER=0x3 CONFIG_SYS_I2C_MXC=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_NVMEM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y diff --git a/doc/device-tree-bindings/sysinfo/tq,eeprom-sysinfo.txt b/doc/device-tree-bindings/sysinfo/tq,eeprom-sysinfo.txt new file mode 100644 index 00000000000..678fff0e812 --- /dev/null +++ b/doc/device-tree-bindings/sysinfo/tq,eeprom-sysinfo.txt @@ -0,0 +1,36 @@ +TQ EEPROM Sysinfo Driver +------------------------ + +This binding describes a sysinfo provider which retrieves system +identification information from an I2C EEPROM device. + +Required properties: + +- compatible: "tq,eeprom-sysinfo" +- nvmem-cells: phandle referencing the nvmem cell +- nvmem-cell-names: string, should be "device_info" + +Example: + +&i2c1 { + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + module_info: module-info@20 { + reg = <0x20 0x60>; + }; + }; + }; +}; + +sysinfo { + compatible = "tq,eeprom-sysinfo"; + nvmem-cells = <&module_info>; + nvmem-cell-names = "device_info"; +}; diff --git a/drivers/sysinfo/Kconfig b/drivers/sysinfo/Kconfig index df83df69ffb..6922dac9170 100644 --- a/drivers/sysinfo/Kconfig +++ b/drivers/sysinfo/Kconfig @@ -59,4 +59,12 @@ config SYSINFO_GPIO This ternary number is then mapped to a board revision name using device tree properties. +config SYSINFO_TQ_EEPROM + bool "Enable TQ-Systems EEPROM sysinfo driver" + depends on I2C_EEPROM + depends on SPL_I2C_EEPROM || !SPL_SYSINFO + help + Support querying EEPROM of TQ-Systems SOMs to determine board + information. + endif diff --git a/drivers/sysinfo/Makefile b/drivers/sysinfo/Makefile index 26ca3150999..d21fb3c2270 100644 --- a/drivers/sysinfo/Makefile +++ b/drivers/sysinfo/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_SYSINFO_IOT2050) += iot2050.o obj-$(CONFIG_SYSINFO_RCAR3) += rcar3.o obj-$(CONFIG_SYSINFO_SANDBOX) += sandbox.o obj-$(CONFIG_SYSINFO_SMBIOS) += smbios.o +obj-$(CONFIG_SYSINFO_TQ_EEPROM) += tq_eeprom.o diff --git a/drivers/sysinfo/tq_eeprom.c b/drivers/sysinfo/tq_eeprom.c new file mode 100644 index 00000000000..63be07b664e --- /dev/null +++ b/drivers/sysinfo/tq_eeprom.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Nora Schiffer + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define TQ_EE_RSV1_BYTES 10 +#define TQ_EE_SERIAL_BYTES 8 +#define TQ_EE_RSV2_BYTES 8 +#define TQ_EE_BDID_BYTES 0x40 + +struct tq_eeprom_data { + u8 mac[ETH_ALEN]; /* 0x20 ... 0x25 */ + u8 rsv1[TQ_EE_RSV1_BYTES]; + u8 serial[TQ_EE_SERIAL_BYTES]; /* 0x30 ... 0x37 */ + u8 rsv2[TQ_EE_RSV2_BYTES]; + u8 id[TQ_EE_BDID_BYTES]; /* 0x40 ... 0x7f */ +}; + +static_assert(sizeof(struct tq_eeprom_data) == 0x60, + "struct tq_eeprom_data has incorrect size"); + +/** + * struct sysinfo_tq_eeprom_priv - sysinfo private data + */ +struct sysinfo_tq_eeprom_priv { + struct nvmem_cell device_info_cell; + + /* Reserve extra space for \0 in id and serial */ + char id[TQ_EE_BDID_BYTES + 1]; + char serial[TQ_EE_SERIAL_BYTES + 1]; + u8 mac[ETH_ALEN]; +}; + +static void tq_eeprom_parse_id(struct udevice *dev, const struct tq_eeprom_data *data) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < sizeof(data->id); i++) { + if (!(isprint(data->id[i]) && isascii(data->id[i]))) + break; + } + + if (i == 0) + dev_warn(dev, "no valid model name in EEPROM\n"); + + snprintf(priv->id, sizeof(priv->id), "%.*s", i, data->id); +} + +static int tq_eeprom_serial_len(const struct tq_eeprom_data *data, bool allow_upper) +{ + int i; + + for (i = 0; i < sizeof(data->serial); i++) { + if (!(isdigit(data->serial[i]) || (allow_upper && isupper(data->serial[i])))) + break; + } + + return i; +} + +static void tq_eeprom_parse_serial(struct udevice *dev, const struct tq_eeprom_data *data) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + bool use_new_format; + int len; + + use_new_format = data->serial[0] == 'T' && data->serial[1] == 'Q'; + + len = tq_eeprom_serial_len(data, use_new_format); + + /* For now, only serial numbers with the exact size of the field are accepted */ + if (len != sizeof(data->serial)) { + dev_warn(dev, "no valid serial number in EEPROM\n"); + len = 0; + } + + snprintf(priv->serial, sizeof(priv->serial), "%.*s", len, data->serial); +} + +static int tq_eeprom_dump(const struct sysinfo_tq_eeprom_priv *priv) +{ + printf("TQ EEPROM:\n"); + printf(" ID: %s\n", priv->id[0] ? priv->id : ""); + printf(" SN: %s\n", priv->serial[0] ? priv->serial : ""); + printf(" MAC: "); + if (is_valid_ethaddr(priv->mac)) + printf("%pM\n", priv->mac); + else + printf("\n"); + + return 0; +} + +static int sysinfo_tq_eeprom_detect(struct udevice *dev) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + struct tq_eeprom_data data; + int ret; + + ret = nvmem_cell_read(&priv->device_info_cell, (u8 *)&data, sizeof(data)); + if (ret < 0) { + dev_err(dev, "EEPROM read failed: %d\n", ret); + return ret; + } + + tq_eeprom_parse_id(dev, &data); + tq_eeprom_parse_serial(dev, &data); + memcpy(priv->mac, data.mac, ETH_ALEN); + + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + tq_eeprom_dump(priv); + + return 0; +} + +static int sysinfo_tq_eeprom_get_str(struct udevice *dev, int id, size_t size, char *val) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_TQ_MODEL: + if (!priv->id[0]) + return -ENODATA; + + strlcpy(val, priv->id, size); + return 0; + + case SYSID_TQ_SERIAL: + if (!priv->serial[0]) + return -ENODATA; + + strlcpy(val, priv->serial, size); + return 0; + + default: + return -EINVAL; + } +} + +static int sysinfo_tq_eeprom_get_data(struct udevice *dev, int id, void **data, size_t *size) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_TQ_MAC_ADDR: + if (!is_valid_ethaddr(priv->mac)) + return -ENODATA; + + *data = priv->mac; + *size = sizeof(priv->mac); + + return 0; + + default: + return -EINVAL; + } +} + +static const struct sysinfo_ops sysinfo_tq_eeprom_ops = { + .detect = sysinfo_tq_eeprom_detect, + .get_str = sysinfo_tq_eeprom_get_str, + .get_data = sysinfo_tq_eeprom_get_data, +}; + +static int sysinfo_tq_eeprom_probe(struct udevice *dev) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + int ret; + + ret = nvmem_cell_get_by_name(dev, "device_info", &priv->device_info_cell); + if (ret) { + dev_err(dev, "device_info not found: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct udevice_id sysinfo_tq_eeprom_ids[] = { + { .compatible = "tq,eeprom-sysinfo" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sysinfo_tq_eeprom) = { + .name = "sysinfo_tq_eeprom", + .id = UCLASS_SYSINFO, + .of_match = sysinfo_tq_eeprom_ids, + .ops = &sysinfo_tq_eeprom_ops, + .priv_auto = sizeof(struct sysinfo_tq_eeprom_priv), + .probe = sysinfo_tq_eeprom_probe, +}; diff --git a/include/sysinfo/tq_eeprom.h b/include/sysinfo/tq_eeprom.h new file mode 100644 index 00000000000..6b1bddd7ce0 --- /dev/null +++ b/include/sysinfo/tq_eeprom.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Nora Schiffer + */ + +#ifndef __SYSINFO_TQ_EEPROM_H__ +#define __SYSINFO_TQ_EEPROM_H__ + +#include + +enum { + /* Model string of TQ-Systems SOM. This is different from BOARD_MODEL, + * which usually combines SOM and baseboard names for TQ hardware + */ + SYSID_TQ_MODEL = SYSID_USER, + /* SOM serial number */ + SYSID_TQ_SERIAL, + /* MAC address */ + SYSID_TQ_MAC_ADDR, +}; + +#endif /* __SYSINFO_TQ_EEPROM_H__ */ -- cgit v1.3.1 From d0a62df75337cd5e44275c51b77383df9db9a339 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 5 Jun 2026 17:51:06 +0800 Subject: cpu: imx8_cpu: Add iMX8MP UltraLite Part cpu type iMX8MP UltraLite part is missed in the cpu type print Signed-off-by: Ye Li Acked-by: Peng Fan --- drivers/cpu/imx8_cpu.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index c6bb938e398..f8202d36fcd 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -73,6 +73,8 @@ static const char *get_imx_type_str(u32 imxtype) return "8MP[5]"; /* Quad-core version of the imx8mp, low cost industrial & HMI */ case MXC_CPU_IMX8MP6: return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */ + case MXC_CPU_IMX8MPUL: + return "8MP UltraLite"; /* Quad-core UltraLite version of the imx8mp */ case MXC_CPU_IMX8MQ: return "8MQ"; /* Quad-core version of the imx8mq */ case MXC_CPU_IMX8MQL: -- cgit v1.3.1 From 3782bf8a0ad1abee3a2a537b9180b63d7ed22d40 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 5 Jun 2026 17:51:07 +0800 Subject: cpu: imx8_cpu: fix the mpidr check The mpidr's type is u32, however dev_read_addr returns a value with type fdt_addr_t(phys_addr_t) which is 64bit long. So the check never fail. This patch we still keep mpidr as u32 type, because i.MX8 only has max two cluster, the higher 32bit will always be 0. Use a variable addr to do the check, if check pass, assign the lower 32 bit to plat->mpidr. Signed-off-by: Peng Fan Signed-off-by: Ye Li --- drivers/cpu/imx8_cpu.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index f8202d36fcd..d94a24ea30a 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -377,6 +377,7 @@ static int imx_cpu_probe(struct udevice *dev) { struct cpu_imx_plat *plat = dev_get_plat(dev); u32 cpurev; + fdt_addr_t addr; set_core_data(dev); cpurev = get_cpu_rev(); @@ -384,12 +385,14 @@ static int imx_cpu_probe(struct udevice *dev) get_imx_rev_str(plat, cpurev & 0xFFF); plat->type = get_imx_type_str((cpurev & 0x1FF000) >> 12); plat->freq_mhz = imx_get_cpu_rate(dev) / 1000000; - plat->mpidr = dev_read_addr(dev); - if (plat->mpidr == FDT_ADDR_T_NONE) { + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) { printf("%s: Failed to get CPU reg property\n", __func__); return -EINVAL; } + plat->mpidr = (u32)addr; + return 0; } -- cgit v1.3.1 From 8763c0169d8d8f16ee8c88fb9672f18638f0bba8 Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Fri, 22 May 2026 17:39:23 +0200 Subject: rtc: pcf85063: adjust date format to adhere to the rtc_time spec The rtc_time documentation in rtc_def.h notes a differences to the common "struct time" that specifies tm_mon as 1 ... 12 and tm_year as year since 0. Also trim register values to valid bits. Fixes: 1c2a2253f798 ("drivers: rtc: add PCF85063 support") Reviewed-by: Alexander Sverdlin Signed-off-by: Alexander Feilke --- drivers/rtc/pcf85063.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/pcf85063.c b/drivers/rtc/pcf85063.c index 737d4547aca..21640b039c1 100644 --- a/drivers/rtc/pcf85063.c +++ b/drivers/rtc/pcf85063.c @@ -35,7 +35,9 @@ static int pcf85063_get_time(struct udevice *dev, struct rtc_time *tm) tm->tm_hour = bcd2bin(regs[2] & 0x3f); tm->tm_mday = bcd2bin(regs[3] & 0x3f); tm->tm_wday = regs[4] & 0x07; - tm->tm_mon = bcd2bin(regs[5] & 0x1f) - 1; + /* rtc register and rtc_time spec uses 1 - 12 */ + tm->tm_mon = bcd2bin(regs[5] & 0x1f); + /* adjust rtc_time (years since 0) to match register spec */ tm->tm_year = bcd2bin(regs[6]) + 2000; return 0; @@ -50,12 +52,21 @@ static int pcf85063_set_time(struct udevice *dev, const struct rtc_time *tm) return -EINVAL; } - regs[0] = bin2bcd(tm->tm_sec); + /* hours, minutes and seconds */ + regs[0] = bin2bcd(tm->tm_sec) & (~PCF85063_REG_SC_OS); + regs[1] = bin2bcd(tm->tm_min); regs[2] = bin2bcd(tm->tm_hour); + + /* Day of month, 1 - 31 */ regs[3] = bin2bcd(tm->tm_mday); - regs[4] = tm->tm_wday; - regs[5] = bin2bcd(tm->tm_mon + 1); + + /* Day of week 0 - 6 */ + regs[4] = tm->tm_wday & 0x07; + + /* rtc register and rtc_time spec uses 1 - 12 */ + regs[5] = bin2bcd(tm->tm_mon); + /* adjust register to match rtc_time spec */ regs[6] = bin2bcd(tm->tm_year % 100); return dm_i2c_write(dev, PCF85063_REG_SC, regs, sizeof(regs)); -- cgit v1.3.1 From 1f04246641079ccf64c29ac53891ddc41d1b1694 Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Fri, 22 May 2026 17:39:24 +0200 Subject: rtc: pcf85063: add support for NXP PCF85063 family Supported devices: - generic PCF85063 / PCF85063TP (no alarm regs) - PCF85063A / PCF85073A (alarm regs) Tested with TQMa8MPxL SOM from TQ-Systems GmbH. Also add missing .data field to rv8263 which represents the number of available registers (= linux `pcf85063_config.max_register + 1`). Signed-off-by: Markus Niebel Reviewed-by: Alexander Sverdlin Signed-off-by: Alexander Feilke --- drivers/rtc/pcf85063.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/rtc/pcf85063.c b/drivers/rtc/pcf85063.c index 21640b039c1..183a214a3e9 100644 --- a/drivers/rtc/pcf85063.c +++ b/drivers/rtc/pcf85063.c @@ -80,12 +80,18 @@ static int pcf85063_reset(struct udevice *dev) static int pcf85063_read(struct udevice *dev, unsigned int offset, u8 *buf, unsigned int len) { + if (offset + len > dev->driver_data) + return -EINVAL; + return dm_i2c_read(dev, offset, buf, len); } static int pcf85063_write(struct udevice *dev, unsigned int offset, const u8 *buf, unsigned int len) { + if (offset + len > dev->driver_data) + return -EINVAL; + return dm_i2c_write(dev, offset, buf, len); } @@ -105,7 +111,11 @@ static int pcf85063_probe(struct udevice *dev) } static const struct udevice_id pcf85063_of_id[] = { - { .compatible = "microcrystal,rv8263" }, + { .compatible = "microcrystal,rv8263", .data = 0x12 }, + { .compatible = "nxp,pcf85063", .data = 0xb }, + { .compatible = "nxp,pcf85063a", .data = 0x12 }, + { .compatible = "nxp,pcf85063tp", .data = 0xb }, + { .compatible = "nxp,pcf85073a", .data = 0x12 }, { } }; -- cgit v1.3.1 From 49754d293ea4a2df923cd70de8a69a4ba150477d Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Fri, 22 May 2026 17:39:25 +0200 Subject: rtc: pcf85063: add missing register definitions Sync definitions from upstream linux v6.19. Reviewed-by: Alexander Sverdlin Signed-off-by: Alexander Feilke --- drivers/rtc/pcf85063.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/pcf85063.c b/drivers/rtc/pcf85063.c index 183a214a3e9..06c85d939e0 100644 --- a/drivers/rtc/pcf85063.c +++ b/drivers/rtc/pcf85063.c @@ -11,11 +11,33 @@ #include #define PCF85063_REG_CTRL1 0x00 /* status */ -#define PCF85063_REG_CTRL1_SR 0x58 +#define PCF85063_REG_CTRL1_CAP_SEL BIT(0) +#define PCF85063_REG_CTRL1_STOP BIT(5) +#define PCF85063_REG_CTRL1_EXT_TEST BIT(7) +#define PCF85063_REG_CTRL1_SWR 0x58 /* Software reset command */ + +#define PCF85063_REG_CTRL2 0x01 +#define PCF85063_CTRL2_AF BIT(6) +#define PCF85063_CTRL2_AIE BIT(7) + +#define PCF85063_REG_OFFSET 0x02 +#define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */ +#define PCF85063_OFFSET_MODE BIT(7) +#define PCF85063_OFFSET_STEP0 4340 +#define PCF85063_OFFSET_STEP1 4069 + +#define PCF85063_REG_CLKO_F_MASK 0x07 /* frequency mask */ +#define PCF85063_REG_CLKO_F_32768HZ 0x00 +#define PCF85063_REG_CLKO_F_OFF 0x07 + +#define PCF85063_REG_RAM 0x03 #define PCF85063_REG_SC 0x04 /* datetime */ #define PCF85063_REG_SC_OS 0x80 +#define PCF85063_REG_ALM_S 0x0b +#define PCF85063_AEN BIT(7) + static int pcf85063_get_time(struct udevice *dev, struct rtc_time *tm) { u8 regs[7]; @@ -74,7 +96,7 @@ static int pcf85063_set_time(struct udevice *dev, const struct rtc_time *tm) static int pcf85063_reset(struct udevice *dev) { - return dm_i2c_reg_write(dev, PCF85063_REG_CTRL1, PCF85063_REG_CTRL1_SR); + return dm_i2c_reg_write(dev, PCF85063_REG_CTRL1, PCF85063_REG_CTRL1_SWR); } static int pcf85063_read(struct udevice *dev, unsigned int offset, u8 *buf, -- cgit v1.3.1 From 2b6de25797b49a1b3eff6d24bfa0f7808028b962 Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Fri, 22 May 2026 17:39:26 +0200 Subject: rtc: pcf85063: keep the divider chain in reset during set_time Sync from upstream linux v6.19. Reviewed-by: Alexander Sverdlin Signed-off-by: Alexander Feilke --- drivers/rtc/pcf85063.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/rtc/pcf85063.c b/drivers/rtc/pcf85063.c index 06c85d939e0..0b336b8c5ee 100644 --- a/drivers/rtc/pcf85063.c +++ b/drivers/rtc/pcf85063.c @@ -68,12 +68,25 @@ static int pcf85063_get_time(struct udevice *dev, struct rtc_time *tm) static int pcf85063_set_time(struct udevice *dev, const struct rtc_time *tm) { u8 regs[7]; + int rc; if (tm->tm_year < 2000 || tm->tm_year > 2099) { dev_err(dev, "Year must be between 2000 and 2099.\n"); return -EINVAL; } + /* + * to accurately set the time, reset the divider chain and keep it in + * reset state until all time/date registers are written + */ + rc = dm_i2c_reg_clrset(dev, PCF85063_REG_CTRL1, + PCF85063_REG_CTRL1_EXT_TEST | + PCF85063_REG_CTRL1_STOP, + PCF85063_REG_CTRL1_STOP); + + if (rc) + return rc; + /* hours, minutes and seconds */ regs[0] = bin2bcd(tm->tm_sec) & (~PCF85063_REG_SC_OS); @@ -91,7 +104,17 @@ static int pcf85063_set_time(struct udevice *dev, const struct rtc_time *tm) /* adjust register to match rtc_time spec */ regs[6] = bin2bcd(tm->tm_year % 100); - return dm_i2c_write(dev, PCF85063_REG_SC, regs, sizeof(regs)); + rc = dm_i2c_write(dev, PCF85063_REG_SC, regs, sizeof(regs)); + if (rc) + return rc; + + /* + * Write the control register as a separate action since the size of + * the register space is different between the PCF85063TP and + * PCF85063A devices. The rollover point can not be used. + */ + return dm_i2c_reg_clrset(dev, PCF85063_REG_CTRL1, + PCF85063_REG_CTRL1_STOP, 0); } static int pcf85063_reset(struct udevice *dev) -- cgit v1.3.1 From d8f535cd8f7cb5f9231f91a3307895db7c9f9552 Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Fri, 22 May 2026 17:39:27 +0200 Subject: rtc: pcf85063: support loading quartz-load capacitance from device tree Use previously ignored quartz-load-femtofarads property from device tree to set load capacitance. If missing, leave the device unconfigured as a default might have been set. force_cap is left out for now but can be retrofitted in the future as there may be different hardware without the 12.500pF flag. Reviewed-by: Alexander Sverdlin Signed-off-by: Alexander Feilke --- drivers/rtc/pcf85063.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'drivers') diff --git a/drivers/rtc/pcf85063.c b/drivers/rtc/pcf85063.c index 0b336b8c5ee..107e8b4d4c8 100644 --- a/drivers/rtc/pcf85063.c +++ b/drivers/rtc/pcf85063.c @@ -140,6 +140,30 @@ static int pcf85063_write(struct udevice *dev, unsigned int offset, return dm_i2c_write(dev, offset, buf, len); } +static int pcf85063_load_capacitance(struct udevice *dev) +{ + u32 load = 7000; + u8 reg = 0; + + if (ofnode_read_u32(dev_ofnode(dev), "quartz-load-femtofarads", &load)) + return 0; + + switch (load) { + default: + dev_warn(dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000", + load); + fallthrough; + case 7000: + break; + case 12500: + reg = PCF85063_REG_CTRL1_CAP_SEL; + break; + } + + return dm_i2c_reg_clrset(dev, PCF85063_REG_CTRL1, + PCF85063_REG_CTRL1_CAP_SEL, reg); +} + static const struct rtc_ops pcf85063_rtc_ops = { .get = pcf85063_get_time, .set = pcf85063_set_time, @@ -150,8 +174,22 @@ static const struct rtc_ops pcf85063_rtc_ops = { static int pcf85063_probe(struct udevice *dev) { + u8 tmp; + int err; + i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS); + err = dm_i2c_read(dev, PCF85063_REG_SC, &tmp, sizeof(tmp)); + if (err) { + dev_err(dev, "RTC chip is not present\n"); + return err; + } + + err = pcf85063_load_capacitance(dev); + if (err < 0) + dev_warn(dev, "failed to set xtal load capacitance: %d", + err); + return 0; } -- cgit v1.3.1 From 059174b9554ef4f366accd75b641447244c00f3c Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Fri, 22 May 2026 17:39:28 +0200 Subject: rtc: pcf85063: add power loss detection during probe Retrofit from upstream linux to try resetting the device after power loss. Reviewed-by: Alexander Sverdlin Signed-off-by: Alexander Feilke --- drivers/rtc/pcf85063.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers') diff --git a/drivers/rtc/pcf85063.c b/drivers/rtc/pcf85063.c index 107e8b4d4c8..421c42c0b81 100644 --- a/drivers/rtc/pcf85063.c +++ b/drivers/rtc/pcf85063.c @@ -185,6 +185,20 @@ static int pcf85063_probe(struct udevice *dev) return err; } + /* + * If a Power loss is detected, SW reset the device. + * From PCF85063A datasheet: + * There is a low probability that some devices will have corruption + * of the registers after the automatic power-on reset... + */ + if (tmp & PCF85063_REG_SC_OS) { + dev_warn(dev, "POR issue detected, sending a SW reset\n"); + err = dm_i2c_reg_clrset(dev, PCF85063_REG_CTRL1, + 0xff, PCF85063_REG_CTRL1_SWR); + if (err < 0) + dev_warn(dev, "SW reset failed, trying to continue\n"); + } + err = pcf85063_load_capacitance(dev); if (err < 0) dev_warn(dev, "failed to set xtal load capacitance: %d", -- cgit v1.3.1 From 8294d86b1d9ec63dbe7d145dc67f2385e3290c0a Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Fri, 22 May 2026 17:39:29 +0200 Subject: drivers: Kconfig: rtc_pcf85063: note unsupported chip features Signed-off-by: Alexander Feilke --- drivers/rtc/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 65d9bf533cb..3b74770b18a 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -163,6 +163,9 @@ config RTC_PCF85063 help If you say yes here you get support for the NXP PCF85063 RTC and compatible chips. + Support for the following chip features is currently not implemented: + - NVMEM device for RAM register + - CLKOUT generation config RTC_PCF8563 bool "Philips PCF8563" -- cgit v1.3.1 From f2390069d45b3490cfd87de6d6bac6e646796b6b Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Thu, 14 May 2026 15:52:19 +0530 Subject: firmware: zynqmp: Add PMC PGGS register read API Add zynqmp_pm_get_pmc_global_pggs_reg() to read PMC Global PGGS3 and PGGS4 registers via firmware IOCTL. Supports IOCTL_READ_PGGS as the preferred path and falls back to IOCTL_READ_REG for older PLM firmware versions that do not support IOCTL_READ_PGGS. Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260514102601.1759779-3-padmarao.begari@amd.com --- drivers/firmware/firmware-zynqmp.c | 54 +++++++++++++++++++++++++++++++++++++- include/zynqmp_firmware.h | 4 +++ 2 files changed, 57 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index fb583580ebe..ea14ed4ef95 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -3,7 +3,7 @@ * Xilinx Zynq MPSoC Firmware driver * * Copyright (C) 2018-2019 Xilinx, Inc. - * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. */ #include @@ -197,6 +197,58 @@ int zynqmp_pm_ufs_cal_reg(u32 *value) *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET); return 0; } +#endif /* CONFIG_ARCH_VERSAL2 */ + +#if defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL2) +u32 zynqmp_pm_get_pmc_global_pggs_reg(u32 reg_addr) +{ + int ret; + u32 value = 0; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + if (reg_addr == PMC_GLOBAL_PGGS3_REG) { + value = 0; + } else if (reg_addr == PMC_GLOBAL_PGGS4_REG) { + value = 1; + } else { + printf("%s: not supported pggs register 0x%x\n", + __func__, reg_addr); + return 0; + } + + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_PGGS); + if (ret) { + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_REG); + if (ret) { + printf("%s: IOCTL_READ_REG is not supported : %d\n" + , __func__, ret); + return 0; + } + + /* find node ID from the pggs3 offset */ + value = PM_REG_PGGS3 + value; + + ret = xilinx_pm_request(PM_IOCTL, value, + IOCTL_READ_REG, 0, 0, 0, 0, + ret_payload); + if (ret) { + printf("%s: node 0x%x get pggs register failed\n", + __func__, value); + return 0; + } + } else { + ret = xilinx_pm_request(PM_IOCTL, PMC_GLOBAL_PGGS3_REG_NODE, + IOCTL_READ_PGGS, value, 0, 0, 0, + ret_payload); + if (ret) { + printf("%s: node 0x%x get pggs register failed\n", + __func__, PMC_GLOBAL_PGGS3_REG_NODE); + return 0; + } + } + + return ret_payload[1]; +} #endif int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value) diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index f5e72625e53..0e545e3db1b 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -470,6 +470,7 @@ int zynqmp_pm_ufs_sram_csr_read(u32 *value); int zynqmp_pm_ufs_sram_csr_write(u32 *value); int zynqmp_pm_ufs_cal_reg(u32 *value); u32 zynqmp_pm_get_pmc_multi_boot_reg(void); +u32 zynqmp_pm_get_pmc_global_pggs_reg(u32 reg_addr); /* Type of Config Object */ #define PM_CONFIG_OBJECT_TYPE_BASE 0x1U @@ -534,4 +535,7 @@ extern smc_call_handler_t __data smc_call_handler; #define PM_DEV_OSPI (0x1822402aU) +#define PM_REG_PGGS3 0x30004003 +#define PMC_GLOBAL_PGGS3_REG_NODE 0x1824C005 + #endif /* _ZYNQMP_FIRMWARE_H_ */ -- cgit v1.3.1 From 19f7def2646f2ec2926e8a0fcff50d4b754eec92 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 25 May 2026 13:45:42 +0200 Subject: reset: Add reset_reset() and reset_reset_bulk() API Add reset_reset() and reset_reset_bulk() functions to the reset controller API. These functions assert and then deassert reset signals in a single call, providing a convenient way to pulse/toggle a reset line. This mimics the Linux kernel's reset_control_reset() and reset_control_bulk_reset() APIs. The new functions are useful for drivers that need to cycle a reset line during initialization or error recovery but with also passing delay parameter. If a driver implements the rst_reset op, it will be called directly with the delay parameter. Otherwise, the reset core performs reset_assert(), optional udelay(), and reset_deassert() as fallback. Reviewed-by: Simon Glass Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/55ddd313c9e7b2d4dc79ab36bdd0040f871610f6.1779709539.git.michal.simek@amd.com --- drivers/reset/reset-uclass.c | 34 ++++++++++++++++++++++++++++++ include/reset-uclass.h | 19 +++++++++++++++++ include/reset.h | 49 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 102 insertions(+) (limited to 'drivers') diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index fe4cebf54f1..c199e3e5da7 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -13,6 +13,7 @@ #include #include #include +#include static inline struct reset_ops *reset_dev_ops(struct udevice *dev) { @@ -225,6 +226,39 @@ int reset_deassert_bulk(struct reset_ctl_bulk *bulk) return 0; } +int reset_reset(struct reset_ctl *reset_ctl, ulong delay_us) +{ + struct reset_ops *ops = reset_dev_ops(reset_ctl->dev); + int ret; + + debug("%s(reset_ctl=%p, delay_us=%lu)\n", __func__, reset_ctl, + delay_us); + + if (ops->rst_reset) + return ops->rst_reset(reset_ctl, delay_us); + + ret = reset_assert(reset_ctl); + if (ret < 0) + return ret; + + udelay(delay_us); + + return reset_deassert(reset_ctl); +} + +int reset_reset_bulk(struct reset_ctl_bulk *bulk, ulong delay_us) +{ + int i, ret; + + for (i = 0; i < bulk->count; i++) { + ret = reset_reset(&bulk->resets[i], delay_us); + if (ret < 0) + return ret; + } + + return 0; +} + int reset_status(struct reset_ctl *reset_ctl) { struct reset_ops *ops = reset_dev_ops(reset_ctl->dev); diff --git a/include/reset-uclass.h b/include/reset-uclass.h index 9a0696dd1e3..7af090b60b5 100644 --- a/include/reset-uclass.h +++ b/include/reset-uclass.h @@ -76,6 +76,25 @@ struct reset_ops { * @return 0 if OK, or a negative error code. */ int (*rst_deassert)(struct reset_ctl *reset_ctl); + /** + * rst_reset - Reset a HW module. + * + * This optional function triggers a reset pulse on the reset line. + * If not implemented, reset_reset() falls back to rst_assert(), + * udelay(@delay_us), then rst_deassert(); that delay is therefore + * observed only on the fallback path. + * + * When rst_reset is provided, @delay_us is controller-specific: the + * implementation should honour it if the hardware needs a minimum + * assertion time before release. It may ignore @delay_us when the + * pulse shape is fixed elsewhere (for example a firmware pulse). + * + * @reset_ctl: The reset signal to pulse. + * @delay_us: Minimum delay in microseconds between assert and + * deassert where applicable; see above. + * @return 0 if OK, or a negative error code. + */ + int (*rst_reset)(struct reset_ctl *reset_ctl, ulong delay_us); /** * rst_status - Check reset signal status. * diff --git a/include/reset.h b/include/reset.h index 036a786d2ac..58574b983f6 100644 --- a/include/reset.h +++ b/include/reset.h @@ -320,6 +320,45 @@ int reset_deassert(struct reset_ctl *reset_ctl); */ int reset_deassert_bulk(struct reset_ctl_bulk *bulk); +/** + * reset_reset - Reset a HW module by asserting and deasserting a reset signal. + * + * This function will assert and then deassert the specified reset signal, + * thus resetting the affected HW module. This is a convenience function + * that combines reset_assert() and reset_deassert(). + * + * If the controller implements struct reset_ops.rst_reset, that callback + * is used and @delay_us is interpreted as documented there. Otherwise the + * core performs reset_assert(), udelay(@delay_us), then reset_deassert(). + * + * @reset_ctl: A reset control struct that was previously successfully + * requested by reset_get_by_*(). + * @delay_us: Delay in microseconds between assert and deassert on the + * fallback path; meaning is driver-specific when rst_reset is used. + * Use 0 for no delay on the fallback path. + * Return: 0 if OK, or a negative error code. + */ +int reset_reset(struct reset_ctl *reset_ctl, ulong delay_us); + +/** + * reset_reset_bulk - Reset all HW modules in a reset control bulk struct. + * + * This calls reset_reset() on each entry in order. Each line therefore + * completes its own assert/delay/deassert (or controller rst_reset) before + * the next entry starts. That matches Linux reset_control_bulk_reset(). + * + * When several lines must stay asserted together for @delay_us (typical + * multi-reset controllers), use reset_assert_bulk(), udelay(@delay_us), + * and reset_deassert_bulk() instead. + * + * @bulk: A reset control bulk struct that was previously successfully + * requested by reset_get_bulk(). + * @delay_us: Delay in microseconds passed to each reset_reset(); see + * reset_reset() and struct reset_ops.rst_reset. + * Return: 0 if OK, or a negative error code. + */ +int reset_reset_bulk(struct reset_ctl_bulk *bulk, ulong delay_us); + /** * rst_status - Check reset signal status. * @@ -443,6 +482,16 @@ static inline int reset_deassert_bulk(struct reset_ctl_bulk *bulk) return 0; } +static inline int reset_reset(struct reset_ctl *reset_ctl, ulong delay_us) +{ + return -ENOSYS; +} + +static inline int reset_reset_bulk(struct reset_ctl_bulk *bulk, ulong delay_us) +{ + return -ENOSYS; +} + static inline int reset_status(struct reset_ctl *reset_ctl) { return -ENOTSUPP; -- cgit v1.3.1 From 724d3cafe3ba8a2b3007c579bf52cd0612e6c565 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 25 May 2026 13:45:43 +0200 Subject: reset: Add sandbox tests for reset_reset() and reset_reset_bulk() Add DM test coverage for the new reset_reset() and reset_reset_bulk() API functions. The sandbox reset driver implements rst_reset so these tests exercise that op (not the assert/udelay/deassert fallback in reset_reset()). reset_reset_bulk() calls reset_reset() on each bulk entry in order, so each line's rst_reset runs in sequence. Reviewed-by: Simon Glass Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/be5411daf0de8eb64fbddf06e8ad82f50066e811.1779709539.git.michal.simek@amd.com --- arch/sandbox/include/asm/reset.h | 3 ++ drivers/reset/sandbox-reset-test.c | 14 ++++++++ drivers/reset/sandbox-reset.c | 31 ++++++++++++++++++ test/dm/reset.c | 67 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 115 insertions(+) (limited to 'drivers') diff --git a/arch/sandbox/include/asm/reset.h b/arch/sandbox/include/asm/reset.h index f0709b41c09..2890e0dc09b 100644 --- a/arch/sandbox/include/asm/reset.h +++ b/arch/sandbox/include/asm/reset.h @@ -10,6 +10,7 @@ struct udevice; int sandbox_reset_query(struct udevice *dev, unsigned long id); int sandbox_reset_is_requested(struct udevice *dev, unsigned long id); +int sandbox_reset_get_count(struct udevice *dev, unsigned long id); int sandbox_reset_test_get(struct udevice *dev); int sandbox_reset_test_get_devm(struct udevice *dev); @@ -19,6 +20,8 @@ int sandbox_reset_test_assert(struct udevice *dev); int sandbox_reset_test_assert_bulk(struct udevice *dev); int sandbox_reset_test_deassert(struct udevice *dev); int sandbox_reset_test_deassert_bulk(struct udevice *dev); +int sandbox_reset_test_reset(struct udevice *dev); +int sandbox_reset_test_reset_bulk(struct udevice *dev); int sandbox_reset_test_free(struct udevice *dev); int sandbox_reset_test_release_bulk(struct udevice *dev); diff --git a/drivers/reset/sandbox-reset-test.c b/drivers/reset/sandbox-reset-test.c index dfacb764bc7..64c205596c5 100644 --- a/drivers/reset/sandbox-reset-test.c +++ b/drivers/reset/sandbox-reset-test.c @@ -96,6 +96,20 @@ int sandbox_reset_test_deassert_bulk(struct udevice *dev) return reset_deassert_bulk(sbrt->bulkp); } +int sandbox_reset_test_reset(struct udevice *dev) +{ + struct sandbox_reset_test *sbrt = dev_get_priv(dev); + + return reset_reset(sbrt->ctlp, 0); +} + +int sandbox_reset_test_reset_bulk(struct udevice *dev) +{ + struct sandbox_reset_test *sbrt = dev_get_priv(dev); + + return reset_reset_bulk(sbrt->bulkp, 0); +} + int sandbox_reset_test_free(struct udevice *dev) { struct sandbox_reset_test *sbrt = dev_get_priv(dev); diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c index 1c0ea7390df..458c332071f 100644 --- a/drivers/reset/sandbox-reset.c +++ b/drivers/reset/sandbox-reset.c @@ -9,12 +9,14 @@ #include #include #include +#include #define SANDBOX_RESET_SIGNALS 101 struct sandbox_reset_signal { bool asserted; bool requested; + int reset_count; }; struct sandbox_reset { @@ -31,6 +33,7 @@ static int sandbox_reset_request(struct reset_ctl *reset_ctl) return -EINVAL; sbr->signals[reset_ctl->id].requested = true; + sbr->signals[reset_ctl->id].reset_count = 0; return 0; } @@ -66,6 +69,21 @@ static int sandbox_reset_deassert(struct reset_ctl *reset_ctl) return 0; } +static int sandbox_reset_reset(struct reset_ctl *reset_ctl, ulong delay_us) +{ + struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev); + + debug("%s(reset_ctl=%p, delay_us=%lu)\n", __func__, reset_ctl, + delay_us); + + sbr->signals[reset_ctl->id].asserted = true; + udelay(delay_us); + sbr->signals[reset_ctl->id].asserted = false; + sbr->signals[reset_ctl->id].reset_count++; + + return 0; +} + static int sandbox_reset_bind(struct udevice *dev) { debug("%s(dev=%p)\n", __func__, dev); @@ -90,6 +108,7 @@ static const struct reset_ops sandbox_reset_reset_ops = { .rfree = sandbox_reset_free, .rst_assert = sandbox_reset_assert, .rst_deassert = sandbox_reset_deassert, + .rst_reset = sandbox_reset_reset, }; U_BOOT_DRIVER(sandbox_reset) = { @@ -125,3 +144,15 @@ int sandbox_reset_is_requested(struct udevice *dev, unsigned long id) return sbr->signals[id].requested; } + +int sandbox_reset_get_count(struct udevice *dev, unsigned long id) +{ + struct sandbox_reset *sbr = dev_get_priv(dev); + + debug("%s(dev=%p, id=%ld)\n", __func__, dev, id); + + if (id >= SANDBOX_RESET_SIGNALS) + return -EINVAL; + + return sbr->signals[id].reset_count; +} diff --git a/test/dm/reset.c b/test/dm/reset.c index dceb6a1dad3..043d7cb7e0f 100644 --- a/test/dm/reset.c +++ b/test/dm/reset.c @@ -120,6 +120,73 @@ static int dm_test_reset_devm(struct unit_test_state *uts) } DM_TEST(dm_test_reset_devm, UTF_SCAN_FDT); +static int dm_test_reset_reset(struct unit_test_state *uts) +{ + struct udevice *dev_reset; + struct udevice *dev_test; + + ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "reset-ctl", + &dev_reset)); + ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID)); + + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test", + &dev_test)); + ut_assertok(sandbox_reset_test_get(dev_test)); + + /* Verify reset_count starts at 0 */ + ut_asserteq(0, sandbox_reset_get_count(dev_reset, TEST_RESET_ID)); + + ut_assertok(sandbox_reset_test_assert(dev_test)); + ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID)); + + ut_assertok(sandbox_reset_test_reset(dev_test)); + + /* Verify reset was pulsed (count incremented) */ + ut_asserteq(1, sandbox_reset_get_count(dev_reset, TEST_RESET_ID)); + ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID)); + + ut_assertok(sandbox_reset_test_free(dev_test)); + + return 0; +} +DM_TEST(dm_test_reset_reset, UTF_SCAN_FDT); + +static int dm_test_reset_reset_bulk(struct unit_test_state *uts) +{ + struct udevice *dev_reset; + struct udevice *dev_test; + + ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "reset-ctl", + &dev_reset)); + ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID)); + ut_asserteq(0, sandbox_reset_query(dev_reset, OTHER_RESET_ID)); + + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test", + &dev_test)); + ut_assertok(sandbox_reset_test_get_bulk(dev_test)); + + /* Verify reset_count starts at 0 */ + ut_asserteq(0, sandbox_reset_get_count(dev_reset, TEST_RESET_ID)); + ut_asserteq(0, sandbox_reset_get_count(dev_reset, OTHER_RESET_ID)); + + ut_assertok(sandbox_reset_test_assert_bulk(dev_test)); + ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID)); + ut_asserteq(1, sandbox_reset_query(dev_reset, OTHER_RESET_ID)); + + ut_assertok(sandbox_reset_test_reset_bulk(dev_test)); + + /* Verify resets were pulsed (counts incremented) */ + ut_asserteq(1, sandbox_reset_get_count(dev_reset, TEST_RESET_ID)); + ut_asserteq(1, sandbox_reset_get_count(dev_reset, OTHER_RESET_ID)); + ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID)); + ut_asserteq(0, sandbox_reset_query(dev_reset, OTHER_RESET_ID)); + + ut_assertok(sandbox_reset_test_release_bulk(dev_test)); + + return 0; +} +DM_TEST(dm_test_reset_reset_bulk, UTF_SCAN_FDT); + static int dm_test_reset_bulk(struct unit_test_state *uts) { struct udevice *dev_reset; -- cgit v1.3.1 From 4e3f64c7cc0c6a5defdceb485313b8a33f231f10 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 25 May 2026 13:45:44 +0200 Subject: reset: sandbox: Cover reset_reset() fallback with second sandbox provider Add a sandbox reset controller compatible string "sandbox,reset-ctl-fallback-only" that reuses the existing sandbox assert, deassert, request, and free helpers but omits rst_reset. That forces reset_reset() through the core assert / udelay / deassert fallback. Extend the reset-ctl-test DT node with a fifth reset line named "fallback" that points at the new provider, and add dm_test_reset_reset_fallback_path which verifies sandbox_reset_get_count() stays zero (rst_reset is never invoked) while the line ends deasserted after reset_reset(). This complements the existing rst_reset coverage on sandbox,reset-ctl and matches the approach of using a separate controller to exercise the fallback path in unit tests. Reviewed-by: Simon Glass Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c1d40db6e2332a8b23ba842385b3f8c3d0290109.1779709539.git.michal.simek@amd.com --- arch/sandbox/dts/test.dts | 10 ++++++++-- drivers/reset/sandbox-reset.c | 27 +++++++++++++++++++++++++++ test/dm/reset.c | 40 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 75 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 0887de4333b..074e5c06ec8 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1530,10 +1530,16 @@ #reset-cells = <1>; }; + resetc_fb: reset-ctl-fallback { + compatible = "sandbox,reset-ctl-fallback-only"; + #reset-cells = <1>; + }; + reset-ctl-test { compatible = "sandbox,reset-ctl-test"; - resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>; - reset-names = "other", "test", "test2", "test3"; + resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>, + <&resetc_fb 5>; + reset-names = "other", "test", "test2", "test3", "fallback"; }; rng { diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c index 458c332071f..12812f0f340 100644 --- a/drivers/reset/sandbox-reset.c +++ b/drivers/reset/sandbox-reset.c @@ -121,6 +121,33 @@ U_BOOT_DRIVER(sandbox_reset) = { .ops = &sandbox_reset_reset_ops, }; +/* + * Second sandbox reset controller for tests: same assert/deassert + * behaviour as sandbox_reset, but no rst_reset so reset_reset() uses + * the core assert / udelay / deassert fallback (reset_count never bumps). + */ +static const struct udevice_id sandbox_reset_fallback_ids[] = { + { .compatible = "sandbox,reset-ctl-fallback-only" }, + { } +}; + +static const struct reset_ops sandbox_reset_fallback_reset_ops = { + .request = sandbox_reset_request, + .rfree = sandbox_reset_free, + .rst_assert = sandbox_reset_assert, + .rst_deassert = sandbox_reset_deassert, +}; + +U_BOOT_DRIVER(sandbox_reset_fallback) = { + .name = "sandbox_reset_fallback", + .id = UCLASS_RESET, + .of_match = sandbox_reset_fallback_ids, + .bind = sandbox_reset_bind, + .probe = sandbox_reset_probe, + .priv_auto = sizeof(struct sandbox_reset), + .ops = &sandbox_reset_fallback_reset_ops, +}; + int sandbox_reset_query(struct udevice *dev, unsigned long id) { struct sandbox_reset *sbr = dev_get_priv(dev); diff --git a/test/dm/reset.c b/test/dm/reset.c index 043d7cb7e0f..91fa7ff723b 100644 --- a/test/dm/reset.c +++ b/test/dm/reset.c @@ -19,6 +19,9 @@ /* This is the other reset phandle specifier handled by bulk */ #define OTHER_RESET_ID 2 +/* Line on reset-ctl-fallback (sandbox,reset-ctl-fallback-only); see test.dts */ +#define FALLBACK_RESET_ID 5 + /* Base test of the reset uclass */ static int dm_test_reset_base(struct unit_test_state *uts) { @@ -151,6 +154,43 @@ static int dm_test_reset_reset(struct unit_test_state *uts) } DM_TEST(dm_test_reset_reset, UTF_SCAN_FDT); +/* + * reset_reset() fallback path: controller has no rst_reset op, so the + * core does assert -> udelay -> deassert. rst_reset-only accounting + * (reset_count) stays zero. Leave the line asserted before reset_reset() + * so we verify the fallback actually pulses it back to deasserted. + */ +static int dm_test_reset_reset_fallback_path(struct unit_test_state *uts) +{ + struct udevice *dev_reset_fb; + struct udevice *dev_test; + struct reset_ctl ctl; + + ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "reset-ctl-fallback", + &dev_reset_fb)); + ut_asserteq(0, sandbox_reset_query(dev_reset_fb, FALLBACK_RESET_ID)); + ut_asserteq(0, sandbox_reset_get_count(dev_reset_fb, FALLBACK_RESET_ID)); + + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test", + &dev_test)); + ut_assertok(reset_get_by_name(dev_test, "fallback", &ctl)); + ut_asserteq_ptr(ctl.dev, dev_reset_fb); + ut_asserteq(FALLBACK_RESET_ID, ctl.id); + + ut_assertok(reset_assert(&ctl)); + ut_asserteq(1, sandbox_reset_query(dev_reset_fb, FALLBACK_RESET_ID)); + ut_asserteq(0, sandbox_reset_get_count(dev_reset_fb, FALLBACK_RESET_ID)); + + ut_assertok(reset_reset(&ctl, 1)); + ut_asserteq(0, sandbox_reset_get_count(dev_reset_fb, FALLBACK_RESET_ID)); + ut_asserteq(0, sandbox_reset_query(dev_reset_fb, FALLBACK_RESET_ID)); + + ut_assertok(reset_free(&ctl)); + + return 0; +} +DM_TEST(dm_test_reset_reset_fallback_path, UTF_SCAN_FDT); + static int dm_test_reset_reset_bulk(struct unit_test_state *uts) { struct udevice *dev_reset; -- cgit v1.3.1 From f59b7a010e2e29d0e2890ec1e60fd0b3f0714ec0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 25 May 2026 13:45:45 +0200 Subject: spi: cadence: Use reset_reset_bulk() for proper reset cycling Use the new reset_reset_bulk() API to properly cycle reset signals during probe instead of just deasserting them. This ensures the controller is properly reset before initialization. Reviewed-by: Simon Glass Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/92e614075d2c4820d3e4485aa0bdda11efd1f7ca.1779709539.git.michal.simek@amd.com --- drivers/spi/cadence_qspi.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 2a4a49c5f1c..984d4a39ded 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -31,6 +31,8 @@ #define CQSPI_DISABLE_STIG_MODE BIT(0) #define CQSPI_DMA_MODE BIT(1) +#define CQSPI_RESET_DELAY_US 10 + __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, const struct spi_mem_op *op) { @@ -256,19 +258,9 @@ static int cadence_spi_probe(struct udevice *bus) priv->resets = devm_reset_bulk_get_optional(bus); if (priv->resets) { - /* Assert all OSPI reset lines */ - ret = reset_assert_bulk(priv->resets); - if (ret) { - dev_err(bus, "Failed to assert OSPI reset: %d\n", ret); - return ret; - } - - udelay(10); - - /* Deassert all OSPI reset lines */ - ret = reset_deassert_bulk(priv->resets); + ret = reset_reset_bulk(priv->resets, CQSPI_RESET_DELAY_US); if (ret) { - dev_err(bus, "Failed to deassert OSPI reset: %d\n", ret); + dev_err(bus, "Failed to reset OSPI: %d\n", ret); return ret; } } -- cgit v1.3.1 From 8efa173b389e5cef6eece991351442baea0264fd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 25 May 2026 13:45:46 +0200 Subject: reset: zynqmp: Implement rst_reset using PM_RESET_ACTION_PULSE Implement the rst_reset operation in the ZynqMP reset driver to use PM_RESET_ACTION_PULSE. This allows the reset controller to perform a reset pulse in a single firmware call instead of separate assert and deassert calls. This matches the Linux kernel implementation of zynqmp_reset_reset(). Reviewed-by: Simon Glass Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/be77d6f1b60f591ef626c14229d85c5cab867967.1779709539.git.michal.simek@amd.com --- drivers/reset/reset-zynqmp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c index d04e8eef3bb..2b58f3a75b4 100644 --- a/drivers/reset/reset-zynqmp.c +++ b/drivers/reset/reset-zynqmp.c @@ -45,6 +45,16 @@ static int zynqmp_reset_deassert(struct reset_ctl *rst) PM_RESET_ACTION_RELEASE); } +static int zynqmp_reset_reset(struct reset_ctl *rst, ulong delay_us) +{ + struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev); + + dev_dbg(rst->dev, "%s(rst=%p) (id=%lu)\n", __func__, rst, rst->id); + + return zynqmp_pm_reset_assert(priv->reset_id + rst->id, + PM_RESET_ACTION_PULSE); +} + static int zynqmp_reset_request(struct reset_ctl *rst) { struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev); @@ -74,6 +84,7 @@ const struct reset_ops zynqmp_reset_ops = { .request = zynqmp_reset_request, .rst_assert = zynqmp_reset_assert, .rst_deassert = zynqmp_reset_deassert, + .rst_reset = zynqmp_reset_reset, }; static const struct udevice_id zynqmp_reset_ids[] = { -- cgit v1.3.1 From 2ea4d3f8a545c70697fe3ce25090d02bec38ec38 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Tue, 16 Dec 2025 17:14:38 +1300 Subject: watchdog: orion_wdt: Add support for armada-xp Update the orion_wdt.c to support armada-xp and similar SoCs. The WDT block used in armada-xp is fairly close to the armada-380 with just a few differences that can be handled based on the compatible property. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- drivers/watchdog/orion_wdt.c | 99 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 93 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c index a2000b968c9..5e89303d284 100644 --- a/drivers/watchdog/orion_wdt.c +++ b/drivers/watchdog/orion_wdt.c @@ -40,8 +40,14 @@ struct orion_wdt_priv { #define TIMER_A370_STATUS 0x04 #define WDT_AXP_FIXED_ENABLE_BIT BIT(10) +#define TIMER1_FIXED_ENABLE_BIT BIT(12) #define WDT_A370_EXPIRED BIT(31) +struct orion_watchdog_data { + int (*plat_start)(struct udevice *dev, u64 timeout, ulong flags); + int (*plat_stop)(struct udevice *dev); +}; + static int orion_wdt_reset(struct udevice *dev) { struct orion_wdt_priv *priv = dev_get_priv(dev); @@ -53,7 +59,59 @@ static int orion_wdt_reset(struct udevice *dev) return 0; } -static int orion_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +static int armadaxp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct orion_wdt_priv *priv = dev_get_priv(dev); + u32 reg; + + priv->timeout = DIV_ROUND_UP(timeout_ms, 1000); + + /* Fix the wdt and timer1 clock freqency to 25MHz */ + reg = readl(priv->reg + TIMER_CTRL); + reg |= (WDT_AXP_FIXED_ENABLE_BIT | TIMER1_FIXED_ENABLE_BIT); + writel(reg, priv->reg + TIMER_CTRL); + + /* Set watchdog duration */ + writel(priv->clk_rate * priv->timeout, + priv->reg + priv->wdt_counter_offset); + + /* Clear the watchdog expiration bit */ + reg = readl(priv->reg + TIMER_A370_STATUS); + reg &= ~WDT_A370_EXPIRED; + writel(reg, priv->reg + TIMER_A370_STATUS); + + /* Enable watchdog timer */ + reg = readl(priv->reg + TIMER_CTRL); + reg |= WDT_ENABLE_BIT; + writel(reg, priv->reg + TIMER_CTRL); + + /* Enable reset on watchdog */ + reg = readl(priv->rstout); + reg |= RSTOUT_ENABLE_BIT; + writel(reg, priv->rstout); + + return 0; +} + +static int armadaxp_wdt_stop(struct udevice *dev) +{ + struct orion_wdt_priv *priv = dev_get_priv(dev); + u32 reg; + + /* Disable reset on watchdog */ + reg = readl(priv->rstout); + reg &= ~RSTOUT_ENABLE_BIT; + writel(reg, priv->rstout); + + /* Disable watchdog timer */ + reg = readl(priv->reg + TIMER_CTRL); + reg &= ~WDT_ENABLE_BIT; + writel(reg, priv->reg + TIMER_CTRL); + + return 0; +} + +static int armada380_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { struct orion_wdt_priv *priv = dev_get_priv(dev); u32 reg; @@ -91,7 +149,7 @@ static int orion_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) return 0; } -static int orion_wdt_stop(struct udevice *dev) +static int armada380_wdt_stop(struct udevice *dev) { struct orion_wdt_priv *priv = dev_get_priv(dev); u32 reg; @@ -113,6 +171,22 @@ static int orion_wdt_stop(struct udevice *dev) return 0; } +static int orion_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct orion_watchdog_data *data = + (struct orion_watchdog_data *)dev_get_driver_data(dev); + + return data->plat_start(dev, timeout_ms, flags); +} + +static int orion_wdt_stop(struct udevice *dev) +{ + struct orion_watchdog_data *data = + (struct orion_watchdog_data *)dev_get_driver_data(dev); + + return data->plat_stop(dev); +} + static inline bool save_reg_from_ofdata(struct udevice *dev, int index, void __iomem **reg, int *offset) { @@ -141,8 +215,10 @@ static int orion_wdt_of_to_plat(struct udevice *dev) if (!save_reg_from_ofdata(dev, 1, &priv->rstout, NULL)) goto err; - if (!save_reg_from_ofdata(dev, 2, &priv->rstout_mask, NULL)) - goto err; + if (device_is_compatible(dev, "marvell,armada-380-wdt")) { + if (!save_reg_from_ofdata(dev, 2, &priv->rstout_mask, NULL)) + goto err; + } return 0; err: @@ -173,9 +249,20 @@ static const struct wdt_ops orion_wdt_ops = { .stop = orion_wdt_stop, }; +static struct orion_watchdog_data armada380_data = { + .plat_start = armada380_wdt_start, + .plat_stop = armada380_wdt_stop, +}; + +static struct orion_watchdog_data armadaxp_data = { + .plat_start = armadaxp_wdt_start, + .plat_stop = armadaxp_wdt_stop, +}; + static const struct udevice_id orion_wdt_ids[] = { - { .compatible = "marvell,armada-380-wdt" }, - {} + { .compatible = "marvell,armada-380-wdt", .data = (ulong)&armada380_data}, + { .compatible = "marvell,armada-xp-wdt", .data = (ulong)&armadaxp_data}, + { } }; U_BOOT_DRIVER(orion_wdt) = { -- cgit v1.3.1 From d98e11bcbcbde2d7448a30cec45d80a9215d3f98 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 16 Mar 2026 19:24:48 -0600 Subject: watchdog: Correct dependencies for WDT_MAX6370 As exposed by "make randconfig", we have an issue with the dependencies for WDT_MAX6370. It needs to select both GPIO and DM_GPIO not just DM_GPIO. Signed-off-by: Tom Rini --- drivers/watchdog/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 9ea617f1e43..0e6e6830fc8 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -217,6 +217,7 @@ config SPL_WDT_GPIO config WDT_MAX6370 bool "MAX6370 watchdog timer support" depends on WDT + select GPIO select DM_GPIO help Select this to enable max6370 watchdog timer. -- cgit v1.3.1 From d62801d09441acfebe2c8b7da66de70e6e5ad492 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 22 Mar 2026 21:39:55 +0000 Subject: watchdog: designware: Fix probe when clk_enable return ENOSYS Rockchip SoCs typically reset with all (or most) clocks ungated. Because of this, U-Boot clock drivers for Rockchip typically do not implement the optional clk-uclass enable/disable ops. Normal driver model behavior is to return -ENOSYS when an uclass ops is not implemented. Ignore -ENOSYS to allow the designware watchdog driver to be probed on platforms that do not implement the clk-uclass enable/disable ops, e.g. Rockchip RK3308. Signed-off-by: Jonas Karlman --- drivers/watchdog/designware_wdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index bd9d7105366..91228de5e8e 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -122,7 +122,7 @@ static int designware_wdt_probe(struct udevice *dev) return ret; ret = clk_enable(&clk); - if (ret) + if (ret && ret != -ENOSYS) return ret; priv->clk_khz = clk_get_rate(&clk) / 1000; -- cgit v1.3.1 From 1a489a1a4375237ce1cabf7f95e2c57506350e7f Mon Sep 17 00:00:00 2001 From: Juuso Rinta Date: Mon, 4 May 2026 12:34:34 +0300 Subject: watchdog: sbsa_gwdt: clamp WOR value to hw max The WOR register is 32 bits, so any tick count exceeding U32_MAX is truncated by writel(). A large requested timeout can wrap to a small value causing the watchdog to fire sooner than requested. Clamp the calculated value to U32_MAX prior to writing the register so over-large requests will be set to the maximum timeout value. Found by code review. Signed-off-by: Juuso Rinta Reviewed-by: Stefan Roese --- drivers/watchdog/sbsa_gwdt.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c index 807884c5bc7..3a924cb2b9a 100644 --- a/drivers/watchdog/sbsa_gwdt.c +++ b/drivers/watchdog/sbsa_gwdt.c @@ -50,6 +50,7 @@ static int sbsa_gwdt_start(struct udevice *dev, u64 timeout, ulong flags) { struct sbsa_gwdt_priv *priv = dev_get_priv(dev); u32 clk; + u64 tout_wdog; /* * it work in the single stage mode in u-boot, @@ -58,8 +59,13 @@ static int sbsa_gwdt_start(struct udevice *dev, u64 timeout, ulong flags) * to half value of timeout. */ clk = get_tbclk(); - writel(clk / (2 * 1000) * timeout, - priv->reg_control + SBSA_GWDT_WOR); + + /* if requested timeout overflows, clamp it to u32_max */ + tout_wdog = ((u64)clk * timeout) / (2 * 1000); + if (tout_wdog > U32_MAX) + tout_wdog = U32_MAX; + + writel(tout_wdog, priv->reg_control + SBSA_GWDT_WOR); /* writing WCS will cause an explicit watchdog refresh */ writel(SBSA_GWDT_WCS_EN, priv->reg_control + SBSA_GWDT_WCS); -- cgit v1.3.1 From 9124bf185ba6206dd2286a78addd74a5449bd9c3 Mon Sep 17 00:00:00 2001 From: Juuso Rinta Date: Mon, 4 May 2026 12:36:58 +0300 Subject: watchdog: octeontx_wdt: fix DT matches to Marvell compatibles The OcteonTX watchdog driver currently matches arm,sbsa-gwdt. On systems with multiple watchdog devices this can be ambiguous since arm,sbsa-gwdt is a generic SBSA binding. Replace the SBSA match with SoC-specific Marvell compatibles marvell,cn10624-wdt and marvell,cn9670-wdt. These compatibles align with the upstream Linux device tree binding: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/watchdog/marvell,cn10624-wdt.yaml Reviewed-by: Aaro Koskinen Signed-off-by: Juuso Rinta Reviewed-by: Stefan Roese --- drivers/watchdog/octeontx_wdt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/watchdog/octeontx_wdt.c b/drivers/watchdog/octeontx_wdt.c index c79d9539c13..7299a9f9739 100644 --- a/drivers/watchdog/octeontx_wdt.c +++ b/drivers/watchdog/octeontx_wdt.c @@ -159,7 +159,8 @@ static const struct octeontx_wdt_data octeon_data = { }; static const struct udevice_id octeontx_wdt_ids[] = { - { .compatible = "arm,sbsa-gwdt", .data = (ulong)&octeontx_data }, + { .compatible = "marvell,cn10624-wdt", .data = (ulong)&octeontx_data }, + { .compatible = "marvell,cn9670-wdt", .data = (ulong)&octeontx_data }, { .compatible = "cavium,octeon-7890-ciu3", .data = (ulong)&octeon_data }, {} }; -- cgit v1.3.1 From 3c3ba75c852e68d5f9a9b388935254a2b3e13bd3 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 11:51:47 +0800 Subject: watchdog: orion_wdt: use dev_read_addr_size_index() Replace devfdt_read_addr_size_index() with dev_read_addr_size_index() when retrieving the register base address. dev_read_addr_size_index() supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan Reviewed-by: Stefan Roese --- drivers/watchdog/orion_wdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c index 5e89303d284..5a6cad135aa 100644 --- a/drivers/watchdog/orion_wdt.c +++ b/drivers/watchdog/orion_wdt.c @@ -193,7 +193,7 @@ static inline bool save_reg_from_ofdata(struct udevice *dev, int index, fdt_addr_t addr; fdt_size_t off; - addr = devfdt_get_addr_size_index(dev, index, &off); + addr = dev_read_addr_size_index(dev, index, &off); if (addr == FDT_ADDR_T_NONE) return false; -- cgit v1.3.1 From b9b27c875f664a42967941bc33dbbaa441f12250 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 11:51:48 +0800 Subject: watchdog: rti: Use dev_read_addr_ptr() devfdt_get_addr() returns FDT_ADDR_T_NONE(-1UL) when fail, using "!priv->regs" to check return value is wrong. Replace devfdt_read_addr() with dev_read_addr_ptr() when retrieving the register base address. dev_read_addr_ptr() supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. Also use "void __iomem *" to replace "phys_addr_t" to avoid type casting. No functional changes. Signed-off-by: Peng Fan Reviewed-by: Stefan Roese --- drivers/watchdog/rti_wdt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/rti_wdt.c b/drivers/watchdog/rti_wdt.c index 7b387266b99..866f555789c 100644 --- a/drivers/watchdog/rti_wdt.c +++ b/drivers/watchdog/rti_wdt.c @@ -39,7 +39,7 @@ #define WDT_PRELOAD_MAX 0xfff struct rti_wdt_priv { - phys_addr_t regs; + void __iomem *regs; unsigned int clk_hz; }; @@ -177,7 +177,7 @@ static int rti_wdt_probe(struct udevice *dev) struct clk clk; int ret; - priv->regs = devfdt_get_addr(dev); + priv->regs = dev_read_addr_ptr(dev); if (!priv->regs) return -EINVAL; -- cgit v1.3.1 From 5843db9dada474aec1d29a149a681657677ed89a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 11:51:49 +0800 Subject: watchdog: mpc8xxx_wdt: Use dev_remap_addr() Use dev_remap_addr() to replace devfdt_remap_addr which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan Reviewed-by: Stefan Roese --- drivers/watchdog/mpc8xxx_wdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index 7fcb866f574..068f99c5fc6 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -81,7 +81,7 @@ static int mpc8xxx_wdt_of_to_plat(struct udevice *dev) { struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev); - priv->base = (void __iomem *)devfdt_remap_addr(dev); + priv->base = (void __iomem *)dev_remap_addr(dev); if (!priv->base) return -EINVAL; -- cgit v1.3.1 From 17f7334c952b7db35457a9e54ba273d5364e6503 Mon Sep 17 00:00:00 2001 From: Francois Berder Date: Mon, 25 May 2026 22:33:14 +0200 Subject: drivers: watchdog: Fix dev_read_addr error check dev_read_addr does not return a void* but fdt_addr_t. Replace invalid usage of dev_read_addr by dev_read_addr_ptr. v2: - Replace dev_read_addr by dev_read_addr_ptr - Change error to EINVAL Signed-off-by: Francois Berder Reviewed-by: Stefan Roese Reviewed-by: Hal Feng --- drivers/watchdog/starfive_wdt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/watchdog/starfive_wdt.c b/drivers/watchdog/starfive_wdt.c index ee9ec4cdc3a..d2c16150f4c 100644 --- a/drivers/watchdog/starfive_wdt.c +++ b/drivers/watchdog/starfive_wdt.c @@ -290,9 +290,9 @@ static int starfive_wdt_of_to_plat(struct udevice *dev) { struct starfive_wdt_priv *wdt = dev_get_priv(dev); - wdt->base = (void *)dev_read_addr(dev); + wdt->base = dev_read_addr_ptr(dev); if (!wdt->base) - return -ENODEV; + return -EINVAL; wdt->apb_clk = devm_clk_get(dev, "apb"); if (IS_ERR(wdt->apb_clk)) -- cgit v1.3.1 From b996053fcb8bce0e69ee3931408e7c6ed3765b43 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 11:58:02 +0800 Subject: mmc: xenon_sdhci: Use livetree API Use livetree API which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Reviewed-by: Stefan Roese Signed-off-by: Peng Fan --- drivers/mmc/xenon_sdhci.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c index 0e4902fab77..6aa73792f96 100644 --- a/drivers/mmc/xenon_sdhci.c +++ b/drivers/mmc/xenon_sdhci.c @@ -537,10 +537,9 @@ static int xenon_sdhci_of_to_plat(struct udevice *dev) host->ioaddr = dev_read_addr_ptr(dev); if (device_is_compatible(dev, "marvell,armada-3700-sdhci")) - priv->pad_ctrl_reg = devfdt_get_addr_index_ptr(dev, 1); + priv->pad_ctrl_reg = dev_read_addr_index_ptr(dev, 1); - name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type", - NULL); + name = ofnode_get_property(dev_ofnode(dev), "marvell,pad-type", NULL); if (name) { if (0 == strncmp(name, "sd", 2)) { priv->pad_type = SOC_PAD_SD; -- cgit v1.3.1 From 185e4f27c8966f4b88af29d7a4e39b768018ff74 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 11:58:03 +0800 Subject: mmc: cv1800b_sdhci: Use dev_read_addr_ptr() Use dev_read_addr_ptr() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Reviewed-by: Stefan Roese Signed-off-by: Peng Fan --- drivers/mmc/cv1800b_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/cv1800b_sdhci.c b/drivers/mmc/cv1800b_sdhci.c index 72c5bfc6f35..b756649f90f 100644 --- a/drivers/mmc/cv1800b_sdhci.c +++ b/drivers/mmc/cv1800b_sdhci.c @@ -85,7 +85,7 @@ static int cv1800b_sdhci_probe(struct udevice *dev) int ret; host->name = dev->name; - host->ioaddr = devfdt_get_addr_ptr(dev); + host->ioaddr = dev_read_addr_ptr(dev); upriv->mmc = &plat->mmc; host->mmc = &plat->mmc; -- cgit v1.3.1 From cf3f7e03ff92d1f992852df771c8b489b7b8e127 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 4 Jun 2026 20:20:24 +0800 Subject: mmc: fsl_esdhc_imx: convert ofnode API to dev_read API Replace ofnode_read_*() calls with their dev_read_*() equivalents in fsl_esdhc_of_to_plat(). Remove the intermediate 'ofnode node' local variable and the now-unnecessary include. No functional change. Signed-off-by: Peng Fan --- drivers/mmc/fsl_esdhc_imx.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 87125493c0d..e718a17f94c 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include @@ -1393,7 +1392,6 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev) struct udevice *vqmmc_dev; int ret; - ofnode node = dev_ofnode(dev); fdt_addr_t addr; unsigned int val; @@ -1407,15 +1405,15 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev) priv->dev = dev; priv->mode = -1; - val = ofnode_read_u32_default(node, "fsl,tuning-step", 1); + val = dev_read_u32_default(dev, "fsl,tuning-step", 1); priv->tuning_step = val; - val = ofnode_read_u32_default(node, "fsl,tuning-start-tap", - ESDHC_TUNING_START_TAP_DEFAULT); + val = dev_read_u32_default(dev, "fsl,tuning-start-tap", + ESDHC_TUNING_START_TAP_DEFAULT); priv->tuning_start_tap = val; - val = ofnode_read_u32_default(node, "fsl,strobe-dll-delay-target", - ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT); + val = dev_read_u32_default(dev, "fsl,strobe-dll-delay-target", + ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT); priv->strobe_dll_delay_target = val; - val = ofnode_read_u32_default(node, "fsl,signal-voltage-switch-extra-delay-ms", 0); + val = dev_read_u32_default(dev, "fsl,signal-voltage-switch-extra-delay-ms", 0); priv->signal_voltage_switch_extra_delay_ms = val; if (dev_read_bool(dev, "broken-cd")) -- cgit v1.3.1 From 80aa5cbd55308170be7dda50259f26b845daa1dc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 4 Jun 2026 20:20:25 +0800 Subject: mmc: msm_sdhci: convert ofnode API to dev_read API Replace ofnode_read_u32(), ofnode_get_property() and ofnode_read_string_index() with their dev_read_*() equivalents in msm_sdc_clk_init(). Remove the intermediate 'ofnode node' local variable. No functional change. Reviewed-by: Casey Connolly Signed-off-by: Peng Fan --- drivers/mmc/msm_sdhci.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index aaa87923604..7bdb02142a2 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -64,14 +64,13 @@ static int msm_sdc_clk_init(struct udevice *dev) { struct msm_sdhc *prv = dev_get_priv(dev); const struct msm_sdhc_variant_info *var_info; - ofnode node = dev_ofnode(dev); ulong clk_rate; int ret, i = 0, n_clks; const char *clk_name; var_info = (void *)dev_get_driver_data(dev); - if (ofnode_read_u32(node, "max-frequency", (uint *)(&clk_rate))) + if (dev_read_u32(dev, "max-frequency", (uint *)(&clk_rate))) clk_rate = 201500000; ret = clk_get_bulk(dev, &prv->clks); @@ -87,7 +86,7 @@ static int msm_sdc_clk_init(struct udevice *dev) } /* If clock-names is unspecified, then the first clock is the core clock */ - if (!ofnode_get_property(node, "clock-names", &n_clks)) { + if (!dev_read_prop(dev, "clock-names", &n_clks)) { if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) { log_warning("Couldn't set core clock rate: %d\n", ret); return -EINVAL; @@ -96,7 +95,7 @@ static int msm_sdc_clk_init(struct udevice *dev) /* Find the index of the "core" clock */ while (i < n_clks) { - ofnode_read_string_index(node, "clock-names", i, &clk_name); + dev_read_string_index(dev, "clock-names", i, &clk_name); if (!strcmp(clk_name, "core")) break; i++; -- cgit v1.3.1 From 162772d59f8d8958c91bd5976f4a791b3ab7503f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 4 Jun 2026 20:20:26 +0800 Subject: mmc: octeontx_hsmmc: convert ofnode API to dev_read API Replace all ofnode_read_*() / ofnode_read_bool() / ofnode_get_property() calls with their dev_read_*() equivalents across octeontx_mmc_get_valid(), octeontx_mmc_get_config(), octeontx_mmc_host_probe() and octeontx_mmc_host_child_pre_probe(). Remove the intermediate 'ofnode node' local variables, the now-unused 'host->node' assignment in the probe function, and the corresponding 'ofnode node' field from struct octeontx_mmc_host. No functional change. Signed-off-by: Peng Fan --- drivers/mmc/octeontx_hsmmc.c | 74 ++++++++++++++++++-------------------------- drivers/mmc/octeontx_hsmmc.h | 1 - 2 files changed, 30 insertions(+), 45 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/octeontx_hsmmc.c b/drivers/mmc/octeontx_hsmmc.c index bb4fb29424b..b4942f99a52 100644 --- a/drivers/mmc/octeontx_hsmmc.c +++ b/drivers/mmc/octeontx_hsmmc.c @@ -3514,7 +3514,7 @@ static u32 xlate_voltage(u32 voltage) */ static bool octeontx_mmc_get_valid(struct udevice *dev) { - const char *stat = ofnode_read_string(dev_ofnode(dev), "status"); + const char *stat = dev_read_string(dev, "status"); if (!stat || !strncmp(stat, "ok", 2)) return true; @@ -3536,16 +3536,13 @@ static int octeontx_mmc_get_config(struct udevice *dev) uint low, high; char env_name[32]; int err; - ofnode node = dev_ofnode(dev); int bus_width = 1; ulong new_max_freq; debug("%s(%s)", __func__, dev->name); slot->cfg.name = dev->name; - slot->cfg.f_max = ofnode_read_s32_default(dev_ofnode(dev), - "max-frequency", - 26000000); + slot->cfg.f_max = dev_read_s32_default(dev, "max-frequency", 26000000); snprintf(env_name, sizeof(env_name), "mmc_max_frequency%d", slot->bus_id); @@ -3562,26 +3559,21 @@ static int octeontx_mmc_get_config(struct udevice *dev) if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) { slot->hs400_tuning_block = - ofnode_read_s32_default(dev_ofnode(dev), - "marvell,hs400-tuning-block", - -1); + dev_read_s32_default(dev, "marvell,hs400-tuning-block", -1); debug("%s(%s): mmc HS400 tuning block: %d\n", __func__, dev->name, slot->hs400_tuning_block); slot->hs200_tap_adj = - ofnode_read_s32_default(dev_ofnode(dev), - "marvell,hs200-tap-adjust", 0); + dev_read_s32_default(dev, "marvell,hs200-tap-adjust", 0); debug("%s(%s): hs200-tap-adjust: %d\n", __func__, dev->name, slot->hs200_tap_adj); slot->hs400_tap_adj = - ofnode_read_s32_default(dev_ofnode(dev), - "marvell,hs400-tap-adjust", 0); + dev_read_s32_default(dev, "marvell,hs400-tap-adjust", 0); debug("%s(%s): hs400-tap-adjust: %d\n", __func__, dev->name, slot->hs400_tap_adj); } - err = ofnode_read_u32_array(dev_ofnode(dev), "voltage-ranges", - voltages, 2); + err = dev_read_u32_array(dev, "voltage-ranges", voltages, 2); if (err) { slot->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; } else { @@ -3601,12 +3593,12 @@ static int octeontx_mmc_get_config(struct udevice *dev) } while (low <= high); } debug("%s: config voltages: 0x%x\n", __func__, slot->cfg.voltages); - slot->slew = ofnode_read_s32_default(node, "cavium,clk-slew", -1); - slot->drive = ofnode_read_s32_default(node, "cavium,drv-strength", -1); + slot->slew = dev_read_s32_default(dev, "cavium,clk-slew", -1); + slot->drive = dev_read_s32_default(dev, "cavium,drv-strength", -1); gpio_request_by_name(dev, "cd-gpios", 0, &slot->cd_gpio, GPIOD_IS_IN); - slot->cd_inverted = ofnode_read_bool(node, "cd-inverted"); + slot->cd_inverted = dev_read_bool(dev, "cd-inverted"); gpio_request_by_name(dev, "wp-gpios", 0, &slot->wp_gpio, GPIOD_IS_IN); - slot->wp_inverted = ofnode_read_bool(node, "wp-inverted"); + slot->wp_inverted = dev_read_bool(dev, "wp-inverted"); if (slot->cfg.voltages & MMC_VDD_165_195) { slot->is_1_8v = true; slot->is_3_3v = false; @@ -3617,7 +3609,7 @@ static int octeontx_mmc_get_config(struct udevice *dev) slot->is_3_3v = true; } - bus_width = ofnode_read_u32_default(node, "bus-width", 1); + bus_width = dev_read_u32_default(dev, "bus-width", 1); /* Note fall-through */ switch (bus_width) { case 8: @@ -3628,63 +3620,63 @@ static int octeontx_mmc_get_config(struct udevice *dev) slot->cfg.host_caps |= MMC_MODE_1BIT; break; } - if (ofnode_read_bool(node, "no-1-8-v")) { + if (dev_read_bool(dev, "no-1-8-v")) { slot->is_3_3v = true; slot->is_1_8v = false; if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34))) pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n", __func__, dev->name); } - if (ofnode_read_bool(node, "mmc-ddr-3-3v")) { + if (dev_read_bool(dev, "mmc-ddr-3-3v")) { slot->is_3_3v = true; slot->is_1_8v = false; if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34))) pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n", __func__, dev->name); } - if (ofnode_read_bool(node, "cap-sd-highspeed") || - ofnode_read_bool(node, "cap-mmc-highspeed") || - ofnode_read_bool(node, "sd-uhs-sdr25")) + if (dev_read_bool(dev, "cap-sd-highspeed") || + dev_read_bool(dev, "cap-mmc-highspeed") || + dev_read_bool(dev, "sd-uhs-sdr25")) slot->cfg.host_caps |= MMC_MODE_HS; if (slot->cfg.f_max >= 50000000 && slot->cfg.host_caps & MMC_MODE_HS) slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; - if (ofnode_read_bool(node, "sd-uhs-sdr50")) + if (dev_read_bool(dev, "sd-uhs-sdr50")) slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; - if (ofnode_read_bool(node, "sd-uhs-ddr50")) + if (dev_read_bool(dev, "sd-uhs-ddr50")) slot->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz; if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) { if (!slot->is_asim && !slot->is_emul) { - if (ofnode_read_bool(node, "mmc-hs200-1_8v")) + if (dev_read_bool(dev, "mmc-hs200-1_8v")) slot->cfg.host_caps |= MMC_MODE_HS200 | MMC_MODE_HS_52MHz; - if (ofnode_read_bool(node, "mmc-hs400-1_8v")) + if (dev_read_bool(dev, "mmc-hs400-1_8v")) slot->cfg.host_caps |= MMC_MODE_HS400 | MMC_MODE_HS_52MHz | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz; slot->cmd_out_hs200_delay = - ofnode_read_u32_default(node, + dev_read_u32_default(dev, "marvell,cmd-out-hs200-dly", MMC_DEFAULT_HS200_CMD_OUT_DLY); debug("%s(%s): HS200 cmd out delay: %d\n", __func__, dev->name, slot->cmd_out_hs200_delay); slot->data_out_hs200_delay = - ofnode_read_u32_default(node, + dev_read_u32_default(dev, "marvell,data-out-hs200-dly", MMC_DEFAULT_HS200_DATA_OUT_DLY); debug("%s(%s): HS200 data out delay: %d\n", __func__, dev->name, slot->data_out_hs200_delay); slot->cmd_out_hs400_delay = - ofnode_read_u32_default(node, + dev_read_u32_default(dev, "marvell,cmd-out-hs400-dly", MMC_DEFAULT_HS400_CMD_OUT_DLY); debug("%s(%s): HS400 cmd out delay: %d\n", __func__, dev->name, slot->cmd_out_hs400_delay); slot->data_out_hs400_delay = - ofnode_read_u32_default(node, + dev_read_u32_default(dev, "marvell,data-out-hs400-dly", MMC_DEFAULT_HS400_DATA_OUT_DLY); debug("%s(%s): HS400 data out delay: %d\n", @@ -3692,12 +3684,10 @@ static int octeontx_mmc_get_config(struct udevice *dev) } } - slot->disable_ddr = ofnode_read_bool(node, "marvell,disable-ddr"); - slot->non_removable = ofnode_read_bool(node, "non-removable"); - slot->cmd_clk_skew = ofnode_read_u32_default(node, - "cavium,cmd-clk-skew", 0); - slot->dat_clk_skew = ofnode_read_u32_default(node, - "cavium,dat-clk-skew", 0); + slot->disable_ddr = dev_read_bool(dev, "marvell,disable-ddr"); + slot->non_removable = dev_read_bool(dev, "non-removable"); + slot->cmd_clk_skew = dev_read_u32_default(dev, "cavium,cmd-clk-skew", 0); + slot->dat_clk_skew = dev_read_u32_default(dev, "cavium,dat-clk-skew", 0); debug("%s(%s): host caps: 0x%x\n", __func__, dev->name, slot->cfg.host_caps); return 0; @@ -3843,7 +3833,6 @@ static int octeontx_mmc_host_probe(struct udevice *dev) pr_err("%s: No device tree information found\n", __func__); return -1; } - host->node = dev_ofnode(dev); host->last_slotid = -1; #if !defined(CONFIG_ARCH_OCTEON) if (otx_is_platform(PLATFORM_ASIM)) @@ -3851,9 +3840,7 @@ static int octeontx_mmc_host_probe(struct udevice *dev) if (otx_is_platform(PLATFORM_EMULATOR)) host->is_emul = true; #endif - host->dma_wait_delay = - ofnode_read_u32_default(dev_ofnode(dev), - "marvell,dma-wait-delay", 1); + host->dma_wait_delay = dev_read_u32_default(dev, "marvell,dma-wait-delay", 1); /* Force reset of eMMC */ writeq(0, host->base_addr + MIO_EMM_CFG()); debug("%s: Clearing MIO_EMM_CFG\n", __func__); @@ -3922,13 +3909,12 @@ static int octeontx_mmc_host_child_pre_probe(struct udevice *dev) struct octeontx_mmc_host *host = dev_get_priv(dev_get_parent(dev)); struct octeontx_mmc_slot *slot; struct mmc_uclass_priv *upriv; - ofnode node = dev_ofnode(dev); u32 bus_id; char name[16]; int err; debug("%s(%s) Pre-Probe\n", __func__, dev->name); - if (ofnode_read_u32(node, "reg", &bus_id)) { + if (dev_read_u32(dev, "reg", &bus_id)) { pr_err("%s(%s): Error: \"reg\" not found in device tree\n", __func__, dev->name); return -1; diff --git a/drivers/mmc/octeontx_hsmmc.h b/drivers/mmc/octeontx_hsmmc.h index 9849121f174..c374ce18838 100644 --- a/drivers/mmc/octeontx_hsmmc.h +++ b/drivers/mmc/octeontx_hsmmc.h @@ -123,7 +123,6 @@ struct octeontx_mmc_host { union mio_emm_cfg emm_cfg; u64 timing_taps; struct mmc *last_mmc; /** Last mmc used */ - ofnode node; int cur_slotid; int last_slotid; int max_width; -- cgit v1.3.1 From 7ab0a58e86599f9430e23af5c64c31adf4999a13 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 22 May 2026 15:14:14 +0800 Subject: power: regulator: Fix power on/off delay issue SD initialization failure happens with some UHS-I SD cards on iMX8MM/iMX93/iMX91 EVK after commit 4fcba5d556b4 ("regulator: implement basic reference counter"). When sending operation condition to SD card, the OCR does not return correct status. The root cause is regulator on/off delay is missed in MMC power cycle with above commit, so SD card is not completely power off. When SD startup, the sequence of MMC power cycle is: mmc_power_init(get vmmc_supply dev) -> mmc_power_off -> udelay(2000) -> mmc_power_on Before above commit, as a fixed regulator, the GPIO is set as: GPIO inactive (in mmc_power_init) -> GPIO inactive and delay off-on-delay-us (in mmc_power_off) -> udelay(2000) -> GPIO active (in mmc_power_on) After the commit: GPIO inactive (in mmc_power_init) -> enable_count is 0, regulator_set_enable returns -EALREADY immediately, so GPIO is inactive but No off-on-delay-us (in mmc_power_off) -> udelay(2000) -> GPIO active (in mmc_power_on) Move the off-on-delay-us delay before setting GPIO active to fix the issue. Signed-off-by: Ye Li Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/regulator/regulator_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c index 85af8d599ad..c0387eff4fc 100644 --- a/drivers/power/regulator/regulator_common.c +++ b/drivers/power/regulator/regulator_common.c @@ -87,6 +87,9 @@ int regulator_common_set_enable(const struct udevice *dev, } } + if (enable && plat->off_on_delay_us) + udelay(plat->off_on_delay_us); + ret = dm_gpio_set_value(&plat->gpio, enable); if (ret) { pr_err("Can't set regulator : %s gpio to: %d\n", dev->name, @@ -97,9 +100,6 @@ int regulator_common_set_enable(const struct udevice *dev, if (enable && plat->startup_delay_us) udelay(plat->startup_delay_us); - if (!enable && plat->off_on_delay_us) - udelay(plat->off_on_delay_us); - if (enable) plat->enable_count++; else -- cgit v1.3.1 From be9ded7803498ae875548e448870199f6563fa10 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 15:29:47 +0800 Subject: power: regulator: tps6287x: Use dev_read_addr_index() Use dev_read_addr_index() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Reviewed-by: Simon Glass Signed-off-by: Peng Fan --- drivers/power/regulator/tps6287x_regulator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/regulator/tps6287x_regulator.c b/drivers/power/regulator/tps6287x_regulator.c index 6d185719199..2e6d85f677a 100644 --- a/drivers/power/regulator/tps6287x_regulator.c +++ b/drivers/power/regulator/tps6287x_regulator.c @@ -141,7 +141,7 @@ static int tps6287x_regulator_probe(struct udevice *dev) pdata->config = (void *)dev_get_driver_data(dev); - slave_id = devfdt_get_addr_index(dev, 0); + slave_id = dev_read_addr_index(dev, 0); ret = i2c_get_chip(dev->parent, slave_id, 1, &pdata->i2c); if (ret) { -- cgit v1.3.1 From 8e873d7ad3e72ebb4b995a73e1e2b93793248abb Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 4 Jun 2026 20:20:27 +0800 Subject: power: domain: meson-ee-pwrc: use dev_read_phandle_with_args for ao-sysctrl Replace the manual ofnode_read_u32() + ofnode_get_by_phandle() sequence with a single dev_read_phandle_with_args() call to resolve the amlogic,ao-sysctrl phandle. This is cleaner and avoids the intermediate phandle value and ofnode_valid() check. No functional change. Reviewed-by: Neil Armstrong Signed-off-by: Peng Fan --- drivers/power/domain/meson-ee-pwrc.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/power/domain/meson-ee-pwrc.c b/drivers/power/domain/meson-ee-pwrc.c index 6361f3a6c59..882238f2937 100644 --- a/drivers/power/domain/meson-ee-pwrc.c +++ b/drivers/power/domain/meson-ee-pwrc.c @@ -435,8 +435,7 @@ static const struct udevice_id meson_ee_pwrc_ids[] = { static int meson_ee_pwrc_probe(struct udevice *dev) { struct meson_ee_pwrc_priv *priv = dev_get_priv(dev); - u32 ao_phandle; - ofnode ao_node; + struct ofnode_phandle_args args; int ret; priv->data = (void *)dev_get_driver_data(dev); @@ -447,16 +446,12 @@ static int meson_ee_pwrc_probe(struct udevice *dev) if (IS_ERR(priv->regmap_hhi)) return PTR_ERR(priv->regmap_hhi); - ret = ofnode_read_u32(dev_ofnode(dev), "amlogic,ao-sysctrl", - &ao_phandle); + ret = dev_read_phandle_with_args(dev, "amlogic,ao-sysctrl", NULL, 0, 0, + &args); if (ret) return ret; - ao_node = ofnode_get_by_phandle(ao_phandle); - if (!ofnode_valid(ao_node)) - return -EINVAL; - - priv->regmap_ao = syscon_node_to_regmap(ao_node); + priv->regmap_ao = syscon_node_to_regmap(args.node); if (IS_ERR(priv->regmap_ao)) return PTR_ERR(priv->regmap_ao); -- cgit v1.3.1 From 788259b6c969de9e9ffc122464aca8fc5a08c7f6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 4 Jun 2026 20:20:28 +0800 Subject: power: domain: meson-gx-pwrc-vpu: use dev_read_phandle_with_args for hhi-sysctrl Replace the manual ofnode_read_u32() + ofnode_get_by_phandle() sequence with a single dev_read_phandle_with_args() call to resolve the amlogic,hhi-sysctrl phandle. This is cleaner and avoids the intermediate phandle value and ofnode_valid() check. No functional change. Reviewed-by: Neil Armstrong Signed-off-by: Peng Fan --- drivers/power/domain/meson-gx-pwrc-vpu.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/power/domain/meson-gx-pwrc-vpu.c b/drivers/power/domain/meson-gx-pwrc-vpu.c index 325296b0dd7..e08c0fac49a 100644 --- a/drivers/power/domain/meson-gx-pwrc-vpu.c +++ b/drivers/power/domain/meson-gx-pwrc-vpu.c @@ -283,24 +283,19 @@ static const struct udevice_id meson_gx_pwrc_vpu_ids[] = { static int meson_gx_pwrc_vpu_probe(struct udevice *dev) { struct meson_gx_pwrc_vpu_priv *priv = dev_get_priv(dev); - u32 hhi_phandle; - ofnode hhi_node; + struct ofnode_phandle_args args; int ret; priv->regmap_ao = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev))); if (IS_ERR(priv->regmap_ao)) return PTR_ERR(priv->regmap_ao); - ret = ofnode_read_u32(dev_ofnode(dev), "amlogic,hhi-sysctrl", - &hhi_phandle); + ret = dev_read_phandle_with_args(dev, "amlogic,hhi-sysctrl", NULL, 0, 0, + &args); if (ret) return ret; - hhi_node = ofnode_get_by_phandle(hhi_phandle); - if (!ofnode_valid(hhi_node)) - return -EINVAL; - - priv->regmap_hhi = syscon_node_to_regmap(hhi_node); + priv->regmap_hhi = syscon_node_to_regmap(args.node); if (IS_ERR(priv->regmap_hhi)) return PTR_ERR(priv->regmap_hhi); -- cgit v1.3.1 From 2d6b735f5a9017f4c77ef522ccad64c84e0a1531 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 4 Jun 2026 20:20:29 +0800 Subject: power: domain: imx8m: convert ofnode API to dev_read API Replace ofnode_for_each_subnode(subnode, dev_ofnode(dev)) with dev_for_each_subnode(subnode, dev) and ofnode_read_u32_default( dev_ofnode(dev), ...) with dev_read_u32_default(dev, ...). No functional change. Signed-off-by: Peng Fan --- drivers/power/domain/imx8m-power-domain.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index 5fdb95fb6a7..a3ef49aa67c 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -476,7 +476,7 @@ static int imx8m_power_domain_bind(struct udevice *dev) const char *name; int ret = 0; - ofnode_for_each_subnode(subnode, dev_ofnode(dev)) { + dev_for_each_subnode(subnode, dev) { /* Bind the subnode to this driver */ name = ofnode_get_name(subnode); @@ -531,7 +531,7 @@ static int imx8m_power_domain_of_to_plat(struct udevice *dev) struct imx_pgc_domain_data *domain_data = (struct imx_pgc_domain_data *)dev_get_driver_data(dev); - pdata->resource_id = ofnode_read_u32_default(dev_ofnode(dev), "reg", -1); + pdata->resource_id = dev_read_u32_default(dev, "reg", -1); pdata->domain = &domain_data->domains[pdata->resource_id]; pdata->regs = domain_data->pgc_regs; pdata->base = dev_read_addr_ptr(dev->parent); -- cgit v1.3.1 From ddbfee1ec0975c64f219180807cd9afdc87b8d76 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 4 Jun 2026 20:20:30 +0800 Subject: power: pmic: pca9450: convert ofnode API to dev_read API Replace ofnode_read_bool(dev_ofnode(dev), ...) with dev_read_bool(dev, ...). No functional change. Signed-off-by: Peng Fan --- drivers/power/pmic/pca9450.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index c95e6357ee8..cbe8cd05be7 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -90,7 +90,7 @@ static int pca9450_probe(struct udevice *dev) return ret; } - if (ofnode_read_bool(dev_ofnode(dev), "nxp,wdog_b-warm-reset")) + if (dev_read_bool(dev, "nxp,wdog_b-warm-reset")) reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_WARM; else reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12; -- cgit v1.3.1 From 9be04779061e466089d00dc908278880cf1844d0 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 4 Jun 2026 20:20:31 +0800 Subject: power: pmic: qcom: convert ofnode API to dev_read API Replace ofnode_read_u32_index(dev_ofnode(dev), ...) with dev_read_u32_index(dev, ...). No functional change. Reviewed-by: Casey Connolly Signed-off-by: Peng Fan --- drivers/power/pmic/pmic_qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/pmic/pmic_qcom.c b/drivers/power/pmic/pmic_qcom.c index 92d0a95859b..4b8dcc6104c 100644 --- a/drivers/power/pmic/pmic_qcom.c +++ b/drivers/power/pmic/pmic_qcom.c @@ -72,7 +72,7 @@ static int pmic_qcom_probe(struct udevice *dev) * contains two discrete values, not a single 64-bit address. * The address is the first value. */ - ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, &priv->usid); + ret = dev_read_u32_index(dev, "reg", 0, &priv->usid); if (ret < 0) return -EINVAL; -- cgit v1.3.1 From 0c9b8e07fd9a10354d6516852150c60acfec3295 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 4 Jun 2026 20:20:32 +0800 Subject: power: regulator: anatop: convert ofnode API to dev_read API Replace ofnode_read_string(dev_ofnode(dev), ...) with dev_read_string(dev, ...). No functional change. Signed-off-by: Peng Fan --- drivers/power/regulator/anatop_regulator.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/power/regulator/anatop_regulator.c b/drivers/power/regulator/anatop_regulator.c index 824a753db16..88570a1f624 100644 --- a/drivers/power/regulator/anatop_regulator.c +++ b/drivers/power/regulator/anatop_regulator.c @@ -170,8 +170,7 @@ static int anatop_regulator_probe(struct udevice *dev) anatop_reg = dev_get_plat(dev); uc_pdata = dev_get_uclass_plat(dev); - anatop_reg->name = ofnode_read_string(dev_ofnode(dev), - "regulator-name"); + anatop_reg->name = dev_read_string(dev, "regulator-name"); if (!anatop_reg->name) return log_msg_ret("regulator-name", -EINVAL); -- cgit v1.3.1 From fa3544f39f3882a60338e6c78b06cbf8b0c7bc06 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 4 Jun 2026 20:20:33 +0800 Subject: power: regulator: qcom-rpmh: convert ofnode API to dev_read API Replace ofnode_read_u32(dev_ofnode(dev), ...) with dev_read_u32(dev, ...), ofnode_read_string(dev_ofnode(dev), ...) with dev_read_string(dev, ...), and ofnode_for_each_subnode(node, dev_ofnode(dev)) with dev_for_each_subnode(node, dev). No functional change. Reviewed-by: Casey Connolly Signed-off-by: Peng Fan --- drivers/power/regulator/qcom-rpmh-regulator.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/power/regulator/qcom-rpmh-regulator.c b/drivers/power/regulator/qcom-rpmh-regulator.c index 4d65aae1690..f1de660c3a0 100644 --- a/drivers/power/regulator/qcom-rpmh-regulator.c +++ b/drivers/power/regulator/qcom-rpmh-regulator.c @@ -5,6 +5,7 @@ #define pr_fmt(fmt) "%s: " fmt, __func__ #include +#include #include #include #include @@ -882,7 +883,7 @@ static int rpmh_regulator_probe(struct udevice *dev) priv->hw_data = init_data->hw_data; priv->enabled = -EINVAL; priv->uv = -ENOTRECOVERABLE; - if (ofnode_read_u32(dev_ofnode(dev), "regulator-initial-mode", &priv->mode)) + if (dev_read_u32(dev, "regulator-initial-mode", &priv->mode)) priv->mode = -EINVAL; plat_data->mode = priv->hw_data->pmic_mode_map; @@ -933,7 +934,7 @@ static int rpmh_regulators_bind(struct udevice *dev) return -ENODEV; } - pmic_id = ofnode_read_string(dev_ofnode(dev), "qcom,pmic-id"); + pmic_id = dev_read_string(dev, "qcom,pmic-id"); if (!pmic_id) { dev_err(dev, "No PMIC ID\n"); return -ENODEV; @@ -941,7 +942,7 @@ static int rpmh_regulators_bind(struct udevice *dev) drv = lists_driver_lookup_name("rpmh_regulator_drm"); - ofnode_for_each_subnode(node, dev_ofnode(dev)) { + dev_for_each_subnode(node, dev) { data = vreg_get_init_data(init_data, node); if (!data) continue; -- cgit v1.3.1 From 39dd6607cd8a3b02ff64b4bb2bebc605195fd961 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 4 Jun 2026 20:20:34 +0800 Subject: power: regulator: scmi: convert ofnode API to dev_read API Replace ofnode_find_subnode(dev_ofnode(dev), ...) with dev_read_subnode(dev, ...). No functional change. Signed-off-by: Peng Fan --- drivers/power/regulator/scmi_regulator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/regulator/scmi_regulator.c b/drivers/power/regulator/scmi_regulator.c index 7d2db1e2bee..aa7b4278260 100644 --- a/drivers/power/regulator/scmi_regulator.c +++ b/drivers/power/regulator/scmi_regulator.c @@ -180,7 +180,7 @@ static int scmi_regulator_bind(struct udevice *dev) ofnode node; int ret; - regul_node = ofnode_find_subnode(dev_ofnode(dev), "regulators"); + regul_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regul_node)) { dev_err(dev, "no regulators node\n"); return -ENXIO; -- cgit v1.3.1 From 903e861b719d27e49a2e35b1ae2930f85045cd4e Mon Sep 17 00:00:00 2001 From: Vincent Jardin Date: Wed, 27 May 2026 16:05:19 +0200 Subject: thermal: jc42: add JEDEC JC-42.4/TSE2004av SPD It is designed as a generic UCLASS_THERMAL driver for any JEDEC JC-42.4 family of on-DIMM temperature sensors (TSE2004av and compatible parts). The driver reads the temperature register over DM I2C. The "jedec,jc-42.4-temp" compatible is Linux-aligned (see Documentation/devicetree/bindings/hwmon/jedec,jc-42.4-temp.yaml in the Linux tree). When CMD_TEMPERATURE is enabled, the sensor becomes available with the standard commands "temperature list" / "temperature get". Signed-off-by: Vincent Jardin Signed-off-by: Peng Fan --- MAINTAINERS | 5 +++ drivers/thermal/Kconfig | 7 ++++ drivers/thermal/Makefile | 1 + drivers/thermal/jc42.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 106 insertions(+) create mode 100644 drivers/thermal/jc42.c (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index ec7217f39f4..56461129e89 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1297,6 +1297,11 @@ T: git https://source.denx.de/u-boot/u-boot.git F: cmd/i3c.c F: drivers/i3c/ +JEDEC JC-42.4 / TSE2004av TEMPERATURE SENSOR +M: Vincent Jardin +S: Maintained +F: drivers/thermal/jc42.c + KWBIMAGE / KWBOOT TOOLS M: Pali Rohár M: Marek Behún diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 91c39aa4dee..04cf3bfa420 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -55,4 +55,11 @@ config TI_LM74_THERMAL Enable thermal support for the Texas Instruments LM74 chip. The driver supports reading CPU temperature. +config DM_THERMAL_JC42 + bool "JEDEC JC-42.4/TSE2004av SPD temperature sensor" + depends on DM_I2C + help + Enable support for the JEDEC JC-42.4 temperature sensor found + on the SPD bus of DDR3 and DDR4 DIMMs (TSE2004av and compatible). + endif # if DM_THERMAL diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index b6f06c00ed9..c9fa7561b45 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_RCAR_GEN3_THERMAL) += rcar_gen3_thermal.o obj-$(CONFIG_SANDBOX) += thermal_sandbox.o obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o obj-$(CONFIG_TI_LM74_THERMAL) += ti-lm74.o +obj-$(CONFIG_DM_THERMAL_JC42) += jc42.o diff --git a/drivers/thermal/jc42.c b/drivers/thermal/jc42.c new file mode 100644 index 00000000000..6945260e8b0 --- /dev/null +++ b/drivers/thermal/jc42.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 Free Mobile - Vincent Jardin + * + * JEDEC JC-42.4 / TSE2004av Temperature Sensor driver. + * + * Generic I2C temperature sensor of the Serial Presence Detect (SPD) + * bus of DDR3 and DDR4 SO-DIMMs / UDIMMs / RDIMMs per the JEDEC + * JC-42.4 standard. The TSE2004av variant adds an integrated SPD + * EEPROM, but the thermal register interface is the same and is + * what this driver exposes. + * + * Register layout (subset): + * 0x05 Ambient temperature, 16-bit big-endian: + * bit 15 : T_CRIT alarm flag (read-only) + * bit 14 : T_HIGH alarm flag (read-only) + * bit 13 : T_LOW alarm flag (read-only) + * bit 12 : sign (two's-complement within bits[12:0]) + * bits[11:0]: magnitude * 16 (LSB = 0.0625 degC = 62.5 mC) + * 0x06 Manufacturer ID (16-bit BE, JEP-106 vendor code) + * 0x07 Device ID + Revision (upper byte = ID, lower = revision) + * ... + */ + +#include +#include +#include +#include + +#define JC42_REG_TEMP 0x05 + +#define JC42_TEMP_SIGN BIT(12) +#define JC42_TEMP_MAGNITUDE GENMASK(11, 0) + +static int jc42_get_temp(struct udevice *dev, int *temp) +{ + u8 buf[2]; + int ret; + int mag; + + ret = dm_i2c_read(dev, JC42_REG_TEMP, buf, sizeof(buf)); + if (ret) + return ret; + + mag = ((buf[0] << 8) | buf[1]) & (JC42_TEMP_SIGN | JC42_TEMP_MAGNITUDE); + if (mag & JC42_TEMP_SIGN) + mag -= (JC42_TEMP_SIGN << 1); + + /* + * mag is in units of 1/16 degC. Multiply first to keep one + * extra bit of precision before the divide. Worst-case range + * for a 13-bit signed value is +/-4096, so the product fits + * comfortably in an int (~4.1M mC). + */ + *temp = mag * 1000 / 16; + + return 0; +} + +static const struct dm_thermal_ops jc42_ops = { + .get_temp = jc42_get_temp, +}; + +/* + * Optional DT label property override: it replace the default DM + * device name (the ofnode name, eg "temp@18") so + * temperature list or temperature get commands + * show a human-meaningful identifier such as "ddr-top" or + * "ddr-bottom". + * It mirrors the Linux hwmon binding which uses label for the + * per-sensor display name. + */ +static int jc42_bind(struct udevice *dev) +{ + const char *label = dev_read_string(dev, "label"); + + if (label && *label) + return device_set_name(dev, label); + return 0; +} + +static const struct udevice_id jc42_match[] = { + { .compatible = "jedec,jc-42.4-temp" }, + { } +}; + +U_BOOT_DRIVER(jc42_thermal) = { + .name = "jc42_thermal", + .id = UCLASS_THERMAL, + .of_match = jc42_match, + .bind = jc42_bind, + .ops = &jc42_ops, +}; -- cgit v1.3.1 From 846f5fd2d17f695477659d5d0866bc1aa8fd3cce Mon Sep 17 00:00:00 2001 From: Vincent Jardin Date: Thu, 28 May 2026 14:57:07 +0200 Subject: thermal: imx_tmu: extend with QorIQ/Layerscape TMU Add support for the on-die Thermal Monitoring Unit (TMU) of the new QorIQ/Layerscape SoCs (LX2160A, LS1028A, LS1088A, ...): examples on a lx2160: => temperature list | Device | Driver | Parent | tmu@1f80000 | imx_tmu | root_driver | cluster67-thermal | imx_tmu | tmu@1f80000 | ddr1-cluster5-thermal | imx_tmu | tmu@1f80000 | wriop-thermal | imx_tmu | tmu@1f80000 | dce-qbman-hsio2-thermal | imx_tmu | tmu@1f80000 | ccn-dpaa-tbu-thermal | imx_tmu | tmu@1f80000 | cluster4-hsio3-thermal | imx_tmu | tmu@1f80000 | cluster23-thermal | imx_tmu | tmu@1f80000 => temperature get tmu@1f80000 tmu@1f80000: 82000 mC => temperature get wriop-thermal wriop-thermal: 81000 mC The parent tmu@... node owns the MMIO and calibration; one UCLASS_THERMAL device is bound per/thermal-zones site so each shows up by its zone name: => dm tree ... thermal 2 [ + ] imx_tmu |-- tmu@1f80000 thermal 3 [ + ] imx_tmu | |-- cluster67-thermal thermal 4 [ + ] imx_tmu | |-- ddr1-cluster5-thermal thermal 5 [ + ] imx_tmu | |-- wriop-thermal thermal 6 [ + ] imx_tmu | |-- dce-qbman-hsio2-thermal thermal 7 [ + ] imx_tmu | |-- ccn-dpaa-tbu-thermal thermal 8 [ + ] imx_tmu | |-- cluster4-hsio3-thermal thermal 9 [ + ] imx_tmu | `-- cluster23-thermal ... The dtsi additions mirror the existing fsl-ls1028a.dtsi: the LX2160A SoC dtsi gains the tmu@1f80000 node plus a thermal-zones hierarchy with 7 sites: cluster67-thermal site 0 A72 clusters 6 + 7 ddr1-cluster5-thermal site 1 DDR1 + A72 cluster 5 wriop-thermal site 2 WRIOP dce-qbman-hsio2-thermal site 3 DCE + QBMAN + HSIO2 ccn-dpaa-tbu-thermal site 4 CCN508 + DPAA + TBU cluster4-hsio3-thermal site 5 A72 cluster 4 + HSIO3 cluster23-thermal site 6 A72 clusters 2 + 3 Signed-off-by: Vincent Jardin Suggested-by: Tom Rini Inspired-by: Peng Fan Signed-off-by: Peng Fan --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 21 ++++ arch/arm/dts/fsl-lx2160a.dtsi | 58 ++++++++++ .../include/asm/arch-fsl-layerscape/sys_proto.h | 30 +++++ drivers/thermal/Kconfig | 9 +- drivers/thermal/imx_tmu.c | 125 ++++++++++++++++++++- 5 files changed, 238 insertions(+), 5 deletions(-) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h (limited to 'drivers') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index a047494b1fd..cbeac6d4383 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -986,6 +986,27 @@ uint get_svr(void) } #endif +/* + * Layerscape mirror of the i.MX get_cpu_temp_grade(). i.MX reads the + * OCOTP "CPU temp grade" fuses; Layerscape has no such fuse, so the + * limits come from the data sheet instead. LX2160A Reference Manual + * Rev. 1 (10/2021) section 1.12.1 specifies the maximum operating + * junction temperature at 105 degC for commercial / embedded parts; + * the lower bound is the standard -40 degC commercial low. + * + * The TMU itself is documented as accurate within +/- 3 degC (RM + * section 28.1), which the thermal driver clears by setting its + * alert threshold 10 degC below critical. + */ +u32 get_cpu_temp_grade(int *minc, int *maxc) +{ + if (minc) + *minc = -40; + if (maxc) + *maxc = 105; + return 0; /* commercial */ +} + #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 551efda8fe4..61d78b74f19 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -594,6 +594,64 @@ }; }; + /* LX2160ARM Chapter 28 ("Thermal Monitoring Unit") */ + tmu: tmu@1f80000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f80000 0x0 0x10000>; + interrupts = ; + fsl,tmu-range = <0x800000e6 0x8001017d>; + fsl,tmu-calibration = <0x00000000 0x00000035 + 0x00000001 0x00000154>; + little-endian; + #thermal-sensor-cells = <1>; + label = "lx2160a-tmu"; /* explicit naming */ + }; + + /* explicit thermal-zones names per LX2160ARM Table 323 */ + thermal-zones { + cluster67-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>; + }; + + ddr1-cluster5-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + }; + + wriop-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 2>; + }; + + dce-qbman-hsio2-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 3>; + }; + + ccn-dpaa-tbu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 4>; + }; + + cluster4-hsio3-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 5>; + }; + + cluster23-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 6>; + }; + }; + /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ emdio1: mdio@8b96000 { compatible = "fsl,ls-mdio"; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h new file mode 100644 index 00000000000..3b78e73c726 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2026 Free Mobile - Vincent Jardin + * + * Layerscape mirror of the i.MX : declares + * the SoC-personality helpers consumed by generic drivers that work on + * both i.MX and QorIQ/Layerscape parts (e.g. drivers/thermal/imx_tmu.c + * for the QorIQ TMU variant). + */ + +#ifndef _ASM_ARCH_FSL_LAYERSCAPE_SYS_PROTO_H +#define _ASM_ARCH_FSL_LAYERSCAPE_SYS_PROTO_H + +#include + +/* + * Per LX2160A Reference Manual, Rev. 1 (10/2021): + * - section 1.12.1: "NXP specs max power at 105 degC junction" for + * commercial / embedded operating conditions. + * - section 28.1: TMU "Accuracy within +/- 3 degC". + * + * Layerscape SoCs do not expose an OCOTP-style "CPU temp grade" fuse, + * so the implementation returns the documented junction-temperature + * limit from the data sheet (-40 .. 105 degC commercial range). The + * thermal driver subtracts 10 degC for its alert threshold, which + * comfortably clears the +/- 3 degC TMU accuracy in both directions. + */ +u32 get_cpu_temp_grade(int *minc, int *maxc); + +#endif /* _ASM_ARCH_FSL_LAYERSCAPE_SYS_PROTO_H */ diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 04cf3bfa420..33a82ca3bf1 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -27,11 +27,12 @@ config IMX_SCU_THERMAL trip is crossed config IMX_TMU - bool "Thermal Management Unit driver for NXP i.MX8M and iMX93" - depends on ARCH_IMX8M || IMX93 + bool "Thermal Management Unit driver for NXP i.MX8M / i.MX93 and QorIQ" + depends on ARCH_IMX8M || IMX93 || FSL_LAYERSCAPE help - Support for Temperature sensors on NXP i.MX8M and iMX93. - It supports one critical trip point and one passive trip point. + Support for the NXP Thermal Management Unit (TMU) sensors on + i.MX8M, i.MX93 and on QorIQ/Layerscape SoCs (LX2160A, + LS1028A, LS1088A, ...). The boot is hold to the cool device to throttle CPUs when the passive trip is crossed diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index 1bde4d07f52..da0825ecd34 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -6,14 +6,17 @@ #include #include -#include #include +#if IS_ENABLED(CONFIG_ARCH_IMX8M) || IS_ENABLED(CONFIG_IMX93) +#include +#endif #include #include #include #include #include #include +#include #include #include #include @@ -22,10 +25,12 @@ #define FLAGS_VER2 0x1 #define FLAGS_VER3 0x2 #define FLAGS_VER4 0x4 +#define FLAGS_QORIQ 0x8 #define TMR_DISABLE 0x0 #define TMR_ME 0x80000000 #define TMR_ALPF 0x0c000000 +#define QORIQ_TMR_ALPF (0x3 << 24) /* QorIQ ALPF lives at bits[25:24] */ #define TMTMIR_DEFAULT 0x00000002 #define TIER_DISABLE 0x0 @@ -33,7 +38,19 @@ #define TER_ADC_PD 0x40000000 #define TER_ALPF 0x3 +/* default CPU delay time to cool down if over temperature */ #define IMX_TMU_POLLING_DELAY_MS 5000 + +/* TRITSR - QorIQ Immediate Temperature Site Register. + * + * Per LX2160A Reference Manual, Rev. 1 (10/2021) section 28.3.1.24 + * the calibrated reading lives in TEMP[8:0] and is reported in + * degrees Kelvin (integer). The QorIQ regs_v1 variant has no + * fractional 0.5 degC bit, unlike the i.MX regs_v2 / VER4 layouts. + */ +#define TRITSR_V BIT(31) /* reading valid */ +#define TRITSR_TEMP_MASK GENMASK(8, 0) /* degrees Kelvin */ +#define TRITSR_KELVIN_OFFSET 273 /* TEMP[8:0] - 273 = degC */ /* * i.MX TMU Registers */ @@ -148,11 +165,37 @@ struct imx_tmu_regs_v3 { u32 trim; }; +/* + * fsl,qoriq-tmu (LX2160A, LS1028A, LS1088A, ...). Same TMU IP family as + * the i.MX "regs_v1" layout but: site-enable is a discrete TMSR at 0x08 + * (TMTMIR moves to 0x0C), and the temperature range registers are + * variable-length at 0xF10 (a SoC may use fewer than 16). Calibration is + * taken from the DT (fsl,tmu-range / fsl,tmu-calibration) exactly like + * the i.MX regs_v1 path, so qoriq reuses imx_tmu_calibration()'s scheme. + */ +struct qoriq_tmu_regs { + u32 tmr; /* 0x000 mode */ + u32 tsr; /* 0x004 status */ + u32 tmsr; /* 0x008 monitor-site enable (bit N = site N) */ + u32 tmtmir; /* 0x00C measurement interval */ + u8 res0[0x10]; + u32 tier; /* 0x020 interrupt enable */ + u32 tidr; /* 0x024 interrupt detect */ + u8 res1[0x58]; + u32 ttcfgr; /* 0x080 temperature config (cal walk) */ + u32 tscfgr; /* 0x084 sensor config (cal walk) */ + u8 res2[0x78]; + struct imx_tmu_site_regs site[SITES_MAX]; /* 0x100 */ + u8 res3[0xd10]; + u32 ttrcr[16]; /* 0xF10 temperature range control */ +}; + union tmu_regs { struct imx_tmu_regs regs_v1; struct imx_tmu_regs_v2 regs_v2; struct imx_tmu_regs_v3 regs_v3; struct imx_tmu_regs_v4 regs_v4; + struct qoriq_tmu_regs regs_qoriq; }; struct imx_tmu_plat { @@ -189,6 +232,9 @@ static int read_temperature(struct udevice *dev, int *temp) } else if (drv_data & FLAGS_VER4) { val = readl(&pdata->regs->regs_v4.tritsr0); valid = val & 0x80000000; + } else if (drv_data & FLAGS_QORIQ) { + val = readl(&pdata->regs->regs_qoriq.site[pdata->id].tritsr); + valid = val & TRITSR_V; } else { val = readl(&pdata->regs->regs_v1.site[pdata->id].tritsr); valid = val & 0x80000000; @@ -213,6 +259,19 @@ static int read_temperature(struct udevice *dev, int *temp) /* Convert Kelvin to Celsius */ *temp -= 273000; + } else if (drv_data & FLAGS_QORIQ) { + /* + * LX2160A Reference Manual, Rev. 1 (10/2021) + * section 28.3.1.24: TEMP[8:0] is the calibrated + * reading in degrees Kelvin (integer, no 0.5 degC + * bit on the regs_v1 variant). The calibration + * point examples in the same RM section 28.1.3 + * use the same Kelvin/Celsius offset: + * TTR0CR=0x800000E6 -> 230K (-43 degC) + * TTR1CR=0x8001017D -> 381K (108 degC) + */ + *temp = ((val & TRITSR_TEMP_MASK) - + TRITSR_KELVIN_OFFSET) * 1000; } else { *temp = (val & 0xff) * 1000; } @@ -265,6 +324,35 @@ static int imx_tmu_calibration(struct udevice *dev) if (drv_data & (FLAGS_VER2 | FLAGS_VER3)) return 0; + if (drv_data & FLAGS_QORIQ) { + const fdt32_t *ranges; + int n; + + ranges = dev_read_prop(dev, "fsl,tmu-range", &len); + if (!ranges || len % 4 || + len / 4 > (int)ARRAY_SIZE(pdata->regs->regs_qoriq.ttrcr)) { + dev_err(dev, "TMU: missing/invalid fsl,tmu-range\n"); + return -ENODEV; + } + n = len / 4; + for (i = 0; i < n; i++) + writel(fdt32_to_cpu(ranges[i]), + &pdata->regs->regs_qoriq.ttrcr[i]); + + calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len); + if (!calibration || len % 8) { + dev_err(dev, "TMU: invalid calibration data.\n"); + return -ENODEV; + } + for (i = 0; i < len; i += 8, calibration += 2) { + writel(fdt32_to_cpu(*calibration), + &pdata->regs->regs_qoriq.ttcfgr); + writel(fdt32_to_cpu(*(calibration + 1)), + &pdata->regs->regs_qoriq.tscfgr); + } + return 0; + } + if (drv_data & FLAGS_VER4) { calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len); if (!calibration || len % 8 || len > 128) { @@ -402,6 +490,18 @@ static inline void imx_tmu_mx8mq_init(struct udevice *dev) { } static void imx_tmu_arch_init(struct udevice *dev) { + /* + * QorIQ takes its calibration from the DT (fsl,tmu-calibration), + * not from OCOTP fuses, so it has no per-SoC arch init. The #if + * below is still required: the i.MX SoC-ID helpers and fuse API + * () do not exist in a Layerscape build, so + * the references must be removed at compile time, not merely + * skipped at runtime. + */ + if (dev_get_driver_data(dev) & FLAGS_QORIQ) + return; + +#if IS_ENABLED(CONFIG_ARCH_IMX8M) || IS_ENABLED(CONFIG_IMX93) if (is_imx8mm() || is_imx8mn()) imx_tmu_mx8mm_mx8mn_init(dev); else if (is_imx8mp()) @@ -412,6 +512,7 @@ static void imx_tmu_arch_init(struct udevice *dev) imx_tmu_mx8mq_init(dev); else dev_err(dev, "Unsupported SoC, TMU calibration not loaded!\n"); +#endif } static void imx_tmu_init(struct udevice *dev) @@ -443,6 +544,15 @@ static void imx_tmu_init(struct udevice *dev) /* Set update_interval */ writel(TMTMIR_DEFAULT, &pdata->regs->regs_v4.tmtmir); + } else if (drv_data & FLAGS_QORIQ) { + /* Disable monitoring */ + writel(TMR_DISABLE, &pdata->regs->regs_qoriq.tmr); + + /* Disable interrupt, using polling instead */ + writel(TIER_DISABLE, &pdata->regs->regs_qoriq.tier); + + /* Set update_interval */ + writel(TMTMIR_DEFAULT, &pdata->regs->regs_qoriq.tmtmir); } else { /* Disable monitoring */ writel(TMR_DISABLE, &pdata->regs->regs_v1.tmr); @@ -511,6 +621,18 @@ static int imx_tmu_enable_msite(struct udevice *dev) /* Enable ME */ reg |= TMR_ME; writel(reg, &pdata->regs->regs_v4.tmr); + } else if (drv_data & FLAGS_QORIQ) { + /* Clear ME, enable every site at once via the discrete TMSR */ + reg = readl(&pdata->regs->regs_qoriq.tmr); + reg &= ~TMR_ME; + writel(reg, &pdata->regs->regs_qoriq.tmr); + + writel(GENMASK(SITES_MAX - 1, 0), + &pdata->regs->regs_qoriq.tmsr); + + reg |= QORIQ_TMR_ALPF; + reg |= TMR_ME; + writel(reg, &pdata->regs->regs_qoriq.tmr); } else { /* Clear the ME before setting MSITE and ALPF*/ reg = readl(&pdata->regs->regs_v1.tmr); @@ -650,6 +772,7 @@ static const struct udevice_id imx_tmu_ids[] = { { .compatible = "fsl,imx8mm-tmu", .data = FLAGS_VER2, }, { .compatible = "fsl,imx8mp-tmu", .data = FLAGS_VER3, }, { .compatible = "fsl,imx93-tmu", .data = FLAGS_VER4, }, + { .compatible = "fsl,qoriq-tmu", .data = FLAGS_QORIQ, }, { } }; -- cgit v1.3.1 From d62b91463b38165fd5a2bb6cb5b6f0c1c09fa91e Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 3 Jun 2026 13:51:57 +0800 Subject: imx9: scmi: Print CPU part number name Decode the CPU part number from PART_NUM fuse and print it in CPU name. For iMX95 and iMX952 Part number fuse is defined as: [7:6] : Package description [5:2] : Segment [1:0] : Number of A55 cores For iMX94, the PART_NUM[7:0] fuse directly reflects the part number value. Signed-off-by: Ye Li Acked-by: Peng Fan Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx9/scmi/soc.c | 88 +++++++++++++++++++++++++++++++++++---- drivers/cpu/imx8_cpu.c | 12 +++++- 2 files changed, 92 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 3f3722a7ce9..3e9f22ae4ae 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP * * Peng Fan */ @@ -716,14 +716,88 @@ int get_reset_reason(bool sys, bool lm) return 0; } -const char *get_imx_type(u32 imxtype) +const char *get_cpu_variant_type_name(u32 type) { - switch (imxtype) { - case SCMI_CPU: - return IMX_PLAT_STR; - default: - return "??"; + u32 val, core_num, part_num; + int ret; + + ret = fuse_read(2, 1, &val); + if (ret) + return NULL; + + /* Get part num */ + part_num = (val >> 4) & 0xff; + if (!part_num) + return NULL; + + if (type == MXC_CPU_IMX95 || type == MXC_CPU_IMX952) { + u32 segment; + static char name[8] = "95294"; + char pn[2]; + + core_num = part_num & 0x3; + segment = (part_num >> 2) & 0xf; + + switch (segment) { + case 0xa: + pn[0] = 'T'; + break; + case 0xb: + pn[0] = 'V'; + break; + case 0xc: + pn[0] = 'C'; + break; + case 0xd: + pn[0] = 'G'; + break; + case 0xe: + pn[0] = 'I'; + break; + case 0xf: + pn[0] = 'N'; + break; + default: + pn[0] = segment + '0'; + break; + } + + pn[1] = core_num * 2 + '0'; + + if (type == MXC_CPU_IMX95) + sprintf(name, "95%c%c", pn[0], pn[1]); + else + sprintf(name, "952%c%c", pn[0], pn[1]); + + return name; + } else if (type == MXC_CPU_IMX94) { + static char *name = "94398"; + + core_num = 8; + + ret = fuse_read(2, 2, &val); + if (ret) + return NULL; + + if (part_num > 30) { /* 943 */ + /* A55 2 & 3 disabled */ + if ((val & 0x18) == 0x18) + core_num = 6; + } else if (part_num > 20) { /* 942 */ + core_num = 5; + + /* m7_0 disabled */ + if ((val & 0x200) == 0x200) + core_num = 4; + } else if (part_num > 10) { /* 941 */ + core_num = 5; + } + sprintf(name, "94%u%u", part_num, core_num); + + return name; } + + return NULL; } void build_info(void) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 2bd76ffa739..7bb7b420176 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019, 2024 NXP + * Copyright 2019, 2024-2026 NXP */ #include @@ -28,8 +28,18 @@ struct cpu_imx_plat { u32 mpidr; }; +__weak const char *get_cpu_variant_type_name(u32 type) +{ + return NULL; +} + static const char *get_imx_type_str(u32 imxtype) { + const char *name = get_cpu_variant_type_name(imxtype); + + if (name) + return name; + switch (imxtype) { case MXC_CPU_IMX8MM: return "8MMQ"; /* Quad-core version of the imx8mm */ -- cgit v1.3.1 From 54ed5729a95bf53ceda7345e4e3839e2f4e85eab Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 11:10:18 +0800 Subject: clk: at91: Use dev_read_addr_ptr() Replace devfdt_get_addr_ptr() with dev_read_addr_ptr() when retrieving the register base address. dev_read_addr_ptr() supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan Tested-by: Manikandan Muralidharan --- drivers/clk/at91/sam9x60.c | 2 +- drivers/clk/at91/sam9x7.c | 2 +- drivers/clk/at91/sama7d65.c | 6 +++--- drivers/clk/at91/sama7g5.c | 6 +++--- drivers/clk/at91/sckc.c | 5 ++++- 5 files changed, 12 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index 2251e2846fa..0d0e39db57e 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -426,7 +426,7 @@ static const struct pmc_clk_setup sam9x60_clk_setup[] = { static int sam9x60_clk_probe(struct udevice *dev) { - void __iomem *base = (void *)devfdt_get_addr_ptr(dev); + void __iomem *base = dev_read_addr_ptr(dev); unsigned int *clkmuxallocs[64], *muxallocs[64]; const char *p[10]; unsigned int cm[10], m[10], *tmpclkmux, *tmpmux; diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index 9ea253e6ff8..93f899b6617 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -817,7 +817,7 @@ static const struct { static int sam9x7_clk_probe(struct udevice *dev) { - void __iomem *base = (void *)devfdt_get_addr_ptr(dev); + void __iomem *base = dev_read_addr_ptr(dev); unsigned int *clkmuxallocs[64], *muxallocs[64]; const char *p[10]; unsigned int cm[10], m[10], *tmpclkmux, *tmpmux; diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 9f0b394543b..0c17a8cf67b 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1176,7 +1176,7 @@ static const struct pmc_clk_setup sama7d65_clk_setup[] = { static int sama7d65_clk_probe(struct udevice *dev) { - void __iomem *base = (void *)devfdt_get_addr(dev); + void __iomem *base = dev_read_addr_ptr(dev); unsigned int *clkmuxallocs[SAMA7D65_MAX_MUX_ALLOCS]; unsigned int *muxallocs[SAMA7D65_MAX_MUX_ALLOCS]; const char *p[12]; @@ -1185,8 +1185,8 @@ static int sama7d65_clk_probe(struct udevice *dev) bool main_osc_bypass; int ret, muxallocindex = 0, clkmuxallocindex = 0, i, j; - if (IS_ERR(base)) - return PTR_ERR(base); + if (!base) + return -EINVAL; memset(muxallocs, 0, ARRAY_SIZE(muxallocs)); memset(clkmuxallocs, 0, ARRAY_SIZE(clkmuxallocs)); diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index f24d251857f..c436038aed2 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -1109,7 +1109,7 @@ static const struct pmc_clk_setup sama7g5_clk_setup[] = { static int sama7g5_clk_probe(struct udevice *dev) { - void __iomem *base = devfdt_get_addr_ptr(dev); + void __iomem *base = dev_read_addr_ptr(dev); unsigned int *clkmuxallocs[SAMA7G5_MAX_MUX_ALLOCS]; unsigned int *muxallocs[SAMA7G5_MAX_MUX_ALLOCS]; const char *p[10]; @@ -1118,8 +1118,8 @@ static int sama7g5_clk_probe(struct udevice *dev) bool main_osc_bypass; int ret, muxallocindex = 0, clkmuxallocindex = 0, i, j; - if (IS_ERR(base)) - return PTR_ERR(base); + if (!base) + return -EINVAL; memset(muxallocs, 0, sizeof(muxallocs)); memset(clkmuxallocs, 0, sizeof(clkmuxallocs)); diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index dcaffd360fd..410bc088248 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -124,12 +124,15 @@ U_BOOT_DRIVER(at91_sam9x60_td_slck) = { static int at91_sam9x60_sckc_probe(struct udevice *dev) { struct sam9x60_sckc *sckc = dev_get_priv(dev); - void __iomem *base = devfdt_get_addr_ptr(dev); + void __iomem *base = dev_read_addr_ptr(dev); const char *slow_rc_osc, *slow_osc; const char *parents[2]; struct clk *clk, c; int ret; + if (!base) + return -EINVAL; + ret = clk_get_by_index(dev, 0, &c); if (ret) return ret; -- cgit v1.3.1 From 179022b8e1985b7fb1e0b454d86b779d29720d83 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 11:10:19 +0800 Subject: clk: altera: Use dev_read_addr_ptr() Replace devfdt_get_addr_ptr() with dev_read_addr_ptr() when retrieving the register base address. dev_read_addr_ptr() supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/clk/altera/clk-mem-n5x.c | 9 +++++---- drivers/clk/altera/clk-n5x.c | 8 ++++---- 2 files changed, 9 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c index ac59571a853..149e3016dd3 100644 --- a/drivers/clk/altera/clk-mem-n5x.c +++ b/drivers/clk/altera/clk-mem-n5x.c @@ -103,12 +103,13 @@ static int socfpga_mem_clk_enable(struct clk *clk) static int socfpga_mem_clk_of_to_plat(struct udevice *dev) { struct socfpga_mem_clk_plat *plat = dev_get_plat(dev); - fdt_addr_t addr; + void __iomem *addr; - addr = devfdt_get_addr(dev); - if (addr == FDT_ADDR_T_NONE) + addr = dev_read_addr_ptr(dev); + if (!addr) return -EINVAL; - plat->regs = (void __iomem *)addr; + + plat->regs = addr; return 0; } diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c index 185c9028a78..0a3bae38589 100644 --- a/drivers/clk/altera/clk-n5x.c +++ b/drivers/clk/altera/clk-n5x.c @@ -454,12 +454,12 @@ static int socfpga_clk_probe(struct udevice *dev) static int socfpga_clk_of_to_plat(struct udevice *dev) { struct socfpga_clk_plat *plat = dev_get_plat(dev); - fdt_addr_t addr; + void __iomem *addr; - addr = devfdt_get_addr(dev); - if (addr == FDT_ADDR_T_NONE) + addr = dev_read_addr_ptr(dev); + if (!addr) return -EINVAL; - plat->regs = (void __iomem *)addr; + plat->regs = addr; return 0; } -- cgit v1.3.1 From 48d74f433e4ff77bdb5a5500b141db07e609ca15 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 11:10:20 +0800 Subject: clk: aspeed: Use dev_read_addr_ptr() Replace devfdt_get_addr_ptr() with dev_read_addr_ptr() when retrieving the register base address. dev_read_addr_ptr() supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/clk/aspeed/clk_ast2500.c | 6 +++--- drivers/clk/aspeed/clk_ast2600.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index b07d7cd419c..94c7f662319 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -544,9 +544,9 @@ static int ast2500_clk_of_to_plat(struct udevice *dev) { struct ast2500_clk_priv *priv = dev_get_priv(dev); - priv->scu = devfdt_get_addr_ptr(dev); - if (IS_ERR(priv->scu)) - return PTR_ERR(priv->scu); + priv->scu = dev_read_addr_ptr(dev); + if (!priv->scu) + return -EINVAL; return 0; } diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index 4530053bc6b..74209e947ed 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -1174,9 +1174,9 @@ static int ast2600_clk_probe(struct udevice *dev) { struct ast2600_clk_priv *priv = dev_get_priv(dev); - priv->scu = devfdt_get_addr_ptr(dev); - if (IS_ERR(priv->scu)) - return PTR_ERR(priv->scu); + priv->scu = dev_read_addr_ptr(dev); + if (!priv->scu) + return -EINVAL; ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); -- cgit v1.3.1 From f683a457b65d4fd002f659ed0fb925d23252a346 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 11:10:21 +0800 Subject: clk: hsdk-cgu: Use dev_read_addr_index_ptr() Replace devfdt_get_addr_index_ptr() with dev_read_addr_index_ptr() when retrieving the register base address. dev_read_addr_index_ptr() supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/clk/clk-hsdk-cgu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c index 53655059279..dbc926a4391 100644 --- a/drivers/clk/clk-hsdk-cgu.c +++ b/drivers/clk/clk-hsdk-cgu.c @@ -753,11 +753,11 @@ static int hsdk_cgu_clk_probe(struct udevice *dev) else hsdk_clk->map = hsdk_4xd_clk_map; - hsdk_clk->cgu_regs = devfdt_get_addr_index_ptr(dev, 0); + hsdk_clk->cgu_regs = dev_read_addr_index_ptr(dev, 0); if (!hsdk_clk->cgu_regs) return -EINVAL; - hsdk_clk->creg_regs = devfdt_get_addr_index_ptr(dev, 1); + hsdk_clk->creg_regs = dev_read_addr_index_ptr(dev, 1); if (!hsdk_clk->creg_regs) return -EINVAL; -- cgit v1.3.1 From 55550b429291b7c46a65a1864c49f25c2ed1a6a3 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 11:10:22 +0800 Subject: clk: sophgo: Use dev_read_addr_ptr() Replace devfdt_get_addr_ptr() with dev_read_addr_ptr() when retrieving the register base address. dev_read_addr_ptr() supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/clk/sophgo/clk-cv1800b.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/sophgo/clk-cv1800b.c b/drivers/clk/sophgo/clk-cv1800b.c index d946ea57a46..248a69321fc 100644 --- a/drivers/clk/sophgo/clk-cv1800b.c +++ b/drivers/clk/sophgo/clk-cv1800b.c @@ -500,9 +500,12 @@ static int cv1800b_register_clk(struct udevice *dev) { struct clk osc; ulong osc_rate; - void *base = devfdt_get_addr_ptr(dev); + void __iomem *base = dev_read_addr_ptr(dev); int i, ret; + if (!base) + return -EINVAL; + ret = clk_get_by_index(dev, 0, &osc); if (ret) { pr_err("Failed to get clock\n"); -- cgit v1.3.1 From ef6b3ccf598820f53b79de452175b912a85ed850 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 12:00:32 +0800 Subject: pinctrl: at91: Use dev_read_addr_index() Use dev_read_addr_index() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/pinctrl/pinctrl-at91.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 2938635ed95..50a130d700f 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -527,7 +527,7 @@ static int at91_pinctrl_probe(struct udevice *dev) if (list_empty(&dev->child_head)) { for (index = 0; index < MAX_GPIO_BANKS; index++) { - addr_base = devfdt_get_addr_index(dev, index); + addr_base = dev_read_addr_index(dev, index); if (addr_base == FDT_ADDR_T_NONE) break; -- cgit v1.3.1 From b6d42b3fbf4fc3cac2e84ab0cefe1f31165b5ec1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 12:00:33 +0800 Subject: pinctrl: nexell: Use dev_read_addr() Use dev_read_addr() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/pinctrl/nexell/pinctrl-nexell.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pinctrl/nexell/pinctrl-nexell.c b/drivers/pinctrl/nexell/pinctrl-nexell.c index af1acd91649..bd89e779864 100644 --- a/drivers/pinctrl/nexell/pinctrl-nexell.c +++ b/drivers/pinctrl/nexell/pinctrl-nexell.c @@ -49,7 +49,7 @@ int nexell_pinctrl_probe(struct udevice *dev) if (!priv) return -EINVAL; - base = devfdt_get_addr(dev); + base = dev_read_addr(dev); if (base == FDT_ADDR_T_NONE) return -EINVAL; -- cgit v1.3.1 From bc988983d25b19cedd76cba1903e321c52198801 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 12:06:01 +0800 Subject: gpio: nx: Use dev_remap_addr() Use dev_remap_addr() to simplify code. dev_remap_addr() does same thing as dev_read_addr() + map_physmem(). And it supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. Also add error handling logic. No functional changes. Signed-off-by: Peng Fan --- drivers/gpio/nx_gpio.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/nx_gpio.c b/drivers/gpio/nx_gpio.c index 5abbb34daea..1c3d27eb1cc 100644 --- a/drivers/gpio/nx_gpio.c +++ b/drivers/gpio/nx_gpio.c @@ -213,9 +213,10 @@ static int nx_gpio_of_to_plat(struct udevice *dev) { struct nx_gpio_plat *plat = dev_get_plat(dev); - plat->regs = map_physmem(devfdt_get_addr(dev), - sizeof(struct nx_gpio_regs), - MAP_NOCACHE); + plat->regs = dev_remap_addr(dev); + if (!plat->regs) + return -EINVAL; + plat->gpio_count = dev_read_s32_default(dev, "nexell,gpio-bank-width", 32); plat->bank_name = dev_read_string(dev, "gpio-bank-name"); -- cgit v1.3.1 From a4e8d80c9d189a245980dd62c26e0e9103599062 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 12:06:02 +0800 Subject: gpio: aspeed: Use dev_read_addr_ptr() Use dev_read_addr_ptr() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/gpio/gpio-aspeed-g7.c | 2 +- drivers/gpio/gpio-aspeed-sgpio.c | 6 +++--- drivers/gpio/gpio-aspeed.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/gpio-aspeed-g7.c b/drivers/gpio/gpio-aspeed-g7.c index 4607468ca05..ae330173f38 100644 --- a/drivers/gpio/gpio-aspeed-g7.c +++ b/drivers/gpio/gpio-aspeed-g7.c @@ -131,7 +131,7 @@ static int aspeed_gpio_probe(struct udevice *dev) uc_priv->bank_name = dev->name; ofnode_read_u32(dev_ofnode(dev), "ngpios", &uc_priv->gpio_count); - priv->regs = devfdt_get_addr_ptr(dev); + priv->regs = dev_read_addr_ptr(dev); return 0; } diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c index 4bbdec756f3..d6144d5706b 100644 --- a/drivers/gpio/gpio-aspeed-sgpio.c +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -223,9 +223,9 @@ static int aspeed_sgpio_probe(struct udevice *dev) ulong apb_freq; int ret; - priv->base = devfdt_get_addr_ptr(dev); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; priv->pdata = (const struct aspeed_sgpio_pdata *)dev_get_driver_data(dev); if (!priv->pdata) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index c5608f4a9df..54a786c4dc0 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -275,7 +275,7 @@ static int aspeed_gpio_probe(struct udevice *dev) uc_priv->bank_name = dev->name; ofnode_read_u32(dev_ofnode(dev), "ngpios", &uc_priv->gpio_count); - priv->regs = devfdt_get_addr_ptr(dev); + priv->regs = dev_read_addr_ptr(dev); return 0; } -- cgit v1.3.1 From 8918af1c0ce56d5dced75b97b737849ae525dacf Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 12:24:03 +0800 Subject: remoteproc: pru: Use dev_read_addr_size_index() Use dev_read_addr_size_index() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. While at here, drop unused 'node'. No functional changes. Signed-off-by: Peng Fan --- drivers/remoteproc/pru_rproc.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 9aec138637b..b0823bfd22d 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -421,19 +421,16 @@ static void pru_set_id(struct pru_privdata *priv, struct udevice *dev) static int pru_probe(struct udevice *dev) { struct pru_privdata *priv; - ofnode node; - - node = dev_ofnode(dev); priv = dev_get_priv(dev); priv->prusspriv = dev_get_priv(dev->parent); - priv->pru_iram = devfdt_get_addr_size_index(dev, PRU_MEM_IRAM, - &priv->pru_iramsz); - priv->pru_ctrl = devfdt_get_addr_size_index(dev, PRU_MEM_CTRL, - &priv->pru_ctrlsz); - priv->pru_debug = devfdt_get_addr_size_index(dev, PRU_MEM_DEBUG, - &priv->pru_debugsz); + priv->pru_iram = dev_read_addr_size_index(dev, PRU_MEM_IRAM, + &priv->pru_iramsz); + priv->pru_ctrl = dev_read_addr_size_index(dev, PRU_MEM_CTRL, + &priv->pru_ctrlsz); + priv->pru_debug = dev_read_addr_size_index(dev, PRU_MEM_DEBUG, + &priv->pru_debugsz); priv->iram_da = 0; priv->pdram_da = 0; -- cgit v1.3.1 From 8e8e624abc1f842c9afd8be5fafbba82adf426a7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 12:24:04 +0800 Subject: remoteproc: ipu: Use dev_read_addr_x() Use dev_read_addr_x() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/remoteproc/ipu_rproc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/remoteproc/ipu_rproc.c b/drivers/remoteproc/ipu_rproc.c index 2ca78b550a7..8f0b619daf7 100644 --- a/drivers/remoteproc/ipu_rproc.c +++ b/drivers/remoteproc/ipu_rproc.c @@ -695,9 +695,8 @@ static int ipu_probe(struct udevice *dev) priv = dev_get_priv(dev); priv->mem.bus_addr = - devfdt_get_addr_size_name(dev, - ipu_mem_names[0], - (fdt_addr_t *)&priv->mem.size); + dev_read_addr_size_name(dev, ipu_mem_names[0], + (fdt_addr_t *)&priv->mem.size); ret = reset_get_by_index(dev, 2, &reset); if (ret < 0) { @@ -718,7 +717,7 @@ static int ipu_probe(struct udevice *dev) priv->mem.cpu_addr = map_physmem(priv->mem.bus_addr, priv->mem.size, MAP_NOCACHE); - if (devfdt_get_addr(dev) == 0x58820000) + if (dev_read_addr(dev) == 0x58820000) priv->id = 0; else priv->id = 1; -- cgit v1.3.1 From c305b8ac862b225d659471d1c2a462717999eb5d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 12:37:13 +0800 Subject: crypto: aspeed: Use dev_read_addr_x() Use dev_read_addr_x() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/crypto/aspeed/aspeed_acry.c | 4 ++-- drivers/crypto/aspeed/aspeed_hace.c | 2 +- drivers/crypto/aspeed/cptra_ecdsa.c | 2 +- drivers/crypto/aspeed/cptra_sha.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/crypto/aspeed/aspeed_acry.c b/drivers/crypto/aspeed/aspeed_acry.c index e3f81ebd5c7..ff01256e150 100644 --- a/drivers/crypto/aspeed/aspeed_acry.c +++ b/drivers/crypto/aspeed/aspeed_acry.c @@ -144,13 +144,13 @@ static int aspeed_acry_probe(struct udevice *dev) return ret; } - acry->base = devfdt_get_addr_index(dev, 0); + acry->base = dev_read_addr_index(dev, 0); if (acry->base == FDT_ADDR_T_NONE) { debug("Failed to get acry base\n"); return acry->base; } - acry->sram_base = devfdt_get_addr_index(dev, 1); + acry->sram_base = dev_read_addr_index(dev, 1); if (acry->sram_base == FDT_ADDR_T_NONE) { debug("Failed to get acry SRAM base\n"); return acry->sram_base; diff --git a/drivers/crypto/aspeed/aspeed_hace.c b/drivers/crypto/aspeed/aspeed_hace.c index 17cc30a7b54..22b5008a296 100644 --- a/drivers/crypto/aspeed/aspeed_hace.c +++ b/drivers/crypto/aspeed/aspeed_hace.c @@ -341,7 +341,7 @@ static int aspeed_hace_probe(struct udevice *dev) return rc; } - hace->base = devfdt_get_addr(dev); + hace->base = dev_read_addr(dev); return rc; } diff --git a/drivers/crypto/aspeed/cptra_ecdsa.c b/drivers/crypto/aspeed/cptra_ecdsa.c index 4b70d89def7..7603ca373ff 100644 --- a/drivers/crypto/aspeed/cptra_ecdsa.c +++ b/drivers/crypto/aspeed/cptra_ecdsa.c @@ -149,7 +149,7 @@ static int cptra_ecdsa_probe(struct udevice *dev) { struct cptra_ecdsa *ce = dev_get_priv(dev); - ce->regs = (void *)devfdt_get_addr(dev); + ce->regs = (void *)dev_read_addr(dev); if (ce->regs == (void *)FDT_ADDR_T_NONE) { debug("cannot map Caliptra mailbox registers\n"); return -EINVAL; diff --git a/drivers/crypto/aspeed/cptra_sha.c b/drivers/crypto/aspeed/cptra_sha.c index 26b97bdd92b..f57778e160d 100644 --- a/drivers/crypto/aspeed/cptra_sha.c +++ b/drivers/crypto/aspeed/cptra_sha.c @@ -219,7 +219,7 @@ static int cptra_sha_probe(struct udevice *dev) { struct cptra_sha *cs = dev_get_priv(dev); - cs->regs = (void *)devfdt_get_addr(dev); + cs->regs = (void *)dev_read_addr(dev); if (cs->regs == (void *)FDT_ADDR_T_NONE) { debug("cannot map Caliptra SHA ACC registers\n"); return -ENODEV; -- cgit v1.3.1 From f2479b58aa7287065351af2a53909586475a2289 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 12:37:14 +0800 Subject: crypto: tegra: Use dev_read_addr_x() Use dev_read_addr_size_name_ptr() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan Reviewed-by: Svyatoslav Ryhel --- drivers/crypto/tegra/tegra_aes.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/crypto/tegra/tegra_aes.c b/drivers/crypto/tegra/tegra_aes.c index 7b374c757ba..55a4cec525b 100644 --- a/drivers/crypto/tegra/tegra_aes.c +++ b/drivers/crypto/tegra/tegra_aes.c @@ -518,7 +518,7 @@ static int tegra_aes_probe(struct udevice *dev) return -EINVAL; } - priv->iram_addr = devfdt_get_addr_size_name_ptr(dev, "iram-buffer", &iram_size); + priv->iram_addr = dev_read_addr_size_name_ptr(dev, "iram-buffer", &iram_size); if (!priv->iram_addr) { log_debug("%s: Cannot find iram buffer address, binding failed\n", __func__); return -EINVAL; -- cgit v1.3.1 From d26cbf4667c9b8193b06c6f8e9fa7334866c94ac Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 12:07:41 +0800 Subject: ram: aspeed: Use dev_read_addr_x() API Use dev_read_addr_ptr() and dev_read_addr_index_ptr() which support both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. While at here, also use ofnode_read_s32_default() to replace fdtdec_get_int(). No functional changes. Signed-off-by: Peng Fan --- drivers/ram/aspeed/sdram_ast2600.c | 15 +++++++-------- drivers/ram/aspeed/sdram_ast2700.c | 4 ++-- 2 files changed, 9 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index 55e80fba3dc..2cf9296468d 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -1076,10 +1076,10 @@ static int ast2600_sdrammc_probe(struct udevice *dev) return ret; } - priv->scu = devfdt_get_addr_ptr(clk_dev); - if (IS_ERR(priv->scu)) { + priv->scu = dev_read_addr_ptr(clk_dev); + if (!priv->scu) { debug("%s(): can't get SCU\n", __func__); - return PTR_ERR(priv->scu); + return -ENODEV; } if (readl(&priv->scu->dram_hdshk) & SCU_DRAM_HDSHK_RDY) { @@ -1136,12 +1136,11 @@ static int ast2600_sdrammc_of_to_plat(struct udevice *dev) { struct dram_info *priv = dev_get_priv(dev); - priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); - priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); - priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); + priv->regs = (void *)(uintptr_t)dev_read_addr_index(dev, 0); + priv->phy_setting = (void *)(uintptr_t)dev_read_addr_index(dev, 1); + priv->phy_status = (void *)(uintptr_t)dev_read_addr_index(dev, 2); - priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "clock-frequency", 0); + priv->clock_rate = ofnode_read_s32_default(dev_ofnode(dev), "clock-frequency", 0); if (!priv->clock_rate) { debug("DDR Clock Rate not defined\n"); return -EINVAL; diff --git a/drivers/ram/aspeed/sdram_ast2700.c b/drivers/ram/aspeed/sdram_ast2700.c index 4a019c4edb1..00974da52bb 100644 --- a/drivers/ram/aspeed/sdram_ast2700.c +++ b/drivers/ram/aspeed/sdram_ast2700.c @@ -956,13 +956,13 @@ static int ast2700_sdrammc_of_to_plat(struct udevice *dev) ofnode node; int rc; - sdrammc->regs = (struct sdrammc_regs *)devfdt_get_addr_index(dev, 0); + sdrammc->regs = (struct sdrammc_regs *)dev_read_addr_index(dev, 0); if (sdrammc->regs == (void *)FDT_ADDR_T_NONE) { debug("cannot map DRAM register\n"); return -ENODEV; } - sdrammc->phy = (void *)devfdt_get_addr_index(dev, 1); + sdrammc->phy = (void *)dev_read_addr_index(dev, 1); if (sdrammc->phy == (void *)FDT_ADDR_T_NONE) { debug("cannot map PHY memory\n"); return -ENODEV; -- cgit v1.3.1 From 305c014fdb7208ced179e47dc3634e7faa6a2502 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 14:48:01 +0800 Subject: reset: ast: Use dev_read_addr_ptr() Use dev_read_addr_ptr() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. While at here, correct error return value, when priv->scu is NULL, PTR_ERR(priv->scu) is 0 which implies success. Change to return '-EINVAL'. No functional changes. Signed-off-by: Peng Fan --- drivers/reset/reset-ast2500.c | 4 ++-- drivers/reset/reset-ast2600.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c index 39b3d025713..c85906bbeb5 100644 --- a/drivers/reset/reset-ast2500.c +++ b/drivers/reset/reset-ast2500.c @@ -77,10 +77,10 @@ static int ast2500_reset_probe(struct udevice *dev) return rc; } - priv->scu = devfdt_get_addr_ptr(scu_dev); + priv->scu = dev_read_addr_ptr(scu_dev); if (IS_ERR_OR_NULL(priv->scu)) { debug("%s: invalid SCU base pointer\n", __func__); - return PTR_ERR(priv->scu); + return -EINVAL; } return 0; diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c index 9b77f6c2b71..71b6220225a 100644 --- a/drivers/reset/reset-ast2600.c +++ b/drivers/reset/reset-ast2600.c @@ -76,10 +76,10 @@ static int ast2600_reset_probe(struct udevice *dev) return rc; } - priv->scu = devfdt_get_addr_ptr(scu_dev); + priv->scu = dev_read_addr_ptr(scu_dev); if (IS_ERR_OR_NULL(priv->scu)) { debug("%s: invalid SCU base pointer\n", __func__); - return PTR_ERR(priv->scu); + return -EINVAL; } return 0; -- cgit v1.3.1 From 8b5e2a25aba97e43180096de71a8ac5617ba25ec Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 14:49:09 +0800 Subject: thermal: ti-bandgap: Use dev_read_addr_index() Use dev_read_addr_index() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/thermal/ti-bandgap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/thermal/ti-bandgap.c b/drivers/thermal/ti-bandgap.c index dc869f108e4..643971e12cd 100644 --- a/drivers/thermal/ti-bandgap.c +++ b/drivers/thermal/ti-bandgap.c @@ -176,7 +176,7 @@ static int ti_bandgap_probe(struct udevice *dev) { struct ti_bandgap *bgp = dev_get_priv(dev); - bgp->base = devfdt_get_addr_index(dev, 1); + bgp->base = dev_read_addr_index(dev, 1); return 0; } -- cgit v1.3.1 From 8e4414d1a9832f640ffedbf90c42c99e2e7b0fa2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 14:50:03 +0800 Subject: misc: k3_avs: Use dev_read_addr_index() Use dev_read_addr_index() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/misc/k3_avs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 0774e0a4c9e..a885c99c547 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -300,7 +300,7 @@ static void k3_avs_program_tshut(struct k3_avs_privdata *priv) void __iomem *cfg2_base; void __iomem *fuse_base; - cfg2_base = (void __iomem *)devfdt_get_addr_index(priv->dev, 1); + cfg2_base = (void __iomem *)dev_read_addr_index(priv->dev, 1); if (IS_ERR(cfg2_base)) { dev_err(priv->dev, "cfg base is not defined\n"); return; @@ -319,7 +319,7 @@ static void k3_avs_program_tshut(struct k3_avs_privdata *priv) */ if (device_is_compatible(priv->dev, "ti,j721e-vtm")) { - fuse_base = (void __iomem *)devfdt_get_addr_index(priv->dev, 2); + fuse_base = (void __iomem *)dev_read_addr_index(priv->dev, 2); if (IS_ERR(fuse_base)) { dev_err(priv->dev, "fuse-base is not defined for J721E Soc\n"); return; -- cgit v1.3.1 From ebb9ee6ef48015d58a08ed8c8e21ad4cd4041e2b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 15:52:18 +0800 Subject: rng: rproc_rng200: Use dev_remap_addr() Use dev_remap_addr() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. And only mapping sizeof(void *) is wrong, RNG_FIFO_COUNT_OFFSET(0x24) is accessed in this driver. So dev_remap_addr() could also fix the mapping size. No functional changes. Signed-off-by: Peng Fan --- drivers/rng/iproc_rng200.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/rng/iproc_rng200.c b/drivers/rng/iproc_rng200.c index 4c49aa9e444..aa211df28cd 100644 --- a/drivers/rng/iproc_rng200.c +++ b/drivers/rng/iproc_rng200.c @@ -155,7 +155,7 @@ static int iproc_rng200_of_to_plat(struct udevice *dev) { struct iproc_rng200_plat *pdata = dev_get_plat(dev); - pdata->base = devfdt_map_physmem(dev, sizeof(void *)); + pdata->base = dev_remap_addr(dev); if (!pdata->base) return -ENODEV; -- cgit v1.3.1 From ffbfe1cec387e35eadf522e4a7d6ffdba956158b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 15:46:15 +0800 Subject: ata: mtk_ahci: Use dev_remap_addr_index() and ofnode API Use dev_remap_addr_index() instead of devfdt_remap_addr_index() to map the controller registers, removing the dependency on FDT-specific helpers. Replace the direct fdt_get_property() lookup combined with dev_of_offset() by dev_read_prop(). No functional changes. Signed-off-by: Peng Fan --- drivers/ata/mtk_ahci.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c index 53aabee0a5e..1d4245ee635 100644 --- a/drivers/ata/mtk_ahci.c +++ b/drivers/ata/mtk_ahci.c @@ -45,7 +45,9 @@ static int mtk_ahci_of_to_plat(struct udevice *dev) { struct mtk_ahci_priv *priv = dev_get_priv(dev); - priv->base = devfdt_remap_addr_index(dev, 0); + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; return 0; } @@ -54,11 +56,9 @@ static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv, struct udevice *dev) { struct mtk_ahci_priv *plat = dev_get_priv(dev); - const void *fdt = gd->fdt_blob; /* enable SATA function if needed */ - if (fdt_get_property(fdt, dev_of_offset(dev), - "mediatek,phy-mode", NULL)) { + if (dev_read_prop(dev, "mediatek,phy-mode", NULL)) { plat->mode = syscon_regmap_lookup_by_phandle(dev, "mediatek,phy-mode"); if (IS_ERR(plat->mode)) { @@ -69,8 +69,8 @@ static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv, SYS_CFG_SATA_MSK, SYS_CFG_SATA_EN); } - ofnode_read_u32(dev_ofnode(dev), "ports-implemented", - &hpriv->port_map); + dev_read_u32(dev, "ports-implemented", &hpriv->port_map); + return 0; } -- cgit v1.3.1 From 8d1d86ff58be46e17bb59b97c2ddc03f167acd05 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 15:46:16 +0800 Subject: ata: dwc_ahci: Use dev_read_addr_index() Use dev_read_addr_index() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/ata/dwc_ahci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c index b480cde4465..0431d370716 100644 --- a/drivers/ata/dwc_ahci.c +++ b/drivers/ata/dwc_ahci.c @@ -39,7 +39,7 @@ static int dwc_ahci_of_to_plat(struct udevice *dev) priv->base = map_physmem(dev_read_addr(dev), sizeof(void *), MAP_NOCACHE); - addr = devfdt_get_addr_index(dev, 1); + addr = dev_read_addr_index(dev, 1); if (addr != FDT_ADDR_T_NONE) { priv->wrapper_base = map_physmem(addr, sizeof(void *), MAP_NOCACHE); -- cgit v1.3.1 From 50b3c87e0e2b6037dfa4dd9ee1e0ddb42165e835 Mon Sep 17 00:00:00 2001 From: Vincent Jardin Date: Tue, 16 Dec 2025 01:53:52 +0100 Subject: net: mvpp2: fix NULL pointer dereference in mvpp2_phy_connect Fix two NULL pointer dereferences in mvpp2_phy_connect(): 1. port->phy_dev->dev is used in dev_warn() but port->phy_dev is not assigned yet (assigned later at line below). 2. port->phy_dev->dev is used in dev_err() inside the "if (!phy_dev)" block, which means phy_dev is NULL. Both cases would cause a crash if the PHY detection fails or returns a generic PHY. Use the already available 'dev' parameter instead. Fixes: 9db60ee470c2 ("net: mvpp2: Convert netdev_xxx to dev_xxx") Signed-off-by: Vincent Jardin --- drivers/net/mvpp2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index fc137df14c4..ae5920a0201 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4528,7 +4528,7 @@ static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port) */ if (phy_dev && phy_dev->drv->uid == 0xffffffff) {/* Generic phy */ - dev_warn(port->phy_dev->dev, + dev_warn(dev, "Marking phy as invalid, link will not be checked\n"); /* set phy_addr to invalid value */ port->phyaddr = PHY_MAX_ADDR; @@ -4540,7 +4540,7 @@ static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port) port->phy_dev = phy_dev; if (!phy_dev) { - dev_err(port->phy_dev->dev, "cannot connect to phy\n"); + dev_err(dev, "cannot connect to phy\n"); return; } phy_dev->supported &= PHY_GBIT_FEATURES; -- cgit v1.3.1 From a9cc75a25eb6b97ae8e22bdb63ef0bd2c6c690c9 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 19 Dec 2025 11:59:34 +1300 Subject: mtd: nand: pxa3xx: Pass valid dev to dev_err() info->controller.active is not initialised so the dev_err() call ends up dereferencing a null pointer causing a crash instead of outputting the error. Add a dev member to struct pxa3xx_nand_info and use that instead of info->controller.active->mtd.dev. Fixes: 661c98121d49 ("mtd: nand: pxa3xx: Fix not calling dev_xxx with a device") Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- drivers/mtd/nand/raw/pxa3xx_nand.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 7324dc72e0a..ef01d48acc0 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -184,6 +184,7 @@ struct pxa3xx_nand_host { struct pxa3xx_nand_info { struct nand_hw_control controller; struct pxa3xx_nand_platform_data *pdata; + struct udevice *dev; struct clk *clk; void __iomem *mmio_base; @@ -585,8 +586,7 @@ static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) ts = get_timer(0); while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) { if (get_timer(ts) > TIMEOUT_DRAIN_FIFO) { - dev_err(info->controller.active->mtd.dev, - "Timeout on RDDREQ while draining the FIFO\n"); + dev_err(info->dev, "Timeout on RDDREQ while draining the FIFO\n"); return; } } @@ -638,8 +638,7 @@ static void handle_data_pio(struct pxa3xx_nand_info *info) DIV_ROUND_UP(info->step_spare_size, 4)); break; default: - dev_err(info->controller.active->mtd.dev, - "%s: invalid state %d\n", __func__, info->state); + dev_err(info->dev, "%s: invalid state %d\n", __func__, info->state); BUG(); } @@ -1557,8 +1556,7 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info, ecc->size = 512; if (ecc_stepsize != 512 || !(nfc_layouts[i].strength)) { - dev_err(info->controller.active->mtd.dev, - "ECC strength %d at page size %d is not supported\n", + dev_err(info->dev, "ECC strength %d at page size %d is not supported\n", strength, page_size); return -ENODEV; } @@ -1799,6 +1797,7 @@ static int pxa3xx_nand_probe(struct udevice *dev) if (ret) return ret; + info->dev = dev; pdata = info->pdata; ret = alloc_nand_resource(dev, info); -- cgit v1.3.1 From bd75c262403062254dfec953bff34bc9cc467206 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 25 Feb 2026 08:10:08 +0100 Subject: serial: serial_octeon_bootcmd.c: use correct Kconfig symbol CONFIG_SYS_IS_IN_ENV does not exist. CONFIG_SYS_CONSOLE_IS_IN_ENV seems to be needed here. Fixes: f1054661e50f ("serial: serial_octeon_bootcmd.c: Add PCI remote console support") Signed-off-by: Heinrich Schuchardt Reviewed-by: Stefan Roese --- drivers/serial/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 5f8b98f0704..c6e457572b1 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -1024,7 +1024,7 @@ config OCTEON_SERIAL_BOOTCMD bool "MIPS Octeon PCI remote bootcmd input" depends on ARCH_OCTEON depends on DM_SERIAL - select SYS_IS_IN_ENV + select SYS_CONSOLE_IS_IN_ENV select CONSOLE_MUX help This driver supports remote input over the PCIe bus from a host -- cgit v1.3.1 From dd1084ed2e91ef013244d83301f817f77a5734c9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:21:56 +0200 Subject: pinctrl: armada-38x: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Stefan Roese --- drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 78184d2860a..c18afe958dc 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -550,7 +550,7 @@ static int armada_38x_pinctrl_probe(struct udevice *dev) return 0; } -struct pinctrl_ops armada_37xx_pinctrl_ops = { +static const struct pinctrl_ops armada_37xx_pinctrl_ops = { .get_pins_count = armada_38x_pinctrl_get_pins_count, .get_pin_name = armada_38x_pinctrl_get_pin_name, .get_functions_count = armada_38x_pinctrl_get_functions_count, -- cgit v1.3.1 From eab66c3a9085e07b227847b0c442ee8d2efb241d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 15:53:06 +0800 Subject: timer: orion: Use dev_remap_addr_index() Use dev_remap_addr_index() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan --- drivers/timer/orion-timer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/timer/orion-timer.c b/drivers/timer/orion-timer.c index 821b681a232..4d1c6b5cef2 100644 --- a/drivers/timer/orion-timer.c +++ b/drivers/timer/orion-timer.c @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include @@ -113,7 +114,7 @@ static int orion_timer_probe(struct udevice *dev) enum input_clock_type type = dev_get_driver_data(dev); struct orion_timer_priv *priv = dev_get_priv(dev); - priv->base = devfdt_remap_addr_index(dev, 0); + priv->base = dev_remap_addr_index(dev, 0); if (!priv->base) { debug("unable to map registers\n"); return -ENOMEM; -- cgit v1.3.1 From 379e9ab2d08328b81ed949b95aea244a823fe4ff Mon Sep 17 00:00:00 2001 From: Julien Stephan Date: Wed, 29 Apr 2026 15:58:56 +0200 Subject: net: Fix alphabetical ordering in drivers/net/Makefile Reorder entries to maintain alphabetical sorting by CONFIG_ names: - Move CONFIG_DWC_ETH_QOS_QCOM before CONFIG_DWC_ETH_QOS_ROCKCHIP - Move CONFIG_DWC_ETH_XGMAC after CONFIG_DWC_ETH_QOS_STM32 - Move CONFIG_MDIO_GPIO_BITBANG before CONFIG_MDIO_IPQ4019 - Move airoha directory at the end This ensures consistent alphabetical ordering throughout the Makefile. Signed-off-by: Julien Stephan Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20260429-add-ethernet-support-for-genio-520-720-v4-3-be54e17239b7@baylibre.com Signed-off-by: David Lechner --- drivers/net/Makefile | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 5e90183d090..c485068e5d2 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o -obj-y += airoha/ obj-$(CONFIG_AIROHA_ETH) += airoha_eth.o obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o @@ -22,12 +21,12 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_DWC_ETH_QOS_ADI) += dwc_eth_qos_adi.o obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o obj-$(CONFIG_DWC_ETH_QOS_INTEL) += dwc_eth_qos_intel.o -obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o -obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o -obj-$(CONFIG_DWC_ETH_XGMAC_SOCFPGA) += dwc_eth_xgmac_socfpga.o +obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o +obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o +obj-$(CONFIG_DWC_ETH_XGMAC_SOCFPGA) += dwc_eth_xgmac_socfpga.o obj-$(CONFIG_E1000) += e1000.o obj-$(CONFIG_E1000_SPI) += e1000_spi.o obj-$(CONFIG_EEPRO100) += eepro100.o @@ -62,9 +61,9 @@ obj-$(CONFIG_KSZ9477) += ksz9477.o obj-$(CONFIG_LITEETH) += liteeth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o +obj-$(CONFIG_MDIO_GPIO_BITBANG) += mdio_gpio.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o -obj-$(CONFIG_MDIO_GPIO_BITBANG) += mdio_gpio.o obj-$(CONFIG_MDIO_MT7531_MMIO) += mdio-mt7531-mmio.o obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o @@ -109,6 +108,7 @@ obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o obj-$(CONFIG_XILINX_AXIMRMAC) += xilinx_axi_mrmac.o obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o +obj-y += airoha/ obj-y += mscc_eswitch/ obj-y += phy/ obj-y += qe/ -- cgit v1.3.1 From 2287b573dffe86e26171352c819dc562c976d6b9 Mon Sep 17 00:00:00 2001 From: Julien Stephan Date: Wed, 29 Apr 2026 15:58:57 +0200 Subject: net: Fix alphabetical ordering in drivers/net/Kconfig Reorder entries under DWC_ETH_QOS to maintain alphabetical sorting by CONFIG_ names: - Move CONFIG_DWC_ETH_QOS_QCOM before CONFIG_DWC_ETH_QOS_ROCKCHIP - Move CONFIG_DWC_ETH_QOS_STARFIVE after CONFIG_DWC_ETH_QOS_ROCKCHIP Signed-off-by: Julien Stephan Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20260429-add-ethernet-support-for-genio-520-720-v4-4-be54e17239b7@baylibre.com Signed-off-by: David Lechner --- drivers/net/Kconfig | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f2e838b84de..4fc7552d19d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -246,6 +246,13 @@ config DWC_ETH_QOS_INTEL The Synopsys Designware Ethernet QOS IP block with the specific configuration used in the Intel Elkhart-Lake soc. +config DWC_ETH_QOS_QCOM + bool "Synopsys DWC Ethernet QOS device support for Qcom SoCs" + depends on DWC_ETH_QOS + help + The Synopsys Designware Ethernet QOS IP block with specific + configuration used in Qcom QCS404 SoC. + config DWC_ETH_QOS_ROCKCHIP bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs" depends on DWC_ETH_QOS && ARCH_ROCKCHIP @@ -254,6 +261,13 @@ config DWC_ETH_QOS_ROCKCHIP The Synopsys Designware Ethernet QOS IP block with specific configuration used in Rockchip SoCs. +config DWC_ETH_QOS_STARFIVE + bool "Synopsys DWC Ethernet QOS device support for STARFIVE" + depends on DWC_ETH_QOS + help + The Synopsys Designware Ethernet QOS IP block with specific + configuration used in STARFIVE JH7110 soc. + config DWC_ETH_QOS_STM32 bool "Synopsys DWC Ethernet QOS device support for STM32" depends on DWC_ETH_QOS && ARCH_STM32MP @@ -271,20 +285,6 @@ config DWC_ETH_QOS_TEGRA186 The Synopsys Designware Ethernet QOS IP block with specific configuration used in NVIDIA's Tegra186 chip. -config DWC_ETH_QOS_QCOM - bool "Synopsys DWC Ethernet QOS device support for Qcom SoCs" - depends on DWC_ETH_QOS - help - The Synopsys Designware Ethernet QOS IP block with specific - configuration used in Qcom QCS404 SoC. - -config DWC_ETH_QOS_STARFIVE - bool "Synopsys DWC Ethernet QOS device support for STARFIVE" - depends on DWC_ETH_QOS - help - The Synopsys Designware Ethernet QOS IP block with specific - configuration used in STARFIVE JH7110 soc. - config E1000 bool "Intel PRO/1000 Gigabit Ethernet support" depends on PCI -- cgit v1.3.1 From 751af7d98f0182f679cd1682c4b34421f94eb8c5 Mon Sep 17 00:00:00 2001 From: Julien Stephan Date: Wed, 29 Apr 2026 15:58:58 +0200 Subject: net: phy: air_phy_lib: Factorize BuckPBus register In preparation of Airoha AN8801R PHY support, move the BuckPBus register accessors and definitions, present in air_en8811h driver, into the Airoha PHY shared code (air_phy_lib), so they will be usable by the new driver without duplicating them. Also, update air_en8811h driver to use the new function names. Adapted from [1]. [1]: https://lore.kernel.org/all/20260326-add-airoha-an8801-support-v2-2-1a42d6b6050f@collabora.com/ Signed-off-by: Julien Stephan Link: https://patch.msgid.link/20260429-add-ethernet-support-for-genio-520-720-v4-5-be54e17239b7@baylibre.com Signed-off-by: David Lechner --- MAINTAINERS | 2 +- drivers/net/phy/airoha/Kconfig | 6 + drivers/net/phy/airoha/Makefile | 1 + drivers/net/phy/airoha/air_en8811.c | 303 ++++++++--------------------------- drivers/net/phy/airoha/air_phy_lib.c | 216 +++++++++++++++++++++++++ drivers/net/phy/airoha/air_phy_lib.h | 39 +++++ 6 files changed, 329 insertions(+), 238 deletions(-) create mode 100644 drivers/net/phy/airoha/air_phy_lib.c create mode 100644 drivers/net/phy/airoha/air_phy_lib.h (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index 4253334e355..dcaf1e08354 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -61,7 +61,7 @@ F: lib/acpi/ AIROHA PHY M: Tommy Shih S: Maintained -F: drivers/net/phy/airoha/air_en8811.c +F: drivers/net/phy/airoha/ ALIST M: Simon Glass diff --git a/drivers/net/phy/airoha/Kconfig b/drivers/net/phy/airoha/Kconfig index 4139df343ad..b48426bf0fa 100644 --- a/drivers/net/phy/airoha/Kconfig +++ b/drivers/net/phy/airoha/Kconfig @@ -7,7 +7,13 @@ config PHY_AIROHA_EN8811 depends on PHY_AIROHA depends on SUPPORTS_FW_LOADER select FW_LOADER + select PHY_AIROHA_PHYLIB select PHY_COMMON_PROPS help AIROHA EN8811H supported. AIROHA AN8811HB supported. + +config PHY_AIROHA_PHYLIB + bool + help + Airoha Ethernet PHY common library diff --git a/drivers/net/phy/airoha/Makefile b/drivers/net/phy/airoha/Makefile index 84d23b19ab0..59051caecef 100644 --- a/drivers/net/phy/airoha/Makefile +++ b/drivers/net/phy/airoha/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_AIROHA_EN8811) += air_en8811.o +obj-$(CONFIG_PHY_AIROHA_PHYLIB) += air_phy_lib.o diff --git a/drivers/net/phy/airoha/air_en8811.c b/drivers/net/phy/airoha/air_en8811.c index 32f06dd6dfa..7a07be2e956 100644 --- a/drivers/net/phy/airoha/air_en8811.c +++ b/drivers/net/phy/airoha/air_en8811.c @@ -25,6 +25,8 @@ #include #include +#include "air_phy_lib.h" + /* MII Registers */ #define AIR_AUX_CTRL_STATUS 0x1d #define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2) @@ -33,10 +35,6 @@ #define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8 #define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc -#define AIR_EXT_PAGE_ACCESS 0x1f -#define AIR_PHY_PAGE_STANDARD 0x0000 -#define AIR_PHY_PAGE_EXTENDED_4 0x0004 - #define AIR_PBUS_MODE_ADDR_HIGH 0x1c /* MII Registers Page 4 */ #define AIR_BPBUS_MODE 0x10 @@ -310,166 +308,6 @@ static int air_pbus_reg_write(struct phy_device *phydev, return ret; } -static int air_buckpbus_reg_write(struct phy_device *phydev, - u32 pbus_address, u32 pbus_data) -{ - int ret, saved_page; - - saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); - if (saved_page < 0) - return saved_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_MODE, - AIR_BPBUS_MODE_ADDR_FIXED); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_HIGH, - upper_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_LOW, - lower_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_HIGH, - upper_16_bits(pbus_data)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_LOW, - lower_16_bits(pbus_data)); - if (ret < 0) - goto restore_page; - -restore_page: - if (ret < 0) - dev_err(phydev->dev, "%s 0x%08x failed: %d\n", __func__, - pbus_address, ret); - - return phy_restore_page(phydev, saved_page, ret); -} - -static int air_buckpbus_reg_read(struct phy_device *phydev, - u32 pbus_address, u32 *pbus_data) -{ - int pbus_data_low, pbus_data_high; - int ret = 0, saved_page; - - saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); - if (saved_page < 0) - return saved_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_MODE, - AIR_BPBUS_MODE_ADDR_FIXED); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_HIGH, - upper_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_LOW, - lower_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - pbus_data_high = phy_read(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_DATA_HIGH); - if (pbus_data_high < 0) { - ret = pbus_data_high; - goto restore_page; - } - - pbus_data_low = phy_read(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_DATA_LOW); - if (pbus_data_low < 0) { - ret = pbus_data_low; - goto restore_page; - } - - *pbus_data = pbus_data_low | (pbus_data_high << 16); - -restore_page: - if (ret < 0) - dev_err(phydev->dev, "%s 0x%08x failed: %d\n", __func__, - pbus_address, ret); - - return phy_restore_page(phydev, saved_page, ret); -} - -static int air_buckpbus_reg_modify(struct phy_device *phydev, - u32 pbus_address, u32 mask, u32 set) -{ - int pbus_data_low, pbus_data_high; - u32 pbus_data_old, pbus_data_new; - int ret = 0, saved_page; - - saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); - if (saved_page < 0) - return saved_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_MODE, - AIR_BPBUS_MODE_ADDR_FIXED); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_HIGH, - upper_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_LOW, - lower_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - pbus_data_high = phy_read(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_DATA_HIGH); - if (pbus_data_high < 0) { - ret = pbus_data_high; - goto restore_page; - } - - pbus_data_low = phy_read(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_DATA_LOW); - if (pbus_data_low < 0) { - ret = pbus_data_low; - goto restore_page; - } - - pbus_data_old = pbus_data_low | (pbus_data_high << 16); - pbus_data_new = (pbus_data_old & ~mask) | set; - if (pbus_data_new == pbus_data_old) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_HIGH, - upper_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_LOW, - lower_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_HIGH, - upper_16_bits(pbus_data_new)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_LOW, - lower_16_bits(pbus_data_new)); - if (ret < 0) - goto restore_page; - -restore_page: - if (ret < 0) - dev_err(phydev->dev, "%s 0x%08x failed: %d\n", __func__, - pbus_address, ret); - - return phy_restore_page(phydev, saved_page, ret); -} - static int air_write_buf(struct phy_device *phydev, unsigned long address, unsigned long array_size, const unsigned char *buffer) { @@ -540,12 +378,12 @@ static int an8811hb_check_crc(struct phy_device *phydev, u32 pbus_value; /* Configure CRC */ - ret = air_buckpbus_reg_modify(phydev, set1, AN8811HB_CRC_RD_EN, - AN8811HB_CRC_RD_EN); + ret = air_phy_buckpbus_reg_modify(phydev, set1, AN8811HB_CRC_RD_EN, + AN8811HB_CRC_RD_EN); if (ret < 0) return ret; - ret = air_buckpbus_reg_read(phydev, set1, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, set1, &pbus_value); if (ret < 0) return ret; @@ -554,14 +392,14 @@ static int an8811hb_check_crc(struct phy_device *phydev, do { mdelay(300); - ret = air_buckpbus_reg_read(phydev, mon2, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, mon2, &pbus_value); if (ret < 0) return ret; debug("%d: reg 0x%x val 0x%x!\n", __LINE__, mon2, pbus_value); if (pbus_value & AN8811HB_CRC_ST) { - ret = air_buckpbus_reg_read(phydev, mon3, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, mon3, &pbus_value); if (ret < 0) return ret; @@ -585,11 +423,11 @@ static int an8811hb_check_crc(struct phy_device *phydev, } } while (--retry); - ret = air_buckpbus_reg_modify(phydev, set1, AN8811HB_CRC_RD_EN, 0); + ret = air_phy_buckpbus_reg_modify(phydev, set1, AN8811HB_CRC_RD_EN, 0); if (ret < 0) return ret; - ret = air_buckpbus_reg_read(phydev, set1, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, set1, &pbus_value); if (ret < 0) return ret; @@ -647,9 +485,9 @@ static int an8811hb_surge_protect_cfg(struct phy_device *phydev) return ret; } - ret = air_buckpbus_reg_modify(phydev, AIR_PHY_CONTROL, - AIR_PHY_CONTROL_SURGE_5R, - AIR_PHY_CONTROL_SURGE_5R); + ret = air_phy_buckpbus_reg_modify(phydev, AIR_PHY_CONTROL, + AIR_PHY_CONTROL_SURGE_5R, + AIR_PHY_CONTROL_SURGE_5R); if (ret < 0) return ret; @@ -707,14 +545,14 @@ static int en8811h_load_firmware(struct phy_device *phydev) goto en8811h_load_firmware_out; } - ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, - EN8811H_FW_CTRL_1_START); + ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_START); if (ret < 0) goto en8811h_load_firmware_out; - ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, - EN8811H_FW_CTRL_2_LOADING, - EN8811H_FW_CTRL_2_LOADING); + ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, + EN8811H_FW_CTRL_2_LOADING, + EN8811H_FW_CTRL_2_LOADING); if (ret < 0) goto en8811h_load_firmware_out; @@ -728,13 +566,13 @@ static int en8811h_load_firmware(struct phy_device *phydev) if (ret < 0) goto en8811h_load_firmware_out; - ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, - EN8811H_FW_CTRL_2_LOADING, 0); + ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, + EN8811H_FW_CTRL_2_LOADING, 0); if (ret < 0) goto en8811h_load_firmware_out; - ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, - EN8811H_FW_CTRL_1_FINISH); + ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_FINISH); if (ret < 0) goto en8811h_load_firmware_out; @@ -742,8 +580,8 @@ static int en8811h_load_firmware(struct phy_device *phydev) if (ret < 0) goto en8811h_load_firmware_out; - air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, - &priv->firmware_version); + air_phy_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, + &priv->firmware_version); dev_info(phydev->dev, "MD32 firmware version: %08x\n", priv->firmware_version); @@ -779,8 +617,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev) if (ret < 0) goto an8811hb_load_firmware_out; - ret = air_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, - AIR_PHY_FW_CTRL_1_START); + ret = air_phy_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, + AIR_PHY_FW_CTRL_1_START); if (ret < 0) goto an8811hb_load_firmware_out; @@ -804,8 +642,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev) if (ret < 0) goto an8811hb_load_firmware_out; - ret = air_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, - AIR_PHY_FW_CTRL_1_FINISH); + ret = air_phy_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, + AIR_PHY_FW_CTRL_1_FINISH); if (ret < 0) goto an8811hb_load_firmware_out; @@ -818,7 +656,7 @@ static int an8811hb_load_firmware(struct phy_device *phydev) do { mdelay(300); - ret = air_buckpbus_reg_read(phydev, AIR_PHY_FW_CTRL_1, ®_val); + ret = air_phy_buckpbus_reg_read(phydev, AIR_PHY_FW_CTRL_1, ®_val); if (ret < 0) goto an8811hb_load_firmware_out; @@ -828,8 +666,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev) debug("%d: reg 0x%x val 0x%x!\n", __LINE__, AIR_PHY_FW_CTRL_1, reg_val); - ret = air_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, - AIR_PHY_FW_CTRL_1_FINISH); + ret = air_phy_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, + AIR_PHY_FW_CTRL_1_FINISH); if (ret < 0) goto an8811hb_load_firmware_out; @@ -839,8 +677,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev) if (ret < 0) goto an8811hb_load_firmware_out; - air_buckpbus_reg_read(phydev, AIR_PHY_MD32FW_VERSION, - &priv->firmware_version); + air_phy_buckpbus_reg_read(phydev, AIR_PHY_MD32FW_VERSION, + &priv->firmware_version); debug("MD32 firmware version: %08x\n", priv->firmware_version); @@ -859,17 +697,17 @@ int an8811hb_cko_cfg(struct phy_device *phydev) int ret = 0; if (!ofnode_read_bool(node, "airoha,phy-output-clock")) { - ret = air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV, - AN8811HB_CLK_DRV_CKO_MASK, - AN8811HB_CLK_DRV_CKOPWD | - AN8811HB_CLK_DRV_CKO_LDPWD | - AN8811HB_CLK_DRV_CKO_LPPWD); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV, + AN8811HB_CLK_DRV_CKO_MASK, + AN8811HB_CLK_DRV_CKOPWD | + AN8811HB_CLK_DRV_CKO_LDPWD | + AN8811HB_CLK_DRV_CKO_LPPWD); if (ret < 0) return ret; debug("CKO Output mode - Disabled\n"); } else { - ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); if (ret < 0) return ret; @@ -888,13 +726,13 @@ static int en8811h_restart_mcu(struct phy_device *phydev) if (ret < 0) return ret; - ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, - EN8811H_FW_CTRL_1_START); + ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_START); if (ret < 0) return ret; - return air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, - EN8811H_FW_CTRL_1_FINISH); + return air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_FINISH); } static int air_led_hw_control_set(struct phy_device *phydev, u8 index, @@ -1083,9 +921,10 @@ static int en8811h_config_serdes_polarity(struct phy_device *phydev) if (pol == PHY_POL_NORMAL) pbus_value |= EN8811H_POLARITY_TX_NORMAL; - return air_buckpbus_reg_modify(phydev, EN8811H_POLARITY, - EN8811H_POLARITY_RX_REVERSE | - EN8811H_POLARITY_TX_NORMAL, pbus_value); + return air_phy_buckpbus_reg_modify(phydev, EN8811H_POLARITY, + EN8811H_POLARITY_RX_REVERSE | + EN8811H_POLARITY_TX_NORMAL, + pbus_value); } static int en8811h_config(struct phy_device *phydev) @@ -1170,12 +1009,12 @@ static int an8811hb_config(struct phy_device *phydev) priv->mcu_needs_restart = true; } - ret = air_buckpbus_reg_read(phydev, AN8811HB_PRO_ID, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_PRO_ID, &pbus_value); if (ret < 0) return ret; priv->pro_id = (pbus_value & AN8811HB_PRO_ID_VERSION) + 1; - ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); if (ret < 0) return ret; priv->pkg_sel = (pbus_value & AN8811HB_HWTRAP2_PKG) >> 12; @@ -1191,8 +1030,8 @@ static int an8811hb_config(struct phy_device *phydev) pbus_value |= AN8811HB_RX_POLARITY_NORMAL; debug("1 pbus_value 0x%x\n", pbus_value); - ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY, - AN8811HB_RX_POLARITY_NORMAL, pbus_value); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY, + AN8811HB_RX_POLARITY_NORMAL, pbus_value); if (ret < 0) return ret; @@ -1203,35 +1042,35 @@ static int an8811hb_config(struct phy_device *phydev) pbus_value |= AN8811HB_TX_POLARITY_NORMAL; debug("2 pbus_value 0x%x\n", pbus_value); - ret = air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY, - AN8811HB_TX_POLARITY_NORMAL, pbus_value); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY, + AN8811HB_TX_POLARITY_NORMAL, pbus_value); if (ret < 0) return ret; /* Configure led gpio pins as output */ if (priv->pkg_sel) { - ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, - AN8811HB_GPIO_OUTPUT_MASK, - AN8811HB_GPIO_OUTPUT_0115); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, + AN8811HB_GPIO_OUTPUT_MASK, + AN8811HB_GPIO_OUTPUT_0115); if (ret < 0) return ret; - ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_SEL_1, - AN8811HB_GPIO_SEL_1_0_MASK | - AN8811HB_GPIO_SEL_1_1_MASK, - AN8811HB_GPIO_SEL_1_0 | - AN8811HB_GPIO_SEL_1_1); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_SEL_1, + AN8811HB_GPIO_SEL_1_0_MASK | + AN8811HB_GPIO_SEL_1_1_MASK, + AN8811HB_GPIO_SEL_1_0 | + AN8811HB_GPIO_SEL_1_1); if (ret < 0) return ret; - ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_SEL_2, - AN8811HB_GPIO_SEL_2_15_MASK, - AN8811HB_GPIO_SEL_2_15); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_SEL_2, + AN8811HB_GPIO_SEL_2_15_MASK, + AN8811HB_GPIO_SEL_2_15); if (ret < 0) return ret; } else { - ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, - AN8811HB_GPIO_OUTPUT_345, - AN8811HB_GPIO_OUTPUT_345); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, + AN8811HB_GPIO_OUTPUT_345, + AN8811HB_GPIO_OUTPUT_345); if (ret < 0) return ret; } @@ -1401,16 +1240,6 @@ static int en8811h_probe(struct phy_device *phydev) return 0; } -static int air_phy_read_page(struct phy_device *phydev) -{ - return phy_read(phydev, MDIO_DEVAD_NONE, AIR_EXT_PAGE_ACCESS); -} - -static int air_phy_write_page(struct phy_device *phydev, int page) -{ - return phy_write(phydev, MDIO_DEVAD_NONE, AIR_EXT_PAGE_ACCESS, page); -} - U_BOOT_PHY_DRIVER(en8811h) = { .name = "Airoha EN8811H", .uid = EN8811H_PHY_ID, diff --git a/drivers/net/phy/airoha/air_phy_lib.c b/drivers/net/phy/airoha/air_phy_lib.c new file mode 100644 index 00000000000..61c3bf82822 --- /dev/null +++ b/drivers/net/phy/airoha/air_phy_lib.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Airoha Ethernet PHY common library + * + * Copyright (C) 2026 Airoha Technology Corp. + * Copyright (C) 2026 Collabora Ltd. + * Louis-Alexis Eyraud + * + * Adapated from https://lore.kernel.org/all/20260326-add-airoha-an8801-support-v2-2-1a42d6b6050f@collabora.com/ + */ + +#include +#include +#include + +#include "air_phy_lib.h" + +#define AIR_EXT_PAGE_ACCESS 0x1f + +static int __air_buckpbus_reg_read(struct phy_device *phydev, + u32 pbus_address, u32 *pbus_data) +{ + int pbus_data_low, pbus_data_high; + int ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_MODE, + AIR_BPBUS_MODE_ADDR_FIXED); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_HIGH, + upper_16_bits(pbus_address)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_LOW, + lower_16_bits(pbus_address)); + if (ret < 0) + return ret; + + pbus_data_high = phy_read(phydev, MDIO_DEVAD_NONE, + AIR_BPBUS_RD_DATA_HIGH); + if (pbus_data_high < 0) + return pbus_data_high; + + pbus_data_low = phy_read(phydev, MDIO_DEVAD_NONE, + AIR_BPBUS_RD_DATA_LOW); + if (pbus_data_low < 0) + return pbus_data_low; + + *pbus_data = pbus_data_low | (pbus_data_high << 16); + return 0; +} + +static int __air_buckpbus_reg_write(struct phy_device *phydev, + u32 pbus_address, u32 pbus_data) +{ + int ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_MODE, + AIR_BPBUS_MODE_ADDR_FIXED); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_HIGH, + upper_16_bits(pbus_address)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_LOW, + lower_16_bits(pbus_address)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_HIGH, + upper_16_bits(pbus_data)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_LOW, + lower_16_bits(pbus_data)); + if (ret < 0) + return ret; + + return 0; +} + +static int __air_buckpbus_reg_modify(struct phy_device *phydev, + u32 pbus_address, u32 mask, u32 set) +{ + int pbus_data_low, pbus_data_high; + u32 pbus_data_old, pbus_data_new; + int ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_MODE, + AIR_BPBUS_MODE_ADDR_FIXED); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_HIGH, + upper_16_bits(pbus_address)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_LOW, + lower_16_bits(pbus_address)); + if (ret < 0) + return ret; + + pbus_data_high = phy_read(phydev, MDIO_DEVAD_NONE, + AIR_BPBUS_RD_DATA_HIGH); + if (pbus_data_high < 0) + return pbus_data_high; + + pbus_data_low = phy_read(phydev, MDIO_DEVAD_NONE, + AIR_BPBUS_RD_DATA_LOW); + if (pbus_data_low < 0) + return pbus_data_low; + + pbus_data_old = pbus_data_low | (pbus_data_high << 16); + pbus_data_new = (pbus_data_old & ~mask) | set; + if (pbus_data_new == pbus_data_old) + return 0; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_HIGH, + upper_16_bits(pbus_address)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_LOW, + lower_16_bits(pbus_address)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_HIGH, + upper_16_bits(pbus_data_new)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_LOW, + lower_16_bits(pbus_data_new)); + if (ret < 0) + return ret; + + return 0; +} + +int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address, + u32 *pbus_data) +{ + int saved_page; + int ret = 0; + + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); + + if (saved_page >= 0) { + ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data); + if (ret < 0) + dev_err(phydev->dev, "%s 0x%08x failed: %d\n", __func__, + pbus_address, ret); + } + + return phy_restore_page(phydev, saved_page, ret); +} + +int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address, + u32 pbus_data) +{ + int saved_page; + int ret = 0; + + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); + + if (saved_page >= 0) { + ret = __air_buckpbus_reg_write(phydev, pbus_address, + pbus_data); + if (ret < 0) + dev_err(phydev->dev, "%s 0x%08x failed: %d\n", __func__, + pbus_address, ret); + } + + return phy_restore_page(phydev, saved_page, ret); +} + +int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address, + u32 mask, u32 set) +{ + int saved_page; + int ret = 0; + + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); + + if (saved_page >= 0) { + ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask, + set); + if (ret < 0) + dev_err(phydev->dev, "%s 0x%08x failed: %d\n", __func__, + pbus_address, ret); + } + + return phy_restore_page(phydev, saved_page, ret); +} + +int air_phy_read_page(struct phy_device *phydev) +{ + return phy_read(phydev, MDIO_DEVAD_NONE, AIR_EXT_PAGE_ACCESS); +} + +int air_phy_write_page(struct phy_device *phydev, int page) +{ + return phy_write(phydev, MDIO_DEVAD_NONE, AIR_EXT_PAGE_ACCESS, page); +} + +MODULE_DESCRIPTION("Airoha PHY Library"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Louis-Alexis Eyraud"); diff --git a/drivers/net/phy/airoha/air_phy_lib.h b/drivers/net/phy/airoha/air_phy_lib.h new file mode 100644 index 00000000000..845d2f7cfb4 --- /dev/null +++ b/drivers/net/phy/airoha/air_phy_lib.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2026 Airoha Technology Corp. + * Copyright (C) 2026 Collabora Ltd. + * Louis-Alexis Eyraud + */ + +#ifndef __AIR_PHY_LIB_H +#define __AIR_PHY_LIB_H + +#define AIR_EXT_PAGE_ACCESS 0x1f + +#define AIR_PHY_PAGE_STANDARD 0x0000 +#define AIR_PHY_PAGE_EXTENDED_1 0x0001 +#define AIR_PHY_PAGE_EXTENDED_4 0x0004 + +/* MII Registers Page 4*/ +#define AIR_BPBUS_MODE 0x10 +#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000 +#define AIR_BPBUS_MODE_ADDR_INCR BIT(15) +#define AIR_BPBUS_WR_ADDR_HIGH 0x11 +#define AIR_BPBUS_WR_ADDR_LOW 0x12 +#define AIR_BPBUS_WR_DATA_HIGH 0x13 +#define AIR_BPBUS_WR_DATA_LOW 0x14 +#define AIR_BPBUS_RD_ADDR_HIGH 0x15 +#define AIR_BPBUS_RD_ADDR_LOW 0x16 +#define AIR_BPBUS_RD_DATA_HIGH 0x17 +#define AIR_BPBUS_RD_DATA_LOW 0x18 + +int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address, + u32 mask, u32 set); +int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address, + u32 *pbus_data); +int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address, + u32 pbus_data); +int air_phy_read_page(struct phy_device *phydev); +int air_phy_write_page(struct phy_device *phydev, int page); + +#endif /* __AIR_PHY_LIB_H */ -- cgit v1.3.1 From 227243b67e6ff65afd7b1a16d9baed4f17689c0a Mon Sep 17 00:00:00 2001 From: Julien Stephan Date: Wed, 29 Apr 2026 15:58:59 +0200 Subject: net: phy: Add airoha AN8801 ethernet phy driver Add Airoha AN8801 Ethernet PHY driver (air_an8801.c). Implement CL22/CL45 MDIO access, LED control, and RGMII delay configuration. Provide probe, initialization, LED setup, and status handling. Expose DTS properties for clock delays. Register driver with PHY framework and trigger on startup. Signed-off-by: Yanqing Wang Signed-off-by: Julien Stephan Reviewed-by: Kevin-KW Huang Link: https://patch.msgid.link/20260429-add-ethernet-support-for-genio-520-720-v4-6-be54e17239b7@baylibre.com Signed-off-by: David Lechner --- MAINTAINERS | 1 + drivers/net/phy/airoha/Kconfig | 7 + drivers/net/phy/airoha/Makefile | 1 + drivers/net/phy/airoha/air_an8801.c | 594 ++++++++++++++++++++++++++++++++++++ 4 files changed, 603 insertions(+) create mode 100644 drivers/net/phy/airoha/air_an8801.c (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index dcaf1e08354..474b2af11bd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -60,6 +60,7 @@ F: lib/acpi/ AIROHA PHY M: Tommy Shih +M: Kevin-KW Huang S: Maintained F: drivers/net/phy/airoha/ diff --git a/drivers/net/phy/airoha/Kconfig b/drivers/net/phy/airoha/Kconfig index b48426bf0fa..2d58d674200 100644 --- a/drivers/net/phy/airoha/Kconfig +++ b/drivers/net/phy/airoha/Kconfig @@ -2,6 +2,13 @@ menuconfig PHY_AIROHA bool "Airoha Ethernet PHYs support" +config PHY_AIROHA_AN8801 + bool "Airoha Ethernet AN8801 support" + depends on PHY_AIROHA + select PHY_AIROHA_PHYLIB + help + Currently support AIROHA AN8801 1G PHY. + config PHY_AIROHA_EN8811 bool "Airoha Ethernet EN8811H support" depends on PHY_AIROHA diff --git a/drivers/net/phy/airoha/Makefile b/drivers/net/phy/airoha/Makefile index 59051caecef..25e44004cfd 100644 --- a/drivers/net/phy/airoha/Makefile +++ b/drivers/net/phy/airoha/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_AIROHA_AN8801) += air_an8801.o obj-$(CONFIG_PHY_AIROHA_EN8811) += air_en8811.o obj-$(CONFIG_PHY_AIROHA_PHYLIB) += air_phy_lib.o diff --git a/drivers/net/phy/airoha/air_an8801.c b/drivers/net/phy/airoha/air_an8801.c new file mode 100644 index 00000000000..9d9958fc665 --- /dev/null +++ b/drivers/net/phy/airoha/air_an8801.c @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * air_an8801.c - PHY driver for Airoha AN8801. + * Copyright (c) 2026 Airoha Technology Corp. + * Copyright (C) 2026 BayLibre, SAS. + * Author: Kevin-KW Huang + * Sita Huang + * Julien Stephan + */ + +#include +#include +#include + +#include "air_phy_lib.h" + +#define AN8801R_PHY_ID1 0xc0ff +#define AN8801R_PHY_ID2 0x0421 +#define AN8801R_PHY_ID ((u32)((AN8801R_PHY_ID1 << 16) | AN8801R_PHY_ID2)) + +#define AN8801R_MAX_LED_SIZE 3 + +/* MII Registers - Airoha Page 4 */ +#define AN8801_PBUS_ACCESS BIT(28) + +/* BPBUS Registers */ +#define AN8801_BPBUS_REG_LED_GPIO 0x54 +#define AN8801_BPBUS_REG_LED_ID_SEL 0x58 +#define LED_ID_GPIO_SEL(led, gpio) ((led) << ((gpio) * 3)) + +#define AN8801_BPBUS_REG_GPIO_MODE 0x70 + +#define AN8801_BPBUS_REG_LINK_MODE 0x5054 +#define AN8801_BPBUS_LINK_MODE_1000 BIT(0) + +#define AN8801_BPBUS_REG_BYPASS_PTP 0x21c004 +#define AN8801_BYP_PTP_RGMII_TO_GPHY BIT(0) + +#define AN8801_BPBUS_REG_TXDLY_STEP 0x21c024 +#define RGMII_DELAY_STEP_MASK GENMASK(2, 0) +#define AIR_RGMII_DELAY_NOSTEP 0 +#define AIR_RGMII_DELAY_STEP_1 1 +#define AIR_RGMII_DELAY_STEP_2 2 +#define AIR_RGMII_DELAY_STEP_3 3 +#define AIR_RGMII_DELAY_STEP_4 4 +#define AIR_RGMII_DELAY_STEP_5 5 +#define AIR_RGMII_DELAY_STEP_6 6 +#define AIR_RGMII_DELAY_STEP_7 7 +#define RGMII_TXDELAY_FORCE_MODE BIT(24) + +#define AN8801_BPBUS_REG_RXDLY_STEP 0x21c02c +#define RGMII_RXDELAY_ALIGN BIT(4) +#define RGMII_RXDELAY_FORCE_MODE BIT(24) + +#define AN8801_BPBUS_REG_EFIFO_CTL(x) (0x270004 + (0x100 * (x))) /* 0..2 */ +#define AN8801_EFIFO_ALL_EN GENMASK(7, 0) +#define AN8801_EFIFO_RX_EN BIT(0) +#define AN8801_EFIFO_TX_EN BIT(1) +#define AN8801_EFIFO_RX_CLK_EN BIT(2) +#define AN8801_EFIFO_TX_CLK_EN BIT(3) +#define AN8801_EFIFO_RX_EEE_EN BIT(4) +#define AN8801_EFIFO_TX_EEE_EN BIT(5) +#define AN8801_EFIFO_RX_ODD_NIBBLE_EN BIT(6) +#define AN8801_EFIFO_TX_ODD_NIBBLE_EN BIT(7) + +#define AN8801_BPBUS_REG_HWRST_DE_GLITCH 0xc8 +#define AN8801_DE_GLITCH_EN BIT(2) +#define AN8801_11_CYCLE_XTAL_PERIOD_DE_GLITCH GENMASK(1, 0) + +#define LED_BCR 0x21 +#define LED_BCR_MODE_MASK GENMASK(1, 0) +#define LED_BCR_TIME_TEST BIT(2) +#define LED_BCR_CLK_EN BIT(3) +#define LED_BCR_EVT_ALL BIT(4) +#define LED_BCR_EXT_CTRL BIT(15) +#define LED_BCR_MODE_DISABLE 0 +#define LED_BCR_MODE_2LED 1 +#define LED_BCR_MODE_3LED_1 2 +#define LED_BCR_MODE_3LED_2 3 + +#define LED_ON_DUR 0x22 +#define LED_ON_DUR_MASK GENMASK(15, 0) + +#define LED_BLINK_DUR 0x23 +#define LED_BLINK_DUR_MASK GENMASK(15, 0) + +#define LED_ON_CTRL(i) (0x024 + ((i) * 2)) +#define LED_ON_EVT_MASK GENMASK(6, 0) +#define LED_ON_EVT_LINK_1000M BIT(0) +#define LED_ON_EVT_LINK_100M BIT(1) +#define LED_ON_EVT_LINK_10M BIT(2) +#define LED_ON_EVT_LINK_DN BIT(3) +#define LED_ON_EVT_FDX BIT(4) +#define LED_ON_EVT_HDX BIT(5) +#define LED_ON_EVT_FORCE BIT(6) +#define LED_ON_POL BIT(14) +#define LED_ON_EN BIT(15) + +#define LED_BLINK_CTRL(i) (0x025 + ((i) * 2)) +#define LED_BLINK_EVT_MASK GENMASK(9, 0) +#define LED_BLINK_EVT_1000M_TX BIT(0) +#define LED_BLINK_EVT_1000M_RX BIT(1) +#define LED_BLINK_EVT_100M_TX BIT(2) +#define LED_BLINK_EVT_100M_RX BIT(3) +#define LED_BLINK_EVT_10M_TX BIT(4) +#define LED_BLINK_EVT_10M_RX BIT(5) +#define LED_BLINK_EVT_FORCE BIT(9) + +#define UNIT_LED_BLINK_DURATION 780 +#define LED_BLINK_DURATION(f) (UNIT_LED_BLINK_DURATION << (f)) + +/* Link on(1G/100M/10M), no activity */ +#define AIR_LED0_ON \ + (LED_ON_EVT_LINK_1000M | LED_ON_EVT_LINK_100M | LED_ON_EVT_LINK_10M) +#define AIR_LED0_BLINK 0x0 +/* No link on, activity(1G/100M/10M TX/RX) */ +#define AIR_LED1_ON 0x0 +#define AIR_LED1_BLINK \ + (LED_BLINK_EVT_1000M_TX | LED_BLINK_EVT_1000M_RX | \ + LED_BLINK_EVT_100M_TX | LED_BLINK_EVT_100M_RX | \ + LED_BLINK_EVT_10M_TX | LED_BLINK_EVT_10M_RX) +/* Link on(100M/10M), activity(100M/10M TX/RX) */ +#define AIR_LED2_ON \ + (LED_ON_EVT_LINK_100M | LED_ON_EVT_LINK_10M) +#define AIR_LED2_BLINK \ + (LED_BLINK_EVT_100M_TX | LED_BLINK_EVT_100M_RX | \ + LED_BLINK_EVT_10M_TX | LED_BLINK_EVT_10M_RX) + +#define INVALID_DATA GENMASK(31, 0) + +#define AN8801_REG_PHY_INTERNAL0 0x600 +#define AN8801_REG_PHY_INTERNAL1 0x601 + +#define AN8801_LED_ENABLE 1 + +enum air_led_gpio_pin { + AIR_LED_GPIO1 = 1, + AIR_LED_GPIO2, + AIR_LED_GPIO3 +}; + +enum air_led { + AIR_LED0 = 0, + AIR_LED1, + AIR_LED2, + AIR_LED3 +}; + +enum air_led_blink_dut { + AIR_LED_BLINK_DUR_32M = 0, + AIR_LED_BLINK_DUR_64M, + AIR_LED_BLINK_DUR_128M, + AIR_LED_BLINK_DUR_256M, + AIR_LED_BLINK_DUR_512M, + AIR_LED_BLINK_DUR_1024M, + AIR_LED_BLINK_DUR_LAST +}; + +enum air_led_polarity { + AIR_ACTIVE_LOW = 0, + AIR_ACTIVE_HIGH, +}; + +enum air_led_mode { + AIR_LED_MODE_DISABLE = 0, + AIR_LED_MODE_USER_DEFINE, + AIR_LED_MODE_LAST +}; + +struct air_led_cfg { + u16 led_en; + u16 gpio; + u16 led_polarity; + u16 led_on_cfg; + u16 led_blk_cfg; +}; + +struct an8801r_priv { + struct air_led_cfg led_cfg[AN8801R_MAX_LED_SIZE]; + u32 led_blink_cfg; + u8 rxdelay_force; + u8 txdelay_force; + u16 rxdelay_step; + u8 rxdelay_align; + u16 txdelay_step; +}; + +#define phydev_cfg(phy) ((struct an8801r_priv *)(phy)->priv) + +/* + * GPIO1 <-> LED0, + * GPIO2 <-> LED1, + * GPIO3 <-> LED2, + */ +static const struct an8801r_priv an8801r_priv_defaults = { + .led_cfg = { + /* LED Enable, GPIO, LED Polarity, LED ON, LED Blink */ + {AN8801_LED_ENABLE, AIR_LED_GPIO1, AIR_ACTIVE_LOW, AIR_LED0_ON, AIR_LED0_BLINK}, + {AN8801_LED_ENABLE, AIR_LED_GPIO2, AIR_ACTIVE_HIGH, AIR_LED1_ON, AIR_LED1_BLINK}, + {AN8801_LED_ENABLE, AIR_LED_GPIO3, AIR_ACTIVE_HIGH, AIR_LED2_ON, AIR_LED2_BLINK}, + }, + .led_blink_cfg = AIR_LED_BLINK_DUR_64M, + .rxdelay_force = false, + .txdelay_force = false, + .rxdelay_step = AIR_RGMII_DELAY_NOSTEP, + .rxdelay_align = false, + .txdelay_step = AIR_RGMII_DELAY_NOSTEP, +}; + +static int an8801_buckpbus_reg_rmw(struct phy_device *phydev, + u32 addr, u32 mask, u32 set) +{ + return air_phy_buckpbus_reg_modify(phydev, + addr | AN8801_PBUS_ACCESS, + mask, set); +} + +static int an8801_buckpbus_reg_set_bits(struct phy_device *phydev, + u32 addr, u32 mask) +{ + return air_phy_buckpbus_reg_modify(phydev, + addr | AN8801_PBUS_ACCESS, + mask, mask); +} + +static int an8801_buckpbus_reg_clear_bits(struct phy_device *phydev, + u32 addr, u32 mask) +{ + return air_phy_buckpbus_reg_modify(phydev, + addr | AN8801_PBUS_ACCESS, + mask, 0); +} + +static int an8801_buckpbus_reg_write(struct phy_device *phydev, u32 addr, u32 data) +{ + return air_phy_buckpbus_reg_write(phydev, addr | AN8801_PBUS_ACCESS, data); +} + +static int an8801r_led_set_usr_def(struct phy_device *phydev, u8 entity, + u16 polar, u16 on_evt, u16 blk_evt) +{ + int ret; + + if (polar == AIR_ACTIVE_HIGH) + on_evt |= LED_ON_POL; + else + on_evt &= ~LED_ON_POL; + + on_evt |= LED_ON_EN; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(entity), on_evt); + if (ret) + return ret; + + return phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(entity), blk_evt); +} + +static int an8801r_led_set_blink(struct phy_device *phydev, u16 blink) +{ + int ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_DUR, + LED_BLINK_DURATION(blink)); + if (ret) + return ret; + + return phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_ON_DUR, + LED_BLINK_DURATION(blink) / 2); +} + +static int an8801r_led_set_mode(struct phy_device *phydev, u8 mode) +{ + int ret; + + ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_BCR); + if (ret < 0) + return ret; + + switch (mode) { + case AIR_LED_MODE_DISABLE: + ret &= ~LED_BCR_EXT_CTRL; + ret &= ~LED_BCR_MODE_MASK; + ret |= LED_BCR_MODE_DISABLE; + break; + case AIR_LED_MODE_USER_DEFINE: + ret |= LED_BCR_EXT_CTRL | LED_BCR_CLK_EN; + break; + } + return phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_BCR, ret); +} + +static int an8801r_led_set_state(struct phy_device *phydev, u8 entity, u8 state) +{ + int ret; + + ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(entity)); + if (ret < 0) + return ret; + + if (state) + ret |= LED_ON_EN; + else + ret &= ~LED_ON_EN; + + return phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(entity), ret); +} + +static int an8801r_led_init(struct phy_device *phydev) +{ + struct an8801r_priv *priv = phydev_cfg(phydev); + struct air_led_cfg *led_cfg = priv->led_cfg; + u16 led_blink_cfg = priv->led_blink_cfg; + int ret, led_id; + + ret = an8801r_led_set_blink(phydev, led_blink_cfg); + if (ret) + return ret; + + ret = an8801r_led_set_mode(phydev, AIR_LED_MODE_USER_DEFINE); + if (ret) { + dev_err(phydev->dev, "AN8801R: Fail to set LED mode, ret %d!\n", ret); + return ret; + } + + for (led_id = AIR_LED0; led_id < AN8801R_MAX_LED_SIZE; led_id++) { + ret = an8801r_led_set_state(phydev, led_id, led_cfg[led_id].led_en); + if (ret) { + dev_err(phydev->dev, "AN8801R: Fail to set LED%d state, ret %d!\n", + led_id, ret); + return ret; + } + + if (!led_cfg[led_id].led_en) + continue; + + ret = an8801_buckpbus_reg_set_bits(phydev, AN8801_BPBUS_REG_LED_GPIO, + BIT(led_cfg[led_id].gpio)); + if (ret) + return ret; + + ret = an8801_buckpbus_reg_set_bits(phydev, AN8801_BPBUS_REG_LED_ID_SEL, + LED_ID_GPIO_SEL(led_id, + led_cfg[led_id].gpio)); + if (ret) + return ret; + + ret = an8801_buckpbus_reg_clear_bits(phydev, AN8801_BPBUS_REG_GPIO_MODE, + BIT(led_cfg[led_id].gpio)); + if (ret) + return ret; + + ret = an8801r_led_set_usr_def(phydev, led_id, + led_cfg[led_id].led_polarity, + led_cfg[led_id].led_on_cfg, + led_cfg[led_id].led_blk_cfg); + if (ret) { + dev_err(phydev->dev, "AN8801R: Fail to set LED%d, ret %d!\n", + led_id, ret); + return ret; + } + } + return 0; +} + +static int an8801r_of_init(struct phy_device *phydev) +{ + struct an8801r_priv *priv = phydev_cfg(phydev); + ofnode node = phy_get_ofnode(phydev); + u32 val = 0; + int ret; + + if (!ofnode_valid(node)) + return -EINVAL; + + if (ofnode_has_property(node, "airoha,rxclk-delay")) { + ret = ofnode_read_u32(node, "airoha,rxclk-delay", &val); + if (ret) { + dev_err(phydev->dev, "airoha,rxclk-delay value is invalid.\n"); + return ret; + } + if (val > AIR_RGMII_DELAY_STEP_7) { + dev_err(phydev->dev, "airoha,rxclk-delay value %u out of range.\n", val); + return -EINVAL; + } + priv->rxdelay_force = true; + priv->rxdelay_step = val; + priv->rxdelay_align = ofnode_read_bool(node, + "airoha,rxclk-delay-align"); + } + + if (ofnode_has_property(node, "airoha,txclk-delay")) { + ret = ofnode_read_u32(node, "airoha,txclk-delay", &val); + if (ret) { + dev_err(phydev->dev, "airoha,txclk-delay value is invalid.\n"); + return ret; + } + if (val > AIR_RGMII_DELAY_STEP_7) { + dev_err(phydev->dev, "airoha,txclk-delay value %u out of range.\n", val); + return -EINVAL; + } + priv->txdelay_force = true; + priv->txdelay_step = val; + } + return 0; +} + +static int an8801r_rgmii_rxdelay(struct phy_device *phydev, u16 delay, u8 align) +{ + u32 reg_val = delay & RGMII_DELAY_STEP_MASK; + int ret; + + if (align) { + reg_val |= RGMII_RXDELAY_ALIGN; + debug("AN8801R: Rxdelay align\n"); + } + reg_val |= RGMII_RXDELAY_FORCE_MODE; + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_RXDLY_STEP, reg_val); + if (ret) + return ret; + + debug("AN8801R: Force rxdelay = %d(0x%x)\n", delay, reg_val); + return 0; +} + +static int an8801r_rgmii_txdelay(struct phy_device *phydev, u16 delay) +{ + u32 reg_val = delay & RGMII_DELAY_STEP_MASK; + int ret; + + reg_val |= RGMII_TXDELAY_FORCE_MODE; + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_TXDLY_STEP, reg_val); + if (ret) + return ret; + + debug("AN8801R: Force txdelay = %d(0x%x)\n", delay, reg_val); + return 0; +} + +static int an8801r_rgmii_delay_config(struct phy_device *phydev) +{ + struct an8801r_priv *priv = phydev_cfg(phydev); + int ret; + + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII_TXID: + return an8801r_rgmii_txdelay(phydev, AIR_RGMII_DELAY_STEP_4); + case PHY_INTERFACE_MODE_RGMII_RXID: + return an8801r_rgmii_rxdelay(phydev, AIR_RGMII_DELAY_NOSTEP, true); + case PHY_INTERFACE_MODE_RGMII_ID: + ret = an8801r_rgmii_txdelay(phydev, AIR_RGMII_DELAY_STEP_4); + if (ret) + return ret; + return an8801r_rgmii_rxdelay(phydev, AIR_RGMII_DELAY_NOSTEP, true); + case PHY_INTERFACE_MODE_RGMII: + default: + if (priv->rxdelay_force) { + ret = an8801r_rgmii_rxdelay(phydev, priv->rxdelay_step, + priv->rxdelay_align); + if (ret) + return ret; + } + if (priv->txdelay_force) + return an8801r_rgmii_txdelay(phydev, priv->txdelay_step); + return 0; + } +} + +static int an8801r_config_init(struct phy_device *phydev) +{ + int ret; + + ret = an8801r_of_init(phydev); + if (ret < 0) + return ret; + + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_HWRST_DE_GLITCH, + AN8801_DE_GLITCH_EN | + AN8801_11_CYCLE_XTAL_PERIOD_DE_GLITCH); + if (ret) + return ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL0, 0x1e); + if (ret) + return ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL1, 0x02); + if (ret) + return ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); + if (ret) + return ret; + + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_BYPASS_PTP, + AN8801_BYP_PTP_RGMII_TO_GPHY); + if (ret) + return ret; + + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(0), + AN8801_EFIFO_RX_EN | + AN8801_EFIFO_TX_EN | + AN8801_EFIFO_RX_CLK_EN | + AN8801_EFIFO_TX_CLK_EN | + AN8801_EFIFO_RX_EEE_EN | + AN8801_EFIFO_TX_EEE_EN); + if (ret) + return ret; + + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(1), + AN8801_EFIFO_ALL_EN); + if (ret) + return ret; + + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(2), + AN8801_EFIFO_ALL_EN); + if (ret) + return ret; + + ret = an8801r_rgmii_delay_config(phydev); + if (ret) + return ret; + + ret = an8801r_led_init(phydev); + if (ret) { + dev_err(phydev->dev, "AN8801R: LED initialize fail, ret %d!\n", ret); + return ret; + } + return 0; +} + +static int an8801r_phy_probe(struct phy_device *phydev) +{ + struct an8801r_priv *priv; + u32 phy_id; + int ret; + + ret = get_phy_id(phydev->bus, phydev->addr, MDIO_DEVAD_NONE, &phy_id); + if (ret) + return ret; + + if (phy_id != AN8801R_PHY_ID) { + dev_err(phydev->dev, + "AN8801R can't be detected (id=0x%08x).\n", phy_id); + return -ENODEV; + } + + priv = malloc(sizeof(*priv)); + if (!priv) + return -ENOMEM; + + *priv = an8801r_priv_defaults; + + phydev->priv = priv; + + return 0; +} + +static int an8801r_read_status(struct phy_device *phydev) +{ + u32 data; + + if (!phydev->link) + return 0; + + debug("AN8801R: SPEED %d\n", phydev->speed); + data = phydev->speed == SPEED_1000 ? AN8801_BPBUS_LINK_MODE_1000 : 0; + + return an8801_buckpbus_reg_rmw(phydev, AN8801_BPBUS_REG_LINK_MODE, + AN8801_BPBUS_LINK_MODE_1000, data); +} + +static int an8801r_startup(struct phy_device *phydev) +{ + int ret; + + ret = genphy_startup(phydev); + if (ret) + return ret; + + return an8801r_read_status(phydev); +} + +U_BOOT_PHY_DRIVER(an8801r) = { + .name = "Airoha AN8801R", + .uid = AN8801R_PHY_ID, + .mask = 0x0ffffff0, + .features = PHY_GBIT_FEATURES, + .probe = &an8801r_phy_probe, + .config = &an8801r_config_init, + .read_page = &air_phy_read_page, + .write_page = &air_phy_write_page, + .startup = &an8801r_startup, + .shutdown = &genphy_shutdown, +}; -- cgit v1.3.1 From 44f7d5945b324ba67dc0162a6eabc13f8f8d73ea Mon Sep 17 00:00:00 2001 From: Julien Stephan Date: Wed, 29 Apr 2026 15:59:00 +0200 Subject: net: dwc_eth_qos: Add mediatek support Synopsys DWC Ethernet QOS device support for MediaTek SoCs. in particular this initial commit adds support for Genio 520/720 and Genio 510/700 EVKs Signed-off-by: fanyi zhang Signed-off-by: Julien Stephan Reviewed-by: Macpaul Lin Link: https://patch.msgid.link/20260429-add-ethernet-support-for-genio-520-720-v4-7-be54e17239b7@baylibre.com Signed-off-by: David Lechner --- MAINTAINERS | 1 + drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 6 + drivers/net/dwc_eth_qos.h | 2 + drivers/net/dwc_eth_qos_mtk.c | 442 ++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 459 insertions(+) create mode 100644 drivers/net/dwc_eth_qos_mtk.c (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index 474b2af11bd..6d73ad26b02 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -436,6 +436,7 @@ F: drivers/clk/mediatek/ F: drivers/cpu/mtk_cpu.c F: drivers/i2c/mtk_i2c.c F: drivers/mmc/mtk-sd.c +F: drivers/net/dwc_eth_qos_mtk.c F: drivers/net/mtk_eth/ F: drivers/net/phy/mediatek/ F: drivers/phy/phy-mtk-* diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 4fc7552d19d..5172b2bae8e 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -246,6 +246,13 @@ config DWC_ETH_QOS_INTEL The Synopsys Designware Ethernet QOS IP block with the specific configuration used in the Intel Elkhart-Lake soc. +config DWC_ETH_QOS_MTK + bool "Synopsys DWC Ethernet QOS device support for MediaTek SoCs" + depends on DWC_ETH_QOS && ARCH_MEDIATEK + help + The Synopsys Designware Ethernet QOS IP block with the specific + configuration used in MediaTek SoCs. + config DWC_ETH_QOS_QCOM bool "Synopsys DWC Ethernet QOS device support for Qcom SoCs" depends on DWC_ETH_QOS diff --git a/drivers/net/Makefile b/drivers/net/Makefile index c485068e5d2..761f7f0f451 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_DWC_ETH_QOS_ADI) += dwc_eth_qos_adi.o obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o obj-$(CONFIG_DWC_ETH_QOS_INTEL) += dwc_eth_qos_intel.o +obj-$(CONFIG_DWC_ETH_QOS_MTK) += dwc_eth_qos_mtk.o obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 0f31d646845..b7e6299c307 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1658,6 +1658,12 @@ static const struct udevice_id eqos_ids[] = { .compatible = "adi,sc59x-dwmac-eqos", .data = (ulong)&eqos_adi_config }, +#endif +#if IS_ENABLED(CONFIG_DWC_ETH_QOS_MTK) + { + .compatible = "mediatek,mt8189-gmac", + .data = (ulong)&eqos_mtk_config + }, #endif { } }; diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index ba16f1a37cb..978b848b46e 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -97,6 +97,7 @@ struct eqos_mac_regs { #define EQOS_MAC_MDIO_ADDRESS_PA_MASK GENMASK(25, 21) #define EQOS_MAC_MDIO_ADDRESS_RDA_MASK GENMASK(20, 16) #define EQOS_MAC_MDIO_ADDRESS_CR_MASK GENMASK(11, 8) +#define EQOS_MAC_MDIO_ADDRESS_CR_60_100 0 #define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 #define EQOS_MAC_MDIO_ADDRESS_CR_150_250 4 @@ -316,3 +317,4 @@ extern struct eqos_config eqos_stm32mp15_config; extern struct eqos_config eqos_stm32mp25_config; extern struct eqos_config eqos_jh7110_config; extern struct eqos_config eqos_adi_config; +extern struct eqos_config eqos_mtk_config; diff --git a/drivers/net/dwc_eth_qos_mtk.c b/drivers/net/dwc_eth_qos_mtk.c new file mode 100644 index 00000000000..43e1085dfe5 --- /dev/null +++ b/drivers/net/dwc_eth_qos_mtk.c @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "dwc_eth_qos.h" + +/* + * Peri Configuration register is SoC specific, + * so add a SoC specific prefix. + */ +#define MT8189_PERI_ETH_CTRL0 0x270 +#define MT8189_PERI_ETH_CTRL1 0x274 +#define MT8189_PERI_ETH_CTRL2 0x278 + +#define EQOS_MTK_RMII_CLK_SRC_INTERNAL BIT(28) +#define EQOS_MTK_RMII_CLK_SRC_RXC BIT(27) +#define EQOS_MTK_ETH_INTF_SEL GENMASK(26, 24) +#define EQOS_MTK_PHY_INTF_MII 0 +#define EQOS_MTK_PHY_INTF_RGMII 1 +#define EQOS_MTK_PHY_INTF_RMII 4 +#define EQOS_MTK_RGMII_TXC_PHASE_CTRL BIT(22) +#define EQOS_MTK_EXT_PHY_MODE BIT(21) +#define EQOS_MTK_TXC_OUT_OP BIT(20) +#define EQOS_MTK_DLY_GTXC_INV BIT(12) +#define EQOS_MTK_DLY_GTXC_STAGE_FINE GENMASK(11, 6) +#define EQOS_MTK_DLY_GTXC_ENABLE BIT(5) +#define EQOS_MTK_DLY_GTXC_STAGES GENMASK(4, 0) + +#define EQOS_MTK_DLY_RXC_INV BIT(25) +#define EQOS_MTK_DLY_RXC_ENABLE BIT(18) +#define EQOS_MTK_DLY_RXC_STAGES GENMASK(17, 13) +#define EQOS_MTK_DLY_TXC_INV BIT(12) +#define EQOS_MTK_DLY_TXC_ENABLE BIT(5) +#define EQOS_MTK_DLY_TXC_STAGES GENMASK(4, 0) + +#define EQOS_MTK_DLY_RMII_RXC_INV BIT(25) +#define EQOS_MTK_DLY_RMII_RXC_ENABLE BIT(18) +#define EQOS_MTK_DLY_RMII_RXC_STAGES GENMASK(17, 13) +#define EQOS_MTK_DLY_RMII_TXC_INV BIT(12) +#define EQOS_MTK_DLY_RMII_TXC_ENABLE BIT(5) +#define EQOS_MTK_DLY_RMII_TXC_STAGES GENMASK(4, 0) + +#define DELAY_MAX_PS 9800 +#define DELAY_PS_PER_STAGE 290 + +struct eqos_mtk_priv { + struct regmap *peri_regmap; + bool rmii_clk_from_mac; + bool rmii_rxc; + u32 tx_delay_stage; + u32 rx_delay_stage; + bool tx_inv; + bool rx_inv; +}; + +static int mtk_clk_init(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + ret = clk_get_by_name(dev, "mac_main", &eqos->clk_tx); + if (ret) { + dev_err(dev, "clk_get_by_name(mac_main) failed: %d", ret); + return ret; + } + + ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref); + if (ret) { + dev_err(dev, "clk_get_by_name(ptp_ref) failed: %d", ret); + return ret; + } + + return 0; +} + +static int mtk_set_delay(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; + u32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0; + + switch (pdata->phy_interface) { + case PHY_INTERFACE_MODE_MII: + delay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_ENABLE, + !!mtk_pdata->tx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_STAGES, mtk_pdata->tx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_INV, mtk_pdata->tx_inv); + + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_ENABLE, + !!mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_STAGES, mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_INV, mtk_pdata->rx_inv); + break; + case PHY_INTERFACE_MODE_RMII: + if (mtk_pdata->rmii_clk_from_mac) { + /* case 1: mac provides the rmii reference clock, + * and the clock output to TXC pin. + * The egress timing can be adjusted by RMII_TXC delay macro circuit. + * The ingress timing can be adjusted by RMII_RXC delay macro circuit. + */ + rmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_TXC_ENABLE, + !!mtk_pdata->tx_delay_stage); + rmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_TXC_STAGES, + mtk_pdata->tx_delay_stage); + rmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_TXC_INV, + mtk_pdata->tx_inv); + + rmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_RXC_ENABLE, + !!mtk_pdata->rx_delay_stage); + rmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_RXC_STAGES, + mtk_pdata->rx_delay_stage); + rmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_RXC_INV, + mtk_pdata->rx_inv); + } else { + /* case 2: the rmii reference clock is from external phy, + * and the property "rmii_rxc" indicates which pin(TXC/RXC) + * the reference clk is connected to. The reference clock is a + * received signal, so rx_delay_stage/rx_inv are used to indicate + * the reference clock timing adjustment + */ + if (mtk_pdata->rmii_rxc) { + /* the rmii reference clock from outside is connected + * to RXC pin, the reference clock will be adjusted + * by RXC delay macro circuit. + */ + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_ENABLE, + !!mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_STAGES, + mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_INV, + mtk_pdata->rx_inv); + } else { + /* the rmii reference clock from outside is connected + * to TXC pin, the reference clock will be adjusted + * by TXC delay macro circuit. + */ + delay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_ENABLE, + !!mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_STAGES, + mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_INV, + mtk_pdata->rx_inv); + } + } + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + gtxc_delay_val |= FIELD_PREP(EQOS_MTK_DLY_GTXC_ENABLE, + !!mtk_pdata->tx_delay_stage); + gtxc_delay_val |= FIELD_PREP(EQOS_MTK_DLY_GTXC_STAGES, + mtk_pdata->tx_delay_stage); + gtxc_delay_val |= FIELD_PREP(EQOS_MTK_DLY_GTXC_INV, mtk_pdata->tx_inv); + gtxc_delay_val |= EQOS_MTK_DLY_GTXC_STAGE_FINE; + + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_ENABLE, + !!mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_STAGES, mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_INV, mtk_pdata->rx_inv); + + break; + default: + dev_err(dev, "phy interface not supported\n"); + return -EINVAL; + } + + regmap_update_bits(mtk_pdata->peri_regmap, + MT8189_PERI_ETH_CTRL0, + EQOS_MTK_RGMII_TXC_PHASE_CTRL | + EQOS_MTK_DLY_GTXC_ENABLE | + EQOS_MTK_DLY_GTXC_INV | + EQOS_MTK_DLY_GTXC_STAGE_FINE | + EQOS_MTK_DLY_GTXC_STAGES, + gtxc_delay_val); + regmap_write(mtk_pdata->peri_regmap, MT8189_PERI_ETH_CTRL1, delay_val); + regmap_write(mtk_pdata->peri_regmap, MT8189_PERI_ETH_CTRL2, rmii_delay_val); + + return 0; +} + +static int mtk_set_interface(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; + int rmii_clk_from_mac = mtk_pdata->rmii_clk_from_mac ? EQOS_MTK_RMII_CLK_SRC_INTERNAL : 0; + int rmii_rxc = mtk_pdata->rmii_rxc ? EQOS_MTK_RMII_CLK_SRC_RXC : 0; + u32 intf_val = 0; + + /* select phy interface in top control domain */ + switch (pdata->phy_interface) { + case PHY_INTERFACE_MODE_MII: + intf_val |= FIELD_PREP(EQOS_MTK_ETH_INTF_SEL, EQOS_MTK_PHY_INTF_MII); + break; + case PHY_INTERFACE_MODE_RMII: + intf_val |= (rmii_rxc | rmii_clk_from_mac); + intf_val |= FIELD_PREP(EQOS_MTK_ETH_INTF_SEL, EQOS_MTK_PHY_INTF_RMII); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + intf_val |= FIELD_PREP(EQOS_MTK_ETH_INTF_SEL, EQOS_MTK_PHY_INTF_RGMII); + break; + default: + dev_err(dev, "phy interface not supported\n"); + return -EINVAL; + } + + /* only support external PHY */ + intf_val |= EQOS_MTK_EXT_PHY_MODE; + + intf_val |= EQOS_MTK_TXC_OUT_OP; + + regmap_write(mtk_pdata->peri_regmap, MT8189_PERI_ETH_CTRL0, intf_val); + + return 0; +} + +static int mtk_config_dt(struct udevice *dev) +{ struct eth_pdata *pdata = dev_get_plat(dev); + struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; + struct ofnode_phandle_args args; + u32 tx_delay_ps = 0, rx_delay_ps = 0; + int ret; + + if (!dev_read_u32(dev, "mediatek,tx-delay-ps", &tx_delay_ps)) { + if (tx_delay_ps > DELAY_MAX_PS) { + dev_err(dev, "Invalid TX clock delay: %dps\n", tx_delay_ps); + return -EINVAL; + } + } + + if (!dev_read_u32(dev, "mediatek,rx-delay-ps", &rx_delay_ps)) { + if (rx_delay_ps > DELAY_MAX_PS) { + dev_err(dev, "Invalid RX clock delay: %dps\n", rx_delay_ps); + return -EINVAL; + } + } + + mtk_pdata->tx_delay_stage = tx_delay_ps / DELAY_PS_PER_STAGE; + mtk_pdata->rx_delay_stage = rx_delay_ps / DELAY_PS_PER_STAGE; + + mtk_pdata->tx_inv = dev_read_bool(dev, "mediatek,txc-inverse"); + mtk_pdata->rx_inv = dev_read_bool(dev, "mediatek,rxc-inverse"); + mtk_pdata->rmii_clk_from_mac = dev_read_bool(dev, "mediatek,rmii-clk-from-mac"); + mtk_pdata->rmii_rxc = dev_read_bool(dev, "mediatek,rmii-rxc"); + + ret = dev_read_phandle_with_args(dev, "mediatek,pericfg", NULL, 0, 0, &args); + if (ret) { + dev_err(dev, "Failed to get mediatek,pericfg property: %d\n", ret); + return ret; + } + + mtk_pdata->peri_regmap = syscon_node_to_regmap(args.node); + if (IS_ERR(mtk_pdata->peri_regmap)) { + dev_err(dev, "fail to get regmap: %d\n", (int)PTR_ERR(mtk_pdata->peri_regmap)); + return PTR_ERR(mtk_pdata->peri_regmap); + } + + return 0; +} + +static int eqos_probe_resources_mtk(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct eqos_mtk_priv *mtk_pdata; + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + ret = eqos_get_base_addr_dt(dev); + if (ret) { + dev_err(dev, "eqos_get_base_addr_dt failed: %d\n", ret); + return ret; + } + + mtk_pdata = calloc(1, sizeof(struct eqos_mtk_priv)); + if (!mtk_pdata) + return -ENOMEM; + + pdata->priv_pdata = mtk_pdata; + + ret = mtk_config_dt(dev); + if (ret) { + dev_err(dev, "mtk config dt failed: %d\n", ret); + goto err; + } + + ret = mtk_clk_init(dev); + if (ret) + goto err; + + pdata->phy_interface = eqos->config->interface(dev); + if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) { + dev_err(dev, "Invalid PHY interface\n"); + ret = -EINVAL; + goto err; + } + + ret = mtk_set_interface(dev); + if (ret) + goto err; + + ret = mtk_set_delay(dev); + if (ret) + goto err; + + debug("%s: OK\n", __func__); + return 0; +err: + free(mtk_pdata); + return ret; +} + +static int eqos_remove_resources_mtk(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; + + debug("%s(dev=%p):\n", __func__, dev); + + free(mtk_pdata); + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_stop_clks_mtk(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clk_disable(&eqos->clk_ptp_ref); + clk_disable(&eqos->clk_tx); + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_start_clks_mtk(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + ret = clk_enable(&eqos->clk_tx); + if (ret < 0) { + dev_err(dev, "clk_enable(mac_main) failed: %d", ret); + goto err; + } + + ret = clk_enable(&eqos->clk_ptp_ref); + if (ret < 0) { + dev_err(dev, "clk_enable(ptp_ref) failed: %d", ret); + goto err_disable_clk_mac_main; + } + + debug("%s: OK\n", __func__); + return 0; + +err_disable_clk_mac_main: + clk_disable(&eqos->clk_tx); +err: + debug("%s: FAILED: %d\n", __func__, ret); + return ret; +} + +static int eqos_fix_mac_speed_mtk(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; + + debug("%s(dev=%p):\n", __func__, dev); + + switch (pdata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + if (eqos->phy->speed == SPEED_1000) + regmap_update_bits(mtk_pdata->peri_regmap, + MT8189_PERI_ETH_CTRL0, + EQOS_MTK_RGMII_TXC_PHASE_CTRL | + EQOS_MTK_DLY_GTXC_ENABLE | + EQOS_MTK_DLY_GTXC_INV | + EQOS_MTK_DLY_GTXC_STAGE_FINE | + EQOS_MTK_DLY_GTXC_STAGES, + EQOS_MTK_RGMII_TXC_PHASE_CTRL); + else + mtk_set_delay(dev); + break; + default: + debug("%s: dev=%p no need to adjust mac delay\n", __func__, dev); + break; + } + + debug("%s: OK\n", __func__); + return 0; +} + +static struct eqos_ops eqos_mtk_ops = { + .eqos_inval_desc = eqos_inval_desc_generic, + .eqos_flush_desc = eqos_flush_desc_generic, + .eqos_inval_buffer = eqos_inval_buffer_generic, + .eqos_flush_buffer = eqos_flush_buffer_generic, + .eqos_probe_resources = eqos_probe_resources_mtk, + .eqos_remove_resources = eqos_remove_resources_mtk, + .eqos_stop_resets = eqos_null_ops, + .eqos_start_resets = eqos_null_ops, + .eqos_stop_clks = eqos_stop_clks_mtk, + .eqos_start_clks = eqos_start_clks_mtk, + .eqos_calibrate_pads = eqos_null_ops, + .eqos_disable_calibration = eqos_null_ops, + .eqos_set_tx_clk_speed = eqos_fix_mac_speed_mtk, + .eqos_get_enetaddr = eqos_null_ops, +}; + +struct eqos_config eqos_mtk_config = { + .reg_access_always_ok = false, + .mdio_wait = 10000, + .swr_wait = 10, + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_60_100, + .axi_bus_width = EQOS_AXI_WIDTH_64, + .interface = dev_read_phy_mode, + .ops = &eqos_mtk_ops +}; -- cgit v1.3.1 From 2258b6419a9fb94a62c566d7804fe4ff551fae7a Mon Sep 17 00:00:00 2001 From: David Lechner Date: Wed, 6 May 2026 18:05:31 -0500 Subject: pinctrl: mediatek: use scnprintf() instead of snprintf() Replace snprintf() with scnprintf() in the MediaTek pinctrl driver. snprintf() returns the number of characters that _would_ have been written if the buffer were large enough, while scnprintf() returns the number of characters actually written to the buffer. Since we use the return value to advance the buffer pointer, we need to use scnprintf() to have the correct pointer arithmetic. Fixes: 76da7482cf39 ("pinctrl: mediatek: print bias info along with pinmux") Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260506-mtk-pinctrl-fix-scnprintf-v1-1-56b99d5809db@baylibre.com Signed-off-by: David Lechner --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index cfffbaeef84..01f67f09407 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -251,7 +251,7 @@ static int mtk_pinconf_get(struct udevice *dev, u32 pin, char *buf, size_t size) if (mtk_get_pin_io_type(dev, pin, &io_type)) return 0; - pos = snprintf(buf, size, " (%s)", io_type.name); + pos = scnprintf(buf, size, " (%s)", io_type.name); if (pos >= size) return pos; @@ -306,7 +306,7 @@ static int mtk_get_pin_muxing(struct udevice *dev, unsigned int selector, if (err) return err; - pos = snprintf(buf, size, "Aux Func.%d", val); + pos = scnprintf(buf, size, "Aux Func.%d", val); if (pos >= size) return 0; @@ -721,7 +721,7 @@ int mtk_pinconf_get_pu_pd(struct udevice *dev, u32 pin, char *buf, size_t size) if (err) return err; - return snprintf(buf, size, " PU:%d PD:%d", pu, pd); + return scnprintf(buf, size, " PU:%d PD:%d", pu, pd); } int mtk_pinconf_get_pupd_r1_r0(struct udevice *dev, u32 pin, char *buf, size_t size) @@ -740,7 +740,7 @@ int mtk_pinconf_get_pupd_r1_r0(struct udevice *dev, u32 pin, char *buf, size_t s if (err) return err; - return snprintf(buf, size, " PUPD:%d R1:%d R0:%d", pupd, r1, r0); + return scnprintf(buf, size, " PUPD:%d R1:%d R0:%d", pupd, r1, r0); } int mtk_pinconf_get_pu_pd_rsel(struct udevice *dev, u32 pin, char *buf, size_t size) @@ -755,7 +755,7 @@ int mtk_pinconf_get_pu_pd_rsel(struct udevice *dev, u32 pin, char *buf, size_t s if (err) return err; - return pos + snprintf(buf + pos, size - pos, " RSEL:%d", rsel); + return pos + scnprintf(buf + pos, size - pos, " RSEL:%d", rsel); } #endif -- cgit v1.3.1 From 6c636eabbde7f7915fe37c84395b23c61c66ce64 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Tue, 26 May 2026 01:41:40 +0000 Subject: treewide: prefer __func__ over __FUNCTION__ and __PRETTY_FUNCTION__ __FUNCTION__ and __PRETTY_FUNCTION__ are gcc extensions that predate the C99 __func__ identifier. scripts/checkpatch.pl emits a warning for any new use of __FUNCTION__ and recommends __func__ instead. In C (unlike C++) __PRETTY_FUNCTION__ is identical to __func__ because C function names do not carry signature information, so the distinction has no behavioural effect here. The majority of the tree already uses __func__, but a handful of older files in arch/, board/, boot/, drivers/, examples/ and include/ still carry the gcc spellings (55 occurrences of __FUNCTION__ across 19 files plus one __PRETTY_FUNCTION__ in drivers/usb/musb-new/omap2430.c). Convert them all to the C99 form so the tree is consistent and new patches in these areas do not have to follow an outdated local style. Ten "Unnecessary ftrace-like logging - prefer using ftrace" warnings remain on the printf("%s\n", __func__) and dbg("%s\n", __func__) function-entry traces in drivers/net/rtl8169.c (behind DEBUG_RTL8169* preprocessor guards) and drivers/usb/host/ohci-hcd.c. checkpatch matches the literal "%s\n", __func__ shape regardless of the wrapper, so silencing those warnings would require changing the debug message text or removing the traces entirely. Signed-off-by: Aristo Chen Reviewed-by: Tom Rini --- arch/arm/mach-kirkwood/cpu.c | 10 +++++----- arch/mips/include/asm/system.h | 4 ++-- arch/powerpc/cpu/mpc85xx/liodn.c | 2 +- board/Marvell/guruplug/guruplug.c | 2 +- board/socrates/nand.c | 2 +- boot/fdt_support.c | 14 +++++++------- drivers/ddr/fsl/main.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen2.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 2 +- drivers/fpga/spartan2.c | 12 ++++++------ drivers/fpga/spartan3.c | 12 ++++++------ drivers/fpga/xilinx.c | 12 ++++++------ drivers/net/mcfmii.c | 2 +- drivers/net/rtl8169.c | 18 +++++++++--------- drivers/rtc/m41t62.c | 4 ++-- drivers/usb/host/ohci-hcd.c | 2 +- drivers/usb/musb-new/omap2430.c | 2 +- examples/standalone/sched.c | 2 +- include/usbdevice.h | 6 +++--- 20 files changed, 57 insertions(+), 57 deletions(-) (limited to 'drivers') diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index a432abe615d..af59d63811c 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -99,16 +99,16 @@ static void kw_sysrst_action(void) if (!s) { debug("Error.. %s failed, check sysrstcmd\n", - __FUNCTION__); + __func__); return; } - debug("Starting %s process...\n", __FUNCTION__); + debug("Starting %s process...\n", __func__); ret = run_command(s, 0); if (ret != 0) - debug("Error.. %s failed\n", __FUNCTION__); + debug("Error.. %s failed\n", __func__); else - debug("%s process finished\n", __FUNCTION__); + debug("%s process finished\n", __func__); } static void kw_sysrst_check(void) @@ -152,7 +152,7 @@ int print_cpuinfo(void) u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) { - printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid); + printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __func__, devid); return -1; } diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index 00699c4c11a..1156e299433 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -259,9 +259,9 @@ extern void __die_if_kernel(const char *, struct pt_regs *, const char *where, unsigned long line); #define die(msg, regs) \ - __die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) + __die(msg, regs, __FILE__ ":" __func__, __LINE__) #define die_if_kernel(msg, regs) \ - __die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) + __die_if_kernel(msg, regs, __FILE__ ":" __func__, __LINE__) static inline void execution_hazard_barrier(void) { diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index af6731cbb3a..ddf0ac99cf6 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -110,7 +110,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, break; #endif default: - printf("Error: Invalid device type to %s\n", __FUNCTION__); + printf("Error: Invalid device type to %s\n", __func__); return; } diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index 7c3cea22b93..78a6d1094b5 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -111,7 +111,7 @@ void mv_phy_88e1121_init(char *name) /* command to read PHY dev address */ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { printf("Err..%s could not read PHY dev address\n", - __FUNCTION__); + __func__); return; } diff --git a/board/socrates/nand.c b/board/socrates/nand.c index b8e6e2cd76e..fc0c04efdd1 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -135,7 +135,7 @@ static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ct break; default: - printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl); + printf("%s: unknown ctrl %#x\n", __func__, ctrl); } if (ctrl & NAND_NCE) diff --git a/boot/fdt_support.c b/boot/fdt_support.c index 1c215e548db..c4d3cc043c5 100644 --- a/boot/fdt_support.c +++ b/boot/fdt_support.c @@ -545,13 +545,13 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) if (banks > MEMORY_BANKS_MAX) { printf("%s: num banks %d exceeds hardcoded limit %d." " Recompile with higher MEMORY_BANKS_MAX?\n", - __FUNCTION__, banks, MEMORY_BANKS_MAX); + __func__, banks, MEMORY_BANKS_MAX); return -1; } err = fdt_check_header(blob); if (err < 0) { - printf("%s: %s\n", __FUNCTION__, fdt_strerror(err)); + printf("%s: %s\n", __func__, fdt_strerror(err)); return err; } @@ -1497,7 +1497,7 @@ static u64 __of_translate_address(const void *blob, int node_offset, /* Cound address cells & copy address locally */ bus->count_cells(blob, parent, &na, &ns); if (!OF_CHECK_COUNTS(na, ns)) { - printf("%s: Bad cell count for %s\n", __FUNCTION__, + printf("%s: Bad cell count for %s\n", __func__, fdt_get_name(blob, node_offset, NULL)); goto bail; } @@ -1524,8 +1524,8 @@ static u64 __of_translate_address(const void *blob, int node_offset, pbus = of_match_bus(blob, parent); pbus->count_cells(blob, parent, &pna, &pns); if (!OF_CHECK_COUNTS(pna, pns)) { - printf("%s: Bad cell count for %s\n", __FUNCTION__, - fdt_get_name(blob, node_offset, NULL)); + printf("%s: Bad cell count for %s\n", __func__, + fdt_get_name(blob, node_offset, NULL)); break; } @@ -1612,7 +1612,7 @@ int fdt_get_dma_range(const void *blob, int node, phys_addr_t *cpu, bus_node = of_match_bus(blob, node); bus_node->count_cells(blob, node, &na, &ns); if (!OF_CHECK_COUNTS(na, ns)) { - printf("%s: Bad cell count for %s\n", __FUNCTION__, + printf("%s: Bad cell count for %s\n", __func__, fdt_get_name(blob, node, NULL)); return -EINVAL; goto out; @@ -1621,7 +1621,7 @@ int fdt_get_dma_range(const void *blob, int node, phys_addr_t *cpu, bus_node = of_match_bus(blob, parent); bus_node->count_cells(blob, parent, &pna, &pns); if (!OF_CHECK_COUNTS(pna, pns)) { - printf("%s: Bad cell count for %s\n", __FUNCTION__, + printf("%s: Bad cell count for %s\n", __func__, fdt_get_name(blob, parent, NULL)); return -EINVAL; goto out; diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index d59e94779ff..2b879c63b5f 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -221,7 +221,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, unsigned int i2c_address = 0; if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); return; } diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index a8520754006..e43dc869fc5 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -21,7 +21,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR; if (ctrl_num != 0) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); return; } diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c index 00b4b376dd4..3a8ad6cc86b 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -26,7 +26,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #endif if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); return; } diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index b0a61fa2b41..ee9811481ab 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -71,7 +71,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, break; #endif default: - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); return; } diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 792e4033428..e3715bf2b24 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -52,7 +52,7 @@ static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize, default: printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + __func__, desc->iface); } return ret_val; @@ -75,7 +75,7 @@ static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) default: printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + __func__, desc->iface); } return ret_val; @@ -234,7 +234,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -279,7 +279,7 @@ static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) /* XXX - checksum the data? */ } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -423,7 +423,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -434,7 +434,7 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ printf ("%s: Slave Serial Dumping is unavailable\n", - __FUNCTION__); + __func__); return FPGA_FAIL; } diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 98405589134..6221041e092 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -57,7 +57,7 @@ static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize, default: printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + __func__, desc->iface); } return ret_val; @@ -80,7 +80,7 @@ static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) default: printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + __func__, desc->iface); } return ret_val; @@ -241,7 +241,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -286,7 +286,7 @@ static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) /* XXX - checksum the data? */ } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -442,7 +442,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -453,7 +453,7 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ printf ("%s: Slave Serial Dumping is unavailable\n", - __FUNCTION__); + __func__); return FPGA_FAIL; } diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 44d7ad6bd54..b6966c7d2cb 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -149,8 +149,8 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype, int flags) { - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); + if (!xilinx_validate(desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); return FPGA_FAIL; } @@ -200,8 +200,8 @@ int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize, int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); + if (!xilinx_validate(desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); return FPGA_FAIL; } @@ -217,7 +217,7 @@ int xilinx_info(xilinx_desc *desc) { int ret_val = FPGA_FAIL; - if (xilinx_validate (desc, (char *)__FUNCTION__)) { + if (xilinx_validate(desc, (char *)__func__)) { printf ("Family: \t"); switch (desc->family) { case xilinx_spartan2: @@ -293,7 +293,7 @@ int xilinx_info(xilinx_desc *desc) ret_val = FPGA_SUCCESS; } else { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); + printf("%s: Invalid device descriptor\n", __func__); } return ret_val; diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 9bf887035d7..79ad6348de8 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -112,7 +112,7 @@ uint mii_send(uint mii_cmd) ep->eir = FEC_EIR_MII; /* clear MII complete */ #ifdef ET_DEBUG printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); + __FILE__, __LINE__, __func__, mii_cmd, mii_reply); #endif return (mii_reply & 0xffff); /* data read from phy */ diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 5b093623619..e203faed26b 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -404,7 +404,7 @@ static int rtl8169_init_board(unsigned long dev_iobase, const char *name) u32 tmp; #ifdef DEBUG_RTL8169 - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = dev_iobase; @@ -534,7 +534,7 @@ static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase, int length = 0; #ifdef DEBUG_RTL8169_RX - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = dev_iobase; @@ -608,7 +608,7 @@ static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase, #ifdef DEBUG_RTL8169_TX int stime = currticks(); - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); printf("sending %d bytes\n", len); #endif @@ -679,7 +679,7 @@ static void rtl8169_set_rx_mode(void) u32 tmp = 0; #ifdef DEBUG_RTL8169 - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif /* IFF_ALLMULTI */ @@ -701,7 +701,7 @@ static void rtl8169_hw_start(struct udevice *dev) #ifdef DEBUG_RTL8169 int stime = currticks(); - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif #if 0 @@ -771,7 +771,7 @@ static void rtl8169_init_ring(struct udevice *dev) #ifdef DEBUG_RTL8169 int stime = currticks(); - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif tpc->cur_rx = 0; @@ -810,7 +810,7 @@ static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr, #ifdef DEBUG_RTL8169 int stime = currticks(); - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = dev_iobase; @@ -851,7 +851,7 @@ static void rtl_halt_common(struct udevice *dev) int i; #ifdef DEBUG_RTL8169 - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = priv->iobase; @@ -906,7 +906,7 @@ static int rtl_init(unsigned long dev_ioaddr, const char *name, int option = -1, Cap10_100 = 0, Cap1000 = 0; #ifdef DEBUG_RTL8169 - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = dev_ioaddr; diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 7bfea9e0b31..b3734baf63e 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -66,7 +66,7 @@ static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf) { debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", - __FUNCTION__, + __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); @@ -83,7 +83,7 @@ static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf) debug("%s: tm is secs=%d, mins=%d, hours=%d, " "mday=%d, mon=%d, year=%d, wday=%d\n", - __FUNCTION__, + __func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); } diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 1d6711ccec4..3fcf9d53d59 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1750,7 +1750,7 @@ static int hc_reset(ohci_t *ohci) int timeout = 30; int smm_timeout = 50; /* 0,5 sec */ - dbg("%s\n", __FUNCTION__); + dbg("%s\n", __func__); #ifdef CONFIG_PCI_EHCI_DEVNO /* diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index 7fd6639013a..c8c6bf0c84f 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -100,7 +100,7 @@ static int omap2430_musb_enable(struct musb *musb) #ifdef CONFIG_TWL4030_USB if (twl4030_usb_ulpi_init()) { serial_printf("ERROR: %s Could not initialize PHY\n", - __PRETTY_FUNCTION__); + __func__); } #endif return 0; diff --git a/examples/standalone/sched.c b/examples/standalone/sched.c index 64518c6890f..969628350d5 100644 --- a/examples/standalone/sched.c +++ b/examples/standalone/sched.c @@ -58,7 +58,7 @@ static uchar dbg = 0; #define PDEBUG(fmt, args...) { \ if(dbg != 0) { \ - printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__);\ + printf("[%s %d %s]: ", __FILE__, __LINE__, __func__);\ printf(fmt, ##args); \ printf("\n"); \ } \ diff --git a/include/usbdevice.h b/include/usbdevice.h index d173c1c4e37..76fda5ff90b 100644 --- a/include/usbdevice.h +++ b/include/usbdevice.h @@ -22,19 +22,19 @@ #define MAX_URBS_QUEUED 5 #if 1 -#define usberr(fmt,args...) serial_printf("ERROR: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args) +#define usberr(fmt, args...) serial_printf("ERROR: %s(), %d: " fmt "\n", __func__, __LINE__, ##args) #else #define usberr(fmt,args...) do{}while(0) #endif #if 0 -#define usbdbg(fmt,args...) serial_printf("debug: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args) +#define usbdbg(fmt, args...) serial_printf("debug: %s(), %d: " fmt "\n", __func__, __LINE__, ##args) #else #define usbdbg(fmt,args...) do{}while(0) #endif #if 0 -#define usbinfo(fmt,args...) serial_printf("info: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args) +#define usbinfo(fmt, args...) serial_printf("info: %s(), %d: " fmt "\n", __func__, __LINE__, ##args) #else #define usbinfo(fmt,args...) do{}while(0) #endif -- cgit v1.3.1 From e65a87e959166e250a486b67ca23270272741643 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Thu, 28 May 2026 15:49:06 +0200 Subject: serial: lpuart: Fix RX FIFO Enable bitmask MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Receive FIFO Enable (RXFE) field in the LPUART FIFO register is bit 3 on all supported architectures. The define has been wrong since it was introduced: for non-i.MX8/i.MXRT it set bit 6, which on LS102xA is read-only-as-zero, so the bug went unnoticed. NXP confirmed bit 3 is correct everywhere, so drop the ARCH-based selection. Link: https://github.com/nxp-imx/uboot-imx/commit/9498bcc514737269bb0ca436f775460741ab8199 Link: https://lore.kernel.org/u-boot/dc163ea7-9063-4dfb-a39a-e643c0bcccf1@oss.nxp.com/ Fixes: 6209e14cb026 ("serial: lpuart: add 32-bit registers lpuart support") Signed-off-by: Emanuele Ghidoli Reviewed-by: Francesco Dolcini Reviewed-by: Sébastien Szymanski --- drivers/serial/serial_lpuart.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 9fdb6503085..3f5fadfc80a 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -53,11 +53,7 @@ #define FIFO_RXSIZE_MASK 0x7 #define FIFO_RXSIZE_OFF 0 #define FIFO_TXFE 0x80 -#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT) #define FIFO_RXFE 0x08 -#else -#define FIFO_RXFE 0x40 -#endif #define WATER_TXWATER_OFF 0 #define WATER_RXWATER_OFF 16 -- cgit v1.3.1 From 4e249b94af928aca29972fc22ef2b5ed0016eab9 Mon Sep 17 00:00:00 2001 From: Torsten Duwe Date: Thu, 28 May 2026 13:22:06 +0200 Subject: clk: enhance clk-gpio to also handle gated-fixed-clock Devicetree commit a198185b9b5 introduced a new type of clock, "gated-fixed-clock", for which Das U-Boot does not have a driver yet. The required code is similar to gpio-gate-clock, and can be added using little extra text space. Use this code e.g. to boot a Rock5 ITX from NVMe Signed-off-by: Torsten Duwe --- configs/rock-5-itx-rk3588_defconfig | 1 + drivers/clk/clk-gpio.c | 29 ++++++++++++++++++++++------- 2 files changed, 23 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/configs/rock-5-itx-rk3588_defconfig b/configs/rock-5-itx-rk3588_defconfig index cb014de4188..adb20c2f3a0 100644 --- a/configs/rock-5-itx-rk3588_defconfig +++ b/configs/rock-5-itx-rk3588_defconfig @@ -52,6 +52,7 @@ CONFIG_AHCI=y CONFIG_AHCI_PCI=y CONFIG_DWC_AHCI=y CONFIG_SPL_CLK=y +CONFIG_CLK_GPIO=y # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c index 4ed14306575..b7abc891ed2 100644 --- a/drivers/clk/clk-gpio.c +++ b/drivers/clk/clk-gpio.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -13,14 +14,18 @@ struct clk_gpio_priv { struct gpio_desc enable; /* GPIO, controlling the gate */ struct clk *clk; /* Gated clock */ + struct udevice *vdd_supply; }; static int clk_gpio_enable(struct clk *clk) { struct clk_gpio_priv *priv = dev_get_priv(clk->dev); - clk_enable(priv->clk); - dm_gpio_set_value(&priv->enable, 1); + if (priv->clk) + clk_enable(priv->clk); + + if (priv->enable.dev) + dm_gpio_set_value(&priv->enable, 1); return 0; } @@ -29,8 +34,11 @@ static int clk_gpio_disable(struct clk *clk) { struct clk_gpio_priv *priv = dev_get_priv(clk->dev); - dm_gpio_set_value(&priv->enable, 0); - clk_disable(priv->clk); + if (priv->enable.dev) + dm_gpio_set_value(&priv->enable, 0); + + if (priv->clk) + clk_disable(priv->clk); return 0; } @@ -39,7 +47,7 @@ static ulong clk_gpio_get_rate(struct clk *clk) { struct clk_gpio_priv *priv = dev_get_priv(clk->dev); - return clk_get_rate(priv->clk); + return (priv->clk) ? clk_get_rate(priv->clk) : -1; } const struct clk_ops clk_gpio_ops = { @@ -57,7 +65,7 @@ static int clk_gpio_probe(struct udevice *dev) if (IS_ERR(priv->clk)) { log_debug("%s: Could not get gated clock: %ld\n", __func__, PTR_ERR(priv->clk)); - return PTR_ERR(priv->clk); + priv->clk = 0; } ret = gpio_request_by_name(dev, "enable-gpios", 0, @@ -65,9 +73,15 @@ static int clk_gpio_probe(struct udevice *dev) if (ret) { log_debug("%s: Could not decode enable-gpios (%d)\n", __func__, ret); - return ret; } + ret = device_get_supply_regulator(dev, "vdd-supply", + &priv->vdd_supply); + if (ret == 0) + ret = regulator_set_enable(priv->vdd_supply, true); + + log_debug("%s: %s regulator = %d\n", __func__, dev->name, ret); + return 0; } @@ -80,6 +94,7 @@ static int clk_gpio_probe(struct udevice *dev) */ static const struct udevice_id clk_gpio_match[] = { { .compatible = "gpio-gate-clock" }, + { .compatible = "gated-fixed-clock" }, { /* sentinel */ } }; -- cgit v1.3.1 From a566d32693600bbbe405ca5a7f4ab07f71f45e86 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 11 Jun 2026 08:01:22 -0600 Subject: Revert "clk: enhance clk-gpio to also handle gated-fixed-clock" I had missed the review comments from Jonas Karlman when applying this, it's not yet ready for inclusion. This reverts commit 4e249b94af928aca29972fc22ef2b5ed0016eab9. Signed-off-by: Tom Rini --- configs/rock-5-itx-rk3588_defconfig | 1 - drivers/clk/clk-gpio.c | 29 +++++++---------------------- 2 files changed, 7 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/configs/rock-5-itx-rk3588_defconfig b/configs/rock-5-itx-rk3588_defconfig index adb20c2f3a0..cb014de4188 100644 --- a/configs/rock-5-itx-rk3588_defconfig +++ b/configs/rock-5-itx-rk3588_defconfig @@ -52,7 +52,6 @@ CONFIG_AHCI=y CONFIG_AHCI_PCI=y CONFIG_DWC_AHCI=y CONFIG_SPL_CLK=y -CONFIG_CLK_GPIO=y # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c index b7abc891ed2..4ed14306575 100644 --- a/drivers/clk/clk-gpio.c +++ b/drivers/clk/clk-gpio.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include @@ -14,18 +13,14 @@ struct clk_gpio_priv { struct gpio_desc enable; /* GPIO, controlling the gate */ struct clk *clk; /* Gated clock */ - struct udevice *vdd_supply; }; static int clk_gpio_enable(struct clk *clk) { struct clk_gpio_priv *priv = dev_get_priv(clk->dev); - if (priv->clk) - clk_enable(priv->clk); - - if (priv->enable.dev) - dm_gpio_set_value(&priv->enable, 1); + clk_enable(priv->clk); + dm_gpio_set_value(&priv->enable, 1); return 0; } @@ -34,11 +29,8 @@ static int clk_gpio_disable(struct clk *clk) { struct clk_gpio_priv *priv = dev_get_priv(clk->dev); - if (priv->enable.dev) - dm_gpio_set_value(&priv->enable, 0); - - if (priv->clk) - clk_disable(priv->clk); + dm_gpio_set_value(&priv->enable, 0); + clk_disable(priv->clk); return 0; } @@ -47,7 +39,7 @@ static ulong clk_gpio_get_rate(struct clk *clk) { struct clk_gpio_priv *priv = dev_get_priv(clk->dev); - return (priv->clk) ? clk_get_rate(priv->clk) : -1; + return clk_get_rate(priv->clk); } const struct clk_ops clk_gpio_ops = { @@ -65,7 +57,7 @@ static int clk_gpio_probe(struct udevice *dev) if (IS_ERR(priv->clk)) { log_debug("%s: Could not get gated clock: %ld\n", __func__, PTR_ERR(priv->clk)); - priv->clk = 0; + return PTR_ERR(priv->clk); } ret = gpio_request_by_name(dev, "enable-gpios", 0, @@ -73,15 +65,9 @@ static int clk_gpio_probe(struct udevice *dev) if (ret) { log_debug("%s: Could not decode enable-gpios (%d)\n", __func__, ret); + return ret; } - ret = device_get_supply_regulator(dev, "vdd-supply", - &priv->vdd_supply); - if (ret == 0) - ret = regulator_set_enable(priv->vdd_supply, true); - - log_debug("%s: %s regulator = %d\n", __func__, dev->name, ret); - return 0; } @@ -94,7 +80,6 @@ static int clk_gpio_probe(struct udevice *dev) */ static const struct udevice_id clk_gpio_match[] = { { .compatible = "gpio-gate-clock" }, - { .compatible = "gated-fixed-clock" }, { /* sentinel */ } }; -- cgit v1.3.1 From 53e9c41847c24b422ecd21421204d4e6a0c07d76 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 25 May 2026 11:09:39 +0800 Subject: dm: core: use DT region size when mapping device addresses Update dev_read_addr_*_ptr() and dev_remap_addr_*() helpers to use dev_read_addr_size_*() and pass the DT-provided region size to map_sysmem() / map_physmem() instead of 0. Ensure mappings are consistent with the size defined in the device tree and avoids implicit or unbounded mappings. When the DT does not provide a size, the behavior remains unchanged since size is initialized to 0. Signed-off-by: Peng Fan --- drivers/core/read.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/core/read.c b/drivers/core/read.c index c0d7a969db2..ba48862f44b 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -132,12 +132,14 @@ fdt_addr_t dev_read_addr_index(const struct udevice *dev, int index) void *dev_read_addr_index_ptr(const struct udevice *dev, int index) { - fdt_addr_t addr = dev_read_addr_index(dev, index); + fdt_addr_t addr; + fdt_size_t size = 0; + addr = dev_read_addr_size_index(dev, index, &size); if (addr == FDT_ADDR_T_NONE) return NULL; - return map_sysmem(addr, 0); + return map_sysmem(addr, size); } fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index, @@ -157,17 +159,19 @@ void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index, if (addr == FDT_ADDR_T_NONE) return NULL; - return map_sysmem(addr, 0); + return map_sysmem(addr, *size); } void *dev_remap_addr_index(const struct udevice *dev, int index) { - fdt_addr_t addr = dev_read_addr_index(dev, index); + fdt_addr_t addr; + fdt_size_t size = 0; + addr = dev_read_addr_size_index(dev, index, &size); if (addr == FDT_ADDR_T_NONE) return NULL; - return map_physmem(addr, 0, MAP_NOCACHE); + return map_physmem(addr, size, MAP_NOCACHE); } fdt_addr_t dev_read_addr_name(const struct udevice *dev, const char *name) @@ -182,12 +186,14 @@ fdt_addr_t dev_read_addr_name(const struct udevice *dev, const char *name) void *dev_read_addr_name_ptr(const struct udevice *dev, const char *name) { - fdt_addr_t addr = dev_read_addr_name(dev, name); + fdt_addr_t addr; + fdt_size_t size = 0; + addr = dev_read_addr_size_name(dev, name, &size); if (addr == FDT_ADDR_T_NONE) return NULL; - return map_sysmem(addr, 0); + return map_sysmem(addr, size); } fdt_addr_t dev_read_addr_size_name(const struct udevice *dev, const char *name, @@ -209,17 +215,19 @@ void *dev_read_addr_size_name_ptr(const struct udevice *dev, const char *name, if (addr == FDT_ADDR_T_NONE) return NULL; - return map_sysmem(addr, 0); + return map_sysmem(addr, *size); } void *dev_remap_addr_name(const struct udevice *dev, const char *name) { - fdt_addr_t addr = dev_read_addr_name(dev, name); + fdt_addr_t addr; + fdt_size_t size = 0; + addr = dev_read_addr_size_name(dev, name, &size); if (addr == FDT_ADDR_T_NONE) return NULL; - return map_physmem(addr, 0, MAP_NOCACHE); + return map_physmem(addr, size, MAP_NOCACHE); } fdt_addr_t dev_read_addr(const struct udevice *dev) @@ -229,12 +237,14 @@ fdt_addr_t dev_read_addr(const struct udevice *dev) void *dev_read_addr_ptr(const struct udevice *dev) { - fdt_addr_t addr = dev_read_addr(dev); + fdt_addr_t addr; + fdt_size_t size = 0; + addr = dev_read_addr_size(dev, &size); if (addr == FDT_ADDR_T_NONE) return NULL; - return map_sysmem(addr, 0); + return map_sysmem(addr, size); } void *dev_remap_addr(const struct udevice *dev) -- cgit v1.3.1 From 9d551d78f74846fc4c4f2b369ca7da420e5e1fd6 Mon Sep 17 00:00:00 2001 From: Francois Berder Date: Thu, 21 May 2026 19:50:48 +0200 Subject: drivers: gpio: Fix dev_read_addr error check dev_read_addr returns FDT_ADDR_T_NONE (-1) in case of error and not 0. Signed-off-by: Francois Berder Reviewed-by: Simon Glass --- drivers/gpio/gpio-fxl6408.c | 2 +- drivers/gpio/pca953x_gpio.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/gpio-fxl6408.c b/drivers/gpio/gpio-fxl6408.c index c8d2dff5f7b..180799139b3 100644 --- a/drivers/gpio/gpio-fxl6408.c +++ b/drivers/gpio/gpio-fxl6408.c @@ -273,7 +273,7 @@ static int fxl6408_probe(struct udevice *dev) u32 val32; addr = dev_read_addr(dev); - if (addr == 0) + if (addr == FDT_ADDR_T_NONE) return -EINVAL; info->addr = addr; diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c index 523ca8473a8..965a5fcf30b 100644 --- a/drivers/gpio/pca953x_gpio.c +++ b/drivers/gpio/pca953x_gpio.c @@ -312,7 +312,7 @@ static int pca953x_probe(struct udevice *dev) u8 val[MAX_BANK]; addr = dev_read_addr(dev); - if (addr == 0) + if (addr == FDT_ADDR_T_NONE) return -ENODEV; info->addr = addr; -- cgit v1.3.1 From 0c57d71f4ef33275a49c422b8375e0c785eb961f Mon Sep 17 00:00:00 2001 From: "Markus Schneider-Pargmann (TI)" Date: Mon, 1 Jun 2026 11:30:46 +0200 Subject: dm: core: Split SIMPLE_PM_BUS into phases Similar to SIMPLE_BUS, create a SPL_SIMPLE_PM_BUS additional to the SIMPLE_PM_BUS. Most boards will not need SIMPLE_PM_BUS in SPL. This is currently needed to reduce the SPL size for beagle bone black with OF_UPSTREAM enabled. Reviewed-by: Simon Glass Reviewed-by: Kory Maincent Signed-off-by: Markus Schneider-Pargmann (TI) --- drivers/core/Kconfig | 8 ++++++++ drivers/core/Makefile | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 5419bf65b5d..cbefb522e58 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -342,6 +342,14 @@ config SIMPLE_PM_BUS Supports the 'simple-pm-bus' driver, which is used for busses that have power domains and/or clocks which need to be enabled before use. +config SPL_SIMPLE_PM_BUS + bool "Support simple-pm-bus driver in SPL" + depends on SPL_DM && SPL_OF_CONTROL && SPL_POWER_DOMAIN + help + Supports the 'simple-pm-bus' driver, which is used for busses that + have power domains and/or clocks which need to be enabled before use, + in SPL. + config OF_TRANSLATE bool "Translate addresses using fdt_translate_address" depends on DM && OF_CONTROL diff --git a/drivers/core/Makefile b/drivers/core/Makefile index a549890c22b..1073c26b2ed 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi.o obj-$(CONFIG_$(PHASE_)DEVRES) += devres.o obj-$(CONFIG_$(PHASE_)DM_DEVICE_REMOVE) += device-remove.o obj-$(CONFIG_$(PHASE_)SIMPLE_BUS) += simple-bus.o -obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o +obj-$(CONFIG_$(PHASE_)SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_DM) += dump.o obj-$(CONFIG_$(PHASE_)REGMAP) += regmap.o obj-$(CONFIG_$(PHASE_)SYSCON) += syscon-uclass.o -- cgit v1.3.1 From 5c3741f1355be429f8258975745f2ec701174cc8 Mon Sep 17 00:00:00 2001 From: "Markus Schneider-Pargmann (TI)" Date: Mon, 1 Jun 2026 11:30:49 +0200 Subject: dm: core: Remove dependency on CLK CLK is an optional dependency of simple-pm-bus. Remove the dependency. Fixes: 447bd8f1e5cf ("simple-pm-bus: Make clocks optional") Signed-off-by: Markus Schneider-Pargmann (TI) --- drivers/core/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index cbefb522e58..ae0c3466772 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -337,7 +337,7 @@ config SIMPLE_BUS_CORRECT_RANGE config SIMPLE_PM_BUS bool "Support simple-pm-bus driver" - depends on DM && OF_CONTROL && CLK && POWER_DOMAIN + depends on DM && OF_CONTROL && POWER_DOMAIN help Supports the 'simple-pm-bus' driver, which is used for busses that have power domains and/or clocks which need to be enabled before use. -- cgit v1.3.1 From de2e3f00f2fa3fc4c11be48b3ef6af7b0fd7bd33 Mon Sep 17 00:00:00 2001 From: Bastien Curutchet Date: Mon, 8 Jun 2026 15:11:59 +0200 Subject: clk: ti: Remove AM33xx dependency The clock controller driven by this driver exists on other OMAP platforms than the AM33xx. Yet, it uses functions provided by arch/arm/mach-omap2/am33xx/clock.c making it unusable by other OMAPs. Replace am33xx-specific do_{enable/disable}_clocks() with new static functions implemented locally. Replace the am33xx-specific clock header with the one shared by all OMAP platforms. Signed-off-by: Bastien Curutchet --- drivers/clk/ti/clk-ctrl.c | 48 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 37 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/ti/clk-ctrl.c b/drivers/clk/ti/clk-ctrl.c index c5c97dc35c4..08f7410edce 100644 --- a/drivers/clk/ti/clk-ctrl.c +++ b/drivers/clk/ti/clk-ctrl.c @@ -8,7 +8,11 @@ #include #include #include -#include +#include +#include +#include + +#define TRANSITION_TIMEOUT_US 10000 struct clk_ti_ctrl_offs { fdt_addr_t start; @@ -33,10 +37,37 @@ static int clk_ti_ctrl_check_offs(struct clk *clk, fdt_addr_t offs) return -EFAULT; } +#define IDLEST_DISABLED (MODULE_CLKCTRL_IDLEST_DISABLED << MODULE_CLKCTRL_IDLEST_SHIFT) +#define IDLEST_TRANSITION (MODULE_CLKCTRL_IDLEST_TRANSITIONING << MODULE_CLKCTRL_IDLEST_SHIFT) +static int clk_ti_ctrl_disable_clock_module(u32 addr) +{ + int val; + + clrsetbits_le32(addr, MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_DISABLE << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + return readl_relaxed_poll_timeout(addr, val, + (val & MODULE_CLKCTRL_IDLEST_MASK) == IDLEST_DISABLED, + TRANSITION_TIMEOUT_US); +} + +static int clk_ti_ctrl_enable_clock_module(u32 addr) +{ + int val; + + clrsetbits_le32(addr, MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + return readl_relaxed_poll_timeout(addr, val, + ((val & MODULE_CLKCTRL_IDLEST_MASK) != IDLEST_DISABLED) && + ((val & MODULE_CLKCTRL_IDLEST_MASK) != IDLEST_TRANSITION), + TRANSITION_TIMEOUT_US); +} + static int clk_ti_ctrl_disable(struct clk *clk) { struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev); - u32 *clk_modules[2] = { }; fdt_addr_t offs; int err; @@ -47,16 +78,13 @@ static int clk_ti_ctrl_disable(struct clk *clk) return err; } - clk_modules[0] = (u32 *)(offs); - dev_dbg(clk->dev, "disable module @ %p\n", clk_modules[0]); - do_disable_clocks(NULL, clk_modules, 1); - return 0; + dev_dbg(clk->dev, "disable module @ %x\n", offs); + return clk_ti_ctrl_disable_clock_module(offs); } static int clk_ti_ctrl_enable(struct clk *clk) { struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev); - u32 *clk_modules[2] = { }; fdt_addr_t offs; int err; @@ -67,10 +95,8 @@ static int clk_ti_ctrl_enable(struct clk *clk) return err; } - clk_modules[0] = (u32 *)(offs); - dev_dbg(clk->dev, "enable module @ %p\n", clk_modules[0]); - do_enable_clocks(NULL, clk_modules, 1); - return 0; + dev_dbg(clk->dev, "enable module @ %x\n", offs); + return clk_ti_ctrl_enable_clock_module(offs); } static ulong clk_ti_ctrl_get_rate(struct clk *clk) -- cgit v1.3.1 From 93d204f7175cb52fa57ebef63a0d940ad5940dbe Mon Sep 17 00:00:00 2001 From: Bastien Curutchet Date: Mon, 8 Jun 2026 15:12:01 +0200 Subject: arm: ti: Introduce back omap4 support omap4 support was dropped by b0ee3fe642c ("arm: ti: Remove omap4 platform support") because the supported boards hadn't done the conversion to CONFIG_DM_I2C in time. It still exists some omap4-based products and they could benefit from the latest U-Boot support for obvious security reasons. Revert part of b0ee3fe642c to introduce back a minimal support for the omap4 platform. Fix the checkpatch's warning/errors induced by this revert. Following warnings are still present: | arch/arm/include/asm/arch-omap4/clock.h:445: WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? | arch/arm/mach-omap2/omap4/hwinit.c:24: WARNING: Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where possible | arch/arm/mach-omap2/omap4/sdram_elpida.c:142: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:143: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:144: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:145: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:146: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:147: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:148: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:149: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:150: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:151: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:152: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:153: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:154: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:155: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:156: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:157: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:158: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:159: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:209: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:210: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:213: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:215: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:216: CHECK: Avoid CamelCase: | arch/arm/mach-omap2/omap4/sdram_elpida.c:217: CHECK: Avoid CamelCase: I didn't find an clean way to fix the "don't use #ifdef" warning as we need to define the gpio_bank for the SPL build only. For the CamelCase warnings, the incriminated attributes represent timings, so IMHO, it is more readable with CamelCase. Set myself as OMAP4 maintainer. Signed-off-by: Bastien Curutchet --- MAINTAINERS | 8 + arch/arm/include/asm/arch-omap4/clock.h | 84 +++++ arch/arm/include/asm/arch-omap4/cpu.h | 109 +++++++ arch/arm/include/asm/arch-omap4/ehci.h | 38 +++ arch/arm/include/asm/arch-omap4/gpio.h | 34 ++ arch/arm/include/asm/arch-omap4/hardware.h | 25 ++ arch/arm/include/asm/arch-omap4/i2c.h | 11 + arch/arm/include/asm/arch-omap4/mem.h | 61 ++++ arch/arm/include/asm/arch-omap4/mmc_host_def.h | 16 + arch/arm/include/asm/arch-omap4/mux_omap4.h | 325 +++++++++++++++++++ arch/arm/include/asm/arch-omap4/omap.h | 143 +++++++++ arch/arm/include/asm/arch-omap4/spl.h | 22 ++ arch/arm/include/asm/arch-omap4/sys_proto.h | 73 +++++ arch/arm/include/asm/omap_common.h | 16 +- arch/arm/mach-omap2/Kconfig | 24 +- arch/arm/mach-omap2/Makefile | 3 +- arch/arm/mach-omap2/omap4/Kconfig | 6 + arch/arm/mach-omap2/omap4/Makefile | 10 + arch/arm/mach-omap2/omap4/boot.c | 103 ++++++ arch/arm/mach-omap2/omap4/hw_data.c | 420 +++++++++++++++++++++++++ arch/arm/mach-omap2/omap4/hwinit.c | 182 +++++++++++ arch/arm/mach-omap2/omap4/prcm-regs.c | 306 ++++++++++++++++++ arch/arm/mach-omap2/omap4/sdram_elpida.c | 265 ++++++++++++++++ common/spl/Kconfig | 4 +- drivers/i2c/Kconfig | 2 +- drivers/mmc/Kconfig | 2 +- 26 files changed, 2278 insertions(+), 14 deletions(-) create mode 100644 arch/arm/include/asm/arch-omap4/clock.h create mode 100644 arch/arm/include/asm/arch-omap4/cpu.h create mode 100644 arch/arm/include/asm/arch-omap4/ehci.h create mode 100644 arch/arm/include/asm/arch-omap4/gpio.h create mode 100644 arch/arm/include/asm/arch-omap4/hardware.h create mode 100644 arch/arm/include/asm/arch-omap4/i2c.h create mode 100644 arch/arm/include/asm/arch-omap4/mem.h create mode 100644 arch/arm/include/asm/arch-omap4/mmc_host_def.h create mode 100644 arch/arm/include/asm/arch-omap4/mux_omap4.h create mode 100644 arch/arm/include/asm/arch-omap4/omap.h create mode 100644 arch/arm/include/asm/arch-omap4/spl.h create mode 100644 arch/arm/include/asm/arch-omap4/sys_proto.h create mode 100644 arch/arm/mach-omap2/omap4/Kconfig create mode 100644 arch/arm/mach-omap2/omap4/Makefile create mode 100644 arch/arm/mach-omap2/omap4/boot.c create mode 100644 arch/arm/mach-omap2/omap4/hw_data.c create mode 100644 arch/arm/mach-omap2/omap4/hwinit.c create mode 100644 arch/arm/mach-omap2/omap4/prcm-regs.c create mode 100644 arch/arm/mach-omap2/omap4/sdram_elpida.c (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index 0dcc7243124..4d4af983596 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -831,6 +831,14 @@ F: drivers/watchdog/omap_wdt.c F: include/linux/pruss_driver.h F: include/linux/soc/ti/ +ARM TI OMAP4 +M: Bastien Curutchet +S: Maintained +F: arch/arm/dts/omap4* +F: arch/arm/include/asm/arch-omap4/ +F: arch/arm/mach-omap2/omap4/ +F: include/configs/ti_omap4_common.h + ARM U8500 M: Stephan Gerhold R: Linus Walleij diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h new file mode 100644 index 00000000000..f020c94428a --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + */ +#ifndef _CLOCKS_OMAP4_H_ +#define _CLOCKS_OMAP4_H_ + +#define LDELAY 1000000 + +#include + +/* ALTCLKSRC */ +#define ALTCLKSRC_MODE_ACTIVE 1 +#define ALTCLKSRC_MODE_MASK 3 +#define ALTCLKSRC_ENABLE_INT_MASK 4 +#define ALTCLKSRC_ENABLE_EXT_MASK 8 + +/* CM_COREAON_USB_PHY_CORE_CLKCTRL */ +#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K BIT(8) + +/* CM_L3INIT_USBPHY_CLKCTRL */ +#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK BIT(8) + +/* TWL6030 SMPS */ +#define SMPS_REG_ADDR_VCORE1 0x55 +#define SMPS_REG_ADDR_VCORE2 0x5B +#define SMPS_REG_ADDR_VCORE3 0x61 +/* TWL6032 SMPS */ +#define SMPS_REG_ADDR_SMPS1 0x55 +#define SMPS_REG_ADDR_SMPS2 0x5B +#define SMPS_REG_ADDR_SMPS5 0x49 + +/* PMIC */ +#define SMPS_I2C_SLAVE_ADDR 0x12 + +/* Clock Defines */ +#define V_OSCK 38400000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + +struct omap4_scrm_regs { + u32 revision; /* 0x0000 */ + u32 pad00[63]; + u32 clksetuptime; /* 0x0100 */ + u32 pmicsetuptime; /* 0x0104 */ + u32 pad01[2]; + u32 altclksrc; /* 0x0110 */ + u32 pad02[2]; + u32 c2cclkm; /* 0x011c */ + u32 pad03[56]; + u32 extclkreq; /* 0x0200 */ + u32 accclkreq; /* 0x0204 */ + u32 pwrreq; /* 0x0208 */ + u32 pad04[1]; + u32 auxclkreq0; /* 0x0210 */ + u32 auxclkreq1; /* 0x0214 */ + u32 auxclkreq2; /* 0x0218 */ + u32 auxclkreq3; /* 0x021c */ + u32 auxclkreq4; /* 0x0220 */ + u32 auxclkreq5; /* 0x0224 */ + u32 pad05[3]; + u32 c2cclkreq; /* 0x0234 */ + u32 pad06[54]; + u32 auxclk0; /* 0x0310 */ + u32 auxclk1; /* 0x0314 */ + u32 auxclk2; /* 0x0318 */ + u32 auxclk3; /* 0x031c */ + u32 auxclk4; /* 0x0320 */ + u32 auxclk5; /* 0x0324 */ + u32 pad07[54]; + u32 rsttime_reg; /* 0x0400 */ + u32 pad08[6]; + u32 c2crstctrl; /* 0x041c */ + u32 extpwronrstctrl; /* 0x0420 */ + u32 pad09[59]; + u32 extwarmrstst_reg; /* 0x0510 */ + u32 apewarmrstst_reg; /* 0x0514 */ + u32 pad10[1]; + u32 c2cwarmrstst_reg; /* 0x051C */ +}; + +#endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h new file mode 100644 index 00000000000..4c9ed455833 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2010 + * Texas Instruments, + */ + +#ifndef _CPU_H +#define _CPU_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct gptimer { + u32 tidr; /* 0x00 r */ + u8 res[0xc]; + u32 tiocp_cfg; /* 0x10 rw */ + u32 tistat; /* 0x14 r */ + u32 tisr; /* 0x18 rw */ + u32 tier; /* 0x1c rw */ + u32 twer; /* 0x20 rw */ + u32 tclr; /* 0x24 rw */ + u32 tcrr; /* 0x28 rw */ + u32 tldr; /* 0x2c rw */ + u32 ttgr; /* 0x30 rw */ + u32 twpc; /* 0x34 r */ + u32 tmar; /* 0x38 rw */ + u32 tcar1; /* 0x3c r */ + u32 tcicr; /* 0x40 rw */ + u32 tcar2; /* 0x44 r */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +/* enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) + +/* Watchdog */ +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct watchdog { + u8 res1[0x34]; + u32 wwps; /* 0x34 r */ + u8 res2[0x10]; + u32 wspr; /* 0x48 rw */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* I2C base */ +#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) +#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) +#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000) +#define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000) + +/* MUSB base */ +#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000) + +/* OMAP4 GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0114 +#define OMAP_GPIO_IRQSTATUS1 0x0118 +#define OMAP_GPIO_IRQSTATUS2 0x0128 +#define OMAP_GPIO_IRQENABLE2 0x012c +#define OMAP_GPIO_IRQENABLE1 0x011c +#define OMAP_GPIO_WAKE_EN 0x0120 +#define OMAP_GPIO_CTRL 0x0130 +#define OMAP_GPIO_OE 0x0134 +#define OMAP_GPIO_DATAIN 0x0138 +#define OMAP_GPIO_DATAOUT 0x013c +#define OMAP_GPIO_LEVELDETECT0 0x0140 +#define OMAP_GPIO_LEVELDETECT1 0x0144 +#define OMAP_GPIO_RISINGDETECT 0x0148 +#define OMAP_GPIO_FALLINGDETECT 0x014c +#define OMAP_GPIO_DEBOUNCE_EN 0x0150 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 +#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 +#define OMAP_GPIO_SETIRQENABLE1 0x0164 +#define OMAP_GPIO_CLEARWKUENA 0x0180 +#define OMAP_GPIO_SETWKUENA 0x0184 +#define OMAP_GPIO_CLEARDATAOUT 0x0190 +#define OMAP_GPIO_SETDATAOUT 0x0194 + +/* + * PRCM + */ + +/* PRM */ +#define PRM_BASE 0x4A306000 +#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) + +#define PRM_RSTCTRL PRM_DEVICE_BASE +#define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) +#define PRM_RSTST_WARM_RESET_MASK 0x07EA + +#endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap4/ehci.h b/arch/arm/include/asm/arch-omap4/ehci.h new file mode 100644 index 00000000000..447c6b1320f --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/ehci.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * OMAP EHCI port support + * Based on LINUX KERNEL + * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com + * Author: Govindraj R + */ + +#ifndef _OMAP4_EHCI_H_ +#define _OMAP4_EHCI_H_ + +#define OMAP_EHCI_BASE (OMAP44XX_L4_CORE_BASE + 0x64C00) +#define OMAP_UHH_BASE (OMAP44XX_L4_CORE_BASE + 0x64000) +#define OMAP_USBTLL_BASE (OMAP44XX_L4_CORE_BASE + 0x62000) + +/* UHH, TLL and opt clocks */ +#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4A009358UL + +#define HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK BIT(24) + +/* TLL Register Set */ +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE BIT(3) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP BIT(2) +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET BIT(1) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY BIT(8) +#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 + +#define OMAP_UHH_SYSCONFIG_SOFTRESET 1 +#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE BIT(2) +#define OMAP_UHH_SYSCONFIG_NOIDLE BIT(2) +#define OMAP_UHH_SYSCONFIG_NOSTDBY BIT(4) + +#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ + OMAP_UHH_SYSCONFIG_NOSTDBY) + +#endif /* _OMAP4_EHCI_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/gpio.h b/arch/arm/include/asm/arch-omap4/gpio.h new file mode 100644 index 00000000000..aceb3e227c9 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/gpio.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä + */ +#ifndef _GPIO_OMAP4_H +#define _GPIO_OMAP4_H + +#include + +#define OMAP_MAX_GPIO 192 + +#define OMAP44XX_GPIO1_BASE 0x4A310000 +#define OMAP44XX_GPIO2_BASE 0x48055000 +#define OMAP44XX_GPIO3_BASE 0x48057000 +#define OMAP44XX_GPIO4_BASE 0x48059000 +#define OMAP44XX_GPIO5_BASE 0x4805B000 +#define OMAP44XX_GPIO6_BASE 0x4805D000 + +#endif /* _GPIO_OMAP4_H */ diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h new file mode 100644 index 00000000000..67e3dae7bce --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/hardware.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ + */ + +#ifndef __OMAP_HARDWARE_H +#define __OMAP_HARDWARE_H + +#include + +/* + * Common hardware definitions + */ + +/* BCH Error Location Module */ +#define ELM_BASE 0x48078000 + +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + +#endif diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h new file mode 100644 index 00000000000..c8f2f9716f1 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/i2c.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2004-2010 + * Texas Instruments, + */ +#ifndef _OMAP4_I2C_H_ +#define _OMAP4_I2C_H_ + +#define I2C_DEFAULT_BASE I2C_BASE1 + +#endif /* _OMAP4_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/mem.h b/arch/arm/include/asm/arch-omap4/mem.h new file mode 100644 index 00000000000..3026a002db3 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/mem.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * + * Author + * Mansoor Ahamed + * + * Initial Code from: + * Richard Woodruff + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define _GPMC_CONFIG + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h new file mode 100644 index 00000000000..bda9bc7db82 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +#include + +/* + * OMAP HSMMC register definitions + */ + +#define OMAP_HSMMC1_BASE 0x4809C000 +#define OMAP_HSMMC2_BASE 0x480B4000 +#define OMAP_HSMMC3_BASE 0x480AD000 + +#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h new file mode 100644 index 00000000000..637d920e0f3 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/mux_omap4.h @@ -0,0 +1,325 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2004-2009 + * Texas Instruments Incorporated + * Richard Woodruff + * Aneesh V + * Balaji Krishnamoorthy + */ +#ifndef _MUX_OMAP4_H_ +#define _MUX_OMAP4_H_ + +#include + +struct pad_conf_entry { + u16 offset; + u16 val; +}; + +#ifdef CONFIG_OFF_PADCONF +#define OFF_PD BIT(12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (2 << 10) +#define OFF_IN BIT(10) +#define OFF_OUT (0 << 10) +#define OFF_EN BIT(9) +#else +#define OFF_PD (0 << 12) +#define OFF_PU (0 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (0 << 10) +#define OFF_IN (0 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (0 << 9) +#endif + +#define IEN BIT(8) +#define IDIS (0 << 8) +#define PTU (3 << 3) +#define PTD BIT(3) +#define EN BIT(3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#define SAFE_MODE M7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif + +#define CORE_REVISION 0x0000 +#define CORE_HWINFO 0x0004 +#define CORE_SYSCONFIG 0x0010 +#define GPMC_AD0 0x0040 +#define GPMC_AD1 0x0042 +#define GPMC_AD2 0x0044 +#define GPMC_AD3 0x0046 +#define GPMC_AD4 0x0048 +#define GPMC_AD5 0x004A +#define GPMC_AD6 0x004C +#define GPMC_AD7 0x004E +#define GPMC_AD8 0x0050 +#define GPMC_AD9 0x0052 +#define GPMC_AD10 0x0054 +#define GPMC_AD11 0x0056 +#define GPMC_AD12 0x0058 +#define GPMC_AD13 0x005A +#define GPMC_AD14 0x005C +#define GPMC_AD15 0x005E +#define GPMC_A16 0x0060 +#define GPMC_A17 0x0062 +#define GPMC_A18 0x0064 +#define GPMC_A19 0x0066 +#define GPMC_A20 0x0068 +#define GPMC_A21 0x006A +#define GPMC_A22 0x006C +#define GPMC_A23 0x006E +#define GPMC_A24 0x0070 +#define GPMC_A25 0x0072 +#define GPMC_NCS0 0x0074 +#define GPMC_NCS1 0x0076 +#define GPMC_NCS2 0x0078 +#define GPMC_NCS3 0x007A +#define GPMC_NWP 0x007C +#define GPMC_CLK 0x007E +#define GPMC_NADV_ALE 0x0080 +#define GPMC_NOE 0x0082 +#define GPMC_NWE 0x0084 +#define GPMC_NBE0_CLE 0x0086 +#define GPMC_NBE1 0x0088 +#define GPMC_WAIT0 0x008A +#define GPMC_WAIT1 0x008C +#define C2C_DATA11 0x008E +#define C2C_DATA12 0x0090 +#define C2C_DATA13 0x0092 +#define C2C_DATA14 0x0094 +#define C2C_DATA15 0x0096 +#define HDMI_HPD 0x0098 +#define HDMI_CEC 0x009A +#define HDMI_DDC_SCL 0x009C +#define HDMI_DDC_SDA 0x009E +#define CSI21_DX0 0x00A0 +#define CSI21_DY0 0x00A2 +#define CSI21_DX1 0x00A4 +#define CSI21_DY1 0x00A6 +#define CSI21_DX2 0x00A8 +#define CSI21_DY2 0x00AA +#define CSI21_DX3 0x00AC +#define CSI21_DY3 0x00AE +#define CSI21_DX4 0x00B0 +#define CSI21_DY4 0x00B2 +#define CSI22_DX0 0x00B4 +#define CSI22_DY0 0x00B6 +#define CSI22_DX1 0x00B8 +#define CSI22_DY1 0x00BA +#define CAM_SHUTTER 0x00BC +#define CAM_STROBE 0x00BE +#define CAM_GLOBALRESET 0x00C0 +#define USBB1_ULPITLL_CLK 0x00C2 +#define USBB1_ULPITLL_STP 0x00C4 +#define USBB1_ULPITLL_DIR 0x00C6 +#define USBB1_ULPITLL_NXT 0x00C8 +#define USBB1_ULPITLL_DAT0 0x00CA +#define USBB1_ULPITLL_DAT1 0x00CC +#define USBB1_ULPITLL_DAT2 0x00CE +#define USBB1_ULPITLL_DAT3 0x00D0 +#define USBB1_ULPITLL_DAT4 0x00D2 +#define USBB1_ULPITLL_DAT5 0x00D4 +#define USBB1_ULPITLL_DAT6 0x00D6 +#define USBB1_ULPITLL_DAT7 0x00D8 +#define USBB1_HSIC_DATA 0x00DA +#define USBB1_HSIC_STROBE 0x00DC +#define USBC1_ICUSB_DP 0x00DE +#define USBC1_ICUSB_DM 0x00E0 +#define SDMMC1_CLK 0x00E2 +#define SDMMC1_CMD 0x00E4 +#define SDMMC1_DAT0 0x00E6 +#define SDMMC1_DAT1 0x00E8 +#define SDMMC1_DAT2 0x00EA +#define SDMMC1_DAT3 0x00EC +#define SDMMC1_DAT4 0x00EE +#define SDMMC1_DAT5 0x00F0 +#define SDMMC1_DAT6 0x00F2 +#define SDMMC1_DAT7 0x00F4 +#define ABE_MCBSP2_CLKX 0x00F6 +#define ABE_MCBSP2_DR 0x00F8 +#define ABE_MCBSP2_DX 0x00FA +#define ABE_MCBSP2_FSX 0x00FC +#define ABE_MCBSP1_CLKX 0x00FE +#define ABE_MCBSP1_DR 0x0100 +#define ABE_MCBSP1_DX 0x0102 +#define ABE_MCBSP1_FSX 0x0104 +#define ABE_PDM_UL_DATA 0x0106 +#define ABE_PDM_DL_DATA 0x0108 +#define ABE_PDM_FRAME 0x010A +#define ABE_PDM_LB_CLK 0x010C +#define ABE_CLKS 0x010E +#define ABE_DMIC_CLK1 0x0110 +#define ABE_DMIC_DIN1 0x0112 +#define ABE_DMIC_DIN2 0x0114 +#define ABE_DMIC_DIN3 0x0116 +#define UART2_CTS 0x0118 +#define UART2_RTS 0x011A +#define UART2_RX 0x011C +#define UART2_TX 0x011E +#define HDQ_SIO 0x0120 +#define I2C1_SCL 0x0122 +#define I2C1_SDA 0x0124 +#define I2C2_SCL 0x0126 +#define I2C2_SDA 0x0128 +#define I2C3_SCL 0x012A +#define I2C3_SDA 0x012C +#define I2C4_SCL 0x012E +#define I2C4_SDA 0x0130 +#define MCSPI1_CLK 0x0132 +#define MCSPI1_SOMI 0x0134 +#define MCSPI1_SIMO 0x0136 +#define MCSPI1_CS0 0x0138 +#define MCSPI1_CS1 0x013A +#define MCSPI1_CS2 0x013C +#define MCSPI1_CS3 0x013E +#define UART3_CTS_RCTX 0x0140 +#define UART3_RTS_SD 0x0142 +#define UART3_RX_IRRX 0x0144 +#define UART3_TX_IRTX 0x0146 +#define SDMMC5_CLK 0x0148 +#define SDMMC5_CMD 0x014A +#define SDMMC5_DAT0 0x014C +#define SDMMC5_DAT1 0x014E +#define SDMMC5_DAT2 0x0150 +#define SDMMC5_DAT3 0x0152 +#define MCSPI4_CLK 0x0154 +#define MCSPI4_SIMO 0x0156 +#define MCSPI4_SOMI 0x0158 +#define MCSPI4_CS0 0x015A +#define UART4_RX 0x015C +#define UART4_TX 0x015E +#define USBB2_ULPITLL_CLK 0x0160 +#define USBB2_ULPITLL_STP 0x0162 +#define USBB2_ULPITLL_DIR 0x0164 +#define USBB2_ULPITLL_NXT 0x0166 +#define USBB2_ULPITLL_DAT0 0x0168 +#define USBB2_ULPITLL_DAT1 0x016A +#define USBB2_ULPITLL_DAT2 0x016C +#define USBB2_ULPITLL_DAT3 0x016E +#define USBB2_ULPITLL_DAT4 0x0170 +#define USBB2_ULPITLL_DAT5 0x0172 +#define USBB2_ULPITLL_DAT6 0x0174 +#define USBB2_ULPITLL_DAT7 0x0176 +#define USBB2_HSIC_DATA 0x0178 +#define USBB2_HSIC_STROBE 0x017A +#define UNIPRO_TX0 0x017C +#define UNIPRO_TY0 0x017E +#define UNIPRO_TX1 0x0180 +#define UNIPRO_TY1 0x0182 +#define UNIPRO_TX2 0x0184 +#define UNIPRO_TY2 0x0186 +#define UNIPRO_RX0 0x0188 +#define UNIPRO_RY0 0x018A +#define UNIPRO_RX1 0x018C +#define UNIPRO_RY1 0x018E +#define UNIPRO_RX2 0x0190 +#define UNIPRO_RY2 0x0192 +#define USBA0_OTG_CE 0x0194 +#define USBA0_OTG_DP 0x0196 +#define USBA0_OTG_DM 0x0198 +#define FREF_CLK1_OUT 0x019A +#define FREF_CLK2_OUT 0x019C +#define SYS_NIRQ1 0x019E +#define SYS_NIRQ2 0x01A0 +#define SYS_BOOT0 0x01A2 +#define SYS_BOOT1 0x01A4 +#define SYS_BOOT2 0x01A6 +#define SYS_BOOT3 0x01A8 +#define SYS_BOOT4 0x01AA +#define SYS_BOOT5 0x01AC +#define DPM_EMU0 0x01AE +#define DPM_EMU1 0x01B0 +#define DPM_EMU2 0x01B2 +#define DPM_EMU3 0x01B4 +#define DPM_EMU4 0x01B6 +#define DPM_EMU5 0x01B8 +#define DPM_EMU6 0x01BA +#define DPM_EMU7 0x01BC +#define DPM_EMU8 0x01BE +#define DPM_EMU9 0x01C0 +#define DPM_EMU10 0x01C2 +#define DPM_EMU11 0x01C4 +#define DPM_EMU12 0x01C6 +#define DPM_EMU13 0x01C8 +#define DPM_EMU14 0x01CA +#define DPM_EMU15 0x01CC +#define DPM_EMU16 0x01CE +#define DPM_EMU17 0x01D0 +#define DPM_EMU18 0x01D2 +#define DPM_EMU19 0x01D4 +#define WAKEUPEVENT_0 0x01D8 +#define WAKEUPEVENT_1 0x01DC +#define WAKEUPEVENT_2 0x01E0 +#define WAKEUPEVENT_3 0x01E4 +#define WAKEUPEVENT_4 0x01E8 +#define WAKEUPEVENT_5 0x01EC +#define WAKEUPEVENT_6 0x01F0 + +#define WKUP_REVISION 0x0000 +#define WKUP_HWINFO 0x0004 +#define WKUP_SYSCONFIG 0x0010 +#define PAD0_SIM_IO 0x0040 +#define PAD1_SIM_CLK 0x0042 +#define PAD0_SIM_RESET 0x0044 +#define PAD1_SIM_CD 0x0046 +#define PAD0_SIM_PWRCTRL 0x0048 +#define PAD1_SR_SCL 0x004A +#define PAD0_SR_SDA 0x004C +#define PAD1_FREF_XTAL_IN 0x004E +#define PAD0_FREF_SLICER_IN 0x0050 +#define PAD1_FREF_CLK_IOREQ 0x0052 +#define PAD0_FREF_CLK0_OUT 0x0054 +#define PAD1_FREF_CLK3_REQ 0x0056 +#define PAD0_FREF_CLK3_OUT 0x0058 +#define PAD1_FREF_CLK4_REQ 0x005A +#define PAD0_FREF_CLK4_OUT 0x005C +#define PAD1_SYS_32K 0x005E +#define PAD0_SYS_NRESPWRON 0x0060 +#define PAD1_SYS_NRESWARM 0x0062 +#define PAD0_SYS_PWR_REQ 0x0064 +#define PAD1_SYS_PWRON_RESET 0x0066 +#define PAD0_SYS_BOOT6 0x0068 +#define PAD1_SYS_BOOT7 0x006A +#define PAD0_JTAG_NTRST 0x006C +#define PAD1_JTAG_TCK 0x006D +#define PAD0_JTAG_RTCK 0x0070 +#define PAD1_JTAG_TMS_TMSC 0x0072 +#define PAD0_JTAG_TDI 0x0074 +#define PAD1_JTAG_TDO 0x0076 +#define PADCONF_WAKEUPEVENT_0 0x007C +#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 +#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 +#define PADCONF_MODE 0x05A8 +#define CONTROL_XTAL_OSCILLATOR 0x05AC +#define CONTROL_CONTROL_I2C_2 0x0604 +#define CONTROL_CONTROL_JTAG 0x0608 +#define CONTROL_CONTROL_SYS 0x060C +#define CONTROL_SPARE_RW 0x0614 +#define CONTROL_SPARE_R 0x0618 +#define CONTROL_SPARE_R_C0 0x061C + +#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A +#endif /* _MUX_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h new file mode 100644 index 00000000000..2912bbc6376 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Authors: + * Aneesh V + * + * Derived from OMAP3 work by + * Richard Woodruff + * Syed Mohammed Khasim + */ + +#ifndef _OMAP4_H_ +#define _OMAP4_H_ + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP44XX_L4_CORE_BASE 0x4A000000 +#define OMAP44XX_L4_WKUP_BASE 0x4A300000 +#define OMAP44XX_L4_PER_BASE 0x48000000 + +#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 +#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 +#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START +#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END + +/* CONTROL_ID_CODE */ +#define CONTROL_ID_CODE 0x4A002204 + +#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F +#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F +#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F +#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F +#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F +#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F + +/* UART */ +#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) +#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) +#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) + +/* General Purpose Timers */ +#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) +#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) +#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) + +/* Watchdog Timer2 - MPU watchdog */ +#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) + +/* + * Hardware Register Details + */ + +/* Watchdog Timer */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* GP Timer */ +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* Control Module */ +#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) +#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f +#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 +#define CONTROL_EFUSE_2_OVERRIDE 0x99084000 + +/* LPDDR2 IO regs */ +#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C +#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E +#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C +#define LPDDR2IO_GR10_WD_MASK (3 << 17) +#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F + +/* CONTROL_EFUSE_2 */ +#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 + +#define MMC1_PWRDNZ BIT(26) +#define MMC1_PBIASLITE_PWRDNZ BIT(22) +#define MMC1_PBIASLITE_VMODE BIT(21) + +#ifndef __ASSEMBLY__ + +struct s32ktimer { + unsigned char res[0x10]; + unsigned int s32k_cr; /* 0x10 */ +}; + +#define DEVICE_TYPE_SHIFT (0x8) +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) + +#endif /* __ASSEMBLY__ */ + +/* + * Non-secure SRAM Addresses + * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE + * at 0x40304000(EMU base) so that our code works for both EMU and GP + */ +#define NON_SECURE_SRAM_START 0x40304000 +#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ +#define NON_SECURE_SRAM_IMG_END 0x4030C000 +#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_ROM_VECT_BASE 0x4030D000 + +/* ABB settings */ +#define OMAP_ABB_SETTLING_TIME 50 +#define OMAP_ABB_CLOCK_CYCLES 16 + +/* ABB tranxdone mask */ +#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) + +#define OMAP44XX_SAR_RAM_BASE 0x4a326000 +#define OMAP_REBOOT_REASON_OFFSET 0xA0C +#define OMAP_REBOOT_REASON_SIZE 0x0F + +/* Boot parameters */ +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + unsigned int boot_message; + unsigned int boot_device_descriptor; + unsigned char boot_device; + unsigned char reset_reason; + unsigned char ch_flags; +}; + +int omap_reboot_mode(char *mode, unsigned int length); +int omap_reboot_mode_clear(void); +int omap_reboot_mode_store(char *mode); +#endif + +#endif diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h new file mode 100644 index 00000000000..d24944af0ae --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/spl.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Texas Instruments, + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_NONE 0x00 +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x03 +#define BOOT_DEVICE_ONENAND 0x04 +#define BOOT_DEVICE_MMC1 0x05 +#define BOOT_DEVICE_MMC2 0x06 +#define BOOT_DEVICE_MMC2_2 0x07 +#define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_USB 0x45 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 +#endif diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h new file mode 100644 index 00000000000..c6e6f6ca480 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; +extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; +extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; +extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; +extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2; +extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2; +extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2; +#else +extern const struct lpddr2_device_details elpida_2G_S4_details; +extern const struct lpddr2_device_details elpida_4G_S4_details; +#endif + +#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +extern const struct lpddr2_device_timings jedec_default_timings; +#else +extern const struct lpddr2_device_timings elpida_2G_S4_timings; +#endif + +struct omap_sysinfo { + char *board_string; +}; + +extern const struct omap_sysinfo sysinfo; + +void gpmc_init(void); +void watchdog_init(void); +u32 get_device_type(void); +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); +void set_muxconf_regs(void); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, + u32 bound); +void sdelay(unsigned long loops); +void setup_early_clocks(void); +void prcm_init(void); +void do_board_detect(void); +void bypass_dpll(u32 const base); +void freq_update_core(void); +u32 get_sys_clk_freq(void); +u32 omap4_ddr_clk(void); +void cancel_out(u32 *num, u32 *den, u32 den_limit); +void sdram_init(void); +u32 omap_sdram_size(void); +u32 cortex_rev(void); +void save_omap_boot_params(void); +void init_omap_revision(void); +void do_io_settings(void); +void sri2c_init(void); +int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); +u32 warm_reset(void); +void force_emif_self_refresh(void); +void setup_warmreset_time(void); + +#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102 + +#endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 5e74f41dd97..9945eeb66b8 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -490,7 +490,7 @@ struct omap_sys_ctrl_regs { u32 ctrl_core_sma_sw_1; }; -#if defined(CONFIG_OMAP54XX) +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) struct dpll_params { u32 m; u32 n; @@ -523,7 +523,7 @@ struct dpll_regs { u32 cm_div_h23_dpll; u32 cm_div_h24_dpll; }; -#endif /* CONFIG_OMAP54XX */ +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ struct dplls { const struct dpll_params *mpu; @@ -547,7 +547,7 @@ struct pmic_data { int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); }; -#if defined(CONFIG_OMAP54XX) +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) enum { OPP_LOW, OPP_NOM, @@ -593,7 +593,7 @@ struct vcores_data { struct volts eve; struct volts iva; }; -#endif /* CONFIG_OMAP54XX */ +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; @@ -626,7 +626,7 @@ const struct dpll_params *get_iva_dpll_params(struct dplls const *); const struct dpll_params *get_usb_dpll_params(struct dplls const *); const struct dpll_params *get_abe_dpll_params(struct dplls const *); -#if defined(CONFIG_OMAP54XX) +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) void do_enable_clocks(u32 const *clk_domains, u32 const *clk_modules_hw_auto, u32 const *clk_modules_explicit_en, @@ -635,7 +635,7 @@ void do_enable_clocks(u32 const *clk_domains, void do_disable_clocks(u32 const *clk_domains, u32 const *clk_modules_disable, u8 wait_for_disable); -#endif /* CONFIG_OMAP54XX */ +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ void do_enable_ipu_clocks(u32 const *clk_domains, u32 const *clk_modules_hw_auto, @@ -653,9 +653,9 @@ void enable_basic_uboot_clocks(void); void enable_usb_clocks(int index); void disable_usb_clocks(int index); -#if defined(CONFIG_OMAP54XX) +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) void scale_vcores(struct vcores_data const *); -#endif /* CONFIG_OMAP54XX */ +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ int get_voltrail_opp(int rail_offset); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 1e989ac48ac..767ca904b61 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -29,6 +29,25 @@ config OMAP34XX imply SYS_THUMB_BUILD imply TWL4030_POWER +config OMAP44XX + bool "OMAP44XX SoC" + select DM_EVENT + select SPL_USE_TINY_PRINTF + select SPL_SYS_NO_VECTOR_TABLE if SPL + imply SPL_FS_FAT + imply SPL_GPIO + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_MMC + imply SPL_POWER + imply SPL_SERIAL + imply SYS_I2C_OMAP24XX + imply SYS_THUMB_BUILD + help + Support for OMAP44x SOC from Texas Instruments. + OMAP44x features two Cortex-A9 cores. + config OMAP54XX bool "OMAP54XX SoC" select ARM_CORTEX_A15_CVE_2017_5715 @@ -139,7 +158,7 @@ config SYS_AUTOMATIC_SDRAM_DETECTION bool choice - depends on OMAP54XX + depends on OMAP44XX || OMAP54XX prompt "Static or dynamic DDR timing calculations" default SYS_EMIF_PRECALCULATED_TIMING_REGS help @@ -152,6 +171,7 @@ config SYS_EMIF_PRECALCULATED_TIMING_REGS config SYS_DEFAULT_LPDDR2_TIMINGS bool "Use default LPDDR2 timing values" + depends on !OMAP44XX select SYS_AUTOMATIC_SDRAM_DETECTION endchoice @@ -195,6 +215,8 @@ endif source "arch/arm/mach-omap2/omap3/Kconfig" +source "arch/arm/mach-omap2/omap4/Kconfig" + source "arch/arm/mach-omap2/omap5/Kconfig" source "arch/arm/mach-omap2/am33xx/Kconfig" diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index fb5ea97e56e..c34caca78af 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -5,6 +5,7 @@ obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ obj-$(CONFIG_OMAP34XX) += omap3/ +obj-$(CONFIG_OMAP44XX) += omap4/ obj-$(CONFIG_OMAP54XX) += omap5/ obj-y += reset.o @@ -18,7 +19,7 @@ endif obj-y += utils.o obj-y += sysinfo-common.o -ifdef CONFIG_OMAP54XX +ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) obj-y += hwinit-common.o obj-y += clocks-common.o obj-y += emif-common.o diff --git a/arch/arm/mach-omap2/omap4/Kconfig b/arch/arm/mach-omap2/omap4/Kconfig new file mode 100644 index 00000000000..b320490d666 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/Kconfig @@ -0,0 +1,6 @@ +if OMAP44XX + +config SYS_SOC + default "omap4" + +endif diff --git a/arch/arm/mach-omap2/omap4/Makefile b/arch/arm/mach-omap2/omap4/Makefile new file mode 100644 index 00000000000..2566c6ca2d3 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2010 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y += boot.o +obj-y += sdram_elpida.o +obj-y += hwinit.o +obj-y += prcm-regs.o +obj-y += hw_data.o diff --git a/arch/arm/mach-omap2/omap4/boot.c b/arch/arm/mach-omap2/omap4/boot.c new file mode 100644 index 00000000000..fc71db42d90 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/boot.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OMAP4 boot + * + * Copyright (C) 2015 Paul Kocialkowski + */ + +#include +#include +#include +#include + +static u32 boot_devices[] = { + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NONE, + BOOT_DEVICE_XIPWAIT, +}; + +u32 omap_sys_boot_device(void) +{ + u32 sys_boot; + + /* Grab the first 5 bits of the status register for SYS_BOOT. */ + sys_boot = readl((u32 *)(*ctrl)->control_status) & ((1 << 5) - 1); + + if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) + return BOOT_DEVICE_NONE; + + return boot_devices[sys_boot]; +} + +int omap_reboot_mode(char *mode, unsigned int length) +{ + unsigned int limit; + unsigned int i; + + if (length < 2) + return -1; + + if (!warm_reset()) + return -1; + + limit = (length < OMAP_REBOOT_REASON_SIZE) ? length : + OMAP_REBOOT_REASON_SIZE; + + for (i = 0; i < (limit - 1); i++) + mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE + + OMAP_REBOOT_REASON_OFFSET + i)); + + mode[i] = '\0'; + + return 0; +} + +int omap_reboot_mode_clear(void) +{ + writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET)); + + return 0; +} + +int omap_reboot_mode_store(char *mode) +{ + unsigned int i; + + for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++) + writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE + + OMAP_REBOOT_REASON_OFFSET + i)); + + writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE + + OMAP_REBOOT_REASON_OFFSET + i)); + + return 0; +} diff --git a/arch/arm/mach-omap2/omap4/hw_data.c b/arch/arm/mach-omap2/omap4/hw_data.c new file mode 100644 index 00000000000..bda7443da79 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/hw_data.c @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * HW data initialization for OMAP4 + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Sricharan R + */ +#include +#include +#include +#include +#include +#include + +/* TPS */ +#define TPS62361_REG_ADDR_SET1 0x1 +#define TPS62361_VSEL0_GPIO 7 +#define TPS62361_BASE_VOLT_MV 500 + +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 + +struct prcm_regs const **prcm = (struct prcm_regs const **)OMAP_SRAM_SCRATCH_PRCM_PTR; +struct dplls const **dplls_data = (struct dplls const **)OMAP_SRAM_SCRATCH_DPLLS_PTR; +struct vcores_data const **omap_vcores = (struct vcores_data const **)OMAP_SRAM_SCRATCH_VCORES_PTR; +struct omap_sys_ctrl_regs const **ctrl = + (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; + +/* + * The M & N values in the following tables are created using the + * following tool: + * tools/omap/clocks_get_m_n.c + * Please use this tool for creating the table for any new frequency. + */ + +/* + * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF + * OMAP4460 OPP_NOM frequency + */ +static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { + {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* + * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) + * OMAP4430 OPP_TURBO frequency + * OMAP4470 OPP_NOM frequency + */ +static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* + * dpll locked at 1200 MHz - MPU clk at 600 MHz + * OMAP4430 OPP_NOM frequency + */ +static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { + {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OMAP4460 OPP_NOM frequency */ +/* OMAP4470 OPP_NOM (Low Power) frequency */ +static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OMAP4430 ES1 OPP_NOM frequency */ +static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { + {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OMAP4430 ES2.X OPP_NOM frequency */ +static const struct dpll_params + core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { + {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { + {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */ + {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */ + {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */ + {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */ + {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { + {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with 32K clock as source */ +static const struct dpll_params abe_dpll_params_32k_196608khz = { + 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 +}; + +static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { + {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +struct dplls omap4430_dplls_es1 = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_es1_1524mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, + .abe = &abe_dpll_params_32k_196608khz, + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4430_dplls_es20 = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_es2_1600mhz_ddr200mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, + .abe = &abe_dpll_params_32k_196608khz, + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4430_dplls = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, + .abe = &abe_dpll_params_32k_196608khz, + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4460_dplls = { + .mpu = mpu_dpll_params_1400mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, + .abe = &abe_dpll_params_32k_196608khz, + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4470_dplls = { + .mpu = mpu_dpll_params_1600mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, + .abe = &abe_dpll_params_32k_196608khz, + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct pmic_data twl6030_4430es1 = { + .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, + .step = 12660, /* 12.66 mV represented in uV */ + /* The code starts at 1 not 0 */ + .start_code = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, +}; + +/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */ +struct pmic_data twl6030 = { + .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, + .step = 12660, /* 12.66 mV represented in uV */ + /* The code starts at 1 not 0 */ + .start_code = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, +}; + +struct pmic_data tps62361 = { + .base_offset = TPS62361_BASE_VOLT_MV, + .step = 10000, /* 10 mV represented in uV */ + .start_code = 0, + .gpio = TPS62361_VSEL0_GPIO, + .gpio_en = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, +}; + +struct vcores_data omap4430_volts_es1 = { + .mpu.value[OPP_NOM] = 1325, + .mpu.addr = SMPS_REG_ADDR_VCORE1, + .mpu.pmic = &twl6030_4430es1, + + .core.value[OPP_NOM] = 1200, + .core.addr = SMPS_REG_ADDR_VCORE3, + .core.pmic = &twl6030_4430es1, + + .mm.value[OPP_NOM] = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030_4430es1, +}; + +struct vcores_data omap4430_volts = { + .mpu.value[OPP_NOM] = 1325, + .mpu.addr = SMPS_REG_ADDR_VCORE1, + .mpu.pmic = &twl6030, + + .core.value[OPP_NOM] = 1200, + .core.addr = SMPS_REG_ADDR_VCORE3, + .core.pmic = &twl6030, + + .mm.value[OPP_NOM] = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030, +}; + +struct vcores_data omap4460_volts = { + .mpu.value[OPP_NOM] = 1203, + .mpu.addr = TPS62361_REG_ADDR_SET1, + .mpu.pmic = &tps62361, + + .core.value[OPP_NOM] = 1200, + .core.addr = SMPS_REG_ADDR_VCORE1, + .core.pmic = &twl6030, + + .mm.value[OPP_NOM] = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030, +}; + +/* + * Take closest integer part of the mV value corresponding to a TWL6032 SMPS + * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7. + */ +struct vcores_data omap4470_volts = { + .mpu.value[OPP_NOM] = 1202, + .mpu.addr = SMPS_REG_ADDR_SMPS1, + .mpu.pmic = &twl6030, + + .core.value[OPP_NOM] = 1126, + .core.addr = SMPS_REG_ADDR_SMPS2, + .core.pmic = &twl6030, + + .mm.value[OPP_NOM] = 1139, + .mm.addr = SMPS_REG_ADDR_SMPS5, + .mm.pmic = &twl6030, +}; + +/* + * Enable essential clock domains, modules and + * do some additional special settings needed + */ +void enable_basic_clocks(void) +{ + u32 const clk_domains_essential[] = { + (*prcm)->cm_l4per_clkstctrl, + (*prcm)->cm_l3init_clkstctrl, + (*prcm)->cm_memif_clkstctrl, + (*prcm)->cm_l4cfg_clkstctrl, + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3_gpmc_clkctrl, + (*prcm)->cm_memif_emif_1_clkctrl, + (*prcm)->cm_memif_emif_2_clkctrl, + (*prcm)->cm_l4cfg_l4_cfg_clkctrl, + (*prcm)->cm_wkup_gpio1_clkctrl, + (*prcm)->cm_l4per_gpio2_clkctrl, + (*prcm)->cm_l4per_gpio3_clkctrl, + (*prcm)->cm_l4per_gpio4_clkctrl, + (*prcm)->cm_l4per_gpio5_clkctrl, + (*prcm)->cm_l4per_gpio6_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_wkup_gptimer1_clkctrl, + (*prcm)->cm_l3init_hsmmc1_clkctrl, + (*prcm)->cm_l3init_hsmmc2_clkctrl, + (*prcm)->cm_l4per_gptimer2_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_l4per_uart3_clkctrl, + (*prcm)->cm_l4per_i2c1_clkctrl, + (*prcm)->cm_l4per_i2c2_clkctrl, + (*prcm)->cm_l4per_i2c3_clkctrl, + (*prcm)->cm_l4per_i2c4_clkctrl, + 0 + }; + + /* Enable optional additional functional clock for GPIO4 */ + setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, GPIO4_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable 96 MHz clock for MMC1 & MMC2 */ + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); + + /* Select 32KHz clock as the source of GPTIMER1 */ + setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, GPTIMER1_CLKCTRL_CLKSEL_MASK); + + /* Enable optional 48M functional clock for USB PHY */ + setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); + + /* Enable 32 KHz clock for USB PHY */ + setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +void enable_basic_uboot_clocks(void) +{ + u32 const clk_domains_essential[] = { + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3init_hsusbotg_clkctrl, + (*prcm)->cm_l3init_usbphy_clkctrl, + (*prcm)->cm_clksel_usb_60mhz, + (*prcm)->cm_l3init_hsusbtll_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_l4per_mcspi1_clkctrl, + (*prcm)->cm_l3init_hsusbhost_clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +void hw_data_init(void) +{ + u32 omap_rev = omap_revision(); + + (*prcm) = &omap4_prcm; + + switch (omap_rev) { + case OMAP4430_ES1_0: + *dplls_data = &omap4430_dplls_es1; + *omap_vcores = &omap4430_volts_es1; + break; + case OMAP4430_ES2_0: + *dplls_data = &omap4430_dplls_es20; + *omap_vcores = &omap4430_volts; + break; + case OMAP4430_ES2_1: + case OMAP4430_ES2_2: + case OMAP4430_ES2_3: + *dplls_data = &omap4430_dplls; + *omap_vcores = &omap4430_volts; + break; + case OMAP4460_ES1_0: + case OMAP4460_ES1_1: + *dplls_data = &omap4460_dplls; + *omap_vcores = &omap4460_volts; + break; + case OMAP4470_ES1_0: + *dplls_data = &omap4470_dplls; + *omap_vcores = &omap4470_volts; + break; + default: + printf("\n INVALID OMAP REVISION "); + } + + *ctrl = &omap4_ctrl; +} diff --git a/arch/arm/mach-omap2/omap4/hwinit.c b/arch/arm/mach-omap2/omap4/hwinit.c new file mode 100644 index 00000000000..9beecb8ad49 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/hwinit.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * Common functions for OMAP4 based boards + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Author : + * Aneesh V + * Steve Sakoman + */ +#include +#include +#include +#include +#include +#include +#include +#include + +u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; + +#if !CONFIG_IS_ENABLED(DM_GPIO) +static const struct gpio_bank gpio_bank_44xx[6] = { + { (void *)OMAP44XX_GPIO1_BASE }, + { (void *)OMAP44XX_GPIO2_BASE }, + { (void *)OMAP44XX_GPIO3_BASE }, + { (void *)OMAP44XX_GPIO4_BASE }, + { (void *)OMAP44XX_GPIO5_BASE }, + { (void *)OMAP44XX_GPIO6_BASE }, +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; +#endif + +/* + * Some tuning of IOs for optimal power and performance + */ +void do_io_settings(void) +{ + u32 omap4_rev = omap_revision(); + u32 lpddr2io; + + if (omap4_rev == OMAP4430_ES1_0) + lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN; + else if (omap4_rev == OMAP4430_ES2_0) + lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER; + else + lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN; + + /* EMIF1 */ + writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); + /* No pull for GR10 as per hw team's recommendation */ + writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, (*ctrl)->control_lpddr2io1_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3); + + /* EMIF2 */ + writel(lpddr2io, (*ctrl)->control_lpddr2io2_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io2_1); + /* No pull for GR10 as per hw team's recommendation */ + writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, (*ctrl)->control_lpddr2io2_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3); + + /* + * Some of these settings (TRIM values) come from eFuse and are + * in turn programmed in the eFuse at manufacturing time after + * calibration of the device. Do the software over-ride only if + * the device is not correctly trimmed + */ + if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) { + writel(LDOSRAM_VOLT_CTRL_OVERRIDE, + (*ctrl)->control_ldosram_iva_voltage_ctrl); + + writel(LDOSRAM_VOLT_CTRL_OVERRIDE, + (*ctrl)->control_ldosram_mpu_voltage_ctrl); + + writel(LDOSRAM_VOLT_CTRL_OVERRIDE, + (*ctrl)->control_ldosram_core_voltage_ctrl); + } + + /* + * Over-ride the register + * i. unconditionally for all 4430 + * ii. only if un-trimmed for 4460 + */ + if (!readl((*ctrl)->control_efuse_1)) + writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1); + + if (omap4_rev < OMAP4460_ES1_0 || !readl((*ctrl)->control_efuse_2)) + writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2); +} + +/* dummy function for omap4 */ +void config_data_eye_leveling_samples(u32 emif_base) +{ +} + +void init_omap_revision(void) +{ + /* + * For some of the ES2/ES1 boards ID_CODE is not reliable: + * Also, ES1 and ES2 have different ARM revisions + * So use ARM revision for identification + */ + unsigned int arm_rev = cortex_rev(); + + switch (arm_rev) { + case MIDR_CORTEX_A9_R0P1: + *omap_si_rev = OMAP4430_ES1_0; + break; + case MIDR_CORTEX_A9_R1P2: + switch (readl(CONTROL_ID_CODE)) { + case OMAP4_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP4430_ES2_0; + break; + case OMAP4_CONTROL_ID_CODE_ES2_1: + *omap_si_rev = OMAP4430_ES2_1; + break; + case OMAP4_CONTROL_ID_CODE_ES2_2: + *omap_si_rev = OMAP4430_ES2_2; + break; + default: + *omap_si_rev = OMAP4430_ES2_0; + break; + } + break; + case MIDR_CORTEX_A9_R1P3: + *omap_si_rev = OMAP4430_ES2_3; + break; + case MIDR_CORTEX_A9_R2P10: + switch (readl(CONTROL_ID_CODE)) { + case OMAP4470_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP4470_ES1_0; + break; + case OMAP4460_CONTROL_ID_CODE_ES1_1: + *omap_si_rev = OMAP4460_ES1_1; + break; + case OMAP4460_CONTROL_ID_CODE_ES1_0: + default: + *omap_si_rev = OMAP4460_ES1_0; + break; + } + break; + default: + *omap_si_rev = OMAP4430_SILICON_ID_INVALID; + break; + } +} + +void omap_die_id(unsigned int *die_id) +{ + die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); + die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1); + die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2); + die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); +} + +void v7_outer_cache_enable(void) +{ + if (!IS_ENABLED(CONFIG_SYS_L2CACHE_OFF)) + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1); +} + +void v7_outer_cache_disable(void) +{ + if (!IS_ENABLED(CONFIG_SYS_L2CACHE_OFF)) + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0); +} + +void vmmc_pbias_config(uint voltage) +{ + u32 value = 0; + + value = readl((*ctrl)->control_pbiaslite); + value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); + writel(value, (*ctrl)->control_pbiaslite); + value = readl((*ctrl)->control_pbiaslite); + value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; + writel(value, (*ctrl)->control_pbiaslite); +} diff --git a/arch/arm/mach-omap2/omap4/prcm-regs.c b/arch/arm/mach-omap2/omap4/prcm-regs.c new file mode 100644 index 00000000000..eaf98b38914 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/prcm-regs.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * HW regs data for OMAP4 + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Sricharan R + */ + +#include + +struct prcm_regs const omap4_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a004100, + .cm_clksel_abe = 0x4a004108, + .cm_dll_ctrl = 0x4a004110, + .cm_clkmode_dpll_core = 0x4a004120, + .cm_idlest_dpll_core = 0x4a004124, + .cm_autoidle_dpll_core = 0x4a004128, + .cm_clksel_dpll_core = 0x4a00412c, + .cm_div_m2_dpll_core = 0x4a004130, + .cm_div_m3_dpll_core = 0x4a004134, + .cm_div_m4_dpll_core = 0x4a004138, + .cm_div_m5_dpll_core = 0x4a00413c, + .cm_div_m6_dpll_core = 0x4a004140, + .cm_div_m7_dpll_core = 0x4a004144, + .cm_ssc_deltamstep_dpll_core = 0x4a004148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, + .cm_emu_override_dpll_core = 0x4a004150, + .cm_clkmode_dpll_mpu = 0x4a004160, + .cm_idlest_dpll_mpu = 0x4a004164, + .cm_autoidle_dpll_mpu = 0x4a004168, + .cm_clksel_dpll_mpu = 0x4a00416c, + .cm_div_m2_dpll_mpu = 0x4a004170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, + .cm_bypclk_dpll_mpu = 0x4a00419c, + .cm_clkmode_dpll_iva = 0x4a0041a0, + .cm_idlest_dpll_iva = 0x4a0041a4, + .cm_autoidle_dpll_iva = 0x4a0041a8, + .cm_clksel_dpll_iva = 0x4a0041ac, + .cm_div_m4_dpll_iva = 0x4a0041b8, + .cm_div_m5_dpll_iva = 0x4a0041bc, + .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, + .cm_bypclk_dpll_iva = 0x4a0041dc, + .cm_clkmode_dpll_abe = 0x4a0041e0, + .cm_idlest_dpll_abe = 0x4a0041e4, + .cm_autoidle_dpll_abe = 0x4a0041e8, + .cm_clksel_dpll_abe = 0x4a0041ec, + .cm_div_m2_dpll_abe = 0x4a0041f0, + .cm_div_m3_dpll_abe = 0x4a0041f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a004208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, + .cm_clkmode_dpll_ddrphy = 0x4a004220, + .cm_idlest_dpll_ddrphy = 0x4a004224, + .cm_autoidle_dpll_ddrphy = 0x4a004228, + .cm_clksel_dpll_ddrphy = 0x4a00422c, + .cm_div_m2_dpll_ddrphy = 0x4a004230, + .cm_div_m4_dpll_ddrphy = 0x4a004238, + .cm_div_m5_dpll_ddrphy = 0x4a00423c, + .cm_div_m6_dpll_ddrphy = 0x4a004240, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, + .cm_shadow_freq_config1 = 0x4a004260, + .cm_mpu_mpu_clkctrl = 0x4a004320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a004400, + .cm_dsp_dsp_clkctrl = 0x4a004420, + + /* cm1.abe */ + .cm1_abe_clkstctrl = 0x4a004500, + .cm1_abe_l4abe_clkctrl = 0x4a004520, + .cm1_abe_aess_clkctrl = 0x4a004528, + .cm1_abe_pdm_clkctrl = 0x4a004530, + .cm1_abe_dmic_clkctrl = 0x4a004538, + .cm1_abe_mcasp_clkctrl = 0x4a004540, + .cm1_abe_mcbsp1_clkctrl = 0x4a004548, + .cm1_abe_mcbsp2_clkctrl = 0x4a004550, + .cm1_abe_mcbsp3_clkctrl = 0x4a004558, + .cm1_abe_slimbus_clkctrl = 0x4a004560, + .cm1_abe_timer5_clkctrl = 0x4a004568, + .cm1_abe_timer6_clkctrl = 0x4a004570, + .cm1_abe_timer7_clkctrl = 0x4a004578, + .cm1_abe_timer8_clkctrl = 0x4a004580, + .cm1_abe_wdt3_clkctrl = 0x4a004588, + + /* cm2.ckgen */ + .cm_clksel_mpu_m3_iss_root = 0x4a008100, + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_scale_fclk = 0x4a008108, + .cm_core_dvfs_perf1 = 0x4a008110, + .cm_core_dvfs_perf2 = 0x4a008114, + .cm_core_dvfs_perf3 = 0x4a008118, + .cm_core_dvfs_perf4 = 0x4a00811c, + .cm_core_dvfs_current = 0x4a008124, + .cm_iva_dvfs_perf_tesla = 0x4a008128, + .cm_iva_dvfs_perf_ivahd = 0x4a00812c, + .cm_iva_dvfs_perf_abe = 0x4a008130, + .cm_iva_dvfs_current = 0x4a008138, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_m4_dpll_per = 0x4a008158, + .cm_div_m5_dpll_per = 0x4a00815c, + .cm_div_m6_dpll_per = 0x4a008160, + .cm_div_m7_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_emu_override_dpll_per = 0x4a008170, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_unipro = 0x4a0081c0, + .cm_idlest_dpll_unipro = 0x4a0081c4, + .cm_autoidle_dpll_unipro = 0x4a0081c8, + .cm_clksel_dpll_unipro = 0x4a0081cc, + .cm_div_m2_dpll_unipro = 0x4a0081d0, + .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, + .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, + + /* cm2.core */ + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_2_clkstctrl = 0x4a008800, + .cm_l3_2_dynamicdep = 0x4a008808, + .cm_l3_2_l3_2_clkctrl = 0x4a008820, + .cm_l3_gpmc_clkctrl = 0x4a008828, + .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_memif_emif_h1_clkctrl = 0x4a008b50, + .cm_memif_emif_h2_clkctrl = 0x4a008b58, + .cm_memif_dll_h_clkctrl = 0x4a008b60, + .cm_c2c_clkstctrl = 0x4a008c00, + .cm_c2c_staticdep = 0x4a008c04, + .cm_c2c_dynamicdep = 0x4a008c08, + .cm_c2c_sad2d_clkctrl = 0x4a008c20, + .cm_c2c_modem_icr_clkctrl = 0x4a008c28, + .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkct = 0x4a008e40, + .cm_ivahd_clkstctrl = 0x4a008f00, + + /* cm2.ivahd */ + .cm_ivahd_ivahd_clkctrl = 0x4a008f20, + .cm_ivahd_sl2_clkctrl = 0x4a008f28, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009000, + .cm_cam_iss_clkctrl = 0x4a009020, + .cm_cam_fdif_clkctrl = 0x4a009028, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009100, + .cm_dss_dss_clkctrl = 0x4a009120, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009200, + .cm_sgx_sgx_clkctrl = 0x4a009220, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009300, + .cm_l3init_hsmmc1_clkctrl = 0x4a009328, + .cm_l3init_hsmmc2_clkctrl = 0x4a009330, + .cm_l3init_hsi_clkctrl = 0x4a009338, + .cm_l3init_hsusbhost_clkctrl = 0x4a009358, + .cm_l3init_hsusbotg_clkctrl = 0x4a009360, + .cm_l3init_hsusbtll_clkctrl = 0x4a009368, + .cm_l3init_p1500_clkctrl = 0x4a009378, + .cm_l3init_fsusb_clkctrl = 0x4a0093d0, + .cm_l3init_usbphy_clkctrl = 0x4a0093e0, + + /* cm2.l4per */ + .cm_l4per_clkstctrl = 0x4a009400, + .cm_l4per_dynamicdep = 0x4a009408, + .cm_l4per_adc_clkctrl = 0x4a009420, + .cm_l4per_gptimer10_clkctrl = 0x4a009428, + .cm_l4per_gptimer11_clkctrl = 0x4a009430, + .cm_l4per_gptimer2_clkctrl = 0x4a009438, + .cm_l4per_gptimer3_clkctrl = 0x4a009440, + .cm_l4per_gptimer4_clkctrl = 0x4a009448, + .cm_l4per_gptimer9_clkctrl = 0x4a009450, + .cm_l4per_elm_clkctrl = 0x4a009458, + .cm_l4per_gpio2_clkctrl = 0x4a009460, + .cm_l4per_gpio3_clkctrl = 0x4a009468, + .cm_l4per_gpio4_clkctrl = 0x4a009470, + .cm_l4per_gpio5_clkctrl = 0x4a009478, + .cm_l4per_gpio6_clkctrl = 0x4a009480, + .cm_l4per_hdq1w_clkctrl = 0x4a009488, + .cm_l4per_hecc1_clkctrl = 0x4a009490, + .cm_l4per_hecc2_clkctrl = 0x4a009498, + .cm_l4per_i2c1_clkctrl = 0x4a0094a0, + .cm_l4per_i2c2_clkctrl = 0x4a0094a8, + .cm_l4per_i2c3_clkctrl = 0x4a0094b0, + .cm_l4per_i2c4_clkctrl = 0x4a0094b8, + .cm_l4per_l4per_clkctrl = 0x4a0094c0, + .cm_l4per_mcasp2_clkctrl = 0x4a0094d0, + .cm_l4per_mcasp3_clkctrl = 0x4a0094d8, + .cm_l4per_mcbsp4_clkctrl = 0x4a0094e0, + .cm_l4per_mgate_clkctrl = 0x4a0094e8, + .cm_l4per_mcspi1_clkctrl = 0x4a0094f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0094f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009500, + .cm_l4per_mcspi4_clkctrl = 0x4a009508, + .cm_l4per_mmcsd3_clkctrl = 0x4a009520, + .cm_l4per_mmcsd4_clkctrl = 0x4a009528, + .cm_l4per_msprohg_clkctrl = 0x4a009530, + .cm_l4per_slimbus2_clkctrl = 0x4a009538, + .cm_l4per_uart1_clkctrl = 0x4a009540, + .cm_l4per_uart2_clkctrl = 0x4a009548, + .cm_l4per_uart3_clkctrl = 0x4a009550, + .cm_l4per_uart4_clkctrl = 0x4a009558, + .cm_l4per_mmcsd5_clkctrl = 0x4a009560, + .cm_l4per_i2c5_clkctrl = 0x4a009568, + .cm_l4sec_clkstctrl = 0x4a009580, + .cm_l4sec_staticdep = 0x4a009584, + .cm_l4sec_dynamicdep = 0x4a009588, + .cm_l4sec_aes1_clkctrl = 0x4a0095a0, + .cm_l4sec_aes2_clkctrl = 0x4a0095a8, + .cm_l4sec_des3des_clkctrl = 0x4a0095b0, + .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8, + .cm_l4sec_rng_clkctrl = 0x4a0095c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4a30610c, + .cm_sys_clksel = 0x4a306110, + .cm_wkup_clkstctrl = 0x4a307800, + .cm_wkup_l4wkup_clkctrl = 0x4a307820, + .cm_wkup_wdtimer1_clkctrl = 0x4a307828, + .cm_wkup_wdtimer2_clkctrl = 0x4a307830, + .cm_wkup_gpio1_clkctrl = 0x4a307838, + .cm_wkup_gptimer1_clkctrl = 0x4a307840, + .cm_wkup_gptimer12_clkctrl = 0x4a307848, + .cm_wkup_synctimer_clkctrl = 0x4a307850, + .cm_wkup_usim_clkctrl = 0x4a307858, + .cm_wkup_sarram_clkctrl = 0x4a307860, + .cm_wkup_keyboard_clkctrl = 0x4a307878, + .cm_wkup_rtc_clkctrl = 0x4a307880, + .cm_wkup_bandgap_clkctrl = 0x4a307888, + .prm_vc_val_bypass = 0x4a307ba0, + .prm_vc_cfg_channel = 0x4a307ba4, + .prm_vc_cfg_i2c_mode = 0x4a307ba8, + .prm_vc_cfg_i2c_clk = 0x4a307bac, +}; + +struct omap_sys_ctrl_regs const omap4_ctrl = { + .control_status = 0x4A0022C4, + .control_std_fuse_die_id_0 = 0x4A002200, + .control_std_fuse_die_id_1 = 0x4A002208, + .control_std_fuse_die_id_2 = 0x4A00220C, + .control_std_fuse_die_id_3 = 0x4A002210, + .control_std_fuse_opp_bgap = 0x4a002260, + .control_status = 0x4a0022c4, + .control_ldosram_iva_voltage_ctrl = 0x4A002320, + .control_ldosram_mpu_voltage_ctrl = 0x4A002324, + .control_ldosram_core_voltage_ctrl = 0x4A002328, + .control_usbotghs_ctrl = 0x4A00233C, + .control_padconf_core_base = 0x4A100000, + .control_pbiaslite = 0x4A100600, + .control_lpddr2io1_0 = 0x4A100638, + .control_lpddr2io1_1 = 0x4A10063C, + .control_lpddr2io1_2 = 0x4A100640, + .control_lpddr2io1_3 = 0x4A100644, + .control_lpddr2io2_0 = 0x4A100648, + .control_lpddr2io2_1 = 0x4A10064C, + .control_lpddr2io2_2 = 0x4A100650, + .control_lpddr2io2_3 = 0x4A100654, + .control_efuse_1 = 0x4A100700, + .control_efuse_2 = 0x4A100704, + .control_padconf_wkup_base = 0x4A31E000, +}; diff --git a/arch/arm/mach-omap2/omap4/sdram_elpida.c b/arch/arm/mach-omap2/omap4/sdram_elpida.c new file mode 100644 index 00000000000..b2bac429a85 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/sdram_elpida.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Timing and Organization details of the Elpida parts used in OMAP4 + * SDPs and Panda + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + */ + +#include +#include + +/* + * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430 + * SDP and Panda. Since the parts used and geometry are identical for + * SDP and Panda for a given OMAP4 revision, this information is kept + * here instead of being in board directory. However the key functions + * exported are weakly linked so that they can be over-ridden in the board + * directory if there is a OMAP4 board in the future that uses a different + * memory device or geometry. + * + * For any new board with different memory devices over-ride one or more + * of the following functions as per the CONFIG flags you intend to enable: + * - emif_get_reg_dump() + * - emif_get_dmm_regs() + * - emif_get_device_details() + * - emif_get_device_timings() + */ + +const struct emif_regs emif_regs_elpida_200_mhz_2cs = { + .sdram_config_init = 0x80000eb9, + .sdram_config = 0x80001ab9, + .ref_ctrl = 0x0000030c, + .sdram_tim1 = 0x08648311, + .sdram_tim2 = 0x101b06ca, + .sdram_tim3 = 0x0048a19f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3214, + .temp_alert_config = 0xd8016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff808 +}; + +const struct emif_regs emif_regs_elpida_380_mhz_1cs = { + .sdram_config_init = 0x80000eb1, + .sdram_config = 0x80001ab1, + .ref_ctrl = 0x000005cd, + .sdram_tim1 = 0x10cb0622, + .sdram_tim2 = 0x20350d52, + .sdram_tim3 = 0x00b1431f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3214, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +const struct emif_regs emif_regs_elpida_400_mhz_1cs = { + .sdram_config_init = 0x80800eb2, + .sdram_config = 0x80801ab2, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3215, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +const struct emif_regs emif_regs_elpida_400_mhz_2cs = { + .sdram_config_init = 0x80000eb9, + .sdram_config = 0x80001ab9, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0xd00b3214, + .temp_alert_config = 0xd8016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80540300, + .is_ma_present = 0x0 +}; + +const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x0 +}; + +const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x1 +}; + +__weak void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + u32 omap4_rev = omap_revision(); + + /* Same devices and geometry on both EMIFs */ + if (omap4_rev == OMAP4430_ES1_0) + *regs = &emif_regs_elpida_380_mhz_1cs; + else if (omap4_rev == OMAP4430_ES2_0) + *regs = &emif_regs_elpida_200_mhz_2cs; + else if (omap4_rev < OMAP4470_ES1_0) + *regs = &emif_regs_elpida_400_mhz_2cs; + else + *regs = &emif_regs_elpida_400_mhz_1cs; +} + +__weak void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + u32 omap_rev = omap_revision(); + + if (omap_rev == OMAP4430_ES1_0) + *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; + else if (omap_rev < OMAP4460_ES1_0) + *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; + else + *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2; +} + +static const struct lpddr2_ac_timings timings_elpida_400_mhz = { + .max_freq = 400000000, + .RL = 6, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_ac_timings timings_elpida_333_mhz = { + .max_freq = 333000000, + .RL = 5, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_ac_timings timings_elpida_200_mhz = { + .max_freq = 200000000, + .RL = 3, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 20, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_min_tck min_tck_elpida = { + .tRL = 3, + .tRP_AB = 3, + .tRCD = 3, + .tWR = 3, + .tRAS_MIN = 3, + .tRRD = 2, + .tWTR = 2, + .tXP = 2, + .tRTP = 2, + .tCKE = 3, + .tCKESR = 3, + .tFAW = 8 +}; + +static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = { + &timings_elpida_200_mhz, + &timings_elpida_333_mhz, + &timings_elpida_400_mhz +}; + +const struct lpddr2_device_timings elpida_2G_S4_timings = { + .ac_timings = elpida_ac_timings, + .min_tck = &min_tck_elpida, +}; + +__weak void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) +{ + u32 omap_rev = omap_revision(); + + /* Identical devices on EMIF1 & EMIF2 */ + *cs0_device_timings = &elpida_2G_S4_timings; + + if (omap_rev == OMAP4430_ES1_0 || omap_rev == OMAP4470_ES1_0) + *cs1_device_timings = NULL; + else + *cs1_device_timings = &elpida_2G_S4_timings; +} + +const struct lpddr2_mr_regs mr_regs = { + .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3, + .mr2 = 0x4, + .mr3 = -1, + .mr10 = MR10_ZQ_ZQINIT, + .mr16 = MR16_REF_FULL_ARRAY +}; + +void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) +{ + *regs = &mr_regs; +} + +__weak const struct read_write_regs *get_bug_regs(u32 *iterations) +{ + return 0; +} diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 5fa94098e49..295dcf97898 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -541,7 +541,7 @@ config SPL_SYS_MMCSD_RAW_MODE ARCH_MX6 || ARCH_MX7 || \ ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA_GEN5 || \ ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ - OMAP54XX || AM33XX || AM43XX || \ + OMAP44XX || OMAP54XX || AM33XX || AM43XX || \ TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED help Support booting from an MMC without a filesystem. @@ -585,7 +585,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR default 0x100 if ARCH_UNIPHIER default 0x0 if ARCH_MVEBU default 0x200 if ARCH_SOCFPGA_GEN5 || ARCH_AT91 - default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ + default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \ OMAP54XX || AM33XX || AM43XX || ARCH_K3 default 0x4000 if ARCH_ROCKCHIP default 0x822 if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 55465dc1d46..73ffbb33871 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -800,7 +800,7 @@ config SYS_I2C_BUS_MAX int "Max I2C busses" depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA default 3 if OMAP34XX || AM33XX || AM43XX - default 4 if ARCH_SOCFPGA + default 4 if ARCH_SOCFPGA || OMAP44XX default 5 if OMAP54XX help Define the maximum number of available I2C buses. diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 22bd3a972bd..eb7661bc648 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -415,7 +415,7 @@ config MMC_OMAP36XX_PINS config HSMMC2_8BIT bool "Enable 8-bit interface for eMMC (interface #2)" - depends on MMC_OMAP_HS && (OMAP54XX || DRA7XX || AM33XX || \ + depends on MMC_OMAP_HS && (OMAP44XX || OMAP54XX || DRA7XX || AM33XX || \ AM43XX || ARCH_KEYSTONE) config SH_MMCIF -- cgit v1.3.1 From 0bef438428ca0118da2ebb44493d5d2090cb05a2 Mon Sep 17 00:00:00 2001 From: Naveen Kumar Chaudhary Date: Sun, 7 Jun 2026 21:03:43 +0530 Subject: serial: cortina: check RX FIFO status before reading data ca_serial_getc() reads from the URX_DATA register unconditionally without first checking whether the RX FIFO contains valid data. When the FIFO is empty, this returns whatever stale value is in the register, which the DM serial framework interprets as a valid character. The DM serial framework expects getc() to return -EAGAIN when no data is available, so it can handle retries and call schedule() to service the watchdog between attempts. Add a check of the UINFO register's UINFO_RX_FIFO_EMPTY bit before reading URX_DATA, returning -EAGAIN when no data is pending. This is consistent with how ca_serial_putc() already checks UINFO_TX_FIFO_FULL before writing. Signed-off-by: Naveen Kumar Chaudhary --- drivers/serial/serial_cortina.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_cortina.c b/drivers/serial/serial_cortina.c index 3ae8fb46584..de8af5b0574 100644 --- a/drivers/serial/serial_cortina.c +++ b/drivers/serial/serial_cortina.c @@ -83,11 +83,13 @@ int ca_serial_setbrg(struct udevice *dev, int baudrate) static int ca_serial_getc(struct udevice *dev) { struct ca_uart_priv *priv = dev_get_priv(dev); - int ch; + unsigned int status; - ch = readl(priv->base + URX_DATA) & 0xFF; + status = readl(priv->base + UINFO); + if (status & UINFO_RX_FIFO_EMPTY) + return -EAGAIN; - return (int)ch; + return readl(priv->base + URX_DATA) & 0xFF; } static int ca_serial_putc(struct udevice *dev, const char ch) -- cgit v1.3.1 From d73aed0b0571828c7ee308adcb1bb1145892dfd1 Mon Sep 17 00:00:00 2001 From: Naveen Kumar Chaudhary Date: Sun, 7 Jun 2026 21:15:42 +0530 Subject: serial: goldfish: return error when device address is invalid goldfish_serial_of_to_plat() returns success even when dev_read_addr() fails to find a valid address. This leaves plat->reg unset and defers the failure to probe(). Return -EINVAL immediately when the address is FDT_ADDR_T_NONE so the failure is reported at the of_to_plat stage where it belongs. Signed-off-by: Naveen Kumar Chaudhary Acked-by: Kuan-Wei Chiu --- drivers/serial/serial_goldfish.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_goldfish.c b/drivers/serial/serial_goldfish.c index 91dc040fcf2..732f167caae 100644 --- a/drivers/serial/serial_goldfish.c +++ b/drivers/serial/serial_goldfish.c @@ -74,8 +74,10 @@ static int goldfish_serial_of_to_plat(struct udevice *dev) fdt_addr_t addr; addr = dev_read_addr(dev); - if (addr != FDT_ADDR_T_NONE) - plat->reg = addr; + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->reg = addr; return 0; } -- cgit v1.3.1 From 2bc9c58e7f09e5c5383ad63f85f35b686d63c0bf Mon Sep 17 00:00:00 2001 From: Kuan-Wei Chiu Date: Mon, 8 Jun 2026 15:47:48 +0000 Subject: timer: goldfish: Return error when device address is invalid goldfish_timer_of_to_plat() currently returns success even when dev_read_addr() fails to find a valid address. This leaves plat->reg unset and defers the failure to probe(). Return -EINVAL immediately when the address is FDT_ADDR_T_NONE so the failure is reported at the of_to_plat stage where it belongs. This aligns the driver with the recent fix introduced in the goldfish serial driver by Naveen Kumar Chaudhary. [1] Link: https://lore.kernel.org/u-boot/vgwnt6mnls3lf3zdm6mz5siztzkvppte4ykszbvifjzukvmksf@maaxe5agqpim/ [1] Signed-off-by: Kuan-Wei Chiu --- drivers/timer/goldfish_timer.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/timer/goldfish_timer.c b/drivers/timer/goldfish_timer.c index 91277d7932a..59ce43fcb46 100644 --- a/drivers/timer/goldfish_timer.c +++ b/drivers/timer/goldfish_timer.c @@ -45,8 +45,10 @@ static int goldfish_timer_of_to_plat(struct udevice *dev) fdt_addr_t addr; addr = dev_read_addr(dev); - if (addr != FDT_ADDR_T_NONE) - plat->reg = addr; + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->reg = addr; return 0; } -- cgit v1.3.1 From 47e9c542ee032e89f556adc73c2aeff3acb0e5a9 Mon Sep 17 00:00:00 2001 From: Kuan-Wei Chiu Date: Mon, 8 Jun 2026 15:47:49 +0000 Subject: rtc: goldfish: Return error when device address is invalid goldfish_rtc_of_to_plat() currently returns success even when dev_read_addr() fails to find a valid address. This leaves plat->reg unset (or 0) and defers the failure to probe(). Return -EINVAL immediately when the address is FDT_ADDR_T_NONE so the failure is reported at the of_to_plat stage where it belongs. This aligns the driver with the recent fix introduced in the goldfish serial driver by Naveen Kumar Chaudhary. [1] Link: https://lore.kernel.org/u-boot/vgwnt6mnls3lf3zdm6mz5siztzkvppte4ykszbvifjzukvmksf@maaxe5agqpim/ [1] Signed-off-by: Kuan-Wei Chiu --- drivers/rtc/goldfish_rtc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/goldfish_rtc.c b/drivers/rtc/goldfish_rtc.c index 4892a63f8d8..652eec7dd0c 100644 --- a/drivers/rtc/goldfish_rtc.c +++ b/drivers/rtc/goldfish_rtc.c @@ -80,9 +80,13 @@ static int goldfish_rtc_of_to_plat(struct udevice *dev) struct goldfish_rtc_plat *plat = dev_get_plat(dev); fdt_addr_t addr; + plat->reg = 0; + addr = dev_read_addr(dev); - if (addr != FDT_ADDR_T_NONE) - plat->reg = addr; + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->reg = addr; return 0; } -- cgit v1.3.1 From 1174c99ab421168221be372bd83a4143bf5f167d Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Wed, 17 Jun 2026 10:48:19 +0300 Subject: treewide: move bi_dram[] from bd to gd Currently, the bi_dram[] information is stored in the board info structure (bd). Because bd is only valid after reserve_board(), dram_init_banksize() must be called late in the initialization process. This limitation is problematic, as it forces us to rely on a variety of bespoke functions to determine board RAM, bank memory sizes, and other early setup requirements. By moving bi_dram[] into the global data (gd), we can run it earlier. This is particularly convenient since boards define their own dram_init_banksize() routines, which do not always rely on parsing Device Tree (DT) memory nodes. Additionally, U-Boot defaults to relocating to the top of the first memory bank. While boards currently use custom functions to override this behavior, having the DRAM bank information available earlier in gd makes relocating to a different bank trivial and standardizes the process. Reviewed-by: Anshul Dalal Tested-by: Michal Simek # Versal Gen 2 Vek385 Tested-by: Anshul Dalal Reviewed-by: Simon Glass Signed-off-by: Ilias Apalodimas Tested-by: Christophe Leroy (CS GROUP) --- api/api_platform.c | 4 +- arch/arm/cpu/armv8/cache_v8.c | 6 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 118 ++++++++++----------- arch/arm/lib/bootm-fdt.c | 5 +- arch/arm/lib/bootm.c | 4 +- arch/arm/lib/cache-cp15.c | 9 +- arch/arm/lib/image.c | 2 +- arch/arm/mach-airoha/an7581/init.c | 8 +- arch/arm/mach-apple/board.c | 4 +- arch/arm/mach-davinci/misc.c | 4 +- arch/arm/mach-imx/ele_ahab.c | 7 +- arch/arm/mach-imx/imx8/ahab.c | 7 +- arch/arm/mach-imx/imx8/cpu.c | 44 ++++---- arch/arm/mach-imx/imx8m/soc.c | 24 ++--- arch/arm/mach-imx/imx8ulp/soc.c | 20 ++-- arch/arm/mach-imx/imx9/scmi/soc.c | 24 ++--- arch/arm/mach-imx/imx9/soc.c | 24 ++--- arch/arm/mach-imx/mx5/mx53_dram.c | 8 +- arch/arm/mach-imx/spl.c | 4 +- arch/arm/mach-k3/k3-ddr.c | 4 +- arch/arm/mach-mvebu/alleycat5/cpu.c | 4 +- arch/arm/mach-mvebu/armada3700/cpu.c | 10 +- arch/arm/mach-mvebu/armada8k/dram.c | 10 +- arch/arm/mach-mvebu/dram.c | 6 +- arch/arm/mach-omap2/am33xx/board.c | 4 +- arch/arm/mach-omap2/omap-cache.c | 5 +- arch/arm/mach-omap2/omap3/emif4.c | 8 +- arch/arm/mach-omap2/omap3/sdrc.c | 8 +- arch/arm/mach-owl/soc.c | 4 +- arch/arm/mach-renesas/memmap-gen3.c | 8 +- arch/arm/mach-renesas/memmap-rzg2l.c | 4 +- arch/arm/mach-rockchip/rk3588/rk3588.c | 8 +- arch/arm/mach-rockchip/sdram.c | 42 ++++---- arch/arm/mach-snapdragon/board.c | 16 +-- arch/arm/mach-socfpga/board.c | 5 +- arch/arm/mach-socfpga/misc_arria10.c | 7 +- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 +- arch/arm/mach-stm32mp/stm32mp1/cpu.c | 7 +- arch/arm/mach-tegra/board2.c | 14 +-- arch/arm/mach-tegra/cboot.c | 4 +- arch/arm/mach-uniphier/dram_init.c | 6 +- arch/arm/mach-uniphier/fdt-fixup.c | 8 +- arch/arm/mach-versal-net/cpu.c | 8 +- arch/arm/mach-versal/cpu.c | 16 +-- arch/arm/mach-versal2/cpu.c | 7 +- arch/arm/mach-zynqmp/cpu.c | 8 +- arch/mips/mach-octeon/dram.c | 4 +- arch/riscv/cpu/k1/dram.c | 12 +-- arch/sandbox/cpu/spl.c | 4 +- arch/x86/cpu/coreboot/sdram.c | 4 +- arch/x86/cpu/efi/payload.c | 4 +- arch/x86/cpu/efi/sdram.c | 4 +- arch/x86/cpu/intel_common/mrc.c | 4 +- arch/x86/cpu/ivybridge/sdram_nop.c | 4 +- arch/x86/cpu/qemu/dram.c | 8 +- arch/x86/cpu/quark/dram.c | 4 +- arch/x86/cpu/slimbootloader/sdram.c | 4 +- arch/x86/cpu/tangier/sdram.c | 4 +- arch/x86/lib/bootm.c | 5 +- arch/x86/lib/fsp/fsp_dram.c | 18 ++-- board/CZ.NIC/turris_1x/turris_1x.c | 42 ++++---- board/armltd/corstone1000/corstone1000.c | 4 +- board/armltd/integrator/integrator.c | 4 +- board/armltd/total_compute/total_compute.c | 6 +- board/armltd/vexpress/vexpress_common.c | 8 +- board/atmel/common/video_display.c | 2 +- board/atmel/sam9x60_curiosity/sam9x60_curiosity.c | 2 +- board/atmel/sam9x75_curiosity/sam9x75_curiosity.c | 2 +- board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c | 2 +- .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 2 +- .../atmel/sama5d29_curiosity/sama5d29_curiosity.c | 2 +- board/atmel/sama5d2_xplained/sama5d2_xplained.c | 2 +- .../atmel/sama7d65_curiosity/sama7d65_curiosity.c | 2 +- .../atmel/sama7g54_curiosity/sama7g54_curiosity.c | 2 +- board/axiado/scm3005/scm3005.c | 4 +- board/broadcom/bcmns3/ns3.c | 4 +- board/compulab/cm_fx6/cm_fx6.c | 28 ++--- board/elgin/elgin_rv1108/elgin_rv1108.c | 4 +- board/esd/meesc/meesc.c | 4 +- board/friendlyarm/nanopi2/board.c | 10 +- board/ge/mx53ppd/mx53ppd.c | 8 +- board/hisilicon/hikey/hikey.c | 24 ++--- board/hisilicon/hikey960/hikey960.c | 4 +- board/hisilicon/poplar/poplar.c | 4 +- board/k+p/kp_imx53/kp_imx53.c | 4 +- board/keymile/pg-wcom-ls102xa/ddr.c | 4 +- board/kontron/sl28/sl28.c | 4 +- board/kontron/sl28/spl_atf.c | 6 +- board/liebherr/btt/btt.c | 2 +- board/menlo/m53menlo/m53menlo.c | 8 +- board/nuvoton/arbel_evb/arbel_evb.c | 26 ++--- board/nxp/imxrt1020-evk/imxrt1020-evk.c | 2 +- board/nxp/imxrt1050-evk/imxrt1050-evk.c | 2 +- board/nxp/imxrt1170-evk/imxrt1170-evk.c | 2 +- board/nxp/ls1021aqds/ddr.c | 4 +- board/nxp/ls1028a/ls1028a.c | 10 +- board/nxp/ls1043aqds/ls1043aqds.c | 8 +- board/nxp/ls1043ardb/ls1043ardb.c | 8 +- board/nxp/ls1046afrwy/ls1046afrwy.c | 8 +- board/nxp/ls1046aqds/ls1046aqds.c | 8 +- board/nxp/ls1046ardb/ls1046ardb.c | 8 +- board/nxp/ls1088a/ls1088a.c | 6 +- board/nxp/ls2080aqds/ls2080aqds.c | 14 +-- board/nxp/ls2080ardb/ls2080ardb.c | 14 +-- board/nxp/lx2160a/lx2160a.c | 6 +- board/phytec/phycore_am62x/phycore-am62x.c | 26 ++--- board/phytec/phycore_am64x/phycore-am64x.c | 18 ++-- board/phytium/durian/durian.c | 4 +- board/phytium/pe2201/pe2201.c | 4 +- board/raspberrypi/rpi/rpi.c | 4 +- board/renesas/common/rcar64-common.c | 6 +- board/renesas/genmai/genmai.c | 4 +- board/renesas/sparrowhawk/sparrowhawk.c | 8 +- board/ronetix/pm9261/pm9261.c | 4 +- board/ronetix/pm9263/pm9263.c | 4 +- board/ronetix/pm9g45/pm9g45.c | 4 +- board/samsung/arndale/arndale.c | 4 +- board/samsung/common/board.c | 6 +- board/samsung/exynos-mobile/exynos-mobile.c | 4 +- board/samsung/goni/goni.c | 12 +-- board/samsung/smdkc100/smdkc100.c | 4 +- board/samsung/smdkv310/smdkv310.c | 16 +-- board/siemens/iot2050/board.c | 16 +-- board/socionext/developerbox/developerbox.c | 6 +- board/st/stih410-b2260/board.c | 4 +- board/ste/stemmy/stemmy.c | 4 +- board/ti/dra7xx/evm.c | 8 +- board/ti/ks2_evm/board.c | 4 +- board/toradex/colibri_imx7/colibri_imx7.c | 8 +- board/toradex/verdin-am62/verdin-am62.c | 2 +- board/toradex/verdin-am62p/verdin-am62p.c | 2 +- board/traverse/ten64/ten64.c | 6 +- board/xilinx/zynq/cmds.c | 6 +- board/xilinx/zynqmp/zynqmp.c | 4 +- boot/image-board.c | 2 +- boot/image-fdt.c | 4 +- cmd/bdinfo.c | 12 +-- cmd/ti/ddr4.c | 8 +- cmd/ufetch.c | 4 +- common/board_f.c | 10 +- common/init/handoff.c | 10 +- drivers/bootcount/bootcount_ram.c | 4 +- drivers/ddr/altera/sdram_agilex.c | 4 +- drivers/ddr/altera/sdram_agilex5.c | 18 ++-- drivers/ddr/altera/sdram_agilex7m.c | 4 +- drivers/ddr/altera/sdram_arria10.c | 12 +-- drivers/ddr/altera/sdram_n5x.c | 4 +- drivers/ddr/altera/sdram_s10.c | 4 +- drivers/ddr/altera/sdram_soc64.c | 28 ++--- drivers/mmc/mvebu_mmc.c | 4 +- drivers/net/mvgbe.c | 4 +- drivers/pci/pci-uclass.c | 8 +- drivers/usb/host/ehci-marvell.c | 4 +- drivers/video/meson/meson_vpu.c | 8 +- drivers/video/sunxi/sunxi_de2.c | 2 +- drivers/video/sunxi/sunxi_display.c | 2 +- include/asm-generic/global_data.h | 7 ++ include/asm-generic/u-boot.h | 4 - include/configs/m53menlo.h | 4 +- include/configs/mx53cx9020.h | 4 +- include/configs/mx53loco.h | 4 +- include/configs/mx53ppd.h | 4 +- include/fdtdec.h | 7 +- include/init.h | 2 +- lib/fdtdec.c | 23 ++-- lib/lmb.c | 19 ++-- test/cmd/bdinfo.c | 7 +- 167 files changed, 707 insertions(+), 714 deletions(-) (limited to 'drivers') diff --git a/api/api_platform.c b/api/api_platform.c index d5cbcd6e201..d4edf3a20fe 100644 --- a/api/api_platform.c +++ b/api/api_platform.c @@ -21,8 +21,8 @@ int platform_sys_info(struct sys_info *si) si->clk_cpu = gd->cpu_clk; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - platform_set_mr(si, gd->bd->bi_dram[i].start, - gd->bd->bi_dram[i].size, MR_ATTR_DRAM); + platform_set_mr(si, gd->dram[i].start, + gd->dram[i].size, MR_ATTR_DRAM); platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM); platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH); diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 6c85022556a..e59528e576e 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -69,9 +69,9 @@ int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs) } for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - mem_map[index].virt = gd->bd->bi_dram[i].start; - mem_map[index].phys = gd->bd->bi_dram[i].start; - mem_map[index].size = gd->bd->bi_dram[i].size; + mem_map[index].virt = gd->dram[i].start; + mem_map[index].phys = gd->dram[i].start; + mem_map[index].size = gd->dram[i].size; mem_map[index].attrs = attrs; index++; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index cbeac6d4383..88adcf35432 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -538,16 +538,16 @@ static inline void final_mmu_setup(void) */ switch (final_map[index].virt) { case CFG_SYS_FSL_DRAM_BASE1: - final_map[index].virt = gd->bd->bi_dram[0].start; - final_map[index].phys = gd->bd->bi_dram[0].start; - final_map[index].size = gd->bd->bi_dram[0].size; + final_map[index].virt = gd->dram[0].start; + final_map[index].phys = gd->dram[0].start; + final_map[index].size = gd->dram[0].size; break; #ifdef CFG_SYS_FSL_DRAM_BASE2 case CFG_SYS_FSL_DRAM_BASE2: #if (CONFIG_NR_DRAM_BANKS >= 2) - final_map[index].virt = gd->bd->bi_dram[1].start; - final_map[index].phys = gd->bd->bi_dram[1].start; - final_map[index].size = gd->bd->bi_dram[1].size; + final_map[index].virt = gd->dram[1].start; + final_map[index].phys = gd->dram[1].start; + final_map[index].size = gd->dram[1].size; #else final_map[index].size = 0; #endif @@ -556,9 +556,9 @@ static inline void final_mmu_setup(void) #ifdef CFG_SYS_FSL_DRAM_BASE3 case CFG_SYS_FSL_DRAM_BASE3: #if (CONFIG_NR_DRAM_BANKS >= 3) - final_map[index].virt = gd->bd->bi_dram[2].start; - final_map[index].phys = gd->bd->bi_dram[2].start; - final_map[index].size = gd->bd->bi_dram[2].size; + final_map[index].virt = gd->dram[2].start; + final_map[index].phys = gd->dram[2].start; + final_map[index].size = gd->dram[2].size; #else final_map[index].size = 0; #endif @@ -1396,10 +1396,10 @@ static int tfa_dram_init_banksize(void) } debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2); - gd->bd->bi_dram[i].start = res.a1; - gd->bd->bi_dram[i].size = res.a2; + gd->dram[i].start = res.a1; + gd->dram[i].size = res.a2; - dram_size -= gd->bd->bi_dram[i].size; + dram_size -= gd->dram[i].size; i++; } while (dram_size); @@ -1410,24 +1410,24 @@ static int tfa_dram_init_banksize(void) #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bd->bi_dram[2].size >= - board_reserve_ram_top(gd->bd->bi_dram[2].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[2].start + - gd->bd->bi_dram[2].size - - board_reserve_ram_top(gd->bd->bi_dram[2].size); + if (gd->dram[2].size >= + board_reserve_ram_top(gd->dram[2].size)) { + gd->arch.resv_ram = gd->dram[2].start + + gd->dram[2].size - + board_reserve_ram_top(gd->dram[2].size); } else #endif { - if (gd->bd->bi_dram[1].size >= - board_reserve_ram_top(gd->bd->bi_dram[1].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[1].start + - gd->bd->bi_dram[1].size - - board_reserve_ram_top(gd->bd->bi_dram[1].size); - } else if (gd->bd->bi_dram[0].size > - board_reserve_ram_top(gd->bd->bi_dram[0].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - - board_reserve_ram_top(gd->bd->bi_dram[0].size); + if (gd->dram[1].size >= + board_reserve_ram_top(gd->dram[1].size)) { + gd->arch.resv_ram = gd->dram[1].start + + gd->dram[1].size - + board_reserve_ram_top(gd->dram[1].size); + } else if (gd->dram[0].size > + board_reserve_ram_top(gd->dram[0].size)) { + gd->arch.resv_ram = gd->dram[0].start + + gd->dram[0].size - + board_reserve_ram_top(gd->dram[0].size); } } #endif /* CONFIG_RESV_RAM */ @@ -1464,30 +1464,30 @@ int dram_init_banksize(void) } #endif - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - + gd->dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; + gd->dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; + gd->dram[1].size = gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; - gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - + if (gd->dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { + gd->dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; + gd->dram[2].size = gd->dram[1].size - CONFIG_SYS_DDR_BLOCK2_SIZE; - gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; + gd->dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; } #endif } else { - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; } #ifdef CFG_SYS_MEM_RESERVE_SECURE - if (gd->bd->bi_dram[0].size > + if (gd->dram[0].size > CFG_SYS_MEM_RESERVE_SECURE) { - gd->bd->bi_dram[0].size -= + gd->dram[0].size -= CFG_SYS_MEM_RESERVE_SECURE; - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size; + gd->arch.secure_ram = gd->dram[0].start + + gd->dram[0].size; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE; } @@ -1496,24 +1496,24 @@ int dram_init_banksize(void) #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bd->bi_dram[2].size >= - board_reserve_ram_top(gd->bd->bi_dram[2].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[2].start + - gd->bd->bi_dram[2].size - - board_reserve_ram_top(gd->bd->bi_dram[2].size); + if (gd->dram[2].size >= + board_reserve_ram_top(gd->dram[2].size)) { + gd->arch.resv_ram = gd->dram[2].start + + gd->dram[2].size - + board_reserve_ram_top(gd->dram[2].size); } else #endif { - if (gd->bd->bi_dram[1].size >= - board_reserve_ram_top(gd->bd->bi_dram[1].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[1].start + - gd->bd->bi_dram[1].size - - board_reserve_ram_top(gd->bd->bi_dram[1].size); - } else if (gd->bd->bi_dram[0].size > - board_reserve_ram_top(gd->bd->bi_dram[0].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - - board_reserve_ram_top(gd->bd->bi_dram[0].size); + if (gd->dram[1].size >= + board_reserve_ram_top(gd->dram[1].size)) { + gd->arch.resv_ram = gd->dram[1].start + + gd->dram[1].size - + board_reserve_ram_top(gd->dram[1].size); + } else if (gd->dram[0].size > + board_reserve_ram_top(gd->dram[0].size)) { + gd->arch.resv_ram = gd->dram[0].start + + gd->dram[0].size - + board_reserve_ram_top(gd->dram[0].size); } } #endif /* CONFIG_RESV_RAM */ @@ -1535,8 +1535,8 @@ int dram_init_banksize(void) CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, NULL, NULL, NULL); if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; + gd->dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->dram[2].size = dp_ddr_size; } else { puts("Not detected"); } @@ -1567,8 +1567,8 @@ void lmb_arch_add_memory(void) if (i == 2) continue; /* skip DP-DDR */ #endif - ram_start = gd->bd->bi_dram[i].start; - ram_size = gd->bd->bi_dram[i].size; + ram_start = gd->dram[i].start; + ram_size = gd->dram[i].size; #ifdef CONFIG_RESV_RAM if (gd->arch.resv_ram >= ram_start && gd->arch.resv_ram < ram_start + ram_size) diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 2671f9a0ebf..a82ceeaf22f 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -35,14 +35,13 @@ int arch_fixup_fdt(void *blob) { __maybe_unused int ret = 0; #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT) - struct bd_info *bd = gd->bd; int bank; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; #ifdef CONFIG_ARMV7_NONSEC ret = armv7_apply_memory_carveout(&start[bank], &size[bank]); if (ret) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 1cde655bc80..9a115cc6078 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -64,8 +64,8 @@ static void setup_memory_tags(struct bd_info *bd) params->hdr.tag = ATAG_MEM; params->hdr.size = tag_size (tag_mem32); - params->u.mem.start = bd->bi_dram[i].start; - params->u.mem.size = bd->bi_dram[i].size; + params->u.mem.start = gd->dram[i].start; + params->u.mem.size = gd->dram[i].size; params = tag_next (params); } diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 947012f2996..28bb6fd36c8 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -94,17 +94,16 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, __weak void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; - /* bd->bi_dram is available only after relocation */ + /* gd->dram is available only after relocation */ if ((gd->flags & GD_FLG_RELOC) == 0) return; debug("%s: bank: %d\n", __func__, bank); - for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + - (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); + for (i = gd->dram[bank].start >> MMU_SECTION_SHIFT; + i < (gd->dram[bank].start >> MMU_SECTION_SHIFT) + + (gd->dram[bank].size >> MMU_SECTION_SHIFT); i++) set_section_dcache(i, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c index 1f672eee2c8..2268661de93 100644 --- a/arch/arm/lib/image.c +++ b/arch/arm/lib/image.c @@ -69,7 +69,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, if (!force_reloc && (le64_to_cpu(ih->flags) & BIT(3))) dst = image - text_offset; else - dst = gd->bd->bi_dram[0].start; + dst = gd->dram[0].start; *relocated_addr = ALIGN(dst, SZ_2M) + text_offset; diff --git a/arch/arm/mach-airoha/an7581/init.c b/arch/arm/mach-airoha/an7581/init.c index ab32706a79d..f33527ca129 100644 --- a/arch/arm/mach-airoha/an7581/init.c +++ b/arch/arm/mach-airoha/an7581/init.c @@ -23,12 +23,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); if (gd->ram_size > SZ_2G) { - gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = gd->ram_base + SZ_2G; + gd->dram[1].size = gd->ram_size - SZ_2G; } return 0; diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 20054f54089..e74a5a76919 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -807,8 +807,8 @@ void build_mem_map(void) ; /* Align RAM mapping to page boundaries */ - base = gd->bd->bi_dram[0].start; - size = gd->bd->bi_dram[0].size; + base = gd->dram[0].start; + size = gd->dram[0].size; size += (base - ALIGN_DOWN(base, SZ_4K)); base = ALIGN_DOWN(base, SZ_4K); size = ALIGN(size, SZ_4K); diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 07125eac7cd..2281686d633 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -33,8 +33,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 86b11bdf2ac..e1284833ac5 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -311,12 +311,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) static inline bool check_in_dram(ulong addr) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - if (addr >= bd->bi_dram[i].start && - addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + if (gd->dram[i].size) { + if (addr >= gd->dram[i].start && + addr < (gd->dram[i].start + gd->dram[i].size)) return true; } } diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 71a3b341913..34712747fa3 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -111,12 +111,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) static inline bool check_in_dram(ulong addr) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - if (addr >= bd->bi_dram[i].start && - addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + if (gd->dram[i].size) { + if (addr >= gd->dram[i].start && + addr < (gd->dram[i].start + gd->dram[i].size)) return true; } } diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index f4738e3fda8..b52675d8aba 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -604,18 +604,18 @@ static void dram_bank_sort(int current_bank) phys_size_t size; while (current_bank > 0) { - if (gd->bd->bi_dram[current_bank - 1].start > - gd->bd->bi_dram[current_bank].start) { - start = gd->bd->bi_dram[current_bank - 1].start; - size = gd->bd->bi_dram[current_bank - 1].size; - - gd->bd->bi_dram[current_bank - 1].start = - gd->bd->bi_dram[current_bank].start; - gd->bd->bi_dram[current_bank - 1].size = - gd->bd->bi_dram[current_bank].size; - - gd->bd->bi_dram[current_bank].start = start; - gd->bd->bi_dram[current_bank].size = size; + if (gd->dram[current_bank - 1].start > + gd->dram[current_bank].start) { + start = gd->dram[current_bank - 1].start; + size = gd->dram[current_bank - 1].size; + + gd->dram[current_bank - 1].start = + gd->dram[current_bank].start; + gd->dram[current_bank - 1].size = + gd->dram[current_bank].size; + + gd->dram[current_bank].start = start; + gd->dram[current_bank].size = size; } current_bank--; } @@ -643,24 +643,24 @@ int dram_init_banksize(void) continue; if (start >= phys_sdram_1_start && start <= end1) { - gd->bd->bi_dram[i].start = start; + gd->dram[i].start = start; if ((end + 1) <= end1) - gd->bd->bi_dram[i].size = + gd->dram[i].size = end - start + 1; else - gd->bd->bi_dram[i].size = end1 - start; + gd->dram[i].size = end1 - start; dram_bank_sort(i); i++; } else if (start >= phys_sdram_2_start && start <= end2) { - gd->bd->bi_dram[i].start = start; + gd->dram[i].start = start; if ((end + 1) <= end2) - gd->bd->bi_dram[i].size = + gd->dram[i].size = end - start + 1; else - gd->bd->bi_dram[i].size = end2 - start; + gd->dram[i].size = end2 - start; dram_bank_sort(i); i++; @@ -670,10 +670,10 @@ int dram_init_banksize(void) /* If error, set to the default value */ if (!i) { - gd->bd->bi_dram[0].start = phys_sdram_1_start; - gd->bd->bi_dram[0].size = phys_sdram_1_size; - gd->bd->bi_dram[1].start = phys_sdram_2_start; - gd->bd->bi_dram[1].size = phys_sdram_2_size; + gd->dram[0].start = phys_sdram_1_start; + gd->dram[0].size = phys_sdram_1_size; + gd->dram[1].start = phys_sdram_2_start; + gd->dram[1].size = phys_sdram_2_size; } return 0; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 498bbe6704f..e600fd6b33e 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -224,11 +224,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx8m_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx8m_mem_map[entry].phys = gd->dram[i].start; + imx8m_mem_map[entry].virt = gd->dram[i].start; + imx8m_mem_map[entry].size = gd->dram[i].size; imx8m_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size); @@ -290,24 +290,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -315,8 +315,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index ccdb949a9da..6d6f3b81aca 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -512,11 +512,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx8ulp_arm64_mem_map[entry].phys = gd->dram[i].start; + imx8ulp_arm64_mem_map[entry].virt = gd->dram[i].start; + imx8ulp_arm64_mem_map[entry].size = gd->dram[i].size; imx8ulp_arm64_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size); @@ -568,24 +568,24 @@ int dram_init_banksize(void) if (ret) return ret; - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_size; + gd->dram[bank].size = sdram_size; } return 0; diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 123c1d51a4d..82b3cdffeea 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -356,11 +356,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx9_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx9_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx9_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx9_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx9_mem_map[entry].phys = gd->dram[i].start; + imx9_mem_map[entry].virt = gd->dram[i].start; + imx9_mem_map[entry].size = gd->dram[i].size; imx9_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx9_mem_map[entry].phys, imx9_mem_map[entry].size); @@ -453,24 +453,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -478,8 +478,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 6576ecefd5f..0c731e76329 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -367,11 +367,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx93_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx93_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx93_mem_map[entry].phys = gd->dram[i].start; + imx93_mem_map[entry].virt = gd->dram[i].start; + imx93_mem_map[entry].size = gd->dram[i].size; imx93_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx93_mem_map[entry].phys, imx93_mem_map[entry].size); @@ -445,24 +445,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -470,8 +470,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; diff --git a/arch/arm/mach-imx/mx5/mx53_dram.c b/arch/arm/mach-imx/mx5/mx53_dram.c index 180a745d435..5f7709e00b0 100644 --- a/arch/arm/mach-imx/mx5/mx53_dram.c +++ b/arch/arm/mach-imx/mx5/mx53_dram.c @@ -35,11 +35,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); return 0; } diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 57ae81c7834..1029c1e4e85 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -375,8 +375,8 @@ void *spl_load_simple_fit_fix_load(const void *fit) #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = imx_ddr_size(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = imx_ddr_size(); return 0; } diff --git a/arch/arm/mach-k3/k3-ddr.c b/arch/arm/mach-k3/k3-ddr.c index 6e3e60cdc86..35c30b1a16f 100644 --- a/arch/arm/mach-k3/k3-ddr.c +++ b/arch/arm/mach-k3/k3-ddr.c @@ -59,8 +59,8 @@ void fixup_memory_node(struct spl_image_info *spl_image) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index be2d9a25bf9..3ebb4294bdd 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -138,8 +138,8 @@ int alleycat5_dram_init_banksize(void) /* * Config single DRAM bank */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index 17525691e68..38d9b40f482 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -256,7 +256,7 @@ int a3700_dram_init_banksize(void) * build_mem_map. */ if (last_end == dram_wins[win].base) { - gd->bd->bi_dram[bank - 1].size += size; + gd->dram[bank - 1].size += size; last_end += size; } else { if (bank == CONFIG_NR_DRAM_BANKS) { @@ -264,8 +264,8 @@ int a3700_dram_init_banksize(void) return -ENOBUFS; } - gd->bd->bi_dram[bank].start = dram_wins[win].base; - gd->bd->bi_dram[bank].size = size; + gd->dram[bank].start = dram_wins[win].base; + gd->dram[bank].size = size; last_end = dram_wins[win].base + size; ++bank; } @@ -276,8 +276,8 @@ int a3700_dram_init_banksize(void) * the rest with zeros. */ for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) { - gd->bd->bi_dram[bank].start = 0; - gd->bd->bi_dram[bank].size = 0; + gd->dram[bank].start = 0; + gd->dram[bank].size = 0; } return 0; diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index fd58551d0e3..af37dfa2252 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -38,16 +38,16 @@ int a8k_dram_init_banksize(void) */ phys_size_t max_bank0_size = SZ_4G - SZ_1G; - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size <= max_bank0_size) { - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return 0; } - gd->bd->bi_dram[0].size = max_bank0_size; + gd->dram[0].size = max_bank0_size; if (CONFIG_NR_DRAM_BANKS > 1) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = gd->ram_size - max_bank0_size; } return 0; diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index c00c6b9b3fc..41eaaa24bd0 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -294,11 +294,11 @@ int dram_init_banksize(void) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = mvebu_sdram_bar(i); - gd->bd->bi_dram[i].size = mvebu_sdram_bs(i); + gd->dram[i].start = mvebu_sdram_bar(i); + gd->dram[i].size = mvebu_sdram_bs(i); /* Clip the banksize to 1GiB if it exceeds the max size */ - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; if (size > MVEBU_SDRAM_SIZE_MAX) mvebu_sdram_bs_set(i, 0x40000000); } diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 8699cf46b67..729533d02d4 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -80,8 +80,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c index 200a08fa5c8..f08a9b263f6 100644 --- a/arch/arm/mach-omap2/omap-cache.c +++ b/arch/arm/mach-omap2/omap-cache.c @@ -53,11 +53,10 @@ void enable_caches(void) void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; - u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + u32 start = gd->dram[bank].start >> MMU_SECTION_SHIFT; + u32 size = gd->dram[bank].size >> MMU_SECTION_SHIFT; u32 end = start + size; debug("%s: bank: %d\n", __func__, bank); diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index 049eedfeb65..67e14d70e92 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -150,10 +150,10 @@ int dram_init_banksize(void) size0 = get_sdr_cs_size(CS0); size1 = get_sdr_cs_size(CS1); - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = size0; + gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->dram[1].size = size1; return 0; } diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 24fae484369..c4187369c29 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -222,10 +222,10 @@ int dram_init_banksize(void) size0 = get_sdr_cs_size(CS0); size1 = get_sdr_cs_size(CS1); - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = size0; + gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->dram[1].size = size1; return 0; } diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index 0130cad7678..e316c2cc40e 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -50,8 +50,8 @@ int dram_init(void) /* This is called after dram_init() so use get_ram_size result */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c index d24419f5daa..f7dc2be6cca 100644 --- a/arch/arm/mach-renesas/memmap-gen3.c +++ b/arch/arm/mach-renesas/memmap-gen3.c @@ -70,8 +70,8 @@ void enable_caches(void) /* Generate entires for DRAM in 32bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) @@ -114,8 +114,8 @@ void enable_caches(void) /* Generate entires for DRAM in 64bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) diff --git a/arch/arm/mach-renesas/memmap-rzg2l.c b/arch/arm/mach-renesas/memmap-rzg2l.c index 3b3c6f7cde9..5981b3c9c4d 100644 --- a/arch/arm/mach-renesas/memmap-rzg2l.c +++ b/arch/arm/mach-renesas/memmap-rzg2l.c @@ -67,8 +67,8 @@ void enable_caches(void) /* Generate entries for DRAM in 32bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index eedce7b9b08..c8de1a21024 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -243,14 +243,14 @@ int arch_cpu_init(void) int rockchip_dram_init_banksize_fixup(struct bd_info *bd) { - size_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size; + size_t ram_top = gd->dram[1].start + gd->dram[1].size; if (ram_top > DRAM_GAP_START) { - bd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start; + gd->dram[1].size = DRAM_GAP_START - gd->dram[1].start; if (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) { - bd->bi_dram[2].start = DRAM_GAP_END; - bd->bi_dram[2].size = ram_top - bd->bi_dram[2].start; + gd->dram[2].start = DRAM_GAP_END; + gd->dram[2].size = ram_top - gd->dram[2].start; } } diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index ea0e3621af7..f0923186fa6 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -171,7 +171,7 @@ static int rockchip_dram_init_banksize(void) /* * Rockchip guaranteed DDR_MEM is ordered so no need to worry about - * bi_dram order. + * dram order. */ for (i = 0, j = 0; i < ddr_info->count; i++, j++) { phys_size_t size = ddr_info->bank[(i + ddr_info->count)]; @@ -261,8 +261,8 @@ static int rockchip_dram_init_banksize(void) * split the region in two, one for before the * reserved memory area and one for after. */ - gd->bd->bi_dram[j].start = start_addr; - gd->bd->bi_dram[j].size = rsrv_start - start_addr; + gd->dram[j].start = start_addr; + gd->dram[j].size = rsrv_start - start_addr; j++; @@ -281,8 +281,8 @@ static int rockchip_dram_init_banksize(void) return -ENOMEM; } - gd->bd->bi_dram[j].start = start_addr; - gd->bd->bi_dram[j].size = size; + gd->dram[j].start = start_addr; + gd->dram[j].size = size; } return 0; @@ -309,15 +309,15 @@ int dram_init_banksize(void) ret); /* Reserve 2M for ATF bl31 */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M; - gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; + gd->dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M; + gd->dram[0].size = top - gd->dram[0].start; /* Add usable memory beyond the blob of space for peripheral near 4GB */ if (ram_top > SZ_4G && top < SZ_4G) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = ram_top - gd->dram[1].start; } else if (ram_top > SZ_4G && top == SZ_4G) { - gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start; + gd->dram[0].size = ram_top - gd->dram[0].start; } #else #ifdef CONFIG_SPL_OPTEE_IMAGE @@ -327,23 +327,23 @@ int dram_init_banksize(void) TRUST_PARAMETER_OFFSET); if (tos_parameter->tee_mem.flags == 1) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = tos_parameter->tee_mem.phy_addr - CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + + gd->dram[1].start = tos_parameter->tee_mem.phy_addr + tos_parameter->tee_mem.size; - gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; + gd->dram[1].size = top - gd->dram[1].start; } else { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x8400000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x8400000; /* Reserve 32M for OPTEE with TA */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE - + gd->bd->bi_dram[0].size + 0x2000000; - gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; + gd->dram[1].start = CFG_SYS_SDRAM_BASE + + gd->dram[0].size + 0x2000000; + gd->dram[1].size = top - gd->dram[1].start; } #else - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = top - gd->dram[0].start; #endif #endif diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 829a0109ac7..35735f1551c 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -73,19 +73,19 @@ static int ddr_bank_cmp(const void *v1, const void *v2) } /* This has to be done post-relocation since gd->bd isn't preserved */ -static void qcom_configure_bi_dram(void) +static void qcom_configure_dram(void) { int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start; - gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size; + gd->dram[i].start = prevbl_ddr_banks[i].start; + gd->dram[i].size = prevbl_ddr_banks[i].size; } } int dram_init_banksize(void) { - qcom_configure_bi_dram(); + qcom_configure_dram(); return 0; } @@ -594,15 +594,15 @@ static void build_mem_map(void) */ mem_map[0].phys = 0x1000; mem_map[0].virt = mem_map[0].phys; - mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys; + mem_map[0].size = gd->dram[0].start - mem_map[0].phys; mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; - for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) { - mem_map[i].phys = gd->bd->bi_dram[j].start; + for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->dram[j].size; i++, j++) { + mem_map[i].phys = gd->dram[j].start; mem_map[i].virt = mem_map[i].phys; - mem_map[i].size = gd->bd->bi_dram[j].size; + mem_map[i].size = gd->dram[j].size; mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \ PTE_BLOCK_INNER_SHARE; } diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 4d7f0b9a79c..b202ca258bc 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -202,11 +202,10 @@ void board_prep_linux(struct bootm_headers *images) void lmb_arch_add_memory(void) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (bd->bi_dram[i].size) - lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size); + if (gd->dram[i].size) + lmb_add(gd->dram[i].start, gd->dram[i].size); } } #endif diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 7e0f3875b7c..338f73d6e73 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -246,7 +246,6 @@ int qspi_flash_software_reset(void) void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; u32 start, size; int i; @@ -261,11 +260,11 @@ void dram_bank_mmu_setup(int bank) * The default implementation of this function allows the DRAM dcache * to be enabled only after relocation. However, to speed up ECC * initialization, we want to be able to enable DRAM dcache before - * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram + * relocation, so we don't check GD_FLG_RELOC (this assumes gd->dram * is set first). */ - start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + start = gd->dram[bank].start >> MMU_SECTION_SHIFT; + size = gd->dram[bank].size >> MMU_SECTION_SHIFT; for (i = start; i < start + size; i++) set_section_dcache(i, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 835eaf48dfa..76c324b55ae 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -825,8 +825,8 @@ static int init_device(struct stm32prog_data *data, dev->mtd = mtd; break; case STM32PROG_RAM: - first_addr = gd->bd->bi_dram[0].start; - last_addr = first_addr + gd->bd->bi_dram[0].size; + first_addr = gd->dram[0].start; + last_addr = first_addr + gd->dram[0].size; dev->erase_size = 1; break; default: diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 252aef1852e..4d81c70b230 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -52,7 +52,6 @@ u32 get_bootauth(void) */ void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; phys_addr_t start; phys_addr_t addr; @@ -67,9 +66,9 @@ void dram_bank_mmu_setup(int bank) size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); #endif } else if (gd->flags & GD_FLG_RELOC) { - /* bd->bi_dram is available only after relocation */ - start = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; + /* gd->dram is available only after relocation */ + start = gd->dram[bank].start; + size = gd->dram[bank].size; use_lmb = true; } else { /* mark cacheable and executable the beggining of the DDR */ diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 396851c5bd8..1763f95ace4 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -393,18 +393,18 @@ int dram_init_banksize(void) /* fall back to default DRAM bank size computation */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = usable_ram_size_below_4g(); #ifdef CONFIG_PHYS_64BIT if (gd->ram_size > SZ_2G) { - gd->bd->bi_dram[1].start = 0x100000000; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = 0x100000000; + gd->dram[1].size = gd->ram_size - SZ_2G; } else #endif { - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[1].start = 0; + gd->dram[1].size = 0; } return 0; @@ -418,7 +418,7 @@ int dram_init_banksize(void) * carve-out, as mentioned above. * * This function is called before dram_init_banksize(), so we can't simply - * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. + * return gd->dram[1].start + gd->dram[1].size. */ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c index e2342b2aece..ff15fa28eb5 100644 --- a/arch/arm/mach-tegra/cboot.c +++ b/arch/arm/mach-tegra/cboot.c @@ -185,8 +185,8 @@ int cboot_dram_init_banksize(void) } for (i = 0; i < ram_bank_count; i++) { - gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; - gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; + gd->dram[i].start = tegra_mem_map[1 + i].virt; + gd->dram[i].size = tegra_mem_map[1 + i].size; } return 0; diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 0e1164a2680..ae495808dec 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -280,9 +280,9 @@ int dram_init_banksize(void) return ret; for (i = 0; i < ARRAY_SIZE(dram_map); i++) { - if (i < ARRAY_SIZE(gd->bd->bi_dram)) { - gd->bd->bi_dram[i].start = dram_map[i].base; - gd->bd->bi_dram[i].size = dram_map[i].size; + if (i < ARRAY_SIZE(gd->dram)) { + gd->dram[i].start = dram_map[i].base; + gd->dram[i].size = dram_map[i].size; } if (!dram_map[i].size) diff --git a/arch/arm/mach-uniphier/fdt-fixup.c b/arch/arm/mach-uniphier/fdt-fixup.c index dfa32fdd48b..4e1de15cd98 100644 --- a/arch/arm/mach-uniphier/fdt-fixup.c +++ b/arch/arm/mach-uniphier/fdt-fixup.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include #include @@ -20,6 +21,7 @@ */ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd) { + DECLARE_GLOBAL_DATA_PTR; unsigned long rsv_addr; const unsigned long rsv_size = 64; int i, ret; @@ -28,11 +30,11 @@ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd) uniphier_get_soc_id() != UNIPHIER_LD20_ID) return 0; - for (i = 0; i < ARRAY_SIZE(bd->bi_dram); i++) { - if (!bd->bi_dram[i].size) + for (i = 0; i < ARRAY_SIZE(gd->dram); i++) { + if (!gd->dram[i].size) continue; - rsv_addr = bd->bi_dram[i].start + bd->bi_dram[i].size; + rsv_addr = gd->dram[i].start + gd->dram[i].size; rsv_addr -= rsv_size; ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c index d088e440f63..78ead1f45f6 100644 --- a/arch/arm/mach-versal-net/cpu.c +++ b/arch/arm/mach-versal-net/cpu.c @@ -69,12 +69,12 @@ void mem_map_fill(void) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; - versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; - versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; - versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].virt = gd->dram[i].start; + versal_mem_map[banks].phys = gd->dram[i].start; + versal_mem_map[banks].size = gd->dram[i].size; versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 363ce3007fd..0dd5cc153c4 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -82,21 +82,21 @@ void mem_map_fill(void) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; #if defined(CONFIG_VERSAL_NO_DDR) - if (gd->bd->bi_dram[i].start < 0x80000000UL || - gd->bd->bi_dram[i].start > 0x100000000UL) { + if (gd->dram[i].start < 0x80000000UL || + gd->dram[i].start > 0x100000000UL) { printf("Ignore caches over %llx/%llx\n", - gd->bd->bi_dram[i].start, - gd->bd->bi_dram[i].size); + gd->dram[i].start, + gd->dram[i].size); continue; } #endif - versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; - versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; - versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].virt = gd->dram[i].start; + versal_mem_map[banks].phys = gd->dram[i].start; + versal_mem_map[banks].size = gd->dram[i].size; versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index a81609cdec7..f65c231bdab 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -109,7 +109,7 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks) * fill_bd_mem_info() - Copy DRAM banks from mem_map to bd_info * * Transfers DRAM bank information from the global versal2_mem_map[] - * array to bd->bi_dram[] for passing memory configuration to the + * array to gd->dram[] for passing memory configuration to the * Linux kernel via boot parameters (ATAGS/FDT). Each bank's physical * address and size are copied. * @@ -119,15 +119,14 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks) */ void fill_bd_mem_info(void) { - struct bd_info *bd = gd->bd; int banks = VERSAL2_MEM_MAP_USED; for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { if (!versal2_mem_map[banks].size) break; - bd->bi_dram[i].start = versal2_mem_map[banks].phys; - bd->bi_dram[i].size = versal2_mem_map[banks].size; + gd->dram[i].start = versal2_mem_map[banks].phys; + gd->dram[i].size = versal2_mem_map[banks].size; banks++; } } diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 5f194aaff9a..3dc47e5d48e 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -92,12 +92,12 @@ void mem_map_fill(void) #if !defined(CONFIG_ZYNQMP_NO_DDR) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; - zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start; - zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start; - zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size; + zynqmp_mem_map[banks].virt = gd->dram[i].start; + zynqmp_mem_map[banks].phys = gd->dram[i].start; + zynqmp_mem_map[banks].size = gd->dram[i].size; zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 5b1311d8b5b..817728aa569 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -41,8 +41,8 @@ int dram_init(void) * No DDR init yet -> run in L2 cache */ gd->ram_size = (4 << 20); - gd->bd->bi_dram[0].size = gd->ram_size; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = gd->ram_size; + gd->dram[1].size = 0; } return 0; diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c index cc1e903c9dd..2893bc6b99a 100644 --- a/arch/riscv/cpu/k1/dram.c +++ b/arch/riscv/cpu/k1/dram.c @@ -56,12 +56,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) { - gd->bd->bi_dram[1].start = 0x100000000; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = 0x100000000; + gd->dram[1].size = gd->ram_size - SZ_2G; } return 0; @@ -82,8 +82,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - start[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + start[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index 1668b58d3fb..460013f933b 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -131,8 +131,8 @@ SPL_LOAD_IMAGE_METHOD("sandbox_image", 7, BOOT_DEVICE_BOARD, load_from_image); int dram_init_banksize(void) { /* These are necessary so TFTP can use LMBs to check its load address */ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); return 0; } diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index cc1edd7badd..81604ee12fb 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -91,8 +91,8 @@ int dram_init_banksize(void) struct memrange *memrange = &lib_sysinfo.memrange[i]; if (memrange->type == CB_MEM_RAM) { - gd->bd->bi_dram[j].start = memrange->base; - gd->bd->bi_dram[j].size = memrange->size; + gd->dram[j].start = memrange->base; + gd->dram[j].size = memrange->size; j++; if (j >= CONFIG_NR_DRAM_BANKS) break; diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 6845ce72ff9..b86d50b2cab 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -123,8 +123,8 @@ int dram_init_banksize(void) if (desc->type != EFI_CONVENTIONAL_MEMORY || (desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20) continue; - gd->bd->bi_dram[num_banks].start = desc->physical_start; - gd->bd->bi_dram[num_banks].size = desc->num_pages << + gd->dram[num_banks].start = desc->physical_start; + gd->dram[num_banks].size = desc->num_pages << EFI_PAGE_SHIFT; num_banks++; } diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c index 6fe40071140..e09fce8bb1b 100644 --- a/arch/x86/cpu/efi/sdram.c +++ b/arch/x86/cpu/efi/sdram.c @@ -24,8 +24,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = efi_get_ram_base(); - gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE; + gd->dram[0].start = efi_get_ram_base(); + gd->dram[0].size = CONFIG_EFI_RAM_SIZE; return 0; } diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index baa1f0e32d6..11ce97b5143 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -67,8 +67,8 @@ void mrc_common_dram_init_banksize(void) if (area->start >= 1ULL << 32) continue; - gd->bd->bi_dram[num_banks].start = area->start; - gd->bd->bi_dram[num_banks].size = area->size; + gd->dram[num_banks].start = area->start; + gd->dram[num_banks].size = area->size; num_banks++; } } diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c index d20c9a2a379..a5e81dfada5 100644 --- a/arch/x86/cpu/ivybridge/sdram_nop.c +++ b/arch/x86/cpu/ivybridge/sdram_nop.c @@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { gd->ram_size = 1ULL << 31; - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index ba3638e6acc..3cba04f2c3e 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -69,13 +69,13 @@ int dram_init_banksize(void) { u64 high_mem_size; - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = qemu_get_low_memory_size(); + gd->dram[0].start = 0; + gd->dram[0].size = qemu_get_low_memory_size(); high_mem_size = qemu_get_high_memory_size(); if (high_mem_size) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = high_mem_size; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = high_mem_size; } return 0; diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 34e576940d4..34fdb7e026a 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -169,8 +169,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c index 75ca5273625..5aa4f6d3e07 100644 --- a/arch/x86/cpu/slimbootloader/sdram.c +++ b/arch/x86/cpu/slimbootloader/sdram.c @@ -129,8 +129,8 @@ int dram_init_banksize(void) return 0; /* simply use a single bank to have whole size for now */ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index 6192f2296b8..6ce96b0569b 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -160,8 +160,8 @@ static int sfi_get_bank_size(void) if (mentry->type != SFI_MEM_CONV) continue; - gd->bd->bi_dram[bank].start = mentry->phys_start; - gd->bd->bi_dram[bank].size = mentry->pages << 12; + gd->dram[bank].start = mentry->phys_start; + gd->dram[bank].size = mentry->pages << 12; bank++; } diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index cde4fbf3557..e054f42fa86 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -43,14 +43,13 @@ void bootm_announce_and_cleanup(void) #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL) int arch_fixup_memory_node(void *blob) { - struct bd_info *bd = gd->bd; int bank; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 730721dc176..a45e4060ef2 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -64,8 +64,8 @@ int dram_init_banksize(void) update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2); if (!ll_boot_init()) { - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; if (update_mtrr) mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); @@ -89,21 +89,21 @@ int dram_init_banksize(void) mtrr_top = max(mtrr_top, res_desc->phys_start + res_desc->len); } else { - gd->bd->bi_dram[bank].start = res_desc->phys_start; - gd->bd->bi_dram[bank].size = res_desc->len; + gd->dram[bank].start = res_desc->phys_start; + gd->dram[bank].size = res_desc->len; if (update_mtrr) mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start, res_desc->len); log_debug("ram %llx %llx\n", - gd->bd->bi_dram[bank].start, - gd->bd->bi_dram[bank].size); + gd->dram[bank].start, + gd->dram[bank].size); } } /* Add the memory below 4GB */ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = low_end; + gd->dram[0].start = 0; + gd->dram[0].size = low_end; /* * Set up an MTRR to the top of low, reserved memory. This is necessary @@ -184,7 +184,7 @@ unsigned int install_e820_map(unsigned int max_entries, #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB) int handoff_arch_save(struct spl_handoff *ho) { - ho->arch.usable_ram_top = gd->bd->bi_dram[0].size; + ho->arch.usable_ram_top = gd->dram[0].size; ho->arch.hob_list = gd->arch.hob_list; return 0; diff --git a/board/CZ.NIC/turris_1x/turris_1x.c b/board/CZ.NIC/turris_1x/turris_1x.c index 2f9557a4170..32535ed6ee0 100644 --- a/board/CZ.NIC/turris_1x/turris_1x.c +++ b/board/CZ.NIC/turris_1x/turris_1x.c @@ -42,9 +42,9 @@ int dram_init_banksize(void) static_assert(CONFIG_NR_DRAM_BANKS >= 3); - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); - size -= gd->bd->bi_dram[0].size; + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); + size -= gd->dram[0].size; /* Note: This address space is not mapped via TLB entries in U-Boot */ @@ -68,16 +68,16 @@ int dram_init_banksize(void) if (size > 0) { /* Free space between PCIe bus 3 MEM and NOR */ - gd->bd->bi_dram[1].start = 0xc0200000; - gd->bd->bi_dram[1].size = min(size, 0xef000000 - gd->bd->bi_dram[1].start); - size -= gd->bd->bi_dram[1].size; + gd->dram[1].start = 0xc0200000; + gd->dram[1].size = min(size, 0xef000000 - gd->dram[1].start); + size -= gd->dram[1].size; } if (size > 0) { /* Free space between NOR and NAND */ - gd->bd->bi_dram[2].start = 0xf0000000; - gd->bd->bi_dram[2].size = min(size, 0xff800000 - gd->bd->bi_dram[2].start); - size -= gd->bd->bi_dram[2].size; + gd->dram[2].start = 0xf0000000; + gd->dram[2].size = min(size, 0xff800000 - gd->dram[2].start); + size -= gd->dram[2].size; } #else puts("\n\n!!! TODO: fix sdcard >2GB RAM\n\n\n"); @@ -231,8 +231,8 @@ void ft_memory_setup(void *blob, struct bd_info *bd) if (!env_get("bootm_low") && !env_get("bootm_size")) { for (count = 0; count < CONFIG_NR_DRAM_BANKS; count++) { - start[count] = gd->bd->bi_dram[count].start; - size[count] = gd->bd->bi_dram[count].size; + start[count] = gd->dram[count].start; + size[count] = gd->dram[count].size; if (!size[count]) break; } @@ -452,13 +452,13 @@ static void recalculate_used_pcie_mem(void) size = gd->ram_size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size -= gd->bd->bi_dram[i].size; + size -= gd->dram[i].size; if (size == 0) return; e = find_law_by_addr_id(CFG_SYS_PCIE3_MEM_PHYS, LAW_TRGT_IF_PCIE_3); - if (e.index < 0 && gd->bd->bi_dram[1].size > 0) { + if (e.index < 0 && gd->dram[1].size > 0) { /* * If there is no LAW for PCIe 3 MEM then 3rd PCIe controller * is inactive, which is the case for Turris 1.0 boards. So @@ -471,8 +471,8 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(bank_size, ""); printf(" of PCIe 3 MEM for DDR RAM\n"); - gd->bd->bi_dram[1].start -= bank_size; - gd->bd->bi_dram[1].size += bank_size; + gd->dram[1].start -= bank_size; + gd->dram[1].size += bank_size; size -= bank_size; if (size == 0) return; @@ -534,9 +534,9 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(free_size2, ""); printf(" of PCIe 2 MEM for DDR RAM\n"); - gd->bd->bi_dram[i].start = free_start2; - gd->bd->bi_dram[i].size = min(size, free_size2); - size -= gd->bd->bi_dram[i].start; + gd->dram[i].start = free_start2; + gd->dram[i].size = min(size, free_size2); + size -= gd->dram[i].start; i++; if (size == 0) return; @@ -548,9 +548,9 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(free_size1, ""); printf(" of PCIe 1 MEM for DDR RAM\n"); - gd->bd->bi_dram[i].start = free_start1; - gd->bd->bi_dram[i].size = min(size, free_size1); - size -= gd->bd->bi_dram[i].size; + gd->dram[i].start = free_start1; + gd->dram[i].size = min(size, free_size1); + size -= gd->dram[i].size; i++; if (size == 0) return; diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c index 16d0e679c3e..eb0f9c06849 100644 --- a/board/armltd/corstone1000/corstone1000.c +++ b/board/armltd/corstone1000/corstone1000.c @@ -86,8 +86,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index eaf87e3bfe3..6cd24bf25fb 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -137,7 +137,7 @@ int misc_init_r (void) int dram_init (void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; #ifdef CONFIG_CM_SPD_DETECT { extern void dram_query(void); @@ -170,7 +170,7 @@ extern void dram_query(void); PHYS_SDRAM_1_SIZE); #endif /* CM_SPD_DETECT */ /* We only have one bank of RAM, set it to whatever was detected */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index 12bb6defab2..057e916ab1b 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -89,9 +89,9 @@ void build_mem_map(void) * The first node is for I/O device, start from node 1 for * updating DRAM info. */ - mem_map[i + 1].virt = gd->bd->bi_dram[i].start; - mem_map[i + 1].phys = gd->bd->bi_dram[i].start; - mem_map[i + 1].size = gd->bd->bi_dram[i].size; + mem_map[i + 1].virt = gd->dram[i].start; + mem_map[i + 1].phys = gd->dram[i].start; + mem_map[i + 1].size = gd->dram[i].size; mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; } diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 3833af59b09..87e53f64e06 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -79,11 +79,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); return 0; diff --git a/board/atmel/common/video_display.c b/board/atmel/common/video_display.c index 77188820581..7cb492b2da6 100644 --- a/board/atmel/common/video_display.c +++ b/board/atmel/common/video_display.c @@ -40,7 +40,7 @@ int at91_video_show_board_info(void) dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - dram_size += gd->bd->bi_dram[i].size; + dram_size += gd->dram[i].size; nand_size = 0; #ifdef CONFIG_NAND_ATMEL diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c index 43797d625e9..b19ae3b4b03 100644 --- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c +++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c @@ -66,7 +66,7 @@ int misc_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; board_leds_init(); diff --git a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c index 364b6a3e24b..5c35239a90a 100644 --- a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c +++ b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c @@ -45,7 +45,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index 858061bf9f9..33ae6a76bf7 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -64,7 +64,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 19341d325bd..0e2d5592753 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -58,7 +58,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c index 8759ff6f01a..1a17db1bd5b 100644 --- a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c +++ b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c @@ -65,7 +65,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index c0862f58606..b48e8fe7697 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -63,7 +63,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c index 764c8f035c9..cdf2793b643 100644 --- a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c +++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c @@ -52,7 +52,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; board_leds_init(); diff --git a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c index b05c9754c96..02543d8e99f 100644 --- a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c +++ b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { // Address of boot parameters - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/axiado/scm3005/scm3005.c b/board/axiado/scm3005/scm3005.c index 4643ba4a55c..b2df6d89cd8 100644 --- a/board/axiado/scm3005/scm3005.c +++ b/board/axiado/scm3005/scm3005.c @@ -96,8 +96,8 @@ int dram_init(void) */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index bb2f1e4f62a..2683f46f41c 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -176,8 +176,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M); - gd->bd->bi_dram[0].size = SZ_16M; + gd->dram[0].start = (BCM_NS3_MEM_END - SZ_16M); + gd->dram[0].size = SZ_16M; return 0; } diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index e20350dc5d5..5bc4d3248bd 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -666,34 +666,34 @@ int misc_init_r(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[1].start = PHYS_SDRAM_2; switch (gd->ram_size) { case 0x10000000: /* DDR_16BIT_256MB */ - gd->bd->bi_dram[0].size = 0x10000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x10000000; + gd->dram[1].size = 0; break; case 0x20000000: /* DDR_32BIT_512MB */ - gd->bd->bi_dram[0].size = 0x20000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x20000000; + gd->dram[1].size = 0; break; case 0x40000000: if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */ - gd->bd->bi_dram[0].size = 0x20000000; - gd->bd->bi_dram[1].size = 0x20000000; + gd->dram[0].size = 0x20000000; + gd->dram[1].size = 0x20000000; } else { /* DDR_64BIT_1GB */ - gd->bd->bi_dram[0].size = 0x40000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x40000000; + gd->dram[1].size = 0; } break; case 0x80000000: /* DDR_64BIT_2GB */ - gd->bd->bi_dram[0].size = 0x40000000; - gd->bd->bi_dram[1].size = 0x40000000; + gd->dram[0].size = 0x40000000; + gd->dram[1].size = 0x40000000; break; case 0xEFF00000: /* DDR_64BIT_4GB */ - gd->bd->bi_dram[0].size = 0x70000000; - gd->bd->bi_dram[1].size = 0x7FF00000; + gd->dram[0].size = 0x70000000; + gd->dram[1].size = 0x7FF00000; break; } diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c index 9fea4f86d5a..33f7ec6d048 100644 --- a/board/elgin/elgin_rv1108/elgin_rv1108.c +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -66,8 +66,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = 0x60000000; - gd->bd->bi_dram[0].size = 0x8000000; + gd->dram[0].start = 0x60000000; + gd->dram[0].size = 0x8000000; return 0; } diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index dce69abdfd1..3d76c936073 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -141,8 +141,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index eb10cd5143d..5e560a7f927 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -532,17 +532,17 @@ int dram_init_banksize(void) /* set global data memory */ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100; - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; /* Number of Row: 14 bits */ if ((reg_val >> 28) == 14) - gd->bd->bi_dram[0].size -= 0x20000000; + gd->dram[0].size -= 0x20000000; /* Number of Memory Chips */ if ((reg_val & 0x3) > 1) { - gd->bd->bi_dram[1].start = 0x80000000; - gd->bd->bi_dram[1].size = 0x40000000; + gd->dram[1].start = 0x80000000; + gd->dram[1].size = 0x40000000; } return 0; } diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index cb9b88a1a58..d3a385bf6b7 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -71,11 +71,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = mx53_dram_size[0]; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = mx53_dram_size[0]; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = mx53_dram_size[1]; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = mx53_dram_size[1]; return 0; } diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 5e60ab9d7b7..ba0465cf96f 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -456,23 +456,23 @@ int dram_init_banksize(void) * 0x3e00,0000 - 0x3fff,ffff: OP-TEE */ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = 0x05e00000; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = 0x05e00000; - gd->bd->bi_dram[1].start = 0x05f00000; - gd->bd->bi_dram[1].size = 0x00001000; + gd->dram[1].start = 0x05f00000; + gd->dram[1].size = 0x00001000; - gd->bd->bi_dram[2].start = 0x05f02000; - gd->bd->bi_dram[2].size = 0x00efd000; + gd->dram[2].start = 0x05f02000; + gd->dram[2].size = 0x00efd000; - gd->bd->bi_dram[3].start = 0x06e00000; - gd->bd->bi_dram[3].size = 0x0060f000; + gd->dram[3].start = 0x06e00000; + gd->dram[3].size = 0x0060f000; - gd->bd->bi_dram[4].start = 0x07410000; - gd->bd->bi_dram[4].size = 0x1aaf0000; + gd->dram[4].start = 0x07410000; + gd->dram[4].size = 0x1aaf0000; - gd->bd->bi_dram[5].start = 0x22000000; - gd->bd->bi_dram[5].size = 0x1c000000; + gd->dram[5].start = 0x22000000; + gd->dram[5].size = 0x1c000000; return 0; } diff --git a/board/hisilicon/hikey960/hikey960.c b/board/hisilicon/hikey960/hikey960.c index fb56762fff6..e7908d4c048 100644 --- a/board/hisilicon/hikey960/hikey960.c +++ b/board/hisilicon/hikey960/hikey960.c @@ -74,8 +74,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c index c3ea080ff75..dbab67d6f65 100644 --- a/board/hisilicon/poplar/poplar.c +++ b/board/hisilicon/poplar/poplar.c @@ -87,8 +87,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET; - gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start; + gd->dram[0].start = KERNEL_TEXT_OFFSET; + gd->dram[0].size = gd->ram_size - gd->dram[0].start; return 0; } diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c index efb7b49cbe0..07668bae7a9 100644 --- a/board/k+p/kp_imx53/kp_imx53.c +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -39,8 +39,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c index 51938a1b4d8..e37d4e767db 100644 --- a/board/keymile/pg-wcom-ls102xa/ddr.c +++ b/board/keymile/pg-wcom-ls102xa/ddr.c @@ -84,8 +84,8 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 8a9502037fb..ce778bc0849 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -175,8 +175,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < nbanks; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } fdt_fixup_memory_banks(blob, base, size, nbanks); diff --git a/board/kontron/sl28/spl_atf.c b/board/kontron/sl28/spl_atf.c index 0710316a48b..cc741dea504 100644 --- a/board/kontron/sl28/spl_atf.c +++ b/board/kontron/sl28/spl_atf.c @@ -36,9 +36,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - dram_regions_info.region[i].addr = gd->bd->bi_dram[i].start; - dram_regions_info.region[i].size = gd->bd->bi_dram[i].size; - dram_regions_info.total_dram_size += gd->bd->bi_dram[i].size; + dram_regions_info.region[i].addr = gd->dram[i].start; + dram_regions_info.region[i].size = gd->dram[i].size; + dram_regions_info.total_dram_size += gd->dram[i].size; } bl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry, diff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c index e1ff041c54f..ba922b43064 100644 --- a/board/liebherr/btt/btt.c +++ b/board/liebherr/btt/btt.c @@ -239,7 +239,7 @@ int spl_start_uboot(void) static const char *get_board_name(void) { - if (gd->bd->bi_dram[0].size == SZ_128M) + if (gd->dram[0].size == SZ_128M) return STR_BTTC; return STR_BTT3; diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index fc76d5765fa..5e76942783f 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -69,11 +69,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = mx53_dram_size[0]; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = mx53_dram_size[0]; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = mx53_dram_size[1]; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = mx53_dram_size[1]; return 0; } diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 05c4dd187fe..68d516c7db8 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -57,7 +57,7 @@ int dram_init_banksize(void) { phys_size_t ram_size = gd->ram_size; - gd->bd->bi_dram[0].start = 0; + gd->dram[0].start = 0; #if defined(CONFIG_SYS_MEM_TOP_HIDE) ram_size += CONFIG_SYS_MEM_TOP_HIDE; @@ -69,25 +69,25 @@ int dram_init_banksize(void) case DRAM_1GB_SIZE: case DRAM_2GB_ECC_SIZE: case DRAM_2GB_SIZE: - gd->bd->bi_dram[0].size = ram_size; - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = ram_size; + gd->dram[1].start = 0; + gd->dram[1].size = 0; break; case DRAM_4GB_ECC_SIZE: - gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; - gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; - gd->bd->bi_dram[1].size = DRAM_2GB_SIZE - + gd->dram[0].size = DRAM_2GB_SIZE; + gd->dram[1].start = DRAM_4GB_SIZE; + gd->dram[1].size = DRAM_2GB_SIZE - (DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE); break; case DRAM_4GB_SIZE: - gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; - gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; - gd->bd->bi_dram[1].size = DRAM_2GB_SIZE; + gd->dram[0].size = DRAM_2GB_SIZE; + gd->dram[1].start = DRAM_4GB_SIZE; + gd->dram[1].size = DRAM_2GB_SIZE; break; default: - gd->bd->bi_dram[0].size = DRAM_1GB_SIZE; - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = DRAM_1GB_SIZE; + gd->dram[1].start = 0; + gd->dram[1].size = 0; break; } diff --git a/board/nxp/imxrt1020-evk/imxrt1020-evk.c b/board/nxp/imxrt1020-evk/imxrt1020-evk.c index 11dbef84688..6843b33679d 100644 --- a/board/nxp/imxrt1020-evk/imxrt1020-evk.c +++ b/board/nxp/imxrt1020-evk/imxrt1020-evk.c @@ -73,7 +73,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/imxrt1050-evk/imxrt1050-evk.c b/board/nxp/imxrt1050-evk/imxrt1050-evk.c index 056489932ac..19d068fc626 100644 --- a/board/nxp/imxrt1050-evk/imxrt1050-evk.c +++ b/board/nxp/imxrt1050-evk/imxrt1050-evk.c @@ -78,7 +78,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/imxrt1170-evk/imxrt1170-evk.c b/board/nxp/imxrt1170-evk/imxrt1170-evk.c index 047aea8181a..3afd5ae2136 100644 --- a/board/nxp/imxrt1170-evk/imxrt1170-evk.c +++ b/board/nxp/imxrt1170-evk/imxrt1170-evk.c @@ -73,7 +73,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/ls1021aqds/ddr.c b/board/nxp/ls1021aqds/ddr.c index fd897e832c8..8d07f6110ce 100644 --- a/board/nxp/ls1021aqds/ddr.c +++ b/board/nxp/ls1021aqds/ddr.c @@ -192,8 +192,8 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c index 196e25931f3..e1e83137f4d 100644 --- a/board/nxp/ls1028a/ls1028a.c +++ b/board/nxp/ls1028a/ls1028a.c @@ -149,7 +149,7 @@ int board_early_init_f(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -202,10 +202,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/ls1043aqds/ls1043aqds.c b/board/nxp/ls1043aqds/ls1043aqds.c index 0f115c16232..dba93add698 100644 --- a/board/nxp/ls1043aqds/ls1043aqds.c +++ b/board/nxp/ls1043aqds/ls1043aqds.c @@ -542,10 +542,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 reg; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1043ardb/ls1043ardb.c b/board/nxp/ls1043ardb/ls1043ardb.c index bba041065b5..678c529cf55 100644 --- a/board/nxp/ls1043ardb/ls1043ardb.c +++ b/board/nxp/ls1043ardb/ls1043ardb.c @@ -305,10 +305,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046afrwy/ls1046afrwy.c b/board/nxp/ls1046afrwy/ls1046afrwy.c index 8889c24f1f0..6c35c0a4347 100644 --- a/board/nxp/ls1046afrwy/ls1046afrwy.c +++ b/board/nxp/ls1046afrwy/ls1046afrwy.c @@ -198,10 +198,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046aqds/ls1046aqds.c b/board/nxp/ls1046aqds/ls1046aqds.c index 679b0b2235f..ddd9993986f 100644 --- a/board/nxp/ls1046aqds/ls1046aqds.c +++ b/board/nxp/ls1046aqds/ls1046aqds.c @@ -426,10 +426,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 reg; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046ardb/ls1046ardb.c b/board/nxp/ls1046ardb/ls1046ardb.c index 83b280f7646..6677e271029 100644 --- a/board/nxp/ls1046ardb/ls1046ardb.c +++ b/board/nxp/ls1046ardb/ls1046ardb.c @@ -171,10 +171,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1088a/ls1088a.c b/board/nxp/ls1088a/ls1088a.c index 5783dd8a403..1b477e83676 100644 --- a/board/nxp/ls1088a/ls1088a.c +++ b/board/nxp/ls1088a/ls1088a.c @@ -830,7 +830,7 @@ int board_init(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -959,8 +959,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } #ifdef CONFIG_RESV_RAM diff --git a/board/nxp/ls2080aqds/ls2080aqds.c b/board/nxp/ls2080aqds/ls2080aqds.c index aba0560181a..325dc817aaf 100644 --- a/board/nxp/ls2080aqds/ls2080aqds.c +++ b/board/nxp/ls2080aqds/ls2080aqds.c @@ -253,12 +253,12 @@ int misc_init_r(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->dram[2].size) { puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); + print_size(gd->dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } #endif @@ -302,10 +302,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/ls2080ardb/ls2080ardb.c b/board/nxp/ls2080ardb/ls2080ardb.c index d08598d1c62..9dec818280b 100644 --- a/board/nxp/ls2080ardb/ls2080ardb.c +++ b/board/nxp/ls2080ardb/ls2080ardb.c @@ -359,12 +359,12 @@ int misc_init_r(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->dram[2].size) { puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); + print_size(gd->dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } #endif @@ -487,10 +487,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) size = calloc(total_memory_banks, sizeof(u64)); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/lx2160a/lx2160a.c b/board/nxp/lx2160a/lx2160a.c index b7a6ccf46aa..10729dfaf24 100644 --- a/board/nxp/lx2160a/lx2160a.c +++ b/board/nxp/lx2160a/lx2160a.c @@ -573,7 +573,7 @@ void detail_board_ddr_info(void) puts("\nDDR "); for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - ddr_size += gd->bd->bi_dram[i].size; + ddr_size += gd->dram[i].size; print_size(ddr_size, ""); print_ddr_info(0); } @@ -808,8 +808,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the three GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } #ifdef CONFIG_RESV_RAM diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 3cdcbf2ecc9..6df521d789f 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -93,7 +93,7 @@ int dram_init_banksize(void) { u8 ram_size; - memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS); if (!IS_ENABLED(CONFIG_CPU_V7R)) return fdtdec_setup_memory_banksize(); @@ -101,34 +101,34 @@ int dram_init_banksize(void) ram_size = phytec_get_am62_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x40000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x40000000; gd->ram_size = 0x40000000; break; case EEPROM_RAM_SIZE_2GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; break; case EEPROM_RAM_SIZE_4GB: /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR upper region */ - gd->bd->bi_dram[1].start = 0x880000000; - gd->bd->bi_dram[1].size = 0x80000000; + gd->dram[1].start = 0x880000000; + gd->dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif break; default: /* Continue with default 2GB setup */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; printf("DDR size %d is not supported\n", ram_size); } @@ -186,8 +186,8 @@ int do_board_detect(void) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } ret = fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c index 114aa217023..5e077872152 100644 --- a/board/phytec/phycore_am64x/phycore-am64x.c +++ b/board/phytec/phycore_am64x/phycore-am64x.c @@ -66,7 +66,7 @@ int dram_init_banksize(void) { u8 ram_size; - memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS); if (!IS_ENABLED(CONFIG_CPU_V7R)) return fdtdec_setup_memory_banksize(); @@ -74,21 +74,21 @@ int dram_init_banksize(void) ram_size = phytec_get_am64_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x40000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x40000000; gd->ram_size = 0x40000000; break; case EEPROM_RAM_SIZE_2GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; break; default: /* Continue with default 2GB setup */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; printf("DDR size %d is not supported\n", ram_size); } @@ -109,8 +109,8 @@ int do_board_detect(void) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } return fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c index 9fc63febdac..a738e3542e2 100644 --- a/board/phytium/durian/durian.c +++ b/board/phytium/durian/durian.c @@ -31,8 +31,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c index 6824454cdf4..421e193e730 100644 --- a/board/phytium/pe2201/pe2201.c +++ b/board/phytium/pe2201/pe2201.c @@ -44,8 +44,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index b0a1484c0fa..885c660a289 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -356,9 +356,9 @@ int dram_init_banksize(void) /* Update gd->ram_size to reflect total RAM across all banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (gd->bd->bi_dram[i].size == 0) + if (gd->dram[i].size == 0) break; - total_size += gd->bd->bi_dram[i].size; + total_size += gd->dram[i].size; } gd->ram_size = total_size; diff --git a/board/renesas/common/rcar64-common.c b/board/renesas/common/rcar64-common.c index 3d537be4d02..09667d46d99 100644 --- a/board/renesas/common/rcar64-common.c +++ b/board/renesas/common/rcar64-common.c @@ -49,15 +49,15 @@ int dram_init_banksize(void) return 0; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (gd->bd->bi_dram[bank].start != 0x48000000) + if (gd->dram[bank].start != 0x48000000) continue; /* * If this U-Boot runs in EL3, make the bottom 128 MiB * available for loading of follow up firmware blobs. */ - gd->bd->bi_dram[bank].start -= 0x8000000; - gd->bd->bi_dram[bank].size += 0x8000000; + gd->dram[bank].start -= 0x8000000; + gd->dram[bank].size += 0x8000000; break; } diff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c index 8153aed15e3..9245bf348f8 100644 --- a/board/renesas/genmai/genmai.c +++ b/board/renesas/genmai/genmai.c @@ -43,7 +43,7 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c index a229542ba7e..1503de675d5 100644 --- a/board/renesas/sparrowhawk/sparrowhawk.c +++ b/board/renesas/sparrowhawk/sparrowhawk.c @@ -261,10 +261,10 @@ void renesas_dram_init_banksize(void) /* 16 GiB device, adjust memory map. */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (gd->bd->bi_dram[bank].start == 0x480000000ULL) - gd->bd->bi_dram[bank].size = 0x180000000ULL; - else if (gd->bd->bi_dram[bank].start == 0x600000000ULL) - gd->bd->bi_dram[bank].size = 0x200000000ULL; + if (gd->dram[bank].start == 0x480000000ULL) + gd->dram[bank].size = 0x180000000ULL; + else if (gd->dram[bank].start == 0x600000000ULL) + gd->dram[bank].size = 0x200000000ULL; } } diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 1f78654b685..7a0a93c1afe 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -103,8 +103,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index cc58e0f3a38..0ff49dceb9e 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -97,8 +97,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 5d5edd9f253..b5664296a81 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -150,8 +150,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index e70b4a82687..130136e8596 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -67,8 +67,8 @@ int dram_init_banksize(void) addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; + gd->dram[i].start = addr; + gd->dram[i].size = size; } return 0; diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index eed1c2450fa..da3510023c4 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -115,7 +115,7 @@ int board_init(void) ulong size = CONFIG_SYS_MEM_TOP_HIDE; gd->ram_size -= size; - gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; + gd->dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; #endif exynos_init(); @@ -143,8 +143,8 @@ int dram_init_banksize(void) addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; + gd->dram[i].start = addr; + gd->dram[i].size = size; } return 0; diff --git a/board/samsung/exynos-mobile/exynos-mobile.c b/board/samsung/exynos-mobile/exynos-mobile.c index 6b2b1523663..d91e2e7d3f2 100644 --- a/board/samsung/exynos-mobile/exynos-mobile.c +++ b/board/samsung/exynos-mobile/exynos-mobile.c @@ -346,8 +346,8 @@ int dram_init_banksize(void) unsigned int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = mem_map[i + 1].phys; - gd->bd->bi_dram[i].size = mem_map[i + 1].size; + gd->dram[i].start = mem_map[i + 1].phys; + gd->dram[i].size = mem_map[i + 1].size; } return 0; diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index a1047f3fd2a..96a411233d1 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -43,12 +43,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = PHYS_SDRAM_2_SIZE; + gd->dram[2].start = PHYS_SDRAM_3; + gd->dram[2].size = PHYS_SDRAM_3_SIZE; return 0; } diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 7d0b0fcb0ae..7e992c23a1b 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -56,8 +56,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 5a4874b29cd..f013893b465 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -57,17 +57,17 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, + gd->dram[2].start = PHYS_SDRAM_3; + gd->dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE); - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, + gd->dram[3].start = PHYS_SDRAM_4; + gd->dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); return 0; diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index 79cf34b40eb..69d3b9d61d3 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -397,20 +397,20 @@ int dram_init_banksize(void) if (gd->ram_size > SZ_2G) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = SZ_2G; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = SZ_2G; /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = CFG_SYS_SDRAM_BASE1; + gd->dram[1].size = gd->ram_size - SZ_2G; } else { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[1].start = 0; + gd->dram[1].size = 0; } return 0; diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index 556a9ed527e..a7bd08f69ad 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -170,11 +170,11 @@ int dram_init_banksize(void) struct draminfo_entry *ent = synquacer_draminfo->entry; int i; - for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { + for (i = 0; i < ARRAY_SIZE(gd->dram); i++) { if (i < synquacer_draminfo->nr_regions) { debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); - gd->bd->bi_dram[i].start = ent[i].base; - gd->bd->bi_dram[i].size = ent[i].size; + gd->dram[i].start = ent[i].base; + gd->dram[i].size = ent[i].size; } } diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index f5174720434..a1b0265d5ac 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -18,8 +18,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/ste/stemmy/stemmy.c b/board/ste/stemmy/stemmy.c index 826c002907d..66330184af8 100644 --- a/board/ste/stemmy/stemmy.c +++ b/board/ste/stemmy/stemmy.c @@ -70,8 +70,8 @@ int dram_init_banksize(void) if (t->hdr.tag != ATAG_MEM) continue; - gd->bd->bi_dram[bank].start = t->u.mem.start; - gd->bd->bi_dram[bank].size = t->u.mem.size; + gd->dram[bank].start = t->u.mem.start; + gd->dram[bank].size = t->u.mem.size; if (++bank == CONFIG_NR_DRAM_BANKS) break; } diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 0966db2bb62..6f1fed43e36 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -643,11 +643,11 @@ int dram_init_banksize(void) ram_size = board_ti_get_emif_size(); - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = get_effective_memsize(); if (ram_size > CFG_MAX_MEM_MAPPED) { - gd->bd->bi_dram[1].start = 0x200000000; - gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; + gd->dram[1].start = 0x200000000; + gd->dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; } return 0; diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index a92aa5cfc67..43330993955 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -117,8 +117,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) } nbanks = 1; - start[0] = bd->bi_dram[0].start; - size[0] = bd->bi_dram[0].size; + start[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; /* adjust memory start address for LPAE */ if (lpae) { diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 69a8a18d3a7..c63812bd966 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -288,13 +288,13 @@ int ft_board_setup(void *blob, struct bd_info *bd) * Reserve 1MB of memory for M4 (1MiB is also the minimum * alignment for Linux due to MMU section size restrictions). */ - start[0] = gd->bd->bi_dram[0].start; + start[0] = gd->dram[0].start; size[0] = SZ_256M - SZ_1M; /* If needed, create a second entry for memory beyond 256M */ - if (gd->bd->bi_dram[0].size > SZ_256M) { - start[1] = gd->bd->bi_dram[0].start + SZ_256M; - size[1] = gd->bd->bi_dram[0].size - SZ_256M; + if (gd->dram[0].size > SZ_256M) { + start[1] = gd->dram[0].start + SZ_256M; + size[1] = gd->dram[0].size - SZ_256M; areas = 2; } diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 19ac2ae9313..26af1af2069 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -44,7 +44,7 @@ int dram_init_banksize(void) printf("Error setting up memory banksize. %d\n", ret); /* Use the detected RAM size, we only support 1 bank right now. */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return ret; } diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c index 1234b3887c6..ec7775e06a7 100644 --- a/board/toradex/verdin-am62p/verdin-am62p.c +++ b/board/toradex/verdin-am62p/verdin-am62p.c @@ -78,7 +78,7 @@ int dram_init_banksize(void) printf("Error setting up memory banksize. %d\n", ret); /* Use the detected RAM size, we only support 1 bank right now. */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return ret; } diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c index ac8c9a9a81a..5c45f9932c5 100644 --- a/board/traverse/ten64/ten64.c +++ b/board/traverse/ten64/ten64.c @@ -148,7 +148,7 @@ int fsl_initdram(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -277,8 +277,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; /* reduce size if reserved memory is within this bank */ if (IS_ENABLED(CONFIG_RESV_RAM) && RESV_MEM_IN_BANK(i)) size[i] = gd->arch.resv_ram - base[i]; diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c index 05ecb75406b..d8eff203a56 100644 --- a/board/xilinx/zynq/cmds.c +++ b/board/xilinx/zynq/cmds.c @@ -347,10 +347,10 @@ static int zynq_verify_image(u32 src_ptr) * This validation is just for PS DDR. * TODO: Update this for PL DDR check as well. */ - if (part_load_addr < gd->bd->bi_dram[0].start && + if (part_load_addr < gd->dram[0].start && ((part_load_addr + part_data_len) > - (gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size))) { + (gd->dram[0].start + + gd->dram[0].size))) { printf("INVALID_LOAD_ADDRESS_FAIL\n"); return -1; } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index eb41f84c198..a12c039d8c9 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -279,8 +279,8 @@ int dram_init(void) #else int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = get_effective_memsize(); mem_map_fill(); diff --git a/boot/image-board.c b/boot/image-board.c index 265f29d44ff..67938fdd200 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -118,7 +118,7 @@ phys_addr_t env_get_bootm_low(void) #if defined(CFG_SYS_SDRAM_BASE) return CFG_SYS_SDRAM_BASE; #elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV) - return gd->bd->bi_dram[0].start; + return gd->dram[0].start; #else return 0; #endif diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 1150131a11e..9e0e0f93edd 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -260,8 +260,8 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) of_start = NULL; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* DRAM bank addresses are too low, skip it. */ if (start + size < low) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index ddf77303735..bf1eca75904 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -77,15 +77,15 @@ void bdinfo_print_mhz(const char *name, unsigned long hz) printf("%-12s= %6s MHz\n", name, strmhz(buf, hz)); } -static void print_bi_dram(const struct bd_info *bd) +static void print_dram(const struct bd_info *bd) { int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { + if (gd->dram[i].size) { bdinfo_print_num_l("DRAM bank", i); - bdinfo_print_num_ll("-> start", bd->bi_dram[i].start); - bdinfo_print_num_ll("-> size", bd->bi_dram[i].size); + bdinfo_print_num_ll("-> start", gd->dram[i].start); + bdinfo_print_num_ll("-> size", gd->dram[i].size); } } } @@ -144,7 +144,7 @@ static int bdinfo_print_all(struct bd_info *bd) bdinfo_print_num_l("bd address", (ulong)bd); #endif bdinfo_print_num_l("boot_params", (ulong)bd->bi_boot_params); - print_bi_dram(bd); + print_dram(bd); bdinfo_print_num_l("flashstart", (ulong)bd->bi_flashstart); bdinfo_print_num_l("flashsize", (ulong)bd->bi_flashsize); bdinfo_print_num_l("flashoffset", (ulong)bd->bi_flashoffset); @@ -199,7 +199,7 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) print_eth(); return CMD_RET_SUCCESS; case 'm': - print_bi_dram(bd); + print_dram(bd); return CMD_RET_SUCCESS; default: return CMD_RET_USAGE; diff --git a/cmd/ti/ddr4.c b/cmd/ti/ddr4.c index a8d71d11a91..36277cc154c 100644 --- a/cmd/ti/ddr4.c +++ b/cmd/ti/ddr4.c @@ -227,10 +227,10 @@ static int do_ddr4_ecc_inject(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - if (!((start_addr >= gd->bd->bi_dram[0].start && - (start_addr <= (gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - 1))) || - (start_addr >= gd->bd->bi_dram[1].start && - (start_addr <= (gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size - 1))))) { + if (!((start_addr >= gd->dram[0].start && + (start_addr <= (gd->dram[0].start + gd->dram[0].size - 1))) || + (start_addr >= gd->dram[1].start && + (start_addr <= (gd->dram[1].start + gd->dram[1].size - 1))))) { puts("Address is not in the DDR range\n"); return CMD_RET_FAILURE; } diff --git a/cmd/ufetch.c b/cmd/ufetch.c index e7b5d773f5e..763ab42c48a 100644 --- a/cmd/ufetch.c +++ b/cmd/ufetch.c @@ -202,8 +202,8 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc, printf("CPU: " RESET CONFIG_SYS_ARCH " (%d cores, 1 in use)\n", n_cpus); break; case MEMORY: - for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->bd->bi_dram[j].size; j++) - size += gd->bd->bi_dram[j].size; + for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->dram[j].size; j++) + size += gd->dram[j].size; printf("Memory:" RESET " "); print_size(size, "\n"); break; diff --git a/common/board_f.c b/common/board_f.c index fdb3577fec0..a3abec35271 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -222,11 +222,11 @@ static int show_dram_config(void) debug("\nRAM Configuration:\n"); for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; debug("Bank #%d: %llx ", i, - (unsigned long long)(gd->bd->bi_dram[i].start)); + (unsigned long long)(gd->dram[i].start)); #ifdef DEBUG - print_size(gd->bd->bi_dram[i].size, "\n"); + print_size(gd->dram[i].size, "\n"); #endif } debug("\nDRAM: "); @@ -244,8 +244,8 @@ static int show_dram_config(void) __weak int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); return 0; } diff --git a/common/init/handoff.c b/common/init/handoff.c index a7cd065fb38..a4d9d14393b 100644 --- a/common/init/handoff.c +++ b/common/init/handoff.c @@ -12,14 +12,13 @@ DECLARE_GLOBAL_DATA_PTR; void handoff_save_dram(struct spl_handoff *ho) { - struct bd_info *bd = gd->bd; int i; ho->ram_size = gd->ram_size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - ho->ram_bank[i].start = bd->bi_dram[i].start; - ho->ram_bank[i].size = bd->bi_dram[i].size; + ho->ram_bank[i].start = gd->dram[i].start; + ho->ram_bank[i].size = gd->dram[i].size; } } @@ -30,11 +29,10 @@ void handoff_load_dram_size(struct spl_handoff *ho) void handoff_load_dram_banks(struct spl_handoff *ho) { - struct bd_info *bd = gd->bd; int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - bd->bi_dram[i].start = ho->ram_bank[i].start; - bd->bi_dram[i].size = ho->ram_bank[i].size; + gd->dram[i].start = ho->ram_bank[i].start; + gd->dram[i].size = ho->ram_bank[i].size; } } diff --git a/drivers/bootcount/bootcount_ram.c b/drivers/bootcount/bootcount_ram.c index 33e157b865a..f726d9ab016 100644 --- a/drivers/bootcount/bootcount_ram.c +++ b/drivers/bootcount/bootcount_ram.c @@ -27,7 +27,7 @@ void bootcount_store(ulong a) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; save_addr = (ulong *)(size - BOOTCOUNT_ADDR); writel(a, save_addr); writel(CONFIG_SYS_BOOTCOUNT_MAGIC, &save_addr[1]); @@ -50,7 +50,7 @@ ulong bootcount_load(void) int i, tmp; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; save_addr = (ulong *)(size - BOOTCOUNT_ADDR); counter = readl(&save_addr[0]); diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index b36a765a5de..2d2b72cf766 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -104,7 +104,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); return -ENXIO; @@ -158,7 +158,7 @@ int sdram_mmr_init_full(struct udevice *dev) sdram_set_firewall(&bd); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; debug("DDR: HMC init success\n"); diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c index ee66c72157a..d14e4bc5dcc 100644 --- a/drivers/ddr/altera/sdram_agilex5.c +++ b/drivers/ddr/altera/sdram_agilex5.c @@ -302,7 +302,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, gd->bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); ret = -ENXIO; @@ -345,19 +345,19 @@ int sdram_mmr_init_full(struct udevice *dev) for (i = 0; i < config_dram_banks; i++) { remaining_size = hw_size - size_counter; if (remaining_size <= dram_bank_info[i].max_size) { - gd->bd->bi_dram[i].start = dram_bank_info[i].start; - gd->bd->bi_dram[i].size = remaining_size; + gd->dram[i].start = dram_bank_info[i].start; + gd->dram[i].size = remaining_size; debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n", - i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); + i, gd->dram[i].start, gd->dram[i].size); break; } - gd->bd->bi_dram[i].start = dram_bank_info[i].start; - gd->bd->bi_dram[i].size = dram_bank_info[i].max_size; + gd->dram[i].start = dram_bank_info[i].start; + gd->dram[i].size = dram_bank_info[i].max_size; debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n", - i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); - size_counter += gd->bd->bi_dram[i].size; + i, gd->dram[i].start, gd->dram[i].size); + size_counter += gd->dram[i].size; } gd->ram_size = hw_size; @@ -408,7 +408,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR: firewall init success\n"); - priv->info.base = gd->bd->bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; /* Ending DDR driver initialization success tracking */ diff --git a/drivers/ddr/altera/sdram_agilex7m.c b/drivers/ddr/altera/sdram_agilex7m.c index 9b3cc5c7b86..e4d522202d8 100644 --- a/drivers/ddr/altera/sdram_agilex7m.c +++ b/drivers/ddr/altera/sdram_agilex7m.c @@ -375,7 +375,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { printf("%s: Failed to decode memory node\n", memory_type_in_use(dev)); @@ -484,7 +484,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("%s: firewall init success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; /* Ending DDR driver initialization success tracking */ diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index c281f711fdf..9cc809b8001 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -674,9 +674,9 @@ static void sdram_size_check(void) debug("DDR: Running SDRAM size sanity check\n"); - ram_check = get_ram_size((long *)gd->bd->bi_dram[0].start, - gd->bd->bi_dram[0].size); - if (ram_check != gd->bd->bi_dram[0].size) { + ram_check = get_ram_size((long *)gd->dram[0].start, + gd->dram[0].size); + if (ram_check != gd->dram[0].size) { puts("DDR: SDRAM size check failed!\n"); hang(); } @@ -719,14 +719,14 @@ int ddr_calibration_sequence(void) /* setup the dram info within bd */ dram_init_banksize(); - if (gd->ram_size != gd->bd->bi_dram[0].size) { + if (gd->ram_size != gd->dram[0].size) { printf("DDR: Warning: DRAM size from device tree (%ld MiB)\n", - gd->bd->bi_dram[0].size >> 20); + gd->dram[0].size >> 20); printf(" mismatch with hardware (%ld MiB).\n", gd->ram_size >> 20); } - if (gd->bd->bi_dram[0].size > gd->ram_size) { + if (gd->dram[0].size > gd->ram_size) { printf("DDR: Error: DRAM size from device tree is greater\n"); printf(" than hardware size.\n"); hang(); diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 17ec6afa82b..900d4f59989 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -2279,7 +2279,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { debug("%s: Failed to decode memory node\n", __func__); return -1; @@ -2287,7 +2287,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR: %lld MiB\n", gd->ram_size >> 20); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; sdram_size_check(&bd); diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 4ac4c79e0ac..6664090f86a 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -285,7 +285,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); return -1; @@ -328,7 +328,7 @@ int sdram_mmr_init_full(struct udevice *dev) sdram_size_check(&bd); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; debug("DDR: HMC init success\n"); diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 8ee7049b164..93df3d1812a 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -150,8 +150,8 @@ void sdram_init_ecc_bits(struct bd_info *bd) icache_enable(); - start_addr = bd->bi_dram[0].start; - size = bd->bi_dram[0].size; + start_addr = gd->dram[0].start; + size = gd->dram[0].size; /* Initialize small block for page table */ memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF); @@ -174,8 +174,8 @@ void sdram_init_ecc_bits(struct bd_info *bd) if (bank >= CONFIG_NR_DRAM_BANKS) break; - start_addr = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; + start_addr = gd->dram[bank].start; + size = gd->dram[bank].size; } dcache_disable(); @@ -198,12 +198,12 @@ void sdram_size_check(struct bd_info *bd) phys_addr_t start = 0; phys_size_t remaining_size; - start = bd->bi_dram[bank].start; - remaining_size = bd->bi_dram[bank].size; + start = gd->dram[bank].start; + remaining_size = gd->dram[bank].size; debug("Checking bank %d: start=0x%llx, size=0x%llx\n", bank, start, remaining_size); - while (ram_check < bd->bi_dram[bank].size) { + while (ram_check < gd->dram[bank].size) { phys_size_t size, test_size, detected_size; size = min((phys_addr_t)SZ_1G, (phys_addr_t)remaining_size); @@ -232,7 +232,7 @@ void sdram_size_check(struct bd_info *bd) } ram_check += detected_size; - remaining_size = bd->bi_dram[bank].size - ram_check; + remaining_size = gd->dram[bank].size - ram_check; } total_ram_check += ram_check; @@ -292,10 +292,10 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) u32 lower, upper; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (!bd->bi_dram[i].size) + if (!gd->dram[i].size) continue; - value = bd->bi_dram[i].start; + value = gd->dram[i].start; /* Keep first 1MB of SDRAM memory region as secure region when * using ATF flow, where the ATF code is located. @@ -322,7 +322,7 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) (i * 4 * sizeof(u32))); /* Setting non-secure MPU limit and limit extended */ - value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + value = gd->dram[i].start + gd->dram[i].size - 1; lower = lower_32_bits(value); upper = upper_32_bits(value); @@ -354,10 +354,10 @@ static void sdram_set_firewall_f2sdram(struct bd_info *bd) phys_size_t value; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (!bd->bi_dram[i].size) + if (!gd->dram[i].size) continue; - value = bd->bi_dram[i].start; + value = gd->dram[i].start; /* Keep first 1MB of SDRAM memory region as secure region when * using ATF flow, where the ATF code is located. @@ -376,7 +376,7 @@ static void sdram_set_firewall_f2sdram(struct bd_info *bd) (i * 4 * sizeof(u32))); /* Setting limit and limit extended */ - value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + value = gd->dram[i].start + gd->dram[i].size - 1; lower = lower_32_bits(value); upper = upper_32_bits(value); diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c index 5af1953cd14..89d511c1a6f 100644 --- a/drivers/mmc/mvebu_mmc.c +++ b/drivers/mmc/mvebu_mmc.c @@ -375,8 +375,8 @@ static void mvebu_window_setup(const struct mmc *mmc) break; } - size = gd->bd->bi_dram[i].size; - base = gd->bd->bi_dram[i].start; + size = gd->dram[i].size; + base = gd->dram[i].start; if (size && attrib) { mvebu_mmc_write(mmc, WINDOW_CTRL(i), MVCPU_WIN_CTRL_DATA(size, diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 107a33aa9f5..4dc738980cb 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -256,8 +256,8 @@ static void set_dram_access(struct mvgbe_registers *regs) win_param.access_ctrl = EWIN_ACCESS_FULL; win_param.high_addr = 0; /* Get bank base and size */ - win_param.base_addr = gd->bd->bi_dram[i].start; - win_param.size = gd->bd->bi_dram[i].size; + win_param.base_addr = gd->dram[i].start; + win_param.size = gd->dram[i].size; if (win_param.size == 0) win_param.enable = 0; else diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index f58d542ef75..4bdd1f7477f 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1126,14 +1126,14 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, return 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - phys_addr_t start = bd->bi_dram[i].start; + if (gd->dram[i].size) { + phys_addr_t start = gd->dram[i].start; if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY)) - start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start); + start = virt_to_phys((void *)(uintptr_t)gd->dram[i].start); pci_set_region(hose->regions + hose->region_count++, - start, start, bd->bi_dram[i].size, + start, start, gd->dram[i].size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); } } diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 794a4168913..38ee17f063d 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -222,8 +222,8 @@ static void usb_brg_adrdec_setup(int index) break; } - size = gd->bd->bi_dram[i].size; - base = gd->bd->bi_dram[i].start; + size = gd->dram[i].size; + base = gd->dram[i].start; if ((size) && (attrib)) writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM, attrib, MVCPU_WIN_ENABLE), diff --git a/drivers/video/meson/meson_vpu.c b/drivers/video/meson/meson_vpu.c index ca627728743..a686faf9f58 100644 --- a/drivers/video/meson/meson_vpu.c +++ b/drivers/video/meson/meson_vpu.c @@ -81,8 +81,8 @@ cvbs: meson_fb.fb_size = ALIGN(meson_fb.xsize * meson_fb.ysize * ((1 << VPU_MAX_LOG2_BPP) / 8) + MESON_VPU_OVERSCAN, EFI_PAGE_SIZE); - meson_fb.base = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - meson_fb.fb_size; + meson_fb.base = gd->dram[0].start + + gd->dram[0].size - meson_fb.fb_size; /* Override the framebuffer address */ uc_plat->base = meson_fb.base; @@ -175,8 +175,8 @@ static void meson_vpu_setup_simplefb(void *fdt) * at the end of the RAM and we strip this portion from the kernel * allowed region */ - mem_start = gd->bd->bi_dram[0].start; - mem_size = gd->bd->bi_dram[0].size - meson_fb.fb_size; + mem_start = gd->dram[0].start; + mem_size = gd->dram[0].size - meson_fb.fb_size; ret = fdt_fixup_memory_banks(fdt, &mem_start, &mem_size, 1); if (ret) { eprintf("Cannot setup simplefb: Error reserving memory\n"); diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 154641b9a69..ab36ee1595b 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -368,7 +368,7 @@ int sunxi_simplefb_setup(void *blob) return 0; /* Keep older kernels working */ } - start = gd->bd->bi_dram[0].start; + start = gd->dram[0].start; size = de2_plat->base - start; ret = fdt_fixup_memory_banks(blob, &start, &size, 1); if (ret) { diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 4a6a89ef9d2..fa492c661db 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -1336,7 +1336,7 @@ int sunxi_simplefb_setup(void *blob) * and e.g. Linux refuses to iomap RAM on ARM, see: * linux/arch/arm/mm/ioremap.c around line 301. */ - start = gd->bd->bi_dram[0].start; + start = gd->dram[0].start; size = sunxi_display->fb_addr - start; ret = fdt_fixup_memory_banks(blob, &start, &size, 1); if (ret) { diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index ba6a10cf2ad..ad7ebb1bbc9 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -457,6 +457,13 @@ struct global_data { */ struct upl *upl; #endif + /** + * @dram: array describing DRAM banks (start address and size for each bank) + */ + struct { /* RAM configuration */ + phys_addr_t start; + phys_size_t size; + } dram[CONFIG_NR_DRAM_BANKS]; }; #ifndef DO_DEPS_ONLY static_assert(sizeof(struct global_data) == GD_SIZE); diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 8c619c1b74a..931fe2f3274 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -59,10 +59,6 @@ struct bd_info { #endif ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ - struct { /* RAM configuration */ - phys_addr_t start; - phys_size_t size; - } bi_dram[CONFIG_NR_DRAM_BANKS]; }; #endif /* __ASSEMBLY__ */ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index a6aafb51854..36e330887cd 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -15,9 +15,9 @@ * Memory configurations */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 2bd1426c7d9..e823611d2e4 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -51,9 +51,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 14095b99f03..acd6eb6f8ac 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -86,9 +86,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 3707de254e1..65babf50546 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -81,9 +81,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/fdtdec.h b/include/fdtdec.h index 46eaa0da63c..51d9f14a9f2 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -57,6 +57,7 @@ struct fdt_memory { }; struct bd_info; +struct global_data; /** * enum fdt_source_t - indicates where the devicetree came from @@ -974,7 +975,7 @@ int fdtdec_setup_mem_size_base(void); int fdtdec_setup_mem_size_base_lowest(void); /** - * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram + * fdtdec_setup_memory_banksize() - decode and populate gd->dram * * Decode the /memory 'reg' property to determine the address and size of the * memory banks. Use this data to populate the global data board info with the @@ -1256,12 +1257,12 @@ int board_fdt_blob_setup(void **fdtp); * @param basep Returns base address of first memory bank (NULL to * ignore) * @param sizep Returns total memory size (NULL to ignore) - * @param bd Updated with the memory bank information (NULL to skip) + * @param gd_ptr Updated with the memory bank information (NULL to skip) * Return: 0 if OK, -ve on error */ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, phys_addr_t *basep, phys_size_t *sizep, - struct bd_info *bd); + struct global_data *gd_ptr); /** * fdtdec_get_srcname() - Get the name of where the devicetree comes from diff --git a/include/init.h b/include/init.h index c31ebd83b85..23466d3f153 100644 --- a/include/init.h +++ b/include/init.h @@ -80,7 +80,7 @@ int dram_init(void); * dram_init_banksize() - Set up DRAM bank sizes * * This can be implemented by boards to set up the DRAM bank information in - * gd->bd->bi_dram(). It is called just before relocation, after dram_init() + * gd->dram[] It is called just before relocation, after dram_init() * is called. * * If this is not provided, a default implementation will try to set up a diff --git a/lib/fdtdec.c b/lib/fdtdec.c index d0a84b5034b..b91e067106d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -35,6 +35,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -1142,14 +1143,14 @@ int fdtdec_setup_memory_banksize(void) if (ret != 0) return -EINVAL; - gd->bd->bi_dram[bank].start = (phys_addr_t)res.start; - gd->bd->bi_dram[bank].size = + gd->dram[bank].start = (phys_addr_t)res.start; + gd->dram[bank].size = (phys_size_t)(res.end - res.start + 1); debug("%s: DRAM Bank #%d: start = %pap, size = %pap\n", __func__, bank, - &gd->bd->bi_dram[bank].start, - &gd->bd->bi_dram[bank].size); + &gd->dram[bank].start, + &gd->dram[bank].size); } return 0; @@ -1930,7 +1931,7 @@ int fdtdec_resetup(int *rescan) int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, phys_addr_t *basep, phys_size_t *sizep, - struct bd_info *bd) + gd_t *gd_ptr) { int addr_cells, size_cells; const u32 *cell, *end; @@ -1982,8 +1983,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, } /* Note: if no matching subnode was found we use the parent node */ - if (bd) { - memset(bd->bi_dram, '\0', sizeof(bd->bi_dram[0]) * + if (gd_ptr) { + memset(gd_ptr->dram, '\0', sizeof(gd_ptr->dram[0]) * CONFIG_NR_DRAM_BANKS); } @@ -1999,8 +2000,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, if (addr_cells == 2) addr += (u64)fdt32_to_cpu(*cell++) << 32UL; addr += fdt32_to_cpu(*cell++); - if (bd) - bd->bi_dram[bank].start = addr; + if (gd_ptr) + gd_ptr->dram[bank].start = addr; if (basep && !bank) *basep = (phys_addr_t)addr; @@ -2022,8 +2023,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, } } - if (bd) - bd->bi_dram[bank].size = size; + if (gd_ptr) + gd_ptr->dram[bank].size = size; total_size += size; } diff --git a/lib/lmb.c b/lib/lmb.c index 779df35eb9c..77440a48486 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -555,12 +555,12 @@ static void lmb_reserve_uboot_region(void) #endif for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (!gd->bd->bi_dram[bank].size || - rsv_start < gd->bd->bi_dram[bank].start) + if (!gd->dram[bank].size || + rsv_start < gd->dram[bank].start) continue; /* Watch out for RAM at end of address space! */ - bank_end = gd->bd->bi_dram[bank].start + - gd->bd->bi_dram[bank].size - 1; + bank_end = gd->dram[bank].start + + gd->dram[bank].size - 1; if (rsv_start > bank_end) continue; if (bank_end > end) @@ -615,7 +615,6 @@ static void lmb_add_memory(void) phys_addr_t bank_end; phys_size_t size; u64 ram_top = gd->ram_top; - struct bd_info *bd = gd->bd; if (CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP)) return lmb_arch_add_memory(); @@ -625,22 +624,22 @@ static void lmb_add_memory(void) ram_top = 0x100000000ULL; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - size = bd->bi_dram[i].size; + size = gd->dram[i].size; if (size) { - lmb_add(bd->bi_dram[i].start, size); + lmb_add(gd->dram[i].start, size); if (!IS_ENABLED(CONFIG_LMB_LIMIT_DMA_BELOW_RAM_TOP)) continue; - bank_end = bd->bi_dram[i].start + size; + bank_end = gd->dram[i].start + size; /* * Reserve memory above ram_top as * no-overwrite so that it cannot be * allocated */ - if (bd->bi_dram[i].start >= ram_top) - lmb_reserve(bd->bi_dram[i].start, size, + if (gd->dram[i].start >= ram_top) + lmb_reserve(gd->dram[i].start, size, LMB_NOOVERWRITE); else if (bank_end > ram_top) lmb_reserve(ram_top, bank_end - ram_top, diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c index 7f4f1868c6a..7b7fb0894dd 100644 --- a/test/cmd/bdinfo.c +++ b/test/cmd/bdinfo.c @@ -138,16 +138,15 @@ static int lmb_test_dump_all(struct unit_test_state *uts) static int bdinfo_check_mem(struct unit_test_state *uts) { - struct bd_info *bd = gd->bd; int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { + if (gd->dram[i].size) { ut_assertok(test_num_l(uts, "DRAM bank", i)); ut_assertok(test_num_ll(uts, "-> start", - bd->bi_dram[i].start)); + gd->dram[i].start)); ut_assertok(test_num_ll(uts, "-> size", - bd->bi_dram[i].size)); + gd->dram[i].size)); } } -- cgit v1.3.1 From 08fc979a61aff7ede01a89d2b68b86128af64361 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 9 Jun 2026 03:25:11 +0200 Subject: Kconfig: power: pmic: fix typo While restyling Kconfig the script checkpatch.pl gives this info: WARNING: 'refered' may be misspelled - perhaps 'referred'? Fix by changing 'refered' to 'referred'. Signed-off-by: Johan Jonker Reviewed-by: Tom Rini --- drivers/power/pmic/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 5bc14842e66..8504ae2b079 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -376,7 +376,7 @@ config DM_PMIC_TPS80031 This config enables implementation of driver-model pmic uclass features for TPS80031/TPS80032 PMICs. The driver implements read/write operations. This is a Power Management IC with a decent set of peripherals from which - 5 Buck Converters refered as Switched-mode power supply (SMPS), 11 General- + 5 Buck Converters referred as Switched-mode power supply (SMPS), 11 General- Purpose Low-Dropout Voltage Regulators (LDO), USB OTG Module, Real-Time Clock (RTC) with Timer and Alarm Wake-Up, Two Digital PWM Outputs and more with I2C Compatible Interface. PMIC occupies 4 I2C addresses. -- cgit v1.3.1 From d20d285cf0b72347b7ba37694272206865d86824 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 9 Jun 2026 03:25:28 +0200 Subject: Kconfig: themal: fix typo While restyling Kconfig the script checkpatch.pl gives this info: WARNING: Possible repeated word: 'for' Fix by changing 'for for' to 'for'. Signed-off-by: Johan Jonker Reviewed-by: Tom Rini --- drivers/thermal/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 33a82ca3bf1..0015dec1062 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -47,7 +47,7 @@ config RCAR_GEN3_THERMAL config TI_DRA7_THERMAL bool "Temperature sensor driver for TI dra7xx SOCs" help - Enable thermal support for for the Texas Instruments DRA752 SoC family. + Enable thermal support for the Texas Instruments DRA752 SoC family. The driver supports reading CPU temperature. config TI_LM74_THERMAL -- cgit v1.3.1 From 2ffe9687013b615a6053e3a85080433626c6f3b5 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 9 Jun 2026 03:25:43 +0200 Subject: Kconfig: misc: add empty line Restyle by adding an empty line between configs. Signed-off-by: Johan Jonker Reviewed-by: Tom Rini --- drivers/misc/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index ea785793d18..0b52515c700 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -647,6 +647,7 @@ config IHS_FPGA gdsys devices, which supply the majority of the functionality offered by the devices. This driver supports both CON and CPU variants of the devices, depending on the device tree entry. + config ESM_K3 bool "Enable K3 ESM driver" depends on ARCH_K3 -- cgit v1.3.1 From 54cac2bf5cd53311d50b182d5885770126c8ce33 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Wed, 10 Jun 2026 16:39:01 +0200 Subject: Kconfig: i2c: restyle Restyle all Kconfigs for "i2c": Menu entries : no space left Menu attributes: 1 TAB Help text : 1 TAB + 2 spaces Replace '---help---' by 'help' Signed-off-by: Johan Jonker --- drivers/i2c/Kconfig | 140 +++++++++++++++++++++++----------------------- drivers/i2c/muxes/Kconfig | 2 +- 2 files changed, 71 insertions(+), 71 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 8c2f71b9fe2..ab5af17858c 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -110,16 +110,16 @@ config I2C_CROS_EC_TUNNEL config I2C_CROS_EC_LDO bool "Provide access to LDOs on the Chrome OS EC" depends on CROS_EC - ---help--- - On many Chromebooks the main PMIC is inaccessible to the AP. This is - often dealt with by using an I2C pass-through interface provided by - the EC. On some unfortunate models (e.g. Spring) the pass-through - is not available, and an LDO message is available instead. This - option enables a driver which provides very basic access to those - regulators, via the EC. We implement this as an I2C bus which - emulates just the TPS65090 messages we know about. This is done to - avoid duplicating the logic in the TPS65090 regulator driver for - enabling/disabling an LDO. + help + On many Chromebooks the main PMIC is inaccessible to the AP. This is + often dealt with by using an I2C pass-through interface provided by + the EC. On some unfortunate models (e.g. Spring) the pass-through + is not available, and an LDO message is available instead. This + option enables a driver which provides very basic access to those + regulators, via the EC. We implement this as an I2C bus which + emulates just the TPS65090 messages we know about. This is done to + avoid duplicating the logic in the TPS65090 regulator driver for + enabling/disabling an LDO. config I2C_SET_DEFAULT_BUS_NUM bool "Set default I2C bus number" @@ -180,9 +180,9 @@ config SYS_I2C_IPROC Say yes here to to enable the Broadco I2C driver. config SYS_I2C_FSL - bool "Freescale I2C bus driver" - depends on M68K || PPC - help + bool "Freescale I2C bus driver" + depends on M68K || PPC + help Add support for Freescale I2C busses as used on MPC8240, MPC8245, and MPC85xx processors. @@ -249,14 +249,14 @@ config SYS_I2C_DW_PCI controller. config SYS_I2C_AST2600 - bool "AST2600 I2C Controller" - depends on DM_I2C && ARCH_ASPEED - help - Say yes here to select AST2600 I2C Host Controller. The driver - support AST2600 I2C new mode register. This I2C controller supports: - _Standard-mode (up to 100 kHz) - _Fast-mode (up to 400 kHz) - _Fast-mode Plus (up to 1 MHz) + bool "AST2600 I2C Controller" + depends on DM_I2C && ARCH_ASPEED + help + Say yes here to select AST2600 I2C Host Controller. The driver + support AST2600 I2C new mode register. This I2C controller supports: + _Standard-mode (up to 100 kHz) + _Fast-mode (up to 400 kHz) + _Fast-mode Plus (up to 1 MHz) config SYS_I2C_ASPEED bool "Aspeed I2C Controller" @@ -333,50 +333,50 @@ if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) config SYS_I2C_MXC_I2C1 bool "NXP MXC I2C1" help - Add support for NXP MXC I2C Controller 1. - Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A + Add support for NXP MXC I2C Controller 1. + Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C2 bool "NXP MXC I2C2" help - Add support for NXP MXC I2C Controller 2. - Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A + Add support for NXP MXC I2C Controller 2. + Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C3 bool "NXP MXC I2C3" help - Add support for NXP MXC I2C Controller 3. - Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A + Add support for NXP MXC I2C Controller 3. + Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C4 bool "NXP MXC I2C4" help - Add support for NXP MXC I2C Controller 4. - Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A + Add support for NXP MXC I2C Controller 4. + Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C5 bool "NXP MXC I2C5" help - Add support for NXP MXC I2C Controller 5. - Required for SoCs which have I2C MXC controller 5 eg LX2160A + Add support for NXP MXC I2C Controller 5. + Required for SoCs which have I2C MXC controller 5 eg LX2160A config SYS_I2C_MXC_I2C6 bool "NXP MXC I2C6" help - Add support for NXP MXC I2C Controller 6. - Required for SoCs which have I2C MXC controller 6 eg LX2160A + Add support for NXP MXC I2C Controller 6. + Required for SoCs which have I2C MXC controller 6 eg LX2160A config SYS_I2C_MXC_I2C7 bool "NXP MXC I2C7" help - Add support for NXP MXC I2C Controller 7. - Required for SoCs which have I2C MXC controller 7 eg LX2160A + Add support for NXP MXC I2C Controller 7. + Required for SoCs which have I2C MXC controller 7 eg LX2160A config SYS_I2C_MXC_I2C8 bool "NXP MXC I2C8" help - Add support for NXP MXC I2C Controller 8. - Required for SoCs which have I2C MXC controller 8 eg LX2160A + Add support for NXP MXC I2C Controller 8. + Required for SoCs which have I2C MXC controller 8 eg LX2160A endif if SYS_I2C_MXC_I2C1 @@ -385,13 +385,13 @@ config SYS_MXC_I2C1_SPEED default 40000000 if TARGET_LS2080A_EMU default 100000 help - MXC I2C Channel 1 speed + MXC I2C Channel 1 speed config SYS_MXC_I2C1_SLAVE hex "I2C1 Slave" default 0x0 help - MXC I2C1 Slave + MXC I2C1 Slave endif if SYS_I2C_MXC_I2C2 @@ -400,13 +400,13 @@ config SYS_MXC_I2C2_SPEED default 40000000 if TARGET_LS2080A_EMU default 100000 help - MXC I2C Channel 2 speed + MXC I2C Channel 2 speed config SYS_MXC_I2C2_SLAVE hex "I2C2 Slave" default 0x0 help - MXC I2C2 Slave + MXC I2C2 Slave endif if SYS_I2C_MXC_I2C3 @@ -414,13 +414,13 @@ config SYS_MXC_I2C3_SPEED int "I2C Channel 3 speed" default 100000 help - MXC I2C Channel 3 speed + MXC I2C Channel 3 speed config SYS_MXC_I2C3_SLAVE hex "I2C3 Slave" default 0x0 help - MXC I2C3 Slave + MXC I2C3 Slave endif if SYS_I2C_MXC_I2C4 @@ -428,13 +428,13 @@ config SYS_MXC_I2C4_SPEED int "I2C Channel 4 speed" default 100000 help - MXC I2C Channel 4 speed + MXC I2C Channel 4 speed config SYS_MXC_I2C4_SLAVE hex "I2C4 Slave" default 0x0 help - MXC I2C4 Slave + MXC I2C4 Slave endif if SYS_I2C_MXC_I2C5 @@ -442,13 +442,13 @@ config SYS_MXC_I2C5_SPEED int "I2C Channel 5 speed" default 100000 help - MXC I2C Channel 5 speed + MXC I2C Channel 5 speed config SYS_MXC_I2C5_SLAVE hex "I2C5 Slave" default 0x0 help - MXC I2C5 Slave + MXC I2C5 Slave endif if SYS_I2C_MXC_I2C6 @@ -456,13 +456,13 @@ config SYS_MXC_I2C6_SPEED int "I2C Channel 6 speed" default 100000 help - MXC I2C Channel 6 speed + MXC I2C Channel 6 speed config SYS_MXC_I2C6_SLAVE hex "I2C6 Slave" default 0x0 help - MXC I2C6 Slave + MXC I2C6 Slave endif if SYS_I2C_MXC_I2C7 @@ -470,13 +470,13 @@ config SYS_MXC_I2C7_SPEED int "I2C Channel 7 speed" default 100000 help - MXC I2C Channel 7 speed + MXC I2C Channel 7 speed config SYS_MXC_I2C7_SLAVE hex "I2C7 Slave" default 0x0 help - MXC I2C7 Slave + MXC I2C7 Slave endif if SYS_I2C_MXC_I2C8 @@ -484,13 +484,13 @@ config SYS_MXC_I2C8_SPEED int "I2C Channel 8 speed" default 100000 help - MXC I2C Channel 8 speed + MXC I2C Channel 8 speed config SYS_MXC_I2C8_SLAVE hex "I2C8 Slave" default 0x0 help - MXC I2C8 Slave + MXC I2C8 Slave endif config SYS_I2C_NEXELL @@ -668,19 +668,19 @@ config SYS_I2C_STM32F7 help Enable this option to add support for STM32 I2C controller introduced with STM32F7/H7 SoCs. This I2C controller supports : - _ Slave and master modes - _ Multimaster capability - _ Standard-mode (up to 100 kHz) - _ Fast-mode (up to 400 kHz) - _ Fast-mode Plus (up to 1 MHz) - _ 7-bit and 10-bit addressing mode - _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) - _ All 7-bit addresses acknowledge mode - _ General call - _ Programmable setup and hold times - _ Easy to use event management - _ Optional clock stretching - _ Software reset + _ Slave and master modes + _ Multimaster capability + _ Standard-mode (up to 100 kHz) + _ Fast-mode (up to 400 kHz) + _ Fast-mode Plus (up to 1 MHz) + _ 7-bit and 10-bit addressing mode + _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) + _ All 7-bit addresses acknowledge mode + _ General call + _ Programmable setup and hold times + _ Easy to use event management + _ Optional clock stretching + _ Software reset config SYS_I2C_SUN6I_P2WI bool "Allwinner sun6i P2WI controller" @@ -792,10 +792,10 @@ config SYS_I2C_XILINX_XIIC Support for Xilinx AXI I2C controller. config SYS_I2C_IHS - bool "gdsys IHS I2C driver" - depends on DM_I2C - help - Support for gdsys IHS I2C driver on FPGA bus. + bool "gdsys IHS I2C driver" + depends on DM_I2C + help + Support for gdsys IHS I2C driver on FPGA bus. source "drivers/i2c/muxes/Kconfig" diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index 3b1220b2105..9f642e4451f 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -49,7 +49,7 @@ config I2C_MUX_PCA954x MAX7356, MAX7357, MAX7358, MAX7367, MAX7368 and MAX7369 config I2C_MUX_GPIO - tristate "GPIO-based I2C multiplexer" + tristate "GPIO-based I2C multiplexer" depends on I2C_MUX && DM_GPIO select DEVRES help -- cgit v1.3.1 From 11b7a94757954822d58316024f02a367bfdda99a Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Wed, 10 Jun 2026 16:39:20 +0200 Subject: Kconfig: mtd: restyle Restyle all Kconfigs for "mtd": Menu entries : no space left Menu attributes: 1 TAB Help text : 1 TAB + 2 spaces Replace '---help---' by 'help' Signed-off-by: Johan Jonker [trini: Add missing indentation on a few more multi-paragraph help texts] Signed-off-by: Tom Rini --- drivers/mtd/Kconfig | 20 +++++++-------- drivers/mtd/nand/raw/Kconfig | 34 +++++++++++++------------- drivers/mtd/spi/Kconfig | 58 ++++++++++++++++++++++---------------------- drivers/mtd/ubi/Kconfig | 4 +-- 4 files changed, 58 insertions(+), 58 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 21b8b21f6b2..38d6dd142dd 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -205,16 +205,16 @@ config HBMC_AM654 bool "HyperBus controller driver for AM65x SoC" depends on MULTIPLEXER && (MUX_MMIO || SPL_MUX_MMIO) help - This is the driver for HyperBus controller on TI's AM65x and - other SoCs + This is the driver for HyperBus controller on TI's AM65x and + other SoCs config STM32_FLASH bool "STM32 MCU Flash driver" depends on ARCH_STM32 select USE_SYS_MAX_FLASH_BANKS help - This is the driver of embedded flash for some STMicroelectronics - STM32 MCU. + This is the driver of embedded flash for some STMicroelectronics + STM32 MCU. config SYS_MAX_FLASH_SECT int "Maximum number of sectors on a flash chip" @@ -236,17 +236,17 @@ config SYS_MAX_FLASH_BANKS depends on USE_SYS_MAX_FLASH_BANKS default 1 help - Max number of Flash memory banks using by the MTD framework, in the - flash CFI driver and in some other driver to define the flash_info - struct declaration. + Max number of Flash memory banks using by the MTD framework, in the + flash CFI driver and in some other driver to define the flash_info + struct declaration. config SYS_MAX_FLASH_BANKS_DETECT bool "Detection of flash banks number in CFI driver" depends on CFI_FLASH && FLASH_CFI_DRIVER help - This enables detection of number of flash banks in CFI driver, - to reduce the effective number of flash bank, between 0 and - CONFIG_SYS_MAX_FLASH_BANKS + This enables detection of number of flash banks in CFI driver, + to reduce the effective number of flash bank, between 0 and + CONFIG_SYS_MAX_FLASH_BANKS source "drivers/mtd/nand/Kconfig" diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 2999e6b1710..b5dfad7380f 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -310,47 +310,47 @@ choice prompt "ECC scheme" default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW help - On OMAP platforms, this CONFIG specifies NAND ECC scheme. - It can take following values: - OMAP_ECC_HAM1_CODE_SW + On OMAP platforms, this CONFIG specifies NAND ECC scheme. + It can take following values: + OMAP_ECC_HAM1_CODE_SW 1-bit Hamming code using software lib. (for legacy devices only) - OMAP_ECC_HAM1_CODE_HW + OMAP_ECC_HAM1_CODE_HW 1-bit Hamming code using GPMC hardware. (for legacy devices only) - OMAP_ECC_BCH4_CODE_HW_DETECTION_SW + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW 4-bit BCH code (unsupported) - OMAP_ECC_BCH4_CODE_HW + OMAP_ECC_BCH4_CODE_HW 4-bit BCH code (unsupported) - OMAP_ECC_BCH8_CODE_HW_DETECTION_SW + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 8-bit BCH code with - ecc calculation using GPMC hardware engine, - error detection using software library. - requires CONFIG_BCH to enable software BCH library (For legacy device which do not have ELM h/w engine) - OMAP_ECC_BCH8_CODE_HW + OMAP_ECC_BCH8_CODE_HW 8-bit BCH code with - ecc calculation using GPMC hardware engine, - error detection using ELM hardware engine. - OMAP_ECC_BCH16_CODE_HW + OMAP_ECC_BCH16_CODE_HW 16-bit BCH code with - ecc calculation using GPMC hardware engine, - error detection using ELM hardware engine. - How to select ECC scheme on OMAP and AMxx platforms ? - ----------------------------------------------------- - Though higher ECC schemes have more capability to detect and correct - bit-flips, but still selection of ECC scheme is dependent on following - - hardware engines present in SoC. + How to select ECC scheme on OMAP and AMxx platforms ? + ----------------------------------------------------- + Though higher ECC schemes have more capability to detect and correct + bit-flips, but still selection of ECC scheme is dependent on following + - hardware engines present in SoC. Some legacy OMAP SoC do not have ELM h/w engine thus such SoC cannot support BCHx_HW ECC schemes. - - size of OOB/Spare region + - size of OOB/Spare region With higher ECC schemes, more OOB/Spare area is required to store ECC. So choice of ECC scheme is limited by NAND oobsize. - In general following expression can help: + In general following expression can help: NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES - where + where NAND_OOBSIZE = number of bytes available in OOB/spare area per NAND page. NAND_PAGESIZE = bytes in main-area of NAND page. diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index de78a6cb707..4ff58380b59 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -94,39 +94,39 @@ config SPI_FLASH_SFDP_SUPPORT bool "SFDP table parsing support for SPI NOR flashes" depends on !SPI_FLASH_BAR help - Enable support for parsing and auto discovery of parameters for - SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) - tables as per JESD216 standard. + Enable support for parsing and auto discovery of parameters for + SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) + tables as per JESD216 standard. config SPI_FLASH_SMART_HWCAPS bool "Smart hardware capability detection based on SPI MEM supports_op() hook" default y help - Enable support for smart hardware capability detection based on SPI - MEM supports_op() hook that lets controllers express whether they - can support a type of operation in a much more refined way compared - to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc. + Enable support for smart hardware capability detection based on SPI + MEM supports_op() hook that lets controllers express whether they + can support a type of operation in a much more refined way compared + to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc. config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT bool "Command extension type is INVERT for Software Reset on boot" help - Because of SFDP information can not be get before boot. - So define command extension type is INVERT when Software Reset on boot only. + Because of SFDP information can not be get before boot. + So define command extension type is INVERT when Software Reset on boot only. config SPI_FLASH_SOFT_RESET bool "Software Reset support for SPI NOR flashes" help - Enable support for xSPI Software Reset. It will be used to switch from - Octal DTR mode to legacy mode on shutdown and boot (if enabled). + Enable support for xSPI Software Reset. It will be used to switch from + Octal DTR mode to legacy mode on shutdown and boot (if enabled). config SPI_FLASH_SOFT_RESET_ON_BOOT bool "Perform a Software Reset on boot on flashes that boot in stateful mode" depends on SPI_FLASH_SOFT_RESET help - Perform a Software Reset on boot to allow detecting flashes that are - handed to us in Octal DTR mode. Do not enable this config on flashes - that are not supposed to be handed to U-Boot in Octal DTR mode, even - if they _do_ support the Soft Reset sequence. + Perform a Software Reset on boot to allow detecting flashes that are + handed to us in Octal DTR mode. Do not enable this config on flashes + that are not supposed to be handed to U-Boot in Octal DTR mode, even + if they _do_ support the Soft Reset sequence. config SPI_FLASH_BAR bool "SPI flash Bank/Extended address register support" @@ -139,18 +139,18 @@ config SPI_FLASH_LOCK bool "Enable the Locking feature" default y help - Enable the SPI flash lock support. By default this is set to y. - If you intend not to use the lock support you should say n here. + Enable the SPI flash lock support. By default this is set to y. + If you intend not to use the lock support you should say n here. config SPI_FLASH_UNLOCK_ALL bool "Unlock the entire SPI flash on u-boot startup" default y help - Some flashes tend to power up with the software write protection - bits set. If this option is set, the whole flash will be unlocked. + Some flashes tend to power up with the software write protection + bits set. If this option is set, the whole flash will be unlocked. - For legacy reasons, this option default to y. But if you intend to - actually use the software protection bits you should say n here. + For legacy reasons, this option default to y. But if you intend to + actually use the software protection bits you should say n here. config SPI_FLASH_ATMEL bool "Atmel SPI flash support" @@ -201,9 +201,9 @@ config SPI_FLASH_S28HX_T bool "Cypress SEMPER Octal (S28) chip support" depends on SPI_FLASH_SPANSION help - Add support for the Cypress S28HL-T and S28HS-T chip. This is a separate - config because the fixup hooks for this flash add extra size overhead. - Boards that don't use the flash can disable this to save space. + Add support for the Cypress S28HL-T and S28HS-T chip. This is a separate + config because the fixup hooks for this flash add extra size overhead. + Boards that don't use the flash can disable this to save space. config SPI_FLASH_STMICRO bool "STMicro SPI flash support" @@ -214,9 +214,9 @@ config SPI_FLASH_MT35XU bool "Micron MT35XU chip support" depends on SPI_FLASH_STMICRO help - Add support for the Micron MT35XU chip. This is a separate config - because the fixup hooks for this flash add extra size overhead. Boards - that don't use the flash can disable this to save space. + Add support for the Micron MT35XU chip. This is a separate config + because the fixup hooks for this flash add extra size overhead. Boards + that don't use the flash can disable this to save space. config SPI_FLASH_SST bool "SST SPI flash support" @@ -282,7 +282,7 @@ config SPI_FLASH_MTD bool "SPI Flash MTD support" depends on SPI_FLASH && MTD help - Enable the MTD support for spi flash layer, this adapter is for + Enable the MTD support for spi flash layer, this adapter is for translating mtd_read/mtd_write commands into spi_flash_read/write commands. It is not intended to use it within sf_cmd or the SPI flash subsystem. Such an adapter is needed for subsystems like @@ -294,7 +294,7 @@ config SPL_SPI_FLASH_MTD bool "SPI flash MTD support for SPL" depends on SPI_FLASH && SPL help - Enable the MTD support for the SPI flash layer in SPL. + Enable the MTD support for the SPI flash layer in SPL. If unsure, say N diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index ba77c034736..e523a4c4707 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -82,8 +82,8 @@ config MTD_UBI_BEB_LIMIT config MTD_UBI_FASTMAP bool "UBI Fastmap (Experimental feature)" help - Important: this feature is experimental so far and the on-flash - format for fastmap may change in the next kernel versions + Important: this feature is experimental so far and the on-flash + format for fastmap may change in the next kernel versions Fastmap is a mechanism which allows attaching an UBI device in nearly constant time. Instead of scanning the whole MTD device it -- cgit v1.3.1 From 2b92ad862243f8052b66ac8b8b5e4cc2535cb6fc Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Wed, 10 Jun 2026 16:39:39 +0200 Subject: Kconfig: net: restyle Restyle all Kconfigs for "net": Menu entries : no space left Menu attributes: 1 TAB Help text : 1 TAB + 2 spaces Replace '---help---' by 'help' Signed-off-by: Johan Jonker --- drivers/net/Kconfig | 48 ++++++++++++++++++++++++------------------------ drivers/net/phy/Kconfig | 18 +++++++++--------- drivers/net/ti/Kconfig | 4 ++-- 3 files changed, 35 insertions(+), 35 deletions(-) (limited to 'drivers') diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 5172b2bae8e..4399c6c7a99 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -184,10 +184,10 @@ config CALXEDA_XGMAC config DWC_ETH_XGMAC bool select PHYLIB - help - This driver supports the Synopsys Designware Ethernet XGMAC (10G - Ethernet MAC) IP block. The IP supports many options for bus type, - clocking/reset structure, and feature list. + help + This driver supports the Synopsys Designware Ethernet XGMAC (10G + Ethernet MAC) IP block. The IP supports many options for bus type, + clocking/reset structure, and feature list. config DWC_ETH_XGMAC_SOCFPGA bool "Synopsys DWC Ethernet XGMAC device support for SOCFPGA" @@ -229,8 +229,8 @@ config DWC_ETH_QOS_ADI bool "Synopsys DWC Ethernet QOS device support for ADI SC59x-64 parts" depends on DWC_ETH_QOS && ARCH_SC5XX help - The Synopsis Designware Ethernet QoS IP block with the specific - configuration used in the ADI ADSP-SC59X 64 bit SoCs + The Synopsis Designware Ethernet QoS IP block with the specific + configuration used in the ADI ADSP-SC59X 64 bit SoCs config DWC_ETH_QOS_IMX bool "Synopsys DWC Ethernet QOS device support for IMX" @@ -467,9 +467,9 @@ config FSL_FM_10GEC_REGULAR_NOTATION help On SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and MAC as below: - 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 + 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 While on SoCs T1024, etc, the notation between 10GEC and MAC as below: - 10GEC1->MAC1, 10GEC2->MAC2 + 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. @@ -536,7 +536,7 @@ config KSZ9477 config LITEETH bool "LiteX LiteEth Ethernet MAC" help - Driver for the LiteEth Ethernet MAC from LiteX. + Driver for the LiteEth Ethernet MAC from LiteX. config MV88E6XXX bool "Marvell MV88E6xxx Ethernet switch DSA driver" @@ -708,12 +708,12 @@ config SJA1105 family. These are 5-port devices and are managed over an SPI interface. Probing is handled based on OF bindings. The driver supports the following revisions: - - SJA1105E (Gen. 1, No TT-Ethernet) - - SJA1105T (Gen. 1, TT-Ethernet) - - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet) - - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet) - - SJA1105R (Gen. 2, SGMII, No TT-Ethernet) - - SJA1105S (Gen. 2, SGMII, TT-Ethernet) + - SJA1105E (Gen. 1, No TT-Ethernet) + - SJA1105T (Gen. 1, TT-Ethernet) + - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet) + - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet) + - SJA1105R (Gen. 2, SGMII, No TT-Ethernet) + - SJA1105S (Gen. 2, SGMII, TT-Ethernet) config SMC911X bool "SMSC LAN911x and LAN921x controller driver" @@ -747,11 +747,11 @@ config SUN4I_EMAC This driver supports the Allwinner based SUN4I Ethernet MAC. config SUN8I_EMAC - bool "Allwinner Sun8i Ethernet MAC support" - select PHYLIB + bool "Allwinner Sun8i Ethernet MAC support" + select PHYLIB select PHY_GIGE - help - This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC. + help + This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC. It can be found in H3/A64/A83T based SoCs and compatible with both External and Internal PHYs. @@ -912,7 +912,7 @@ config FEC1_PHY help Define to the hardcoded PHY address which corresponds to the given FEC; i. e. - #define CONFIG_FEC1_PHY 4 + #define CONFIG_FEC1_PHY 4 means that the PHY with address 4 is connected to FEC1 When set to -1, means to probe for first available. @@ -936,7 +936,7 @@ config FEC2_PHY help Define to the hardcoded PHY address which corresponds to the given FEC; i. e. - #define CONFIG_FEC1_PHY 4 + #define CONFIG_FEC1_PHY 4 means that the PHY with address 4 is connected to FEC1 When set to -1, means to probe for first available. @@ -1041,7 +1041,7 @@ config MDIO_GPIO_BITBANG bool "GPIO bitbanging MDIO driver" depends on DM_MDIO && DM_GPIO help - Driver for bitbanging MDIO + Driver for bitbanging MDIO config MDIO_MUX_I2CREG bool "MDIO MUX accessed as a register over I2C" @@ -1087,8 +1087,8 @@ config MDIO_MSCC_MIIM depends on DM_MDIO select REGMAP help - This driver supports MDIO interface found in Microsemi and Microchip - network switches. + This driver supports MDIO interface found in Microsemi and Microchip + network switches. config MDIO_MUX_MMIOREG bool "MDIO MUX accessed as a MMIO register access" diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 0025c895f12..3f7953d693c 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -81,7 +81,7 @@ config PHYLIB_10G config PHY_ADIN bool "Analog Devices Industrial Ethernet PHYs" help - Add support for configuring RGMII on Analog Devices ADIN PHYs. + Add support for configuring RGMII on Analog Devices ADIN PHYs. menuconfig PHY_AQUANTIA bool "Aquantia Ethernet PHYs support" @@ -126,9 +126,9 @@ config SYS_CORTINA_NO_FW_UPLOAD bool "Cortina firmware loading support" depends on PHY_CORTINA help - Cortina phy has provision to store phy firmware in attached dedicated - EEPROM. And boards designed with such EEPROM does not require firmware - upload. + Cortina phy has provision to store phy firmware in attached dedicated + EEPROM. And boards designed with such EEPROM does not require firmware + upload. choice prompt "Location of the Cortina firmware" @@ -167,7 +167,7 @@ config PHY_CORTINA_ACCESS default y depends on CORTINA_NI_ENET help - Cortina Access Ethernet PHYs init process + Cortina Access Ethernet PHYs init process config PHY_DAVICOM bool "Davicom Ethernet PHYs support" @@ -317,13 +317,13 @@ config PHY_TERANETICS config PHY_TI bool "Texas Instruments Ethernet PHYs support" - ---help--- + help Adds PHY registration support for TI PHYs. config PHY_TI_DP83867 select PHY_TI bool "Texas Instruments Ethernet DP83867 PHY support" - ---help--- + help Adds support for the TI DP83867 1Gbit PHY. config SPL_PHY_TI_DP83867 @@ -333,13 +333,13 @@ config SPL_PHY_TI_DP83867 config PHY_TI_DP83869 select PHY_TI bool "Texas Instruments Ethernet DP83869 PHY support" - ---help--- + help Adds support for the TI DP83869 1Gbit PHY. config PHY_TI_GENERIC select PHY_TI bool "Texas Instruments Generic Ethernet PHYs support" - ---help--- + help Adds support for Generic TI PHYs that don't need special handling but the PHY name is associated with a PHY ID. diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index 93c3a0c35f2..2d72af8aade 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -14,7 +14,7 @@ config DRIVER_TI_EMAC bool "TI Davinci EMAC" depends on ARCH_DAVINCI || ARCH_OMAP2PLUS help - Support for davinci emac + Support for davinci emac config DRIVER_TI_EMAC_USE_RMII depends on DRIVER_TI_EMAC @@ -26,7 +26,7 @@ config DRIVER_TI_KEYSTONE_NET bool "TI Keystone 2 Ethernet" depends on ARCH_KEYSTONE help - This driver supports the TI Keystone 2 Ethernet subsystem + This driver supports the TI Keystone 2 Ethernet subsystem choice prompt "TI Keystone 2 Ethernet NETCP IP revision" -- cgit v1.3.1 From 591086d49d170aa32b851011f0c456082e5c2d48 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Wed, 10 Jun 2026 16:39:57 +0200 Subject: Kconfig: pinctrl: restyle Restyle all Kconfigs for "pinctrl": Menu entries : no space left Menu attributes: 1 TAB Help text : 1 TAB + 2 spaces Replace '---help---' by 'help' Signed-off-by: Johan Jonker --- drivers/pinctrl/broadcom/Kconfig | 8 ++++---- drivers/pinctrl/mediatek/Kconfig | 2 +- drivers/pinctrl/mscc/Kconfig | 20 ++++++++++---------- drivers/pinctrl/mvebu/Kconfig | 12 ++++++------ drivers/pinctrl/qcom/Kconfig | 10 +++++----- 5 files changed, 26 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/broadcom/Kconfig b/drivers/pinctrl/broadcom/Kconfig index b01b725583a..d7cf3855928 100644 --- a/drivers/pinctrl/broadcom/Kconfig +++ b/drivers/pinctrl/broadcom/Kconfig @@ -3,13 +3,13 @@ config PINCTRL_BCM283X default y bool "Broadcom 283x family pin control driver" help - Support pin multiplexing and pin configuration control on - Broadcom's 283x family of SoCs. + Support pin multiplexing and pin configuration control on + Broadcom's 283x family of SoCs. config PINCTRL_BCM6838 depends on ARCH_BMIPS && PINCTRL_FULL && OF_CONTROL default y bool "Broadcom 6838 family pin control driver" help - Support pin multiplexing and pin configuration control on - Broadcom's 6838 family of SoCs. + Support pin multiplexing and pin configuration control on + Broadcom's 6838 family of SoCs. diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index cf72a7df62c..5a90d74a9e1 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -59,7 +59,7 @@ config PINCTRL_MT8516 select PINCTRL_MTK config PINCTRL_MT8518 - bool "MT8518 SoC pinctrl driver" + bool "MT8518 SoC pinctrl driver" select PINCTRL_MTK endif diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig index 567c93f404c..285787c4467 100644 --- a/drivers/pinctrl/mscc/Kconfig +++ b/drivers/pinctrl/mscc/Kconfig @@ -10,8 +10,8 @@ config PINCTRL_MSCC_OCELOT default y bool "Microsemi ocelot family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi ocelot SoCs. + Support pin multiplexing and pin configuration control on + Microsemi ocelot SoCs. config PINCTRL_MSCC_LUTON depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL @@ -19,8 +19,8 @@ config PINCTRL_MSCC_LUTON default y bool "Microsemi luton family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi luton SoCs. + Support pin multiplexing and pin configuration control on + Microsemi luton SoCs. config PINCTRL_MSCC_JR2 depends on SOC_JR2 && PINCTRL_FULL && OF_CONTROL @@ -28,8 +28,8 @@ config PINCTRL_MSCC_JR2 default y bool "Microsemi jr2 family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi jr2 SoCs. + Support pin multiplexing and pin configuration control on + Microsemi jr2 SoCs. config PINCTRL_MSCC_SERVALT depends on SOC_SERVALT && PINCTRL_FULL && OF_CONTROL @@ -37,8 +37,8 @@ config PINCTRL_MSCC_SERVALT default y bool "Microsemi servalt family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi servalt SoCs. + Support pin multiplexing and pin configuration control on + Microsemi servalt SoCs. config PINCTRL_MSCC_SERVAL depends on SOC_SERVAL && PINCTRL_FULL && OF_CONTROL @@ -46,6 +46,6 @@ config PINCTRL_MSCC_SERVAL default y bool "Microsemi serval family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi serval SoCs. + Support pin multiplexing and pin configuration control on + Microsemi serval SoCs. diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig index 10ba440f246..72b97a7935d 100644 --- a/drivers/pinctrl/mvebu/Kconfig +++ b/drivers/pinctrl/mvebu/Kconfig @@ -4,22 +4,22 @@ config PINCTRL_ARMADA_38X depends on ARMADA_38X && PINCTRL_FULL bool "Armada 38x pin control driver" help - Support pin multiplexing and pin configuration control on - Marvell's Armada-38x SoC. + Support pin multiplexing and pin configuration control on + Marvell's Armada-38x SoC. config PINCTRL_ARMADA_37XX depends on ARMADA_3700 && PINCTRL_FULL select DEVRES bool "Armada 37xx pin control driver" help - Support pin multiplexing and pin configuration control on - Marvell's Armada-37xx SoC. + Support pin multiplexing and pin configuration control on + Marvell's Armada-37xx SoC. config PINCTRL_ARMADA_8K depends on (ARMADA_8K || ALLEYCAT_5) && PINCTRL_FULL bool "Armada 7k/8k pin control driver" help - Support pin multiplexing and pin configuration control on - Marvell's Armada-8K SoC. + Support pin multiplexing and pin configuration control on + Marvell's Armada-8K SoC. endif diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 43100d5d981..0bea461fcc3 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -79,12 +79,12 @@ config PINCTRL_QCOM_QCS404 as well as the associated GPIO driver. config PINCTRL_QCOM_QCS615 - bool "Qualcomm QCS615 Pinctrl" + bool "Qualcomm QCS615 Pinctrl" default y if PINCTRL_QCOM_GENERIC - select PINCTRL_QCOM - help - Say Y here to enable support for pinctrl on the Snapdragon QCS615 SoC, - as well as the associated GPIO driver. + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon QCS615 SoC, + as well as the associated GPIO driver. config PINCTRL_QCOM_SA8775P bool "Qualcomm SA8775P Pinctrl" -- cgit v1.3.1 From b2c5dd6048caeac7a87175b0d7200565a9ae760a Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Wed, 10 Jun 2026 16:40:13 +0200 Subject: Kconfig: power: restyle Restyle all Kconfigs for "power": Menu entries : no space left Menu attributes: 1 TAB Help text : 1 TAB + 2 spaces Replace '---help---' by 'help' Signed-off-by: Johan Jonker [trini: Add missing indentation on a few more multi-paragraph help texts] Signed-off-by: Tom Rini --- drivers/power/Kconfig | 364 ++++++++++++++++----------------- drivers/power/domain/Kconfig | 8 +- drivers/power/pmic/Kconfig | 384 +++++++++++++++++------------------ drivers/power/regulator/Kconfig | 438 ++++++++++++++++++++-------------------- 4 files changed, 597 insertions(+), 597 deletions(-) (limited to 'drivers') diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 1b06d8a66c7..66c389d073b 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -1,7 +1,7 @@ menuconfig POWER - bool "Power" - default y - help + bool "Power" + default y + help Enable support for power control in U-Boot. This includes support for PMICs (Power-management Integrated Circuits) and some of the features provided by PMICs. In particular, voltage regulators can @@ -63,98 +63,98 @@ choice config SUNXI_NO_PMIC bool "board without a pmic" - ---help--- - Select this for boards which do not use a PMIC. + help + Select this for boards which do not use a PMIC. config AXP152_POWER bool "axp152 pmic support" depends on MACH_SUN5I select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the axp152 pmic found on most - A10s boards. + help + Select this to enable support for the axp152 pmic found on most + A10s boards. config AXP209_POWER bool "axp209 pmic support" depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3S select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the axp209 pmic found on most - A10, A13 and A20 boards. + help + Select this to enable support for the axp209 pmic found on most + A10, A13 and A20 boards. config AXP221_POWER bool "axp221 / axp223 pmic support" depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the axp221/axp223 pmic found on most - A23 and A31 boards. + help + Select this to enable support for the axp221/axp223 pmic found on most + A23 and A31 boards. config AXP305_POWER bool "axp305 pmic support" depends on MACH_SUN50I_H616 select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the axp305 pmic found on most - H616 boards. + help + Select this to enable support for the axp305 pmic found on most + H616 boards. config AXP313_POWER bool "axp313 pmic support" depends on MACH_SUN50I_H616 select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the AXP313 PMIC found on some - H616 boards. + help + Select this to enable support for the AXP313 PMIC found on some + H616 boards. config AXP717_POWER bool "axp717 pmic support" select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the AXP717 PMIC found on some boards. + help + Select this to enable support for the AXP717 PMIC found on some boards. config AXP803_POWER bool "AXP803 PMIC support" select AXP_PMIC_BUS - ---help--- - Select this to enable support for the AXP803 PMIC found on some boards. + help + Select this to enable support for the AXP803 PMIC found on some boards. config AXP809_POWER bool "axp809 pmic support" depends on MACH_SUN9I select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Say y here to enable support for the axp809 pmic found on A80 boards. + help + Say y here to enable support for the axp809 pmic found on A80 boards. config AXP818_POWER bool "axp818 pmic support" depends on MACH_SUN8I_A83T select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Say y here to enable support for the axp818 pmic found on - A83T dev board. + help + Say y here to enable support for the axp818 pmic found on + A83T dev board. config AXP318W_POWER bool "axp318w pmic support" select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the AXP318W PMIC found on some - A733 boards. + help + Select this to enable support for the AXP318W PMIC found on some + A733 boards. config SY8106A_POWER bool "SY8106A pmic support" depends on MACH_SUNXI_H3_H5 - ---help--- - Select this to enable support for the SY8106A pmic found on some - H3 boards. + help + Select this to enable support for the SY8106A pmic found on some + H3 boards. endchoice @@ -166,22 +166,22 @@ config AXP_I2C_ADDRESS default 0x36 if AXP318W_POWER default 0x30 if AXP152_POWER default 0x34 - ---help--- - I2C address of the AXP PMIC, used for the SPL only. + help + I2C address of the AXP PMIC, used for the SPL only. config AXP_DCDC1_VOLT int "axp pmic dcdc1 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP803_POWER default 3300 if AXP818_POWER || MACH_SUN8I_R40 || AXP803_POWER default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I - ---help--- - Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to - disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for - generic 3.3V IO voltage for external devices like the lcd-panal and - sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to - save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T - dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally - powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG. + help + Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to + disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for + generic 3.3V IO voltage for external devices like the lcd-panal and + sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to + save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T + dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally + powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG. config AXP_DCDC2_VOLT int "axp pmic dcdc2 voltage" @@ -194,16 +194,16 @@ config AXP_DCDC2_VOLT default 1200 if MACH_SUN6I default 1100 if MACH_SUN8I default 0 if MACH_SUN9I - ---help--- - Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to - disable dcdc2. - On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V. - On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V. - On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V. - On A80 boards dcdc2 powers the GPU and can be left off. - On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V. - On R40 boards dcdc2 is VDD-CPU and should be 1.1V - On boards using the AXP313 or AXP717 it's often VDD-CPU. + help + Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to + disable dcdc2. + On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V. + On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V. + On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V. + On A80 boards dcdc2 powers the GPU and can be left off. + On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V. + On R40 boards dcdc2 is VDD-CPU and should be 1.1V + On boards using the AXP313 or AXP717 it's often VDD-CPU. config AXP_DCDC3_VOLT int "axp pmic dcdc3 voltage" @@ -214,18 +214,18 @@ config AXP_DCDC3_VOLT default 1100 if AXP313_POWER default 1100 if MACH_SUN8I_R40 default 1200 if MACH_SUN6I || MACH_SUN8I - ---help--- - Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to - disable dcdc3. - On A10(s) / A13 / A20 boards with an axp209 dcdc3 is VDD-INT-DLL and - should be 1.25V. - On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V. - On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V. - On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V. - On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. - On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V. - On boards using the AXP313 or AXP717 it's often VDD-DRAM and should - be 1.1V for LPDDR4. + help + Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to + disable dcdc3. + On A10(s) / A13 / A20 boards with an axp209 dcdc3 is VDD-INT-DLL and + should be 1.25V. + On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V. + On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V. + On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V. + On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. + On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V. + On boards using the AXP313 or AXP717 it's often VDD-DRAM and should + be 1.1V for LPDDR4. config AXP_DCDC4_VOLT int "axp pmic dcdc4 voltage" @@ -235,25 +235,25 @@ config AXP_DCDC4_VOLT default 0 if MACH_SUN8I default 900 if MACH_SUN9I default 1500 if AXP305_POWER - ---help--- - Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to - disable dcdc4. - On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V. - On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V. - On A23 / A33 boards dcdc4 is unused and should be disabled. - On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V. - On A83T boards dcdc4 is used for VDD-GPU. - On H616 boards dcdcd is used for VCC-DRAM. + help + Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to + disable dcdc4. + On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V. + On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V. + On A23 / A33 boards dcdc4 is unused and should be disabled. + On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V. + On A83T boards dcdc4 is used for VDD-GPU. + On H616 boards dcdcd is used for VCC-DRAM. config AXP_DCDC5_VOLT int "axp pmic dcdc5 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP803_POWER default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I - ---help--- - Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to - disable dcdc5. - On A23 / A31 / A33 / A80 / A83T / R40 boards dcdc5 is VCC-DRAM and - should be 1.5V, 1.35V if DDR3L is used. + help + Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to + disable dcdc5. + On A23 / A31 / A33 / A80 / A83T / R40 boards dcdc5 is VCC-DRAM and + should be 1.5V, 1.35V if DDR3L is used. config AXP_ALDO1_VOLT int "axp pmic (a)ldo1 voltage" @@ -261,14 +261,14 @@ config AXP_ALDO1_VOLT default 0 if MACH_SUN6I || MACH_SUN8I_R40 default 1800 if MACH_SUN8I_A83T default 3000 if MACH_SUN8I || MACH_SUN9I - ---help--- - Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to - disable aldo1. - On A31 boards aldo1 is often used to power the wifi module. - On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V. - On A80 boards aldo1 powers the USB hosts and should be 3.0V. - On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and - should be 1.8V. + help + Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to + disable aldo1. + On A31 boards aldo1 is often used to power the wifi module. + On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V. + On A80 boards aldo1 powers the USB hosts and should be 3.0V. + On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and + should be 1.8V. config AXP_ALDO2_VOLT int "axp pmic (a)ldo2 voltage" @@ -277,188 +277,188 @@ config AXP_ALDO2_VOLT default 0 if MACH_SUN6I || MACH_SUN9I default 1800 if MACH_SUN8I_A83T default 2500 if MACH_SUN8I - ---help--- - Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to - disable aldo2. - On A10(s) / A13 / A20 boards aldo2 is AVCC and should be 3.0V. - On A31 boards aldo2 is typically unused and should be disabled. - On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V. - On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V. - On A80 boards aldo2 powers PB pingroup and camera IO and can be left off. - On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC, - LPDDR2, and the codec. It should be 1.8V. + help + Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to + disable aldo2. + On A10(s) / A13 / A20 boards aldo2 is AVCC and should be 3.0V. + On A31 boards aldo2 is typically unused and should be disabled. + On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V. + On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V. + On A80 boards aldo2 powers PB pingroup and camera IO and can be left off. + On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC, + LPDDR2, and the codec. It should be 1.8V. config AXP_ALDO3_VOLT int "axp pmic (a)ldo3 voltage" depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 if AXP209_POWER || MACH_SUN9I default 3000 if MACH_SUN6I || MACH_SUN8I - ---help--- - Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to - disable aldo3. - On A10(s) / A13 / A20 boards aldo3 should be 2.8V. - On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should - be 3.0V. - On A80 boards aldo3 is normally not used. - On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be - 3.0V. + help + Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to + disable aldo3. + On A10(s) / A13 / A20 boards aldo3 should be 2.8V. + On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should + be 3.0V. + On A80 boards aldo3 is normally not used. + On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be + 3.0V. choice prompt "axp pmic (a)ldo3 voltage rate control" depends on AXP209_POWER default AXP_ALDO3_VOLT_SLOPE_NONE - ---help--- - The AXP can slowly ramp up voltage to reduce the inrush current when - changing voltages. - Note, this does not apply when enabling/disabling LDO3. See - "axp pmic (a)ldo3 inrush quirk" below to enable a slew rate to limit - inrush current on broken board designs. + help + The AXP can slowly ramp up voltage to reduce the inrush current when + changing voltages. + Note, this does not apply when enabling/disabling LDO3. See + "axp pmic (a)ldo3 inrush quirk" below to enable a slew rate to limit + inrush current on broken board designs. config AXP_ALDO3_VOLT_SLOPE_NONE bool "No voltage slope" - ---help--- - Tries to reach the next voltage setting near instantaneously. Measurements - indicate that this is about 0.0167 V/uS. + help + Tries to reach the next voltage setting near instantaneously. Measurements + indicate that this is about 0.0167 V/uS. config AXP_ALDO3_VOLT_SLOPE_16 bool "1.6 mV per uS" - ---help--- - Increases the voltage by 1.6 mV per uS until the final voltage has - been reached. Note that the scaling is in 25 mV steps and thus - the slew rate in reality is about 25 mV/31.250 uS. + help + Increases the voltage by 1.6 mV per uS until the final voltage has + been reached. Note that the scaling is in 25 mV steps and thus + the slew rate in reality is about 25 mV/31.250 uS. config AXP_ALDO3_VOLT_SLOPE_08 bool "0.8 mV per uS" - ---help--- - Increases the voltage by 0.8 mV per uS until the final voltage has - been reached. Note that the scaling is in 25 mV steps however and thus - the slew rate in reality is about 25 mV/15.625 uS. - This is the slowest supported rate. + help + Increases the voltage by 0.8 mV per uS until the final voltage has + been reached. Note that the scaling is in 25 mV steps however and thus + the slew rate in reality is about 25 mV/15.625 uS. + This is the slowest supported rate. endchoice config AXP_ALDO3_INRUSH_QUIRK bool "axp pmic (a)ldo3 inrush quirk" depends on AXP209_POWER - ---help--- - The reference design denotes a value of 4.7 uF for the output capacitor - of LDO3. Some boards have too high capacitance causing an inrush current - and resulting an AXP209 shutdown. + help + The reference design denotes a value of 4.7 uF for the output capacitor + of LDO3. Some boards have too high capacitance causing an inrush current + and resulting an AXP209 shutdown. config AXP_ALDO4_VOLT int "axp pmic (a)ldo4 voltage" depends on AXP209_POWER default 0 if AXP209_POWER - ---help--- - Set the voltage (mV) to program the axp pmic aldo4 at, set to 0 to - disable aldo4. - On A10(s) / A13 / A20 boards aldo4 should be 2.8V. + help + Set the voltage (mV) to program the axp pmic aldo4 at, set to 0 to + disable aldo4. + On A10(s) / A13 / A20 boards aldo4 should be 2.8V. config AXP_DLDO1_VOLT int "axp pmic dldo1 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to - disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used - to power the ethernet phy. On A23, A33 and A80 boards this is often - used to power the wifi. + help + Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to + disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used + to power the ethernet phy. On A23, A33 and A80 boards this is often + used to power the wifi. config AXP_DLDO2_VOLT int "axp pmic dldo2 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 3000 if MACH_SUN9I default 0 - ---help--- - Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to - disable dldo2. - On A80 boards dldo2 normally powers the PL pins and should be 3.0V. + help + Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to + disable dldo2. + On A80 boards dldo2 normally powers the PL pins and should be 3.0V. config AXP_DLDO3_VOLT int "axp pmic dldo3 voltage" depends on AXP221_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic dldo3 at, set to 0 to - disable dldo3. + help + Set the voltage (mV) to program the axp pmic dldo3 at, set to 0 to + disable dldo3. config AXP_DLDO4_VOLT int "axp pmic dldo4 voltage" depends on AXP221_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic dldo4 at, set to 0 to - disable dldo4. + help + Set the voltage (mV) to program the axp pmic dldo4 at, set to 0 to + disable dldo4. config AXP_ELDO1_VOLT int "axp pmic eldo1 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to - disable eldo1. + help + Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to + disable eldo1. config AXP_ELDO2_VOLT int "axp pmic eldo2 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to - disable eldo2. + help + Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to + disable eldo2. config AXP_ELDO3_VOLT int "axp pmic eldo3 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 3000 if MACH_SUN9I default 0 - ---help--- - Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to - disable eldo3. On some A31(s) tablets it might be used to supply - 1.2V for the SSD2828 chip (converter of parallel LCD interface - into MIPI DSI). - On A80 boards it powers the PM pingroup and should be 3.0V. + help + Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to + disable eldo3. On some A31(s) tablets it might be used to supply + 1.2V for the SSD2828 chip (converter of parallel LCD interface + into MIPI DSI). + On A80 boards it powers the PM pingroup and should be 3.0V. config AXP_FLDO1_VOLT int "axp pmic fldo1 voltage" depends on AXP818_POWER default 0 if MACH_SUN8I_A83T - ---help--- - Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to - disable fldo1. - On A83T / H8 boards fldo1 is VCC-HSIC and should be 1.2V if HSIC is - used. + help + Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to + disable fldo1. + On A83T / H8 boards fldo1 is VCC-HSIC and should be 1.2V if HSIC is + used. config AXP_FLDO2_VOLT int "axp pmic fldo2 voltage" depends on AXP818_POWER default 900 if MACH_SUN8I_A83T - ---help--- - Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to - disable fldo2. - On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V. + help + Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to + disable fldo2. + On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V. config AXP_FLDO3_VOLT int "axp pmic fldo3 voltage" depends on AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to - disable fldo3. + help + Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to + disable fldo3. config AXP_SW_ON bool "axp pmic sw on" depends on AXP809_POWER || AXP818_POWER - ---help--- - Enable to turn on axp pmic sw. + help + Enable to turn on axp pmic sw. config SY8106A_VOUT1_VOLT int "SY8106A pmic VOUT1 voltage" depends on SY8106A_POWER default 1200 - ---help--- - Set the voltage (mV) to program the SY8106A pmic VOUT1. This - is typically used to power the VDD-CPU and should be 1200mV. - Values can range from 680mV till 1950mV. + help + Set the voltage (mV) to program the SY8106A pmic VOUT1. This + is typically used to power the VDD-CPU and should be 1200mV. + Values can range from 680mV till 1950mV. config TPS6586X_POWER bool "Enable legacy driver for TI TPS6586x power management chip" @@ -467,9 +467,9 @@ config TWL4030_POWER depends on OMAP34XX bool "Enable driver for TI TWL4030 power management chip" imply CMD_POWEROFF - ---help--- - The TWL4030 in a combination audio CODEC/power management with - GPIO and it is commonly used with the OMAP3 family of processors + help + The TWL4030 in a combination audio CODEC/power management with + GPIO and it is commonly used with the OMAP3 family of processors config POWER_MT6323 bool "Poweroff driver for mediatek mt6323" diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 4112b777371..bb9c52155d2 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -35,10 +35,10 @@ config BCM6328_POWER_DOMAIN config IMX8_POWER_DOMAIN bool "Enable i.MX8 power domain driver" - depends on ARCH_IMX8 - help - Enable support for manipulating NXP i.MX8 on-SoC power domains via IPC - requests to the SCU. + depends on ARCH_IMX8 + help + Enable support for manipulating NXP i.MX8 on-SoC power domains via IPC + requests to the SCU. config IMX8M_POWER_DOMAIN bool "Enable i.MX8M power domain driver" diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 8504ae2b079..4bd9b4e1940 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -1,14 +1,14 @@ config DM_PMIC bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC)" depends on DM - ---help--- - This config enables the driver-model PMIC support. - UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. - For the multi-function PMIC devices, this can be used as parent I/O - device for each IC's interface. Then, each children uses its parent - for read/write. For detailed description, please refer to the files: - - 'drivers/power/pmic/pmic-uclass.c' - - 'include/power/pmic.h' + help + This config enables the driver-model PMIC support. + UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. + For the multi-function PMIC devices, this can be used as parent I/O + device for each IC's interface. Then, each children uses its parent + for read/write. For detailed description, please refer to the files: + - 'drivers/power/pmic/pmic-uclass.c' + - 'include/power/pmic.h' if DM_PMIC @@ -16,34 +16,34 @@ config SPL_DM_PMIC bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC) in SPL" depends on SPL_DM default y - ---help--- - This config enables the driver-model PMIC support in SPL. - UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. - For the multi-function PMIC devices, this can be used as parent I/O - device for each IC's interface. Then, each children uses its parent - for read/write. For detailed description, please refer to the files: - - 'drivers/power/pmic/pmic-uclass.c' - - 'include/power/pmic.h' + help + This config enables the driver-model PMIC support in SPL. + UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. + For the multi-function PMIC devices, this can be used as parent I/O + device for each IC's interface. Then, each children uses its parent + for read/write. For detailed description, please refer to the files: + - 'drivers/power/pmic/pmic-uclass.c' + - 'include/power/pmic.h' config PMIC_CHILDREN bool "Allow child devices for PMICs" default y - ---help--- - This allows PMICs to support child devices (such as regulators) in - SPL. This adds quite a bit of code so if you are not using this - feature you can turn it off. Most likely you should turn it on for - U-Boot proper. + help + This allows PMICs to support child devices (such as regulators) in + SPL. This adds quite a bit of code so if you are not using this + feature you can turn it off. Most likely you should turn it on for + U-Boot proper. config SPL_PMIC_CHILDREN bool "Allow child devices for PMICs in SPL" depends on SPL_DM_PMIC default y - ---help--- - This allows PMICs to support child devices (such as regulators) in - SPL. This adds quite a bit of code so if you are not using this - feature you can turn it off. In this case you may need a 'back door' - to call your regulator code (e.g. see rk8xx.c for direct functions - for use in SPL). + help + This allows PMICs to support child devices (such as regulators) in + SPL. This adds quite a bit of code so if you are not using this + feature you can turn it off. In this case you may need a 'back door' + to call your regulator code (e.g. see rk8xx.c for direct functions + for use in SPL). config PMIC_AB8500 bool "Enable driver for ST-Ericsson AB8500 PMIC via PRCMU" @@ -57,11 +57,11 @@ config PMIC_AB8500 config PMIC_ACT8846 bool "Enable support for the active-semi 8846 PMIC" depends on DM_I2C - ---help--- - This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout - regulators (LDOs). It also provides some GPIO, reset and battery - functions. It uses an I2C interface and is designed for use with - tablets and smartphones. + help + This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout + regulators (LDOs). It also provides some GPIO, reset and battery + functions. It uses an I2C interface and is designed for use with + tablets and smartphones. config PMIC_AXP bool "Enable Driver Model for X-Powers AXP PMICs" @@ -101,8 +101,8 @@ config PMIC_AS3722 required for a tablets or laptop. config DM_PMIC_BD71837 - bool "Enable Driver Model for PMIC BD71837" - help + bool "Enable Driver Model for PMIC BD71837" + help This config enables implementation of driver-model pmic uclass features for PMIC BD71837. The driver implements read/write operations. @@ -173,257 +173,257 @@ config SPL_DM_PMIC_PCA9450 config DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC PFUZE100. The driver implements read/write operations. + help + This config enables implementation of driver-model pmic uclass features + for PMIC PFUZE100. The driver implements read/write operations. config SPL_DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100 in SPL" depends on SPL_DM_PMIC - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC PFUZE100 in SPL. The driver implements read/write operations. + help + This config enables implementation of driver-model pmic uclass features + for PMIC PFUZE100 in SPL. The driver implements read/write operations. config DM_PMIC_MAX8907 bool "Enable Driver Model for PMIC MAX8907" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX8907. The driver implements read/write operations. - This is a Power Management IC with a decent set of peripherals from which - 3 DC-to-DC Step-Down (SD) Regulators, 20 Low-Dropout Linear (LDO) Regulators, - Real-Time Clock (RTC) and more with I2C Compatible Interface. + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX8907. The driver implements read/write operations. + This is a Power Management IC with a decent set of peripherals from which + 3 DC-to-DC Step-Down (SD) Regulators, 20 Low-Dropout Linear (LDO) Regulators, + Real-Time Clock (RTC) and more with I2C Compatible Interface. config DM_PMIC_MAX77663 bool "Enable Driver Model for PMIC MAX77663" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX77663. The driver implements read/write operations. - This is a Power Management IC with a decent set of peripherals from which - 4 DC-to-DC Step-Down (SD) Regulators, 9 Low-Dropout Linear (LDO) Regulators, - 8 GPIOs, Real-Time Clock (RTC) and more with I2C Compatible Interface. + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX77663. The driver implements read/write operations. + This is a Power Management IC with a decent set of peripherals from which + 4 DC-to-DC Step-Down (SD) Regulators, 9 Low-Dropout Linear (LDO) Regulators, + 8 GPIOs, Real-Time Clock (RTC) and more with I2C Compatible Interface. config DM_PMIC_MAX77686 bool "Enable Driver Model for PMIC MAX77686" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX77686. The driver implements read/write operations. + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX77686. The driver implements read/write operations. config DM_PMIC_MAX8998 bool "Enable Driver Model for PMIC MAX8998" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX8998. The driver implements read/write operations. + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX8998. The driver implements read/write operations. config DM_PMIC_MC34708 bool "Enable Driver Model for PMIC MC34708" help - This config enables implementation of driver-model pmic uclass features - for PMIC MC34708. The driver implements read/write operations. + This config enables implementation of driver-model pmic uclass features + for PMIC MC34708. The driver implements read/write operations. config PMIC_MAX8997 bool "Enable Driver Model for PMIC MAX8997" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX8997. The driver implements read/write operations. - This is a Power Management IC with RTC, Fuel Gauge, MUIC control on Chip. - - 21x LDOs - - 12x GPIOs - - Haptic motor driver - - RTC with two alarms - - Fuel Gauge and one backup battery charger - - MUIC - - Others + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX8997. The driver implements read/write operations. + This is a Power Management IC with RTC, Fuel Gauge, MUIC control on Chip. + - 21x LDOs + - 12x GPIOs + - Haptic motor driver + - RTC with two alarms + - Fuel Gauge and one backup battery charger + - MUIC + - Others config PMIC_QCOM bool "Enable Driver Model for Qualcomm generic PMIC" - ---help--- - The Qcom PMIC is connected to one (or several) processors - with SPMI bus. It has 2 slaves with several peripherals: - - 18x LDO - - 4x GPIO - - Power and Reset buttons - - Watchdog - - RTC - - Vibrator drivers - - Others - - Driver binding info: doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt + help + The Qcom PMIC is connected to one (or several) processors + with SPMI bus. It has 2 slaves with several peripherals: + - 18x LDO + - 4x GPIO + - Power and Reset buttons + - Watchdog + - RTC + - Vibrator drivers + - Others + + Driver binding info: doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt config PMIC_RK8XX bool "Enable support for Rockchip PMIC RK8XX" select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF - ---help--- - The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, - an RTC and two low Rds (resistance (drain to source)) switches. It is - accessed via an I2C interface. The device is used with Rockchip SoCs. - This driver implements register read/write operations. + help + The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, + an RTC and two low Rds (resistance (drain to source)) switches. It is + accessed via an I2C interface. The device is used with Rockchip SoCs. + This driver implements register read/write operations. config SPL_PMIC_RK8XX bool "Enable support for Rockchip PMIC RK8XX in SPL" depends on SPL_DM_PMIC - ---help--- - The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, - an RTC and two low Rds (resistance (drain to source)) switches. It is - accessed via an I2C interface. The device is used with Rockchip SoCs. - This driver implements register read/write operations. + help + The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, + an RTC and two low Rds (resistance (drain to source)) switches. It is + accessed via an I2C interface. The device is used with Rockchip SoCs. + This driver implements register read/write operations. config PMIC_S2MPS11 bool "Enable Driver Model for PMIC Samsung S2MPS11" - ---help--- - The Samsung S2MPS11 PMIC provides: - - 38 adjustable LDO regulators - - 9 High-Efficiency Buck Converters - - 1 BuckBoost Converter - - RTC with two alarms - - Backup battery charger - - I2C Configuration Interface - This driver provides access to I/O interface only. - Binding info: doc/device-tree-bindings/pmic/s2mps11.txt + help + The Samsung S2MPS11 PMIC provides: + - 38 adjustable LDO regulators + - 9 High-Efficiency Buck Converters + - 1 BuckBoost Converter + - RTC with two alarms + - Backup battery charger + - I2C Configuration Interface + This driver provides access to I/O interface only. + Binding info: doc/device-tree-bindings/pmic/s2mps11.txt config DM_PMIC_SANDBOX bool "Enable Driver Model for emulated Sandbox PMIC" - ---help--- - Enable the driver for Sandbox PMIC emulation. The emulated PMIC device - depends on two drivers: - - sandbox PMIC I/O driver - implements dm pmic operations - - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission - - A detailed information can be found in header: '' - - The Sandbox PMIC info: - * I/O interface: - - I2C chip address: 0x40 - - first register address: 0x0 - - register count: 0x10 - * Adjustable outputs: - - 2x LDO - - 2x BUCK - - Each, with a different operating conditions (header). - * Reset values: - - set by i2c emul driver's probe() (defaults in header) - - Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt + help + Enable the driver for Sandbox PMIC emulation. The emulated PMIC device + depends on two drivers: + - sandbox PMIC I/O driver - implements dm pmic operations + - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission + + A detailed information can be found in header: '' + + The Sandbox PMIC info: + * I/O interface: + - I2C chip address: 0x40 + - first register address: 0x0 + - register count: 0x10 + * Adjustable outputs: + - 2x LDO + - 2x BUCK + - Each, with a different operating conditions (header). + * Reset values: + - set by i2c emul driver's probe() (defaults in header) + + Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt config DM_PMIC_CPCAP bool "Enable Driver Model for Motorola CPCAP" help - The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC - whose main purpose is power control. It was used in a wide variety of - Motorola products, both Tegra and OMAP based. The most notable devices - using this PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2. - Unlike most PMICs, this one is not I2C based; it uses the SPI bus. The - core driver provides both read and write access to the device registers. + The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC + whose main purpose is power control. It was used in a wide variety of + Motorola products, both Tegra and OMAP based. The most notable devices + using this PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2. + Unlike most PMICs, this one is not I2C based; it uses the SPI bus. The + core driver provides both read and write access to the device registers. config PMIC_S5M8767 bool "Enable Driver Model for the Samsung S5M8767 PMIC" - ---help--- - The S5M8767 PMIC provides a large array of LDOs and BUCKs for use - as a SoC power controller. It also provides 32KHz clock outputs. This - driver provides basic register access and sets up the attached - regulators if regulator support is enabled. + help + The S5M8767 PMIC provides a large array of LDOs and BUCKs for use + as a SoC power controller. It also provides 32KHz clock outputs. This + driver provides basic register access and sets up the attached + regulators if regulator support is enabled. config PMIC_RN5T567 bool "Enable driver for Ricoh RN5T567 PMIC" - ---help--- - The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO - regulators Real-Time Clock and 4 GPIOs. This driver provides - register access only. + help + The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO + regulators Real-Time Clock and 4 GPIOs. This driver provides + register access only. config SPL_PMIC_RN5T567 bool "Enable driver for Ricoh RN5T567 PMIC in SPL" depends on SPL_DM_PMIC - ---help--- - The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO - regulators Real-Time Clock and 4 GPIOs. This driver provides - register access only. + help + The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO + regulators Real-Time Clock and 4 GPIOs. This driver provides + register access only. config PMIC_TPS65090 bool "Enable driver for Texas Instruments TPS65090 PMIC" - ---help--- - The TPS65090 is a PMIC containing several LDOs, DC to DC convertors, - FETs and a battery charger. This driver provides register access - only, and you can enable the regulator/charger drivers separately if - required. + help + The TPS65090 is a PMIC containing several LDOs, DC to DC convertors, + FETs and a battery charger. This driver provides register access + only, and you can enable the regulator/charger drivers separately if + required. config PMIC_PALMAS bool "Enable driver for Texas Instruments PALMAS PMIC" - ---help--- - The PALMAS is a PMIC containing several LDOs, SMPS. - This driver binds the pmic children. + help + The PALMAS is a PMIC containing several LDOs, SMPS. + This driver binds the pmic children. config PMIC_LP873X bool "Enable driver for Texas Instruments LP873X PMIC" - ---help--- - The LP873X is a PMIC containing couple of LDOs and couple of SMPS. - This driver binds the pmic children. + help + The LP873X is a PMIC containing couple of LDOs and couple of SMPS. + This driver binds the pmic children. config PMIC_LP87565 bool "Enable driver for Texas Instruments LP87565 PMIC" - ---help--- - The LP87565 is a PMIC containing a bunch of SMPS. - This driver binds the pmic children. + help + The LP87565 is a PMIC containing a bunch of SMPS. + This driver binds the pmic children. config DM_PMIC_TPS65910 bool "Enable driver for Texas Instruments TPS65910 PMIC" - ---help--- - The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost - DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO - pmic children. + help + The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost + DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO + pmic children. config DM_PMIC_TPS80031 bool "Enable driver for Texas Instruments TPS80031/TPS80032 PMIC" - ---help--- - This config enables implementation of driver-model pmic uclass features - for TPS80031/TPS80032 PMICs. The driver implements read/write operations. - This is a Power Management IC with a decent set of peripherals from which - 5 Buck Converters referred as Switched-mode power supply (SMPS), 11 General- - Purpose Low-Dropout Voltage Regulators (LDO), USB OTG Module, Real-Time - Clock (RTC) with Timer and Alarm Wake-Up, Two Digital PWM Outputs and more - with I2C Compatible Interface. PMIC occupies 4 I2C addresses. + help + This config enables implementation of driver-model pmic uclass features + for TPS80031/TPS80032 PMICs. The driver implements read/write operations. + This is a Power Management IC with a decent set of peripherals from which + 5 Buck Converters referred as Switched-mode power supply (SMPS), 11 General- + Purpose Low-Dropout Voltage Regulators (LDO), USB OTG Module, Real-Time + Clock (RTC) with Timer and Alarm Wake-Up, Two Digital PWM Outputs and more + with I2C Compatible Interface. PMIC occupies 4 I2C addresses. config PMIC_STPMIC1 bool "Enable support for STMicroelectronics STPMIC1 PMIC" depends on DM_I2C select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF && !ARM_PSCI_FW - ---help--- - The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. - It is accessed via an I2C interface. The device is used with STM32MP1 - SoCs. This driver implements register read/write operations. + help + The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. + It is accessed via an I2C interface. The device is used with STM32MP1 + SoCs. This driver implements register read/write operations. config SPL_PMIC_PALMAS bool "Enable driver for Texas Instruments PALMAS PMIC" depends on SPL_DM_PMIC help - The PALMAS is a PMIC containing several LDOs, SMPS. - This driver binds the pmic children in SPL. + The PALMAS is a PMIC containing several LDOs, SMPS. + This driver binds the pmic children in SPL. config SPL_PMIC_LP873X bool "Enable driver for Texas Instruments LP873X PMIC" depends on SPL_DM_PMIC help - The LP873X is a PMIC containing couple of LDOs and couple of SMPS. - This driver binds the pmic children in SPL. + The LP873X is a PMIC containing couple of LDOs and couple of SMPS. + This driver binds the pmic children in SPL. config SPL_PMIC_LP87565 bool "Enable driver for Texas Instruments LP87565 PMIC" depends on SPL_DM_PMIC help - The LP87565 is a PMIC containing a bunch of SMPS. - This driver binds the pmic children in SPL. + The LP87565 is a PMIC containing a bunch of SMPS. + This driver binds the pmic children in SPL. config PMIC_TPS65941 bool "Enable driver for Texas Instruments TPS65941 PMIC" depends on DM_PMIC help - The TPS65941 is a PMIC containing a bunch of SMPS & LDOs. - This driver binds the pmic children. + The TPS65941 is a PMIC containing a bunch of SMPS & LDOs. + This driver binds the pmic children. config PMIC_TPS65219 bool "Enable driver for Texas Instruments TPS65219 PMIC" depends on DM_PMIC help - The TPS65219 is a PMIC containing a bunch of SMPS & LDOs. - This driver binds the pmic children. + The TPS65219 is a PMIC containing a bunch of SMPS & LDOs. + This driver binds the pmic children. config PMIC_RAA215300 bool "Renesas RAA215300 PMIC driver" @@ -445,11 +445,11 @@ endif config PMIC_TPS65217 bool "Enable driver for Texas Instruments TPS65217 PMIC" - ---help--- - The TPS65217 is a PMIC containing several LDOs, DC to DC convertors, - FETs and a battery charger. This driver provides register access - only, and you can enable the regulator/charger drivers separately if - required. + help + The TPS65217 is a PMIC containing several LDOs, DC to DC convertors, + FETs and a battery charger. This driver provides register access + only, and you can enable the regulator/charger drivers separately if + required. config POWER_TPS65218 bool "Enable legacy driver for TPS65218 PMIC" @@ -485,9 +485,9 @@ config POWER_PFUZE3000 config POWER_MC34VR500 bool "Enable driver for Freescale MC34VR500 PMIC" - ---help--- - The MC34VR500 is used in conjunction with the FSL T1 and LS1 series - SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed - via an I2C interface. + help + The MC34VR500 is used in conjunction with the FSL T1 and LS1 series + SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed + via an I2C interface. endif diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index ca5de5b8726..3b3ed97eb9f 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -1,38 +1,38 @@ config DM_REGULATOR bool "Enable Driver Model for REGULATOR drivers (UCLASS_REGULATOR)" depends on DM - ---help--- - This config enables the driver model regulator support. - UCLASS_REGULATOR - designed to provide a common API for basic regulator's - functions, like get/set Voltage or Current value, enable state, etc... - Note: - When enabling this, please read the description, found in the files: - - 'include/power/pmic.h' - - 'include/power/regulator.h' - - 'drivers/power/pmic/pmic-uclass.c' - - 'drivers/power/pmic/regulator-uclass.c' - It's important to call the device_bind() with the proper node offset, - when binding the regulator devices. The pmic_bind_childs() can be used - for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_dev() - otherwise. Detailed information can be found in the header file. + help + This config enables the driver model regulator support. + UCLASS_REGULATOR - designed to provide a common API for basic regulator's + functions, like get/set Voltage or Current value, enable state, etc... + Note: + When enabling this, please read the description, found in the files: + - 'include/power/pmic.h' + - 'include/power/regulator.h' + - 'drivers/power/pmic/pmic-uclass.c' + - 'drivers/power/pmic/regulator-uclass.c' + It's important to call the device_bind() with the proper node offset, + when binding the regulator devices. The pmic_bind_childs() can be used + for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_dev() + otherwise. Detailed information can be found in the header file. config SPL_DM_REGULATOR bool "Enable regulators for SPL" depends on DM_REGULATOR && SPL_POWER - ---help--- - Regulators are seldom needed in SPL. Even if they are accessed, some - code space can be saved by accessing the PMIC registers directly. - Enable this option if you need regulators in SPL and can cope with - the extra code size. + help + Regulators are seldom needed in SPL. Even if they are accessed, some + code space can be saved by accessing the PMIC registers directly. + Enable this option if you need regulators in SPL and can cope with + the extra code size. config REGULATOR_ACT8846 bool "Enable driver for ACT8846 regulator" depends on DM_REGULATOR && PMIC_ACT8846 - ---help--- - Enable support for the regulator functions of the ACT8846 PMIC. The - driver implements get/set api for the various BUCKS and LDOS supported - by the PMIC device. This driver is controlled by a device tree node - which includes voltage limits. + help + Enable support for the regulator functions of the ACT8846 PMIC. The + driver implements get/set api for the various BUCKS and LDOS supported + by the PMIC device. This driver is controlled by a device tree node + which includes voltage limits. config REGULATOR_AS3722 bool "Enable driver for AS7322 regulator" @@ -75,33 +75,33 @@ config DM_REGULATOR_BD71837 bool "Enable Driver Model for ROHM BD71837/BD71847 regulators" depends on DM_REGULATOR && DM_PMIC_BD71837 help - This config enables implementation of driver-model regulator uclass - features for regulators on ROHM BD71837 and BD71847 PMICs. - BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced version - containing 6 bucks and 6 LDOs. The driver implements get/set api for - value and enable. + This config enables implementation of driver-model regulator uclass + features for regulators on ROHM BD71837 and BD71847 PMICs. + BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced version + containing 6 bucks and 6 LDOs. The driver implements get/set api for + value and enable. config SPL_DM_REGULATOR_BD71837 bool "Enable Driver Model for ROHM BD71837/BD71847 regulators in SPL" depends on DM_REGULATOR_BD71837 && SPL help - This config enables implementation of driver-model regulator uclass - features for regulators on ROHM BD71837 and BD71847 in SPL. + This config enables implementation of driver-model regulator uclass + features for regulators on ROHM BD71837 and BD71847 in SPL. config DM_REGULATOR_PCA9450 bool "Enable Driver Model for NXP PCA9450 regulators" depends on DM_REGULATOR && DM_PMIC_PCA9450 help - This config enables implementation of driver-model regulator uclass - features for regulators on NXP PCA9450 PMICs. PCA9450 contains 6 bucks - and 5 LDOS. The driver implements get/set api for value and enable. + This config enables implementation of driver-model regulator uclass + features for regulators on NXP PCA9450 PMICs. PCA9450 contains 6 bucks + and 5 LDOS. The driver implements get/set api for value and enable. config SPL_DM_REGULATOR_PCA9450 bool "Enable Driver Model for NXP PCA9450 regulators in SPL" depends on DM_REGULATOR_PCA9450 && SPL help - This config enables implementation of driver-model regulator uclass - features for regulators on ROHM PCA9450 in SPL. + This config enables implementation of driver-model regulator uclass + features for regulators on ROHM PCA9450 in SPL. config DM_REGULATOR_DA9063 bool "Enable Driver Model for REGULATOR DA9063" @@ -127,55 +127,55 @@ config DM_REGULATOR_PFUZE100 bool "Enable Driver Model for REGULATOR PFUZE100" depends on DM_REGULATOR && DM_PMIC_PFUZE100 default DM_PMIC_PFUZE100 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR PFUZE100. The driver implements get/set api for: - value, enable and mode. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR PFUZE100. The driver implements get/set api for: + value, enable and mode. config SPL_DM_REGULATOR_PFUZE100 bool "Enable Driver Model for REGULATOR PFUZE100 in SPL" depends on SPL_DM_REGULATOR && SPL_DM_PMIC_PFUZE100 default SPL_DM_PMIC_PFUZE100 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR PFUZE100. The driver implements get/set api for: - value, enable and mode. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR PFUZE100. The driver implements get/set api for: + value, enable and mode. config REGULATOR_PWM bool "Enable driver for PWM regulators" depends on DM_REGULATOR && DM_PWM - ---help--- - Enable support for the PWM regulator functions which voltage are - controlled by PWM duty ratio. Some of Rockchip board using this kind - of regulator. The driver implements get/set api for the various BUCKS. - This driver is controlled by a device tree node - which includes voltage limits. + help + Enable support for the PWM regulator functions which voltage are + controlled by PWM duty ratio. Some of Rockchip board using this kind + of regulator. The driver implements get/set api for the various BUCKS. + This driver is controlled by a device tree node + which includes voltage limits. config DM_REGULATOR_MAX8907 bool "Enable Driver Model for REGULATOR MAX8907" depends on DM_REGULATOR && DM_PMIC_MAX8907 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR MAX8907. The driver supports both DC-to-DC - Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators - found in MAX8907 PMIC and implements get/set api for value and enable. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR MAX8907. The driver supports both DC-to-DC + Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators + found in MAX8907 PMIC and implements get/set api for value and enable. config DM_REGULATOR_MAX77663 bool "Enable Driver Model for REGULATOR MAX77663" depends on DM_REGULATOR && DM_PMIC_MAX77663 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR MAX77663. The driver supports both DC-to-DC - Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators - found in MAX77663 PMIC and implements get/set api for value and enable. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR MAX77663. The driver supports both DC-to-DC + Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators + found in MAX77663 PMIC and implements get/set api for value and enable. config DM_REGULATOR_MAX77686 bool "Enable Driver Model for REGULATOR MAX77686" depends on DM_REGULATOR && DM_PMIC_MAX77686 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR MAX77686. The driver implements get/set api for: - value, enable and mode. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR MAX77686. The driver implements get/set api for: + value, enable and mode. config DM_REGULATOR_NPCM8XX bool "Enable Driver Model for NPCM8xx voltage supply" @@ -221,33 +221,33 @@ config DM_REGULATOR_FIXED bool "Enable Driver Model for REGULATOR Fixed value" depends on DM_REGULATOR select DM_REGULATOR_COMMON - ---help--- - This config enables implementation of driver-model regulator uclass - features for fixed value regulators. The driver implements get/set api - for enable and get only for voltage value. + help + This config enables implementation of driver-model regulator uclass + features for fixed value regulators. The driver implements get/set api + for enable and get only for voltage value. config SPL_DM_REGULATOR_FIXED bool "Enable Driver Model for REGULATOR Fixed value in SPL" depends on DM_REGULATOR_FIXED && SPL select SPL_DM_REGULATOR_COMMON - ---help--- - This config enables implementation of driver-model regulator uclass - features for fixed value regulators in SPL. + help + This config enables implementation of driver-model regulator uclass + features for fixed value regulators in SPL. config DM_REGULATOR_GPIO bool "Enable Driver Model for GPIO REGULATOR" depends on DM_REGULATOR && DM_GPIO select DM_REGULATOR_COMMON - ---help--- - This config enables implementation of driver-model regulator uclass - features for gpio regulators. The driver implements get/set for - voltage value. + help + This config enables implementation of driver-model regulator uclass + features for gpio regulators. The driver implements get/set for + voltage value. config DM_REGULATOR_QCOM_RPMH bool "Enable driver model for Qualcomm RPMh regulator" depends on DM_REGULATOR && QCOM_RPMH select DEVRES - ---help--- + help Enable support for the Qualcomm RPMh regulator. The driver implements get/set api for a limited set of regulators used by u-boot. @@ -255,7 +255,7 @@ config DM_REGULATOR_QCOM_RPMH config DM_REGULATOR_QCOM_USB_VBUS bool "Enable driver model for Qualcomm USB vbus regulator" depends on DM_REGULATOR && DM_PMIC - ---help--- + help Enable support for the Qualcomm USB Vbus regulator. The driver implements get/set api for the regulator to be used by u-boot. @@ -263,18 +263,18 @@ config SPL_DM_REGULATOR_GPIO bool "Enable Driver Model for GPIO REGULATOR in SPL" depends on DM_REGULATOR_GPIO && SPL_DM_GPIO select SPL_DM_REGULATOR_COMMON - ---help--- - This config enables implementation of driver-model regulator uclass - features for gpio regulators in SPL. + help + This config enables implementation of driver-model regulator uclass + features for gpio regulators in SPL. config REGULATOR_RK8XX bool "Enable driver for RK8XX regulators" depends on DM_REGULATOR && PMIC_RK8XX - ---help--- - Enable support for the regulator functions of the RK8XX PMIC. The - driver implements get/set api for the various BUCKS and LDOs supported - by the PMIC device. This driver is controlled by a device tree node - which includes voltage limits. + help + Enable support for the regulator functions of the RK8XX PMIC. The + driver implements get/set api for the various BUCKS and LDOs supported + by the PMIC device. This driver is controlled by a device tree node + which includes voltage limits. config SPL_REGULATOR_RK8XX bool "Enable driver for RK8XX regulators in SPL" @@ -288,162 +288,162 @@ config SPL_REGULATOR_RK8XX config DM_REGULATOR_S2MPS11 bool "Enable driver for S2MPS11 regulator" depends on DM_REGULATOR && PMIC_S2MPS11 - ---help--- - This enables implementation of driver-model regulator uclass - features for REGULATOR S2MPS11. - The driver implements get/set api for: value and enable. + help + This enables implementation of driver-model regulator uclass + features for REGULATOR S2MPS11. + The driver implements get/set api for: value and enable. config REGULATOR_S5M8767 bool "Enable support for S5M8767 regulator" depends on DM_REGULATOR && PMIC_S5M8767 - ---help--- - This enables the regulator features of the S5M8767, allowing voltages - to be set, etc. The driver is not fully complete but supports most - common requirements, including all LDOs and BUCKs. This allows many - supplies to be set automatically using the device tree values. + help + This enables the regulator features of the S5M8767, allowing voltages + to be set, etc. The driver is not fully complete but supports most + common requirements, including all LDOs and BUCKs. This allows many + supplies to be set automatically using the device tree values. config DM_REGULATOR_SANDBOX bool "Enable Driver Model for Sandbox PMIC regulator" depends on DM_REGULATOR && DM_PMIC_SANDBOX - ---help--- - Enable the regulator driver for emulated Sandbox PMIC. - The emulated PMIC device depends on two drivers: - - sandbox PMIC I/O driver - implements dm pmic operations - - sandbox PMIC regulator driver - implements dm regulator operations - - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission - - The regulator driver provides uclass operations for sandbox PMIC's - regulators. The driver implements get/set api for: voltage, current, - operation mode and enable state. - The driver supports LDO and BUCK regulators. - - The Sandbox PMIC info: - * I/O interface: - - I2C chip address: 0x40 - - first register address: 0x0 - - register count: 0x10 - * Adjustable outputs: - - 2x LDO - - 2x BUCK - - Each, with a different operating conditions (header). - * Reset values: - - set by i2c emul driver's probe() (defaults in header) - - A detailed information can be found in header: '' - Binding info: 'doc/device-tree-bindings/pmic/max77686.txt' + help + Enable the regulator driver for emulated Sandbox PMIC. + The emulated PMIC device depends on two drivers: + - sandbox PMIC I/O driver - implements dm pmic operations + - sandbox PMIC regulator driver - implements dm regulator operations + - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission + + The regulator driver provides uclass operations for sandbox PMIC's + regulators. The driver implements get/set api for: voltage, current, + operation mode and enable state. + The driver supports LDO and BUCK regulators. + + The Sandbox PMIC info: + * I/O interface: + - I2C chip address: 0x40 + - first register address: 0x0 + - register count: 0x10 + * Adjustable outputs: + - 2x LDO + - 2x BUCK + - Each, with a different operating conditions (header). + * Reset values: + - set by i2c emul driver's probe() (defaults in header) + + A detailed information can be found in header: '' + Binding info: 'doc/device-tree-bindings/pmic/max77686.txt' config REGULATOR_TPS65090 bool "Enable driver for TPS65090 PMIC regulators" depends on PMIC_TPS65090 - ---help--- - The TPS65090 provides several FETs (Field-effect Transistors, - effectively switches) which are supported by this driver as - regulators, one for each FET. The standard regulator interface is - supported, but it is only possible to turn the regulators on or off. - There is no voltage/current control. + help + The TPS65090 provides several FETs (Field-effect Transistors, + effectively switches) which are supported by this driver as + regulators, one for each FET. The standard regulator interface is + supported, but it is only possible to turn the regulators on or off. + There is no voltage/current control. config DM_REGULATOR_PALMAS bool "Enable driver for PALMAS PMIC regulators" - depends on PMIC_PALMAS - ---help--- - This enables implementation of driver-model regulator uclass - features for REGULATOR PALMAS and the family of PALMAS PMICs. - The driver implements get/set api for: value and enable. + depends on PMIC_PALMAS + help + This enables implementation of driver-model regulator uclass + features for REGULATOR PALMAS and the family of PALMAS PMICs. + The driver implements get/set api for: value and enable. config DM_REGULATOR_PBIAS bool "Enable driver for PBIAS regulator" depends on DM_REGULATOR select REGMAP select SYSCON - ---help--- - This enables implementation of driver-model regulator uclass - features for pseudo-regulator PBIAS found in the OMAP SOCs. - This pseudo-regulator is used to provide a BIAS voltage to MMC1 - signal pads and must be configured properly during a voltage switch. - Voltage switching is required by some operating modes of SDcards and - eMMC. + help + This enables implementation of driver-model regulator uclass + features for pseudo-regulator PBIAS found in the OMAP SOCs. + This pseudo-regulator is used to provide a BIAS voltage to MMC1 + signal pads and must be configured properly during a voltage switch. + Voltage switching is required by some operating modes of SDcards and + eMMC. config DM_REGULATOR_LP873X bool "Enable driver for LP873X PMIC regulators" - depends on PMIC_LP873X - ---help--- - This enables implementation of driver-model regulator uclass - features for REGULATOR LP873X and the family of LP873X PMICs. - The driver implements get/set api for: value and enable. + depends on PMIC_LP873X + help + This enables implementation of driver-model regulator uclass + features for REGULATOR LP873X and the family of LP873X PMICs. + The driver implements get/set api for: value and enable. config DM_REGULATOR_LP87565 bool "Enable driver for LP87565 PMIC regulators" - depends on PMIC_LP87565 - ---help--- - This enables implementation of driver-model regulator uclass - features for REGULATOR LP87565 and the family of LP87565 PMICs. - LP87565 series of PMICs have 4 single phase BUCKs that can also - be configured in multi phase modes. The driver implements - get/set api for value and enable. + depends on PMIC_LP87565 + help + This enables implementation of driver-model regulator uclass + features for REGULATOR LP87565 and the family of LP87565 PMICs. + LP87565 series of PMICs have 4 single phase BUCKs that can also + be configured in multi phase modes. The driver implements + get/set api for value and enable. config DM_REGULATOR_STM32_VREFBUF bool "Enable driver for STMicroelectronics STM32 VREFBUF" depends on DM_REGULATOR && (STM32H7 || ARCH_STM32MP) help - This driver supports STMicroelectronics STM32 VREFBUF (voltage - reference buffer) which can be used as voltage reference for - internal ADCs, DACs and also for external components through - dedicated Vref+ pin. + This driver supports STMicroelectronics STM32 VREFBUF (voltage + reference buffer) which can be used as voltage reference for + internal ADCs, DACs and also for external components through + dedicated Vref+ pin. config DM_REGULATOR_TPS65910 bool "Enable driver for TPS65910 PMIC regulators" depends on DM_PMIC_TPS65910 - ---help--- - The TPS65910 PMIC provides 4 SMPSs and 8 LDOs. This driver supports all - regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements - the get/set api for value and enable. + help + The TPS65910 PMIC provides 4 SMPSs and 8 LDOs. This driver supports all + regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements + the get/set api for value and enable. config DM_REGULATOR_TPS65911 bool "Enable driver for TPS65911 PMIC regulators" depends on DM_PMIC_TPS65910 - ---help--- - This config enables implementation of driver-model regulator - uclass features for the TPS65911 PMIC. The driver supports Step-Down - DC-DC Converters for Processor Cores (VDD1 and VDD2), Step-Down DC-DC - Converter for I/O Power (VIO), Controller for External FETs (VDDCtrl) - and LDO Voltage Regulators found in TPS65911 PMIC and implements - get/set api for value and enable. + help + This config enables implementation of driver-model regulator + uclass features for the TPS65911 PMIC. The driver supports Step-Down + DC-DC Converters for Processor Cores (VDD1 and VDD2), Step-Down DC-DC + Converter for I/O Power (VIO), Controller for External FETs (VDDCtrl) + and LDO Voltage Regulators found in TPS65911 PMIC and implements + get/set api for value and enable. config DM_REGULATOR_TPS62360 bool "Enable driver for TPS6236x Power Regulator" depends on DM_REGULATOR help - The TPS6236X DC/DC step down converter provides a single output - power line peaking at 3A current. This driver supports all four - variants of the chip (TPS62360, TPS62361, TPS62362, TPS62363). It - implements the get/set api for value only, as the power line is - always on. + The TPS6236X DC/DC step down converter provides a single output + power line peaking at 3A current. This driver supports all four + variants of the chip (TPS62360, TPS62361, TPS62362, TPS62363). It + implements the get/set api for value only, as the power line is + always on. config DM_REGULATOR_TPS80031 bool "Enable driver for TPS80031/TPS80032 PMIC regulators" depends on DM_PMIC_TPS80031 - ---help--- - This enables implementation of driver-model regulator uclass - features for TPS80031/TPS80032 PMICs. The driver implements - get/set api for: value and enable. + help + This enables implementation of driver-model regulator uclass + features for TPS80031/TPS80032 PMICs. The driver implements + get/set api for: value and enable. config DM_REGULATOR_TPS6287X bool "Enable driver for TPS6287x Power Regulator" depends on DM_REGULATOR help - The TPS6287X is a step down converter with a fast transient - response. This driver supports all four variants of the chip - (TPS62870, TPS62871, TPS62872, TPS62873). It implements the - get/set api for value only, as the power line is always on. + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. config DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators" depends on DM_REGULATOR && PMIC_STPMIC1 - ---help--- - Enable support for the regulator functions of the STPMIC1 PMIC. The - driver implements get/set api for the various BUCKS and LDOs supported - by the PMIC device. This driver is controlled by a device tree node - which includes voltage limits. + help + Enable support for the regulator functions of the STPMIC1 PMIC. The + driver implements get/set api for the various BUCKS and LDOs supported + by the PMIC device. This driver is controlled by a device tree node + which includes voltage limits. config DM_REGULATOR_ANATOP bool "Enable driver for ANATOP regulators" @@ -451,18 +451,18 @@ config DM_REGULATOR_ANATOP select REGMAP select SYSCON help - Enable support for the Freescale i.MX on-chip ANATOP LDO - regulators. It is recommended that this option be enabled on - i.MX6 platform. + Enable support for the Freescale i.MX on-chip ANATOP LDO + regulators. It is recommended that this option be enabled on + i.MX6 platform. config SPL_DM_REGULATOR_TPS6287X bool "Enable driver for TPS6287x Power Regulator" depends on SPL_DM_REGULATOR help - The TPS6287X is a step down converter with a fast transient - response. This driver supports all four variants of the chip - (TPS62870, TPS62871, TPS62872, TPS62873). It implements the - get/set api for value only, as the power line is always on. + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. config SPL_DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators in SPL" @@ -474,54 +474,54 @@ config SPL_DM_REGULATOR_PALMAS bool "Enable driver for PALMAS PMIC regulators" depends on SPL_PMIC_PALMAS help - This enables implementation of driver-model regulator uclass - features for REGULATOR PALMAS and the family of PALMAS PMICs. - The driver implements get/set api for: value and enable in SPL. + This enables implementation of driver-model regulator uclass + features for REGULATOR PALMAS and the family of PALMAS PMICs. + The driver implements get/set api for: value and enable in SPL. config SPL_DM_REGULATOR_LP87565 bool "Enable driver for LP87565 PMIC regulators" depends on SPL_PMIC_LP87565 help - This enables implementation of driver-model regulator uclass - features for REGULATOR LP87565 and the family of LP87565 PMICs. - LP87565 series of PMICs have 4 single phase BUCKs that can also - be configured in multi phase modes. The driver implements - get/set api for value and enable in SPL. + This enables implementation of driver-model regulator uclass + features for REGULATOR LP87565 and the family of LP87565 PMICs. + LP87565 series of PMICs have 4 single phase BUCKs that can also + be configured in multi phase modes. The driver implements + get/set api for value and enable in SPL. config SPL_DM_REGULATOR_LP873X bool "Enable driver for LP873X PMIC regulators" depends on SPL_PMIC_LP873X help - This enables implementation of driver-model regulator uclass - features for REGULATOR LP873X and the family of LP873X PMICs. - The driver implements get/set api for: value and enable in SPL. + This enables implementation of driver-model regulator uclass + features for REGULATOR LP873X and the family of LP873X PMICs. + The driver implements get/set api for: value and enable in SPL. config DM_REGULATOR_TPS65941 bool "Enable driver for TPS65941 PMIC regulators" - depends on PMIC_TPS65941 + depends on PMIC_TPS65941 help - This enables implementation of driver-model regulator uclass - features for REGULATOR TPS65941 and the family of TPS65941 PMICs. - TPS65941 series of PMICs have 5 single phase BUCKs that can also - be configured in multi phase modes & 4 LDOs. The driver implements - get/set api for value and enable. + This enables implementation of driver-model regulator uclass + features for REGULATOR TPS65941 and the family of TPS65941 PMICs. + TPS65941 series of PMICs have 5 single phase BUCKs that can also + be configured in multi phase modes & 4 LDOs. The driver implements + get/set api for value and enable. config DM_REGULATOR_SCMI bool "Enable driver for SCMI voltage domain regulators" depends on DM_REGULATOR select SCMI_AGENT - help - Enable this option if you want to support regulators exposed through + help + Enable this option if you want to support regulators exposed through the SCMI voltage domain protocol by a SCMI server. config DM_REGULATOR_TPS65219 bool "Enable driver for TPS65219 PMIC regulators" - depends on PMIC_TPS65219 + depends on PMIC_TPS65219 help - This enables implementation of driver-model regulator uclass - features for REGULATOR TPS65219 and the family of TPS65219 PMICs. - TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs. - The driver implements get/set api for value and enable. + This enables implementation of driver-model regulator uclass + features for REGULATOR TPS65219 and the family of TPS65219 PMICs. + TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs. + The driver implements get/set api for value and enable. config REGULATOR_RZG2L_USBPHY bool "Enable driver for RZ/G2L USB PHY VBUS supply" @@ -534,11 +534,11 @@ config REGULATOR_RZG2L_USBPHY config DM_REGULATOR_CPCAP bool "Enable driver for CPCAP PMIC regulators" depends on DM_REGULATOR && DM_PMIC_CPCAP - ---help--- - Enable implementation of driver-model regulator uclass features for - REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching - (SW) Regulators and Low-Dropout Linear (LDO) Regulators found in CPCAP - PMIC and implements get/set api for voltage and state. + help + Enable implementation of driver-model regulator uclass features for + REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching + (SW) Regulators and Low-Dropout Linear (LDO) Regulators found in CPCAP + PMIC and implements get/set api for voltage and state. config DM_REGULATOR_MT6357 bool "Enable driver for MediaTek MT6357 PMIC regulators" -- cgit v1.3.1 From 8b09b702d488799ee42fbc7be3b8434e8a1c2fa0 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Wed, 10 Jun 2026 16:40:27 +0200 Subject: Kconfig: usb: restyle Restyle all Kconfigs for "usb": Menu entries : no space left Menu attributes: 1 TAB Help text : 1 TAB + 2 spaces Replace '---help---' by 'help' Signed-off-by: Johan Jonker --- drivers/usb/Kconfig | 16 ++++++++-------- drivers/usb/eth/Kconfig | 16 ++++++++-------- drivers/usb/gadget/Kconfig | 22 +++++++++++----------- drivers/usb/host/Kconfig | 44 ++++++++++++++++++++++---------------------- drivers/usb/musb-new/Kconfig | 14 +++++++------- 5 files changed, 56 insertions(+), 56 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 93c5ee69b25..05ac388ecf2 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -1,7 +1,7 @@ menuconfig USB bool "USB support" select BLK - ---help--- + help Universal Serial Bus (USB) is a specification for a serial bus subsystem which offers higher speeds and more features than the traditional PC serial port. The bus supplies power to peripherals @@ -94,7 +94,7 @@ comment "USB peripherals" config USB_STORAGE bool "USB Mass Storage support" - ---help--- + help Say Y here if you want to connect USB mass storage devices to your board's USB port. @@ -103,7 +103,7 @@ config USB_KEYBOARD depends on DM_USB select DM_KEYBOARD select SYS_STDIO_DEREGISTER - ---help--- + help Say Y here if you want to use a USB keyboard for U-Boot command line input. @@ -111,7 +111,7 @@ config USB_ONBOARD_HUB bool "Onboard USB hub support" depends on DM_USB select DEVRES - ---help--- + help Say Y here if you want to support discrete onboard USB hubs that don't require an additional control bus for initialization, but need some non-trivial form of initialization, such as enabling a @@ -163,17 +163,17 @@ choice prompt "USB keyboard polling" default SYS_USB_EVENT_POLL_VIA_INT_QUEUE if ARCH_SUNXI default SYS_USB_EVENT_POLL - ---help--- + help Enable a polling mechanism for USB keyboard. config SYS_USB_EVENT_POLL - bool "Interrupt polling" + bool "Interrupt polling" config SYS_USB_EVENT_POLL_VIA_INT_QUEUE - bool "Poll via interrupt queue" + bool "Poll via interrupt queue" config SYS_USB_EVENT_POLL_VIA_CONTROL_EP - bool "Poll via control EP" + bool "Poll via control EP" endchoice diff --git a/drivers/usb/eth/Kconfig b/drivers/usb/eth/Kconfig index 2f6bfa8e71b..b9b77f46743 100644 --- a/drivers/usb/eth/Kconfig +++ b/drivers/usb/eth/Kconfig @@ -1,6 +1,6 @@ menuconfig USB_HOST_ETHER bool "USB to Ethernet Controller Drivers" - ---help--- + help Say Y here if you would like to enable support for USB Ethernet adapters. @@ -9,14 +9,14 @@ if USB_HOST_ETHER config USB_ETHER_ASIX bool "ASIX AX8817X (USB 2.0) support" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support ASIX AX8817X based USB 2.0 Ethernet Devices. config USB_ETHER_ASIX88179 bool "ASIX AX88179 (USB 3.0) support" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support ASIX AX88179 based USB 3.0 Ethernet Devices. @@ -24,7 +24,7 @@ config USB_ETHER_LAN75XX bool "Microchip LAN75XX support" depends on USB_HOST_ETHER depends on PHYLIB - ---help--- + help Say Y here if you would like to support Microchip LAN75XX Hi-Speed USB 2.0 to 10/100/1000 Gigabit Ethernet controller. Supports 10Base-T/ 100Base-TX/1000Base-T. @@ -34,7 +34,7 @@ config USB_ETHER_LAN78XX bool "Microchip LAN78XX support" depends on USB_HOST_ETHER depends on PHYLIB - ---help--- + help Say Y here if you would like to support Microchip LAN78XX USB 3.1 Gen 1 to 10/100/1000 Gigabit Ethernet controller. Supports 10Base-T/ 100Base-TX/1000Base-T. @@ -43,14 +43,14 @@ config USB_ETHER_LAN78XX config USB_ETHER_MCS7830 bool "MOSCHIP MCS7830 (7730/7830/7832) suppport" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support MOSCHIP MCS7830 based (7730/7830/7832) USB 2.0 Ethernet Devices. config USB_ETHER_RTL8152 bool "Realtek RTL8152B/RTL8153 support" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support Realtek RTL8152B/RTL8153 base USB Ethernet Devices. This driver also supports compatible devices from Samsung, Lenovo, TP-LINK and Nvidia. @@ -58,7 +58,7 @@ config USB_ETHER_RTL8152 config USB_ETHER_SMSC95XX bool "SMSC LAN95x support" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support SMSC LAN95xx based USB 2.0 Ethernet Devices. diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 5390878254a..e42d5a43696 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -19,10 +19,10 @@ menuconfig USB_GADGET select DM_USB imply CMD_BIND help - USB is a master/slave protocol, organized with one master - host (such as a PC) controlling up to 127 peripheral devices. - The USB hardware is asymmetric, which makes it easier to set up: - you can't connect a "to-the-host" connector to a peripheral. + USB is a master/slave protocol, organized with one master + host (such as a PC) controlling up to 127 peripheral devices. + The USB hardware is asymmetric, which makes it easier to set up: + you can't connect a "to-the-host" connector to a peripheral. U-Boot can run in the host, or in the peripheral. In both cases you need a low level bus controller driver, and some software @@ -164,10 +164,10 @@ config USB_GADGET_VBUS_DRAW range 2 500 default 2 help - Some devices need to draw power from USB when they are - configured, perhaps to operate circuitry or to recharge - batteries. This is in addition to any local power supply, - such as an AC adapter or batteries. + Some devices need to draw power from USB when they are + configured, perhaps to operate circuitry or to recharge + batteries. This is in addition to any local power supply, + such as an AC adapter or batteries. Enter the maximum power your device draws through USB, in milliAmperes. The permitted range of values is 2 - 500 mA; @@ -350,9 +350,9 @@ config SPL_DFU_RAM bool "RAM device" depends on SPL_DFU && SPL_RAM_SUPPORT help - select RAM/DDR memory device for loading binary images - (u-boot/kernel) to the selected device partition using - DFU and execute the u-boot/kernel from RAM. + select RAM/DDR memory device for loading binary images + (u-boot/kernel) to the selected device partition using + DFU and execute the u-boot/kernel from RAM. endchoice diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index d75883e2865..6bbed9cb513 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -24,7 +24,7 @@ config USB_XHCI_HCD bool "xHCI HCD (USB 3.0) support" depends on DM && OF_CONTROL select USB_HOST - ---help--- + help The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 "SuperSpeed" host controller hardware. @@ -149,7 +149,7 @@ config USB_EHCI_HCD select USB_HOST select EHCI_DESC_BIG_ENDIAN if SYS_BIG_ENDIAN select EHCI_MMIO_BIG_ENDIAN if SYS_BIG_ENDIAN - ---help--- + help The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. If your USB host controller supports USB 2.0, you will likely want to @@ -174,14 +174,14 @@ config USB_EHCI_ATMEL bool "Support for Atmel on-chip EHCI USB controller" depends on ARCH_AT91 default y - ---help--- + help Enables support for the on-chip EHCI controller on Atmel chips. config USB_EHCI_EXYNOS bool "Support for Samsung Exynos EHCI USB controller" depends on ARCH_EXYNOS default y - ---help--- + help Enables support for the on-chip EHCI controller on Samsung Exynos SoCs. @@ -191,7 +191,7 @@ config USB_EHCI_MARVELL default y select USB_EHCI_IS_TDI if !ARM64 select USB_EHCI_IS_TDI if ALLEYCAT_5 - ---help--- + help Enables support for the on-chip EHCI controller on MVEBU SoCs. config USB_EHCI_MX5 @@ -205,7 +205,7 @@ config USB_EHCI_MX6 depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT select EHCI_HCD_INIT_AFTER_RESET default y - ---help--- + help Enables support for the on-chip EHCI controller on i.MX6 SoCs. config USB_EHCI_MX7 @@ -215,7 +215,7 @@ config USB_EHCI_MX7 select PHY if IMX8M || IMX9 select NOP_PHY if IMX8M || IMX9 default y - ---help--- + help Enables support for the on-chip EHCI controller on i.MX7/i.MX8M/i.MX9 SoCs. config USB_EHCI_MXS @@ -230,7 +230,7 @@ config USB_EHCI_MXS config USB_EHCI_NPCM bool "Support for Nuvoton NPCM on-chip EHCI USB controller" depends on ARCH_NPCM - ---help--- + help Enables support for the on-chip EHCI controller on Nuvoton NPCM chips. @@ -240,7 +240,7 @@ config USB_EHCI_OMAP select PHY imply NOP_PHY default y - ---help--- + help Enables support for the on-chip EHCI controller on OMAP3 and later SoCs. @@ -255,7 +255,7 @@ if USB_EHCI_MX6 || USB_EHCI_MX7 config MXC_USB_OTG_HACTIVE bool "USB Power pin high active" - ---help--- + help Set the USB Power pin polarity to be high active (PWR_POL) endif @@ -265,7 +265,7 @@ config USB_EHCI_MSM depends on DM_USB select USB_ULPI select MSM8916_USB_PHY - ---help--- + help Enables support for the on-chip EHCI controller on Qualcomm Snapdragon SoCs. @@ -280,7 +280,7 @@ config USB_EHCI_TEGRA bool "Support for NVIDIA Tegra on-chip EHCI USB controller" depends on ARCH_TEGRA select USB_EHCI_IS_TDI - ---help--- + help Enable support for Tegra on-chip EHCI USB controller. If you enable ULPI and your PHY needs a different reference clock than the standard 24 MHz then you have to define CFG_ULPI_REF_CLK to the appropriate @@ -291,14 +291,14 @@ config USB_EHCI_ZYNQ depends on ARCH_ZYNQ default y select USB_EHCI_IS_TDI - ---help--- + help Enable support for Zynq on-chip EHCI USB controller config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on DM_USB default ARCH_SUNXI - ---help--- + help Enables support for generic EHCI controller. config EHCI_HCD_INIT_AFTER_RESET @@ -310,7 +310,7 @@ config USB_EHCI_FSL select EHCI_HCD_INIT_AFTER_RESET select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \ !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020) - ---help--- + help Enables support for the on-chip EHCI controller on FSL chips. config SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -340,7 +340,7 @@ config USB_OHCI_HCD depends on DM && OF_CONTROL select USB_HOST select USB_OHCI_NEW - ---help--- + help The Open Host Controller Interface (OHCI) is a standard for accessing USB 1.1 host controller hardware. It does more in hardware than Intel's UHCI specification. If your USB host controller follows the OHCI spec, @@ -361,7 +361,7 @@ config USB_OHCI_PCI config USB_OHCI_GENERIC bool "Support for generic OHCI USB controller" default ARCH_SUNXI - ---help--- + help Enables support for generic OHCI controller. config USB_OHCI_DA8XX @@ -374,7 +374,7 @@ config USB_OHCI_DA8XX config USB_OHCI_NPCM bool "Support for Nuvoton NPCM on-chip OHCI USB controller" depends on ARCH_NPCM - ---help--- + help Enables support for the on-chip OHCI controller on Nuvoton NPCM chips. @@ -391,7 +391,7 @@ config SYS_OHCI_SWAP_REG_ACCESS config USB_UHCI_HCD bool "UHCI HCD (most Intel and VIA) support" select USB_HOST - ---help--- + help The Universal Host Controller Interface is a standard by Intel for accessing the USB hardware in the PC (which is also called the USB host controller). If your USB host controller conforms to this @@ -410,7 +410,7 @@ config USB_DWC2 bool "DesignWare USB2 Core support" depends on DM && OF_CONTROL select USB_HOST - ---help--- + help The DesignWare USB 2.0 controller is compliant with the USB-Implementers Forum (USB-IF) USB 2.0 specifications. Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) @@ -421,7 +421,7 @@ if USB_DWC2 config USB_DWC2_BUFFER_SIZE int "Data buffer size in kB" default 64 - ---help--- + help By default 64 kB buffer is used but if amount of RAM avaialble on the target is not enough to accommodate allocation of buffer of that size it is possible to shrink it. Smaller sizes should be fine @@ -433,7 +433,7 @@ config USB_R8A66597_HCD bool "Renesas R8A66597 USB Core support" depends on DM && OF_CONTROL select USB_HOST - ---help--- + help This enables support for the on-chip Renesas R8A66597 USB 2.0 controller, present in various RZ and SH SoCs. diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index f8daaddc657..6fb37c787de 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -23,11 +23,11 @@ config USB_MUSB_GADGET if USB_MUSB_HOST || USB_MUSB_GADGET config USB_MUSB_SC5XX - bool "Analog Devices MUSB support" - depends on (SC57X || SC58X) + bool "Analog Devices MUSB support" + depends on (SC57X || SC58X) help - Say y here to enable support for the USB controller on - ADI SC57X/SC58X processors. + Say y here to enable support for the USB controller on + ADI SC57X/SC58X processors. config USB_MUSB_DA8XX bool "Enable DA8xx MUSB Controller" @@ -81,9 +81,9 @@ config USB_MUSB_SUNXI depends on PHY_SUN4I_USB select USB_MUSB_PIO_ONLY default y - ---help--- - Say y here to enable support for the sunxi OTG / DRC USB controller - used on almost all sunxi boards. + help + Say y here to enable support for the sunxi OTG / DRC USB controller + used on almost all sunxi boards. config USB_MUSB_UX500 bool "Enable ST-Ericsson Ux500 USB controller" -- cgit v1.3.1 From 55ae284935295843ac6697e67425cc163756c1cf Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Wed, 10 Jun 2026 16:40:50 +0200 Subject: Kconfig: video: restyle Restyle all Kconfigs for "video": Menu entries : no space left Menu attributes: 1 TAB Help text : 1 TAB + 2 spaces Replace '---help---' by 'help' Signed-off-by: Johan Jonker [trini: Add missing indentation on a multi-paragraph help text] Signed-off-by: Tom Rini --- drivers/video/Kconfig | 172 ++++++++++++++++++++--------------------- drivers/video/bridge/Kconfig | 4 +- drivers/video/imx/Kconfig | 2 +- drivers/video/rockchip/Kconfig | 4 +- drivers/video/tegra/Kconfig | 42 +++++----- drivers/video/ti/Kconfig | 2 +- drivers/video/zynqmp/Kconfig | 6 +- 7 files changed, 116 insertions(+), 116 deletions(-) (limited to 'drivers') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 5a0dfb159c4..15000e21840 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -254,10 +254,10 @@ config SYS_WHITE_ON_BLACK bool "Display console as white on a black background" default y if ARCH_AT91 || ARCH_EXYNOS || ARCH_ROCKCHIP || ARCH_TEGRA || X86 || ARCH_SUNXI help - Normally the display is black on a white background, Enable this - option to invert this, i.e. white on a black background. This can be - better in low-light situations or to reduce eye strain in some - cases. + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background. This can be + better in low-light situations or to reduce eye strain in some + cases. config NO_FB_CLEAR bool "Skip framebuffer clear" @@ -515,10 +515,10 @@ config FRAMEBUFFER_VESA_MODE config VIDEO_LCD_ANX9804 bool "ANX9804 bridge chip" - ---help--- - Support for the ANX9804 bridge chip, which can take pixel data coming - from a parallel LCD interface and translate it on the fy into a DP - interface for driving eDP TFT displays. It uses I2C for configuration. + help + Support for the ANX9804 bridge chip, which can take pixel data coming + from a parallel LCD interface and translate it on the fy into a DP + interface for driving eDP TFT displays. It uses I2C for configuration. config ATMEL_LCD bool "Atmel LCD panel support" @@ -556,8 +556,8 @@ config VIDEO_LCD_HIMAX_HX8394 depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Himax HX8394 - dsi 4dl panel. + Say Y here if you want to enable support for Himax HX8394 + dsi 4dl panel. config VIDEO_LCD_ILITEK_ILI9806E bool "Ilitek ILI9806E-based panels" @@ -612,8 +612,8 @@ config VIDEO_LCD_RAYDIUM_RM68200 depends on BACKLIGHT select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Raydium RM68200 - 720x1280 DSI video mode panel. + Say Y here if you want to enable support for Raydium RM68200 + 720x1280 DSI video mode panel. config VIDEO_LCD_RENESAS_R61307 bool "Renesas R61307 DSI video mode panel" @@ -662,38 +662,38 @@ config VIDEO_LCD_SHARP_LQ101R1SX01 config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" - ---help--- - Support for the SSD2828 bridge chip, which can take pixel data coming - from a parallel LCD interface and translate it on the fly into MIPI DSI - interface for driving a MIPI compatible LCD panel. It uses SPI for - configuration. + help + Support for the SSD2828 bridge chip, which can take pixel data coming + from a parallel LCD interface and translate it on the fly into MIPI DSI + interface for driving a MIPI compatible LCD panel. It uses SPI for + configuration. config VIDEO_LCD_SSD2828_TX_CLK int "SSD2828 TX_CLK frequency (in MHz)" depends on VIDEO_LCD_SSD2828 default 0 - ---help--- - The frequency of the crystal, which is clocking SSD2828. It may be - anything in the 8MHz-30MHz range and the exact value should be - retrieved from the board schematics. Or in the case of Allwinner - hardware, it can be usually found as 'lcd_xtal_freq' variable in - FEX files. It can be also set to 0 for selecting PCLK from the - parallel LCD interface instead of TX_CLK as the PLL clock source. + help + The frequency of the crystal, which is clocking SSD2828. It may be + anything in the 8MHz-30MHz range and the exact value should be + retrieved from the board schematics. Or in the case of Allwinner + hardware, it can be usually found as 'lcd_xtal_freq' variable in + FEX files. It can be also set to 0 for selecting PCLK from the + parallel LCD interface instead of TX_CLK as the PLL clock source. config VIDEO_LCD_SSD2828_RESET string "RESET pin of SSD2828" depends on VIDEO_LCD_SSD2828 default "" - ---help--- - The reset pin of SSD2828 chip. This takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + The reset pin of SSD2828 chip. This takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_TDO_TL070WSH30 bool "TDO TL070WSH30 DSI LCD panel support" select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for TDO TL070WSH30 - 1024x600 DSI video mode panel. + Say Y here if you want to enable support for TDO TL070WSH30 + 1024x600 DSI video mode panel. config VIDEO_LCD_HITACHI_TX10D07VM0BAA bool "Hitachi TX10D07VM0BAA 480x800 MIPI DSI video mode panel" @@ -705,10 +705,10 @@ config VIDEO_LCD_HITACHI_TX10D07VM0BAA config VIDEO_LCD_HITACHI_TX18D42VM bool "Hitachi tx18d42vm LVDS LCD panel support" - ---help--- - Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a - lcd controller which needs to be initialized over SPI, once that is - done they work like a regular LVDS panel. + help + Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a + lcd controller which needs to be initialized over SPI, once that is + done they work like a regular LVDS panel. config VIDEO_LCD_SONY_L4F00430T01 bool "Sony L4F00430T01 480x800 LCD panel support" @@ -731,44 +731,44 @@ config VIDEO_LCD_SPI_CS string "SPI CS pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. The option takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_SCLK string "SPI SCLK pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. The option takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_MOSI string "SPI MOSI pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. The option takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_MISO string "SPI MISO pin for LCD related config job (optional)" depends on VIDEO_LCD_SSD2828 default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. If wired up, this pin may provide additional - useful functionality. Such as bi-directional communication with the - hardware and LCD panel id retrieval (if the panel can report it). The - option takes a string in the format understood by 'sunxi_name_to_gpio' - function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. If wired up, this pin may provide additional + useful functionality. Such as bi-directional communication with the + hardware and LCD panel id retrieval (if the panel can report it). The + option takes a string in the format understood by 'sunxi_name_to_gpio' + function, e.g. PH1 for pin 1 of port H. source "drivers/video/meson/Kconfig" @@ -776,9 +776,9 @@ config VIDEO_MVEBU bool "Armada XP LCD controller" depends on ARCH_MVEBU imply VIDEO_DAMAGE - ---help--- - Support for the LCD controller integrated in the Marvell - Armada XP SoC. + help + Support for the LCD controller integrated in the Marvell + Armada XP SoC. config VIDEO_OMAP3 bool "Enable OMAP3+ DSS Support" @@ -789,23 +789,23 @@ config VIDEO_OMAP3 config I2C_EDID bool "Enable EDID library" help - This enables library for accessing EDID data from an LCD panel. + This enables library for accessing EDID data from an LCD panel. config I2C_EDID_STANDARD bool "Enable standard timings EDID library expansion" depends on I2C_EDID help - This enables standard timings expansion for EDID data from an LCD panel. + This enables standard timings expansion for EDID data from an LCD panel. config DISPLAY bool "Enable Display support" depends on DM select I2C_EDID help - This supports drivers that provide a display, such as eDP (Embedded - DisplayPort) and HDMI (High Definition Multimedia Interface). - The devices provide a simple interface to start up the display, - read display information and enable it. + This supports drivers that provide a display, such as eDP (Embedded + DisplayPort) and HDMI (High Definition Multimedia Interface). + The devices provide a simple interface to start up the display, + read display information and enable it. config NXP_TDA19988 bool "Enable NXP TDA19988 support" @@ -819,7 +819,7 @@ config ATMEL_HLCD depends on ARCH_AT91 imply VIDEO_DAMAGE help - HLCDC supports video output to an attached LCD panel. + HLCDC supports video output to an attached LCD panel. config BACKLIGHT_AAT2870 bool "Backlight Driver for AAT2870" @@ -938,9 +938,9 @@ config VIDEO_NX bool "Enable video support on Nexell SoC" depends on ARCH_S5P6818 || ARCH_S5P4418 help - Nexell SoC supports many video output options including eDP and - HDMI. This option enables this support which can be used on devices - which have an eDP display connected. + Nexell SoC supports many video output options including eDP and + HDMI. This option enables this support which can be used on devices + which have an eDP display connected. config VIDEO_SEPS525 bool "Enable video support for Seps525" @@ -1026,9 +1026,9 @@ config OSD bool "Enable OSD support" depends on DM help - This supports drivers that provide a OSD (on-screen display), which - is a (usually text-oriented) graphics buffer to show information on - a display. + This supports drivers that provide a OSD (on-screen display), which + is a (usually text-oriented) graphics buffer to show information on + a display. config SANDBOX_OSD bool "Enable sandbox OSD" @@ -1221,10 +1221,10 @@ config SPL_SPLASH_SCREEN config SPL_SYS_WHITE_ON_BLACK bool "Display console as white on a black background at SPL" help - Normally the display is black on a white background, Enable this - option to invert this, i.e. white on a black background at spl stage. - This can be better in low-light situations or to reduce eye strain in - some cases. + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background at spl stage. + This can be better in low-light situations or to reduce eye strain in + some cases. config SPL_VIDEO_PCI_DEFAULT_FB_SIZE hex "Default framebuffer size to use if no drivers request it at SPL" @@ -1287,10 +1287,10 @@ config SPL_SIMPLE_PANEL config SPL_SYS_WHITE_ON_BLACK bool "Display console as white on a black background at SPL" help - Normally the display is black on a white background, Enable this - option to invert this, i.e. white on a black background at spl stage. - This can be better in low-light situations or to reduce eye strain in - some cases. + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background at spl stage. + This can be better in low-light situations or to reduce eye strain in + some cases. config SPL_VIDEO_REMOVE bool "Remove video driver after SPL stage" @@ -1416,13 +1416,13 @@ config SPL_VIDEO_BPP32 will be empty. config SPL_HIDE_LOGO_VERSION - bool "Hide the version information on the splash screen at SPL" - help - Normally the U-Boot version string is shown on the display when the - splash screen is enabled. This information is not otherwise visible - since video starts up after U-Boot has displayed the initial banner. + bool "Hide the version information on the splash screen at SPL" + help + Normally the U-Boot version string is shown on the display when the + splash screen is enabled. This information is not otherwise visible + since video starts up after U-Boot has displayed the initial banner. - Enable this option to hide this information. + Enable this option to hide this information. endif endmenu diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig index 5322a002928..81261c61005 100644 --- a/drivers/video/bridge/Kconfig +++ b/drivers/video/bridge/Kconfig @@ -41,8 +41,8 @@ config VIDEO_BRIDGE_ANALOGIX_ANX6345 depends on VIDEO_BRIDGE select DM_I2C help - The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD - panel to be connected to an parallel LCD interface. + The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD + panel to be connected to an parallel LCD interface. config VIDEO_BRIDGE_SOLOMON_SSD2825 bool "Solomon SSD2825 bridge driver" diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig index c25f209629e..0c386595559 100644 --- a/drivers/video/imx/Kconfig +++ b/drivers/video/imx/Kconfig @@ -20,7 +20,7 @@ config IPU_CLK_LEGACY depends on VIDEO_IPUV3 && !CLK default y help - Use legacy clock management instead of Common Clock Framework. + Use legacy clock management instead of Common Clock Framework. config IMX_LDB bool "Freescale i.MX8MP LDB bridge" diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 96af6d28ef0..41d249cb90c 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -21,7 +21,7 @@ menuconfig VIDEO_ROCKCHIP Rockchip RK3288 and RK3399. config VIDEO_ROCKCHIP_MAX_XRES - int "Maximum horizontal resolution (for memory allocation purposes)" + int "Maximum horizontal resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP default 3840 if DISPLAY_ROCKCHIP_HDMI default 1920 @@ -31,7 +31,7 @@ config VIDEO_ROCKCHIP_MAX_XRES framebuffer during device-model binding/probing. config VIDEO_ROCKCHIP_MAX_YRES - int "Maximum vertical resolution (for memory allocation purposes)" + int "Maximum vertical resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP default 2160 if DISPLAY_ROCKCHIP_HDMI default 1080 diff --git a/drivers/video/tegra/Kconfig b/drivers/video/tegra/Kconfig index 8bc29f2838b..125504024fc 100644 --- a/drivers/video/tegra/Kconfig +++ b/drivers/video/tegra/Kconfig @@ -9,13 +9,13 @@ config VIDEO_TEGRA depends on OF_CONTROL && ARCH_TEGRA select HOST1X_TEGRA help - Enable support for Display Controller found in Tegra SoC. The - Display Controller Complex integrates two independent display - controllers. Each display controller is capable of interfacing - to an external display device, which can be a parallel interface - or SPI LCD, DVI, an HDMI HDTV, RGB monitor or a MIPI DSI LCD. - Direct interface is supported directly to most LCD displays with - TFT or TFT-like interface. + Enable support for Display Controller found in Tegra SoC. The + Display Controller Complex integrates two independent display + controllers. Each display controller is capable of interfacing + to an external display device, which can be a parallel interface + or SPI LCD, DVI, an HDMI HDTV, RGB monitor or a MIPI DSI LCD. + Direct interface is supported directly to most LCD displays with + TFT or TFT-like interface. config VIDEO_DSI_TEGRA bool "Enable DSI controller support on Tegra devices" @@ -23,9 +23,9 @@ config VIDEO_DSI_TEGRA select VIDEO_TEGRA select VIDEO_MIPI_DSI help - Enable support for the Display Serial Interface (DSI) found in - Tegra SoC. It is a MIPI standard serial bitstream, intended to - provide a low pin count interface to a display panel. + Enable support for the Display Serial Interface (DSI) found in + Tegra SoC. It is a MIPI standard serial bitstream, intended to + provide a low pin count interface to a display panel. config VIDEO_HDMI_TEGRA bool "Enable HDMI support on Tegra devices" @@ -33,31 +33,31 @@ config VIDEO_HDMI_TEGRA select I2C_EDID select VIDEO_TEGRA help - Enable support for the High-Definition Multimedia Interface (HDMI) - found in Tegra SoC. + Enable support for the High-Definition Multimedia Interface (HDMI) + found in Tegra SoC. config TEGRA_BACKLIGHT_PWM bool "Enable Tegra DC PWM backlight support" depends on BACKLIGHT && VIDEO_TEGRA help - Enable support for the Display Controller dependent PWM backlight - found in the Tegra SoC and usually used with DSI panels. + Enable support for the Display Controller dependent PWM backlight + found in the Tegra SoC and usually used with DSI panels. config TEGRA_8BIT_CPU_BRIDGE bool "Enable 8 bit panel communication protocol for Tegra 20/30" depends on VIDEO_BRIDGE && DM_GPIO && VIDEO_TEGRA select VIDEO_MIPI_DSI help - Tegra 20 and Tegra 30 feature 8 bit CPU driver panel control - protocol. This option allows use it as a MIPI DSI bridge to - set up and control compatible panel. + Tegra 20 and Tegra 30 feature 8 bit CPU driver panel control + protocol. This option allows use it as a MIPI DSI bridge to + set up and control compatible panel. config VIDEO_TEGRA124 bool "Enable video support on Tegra124" depends on ARCH_TEGRA imply VIDEO_DAMAGE help - Tegra124 supports many video output options including eDP and - HDMI. At present only eDP is supported by U-Boot. This option - enables this support which can be used on devices which - have an eDP display connected. + Tegra124 supports many video output options including eDP and + HDMI. At present only eDP is supported by U-Boot. This option + enables this support which can be used on devices which + have an eDP display connected. diff --git a/drivers/video/ti/Kconfig b/drivers/video/ti/Kconfig index 0483f760ea1..a3cbefef0de 100644 --- a/drivers/video/ti/Kconfig +++ b/drivers/video/ti/Kconfig @@ -6,4 +6,4 @@ config AM335X_LCD bool "Enable AM335x video support" depends on ARCH_OMAP2PLUS help - Supports video output to an attached LCD panel. + Supports video output to an attached LCD panel. diff --git a/drivers/video/zynqmp/Kconfig b/drivers/video/zynqmp/Kconfig index b35cd1fb342..2c737710639 100644 --- a/drivers/video/zynqmp/Kconfig +++ b/drivers/video/zynqmp/Kconfig @@ -3,6 +3,6 @@ config VIDEO_ZYNQMP_DPSUB bool "Enable video support for ZynqMP Display Port" depends on ZYNQMP_POWER_DOMAIN help - Enable support for Xilinx ZynqMP Display Port. Currently this file - is used as placeholder for driver. The main reason is to record - compatible string and calling power domain driver. + Enable support for Xilinx ZynqMP Display Port. Currently this file + is used as placeholder for driver. The main reason is to record + compatible string and calling power domain driver. -- cgit v1.3.1 From 173ffc7bcfbf6af70cd3b46a30110dad18278f72 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Wed, 10 Jun 2026 16:41:04 +0200 Subject: Kconfig: gpio: add empty line Restyle by adding an empty line between configs. Signed-off-by: Johan Jonker --- drivers/gpio/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 5084af23269..bcd81c510f8 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -756,6 +756,7 @@ config SPL_ADP5585_GPIO depends on SPL_DM_GPIO && SPL_I2C help Support ADP5585 GPIO expander in SPL. + config MPFS_GPIO bool "Enable Polarfire SoC GPIO driver" depends on DM_GPIO -- cgit v1.3.1 From 145d58e2c7276f68195a7fc760457a5b88f867dd Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Wed, 10 Jun 2026 16:41:21 +0200 Subject: Kconfig: drivers: restyle remaining Restyle all Kconfigs for the rest of "drivers": Menu entries : no space left Menu attributes: 1 TAB Help text : 1 TAB + 2 spaces Replace '---help---' by 'help' Signed-off-by: Johan Jonker [trini: Add missing indentation on a few more multi-paragraph help texts] Signed-off-by: Tom Rini --- drivers/adc/Kconfig | 2 +- drivers/block/Kconfig | 8 ++++---- drivers/bootcount/Kconfig | 4 ++-- drivers/clk/Kconfig | 4 ++-- drivers/clk/owl/Kconfig | 8 ++++---- drivers/clk/renesas/Kconfig | 8 ++++---- drivers/crypto/aspeed/Kconfig | 8 ++++---- drivers/crypto/fsl/Kconfig | 10 ++++----- drivers/ddr/fsl/Kconfig | 4 ++-- drivers/dma/ti/Kconfig | 16 +++++++-------- drivers/gpio/Kconfig | 48 +++++++++++++++++++++---------------------- drivers/led/Kconfig | 2 +- drivers/memory/Kconfig | 16 +++++++-------- drivers/mfd/Kconfig | 6 +++--- drivers/misc/Kconfig | 8 ++++---- drivers/mmc/Kconfig | 8 ++++---- drivers/mux/Kconfig | 12 +++++------ drivers/pci/Kconfig | 16 +++++++-------- drivers/pci_endpoint/Kconfig | 8 ++++---- drivers/phy/Kconfig | 18 ++++++++-------- drivers/phy/qcom/Kconfig | 2 +- drivers/ram/aspeed/Kconfig | 14 ++++++------- drivers/ram/octeon/Kconfig | 6 +++--- drivers/ram/stm32mp1/Kconfig | 36 ++++++++++++++++---------------- drivers/reboot-mode/Kconfig | 18 ++++++++-------- drivers/rtc/Kconfig | 4 ++-- drivers/serial/Kconfig | 16 +++++++-------- drivers/smem/Kconfig | 30 +++++++++++++-------------- drivers/soc/ti/Kconfig | 4 ++-- drivers/spi/Kconfig | 28 ++++++++++++------------- drivers/spmi/Kconfig | 8 ++++---- drivers/thermal/Kconfig | 24 +++++++++++----------- drivers/ufs/Kconfig | 4 ++-- drivers/watchdog/Kconfig | 8 ++++---- 34 files changed, 208 insertions(+), 208 deletions(-) (limited to 'drivers') diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index 2b45f9e5eba..d5ef0795401 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -5,7 +5,7 @@ config ADC This enables ADC API for drivers, which allows driving ADC features by single and multi-channel methods for: - start/stop/get data for conversion of a single-channel selected by - a number or multi-channels selected by a bitmask + a number or multi-channels selected by a bitmask - get data mask (ADC resolution) ADC reference Voltage supply options: - methods for get Vdd/Vss reference Voltage values with polarity diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index adf338ab00c..d44cf4bcb6b 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -68,10 +68,10 @@ config BLKMAP bool "Composable virtual block devices (blkmap)" depends on BLK help - Create virtual block devices that are backed by various sources, - e.g. RAM, or parts of an existing block device. Though much more - rudimentary, it borrows a lot of ideas from Linux's device mapper - subsystem. + Create virtual block devices that are backed by various sources, + e.g. RAM, or parts of an existing block device. Though much more + rudimentary, it borrows a lot of ideas from Linux's device mapper + subsystem. Example use-cases: - Treat a region of RAM as a block device, i.e. a RAM disk. This let's diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 4c0c8d89bb4..af6bd2f1a7d 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -68,7 +68,7 @@ config BOOTCOUNT_ENV saveenv on all reboots, the environment variable "upgrade_available" is used. If "upgrade_available" is 0, "bootcount" is always 0. If "upgrade_available" is 1, - "bootcount" is incremented in the environment. + "bootcount" is incremented in the environment. So the Userspace Application must set the "upgrade_available" and "bootcount" variables to 0, if the system booted successfully. @@ -83,7 +83,7 @@ config BOOTCOUNT_AT91 depends on AT91SAM9XE config DM_BOOTCOUNT - bool "Boot counter in a device-model device" + bool "Boot counter in a device-model device" help Enables reading/writing the bootcount in a device-model based backing store. If an entry in /chosen/u-boot,bootcount-device diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c2da7b3938b..addcece4da3 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -134,8 +134,8 @@ config CLK_CDCE9XX bool "Enable CDCD9XX clock driver" depends on CLK && ARCH_OMAP2PLUS help - Enable the clock synthesizer driver for CDCE913/925/937/949 - series of chips. + Enable the clock synthesizer driver for CDCE913/925/937/949 + series of chips. config CLK_ICS8N3QV01 bool "Enable ICS8N3QV01 VCXO driver" diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig index c6afef90034..5f3b8fe8ab4 100644 --- a/drivers/clk/owl/Kconfig +++ b/drivers/clk/owl/Kconfig @@ -1,8 +1,8 @@ config CLK_OWL - bool "Actions Semi OWL clock drivers" - depends on CLK && ARCH_OWL - help - Enable support for clock managemet unit present in Actions Semi + bool "Actions Semi OWL clock drivers" + depends on CLK && ARCH_OWL + help + Enable support for clock managemet unit present in Actions Semi Owl series S900/S700 SoCs. diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 72f99e9fa1b..1893b6c4181 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -61,11 +61,11 @@ config CLK_RCAR_GEN3 Enable this to support the clocks on Renesas R-Car Gen3 and Gen4 SoCs. config CLK_R8A774A1 - bool "Renesas R8A774A1 clock driver" + bool "Renesas R8A774A1 clock driver" def_bool y if R8A774A1 - depends on CLK_RCAR_GEN3 - help - Enable this to support the clocks on Renesas R8A774A1 SoC. + depends on CLK_RCAR_GEN3 + help + Enable this to support the clocks on Renesas R8A774A1 SoC. config CLK_R8A774B1 bool "Renesas R8A774B1 clock driver" diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig index 401225b8528..a4710257f62 100644 --- a/drivers/crypto/aspeed/Kconfig +++ b/drivers/crypto/aspeed/Kconfig @@ -15,11 +15,11 @@ config ASPEED_ACRY bool "ASPEED RSA and ECC Engine" depends on ASPEED_AST2600 help - Select this option to enable a driver for using the RSA/ECC engine in - the ASPEED BMC SoCs. + Select this option to enable a driver for using the RSA/ECC engine in + the ASPEED BMC SoCs. - Enabling this allows the use of RSA/ECC operations in hardware without requiring the - software implementations. It also improves performance and saves code size. + Enabling this allows the use of RSA/ECC operations in hardware without requiring the + software implementations. It also improves performance and saves code size. config ASPEED_CPTRA_SHA bool "Caliptra SHA ACC for Aspeed AST27xx SoCs" diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index eb01c6cf700..1398b0033f0 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -27,27 +27,27 @@ config CAAM_64BIT config SYS_FSL_HAS_SEC bool help - Enable Freescale Secure Boot and Trusted Architecture + Enable Freescale Secure Boot and Trusted Architecture config SYS_FSL_SEC_COMPAT_2 bool help - Secure boot and trust architecture compatible version 2 + Secure boot and trust architecture compatible version 2 config SYS_FSL_SEC_COMPAT_4 bool help - Secure boot and trust architecture compatible version 4 + Secure boot and trust architecture compatible version 4 config SYS_FSL_SEC_COMPAT_5 bool help - Secure boot and trust architecture compatible version 5 + Secure boot and trust architecture compatible version 5 config SYS_FSL_SEC_COMPAT_6 bool help - Secure boot and trust architecture compatible version 6 + Secure boot and trust architecture compatible version 6 config SYS_FSL_SEC_BE bool "Big-endian access to Freescale Secure Boot" diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 7f8f3570dd8..b11fa79ca59 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -21,12 +21,12 @@ if SYS_FSL_DDR || SYS_FSL_MMDC config SYS_FSL_DDR_BE bool help - Access DDR registers in big-endian + Access DDR registers in big-endian config SYS_FSL_DDR_LE bool help - Access DDR registers in little-endian + Access DDR registers in little-endian config FSL_DDR_BIST bool diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index d904982c800..8c9b377e8a3 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -3,14 +3,14 @@ if ARCH_K3 config TI_K3_NAVSS_UDMA - bool "Texas Instruments UDMA" - depends on ARCH_K3 - select DEVRES - select DMA - select TI_K3_NAVSS_RINGACC - select TI_K3_PSIL - help - Support for UDMA used in K3 devices. + bool "Texas Instruments UDMA" + depends on ARCH_K3 + select DEVRES + select DMA + select TI_K3_NAVSS_RINGACC + select TI_K3_PSIL + help + Support for UDMA used in K3 devices. endif config TI_K3_PSIL diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index bcd81c510f8..75b35fbc5be 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -294,9 +294,9 @@ config MAX7320_GPIO bool "MAX7320 I2C GPIO Expander driver" depends on DM_GPIO && DM_I2C help - Support for MAX7320 I2C 8/16-bit GPIO expander. - original maxim device has 8 push/pull outputs, - some clones offers 16bit. + Support for MAX7320 I2C 8/16-bit GPIO expander. + original maxim device has 8 push/pull outputs, + some clones offers 16bit. config MAX77663_GPIO bool "MAX77663 GPIO cell of PMIC driver" @@ -313,23 +313,23 @@ config MCP230XX_GPIO help Support for Microchip's MCP230XX I2C and SPI connected GPIO devices. The following chips are supported: - - MCP23008 - - MCP23017 - - MCP23018 - - MCP23S08 - - MCP23S17 - - MCP23S18 + - MCP23008 + - MCP23017 + - MCP23018 + - MCP23S08 + - MCP23S17 + - MCP23S18 config MSCC_SGPIO bool "Microsemi Serial GPIO driver" depends on DM_GPIO && SOC_VCOREIII help Support for the VCoreIII SoC serial GPIO device. By using a - serial interface, the SIO controller significantly extends - the number of available GPIOs with a minimum number of - additional pins on the device. The primary purpose of the - SIO controller is to connect control signals from SFP - modules and to act as an LED controller. + serial interface, the SIO controller significantly extends + the number of available GPIOs with a minimum number of + additional pins on the device. The primary purpose of the + SIO controller is to connect control signals from SFP + modules and to act as an LED controller. config MSM_GPIO bool "Qualcomm GPIO driver" @@ -404,8 +404,8 @@ config PCF8575_GPIO bool "PCF8575 I2C GPIO Expander driver" depends on DM_GPIO && DM_I2C help - Support for PCF8575 I2C 16-bit GPIO expander. Most of these - chips are from NXP and TI. + Support for PCF8575 I2C 16-bit GPIO expander. Most of these + chips are from NXP and TI. config RCAR_GPIO bool "Renesas R-Car GPIO driver" @@ -459,9 +459,9 @@ config SUNXI_GPIO config SUNXI_NEW_PINCTRL bool depends on SUNXI_GPIO - ---help--- - The Allwinner D1 and other new SoCs use a different register map - for the GPIO block, which we need to know about in the SPL. + help + The Allwinner D1 and other new SoCs use a different register map + for the GPIO block, which we need to know about in the SPL. config XILINX_GPIO bool "Xilinx GPIO driver" @@ -728,15 +728,15 @@ config SLG7XL45106_I2C_GPO bool "slg7xl45106 i2c gpo expander" depends on DM_GPIO && ARCH_ZYNQMP help - Support for slg7xl45106 i2c gpo expander. It is an i2c based - 8-bit gpo expander, all gpo lines are controlled by writing - value into data register. + Support for slg7xl45106 i2c gpo expander. It is an i2c based + 8-bit gpo expander, all gpo lines are controlled by writing + value into data register. config GPIO_SCMI bool "SCMI GPIO pinctrl driver" depends on DM_GPIO && PINCTRL_SCMI help - Support pinctrl GPIO over the SCMI interface. + Support pinctrl GPIO over the SCMI interface. config ADP5585_GPIO bool "ADP5585 GPIO driver" @@ -761,6 +761,6 @@ config MPFS_GPIO bool "Enable Polarfire SoC GPIO driver" depends on DM_GPIO help - Enable to support the GPIO driver on Polarfire SoC + Enable to support the GPIO driver on Polarfire SoC endif diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index de95a1debdc..04ebc24e8cf 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -133,7 +133,7 @@ config LED_GPIO config SPL_LED_GPIO bool "LED support for GPIO-connected LEDs in SPL" - depends on SPL_LED && SPL_DM_GPIO + depends on SPL_LED && SPL_DM_GPIO help This option is an SPL-variant of the LED_GPIO option. See the help of LED_GPIO for details. diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 591d9d9c656..82d0fa80396 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -44,15 +44,15 @@ config STM32_OMM This driver manages the muxing between the 2 OSPI busses and the 2 output ports. There are 4 possible muxing configurations: - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 - output is on port 2 + output is on port 2 - OSPI1 and OSPI2 are multiplexed over the same output port 1 - swapped mode (no multiplexing), OSPI1 output is on port 2, - OSPI2 output is on port 1 + OSPI2 output is on port 1 - OSPI1 and OSPI2 are multiplexed over the same output port 2 It also manages : - - the split of the memory area shared between the 2 OSPI instances. - - chip select selection override. - - the time between 2 transactions in multiplexed mode. + - the split of the memory area shared between the 2 OSPI instances. + - chip select selection override. + - the time between 2 transactions in multiplexed mode. config TI_AEMIF tristate "Texas Instruments AEMIF driver" @@ -71,9 +71,9 @@ config TI_GPMC depends on MEMORY && CLK && OF_CONTROL help This driver is for the General Purpose Memory Controller (GPMC) - present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows - interfacing to a variety of asynchronous as well as synchronous - memory drives like NOR, NAND, OneNAND, SRAM. + present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows + interfacing to a variety of asynchronous as well as synchronous + memory drives like NOR, NAND, OneNAND, SRAM. if TI_GPMC config TI_GPMC_DEBUG diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index ae53b02f27c..79f4db9849c 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1,4 +1,4 @@ config MFD_ATMEL_SMC - bool "Atmel Static Memory Controller driver" - help - Say yes here to support Atmel Static Memory Controller driver. + bool "Atmel Static Memory Controller driver" + help + Say yes here to support Atmel Static Memory Controller driver. diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 0b52515c700..bde5c640de8 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -71,9 +71,9 @@ config ATSHA204A select BITREVERSE depends on MISC help - Enable support for I2C connected Atmel's ATSHA204A - CryptoAuthentication module found for example on the Turris Omnia - board. + Enable support for I2C connected Atmel's ATSHA204A + CryptoAuthentication module found for example on the Turris Omnia + board. config GATEWORKS_SC bool "Gateworks System Controller Support" @@ -94,7 +94,7 @@ config QCOM_GENI etc. config ROCKCHIP_EFUSE - bool "Rockchip e-fuse support" + bool "Rockchip e-fuse support" depends on MISC help Enable (read-only) access for the e-fuse block found in Rockchip diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 0996d9fc30d..131be3106a1 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -332,7 +332,7 @@ config MMC_MESON_GX bool "Meson GX EMMC controller support" depends on ARCH_MESON help - Support for EMMC host controller on Meson GX ARM SoCs platform (S905) + Support for EMMC host controller on Meson GX ARM SoCs platform (S905) config MMC_OWL bool "Actions OWL Multimedia Card Interface support" @@ -659,8 +659,8 @@ config MMC_SDHCI_MSM depends on MMC_SDHCI && ARCH_SNAPDRAGON help Enables support for SDHCI 2.0 controller present on some Qualcomm - Snapdragon devices. This device is compatible with eMMC v4.5 and - SD 3.0 specifications. Both SD and eMMC devices are supported. + Snapdragon devices. This device is compatible with eMMC v4.5 and + SD 3.0 specifications. Both SD and eMMC devices are supported. Card-detect gpios are not supported. config MMC_SDHCI_MV @@ -852,7 +852,7 @@ config FTSDC010_SDIO bool "Support ftsdc010 sdio" depends on FTSDC010 help - This can enable ftsdc010 sdio function. + This can enable ftsdc010 sdio function. config MMC_MTK bool "MediaTek SD/MMC Card Interface support" diff --git a/drivers/mux/Kconfig b/drivers/mux/Kconfig index de74e5d5e4e..383dac532c1 100644 --- a/drivers/mux/Kconfig +++ b/drivers/mux/Kconfig @@ -5,17 +5,17 @@ config MULTIPLEXER depends on DM select DEVRES help - The mux framework is a minimalistic subsystem that handles multiplexer - controllers. It provides the same API as Linux and mux drivers should - be portable with a minimum effort. + The mux framework is a minimalistic subsystem that handles multiplexer + controllers. It provides the same API as Linux and mux drivers should + be portable with a minimum effort. if MULTIPLEXER config SPL_MUX_MMIO bool "MMIO register bitfield-controlled Multiplexer" - depends on MULTIPLEXER && SYSCON - help - MMIO register bitfield-controlled Multiplexer controller. + depends on MULTIPLEXER && SYSCON + help + MMIO register bitfield-controlled Multiplexer controller. The driver builds multiplexer controllers for bitfields in a syscon register. For N bit wide bitfields, there will be 2^N possible diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 39df0e776df..9ffccc3a80b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -101,11 +101,11 @@ config PCI_ENHANCED_ALLOCATION devices in place of traditional BARS for allocation of resources. config PCI_ARID - bool "Enable Alternate Routing-ID support for PCI" - help - Say Y here if you want to enable Alternate Routing-ID capability - support on PCI devices. This helps to skip some devices in BDF - scan that are not present. + bool "Enable Alternate Routing-ID support for PCI" + help + Say Y here if you want to enable Alternate Routing-ID capability + support on PCI devices. This helps to skip some devices in BDF + scan that are not present. config PCI_SCAN_SHOW bool "Show PCI devices during startup" @@ -287,7 +287,7 @@ config PCI_IOMMU_EXTRA_MAPPINGS the node describing the PCI controller. The intent is to cover SR-IOV scenarios which need mappings for VFs and PCI hot-plug scenarios. More documentation can be found under: - arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra + arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra config PCIE_LAYERSCAPE_EP bool "Layerscape PCIe Endpoint mode support" @@ -440,8 +440,8 @@ config PCIE_XILINX_NWL bool "Xilinx NWL PCIe controller" depends on ARCH_ZYNQMP help - Say 'Y' here if you want support for Xilinx / AMD NWL PCIe - controller as Root Port. + Say 'Y' here if you want support for Xilinx / AMD NWL PCIe + controller as Root Port. config PCIE_PLDA_COMMON bool diff --git a/drivers/pci_endpoint/Kconfig b/drivers/pci_endpoint/Kconfig index 9900481daa6..d1db4951a0c 100644 --- a/drivers/pci_endpoint/Kconfig +++ b/drivers/pci_endpoint/Kconfig @@ -9,10 +9,10 @@ config PCI_ENDPOINT bool "PCI Endpoint Support" depends on DM help - Enable this configuration option to support configurable PCI - endpoints. This should be enabled if the platform has a PCI - controllers that can operate in endpoint mode (as a device - connected to PCI host or bridge). + Enable this configuration option to support configurable PCI + endpoints. This should be enabled if the platform has a PCI + controllers that can operate in endpoint mode (as a device + connected to PCI host or bridge). config PCIE_CADENCE_EP bool "Cadence PCIe endpoint controller" diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index eafa82fe494..89d84df96ae 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -72,14 +72,14 @@ config AB8500_USB_PHY Support for the USB OTG PHY in ST-Ericsson AB8500. config APPLE_ATCPHY - bool "Apple Type-C PHY Driver" - depends on PHY && ARCH_APPLE - default y - help - Support for the Apple Type-C PHY. + bool "Apple Type-C PHY Driver" + depends on PHY && ARCH_APPLE + default y + help + Support for the Apple Type-C PHY. - This is a dummy driver since the PHY is initialized - sufficiently by previous stage firmware. + This is a dummy driver since the PHY is initialized + sufficiently by previous stage firmware. config BCM6318_USBH_PHY bool "BCM6318 USBH PHY support" @@ -249,14 +249,14 @@ config MT7620_USB_PHY depends on PHY depends on SOC_MT7620 help - Support the intergated USB PHY in MediaTek MT7620 SoC + Support the intergated USB PHY in MediaTek MT7620 SoC config MT76X8_USB_PHY bool "MediaTek MT76x8 (7628/88) USB PHY support" depends on PHY depends on SOC_MT7628 help - Support the USB PHY in MT76x8 SoCs + Support the USB PHY in MT76x8 SoCs This PHY is found on MT76x8 devices supporting USB. diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index 7094903d869..1fdadaccb12 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -2,7 +2,7 @@ config MSM8916_USB_PHY bool select PHY help - Support the Qualcomm MSM8916 USB PHY + Support the Qualcomm MSM8916 USB PHY This PHY is found on qualcomm dragonboard410c development board. diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig index e4918460de6..023444b700c 100644 --- a/drivers/ram/aspeed/Kconfig +++ b/drivers/ram/aspeed/Kconfig @@ -4,19 +4,19 @@ menuconfig ASPEED_RAM depends on ARCH_ASPEED || TARGET_ASPEED_AST2700_IBEX default ARCH_ASPEED help - Configuration options for DDR SDRAM on ASPEED systems. + Configuration options for DDR SDRAM on ASPEED systems. - RAM initialisation is always built in for the platform. This menu - allows customisation of the configuration used. + RAM initialisation is always built in for the platform. This menu + allows customisation of the configuration used. config ASPEED_DDR4_DUALX8 bool "Enable Dual X8 DDR4 die" depends on ASPEED_RAM help - Say Y if dual X8 DDR4 die is used on the board. The ASPEED DDRM - SRAM controller needs to know if the memory chip mounted on the - board is dual x8 die or not, otherwise it may get the wrong - size of the memory space. + Say Y if dual X8 DDR4 die is used on the board. The ASPEED DDRM + SRAM controller needs to know if the memory chip mounted on the + board is dual x8 die or not, otherwise it may get the wrong + size of the memory space. config ASPEED_BYPASS_SELFTEST depends on ASPEED_RAM diff --git a/drivers/ram/octeon/Kconfig b/drivers/ram/octeon/Kconfig index f19957293f9..37bf4851400 100644 --- a/drivers/ram/octeon/Kconfig +++ b/drivers/ram/octeon/Kconfig @@ -2,14 +2,14 @@ config RAM_OCTEON bool "Ram drivers for Octeon SoCs" depends on RAM && ARCH_OCTEON help - This enables support for RAM drivers for Octeon SoCs. + This enables support for RAM drivers for Octeon SoCs. if RAM_OCTEON config RAM_OCTEON_DDR4 bool "Octeon III DDR4 RAM support" help - This enables support for DDR4 RAM suppoort for Octeon III. This does - not include support for Octeon CN70XX. + This enables support for DDR4 RAM suppoort for Octeon III. This does + not include support for Octeon CN70XX. endif # RAM_OCTEON diff --git a/drivers/ram/stm32mp1/Kconfig b/drivers/ram/stm32mp1/Kconfig index 1aaf064c30c..76bd17a8874 100644 --- a/drivers/ram/stm32mp1/Kconfig +++ b/drivers/ram/stm32mp1/Kconfig @@ -6,43 +6,43 @@ config STM32MP1_DDR select SPL_RAM if SPL default y help - activate STM32MP1 DDR controller driver for STM32MP1 soc - family: support for LPDDR2, LPDDR3 and DDR3 - the SDRAM parameters for controleur and phy need to be provided - in device tree (computed by DDR tuning tools) + activate STM32MP1 DDR controller driver for STM32MP1 soc + family: support for LPDDR2, LPDDR3 and DDR3 + the SDRAM parameters for controleur and phy need to be provided + in device tree (computed by DDR tuning tools) config STM32MP1_DDR_INTERACTIVE bool "STM32MP1 DDR driver : interactive support" depends on STM32MP1_DDR help - activate interactive support in STM32MP1 DDR controller driver - used for DDR tuning tools - to enter in intercative mode type 'd' during SPL DDR driver - initialisation + activate interactive support in STM32MP1 DDR controller driver + used for DDR tuning tools + to enter in intercative mode type 'd' during SPL DDR driver + initialisation config STM32MP1_DDR_INTERACTIVE_FORCE bool "STM32MP1 DDR driver : force interactive mode" depends on STM32MP1_DDR_INTERACTIVE help - force interactive mode in STM32MP1 DDR controller driver - skip the polling of character 'd' in console - useful when SPL is loaded in sysram - directly by programmer + force interactive mode in STM32MP1 DDR controller driver + skip the polling of character 'd' in console + useful when SPL is loaded in sysram + directly by programmer config STM32MP1_DDR_TESTS bool "STM32MP1 DDR driver : tests support" depends on STM32MP1_DDR_INTERACTIVE default y help - activate test support for interactive support in - STM32MP1 DDR controller driver: command test + activate test support for interactive support in + STM32MP1 DDR controller driver: command test config STM32MP1_DDR_TUNING bool "STM32MP1 DDR driver : support of tuning" depends on STM32MP1_DDR_INTERACTIVE default y help - activate tuning command in STM32MP1 DDR interactive mode - used for DDR tuning tools - - DQ Deskew algorithm - - DQS Trimming + activate tuning command in STM32MP1 DDR interactive mode + used for DDR tuning tools + - DQ Deskew algorithm + - DQS Trimming diff --git a/drivers/reboot-mode/Kconfig b/drivers/reboot-mode/Kconfig index 72b33d71223..3fdb4218a8b 100644 --- a/drivers/reboot-mode/Kconfig +++ b/drivers/reboot-mode/Kconfig @@ -11,26 +11,26 @@ config DM_REBOOT_MODE depends on DM select DEVRES help - Enable support for reboot mode control. This will allow users to - adjust the boot process based on reboot mode parameter - passed to U-Boot. + Enable support for reboot mode control. This will allow users to + adjust the boot process based on reboot mode parameter + passed to U-Boot. config DM_REBOOT_MODE_GPIO bool "Use GPIOs as reboot mode backend" depends on DM_REBOOT_MODE help - Use GPIOs to control the reboot mode. This will allow users to boot - a device in a specific mode by using a GPIO that can be controlled - outside U-Boot. + Use GPIOs to control the reboot mode. This will allow users to boot + a device in a specific mode by using a GPIO that can be controlled + outside U-Boot. config DM_REBOOT_MODE_RTC bool "Use RTC as reboot mode backend" depends on DM_RTC depends on DM_REBOOT_MODE help - Use RTC non volatile memory to control the reboot mode. This will allow users to boot - a device in a specific mode by using a register(s) that can be controlled - outside U-Boot (e.g. Kernel). + Use RTC non volatile memory to control the reboot mode. This will allow users to boot + a device in a specific mode by using a register(s) that can be controlled + outside U-Boot (e.g. Kernel). config REBOOT_MODE_NVMEM bool "Use NVMEM reboot mode" diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 3b74770b18a..6fb3019a644 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -44,8 +44,8 @@ config VPL_DM_RTC config RTC_ENABLE_32KHZ_OUTPUT bool "Enable RTC 32Khz output" help - Some real-time clocks support the output of 32kHz square waves (such as ds3231), - the config symbol choose Real Time Clock device 32Khz output feature. + Some real-time clocks support the output of 32kHz square waves (such as ds3231), + the config symbol choose Real Time Clock device 32Khz output feature. config RTC_ARMADA38X bool "Enable Armada 38x Marvell SoC RTC" diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index c6e457572b1..e221800d5d0 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -759,11 +759,11 @@ config MVEBU_A3700_UART config MCFUART bool "Freescale ColdFire UART support" depends on M68K - help - Choose this option to add support for UART driver on the ColdFire - SoC's family. The serial communication channel provides a full-duplex - asynchronous/synchronous receiver and transmitter deriving an - operating frequency from the internal bus clock or an external clock. + help + Choose this option to add support for UART driver on the ColdFire + SoC's family. The serial communication channel provides a full-duplex + asynchronous/synchronous receiver and transmitter deriving an + operating frequency from the internal bus clock or an external clock. config MXC_UART bool "IMX serial port support" @@ -1027,9 +1027,9 @@ config OCTEON_SERIAL_BOOTCMD select SYS_CONSOLE_IS_IN_ENV select CONSOLE_MUX help - This driver supports remote input over the PCIe bus from a host - to U-Boot for entering commands. It is utilized by the host - commands 'oct-remote-load' and 'oct-remote-bootcmd'. + This driver supports remote input over the PCIe bus from a host + to U-Boot for entering commands. It is utilized by the host + commands 'oct-remote-load' and 'oct-remote-bootcmd'. config OCTEON_SERIAL_PCIE_CONSOLE bool "MIPS Octeon PCIe remote console" diff --git a/drivers/smem/Kconfig b/drivers/smem/Kconfig index e5d7dcc81b1..5b68ad5f10f 100644 --- a/drivers/smem/Kconfig +++ b/drivers/smem/Kconfig @@ -4,22 +4,22 @@ menuconfig SMEM if SMEM config SANDBOX_SMEM - bool "Sandbox Shared Memory Manager (SMEM)" - depends on SANDBOX && DM - help - enable SMEM support for sandbox. This is an emulation of a real SMEM - manager. - The sandbox driver allocates a shared memory from the heap and - initialzies it on start. + bool "Sandbox Shared Memory Manager (SMEM)" + depends on SANDBOX && DM + help + enable SMEM support for sandbox. This is an emulation of a real SMEM + manager. + The sandbox driver allocates a shared memory from the heap and + initialzies it on start. config MSM_SMEM - bool "Qualcomm Shared Memory Manager (SMEM)" - depends on DM - depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX - select DEVRES - help - Enable support for the Qualcomm Shared Memory Manager. - The driver provides an interface to items in a heap shared among all - processors in a Qualcomm platform. + bool "Qualcomm Shared Memory Manager (SMEM)" + depends on DM + depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX + select DEVRES + help + Enable support for the Qualcomm Shared Memory Manager. + The driver provides an interface to items in a heap shared among all + processors in a Qualcomm platform. endif # menu "SMEM Support" diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 36129cb72f6..9734bf32cb0 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -21,8 +21,8 @@ config TI_KEYSTONE_SERDES bool "Keystone SerDes driver for ethernet" depends on ARCH_KEYSTONE help - SerDes driver for Keystone SoC used for ethernet support on TI - K2 platforms. + SerDes driver for Keystone SoC used for ethernet support on TI + K2 platforms. config TI_PRUSS bool "Support for TI's K3 based Pruss driver" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index cfbedd64c4c..009dd997efb 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -2,10 +2,10 @@ menuconfig SPI bool "SPI Support" help The "Serial Peripheral Interface" is a low level synchronous - protocol. Chips that support SPI can have data transfer rates - up to several tens of Mbit/sec. Chips are addressed with a - controller and a chipselect. Most SPI slaves don't support - dynamic device discovery; some are even write-only or read-only. + protocol. Chips that support SPI can have data transfer rates + up to several tens of Mbit/sec. Chips are addressed with a + controller and a chipselect. Most SPI slaves don't support + dynamic device discovery; some are even write-only or read-only. SPI is widely used by microcontrollers to talk with sensors, eeprom and flash memory, codecs and various other controller @@ -200,11 +200,11 @@ config CADENCE_XSPI by using the Auto Command work mode. config CF_SPI - bool "ColdFire SPI driver" - depends on M68K - help - Enable the ColdFire SPI driver. This driver can be used on - some m68k SoCs. + bool "ColdFire SPI driver" + depends on M68K + help + Enable the ColdFire SPI driver. This driver can be used on + some m68k SoCs. config CV1800B_SPIF bool "Sophgo cv1800b SPI Flash Controller driver" @@ -352,7 +352,7 @@ config MTK_SNOR select DEVRES help Enable the Mediatek SPINOR controller driver. This driver has - better read/write performance with NOR. + better read/write performance with NOR. config MTK_SNFI_SPI bool "Mediatek SPI memory controller driver" @@ -544,8 +544,8 @@ config SPI_SIFIVE config SOFT_SPI bool "Soft SPI driver" help - Enable Soft SPI driver. This driver is to use GPIO simulate - the SPI protocol. + Enable Soft SPI driver. This driver is to use GPIO simulate + the SPI protocol. config SPI_SN_F_OSPI tristate "Socionext F_OSPI SPI flash controller" @@ -673,8 +673,8 @@ config ZYNQMP_GQSPI config SPI_STACKED_PARALLEL bool "Enable support for stacked or parallel memories" help - Enable support for stacked/or parallel memories. This functionality - may appear on Xilinx hardware. By default this is disabled. + Enable support for stacked/or parallel memories. This functionality + may appear on Xilinx hardware. By default this is disabled. endif # if DM_SPI diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig index ab4878ebae4..e28fd9af1d0 100644 --- a/drivers/spmi/Kconfig +++ b/drivers/spmi/Kconfig @@ -3,7 +3,7 @@ menu "SPMI support" config SPMI bool "Enable SPMI bus support" depends on DM - ---help--- + help Select this to enable to support SPMI bus. SPMI (System Power Management Interface) bus is used to connect PMIC devices on various SoCs. @@ -11,13 +11,13 @@ config SPMI config SPMI_MSM bool "Support Qualcomm SPMI bus" depends on SPMI - ---help--- + help Support SPMI bus implementation found on Qualcomm Snapdragon SoCs. config SPMI_SANDBOX bool "Support for Sandbox SPMI bus" depends on SPMI - ---help--- + help Demo SPMI bus implementation. Emulates part of PM8916 as single - slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3. + slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3. endmenu diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 0015dec1062..9ad0d699850 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -13,9 +13,9 @@ config IMX_THERMAL depends on MX6 || MX7 help Support for Temperature Monitor (TEMPMON) found on Freescale i.MX SoCs. - It supports one critical trip point and one passive trip point. The - cpufreq is used as the cooling device to throttle CPUs when the - passive trip is crossed. + It supports one critical trip point and one passive trip point. The + cpufreq is used as the cooling device to throttle CPUs when the + passive trip is crossed. config IMX_SCU_THERMAL bool "Temperature sensor driver for NXP i.MX8" @@ -29,7 +29,7 @@ config IMX_SCU_THERMAL config IMX_TMU bool "Thermal Management Unit driver for NXP i.MX8M / i.MX93 and QorIQ" depends on ARCH_IMX8M || IMX93 || FSL_LAYERSCAPE - help + help Support for the NXP Thermal Management Unit (TMU) sensors on i.MX8M, i.MX93 and on QorIQ/Layerscape SoCs (LX2160A, LS1028A, LS1088A, ...). @@ -45,16 +45,16 @@ config RCAR_GEN3_THERMAL driver into the U-Boot thermal framework. config TI_DRA7_THERMAL - bool "Temperature sensor driver for TI dra7xx SOCs" - help - Enable thermal support for the Texas Instruments DRA752 SoC family. - The driver supports reading CPU temperature. + bool "Temperature sensor driver for TI dra7xx SOCs" + help + Enable thermal support for the Texas Instruments DRA752 SoC family. + The driver supports reading CPU temperature. config TI_LM74_THERMAL - bool "Temperature sensor driver for TI LM74 chip" - help - Enable thermal support for the Texas Instruments LM74 chip. - The driver supports reading CPU temperature. + bool "Temperature sensor driver for TI LM74 chip" + help + Enable thermal support for the Texas Instruments LM74 chip. + The driver supports reading CPU temperature. config DM_THERMAL_JC42 bool "JEDEC JC-42.4/TSE2004av SPD temperature sensor" diff --git a/drivers/ufs/Kconfig b/drivers/ufs/Kconfig index 49472933de3..0b5df54e8fb 100644 --- a/drivers/ufs/Kconfig +++ b/drivers/ufs/Kconfig @@ -19,7 +19,7 @@ config UFS_AMD_VERSAL2 config UFS_CADENCE bool "Cadence platform driver for UFS" depends on UFS - help + help This selects the platform driver for the Cadence UFS host controller present on present TI's J721e devices. @@ -51,7 +51,7 @@ config UFS_PCI config UFS_QCOM bool "Qualcomm Host Controller driver for UFS" depends on UFS && ARCH_SNAPDRAGON - help + help This selects the platform driver for the UFS host controller present on Qualcomm Snapdragon SoCs. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0e6e6830fc8..b91727e1265 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -384,10 +384,10 @@ config WDT_SBSA bool "SBSA watchdog timer support" depends on WDT help - Select this to enable SBSA watchdog timer. - This driver can operate ARM SBSA Generic Watchdog as a single stage. - In the single stage mode, when the timeout is reached, your system - will be reset by WS1. The first signal (WS0) is ignored. + Select this to enable SBSA watchdog timer. + This driver can operate ARM SBSA Generic Watchdog as a single stage. + In the single stage mode, when the timeout is reached, your system + will be reset by WS1. The first signal (WS0) is ignored. config WDT_SIEMENS_PMIC bool "Enable PMIC Watchdog Timer support for Siemens platforms" -- cgit v1.3.1 From eec819b98439c50f8ea38ac078ff6a862ea03038 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 22 May 2026 15:27:05 +0800 Subject: usb: f_sdp: handle the spl load function failure Current implementation does not check the return value of spl load function. If the spl load is failed, SPL may meet crash due to spl_image variable is not initialized. Add the failure check, so SPL can print and stop with error. Signed-off-by: Ye Li Fixes: 2c72ead73874 ("usb: gadget: f_sdp: Allow SPL to load and boot FIT via SDP") Reviewed-by: Mattijs Korpershoek Link: https://patch.msgid.link/20260522072705.1156220-1-ye.li@nxp.com Signed-off-by: Mattijs Korpershoek --- drivers/usb/gadget/f_sdp.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index f72e27028b7..cd2c282247a 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -75,6 +75,7 @@ struct hid_report { #define SDP_HID_PACKET_SIZE_EP1 1024 #define SDP_EXIT 1 +#define SDP_FAIL 2 struct sdp_command { u16 cmd; @@ -840,11 +841,14 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_LOAD_FIT if (image_get_magic(header) == FDT_MAGIC) { struct spl_load_info load; + int ret; debug("Found FIT\n"); spl_load_init(&load, sdp_load_read, header, 1); - spl_load_simple_fit(spl_image, &load, 0, - header); + ret = spl_load_simple_fit(spl_image, &load, 0, + header); + if (ret) + return SDP_FAIL; return SDP_EXIT; } @@ -852,9 +856,13 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && valid_container_hdr((void *)header)) { struct spl_load_info load; + int ret; spl_load_init(&load, sdp_load_read, header, 1); - spl_load_imx_container(spl_image, &load, 0); + ret = spl_load_imx_container(spl_image, &load, 0); + if (ret) + return SDP_FAIL; + return SDP_EXIT; } @@ -924,6 +932,8 @@ int spl_sdp_handle(struct udevice *udc, struct spl_image_info *spl_image, if (flag == SDP_EXIT) return 0; + else if (flag == SDP_FAIL) + return -EIO; schedule(); dm_usb_gadget_handle_interrupts(udc); -- cgit v1.3.1 From 1c758ce38caa783c85129753c1ecc9d14a203d8e Mon Sep 17 00:00:00 2001 From: Mattijs Korpershoek Date: Wed, 17 Jun 2026 13:14:48 +0200 Subject: usb: gadget: f_mass_storage: Disable eps during disconnect When trying two ums commands in a row, the second one no longer enumerates properly from the host. This happens since commit 59310d1ecb9f ("usb: gadget: introduce 'enabled' flag in struct usb_ep") causing usb_ep_enable() to return early when ep->enabled is already set. Gadget function drivers (such as f_fastboot or f_mass_storage) implement a disable() function which is called whenever we are done using the gadget. Because f_mass_storage driver does not disable the endpoints, ep->enabled will never be set to false again. This can be reproduced on the STM32MP157C-DK2 or the Khadas VIM3 boards. Add calls to usb_ep_disable() as done in linux [1] to fix this. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9fff139aeb11186fd8e75860c959c86cb43ab2f6 Fixes: 59310d1ecb9f ("usb: gadget: introduce 'enabled' flag in struct usb_ep") Reported-by: Patrice Chotard Reviewed-by: Patrice Chotard Link: https://patch.msgid.link/20260617-ums-disconnect-v2-1-6e52d9de1d36@kernel.org Signed-off-by: Mattijs Korpershoek --- drivers/usb/gadget/f_mass_storage.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index 71dc58da3f0..87ed25e8bb3 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -2275,6 +2275,17 @@ static int fsg_set_alt(struct usb_function *f, unsigned intf, unsigned alt) static void fsg_disable(struct usb_function *f) { struct fsg_dev *fsg = fsg_from_func(f); + + /* Disable the endpoints */ + if (fsg->bulk_in_enabled) { + usb_ep_disable(fsg->bulk_in); + fsg->bulk_in_enabled = 0; + } + if (fsg->bulk_out_enabled) { + usb_ep_disable(fsg->bulk_out); + fsg->bulk_out_enabled = 0; + } + fsg->common->new_fsg = NULL; raise_exception(fsg->common, FSG_STATE_CONFIG_CHANGE); } -- cgit v1.3.1 From b4610c7177c5ea978837693be7b18779414e6212 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 9 Jun 2026 16:36:25 +0800 Subject: serial: lpuart: Use livetree API for fdt access Use livetree API, otherwise driver will fail to read properties from the device tree when OF_LIVE is enabled. Signed-off-by: Peng Fan --- drivers/serial/serial_lpuart.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 3f5fadfc80a..955f1c96407 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -519,8 +519,7 @@ static int lpuart_serial_probe(struct udevice *dev) static int lpuart_serial_of_to_plat(struct udevice *dev) { struct lpuart_serial_plat *plat = dev_get_plat(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); + ofnode node = dev_ofnode(dev); fdt_addr_t addr; addr = dev_read_addr(dev); @@ -530,18 +529,18 @@ static int lpuart_serial_of_to_plat(struct udevice *dev) plat->reg = (void *)addr; plat->flags = dev_get_driver_data(dev); - if (fdtdec_get_bool(blob, node, "little-endian")) + if (ofnode_read_bool(node, "little-endian")) plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG; - if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart")) + if (ofnode_device_is_compatible(node, "fsl,ls1021a-lpuart")) plat->devtype = DEV_LS1021A; - else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imx7ulp-lpuart")) plat->devtype = DEV_MX7ULP; - else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,vf610-lpuart")) plat->devtype = DEV_VF610; - else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imx8qm-lpuart")) plat->devtype = DEV_IMX8; - else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imxrt-lpuart")) plat->devtype = DEV_IMXRT; return 0; -- cgit v1.3.1 From 8db4311b4b2b918005cf2d2e67e58d31f44507cc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 9 Jun 2026 16:36:26 +0800 Subject: gpio: imx_rgpio2p: Use dev_read_addr_index Use dev_read_addr_index which supports livetree API, otherwise driver will fail to get addr when OF_LIVE is enabled. Signed-off-by: Peng Fan --- drivers/gpio/imx_rgpio2p.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c index 7cf178f8a48..ba3c5fcf25b 100644 --- a/drivers/gpio/imx_rgpio2p.c +++ b/drivers/gpio/imx_rgpio2p.c @@ -194,11 +194,11 @@ static int imx_rgpio2p_bind(struct udevice *dev) dual_base = true; if (dual_base) { - addr = devfdt_get_addr_index(dev, 1); + addr = dev_read_addr_index(dev, 1); if (addr == FDT_ADDR_T_NONE) return -EINVAL; } else { - addr = devfdt_get_addr_index(dev, 0); + addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) return -EINVAL; -- cgit v1.3.1 From 170291f04267269c1cbe88628d03b29feec4d6c0 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 9 Jun 2026 16:36:27 +0800 Subject: misc: ele: Use dev_read_addr Use dev_read_addr which supports livetree API, otherwise driver will fail to get addr when OF_LIVE is enabled. Signed-off-by: Peng Fan --- drivers/misc/imx_ele/ele_mu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index cdb85b999db..65a4779c041 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -209,7 +209,7 @@ static int imx8ulp_mu_probe(struct udevice *dev) debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); - addr = devfdt_get_addr(dev); + addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; -- cgit v1.3.1 From 450d9eaf5e64663674f21efec82f2c1dc6cac6d5 Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:34 +0300 Subject: clk: imx6q: cosmetic: keep pll definitions together Make it easier to reason about by keeping similar clocks grouped together. While at it, fix comment spacing. Signed-off-by: Brian Ruley --- drivers/clk/imx/clk-imx6q.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index f57ac79f8ca..cd06d211e8d 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -126,18 +126,19 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_PLL3_USB_OTG, imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3)); + clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", + base + 0xa0, 0x7f)); + clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", + "osc", base + 0xe0, 0x3)); + clk_dm(IMX6QDL_CLK_PLL3_60M, imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); clk_dm(IMX6QDL_CLK_PLL3_80M, imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); clk_dm(IMX6QDL_CLK_PLL3_120M, imx_clk_fixed_factor(dev, "pll3_120m", "pll3_usb_otg", 1, 4)); - clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", - base + 0xa0, 0x7f)); clk_dm(IMX6QDL_CLK_PLL5_VIDEO, imx_clk_gate(dev, "pll5_video", "pll5", base + 0xa0, 13)); - clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", - "osc", base + 0xe0, 0x3)); clk_dm(IMX6QDL_CLK_PLL6_ENET, imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); @@ -279,9 +280,9 @@ static int imx6q_clk_probe(struct udevice *dev) ldb_di_sels, ARRAY_SIZE(ldb_di_sels))); } else { /* - * Need to set these as read-only due to a hardware bug. - * Keeping default mux values. Fixed on the i.MX6 QuadPlus - */ + * Need to set these as read-only due to a hardware bug. + * Keeping default mux values. Fixed on the i.MX6 QuadPlus + */ clk_dm(IMX6QDL_CLK_LDB_DI0_SEL, imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), -- cgit v1.3.1 From d6331d465d8ae6091a737d5df15ec3c76ee85c5f Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:35 +0300 Subject: clk: imx6q: guard video clocks behind config Do not touch the video clocks unless explicitly required by the configuration. This avoids the issue of the binary size increase on SPL builds that do not enable video. For those that do, they should increase the size limit to fit the new code and data. Signed-off-by: Brian Ruley --- drivers/clk/imx/clk-imx6q.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index cd06d211e8d..67c0261091d 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -72,6 +72,8 @@ static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; + +#if CONFIG_IS_ENABLED(VIDEO) static const char *const ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", @@ -112,6 +114,7 @@ static const char *ipu2_di1_sels_2[] = { }; static unsigned int share_count_mipi_core_cfg; +#endif /* CONFIG_IS_ENABLED(VIDEO) */ static int imx6q_clk_probe(struct udevice *dev) { @@ -264,6 +267,7 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22)); +#if CONFIG_IS_ENABLED(VIDEO) clk_dm(IMX6QDL_CLK_IPU1_SEL, imx_clk_mux(dev, "ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels))); @@ -414,6 +418,7 @@ static int imx6q_clk_probe(struct udevice *dev) ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT)); } +#endif /* CONFIG_IS_ENABLED(VIDEO) */ clk_dm(IMX6QDL_CLK_ECSPI1, imx_clk_gate2(dev, "ecspi1", "ecspi_root", base + 0x6c, 0)); @@ -454,6 +459,8 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1)); + +#if CONFIG_IS_ENABLED(VIDEO) clk_dm(IMX6QDL_CLK_MIPI_CORE_CFG, imx_clk_gate2_shared(dev, "mipi_core_cfg", "video_27m", base + 0x74, 16, @@ -481,6 +488,7 @@ static int imx6q_clk_probe(struct udevice *dev) SET_CLK_PARENT(IMX6QDL_CLK_IPU1_SEL, IMX6QDL_CLK_PLL3_PFD1_540M); } +#endif /* CONFIG_IS_ENABLED(VIDEO) */ return 0; } -- cgit v1.3.1 From 73394a3cdcea4e6670d7f34b79bbb54586a5b840 Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:36 +0300 Subject: clk: imx6q: add missing pll bypasses After reset, all PLLs are bypassed by default so unbypass them so that dependent clocks can function correctly. Signed-off-by: Brian Ruley --- drivers/clk/imx/clk-imx6q.c | 90 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 80 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 67c0261091d..9ee3109bf1d 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -46,6 +46,33 @@ static struct clk_ops imx6q_clk_ops = { .disable = ccf_clk_disable, }; +static const char *const pll_bypass_src_sels[] = { + "osc", + "lvds1_in", + "lvds2_in", + "dummy", +}; + +static const char *const pll2_bypass_sels[] = { + "pll2", + "pll2_bypass_src", +}; + +static const char *const pll3_bypass_sels[] = { + "pll3", + "pll3_bypass_src", +}; + +static const char *const pll5_bypass_sels[] = { + "pll5", + "pll5_bypass_src", +}; + +static const char *const pll6_bypass_sels[] = { + "pll6", + "pll6_bypass_src", +}; + static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", @@ -123,27 +150,70 @@ static int imx6q_clk_probe(struct udevice *dev) /* Anatop clocks */ base = (void *)ANATOP_BASE_ADDR; - clk_dm(IMX6QDL_CLK_PLL2, - imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc", - base + 0x30, 0x1)); - clk_dm(IMX6QDL_CLK_PLL3_USB_OTG, - imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", - base + 0x10, 0x3)); + clk_dm(IMX6QDL_PLL2_BYPASS_SRC, + imx_clk_mux(dev, "pll2_bypass_src", base + 0x30, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL3_BYPASS_SRC, + imx_clk_mux(dev, "pll3_bypass_src", base + 0x10, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL5_BYPASS_SRC, + imx_clk_mux(dev, "pll5_bypass_src", base + 0xa0, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL6_BYPASS_SRC, + imx_clk_mux(dev, "pll6_bypass_src", base + 0xe0, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + + clk_dm(IMX6QDL_CLK_PLL2, imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2", + "osc", base + 0x30, 0x1)); + clk_dm(IMX6QDL_CLK_PLL3, imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3", + "osc", base + 0x10, 0x3)); clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f)); clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3)); + clk_dm(IMX6QDL_PLL2_BYPASS, + imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1, + pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL3_BYPASS, + imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1, + pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL5_BYPASS, + imx_clk_mux_flags(dev, "pll5_bypass", base + 0xa0, 16, 1, + pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL6_BYPASS, + imx_clk_mux_flags(dev, "pll6_bypass", base + 0xe0, 16, 1, + pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), + CLK_SET_RATE_PARENT)); + + SET_CLK_PARENT(IMX6QDL_PLL2_BYPASS, IMX6QDL_CLK_PLL2); + SET_CLK_PARENT(IMX6QDL_PLL3_BYPASS, IMX6QDL_CLK_PLL3); + SET_CLK_PARENT(IMX6QDL_PLL5_BYPASS, IMX6QDL_CLK_PLL5); + SET_CLK_PARENT(IMX6QDL_PLL6_BYPASS, IMX6QDL_CLK_PLL6); + + clk_dm(IMX6QDL_CLK_PLL2_BUS, + imx_clk_gate(dev, "pll2_bus", "pll2_bypass", base + 0x30, 13)); + clk_dm(IMX6QDL_CLK_PLL3_USB_OTG, + imx_clk_gate(dev, "pll3_usb_otg", "pll3_bypass", base + 0x10, + 13)); + clk_dm(IMX6QDL_CLK_PLL5_VIDEO, + imx_clk_gate(dev, "pll5_video", "pll5_bypass", base + 0xa0, 13)); + clk_dm(IMX6QDL_CLK_PLL6_ENET, + imx_clk_gate(dev, "pll6_enet", "pll6_bypass", base + 0xe0, 13)); + clk_dm(IMX6QDL_CLK_PLL3_60M, imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); clk_dm(IMX6QDL_CLK_PLL3_80M, imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); clk_dm(IMX6QDL_CLK_PLL3_120M, imx_clk_fixed_factor(dev, "pll3_120m", "pll3_usb_otg", 1, 4)); - clk_dm(IMX6QDL_CLK_PLL5_VIDEO, - imx_clk_gate(dev, "pll5_video", "pll5", base + 0xa0, 13)); - clk_dm(IMX6QDL_CLK_PLL6_ENET, - imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); -- cgit v1.3.1 From db4aa4571882a8d42c3b2b8da9cf6099a8db8852 Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:38 +0300 Subject: clk: imx6q: configure ldb clock selectors A hardware bug prevents LDB clock selectors from being configured later on non-plus i.MX6QD variants, so let's set the desired configuration in the probe before we register them. We also have to make the necessary clock functions available in XPL builds. Signed-off-by: Brian Ruley --- drivers/clk/imx/clk-imx6q.c | 119 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 9ee3109bf1d..393b4215fe8 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "clk.h" @@ -141,6 +142,121 @@ static const char *ipu2_di1_sels_2[] = { }; static unsigned int share_count_mipi_core_cfg; + +static void of_assigned_ldb_sels(struct udevice *dev, int *ldb_di0_sel, + int *ldb_di1_sel) +{ + struct ofnode_phandle_args clk_args, parent_args; + ofnode node = dev_ofnode(dev); + int count, err; + + count = dev_count_phandle_with_args(dev, "assigned-clocks", + "#clock-cells", 0); + if (count <= 0) { + if (count == 0) + debug("%s: no assigned_clocks found\n", dev->name); + else + pr_err("%s: failed to get phandle count (%d)\n", + dev->name, count); + return; + } + + for (int i = 0; i < count; i++) { + err = dev_read_phandle_with_args(dev, "assigned-clocks", + "#clock-cells", 0, i, + &clk_args); + if (err == -ENOENT) + /* Skip empty handles */ + continue; + else if (err < 0) + return; + + if (!ofnode_equal(clk_args.node, node) || + clk_args.args[0] >= IMX6QDL_CLK_END) { + pr_err("%s: clock %d not in ccm\n", dev->name, i); + return; + } + + err = dev_read_phandle_with_args(dev, "assigned-clock-parents", + "#clock-cells", 0, i, + &parent_args); + if (err < 0) + return; + + if (!ofnode_equal(parent_args.node, node) || + parent_args.args[0] >= IMX6QDL_CLK_END) { + pr_err("%s: parent clock %d not in ccm\n", dev->name, + i); + return; + } + + if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI0_SEL) + *ldb_di0_sel = parent_args.args[0]; + else if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI1_SEL) + *ldb_di1_sel = parent_args.args[0]; + } +} + +static void imx6q_init_ldb_clks(struct udevice *dev) +{ + int ldb_di_sel[] = { IMX6QDL_CLK_END, IMX6QDL_CLK_END }; + enum ldb_di_clock ldb_di_clk[] = { MXC_MMDC_CH1_CLK, MXC_MMDC_CH1_CLK }; + + of_assigned_ldb_sels(dev, &ldb_di_sel[0], &ldb_di_sel[1]); + for (int i = 0; i < 2; i++) { + switch (ldb_di_sel[i]) { + case IMX6QDL_CLK_PLL5_VIDEO_DIV: + ldb_di_clk[i] = MXC_PLL5_CLK; + break; + case IMX6QDL_CLK_PLL2_PFD0_352M: + ldb_di_clk[i] = MXC_PLL2_PFD0_CLK; + break; + case IMX6QDL_CLK_PLL2_PFD2_396M: { + struct clk *clk, *parent; + + int err = clk_get_by_id(IMX6QDL_CLK_PERIPH_PRE, &clk); + + if (err) { + pr_err("%s: failed to get periph_pre clock " + "(%d)\n", + dev->name, err); + return; + } + + err = clk_get_by_id(IMX6QDL_CLK_PLL2_PFD2_396M, + &parent); + if (err) { + pr_err("%s: failed to get pll2_pfd2_396m clock" + " (%d)\n", + dev->name, err); + return; + } + + if (parent == clk) { + pr_err("%s: ldb_di%d_sel: couldn't disable " + "pll2_pfd2_396m clock\n", + dev->name, i); + return; + } + + ldb_di_clk[i] = MXC_PLL2_PFD2_CLK; + break; + } + case IMX6QDL_CLK_MMDC_CH1_AXI: + case IMX6QDL_CLK_END: + /* use the default clock */ + break; + case IMX6QDL_CLK_PLL3_USB_OTG: + ldb_di_clk[i] = MXC_PLL3_SW_CLK; + break; + default: + pr_err("%s: invalid LDB clock parent\n", dev->name); + return; + } + } + + select_ldb_di_clock_source(ldb_di_clk[0], ldb_di_clk[1]); +} #endif /* CONFIG_IS_ENABLED(VIDEO) */ static int imx6q_clk_probe(struct udevice *dev) @@ -356,7 +472,10 @@ static int imx6q_clk_probe(struct udevice *dev) /* * Need to set these as read-only due to a hardware bug. * Keeping default mux values. Fixed on the i.MX6 QuadPlus + * Need to set the clocks now and make them read-only due to a + * hardware bug. Fixed on the i.MX6 QuadPlus */ + imx6q_init_ldb_clks(dev); clk_dm(IMX6QDL_CLK_LDB_DI0_SEL, imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), -- cgit v1.3.1 From d8673fd3b5998ceb2ba3552a9d579c14566ffec7 Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:39 +0300 Subject: video: imx: ipuv3: enable ipu clk before writing registers in CCF Obviously, the clock has to be enabled if writing to it's registers. This was missed because the board I tested on had enabled the clocks in early init. Also, remove the completely useless "ipu_clk_enabled" struct member and use the accurate usecount / enabled_count instead. Signed-off-by: Brian Ruley --- drivers/video/imx/ipu.h | 1 - drivers/video/imx/ipu_common.c | 13 +++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/video/imx/ipu.h b/drivers/video/imx/ipu.h index ae40e20bc28..aecb6adffce 100644 --- a/drivers/video/imx/ipu.h +++ b/drivers/video/imx/ipu.h @@ -136,7 +136,6 @@ struct ipu_ctx { struct clk *ipu_clk; struct clk *ldb_clk; - unsigned char ipu_clk_enabled; struct clk *di_clk[2]; struct clk *pixel_clk[2]; diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index 8630374a055..d3b52605731 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -299,9 +299,9 @@ struct ipu_ctx *ipu_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) clk_set_parent(ctx->pixel_clk[0], ctx->ipu_clk); clk_set_parent(ctx->pixel_clk[1], ctx->ipu_clk); +#endif clk_enable(ctx->ipu_clk); -#endif for (int i = 0; i <= 1; i++) { ret = ipu_di_clk_init(ctx, i); @@ -384,10 +384,8 @@ int32_t ipu_init_channel(struct ipu_ctx *ctx, ipu_channel_t channel, debug("init channel = %d\n", IPU_CHAN_ID(channel)); - if (ctx->ipu_clk_enabled == 0) { - ctx->ipu_clk_enabled = 1; + if (!ipu_clk_enabled(ctx)) clk_enable(ipu_clk); - } if (*channel_init_mask & (1L << IPU_CHAN_ID(channel))) { printf("Warning: channel already initialized %d\n", @@ -543,7 +541,6 @@ void ipu_uninit_channel(struct ipu_ctx *ctx, ipu_channel_t channel) if (ipu_conf == 0) { clk_disable(ctx->ipu_clk); - ctx->ipu_clk_enabled = 0; } } @@ -1045,5 +1042,9 @@ ipu_color_space_t format_to_colorspace(u32 fmt) bool ipu_clk_enabled(struct ipu_ctx *ctx) { - return ctx->ipu_clk_enabled; +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + return clk_get_usecount(ctx->ipu_clk); +#else + return ctx->ipu_clk->enable_count; +#endif } -- cgit v1.3.1 From 3c9cb48b4757f631e30a6cba634d62be815ac066 Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:40 +0300 Subject: clk: clk-divider: add clk_register_divider_table() The existing clk_register_divider() only supports linear or power-of-two divider mappings. Some hardware (e.g. i.MX6 PLL5 post_div and video_div) uses non-linear register-value-to-divisor mappings that require a lookup table. Add clk_register_divider_table() which accepts a clk_div_table, and reimplement clk_register_divider() as a wrapper passing table=NULL. Signed-off-by: Brian Ruley --- drivers/clk/clk-divider.c | 16 +++++++++++++--- include/linux/clk-provider.h | 5 +++++ 2 files changed, 18 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index e692b9c2167..d30786a9e6c 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -228,20 +228,30 @@ static struct clk *_register_divider(struct udevice *dev, const char *name, return clk; } -struct clk *clk_register_divider(struct udevice *dev, const char *name, +struct clk *clk_register_divider_table(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, - u8 clk_divider_flags) + u8 clk_divider_flags, const struct clk_div_table *table) { struct clk *clk; clk = _register_divider(dev, name, parent_name, flags, reg, shift, - width, clk_divider_flags, NULL); + width, clk_divider_flags, table); if (IS_ERR(clk)) return ERR_CAST(clk); return clk; } +struct clk *clk_register_divider(struct udevice *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags) +{ + return clk_register_divider_table(dev, name, parent_name, flags, reg, + shift, width, clk_divider_flags, + NULL); +} + U_BOOT_DRIVER(ccf_clk_divider) = { .name = UBOOT_DM_CLK_CCF_DIVIDER, .id = UCLASS_CLK, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2d754fa4287..366f2d968a3 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -246,6 +246,11 @@ struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk *clk_register_divider_table(struct udevice *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table); + struct clk *clk_register_divider(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, -- cgit v1.3.1 From 40c9ef1e77aa991c79a7408547aa3a0a8a3a858b Mon Sep 17 00:00:00 2001 From: Brian Ruley Date: Tue, 16 Jun 2026 15:51:41 +0300 Subject: clk: imx6q: use clk_divider_table instead of fixed factor for pll5 divs Now that non-linear clk divider tables are supported, replace the fixed factor implementation with the proper divider, which allows more fine control over clock rates. Signed-off-by: Brian Ruley --- drivers/clk/imx/clk-imx6q.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 393b4215fe8..846b8011f5c 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -101,6 +101,21 @@ static const char *const ecspi_sels[] = { "osc", }; +static const struct clk_div_table post_div_table[] = { + { .val = 2, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 0, .div = 4, }, + { /* sentinel */ } +}; + +static const struct clk_div_table video_div_table[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 1, }, + { .val = 3, .div = 4, }, + { /* sentinel */ } +}; + #if CONFIG_IS_ENABLED(VIDEO) static const char *const ipu_sels[] = { "mmdc_ch0_axi", @@ -341,10 +356,14 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_PLL2_198M, imx_clk_fixed_factor(dev, "pll2_198m", "pll2_pfd2_396m", 1, 2)); clk_dm(IMX6QDL_CLK_PLL5_POST_DIV, - imx_clk_fixed_factor(dev, "pll5_post_div", "pll5_video", 1, 1)); + clk_register_divider_table(dev, "pll5_post_div", "pll5_video", + CLK_SET_RATE_PARENT, base + 0xa0, 19, + 2, 0, post_div_table)); clk_dm(IMX6QDL_CLK_PLL5_VIDEO_DIV, - imx_clk_fixed_factor(dev, "pll5_video_div", "pll5_post_div", 1, - 1)); + clk_register_divider_table(dev, "pll5_video_div", + "pll5_post_div", CLK_SET_RATE_PARENT, + base + 0x170, 30, 2, 0, + video_div_table)); clk_dm(IMX6QDL_CLK_VIDEO_27M, imx_clk_fixed_factor(dev, "video_27m", "pll3_pfd1_540m", 1, 20)); -- cgit v1.3.1 From 00bba5a3587f1b18e8ed8aa67c5dcfca7917dc89 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 26 Jun 2026 19:11:52 +0800 Subject: misc: ele_api: Add V2X Get State API Add V2X Get State API to return V2X states for debug purpose Signed-off-by: Ye Li --- arch/arm/include/asm/mach-imx/ele_api.h | 8 ++++++++ drivers/misc/imx_ele/ele_api.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) (limited to 'drivers') diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 04e7f20a2a6..8d779d6ae1b 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -30,6 +30,7 @@ #define ELE_START_RNG (0xA3) #define ELE_CMD_DERIVE_KEY (0xA9) #define ELE_GENERATE_DEK_BLOB (0xAF) +#define ELE_V2X_GET_STATE_REQ (0xB2) #define ELE_ENABLE_PATCH_REQ (0xC3) #define ELE_RELEASE_RDC_REQ (0xC4) #define ELE_GET_FW_STATUS_REQ (0xC5) @@ -141,6 +142,12 @@ struct ele_get_info_data { u32 reserved[8]; }; +struct v2x_get_state { + u8 v2x_state; + u8 v2x_power_state; + u32 v2x_err_code; +}; + int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response); int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response); int ele_release_container(u32 *response); @@ -166,4 +173,5 @@ int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response); int ele_set_gmid(u32 *response); int ele_volt_change_start_req(void); int ele_volt_change_finish_req(void); +int ele_v2x_get_state(struct v2x_get_state *state, u32 *response); #endif diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 8ee0a7733ca..355fd86ed8c 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -795,6 +795,38 @@ int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_outp return ret; } +int ele_v2x_get_state(struct v2x_get_state *state, u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg = {}; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 1; + msg.command = ELE_V2X_GET_STATE_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + state->v2x_state = msg.data[1] & 0xFF; + state->v2x_power_state = (msg.data[1] & 0xFF00) >> 8; + state->v2x_err_code = msg.data[2]; + + return ret; +} + int ele_volt_change_start_req(void) { struct udevice *dev = gd->arch.ele_dev; -- cgit v1.3.1 From 3fa1b49c940fffa5566560d5134f74b063645b7b Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Fri, 12 Jun 2026 17:43:08 +0800 Subject: spi: aspeed: add AST2700 support AST2700 is a 64-bit SoC whose flash AHB windows are decoded above the 32-bit address space, so rework AHB addresses to uintptr_t and decoded window sizes to size_t. Signed-off-by: Ryan Chen --- drivers/spi/spi-aspeed-smc.c | 219 +++++++++++++++++++++++++++++++------------ 1 file changed, 158 insertions(+), 61 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index ca29cfd7c88..0186b01ad9a 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -53,18 +53,20 @@ struct aspeed_spi_regs { u32 dma_len; /* 0x8c DMA Length Register */ u32 dma_checksum; /* 0x90 Checksum Calculation Result */ u32 timings[ASPEED_SPI_MAX_CS]; /* 0x94 Read Timing Compensation */ + u32 _reserved3[83]; /* 0xA8 - 0x1F0 */ + u32 val_kept_wdt; /* 0x1F4 Value Kept WDT */ }; struct aspeed_spi_plat { u8 max_cs; - void __iomem *ahb_base; /* AHB address base for all flash devices. */ + uintptr_t ahb_base; /* AHB address base for all flash devices. */ fdt_size_t ahb_sz; /* Overall AHB window size for all flash device. */ u32 hclk_rate; /* AHB clock rate */ }; struct aspeed_spi_flash { - void __iomem *ahb_base; - u32 ahb_decoded_sz; + uintptr_t ahb_base; + size_t ahb_decoded_sz; u32 ce_ctrl_user; u32 ce_ctrl_read; u32 max_freq; @@ -84,9 +86,9 @@ struct aspeed_spi_info { u32 min_decoded_sz; u32 clk_ctrl_mask; void (*set_4byte)(struct udevice *bus, u32 cs); - u32 (*segment_start)(struct udevice *bus, u32 reg); - u32 (*segment_end)(struct udevice *bus, u32 reg); - u32 (*segment_reg)(u32 start, u32 end); + uintptr_t (*segment_start)(struct udevice *bus, u32 reg); + uintptr_t (*segment_end)(struct udevice *bus, u32 reg); + u32 (*segment_reg)(uintptr_t start, uintptr_t end); int (*adjust_decoded_sz)(struct udevice *bus); u32 (*get_clk_setting)(struct udevice *dev, uint hz); }; @@ -118,30 +120,30 @@ static u32 aspeed_spi_get_io_mode(u32 bus_width) } } -static u32 ast2400_spi_segment_start(struct udevice *bus, u32 reg) +static uintptr_t ast2400_spi_segment_start(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 start_offset = ((reg >> 16) & 0xff) << 23; + uintptr_t start_offset = ((reg >> 16) & 0xff) << 23; if (start_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + start_offset; + return plat->ahb_base + start_offset; } -static u32 ast2400_spi_segment_end(struct udevice *bus, u32 reg) +static uintptr_t ast2400_spi_segment_end(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 end_offset = ((reg >> 24) & 0xff) << 23; + uintptr_t end_offset = ((reg >> 24) & 0xff) << 23; /* Meaningless end_offset, set to physical ahb base. */ if (end_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + end_offset; + return plat->ahb_base + end_offset; } -static u32 ast2400_spi_segment_reg(u32 start, u32 end) +static u32 ast2400_spi_segment_reg(uintptr_t start, uintptr_t end) { if (start == end) return 0; @@ -206,30 +208,30 @@ static u32 ast2400_get_clk_setting(struct udevice *dev, uint max_hz) return hclk_div; } -static u32 ast2500_spi_segment_start(struct udevice *bus, u32 reg) +static uintptr_t ast2500_spi_segment_start(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 start_offset = ((reg >> 16) & 0xff) << 23; + uintptr_t start_offset = ((reg >> 16) & 0xff) << 23; if (start_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + start_offset; + return plat->ahb_base + start_offset; } -static u32 ast2500_spi_segment_end(struct udevice *bus, u32 reg) +static uintptr_t ast2500_spi_segment_end(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 end_offset = ((reg >> 24) & 0xff) << 23; + uintptr_t end_offset = ((reg >> 24) & 0xff) << 23; /* Meaningless end_offset, set to physical ahb base. */ if (end_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + end_offset; + return plat->ahb_base + end_offset; } -static u32 ast2500_spi_segment_reg(u32 start, u32 end) +static u32 ast2500_spi_segment_reg(uintptr_t start, uintptr_t end) { if (start == end) return 0; @@ -346,30 +348,30 @@ end: return hclk_div; } -static u32 ast2600_spi_segment_start(struct udevice *bus, u32 reg) +static uintptr_t ast2600_spi_segment_start(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 start_offset = (reg << 16) & 0x0ff00000; + uintptr_t start_offset = (reg << 16) & 0x0ff00000; if (start_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + start_offset; + return plat->ahb_base + start_offset; } -static u32 ast2600_spi_segment_end(struct udevice *bus, u32 reg) +static uintptr_t ast2600_spi_segment_end(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 end_offset = reg & 0x0ff00000; + uintptr_t end_offset = reg & 0x0ff00000; /* Meaningless end_offset, set to physical ahb base. */ if (end_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + end_offset + 0x100000; + return plat->ahb_base + end_offset + 0x100000; } -static u32 ast2600_spi_segment_reg(u32 start, u32 end) +static u32 ast2600_spi_segment_reg(uintptr_t start, uintptr_t end) { if (start == end) return 0; @@ -473,6 +475,70 @@ static u32 ast2600_get_clk_setting(struct udevice *dev, uint max_hz) return hclk_div; } +static uintptr_t ast2700_spi_segment_start(struct udevice *bus, u32 reg) +{ + struct aspeed_spi_plat *plat = dev_get_plat(bus); + uintptr_t start_offset = (reg & 0x0000ffff) << 16; + + if (start_offset == 0) + return plat->ahb_base; + + return plat->ahb_base + start_offset; +} + +static uintptr_t ast2700_spi_segment_end(struct udevice *bus, u32 reg) +{ + struct aspeed_spi_plat *plat = dev_get_plat(bus); + uintptr_t end_offset = reg & 0xffff0000; + + /* Meaningless end_offset, set to physical ahb base. */ + if (end_offset == 0) + return plat->ahb_base; + + return plat->ahb_base + end_offset; +} + +static u32 ast2700_spi_segment_reg(uintptr_t start, uintptr_t end) +{ + if (start == end) + return 0; + + return (((start >> 16) & 0x7fff) | ((end + 1) & 0x7fff0000)); +} + +static void ast2700_spi_chip_set_4byte(struct udevice *bus, u32 cs) +{ + struct aspeed_spi_priv *priv = dev_get_priv(bus); + u32 reg_val; + + reg_val = readl(&priv->regs->ctrl); + reg_val |= 0x11 << cs; + writel(reg_val, &priv->regs->ctrl); + + reg_val = readl(&priv->regs->val_kept_wdt); + reg_val |= (0x11 << 4) << cs; + writel(reg_val, &priv->regs->val_kept_wdt); +} + +static int ast2700_adjust_decoded_size(struct udevice *bus) +{ + struct aspeed_spi_plat *plat = dev_get_plat(bus); + struct aspeed_spi_priv *priv = dev_get_priv(bus); + struct aspeed_spi_flash *flashes = &priv->flashes[0]; + int ret; + int cs; + + /* Close unused CS. */ + for (cs = priv->num_cs; cs < plat->max_cs; cs++) + flashes[cs].ahb_decoded_sz = 0; + + ret = aspeed_spi_trim_decoded_size(bus); + if (ret != 0) + return ret; + + return 0; +} + /* * As the flash size grows up, we need to trim some decoded * size if needed for the sake of conforming the maximum @@ -512,12 +578,12 @@ static int aspeed_spi_trim_decoded_size(struct udevice *bus) return 0; } -static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, +static int aspeed_spi_read_from_ahb(uintptr_t ahb_base, void *buf, size_t len) { size_t offset = 0; - if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) && + if (IS_ALIGNED(ahb_base, sizeof(uintptr_t)) && IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { readsl(ahb_base, buf, len >> 2); offset = len & ~0x3; @@ -529,12 +595,12 @@ static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, return 0; } -static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, +static int aspeed_spi_write_to_ahb(uintptr_t ahb_base, const void *buf, size_t len) { size_t offset = 0; - if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) && + if (IS_ALIGNED(ahb_base, sizeof(uintptr_t)) && IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { writesl(ahb_base, buf, len >> 2); offset = len & ~0x3; @@ -589,7 +655,7 @@ static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave, struct aspeed_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev); u32 cs = slave_plat->cs[0]; - u32 ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs]; + uintptr_t ce_ctrl_reg = (uintptr_t)&priv->regs->ce_ctrl[cs]; u32 ce_ctrl_val; struct aspeed_spi_flash *flash = &priv->flashes[cs]; u8 dummy_data[16] = {0}; @@ -602,7 +668,7 @@ static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave, op->data.nbytes, op->data.buswidth); if (priv->info == &ast2400_spi_info) - ce_ctrl_reg = (u32)&priv->regs->ctrl; + ce_ctrl_reg = (uintptr_t)&priv->regs->ctrl; /* * Set controller to 4-byte address mode @@ -670,7 +736,7 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) u32 i; u32 cs = slave_plat->cs[0]; u32 cmd_io_conf; - u32 ce_ctrl_reg; + uintptr_t ce_ctrl_reg; if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) { /* @@ -681,9 +747,9 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) return -EOPNOTSUPP; } - ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs]; + ce_ctrl_reg = (uintptr_t)&priv->regs->ce_ctrl[cs]; if (info == &ast2400_spi_info) - ce_ctrl_reg = (u32)&priv->regs->ctrl; + ce_ctrl_reg = (uintptr_t)&priv->regs->ctrl; if (desc->info.length > 0x1000000) priv->info->set_4byte(bus, cs); @@ -693,7 +759,7 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) priv->flashes[cs].ahb_decoded_sz = desc->info.length; for (i = 0; i < priv->num_cs; i++) { - dev_dbg(dev, "cs: %d, sz: 0x%x\n", i, + dev_dbg(dev, "cs: %d, sz: 0x%zx\n", i, priv->flashes[cs].ahb_decoded_sz); } @@ -728,7 +794,7 @@ static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u32 cs = slave_plat->cs[0]; int ret; - dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%x\n", + dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%zx\n", desc->info.op_tmpl.cmd.opcode, offs, len); if (priv->flashes[cs].ahb_decoded_sz < offs + len || @@ -738,7 +804,10 @@ static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, if (ret != 0) return 0; } else { - memcpy_fromio(buf, priv->flashes[cs].ahb_base + offs, len); + memcpy_fromio(buf, + (void __iomem *)(priv->flashes[cs].ahb_base + + (uintptr_t)offs), + len); } return len; @@ -783,19 +852,19 @@ static void aspeed_spi_decoded_range_set(struct udevice *bus) struct aspeed_spi_plat *plat = dev_get_plat(bus); struct aspeed_spi_priv *priv = dev_get_priv(bus); u32 decoded_reg_val; - u32 start_addr, end_addr; + uintptr_t start_addr, end_addr; u32 cs; for (cs = 0; cs < plat->max_cs; cs++) { - start_addr = (u32)priv->flashes[cs].ahb_base; - end_addr = (u32)priv->flashes[cs].ahb_base + + start_addr = priv->flashes[cs].ahb_base; + end_addr = priv->flashes[cs].ahb_base + priv->flashes[cs].ahb_decoded_sz; decoded_reg_val = priv->info->segment_reg(start_addr, end_addr); writel(decoded_reg_val, &priv->regs->segment_addr[cs]); - dev_dbg(bus, "cs: %d, decoded_reg: 0x%x, start: 0x%x, end: 0x%x\n", + dev_dbg(bus, "cs: %d, decoded_reg: 0x%x, start: 0x%lx, end: 0x%lx\n", cs, decoded_reg_val, start_addr, end_addr); } } @@ -851,13 +920,13 @@ static int aspeed_spi_decoded_ranges_sanity(struct udevice *bus) * address base are monotonic increasing with CE#. */ for (cs = plat->max_cs - 1; cs > 0; cs--) { - if ((u32)priv->flashes[cs].ahb_base != 0 && - (u32)priv->flashes[cs].ahb_base < - (u32)priv->flashes[cs - 1].ahb_base + + if (priv->flashes[cs].ahb_base != 0 && + priv->flashes[cs].ahb_base < + priv->flashes[cs - 1].ahb_base + priv->flashes[cs - 1].ahb_decoded_sz) { - dev_err(bus, "decoded range overlay 0x%08x 0x%08x\n", - (u32)priv->flashes[cs].ahb_base, - (u32)priv->flashes[cs - 1].ahb_base); + dev_err(bus, "decoded range overlay 0x%08lx 0x%08lx\n", + priv->flashes[cs].ahb_base, + priv->flashes[cs - 1].ahb_base); return -EINVAL; } } @@ -895,14 +964,13 @@ static int aspeed_spi_read_fixed_decoded_ranges(struct udevice *bus) return ret; for (i = 0; i < count; i++) { - priv->flashes[ranges[i].cs].ahb_base = - (void __iomem *)ranges[i].ahb_base; + priv->flashes[ranges[i].cs].ahb_base = ranges[i].ahb_base; priv->flashes[ranges[i].cs].ahb_decoded_sz = ranges[i].sz; } for (i = 0; i < plat->max_cs; i++) { - dev_dbg(bus, "ahb_base: 0x%p, size: 0x%08x\n", + dev_dbg(bus, "ahb_base: 0x%lx, size: 0x%08zx\n", priv->flashes[i].ahb_base, priv->flashes[i].ahb_decoded_sz); } @@ -1063,6 +1131,32 @@ static const struct aspeed_spi_info ast2600_spi_info = { .get_clk_setting = ast2600_get_clk_setting, }; +static const struct aspeed_spi_info ast2700_fmc_info = { + .io_mode_mask = 0xf0000000, + .max_bus_width = 4, + .min_decoded_sz = 0x10000, + .clk_ctrl_mask = 0x0f000f00, + .set_4byte = ast2700_spi_chip_set_4byte, + .segment_start = ast2700_spi_segment_start, + .segment_end = ast2700_spi_segment_end, + .segment_reg = ast2700_spi_segment_reg, + .adjust_decoded_sz = ast2700_adjust_decoded_size, + .get_clk_setting = ast2600_get_clk_setting, +}; + +static const struct aspeed_spi_info ast2700_spi_info = { + .io_mode_mask = 0xf0000000, + .max_bus_width = 4, + .min_decoded_sz = 0x10000, + .clk_ctrl_mask = 0x0f000f00, + .set_4byte = ast2700_spi_chip_set_4byte, + .segment_start = ast2700_spi_segment_start, + .segment_end = ast2700_spi_segment_end, + .segment_reg = ast2700_spi_segment_reg, + .adjust_decoded_sz = ast2700_adjust_decoded_size, + .get_clk_setting = ast2600_get_clk_setting, +}; + static int aspeed_spi_claim_bus(struct udevice *dev) { struct udevice *bus = dev->parent; @@ -1129,7 +1223,8 @@ static int apseed_spi_of_to_plat(struct udevice *bus) return -EINVAL; } - plat->ahb_base = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahb_sz); + plat->ahb_base = + (uintptr_t)devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahb_sz); if (!plat->ahb_base) { dev_err(bus, "wrong AHB base\n"); return -EINVAL; @@ -1147,8 +1242,8 @@ static int apseed_spi_of_to_plat(struct udevice *bus) plat->hclk_rate = clk_get_rate(&hclk); - dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%llx\n", - (u32)priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz); + dev_dbg(bus, "ctrl_base = 0x%p, ahb_base = 0x%lx, size = 0x%llx\n", + priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz); dev_dbg(bus, "hclk = %dMHz, max_cs = %d\n", plat->hclk_rate / 1000000, plat->max_cs); @@ -1199,6 +1294,8 @@ static const struct udevice_id aspeed_spi_ids[] = { { .compatible = "aspeed,ast2500-spi", .data = (ulong)&ast2500_spi_info, }, { .compatible = "aspeed,ast2600-fmc", .data = (ulong)&ast2600_fmc_info, }, { .compatible = "aspeed,ast2600-spi", .data = (ulong)&ast2600_spi_info, }, + { .compatible = "aspeed,ast2700-fmc", .data = (ulong)&ast2700_fmc_info, }, + { .compatible = "aspeed,ast2700-spi", .data = (ulong)&ast2700_spi_info, }, { } }; -- cgit v1.3.1 From 0758fddb3729b8b4e130f357cf8608ab1f4def5b Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Fri, 12 Jun 2026 17:43:11 +0800 Subject: clk: ast2700: add clock driver support Add clock controller driver for the dual-die AST2700 SoC. The chip has two SCUs (SoC0/CPU at 0x12c02000, SoC1/IO at 0x14c02000), each with its own PLLs (HPLL/APLL/DPLL/MPLL), clock dividers and clock gate controls. This commit registers two UCLASS_CLK drivers matching "aspeed,ast2700-scu0" and "aspeed,ast2700-scu1". Signed-off-by: Ryan Chen --- drivers/clk/aspeed/Makefile | 1 + drivers/clk/aspeed/clk_ast2700.c | 952 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 953 insertions(+) create mode 100644 drivers/clk/aspeed/clk_ast2700.c (limited to 'drivers') diff --git a/drivers/clk/aspeed/Makefile b/drivers/clk/aspeed/Makefile index 84776e5265e..285180b67cf 100644 --- a/drivers/clk/aspeed/Makefile +++ b/drivers/clk/aspeed/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_ASPEED_AST2500) += clk_ast2500.o obj-$(CONFIG_ASPEED_AST2600) += clk_ast2600.o +obj-$(CONFIG_ASPEED_AST2700) += clk_ast2700.o diff --git a/drivers/clk/aspeed/clk_ast2700.c b/drivers/clk/aspeed/clk_ast2700.c new file mode 100644 index 00000000000..ca76abef48f --- /dev/null +++ b/drivers/clk/aspeed/clk_ast2700.c @@ -0,0 +1,952 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +/** + * RGMII clock source tree + * HPLL -->|\ + * | |---->| divider |---->RGMII 125M for MAC#0 & MAC#1 + * APLL -->|/ + */ +#define RGMII_DEFAULT_CLK_SRC SCU1_CLK_HPLL + +struct mac_delay_config { + u32 tx_delay_1000; + u32 rx_delay_1000; + u32 tx_delay_100; + u32 rx_delay_100; + u32 tx_delay_10; + u32 rx_delay_10; +}; + +typedef int (*ast2700_clk_init_fn)(struct udevice *dev); + +struct ast2700_clk_priv { + void __iomem *reg; + ast2700_clk_init_fn init; +}; + +static u32 ast2700_soc1_get_pll_rate(struct ast2700_scu1 *scu, int pll_idx) +{ + union ast2700_pll_reg pll_reg; + u32 mul = 1, div = 1; + + switch (pll_idx) { + case SCU1_CLK_HPLL: + pll_reg.w = readl(&scu->hpll); + break; + case SCU1_CLK_APLL: + pll_reg.w = readl(&scu->apll); + break; + case SCU1_CLK_DPLL: + pll_reg.w = readl(&scu->dpll); + break; + } + + if (!pll_reg.b.bypass) { + mul = (pll_reg.b.m + 1) / (pll_reg.b.n + 1); + div = (pll_reg.b.p + 1); + } + + return ((CLKIN_25M * mul) / div); +} + +#define SCU_CLKSEL2_HCLK_DIV_MASK GENMASK(22, 20) +#define SCU_CLKSEL2_HCLK_DIV_SHIFT 20 + +static u32 ast2700_soc1_get_hclk_rate(struct ast2700_scu1 *scu) +{ + u32 rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + u32 clk_sel2 = readl(&scu->clk_sel2); + u32 hclk_div = (clk_sel2 & SCU_CLKSEL2_HCLK_DIV_MASK) >> + SCU_CLKSEL2_HCLK_DIV_SHIFT; + + if (!hclk_div) + hclk_div = 2; + else + hclk_div++; + + return (rate / hclk_div); +} + +#define SCU1_CLKSEL1_PCLK_DIV_MASK GENMASK(20, 18) +#define SCU1_CLKSEL1_PCLK_DIV_SHIFT 18 + +static u32 ast2700_soc1_get_pclk_rate(struct ast2700_scu1 *scu) +{ + u32 rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + + u32 clk_sel1 = readl(&scu->clk_sel1); + u32 pclk_div = (clk_sel1 & SCU1_CLKSEL1_PCLK_DIV_MASK) >> + SCU1_CLKSEL1_PCLK_DIV_SHIFT; + + return (rate / ((pclk_div + 1) * 2)); +} + +#define SCU_UART_CLKGEN_N_MASK GENMASK(17, 8) +#define SCU_UART_CLKGEN_N_SHIFT 8 +#define SCU_UART_CLKGEN_R_MASK GENMASK(7, 0) +#define SCU_UART_CLKGEN_R_SHIFT 0 + +static u32 ast2700_soc1_get_uart_uxclk_rate(struct ast2700_scu1 *scu) +{ + u32 uxclk_sel = readl(&scu->clk_sel2) & GENMASK(1, 0); + u32 uxclk_ctrl = readl(&scu->uxclk_ctrl); + u32 rate; + + switch (uxclk_sel) { + case 0: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL) / 4; + break; + case 1: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL) / 2; + break; + case 2: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL); + break; + case 3: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + break; + } + + u32 n = (uxclk_ctrl & SCU_UART_CLKGEN_N_MASK) >> + SCU_UART_CLKGEN_N_SHIFT; + u32 r = (uxclk_ctrl & SCU_UART_CLKGEN_R_MASK) >> + SCU_UART_CLKGEN_R_SHIFT; + + return ((rate * r) / (n * 2)); +} + +#define SCU_HUART_CLKGEN_N_MASK GENMASK(17, 8) +#define SCU_HUART_CLKGEN_N_SHIFT 8 +#define SCU_HUART_CLKGEN_R_MASK GENMASK(7, 0) +#define SCU_HUART_CLKGEN_R_SHIFT 0 + +static u32 ast2700_soc1_get_uart_huxclk_rate(struct ast2700_scu1 *scu) +{ + u32 huxclk_sel = (readl(&scu->clk_sel2) & GENMASK(4, 3)) >> 3; + u32 huxclk_ctrl = readl(&scu->huxclk_ctrl); + u32 n = (huxclk_ctrl & SCU_HUART_CLKGEN_N_MASK) >> + SCU_HUART_CLKGEN_N_SHIFT; + u32 r = (huxclk_ctrl & SCU_HUART_CLKGEN_R_MASK) >> + SCU_HUART_CLKGEN_R_SHIFT; + u32 rate; + + switch (huxclk_sel) { + case 0: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL) / 4; + break; + case 1: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL) / 2; + break; + case 2: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL); + break; + case 3: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + break; + } + + return ((rate * r) / (n * 2)); +} + +#define SCU_CLKSRC1_SDIO_DIV_MASK GENMASK(16, 14) +#define SCU_CLKSRC1_SDIO_DIV_SHIFT 14 +#define SCU_CLKSRC1_SDIO_SEL BIT(13) +const int ast2700_sd_div_tbl[] = { + 2, 2, 3, 4, 5, 6, 7, 8 +}; + +static u32 ast2700_soc1_get_sdio_clk_rate(struct ast2700_scu1 *scu) +{ + u32 rate = 0; + u32 clk_sel1 = readl(&scu->clk_sel1); + u32 div = (clk_sel1 & SCU_CLKSRC1_SDIO_DIV_MASK) >> + SCU_CLKSRC1_SDIO_DIV_SHIFT; + + if (clk_sel1 & SCU_CLKSRC1_SDIO_SEL) + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL); + else + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + + if (!div) + div = 1; + + div++; + + return (rate / div); +} + +static void ast2700_init_sdclk(struct ast2700_scu1 *scu) +{ + u32 src_clk = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + u32 reg_280; + int i; + + for (i = 0; i < 8; i++) { + if (src_clk / ast2700_sd_div_tbl[i] <= 125000000) + break; + } + + reg_280 = readl(&scu->clk_sel1); + reg_280 &= ~(SCU_CLKSRC1_SDIO_DIV_MASK | SCU_CLKSRC1_SDIO_SEL); + reg_280 |= i << SCU_CLKSRC1_SDIO_DIV_SHIFT; + writel(reg_280, &scu->clk_sel1); +} + +static u32 +ast2700_soc1_get_uart_clk_rate(struct ast2700_scu1 *scu, int uart_idx) +{ + u32 rate = 0; + + if (readl(&scu->clk_sel1) & BIT(uart_idx)) + rate = ast2700_soc1_get_uart_huxclk_rate(scu); + else + rate = ast2700_soc1_get_uart_uxclk_rate(scu); + + return rate; +} + +static ulong ast2700_soc1_clk_get_rate(struct clk *clk) +{ + struct ast2700_clk_priv *priv = dev_get_priv(clk->dev); + struct ast2700_scu1 *scu = (struct ast2700_scu1 *)priv->reg; + ulong rate = 0; + + switch (clk->id) { + case SCU1_CLK_HPLL: + case SCU1_CLK_APLL: + case SCU1_CLK_DPLL: + rate = ast2700_soc1_get_pll_rate(scu, clk->id); + break; + case SCU1_CLK_AHB: + rate = ast2700_soc1_get_hclk_rate(scu); + break; + case SCU1_CLK_APB: + rate = ast2700_soc1_get_pclk_rate(scu); + break; + case SCU1_CLK_GATE_UART0CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 0); + break; + case SCU1_CLK_GATE_UART1CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 1); + break; + case SCU1_CLK_GATE_UART2CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 2); + break; + case SCU1_CLK_GATE_UART3CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 3); + break; + case SCU1_CLK_GATE_UART5CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 5); + break; + case SCU1_CLK_GATE_UART6CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 6); + break; + case SCU1_CLK_GATE_UART7CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 7); + break; + case SCU1_CLK_GATE_UART8CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 8); + break; + case SCU1_CLK_GATE_UART9CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 9); + break; + case SCU1_CLK_GATE_UART10CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 10); + break; + case SCU1_CLK_GATE_UART11CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 11); + break; + case SCU1_CLK_GATE_UART12CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 12); + break; + case SCU1_CLK_GATE_SDCLK: + rate = ast2700_soc1_get_sdio_clk_rate(scu); + break; + case SCU1_CLK_UXCLK: + rate = ast2700_soc1_get_uart_uxclk_rate(scu); + break; + case SCU1_CLK_HUXCLK: + rate = ast2700_soc1_get_uart_huxclk_rate(scu); + break; + default: + debug("%s: unknown clk %ld\n", __func__, clk->id); + return -ENOENT; + } + + return rate; +} + +static int ast2700_soc1_clk_enable(struct clk *clk) +{ + struct ast2700_clk_priv *priv = dev_get_priv(clk->dev); + struct ast2700_scu1 *scu = (struct ast2700_scu1 *)priv->reg; + u32 clkgate_bit; + + if (clk->id >= 32) + clkgate_bit = BIT(clk->id - 32); + else + clkgate_bit = BIT(clk->id); + + writel(clkgate_bit, &scu->clkgate_clr1); + + return 0; +} + +static const struct clk_ops ast2700_soc1_clk_ops = { + .get_rate = ast2700_soc1_clk_get_rate, + .enable = ast2700_soc1_clk_enable, +}; + +#define SCU_HW_REVISION_ID GENMASK(23, 16) +#define SCU_CPUCLK_MASK GENMASK(4, 2) +#define SCU_CPUCLK_SHIFT 2 +static u32 ast2700_soc0_get_hpll_rate(struct ast2700_scu0 *scu) +{ + u32 chip_id1 = readl(&scu->chip_id1); + u32 hwstrap1 = readl(&scu->hwstrap1); + union ast2700_pll_reg pll_reg; + u32 mul = 1, div = 1; + u32 rate; + + pll_reg.w = readl(&scu->hpll); + + if ((chip_id1 & SCU_HW_REVISION_ID) && (hwstrap1 & BIT(3))) { + switch ((hwstrap1 & GENMASK(4, 2)) >> 2) { + case 2: + rate = 1800000000; + break; + case 3: + rate = 1700000000; + break; + case 6: + rate = 1200000000; + break; + case 7: + rate = 800000000; + break; + default: + rate = 1600000000; + } + } else if (hwstrap1 & GENMASK(3, 2)) { + switch ((hwstrap1 & GENMASK(3, 2)) >> 2) { + case 1U: + rate = 1900000000; + break; + case 2U: + rate = 1800000000; + break; + case 3U: + rate = 1700000000; + break; + default: + rate = 1600000000; + break; + } + } else { + if (pll_reg.b.bypass == 0U) { + /* F = 25Mhz * [(M + 2) / 2 * (n + 1)] / (p + 1) */ + mul = (pll_reg.b.m + 1) / ((pll_reg.b.n + 1) * 2); + div = (pll_reg.b.p + 1); + } + rate = ((CLKIN_25M * mul) / div); + } + + return rate; +} + +static u32 ast2700_soc0_get_pll_rate(struct ast2700_scu0 *scu, int pll_idx) +{ + union ast2700_pll_reg pll_reg; + u32 mul = 1, div = 1; + u32 rate; + + switch (pll_idx) { + case SCU0_CLK_DPLL: + pll_reg.w = readl(&scu->dpll); + break; + case SCU0_CLK_MPLL: + pll_reg.w = readl(&scu->mpll); + break; + default: + pr_err("%s: invalid PSP clock source (%d)\n", __func__, pll_idx); + return 0; + } + + if (pll_reg.b.bypass == 0U) { + if (pll_idx == SCU0_CLK_MPLL) { + /* F = 25Mhz * [M / (n + 1)] / (p + 1) */ + mul = (pll_reg.b.m) / ((pll_reg.b.n + 1)); + div = (pll_reg.b.p + 1); + } else { + /* F = 25Mhz * [(M + 2) / 2 * (n + 1)] / (p + 1) */ + mul = (pll_reg.b.m + 1) / ((pll_reg.b.n + 1) * 2); + div = (pll_reg.b.p + 1); + } + } + + rate = ((CLKIN_25M * mul) / div); + + return rate; +} + +/* + * AST2700A1 + * SCU010[4:2]: + * 000: CPUCLK=MPLL=1.6GHz (MPLL default setting with SCU310, SCU314) + * 001: CPUCLK=HPLL=2.0GHz (HPLL default setting with SCU300, SCU304) + * 010: CPUCLK=HPLL=1.8GHz (HPLL frequency is constance and is not controlled by SCU300, SCU304) + * 011: CPUCLK=HPLL=1.7GHz (HPLL frequency is constance and is not controlled by SCU300, SCU304) + * 100: CPUCLK=MPLL/2=800MHz (MPLL default setting with SCU310, SCU314) + * 101: CPUCLK=HPLL/2=1.0GHz (HPLL default setting with SCU300, SCU304) + * 110: CPUCLK=HPLL=1.2GHz (HPLL frequency is constance and is not controlled by SCU300, SCU304) + * 111: CPUCLK=HPLL=800MHz (HPLL frequency is constance and is not controlled by SCU300, SCU304) + */ + +static u32 ast2700_soc0_get_pspclk_rate(struct ast2700_scu0 *scu) +{ + u32 chip_id1 = readl(&scu->chip_id1); + u32 hwstrap1 = readl(&scu->hwstrap1); + u32 rate; + int cpuclk_set; + + if (chip_id1 & SCU_HW_REVISION_ID) { + cpuclk_set = (hwstrap1 & SCU_CPUCLK_MASK) >> SCU_CPUCLK_SHIFT; + switch (cpuclk_set) { + case 0: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + break; + case 1: + case 2: + case 3: + case 6: + case 7: + rate = ast2700_soc0_get_hpll_rate(scu); + break; + case 4: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL) / 2; + break; + case 5: + rate = ast2700_soc0_get_hpll_rate(scu) / 2; + break; + default: + rate = ast2700_soc0_get_hpll_rate(scu); + break; + } + } else { + if (hwstrap1 & BIT(4)) + rate = ast2700_soc0_get_hpll_rate(scu); + else + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + } + return rate; +} + +static u32 ast2700_soc0_get_axi0clk_rate(struct ast2700_scu0 *scu) +{ + return ast2700_soc0_get_pspclk_rate(scu) / 2; +} + +#define SCU_AHB_DIV_MASK GENMASK(6, 5) +#define SCU_AHB_DIV_SHIFT 5 +static u32 hclk_ast2700a1_div_table[] = { + 6, 5, 4, 7, +}; + +static u32 ast2700_soc0_get_hclk_rate(struct ast2700_scu0 *scu) +{ + u32 hwstrap1 = readl(&scu->hwstrap1); + u32 chip_id1 = readl(&scu->chip_id1); + u32 src_clk; + int div; + + if (chip_id1 & SCU_HW_REVISION_ID) { + if (hwstrap1 & BIT(7)) + src_clk = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + else + src_clk = ast2700_soc0_get_hpll_rate(scu); + + div = (hwstrap1 & SCU_AHB_DIV_MASK) >> SCU_AHB_DIV_SHIFT; + div = hclk_ast2700a1_div_table[div]; + } else { + if (hwstrap1 & BIT(7)) + src_clk = ast2700_soc0_get_hpll_rate(scu); + else + src_clk = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + + div = (hwstrap1 & SCU_AHB_DIV_MASK) >> SCU_AHB_DIV_SHIFT; + + if (!div) + div = 4; + else + div = (div + 1) * 2; + } + return (src_clk / div); +} + +static u32 ast2700_soc0_get_axi1clk_rate(struct ast2700_scu0 *scu) +{ + if (readl(&scu->chip_id1) & SCU_HW_REVISION_ID) + return ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL) / 4; + else + return ast2700_soc0_get_hclk_rate(scu); +} + +#define SCU0_CLKSEL1_PCLK_DIV_MASK GENMASK(25, 23) +#define SCU0_CLKSEL1_PCLK_DIV_SHIFT 23 + +static u32 ast2700_soc0_get_pclk_rate(struct ast2700_scu0 *scu) +{ + u32 rate = ast2700_soc0_get_axi0clk_rate(scu); + u32 clksel1 = readl(&scu->clk_sel1); + int div; + + div = (clksel1 & SCU0_CLKSEL1_PCLK_DIV_MASK) >> + SCU0_CLKSEL1_PCLK_DIV_SHIFT; + + return (rate / ((div + 1) * 2)); +} + +#define SCU_CLKSEL1_MPHYCLK_SEL_MASK GENMASK(19, 18) +#define SCU_CLKSEL1_MPHYCLK_SEL_SHIFT 18 +#define SCU_CLKSEL1_MPHYCLK_DIV_MASK GENMASK(7, 0) +static u32 ast2700_soc0_get_mphyclk_rate(struct ast2700_scu0 *scu) +{ + int div = readl(&scu->mphyclk_para) & SCU_CLKSEL1_MPHYCLK_DIV_MASK; + u32 chip_id1 = readl(&scu->chip_id1); + u32 clk_sel2; + int clk_sel; + u32 rate = 0; + + if (chip_id1 & SCU_HW_REVISION_ID) { + clk_sel2 = readl(&scu->clk_sel2); + clk_sel = (clk_sel2 & SCU_CLKSEL1_MPHYCLK_SEL_MASK) + >> SCU_CLKSEL1_MPHYCLK_SEL_SHIFT; + switch (clk_sel) { + case 0: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + break; + case 1: + rate = ast2700_soc0_get_hpll_rate(scu); + break; + case 2: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_DPLL); + break; + case 3: + rate = 26000000; + break; + } + } else { + rate = ast2700_soc0_get_hpll_rate(scu); + } + + return (rate / (div + 1)); +} + +static void ast2700_mphy_clk_init(struct ast2700_scu0 *scu) +{ + u32 clksrc1, rate = 0; + int i; + + /* set mphy clk */ + if (readl(&scu->chip_id1) & SCU_HW_REVISION_ID) { + clksrc1 = (readl(&scu->clk_sel2) & SCU_CLKSEL1_MPHYCLK_SEL_MASK) + >> SCU_CLKSEL1_MPHYCLK_SEL_SHIFT; + switch (clksrc1) { + case 0: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + break; + case 1: + rate = ast2700_soc0_get_hpll_rate(scu); + break; + case 2: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_DPLL); + break; + case 3: + rate = 26000000; + break; + } + } else { + rate = ast2700_soc0_get_hpll_rate(scu); + } + + for (i = 1; i < 256; i++) { + if ((rate / i) <= 26000000) + break; + } + + /* register defined the value plus 1 is divider*/ + i--; + writel(i, &scu->mphyclk_para); +} + +#define SCU_CLKSRC1_EMMC_DIV_MASK GENMASK(14, 12) +#define SCU_CLKSRC1_EMMC_DIV_SHIFT 12 +#define SCU_CLKSRC1_EMMC_SEL BIT(11) +static u32 ast2700_soc0_get_emmcclk_rate(struct ast2700_scu0 *scu) +{ + u32 clksel1 = readl(&scu->clk_sel1); + u32 rate; + int div; + + div = (clksel1 & SCU_CLKSRC1_EMMC_DIV_MASK) >> SCU_CLKSRC1_EMMC_DIV_SHIFT; + + if (clksel1 & SCU_CLKSRC1_EMMC_SEL) + rate = ast2700_soc0_get_hpll_rate(scu) / 4; + else + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL) / 4; + + return (rate / ((div + 1) * 2)); +} + +static void ast2700_emmc_init(struct ast2700_scu0 *scu) +{ + u32 clksrc1, rate, div; + int i; + + /* set clk/cmd driving */ + writel(2, &scu->gpio18d0_ioctrl); /* clk driving */ + writel(1, &scu->gpio18d1_ioctrl); /* cmd driving */ + writel(1, &scu->gpio18d2_ioctrl); /* data0 driving */ + writel(1, &scu->gpio18d3_ioctrl); /* data1 driving */ + writel(1, &scu->gpio18d4_ioctrl); /* data2 driving */ + writel(1, &scu->gpio18d5_ioctrl); /* data2 driving */ + + /* emmc clk: set clk src mpll/4:400Mhz */ + clksrc1 = readl(&scu->clk_sel1); + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL) / 4; + for (i = 0; i < 8; i++) { + div = (i + 1) * 2; + if ((rate / div) <= 200000000) + break; + } + + clksrc1 &= ~(SCU_CLKSRC1_EMMC_DIV_MASK | SCU_CLKSRC1_EMMC_SEL); + clksrc1 |= (i << SCU_CLKSRC1_EMMC_DIV_SHIFT); + writel(clksrc1, &scu->clk_sel1); +} + +static void ast2700_vga_clk_init(struct ast2700_scu0 *scu) +{ + if ((readl(&scu->chip_id1) & SCU_HW_REVISION_ID) == 0) + return; + + // Use d0clk/d1clk which generated from hpll for vga0/1 after A0 + // Use CRT1clk as soc display source + setbits_le32(&scu->clk_sel3, BIT(14) | BIT(13) | BIT(12)); +} + +static u32 ast2700_soc0_get_uartclk_rate(struct ast2700_scu0 *scu) +{ + u32 clksel2 = readl(&scu->clk_sel2); + u32 div = 1; + u32 rate; + + if (clksel2 & BIT(15)) + rate = 192000000; + else + rate = 24000000; + + if (clksel2 & BIT(30)) + div = 13; + return (rate / div); +} + +static ulong ast2700_soc0_clk_get_rate(struct clk *clk) +{ + struct ast2700_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + switch (clk->id) { + case SCU0_CLK_PSP: + rate = ast2700_soc0_get_pspclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_HPLL: + rate = ast2700_soc0_get_hpll_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_DPLL: + case SCU0_CLK_MPLL: + rate = ast2700_soc0_get_pll_rate((struct ast2700_scu0 *)priv->reg, clk->id); + break; + case SCU0_CLK_AXI0: + rate = ast2700_soc0_get_axi0clk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_AXI1: + rate = ast2700_soc0_get_axi1clk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_AHB: + rate = ast2700_soc0_get_hclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_APB: + rate = ast2700_soc0_get_pclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_GATE_EMMCCLK: + rate = ast2700_soc0_get_emmcclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_GATE_UART4CLK: + rate = ast2700_soc0_get_uartclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_MPHY: + rate = ast2700_soc0_get_mphyclk_rate((struct ast2700_scu0 *)priv->reg); + break; + default: + debug("%s: unknown clk %ld\n", __func__, clk->id); + return -ENOENT; + } + + return rate; +} + +static int ast2700_soc0_clk_enable(struct clk *clk) +{ + struct ast2700_clk_priv *priv = dev_get_priv(clk->dev); + struct ast2700_scu0 *scu = (struct ast2700_scu0 *)priv->reg; + u32 clkgate_bit = BIT(clk->id); + + writel(clkgate_bit, &scu->clkgate_clr); + + return 0; +} + +static const struct clk_ops ast2700_soc0_clk_ops = { + .get_rate = ast2700_soc0_clk_get_rate, + .enable = ast2700_soc0_clk_enable, +}; + +static void ast2700_init_mac_clk(struct ast2700_scu1 *scu) +{ + u32 src_clk = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + u32 reg_280; + u8 div_idx; + + /* The MAC source clock selects HPLL only, and the default clock + * setting is 200 Mhz. + * Calculate the corresponding divider: + * 1: div 2 + * 2: div 3 + * ... + * 7: div 8 + */ + for (div_idx = 1; div_idx <= 7; div_idx++) + if (DIV_ROUND_UP(src_clk, div_idx + 1) == 200000000) + break; + + if (div_idx == 8) { + pr_err("MAC clock cannot divide to 200 MHz\n"); + return; + } + + /* set HPLL clock divider */ + reg_280 = readl(&scu->clk_sel1); + reg_280 &= ~GENMASK(31, 29); + reg_280 |= div_idx << 29; + writel(reg_280, &scu->clk_sel1); +} + +static void ast2700_init_rgmii_clk(struct ast2700_scu1 *scu) +{ + u32 reg_284 = readl(&scu->clk_sel2); + u32 src_clk = ast2700_soc1_get_pll_rate(scu, RGMII_DEFAULT_CLK_SRC); + + if (RGMII_DEFAULT_CLK_SRC == SCU1_CLK_HPLL) { + u32 reg_280; + u8 div_idx; + + /* Calculate the corresponding divider: + * 1: div 4 + * 2: div 6 + * ... + * 7: div 16 + */ + for (div_idx = 1; div_idx <= 7; div_idx++) { + u8 div = 4 + 2 * (div_idx - 1); + + if (DIV_ROUND_UP(src_clk, div) == 125000000) + break; + } + if (div_idx == 8) { + pr_err("RGMII using HPLL cannot divide to 125 MHz\n"); + return; + } + + /* set HPLL clock divider */ + reg_280 = readl(&scu->clk_sel1); + reg_280 &= ~GENMASK(27, 25); + reg_280 |= div_idx << 25; + writel(reg_280, &scu->clk_sel1); + + /* select HPLL clock source */ + reg_284 &= ~BIT(18); + } else { + /* APLL clock divider is fixed to 8 */ + if (DIV_ROUND_UP(src_clk, 8) != 125000000) { + pr_err("RGMII using APLL cannot divide to 125 MHz\n"); + return; + } + + /* select APLL clock source */ + reg_284 |= BIT(18); + } + + writel(reg_284, &scu->clk_sel2); +} + +static void ast2700_init_rmii_clk(struct ast2700_scu1 *scu) +{ + u32 src_clk = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + u32 reg_280; + u8 div_idx; + + /* The RMII source clock selects HPLL only. + * Calculate the corresponding divider: + * 1: div 8 + * 2: div 12 + * ... + * 7: div 32 + */ + for (div_idx = 1; div_idx <= 7; div_idx++) { + u8 div = 8 + 4 * (div_idx - 1); + + if (DIV_ROUND_UP(src_clk, div) == 50000000) + break; + } + if (div_idx == 8) { + pr_err("RMII using HPLL cannot divide to 50 MHz\n"); + return; + } + + /* set RMII clock divider */ + reg_280 = readl(&scu->clk_sel1); + reg_280 &= ~GENMASK(23, 21); + reg_280 |= div_idx << 21; + writel(reg_280, &scu->clk_sel1); +} + +static void ast2700_init_spi(struct ast2700_scu1 *scu) +{ + writel(readl(&scu->io_driving8) | 0x0000aaaa, &scu->io_driving8); /* fwspi driving */ + writel(readl(&scu->io_driving3) | 0x00000aaa, &scu->io_driving3); /* spi0 driving */ + writel(readl(&scu->io_driving3) | 0x0aaa0000, &scu->io_driving3); /* spi1 driving */ + writel(readl(&scu->io_driving4) | 0x00002aaa, &scu->io_driving4); /* spi2 driving */ +} + +#define SCU1_CLK_I3C_DIV_MASK GENMASK(25, 23) +#define SCU1_CLK_I3C_DIV(n) ((n) - 1) +static void ast2700_init_i3c_clk(struct ast2700_scu1 *scu) +{ + u32 reg_284; + + /* I3C 250MHz = HPLL/4 */ + reg_284 = readl(&scu->clk_sel2); + reg_284 &= ~SCU1_CLK_I3C_DIV_MASK; + reg_284 |= FIELD_PREP(SCU1_CLK_I3C_DIV_MASK, SCU1_CLK_I3C_DIV(4)); + writel(reg_284, &scu->clk_sel2); +} + +static int ast2700_clk1_init(struct udevice *dev) +{ + struct ast2700_clk_priv *priv = dev_get_priv(dev); + struct ast2700_scu1 *scu = (struct ast2700_scu1 *)priv->reg; + + ast2700_init_spi(scu); + ast2700_init_mac_clk(scu); + ast2700_init_rgmii_clk(scu); + ast2700_init_rmii_clk(scu); + ast2700_init_sdclk(scu); + ast2700_init_i3c_clk(scu); + + return 0; +} + +static int ast2700_clk0_init(struct udevice *dev) +{ + struct ast2700_clk_priv *priv = dev_get_priv(dev); + struct ast2700_scu0 *scu = (struct ast2700_scu0 *)priv->reg; + + ast2700_emmc_init(scu); + ast2700_mphy_clk_init(scu); + ast2700_vga_clk_init(scu); + + return 0; +} + +static int ast2700_clk_probe(struct udevice *dev) +{ + struct ast2700_clk_priv *priv = dev_get_priv(dev); + + priv->init = (ast2700_clk_init_fn)dev_get_driver_data(dev); + priv->reg = (void __iomem *)dev_read_addr_ptr(dev); + + if (priv->init) + return priv->init(dev); + + return 0; +} + +static int ast2700_clk_bind(struct udevice *dev) +{ + struct udevice *sysreset_dev, *rst_dev; + int ret; + + /* The system reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &sysreset_dev); + if (ret) + debug("Warning: No sysreset driver: ret = %d\n", ret); + + /* Bind the per-SCU reset controller to the same ofnode so that + * <&syscon0/1 RESET_X> phandle references resolve to a UCLASS_RESET + * device. This pairs with the airoha-style binding pattern. + */ + if (CONFIG_IS_ENABLED(RESET_AST2700)) { + ret = device_bind_driver_to_node(dev, "ast2700_reset", "reset", + dev_ofnode(dev), &rst_dev); + if (ret) + debug("Warning: failed to bind reset controller: ret = %d\n", ret); + } + + return 0; +} + +static const struct udevice_id ast2700_soc1_clk_ids[] = { + { .compatible = "aspeed,ast2700-scu1", .data = (ulong)&ast2700_clk1_init }, + { }, +}; + +U_BOOT_DRIVER(aspeed_ast2700_soc1_clk) = { + .name = "aspeed_ast2700_scu1", + .id = UCLASS_CLK, + .of_match = ast2700_soc1_clk_ids, + .priv_auto = sizeof(struct ast2700_clk_priv), + .ops = &ast2700_soc1_clk_ops, + .probe = ast2700_clk_probe, + .bind = ast2700_clk_bind, +}; + +static const struct udevice_id ast2700_soc0_clk_ids[] = { + { .compatible = "aspeed,ast2700-scu0", .data = (ulong)&ast2700_clk0_init }, + { }, +}; + +U_BOOT_DRIVER(aspeed_ast2700_soc0_clk) = { + .name = "aspeed_ast2700_scu0", + .id = UCLASS_CLK, + .of_match = ast2700_soc0_clk_ids, + .priv_auto = sizeof(struct ast2700_clk_priv), + .ops = &ast2700_soc0_clk_ops, + .probe = ast2700_clk_probe, + .bind = ast2700_clk_bind, +}; -- cgit v1.3.1 From 6fb40812ddb846b02d585c55895242959cbb6495 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Fri, 12 Jun 2026 17:43:12 +0800 Subject: reset: ast2700: add reset driver support Add reset controller driver for the dual-die AST2700 SoC. The controller manages module-level reset signals via the modrst register block at offset 0x200 within each SCU. Signed-off-by: Ryan Chen --- MAINTAINERS | 2 +- drivers/reset/Kconfig | 9 +++++ drivers/reset/Makefile | 1 + drivers/reset/reset-ast2700.c | 82 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 93 insertions(+), 1 deletion(-) create mode 100644 drivers/reset/reset-ast2700.c (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index 41059979f30..6a633df499d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -222,7 +222,7 @@ F: drivers/net/ftgmac100.[ch] F: drivers/pinctrl/aspeed/ F: drivers/pwm/pwm-aspeed.c F: drivers/ram/aspeed/ -F: drivers/reset/reset-ast2500.c +F: drivers/reset/reset-ast*.c F: drivers/watchdog/ast_wdt.c N: aspeed N: ast2700 diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index e7c0870c918..c851354c7a5 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -107,6 +107,15 @@ config RESET_AST2600 Say Y if you want to control reset signals of different peripherals through System Control Unit (SCU). +config RESET_AST2700 + bool "Reset controller driver for AST2700 SoCs" + depends on DM_RESET && ASPEED_AST2700 + default y if ASPEED_AST2700 + help + Support for reset controller on AST2700 SoC. + Say Y if you want to control reset signals of different peripherals + through System Control Unit (SCU). + config RESET_ROCKCHIP bool "Reset controller driver for Rockchip SoCs" depends on DM_RESET && ARCH_ROCKCHIP && CLK diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 2c83f858895..3fce96509cd 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o +obj-$(CONFIG_RESET_AST2700) += reset-ast2700.o obj-$(CONFIG_$(PHASE_)RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o diff --git a/drivers/reset/reset-ast2700.c b/drivers/reset/reset-ast2700.c new file mode 100644 index 00000000000..2dd9e36cc0a --- /dev/null +++ b/drivers/reset/reset-ast2700.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include + +/* Offset of the modrst register block within the SCU. */ +#define AST2700_RESET_OFFSET 0x200 + +struct ast2700_reset_priv { + void __iomem *base; +}; + +static int ast2700_reset_assert(struct reset_ctl *reset_ctl) +{ + struct ast2700_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + if (reset_ctl->id < 32) + writel(BIT(reset_ctl->id), priv->base); + else + writel(BIT(reset_ctl->id - 32), priv->base + 0x20); + + return 0; +} + +static int ast2700_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct ast2700_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + if (reset_ctl->id < 32) + writel(BIT(reset_ctl->id), priv->base + 0x04); + else + writel(BIT(reset_ctl->id - 32), priv->base + 0x24); + + return 0; +} + +static int ast2700_reset_status(struct reset_ctl *reset_ctl) +{ + struct ast2700_reset_priv *priv = dev_get_priv(reset_ctl->dev); + int status; + + if (reset_ctl->id < 32) + status = BIT(reset_ctl->id) & readl(priv->base); + else + status = BIT(reset_ctl->id - 32) & readl(priv->base + 0x20); + + return !!status; +} + +static int ast2700_reset_probe(struct udevice *dev) +{ + struct ast2700_reset_priv *priv = dev_get_priv(dev); + void __iomem *scu_base; + + scu_base = dev_read_addr_ptr(dev); + if (!scu_base) + return -EINVAL; + + priv->base = scu_base + AST2700_RESET_OFFSET; + + return 0; +} + +static const struct reset_ops ast2700_reset_ops = { + .rst_assert = ast2700_reset_assert, + .rst_deassert = ast2700_reset_deassert, + .rst_status = ast2700_reset_status, +}; + +U_BOOT_DRIVER(ast2700_reset) = { + .name = "ast2700_reset", + .id = UCLASS_RESET, + .probe = ast2700_reset_probe, + .ops = &ast2700_reset_ops, + .priv_auto = sizeof(struct ast2700_reset_priv), +}; -- cgit v1.3.1 From 4a72fd9fb09109857303ca64fd259009e1d4b554 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Fri, 12 Jun 2026 17:43:13 +0800 Subject: ram: aspeed: add SDRAM controller driver for AST2700 Add a SDRAM controller driver for the AST2700, derived from the existing AST2700 controller code used by the Ibex SPL but adapted to run from ARM U-Boot proper on the Cortex-A35 cores. The DDR4/DDR5 controller and its DesignWare PHY are programmed by the Ibex SPL before ARM U-Boot proper takes over. This driver reads back the configuration left by the SPL, probes the controller, and exposes ram_info (base and size, with the VGA carve-out subtracted) via UCLASS_RAM so that dram_init() can populate gd->ram_size. The PHY firmware-load entry points (dwc_ddrphy_phyinit_userCustom_*) are kept compiled but call a __weak fmc_hdr_get_prebuilt() stub when ARM U-Boot proper is the caller; the real implementation is provided by the Ibex SPL via the same fmc_hdr.h descriptor format (here added for the ARM build). Adds the supporting register-layout headers under arch/arm/include/asm/arch-aspeed/: - sdram.h: SDRAM controller and DWC PHY register definitions - scu.h: SCU bits referenced by the SDRAM driver - fmc_hdr.h: prebuilt-blob descriptor (binary-compatible with arch/riscv/include/asm/arch-ast2700/fmc_hdr.h used by the Ibex SPL) Signed-off-by: Ryan Chen --- MAINTAINERS | 1 + arch/arm/include/asm/arch-aspeed/fmc_hdr.h | 52 +++++++++++ arch/arm/include/asm/arch-aspeed/scu.h | 145 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-aspeed/sdram.h | 137 +++++++++++++++++++++++++++ drivers/ram/aspeed/Kconfig | 2 +- drivers/ram/aspeed/Makefile | 1 + drivers/ram/aspeed/sdram_ast2700.c | 15 ++- 7 files changed, 347 insertions(+), 6 deletions(-) create mode 100644 arch/arm/include/asm/arch-aspeed/fmc_hdr.h create mode 100644 arch/arm/include/asm/arch-aspeed/scu.h create mode 100644 arch/arm/include/asm/arch-aspeed/sdram.h (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index 6a633df499d..74520244e80 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -211,6 +211,7 @@ S: Maintained F: arch/arm/dts/ast* F: arch/arm/mach-aspeed/ F: arch/arm/include/asm/arch-aspeed/ +F: arch/riscv/include/asm/arch-ast2700/ F: board/aspeed/ F: drivers/clk/aspeed/ F: drivers/crypto/aspeed/ diff --git a/arch/arm/include/asm/arch-aspeed/fmc_hdr.h b/arch/arm/include/asm/arch-aspeed/fmc_hdr.h new file mode 100644 index 00000000000..c60277e1a81 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/fmc_hdr.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#ifndef __ASM_AST2700_FMC_HDR_H__ +#define __ASM_AST2700_FMC_HDR_H__ + +#include + +#define HDR_MAGIC 0x48545341 /* ASTH */ +#define HDR_PB_MAX 30 + +enum prebuilt_type { + PBT_END_MARK = 0x0, + + PBT_DDR4_PMU_TRAIN_IMEM, + PBT_DDR4_PMU_TRAIN_DMEM, + PBT_DDR4_2D_PMU_TRAIN_IMEM, + PBT_DDR4_2D_PMU_TRAIN_DMEM, + PBT_DDR5_PMU_TRAIN_IMEM, + PBT_DDR5_PMU_TRAIN_DMEM, + PBT_DP_FW, + PBT_UEFI_X64_AST2700, + + PBT_NUM +}; + +struct fmc_hdr_preamble { + u32 magic; + u32 version; +}; + +struct fmc_hdr_body { + u32 fmc_size; + union { + struct { + u32 type; + u32 size; + } pbs[0]; + u32 raz[29]; + }; +}; + +struct fmc_hdr { + struct fmc_hdr_preamble preamble; + struct fmc_hdr_body body; +} __packed; + +int fmc_hdr_get_prebuilt(u32 type, u32 *ofst, u32 *size); + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/scu.h b/arch/arm/include/asm/arch-aspeed/scu.h new file mode 100644 index 00000000000..1aa7d38bace --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/scu.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef __ASM_AST2700_SCU_H__ +#define __ASM_AST2700_SCU_H__ + +/* SCU0: CPU-die SCU */ +#define SCU0_HWSTRAP 0x010 +#define SCU0_HWSTRAP_DIS_RVAS BIT(30) +#define SCU0_HWSTRAP_DIS_WDTFULL BIT(25) +#define SCU0_HWSTRAP_DISARMICE_TZ BIT(22) +#define SCU0_HWSTRAP_DISABLE_XHCI BIT(21) +#define SCU0_HWSTRAP_BOOTEMMCSPEED BIT(20) +#define SCU0_HWSTRAP_VGA_CC BIT(18) +#define SCU0_HWSTRAP_EN_OPROM BIT(17) +#define SCU0_HWSTRAP_DISARMICE BIT(16) +#define SCU0_HWSTRAP_TSPRSNTSEL BIT(9) +#define SCU0_HWSTRAP_DISDEBUG BIT(8) +#define SCU0_HWSTRAP_HCLKHPLL BIT(7) +#define SCU0_HWSTRAP_HCLKSEL GENMASK(6, 5) +#define SCU0_HWSTRAP_CPUHPLL BIT(4) +#define SCU0_HWSTRAP_HPLLFREQ GENMASK(3, 2) +#define SCU0_HWSTRAP_BOOTSPI BIT(1) +#define SCU0_HWSTRAP_HWSTRAP_DISCPU BIT(0) +#define SCU0_DBGCTL 0x0c8 +#define SCU0_DBGCTL_MASK GENMASK(14, 0) +#define SCU0_DBGCTL_UARTDBG BIT(1) +#define SCU0_RSTCTL1 0x200 +#define SCU0_RSTCTL1_EMMC BIT(17) +#define SCU0_RSTCTL1_HACE BIT(4) +#define SCU0_RSTCTL1_CLR 0x204 +#define SCU0_RSTCTL1_CLR_EMMC BIT(17) +#define SCU0_RSTCTL1_CLR_HACE BIT(4) +#define SCU0_CLKGATE1 0x240 +#define SCU0_CLKGATE1_EMMC BIT(27) +#define SCU0_CLKGATE1_HACE BIT(13) +#define SCU0_CLKGATE1_DDRPHY BIT(11) +#define SCU0_CLKGATE1_CLR 0x244 +#define SCU0_CLKGATE1_CLR_EMMC BIT(27) +#define SCU0_CLKGATE1_CLR_HACE BIT(13) +#define SCU0_CLKGATE1_CLR_DDRPHY BIT(11) +#define SCU0_VGA0_SCRATCH 0x900 +#define SCU0_VGA0_SCRATCH_DRAM_INIT BIT(6) +#define SCU0_PCI_MISC70 0xa70 +#define SCU0_PCI_MISC70_EN_PCIEXHCI0 BIT(3) +#define SCU0_PCI_MISC70_EN_PCIEEHCI0 BIT(2) +#define SCU0_PCI_MISC70_EN_PCIEVGA0 BIT(0) +#define SCU0_PCI_MISC80 0xa80 +#define SCU0_PCI_MISC80_EN_PCIEXHCI1 BIT(3) +#define SCU0_PCI_MISC80_EN_PCIEEHCI1 BIT(2) +#define SCU0_PCI_MISC80_EN_PCIEVGA1 BIT(0) +#define SCU0_PCI_MISCF0 0xaf0 +#define SCU0_PCI_MISCF0_EN_PCIEXHCI1 BIT(3) +#define SCU0_PCI_MISCF0_EN_PCIEEHCI1 BIT(2) +#define SCU0_PCI_MISCF0_EN_PCIEVGA1 BIT(0) +#define SCU0_WPROT1 0xe04 +#define SCU0_WPROT1_0C8 BIT(18) + +/* SCU1: IO-die SCU */ +#define SCU1_REVISION 0x000 +#define SCU1_REVISION_HWID GENMASK(23, 16) +#define SCU1_REVISION_CHIP_EFUSE GENMASK(15, 8) +#define SCU1_HWSTRAP1 0x010 +#define SCU1_HWSTRAP1_DIS_CPTRA BIT(30) +#define SCU1_HWSTRAP1_RECOVERY_USB_PORT GENMASK(29, 28) +#define SCU1_HWSTRAP1_RECOVERY_INTERFACE GENMASK(27, 26) +#define SCU1_HWSTRAP1_RECOVERY_I3C (BIT(26) | BIT(27)) +#define SCU1_HWSTRAP1_RECOVERY_I2C BIT(27) +#define SCU1_HWSTRAP1_RECOVERY_USB BIT(26) +#define SCU1_HWSTRAP1_SPI_FLASH_4_BYTE_MODE BIT(25) +#define SCU1_HWSTRAP1_SPI_FLASH_WAIT_READY BIT(24) +#define SCU1_HWSTRAP1_BOOT_UFS BIT(23) +#define SCU1_HWSTRAP1_DIS_ROM BIT(22) +#define SCU1_HWSTRAP1_DIS_CPTRAJTAG BIT(20) +#define SCU1_HWSTRAP1_UARTDBGSEL BIT(19) +#define SCU1_HWSTRAP1_DIS_UARTDBG BIT(18) +#define SCU1_HWSTRAP1_DIS_WDTFULL BIT(17) +#define SCU1_HWSTRAP1_DISDEBUG1 BIT(16) +#define SCU1_HWSTRAP1_LTPI0_IO_DRIVING GENMASK(15, 14) +#define SCU1_HWSTRAP1_ACPI_1 BIT(13) +#define SCU1_HWSTRAP1_ACPI_0 BIT(12) +#define SCU1_HWSTRAP1_BOOT_EMMC_UFS BIT(11) +#define SCU1_HWSTRAP1_DDR4 BIT(10) +#define SCU1_HWSTRAP1_LOW_SECURE BIT(8) +#define SCU1_HWSTRAP1_EN_EMCS BIT(7) +#define SCU1_HWSTRAP1_EN_GPIOPT BIT(6) +#define SCU1_HWSTRAP1_EN_SECBOOT BIT(5) +#define SCU1_HWSTRAP1_EN_RECOVERY_BOOT BIT(4) +#define SCU1_HWSTRAP1_LTPI0_EN BIT(3) +#define SCU1_HWSTRAP1_LTPI_IDX BIT(2) +#define SCU1_HWSTRAP1_LTPI1_EN BIT(1) +#define SCU1_HWSTRAP1_LTPI_MODE BIT(0) +#define SCU1_HWSTRAP2 0x030 +#define SCU1_HWSTRAP2_FMC_ABR_SINGLE_FLASH BIT(29) +#define SCU1_HWSTRAP2_FMC_ABR_CS_SWAP_DIS BIT(28) +#define SCU1_HWSTRAP2_SPI_TPM_PCR_EXT_EN BIT(27) +#define SCU1_HWSTRAP2_SPI_TPM_HASH_ALGO GENMASK(26, 25) +#define SCU1_HWSTRAP2_BOOT_SPI_FREQ GENMASK(24, 23) +#define SCU1_HWSTRAP2_RESERVED GENMASK(22, 19) +#define SCU1_HWSTRAP2_FWSPI_CRTM GENMASK(18, 17) +#define SCU1_HWSTRAP2_EN_FWSPIAUX BIT(16) +#define SCU1_HWSTRAP2_FWSPISIZE GENMASK(15, 13) +#define SCU1_HWSTRAP2_DIS_REC BIT(12) +#define SCU1_HWSTRAP2_EN_CPTRA_DBG BIT(11) +#define SCU1_HWSTRAP2_TPM_PCR_INDEX GENMASK(6, 2) +#define SCU1_HWSTRAP2_ROM_CLEAR_SRAM BIT(1) +#define SCU1_HWSTRAP2_ABR BIT(0) +#define SCU1_RSTLOG0 0x050 +#define SCU1_RSTLOG0_BMC_CPU BIT(12) +#define SCU1_RSTLOG0_ABR BIT(2) +#define SCU1_RSTLOG0_EXTRSTN BIT(1) +#define SCU1_RSTLOG0_SRST BIT(0) +#define SCU1_MISC1 0x0c0 +#define SCU1_MISC1_UARTDBG_ROUTE GENMASK(23, 22) +#define SCU1_MISC1_UART12_ROUTE GENMASK(21, 20) +#define SCU1_DBGCTL 0x0c8 +#define SCU1_DBGCTL_MASK GENMASK(7, 0) +#define SCU1_DBGCTL_UARTDBG BIT(6) +#define SCU1_RNG_DATA 0x0f4 +#define SCU1_RSTCTL1 0x200 +#define SCU1_RSTCTL1_I3C(x) (BIT(16) << (x)) +#define SCU1_RSTCTL1_CLR 0x204 +#define SCU1_RSTCTL1_CLR_I3C(x) (BIT(16) << (x)) +#define SCU1_RSTCTL2 0x220 +#define SCU1_RSTCTL2_LTPI1 BIT(22) +#define SCU1_RSTCTL2_LTPI0 BIT(20) +#define SCU1_RSTCTL2_I2C BIT(15) +#define SCU1_RSTCTL2_CPTRA BIT(9) +#define SCU1_RSTCTL2_CLR 0x224 +#define SCU1_RSTCTL2_CLR_I2C BIT(15) +#define SCU1_RSTCTL2_CLR_CPTRA BIT(9) +#define SCU1_CLKGATE1 0x240 +#define SCU1_CLKGATE1_I3C(x) (BIT(16) << (x)) +#define SCU1_CLKGATE1_I2C BIT(15) +#define SCU1_CLKGATE1_CLR 0x244 +#define SCU1_CLKGATE1_CLR_I3C(x) (BIT(16) << (x)) +#define SCU1_CLKGATE1_CLR_I2C BIT(15) +#define SCU1_CLKGATE2 0x260 +#define SCU1_CLKGATE2_LTPI1_TX BIT(19) +#define SCU1_CLKGATE2_LTPI_AHB BIT(10) +#define SCU1_CLKGATE2_LTPI0_TX BIT(9) +#define SCU1_CLKGATE2_CLR 0x264 + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/sdram.h b/arch/arm/include/asm/arch-aspeed/sdram.h new file mode 100644 index 00000000000..daf48dd6ed1 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/sdram.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef __ASM_AST2700_SDRAM_H__ +#define __ASM_AST2700_SDRAM_H__ + +struct sdrammc_regs { + u32 prot_key; + u32 intr_status; + u32 intr_clear; + u32 intr_mask; + u32 mcfg; + u32 mctl; + u32 msts; + u32 error_status; + u32 actime1; + u32 actime2; + u32 actime3; + u32 actime4; + u32 actime5; + u32 actime6; + u32 actime7; + u32 dfi_timing; + u32 dcfg; + u32 dctl; + u32 mrctl; + u32 mrwr; + u32 mrrd; + u32 mr01; + u32 mr23; + u32 mr45; + u32 mr67; + u32 refctl; + u32 refmng_ctl; + u32 refsts; + u32 zqctl; + u32 ecc_addr_range; + u32 ecc_failure_status; + u32 ecc_failure_addr; + u32 ecc_test_control; + u32 ecc_test_status; + u32 arbctl; + u32 enccfg; + u32 protect_lock_set; + u32 protect_lock_status; + u32 protect_lock_reset; + u32 enc_min_addr; + u32 enc_max_addr; + u32 enc_key[4]; + u32 enc_iv[3]; + u32 bistcfg; + u32 bist_addr; + u32 bist_size; + u32 bist_patt; + u32 bist_res; + u32 bist_fail_addr; + u32 bist_fail_data[4]; + u32 reserved2[2]; + u32 debug_control; + u32 debug_status; + u32 phy_intf_status; + u32 testcfg; + u32 gfmcfg; + u32 gfm0ctl; + u32 gfm1ctl; + u32 reserved3[0xf8]; +}; + +#define DRAMC_UNLK_KEY 0x1688a8a8 + +/* offset 0x04 */ +#define DRAMC_IRQSTA_PWRCTL_ERR BIT(16) +#define DRAMC_IRQSTA_PHY_ERR BIT(15) +#define DRAMC_IRQSTA_LOWPOWER_DONE BIT(12) +#define DRAMC_IRQSTA_FREQ_CHG_DONE BIT(11) +#define DRAMC_IRQSTA_REF_DONE BIT(10) +#define DRAMC_IRQSTA_ZQ_DONE BIT(9) +#define DRAMC_IRQSTA_BIST_DONE BIT(8) +#define DRAMC_IRQSTA_ECC_RCVY_ERR BIT(5) +#define DRAMC_IRQSTA_ECC_ERR BIT(4) +#define DRAMC_IRQSTA_PROT_ERR BIT(3) +#define DRAMC_IRQSTA_OVERSZ_ERR BIT(2) +#define DRAMC_IRQSTA_MR_DONE BIT(1) +#define DRAMC_IRQSTA_PHY_INIT_DONE BIT(0) + +/* offset 0x14 */ +#define DRAMC_MCTL_WB_SOFT_RESET BIT(24) +#define DRAMC_MCTL_PHY_CLK_DIS BIT(18) +#define DRAMC_MCTL_PHY_RESET BIT(17) +#define DRAMC_MCTL_PHY_POWER_ON BIT(16) +#define DRAMC_MCTL_FREQ_CHG_START BIT(3) +#define DRAMC_MCTL_PHY_LOWPOWER_START BIT(2) +#define DRAMC_MCTL_SELF_REF_START BIT(1) +#define DRAMC_MCTL_PHY_INIT_START BIT(0) + +/* offset 0x40 */ +#define DRAMC_DFICFG_WD_POL BIT(18) +#define DRAMC_DFICFG_CKE_OUT BIT(17) +#define DRAMC_DFICFG_RESET BIT(16) + +/* offset 0x48 */ +#define DRAMC_MRCTL_ERR_STATUS BIT(31) +#define DRAMC_MRCTL_READY_STATUS BIT(30) +#define DRAMC_MRCTL_MR_ADDR BIT(8) +#define DRAMC_MRCTL_CMD_DLL_RST BIT(7) +#define DRAMC_MRCTL_CMD_DQ_SEL BIT(6) +#define DRAMC_MRCTL_CMD_TYPE BIT(2) +#define DRAMC_MRCTL_CMD_WR_CTL BIT(1) +#define DRAMC_MRCTL_CMD_START BIT(0) + +/* offset 0xC0 */ +#define DRAMC_BISTRES_RUNNING BIT(10) +#define DRAMC_BISTRES_FAIL BIT(9) +#define DRAMC_BISTRES_DONE BIT(8) +#define DRAMC_BISTCFG_INIT_MODE BIT(7) +#define DRAMC_BISTCFG_PMODE GENMASK(6, 4) +#define DRAMC_BISTCFG_BMODE GENMASK(3, 2) +#define DRAMC_BISTCFG_ENABLE BIT(1) +#define DRAMC_BISTCFG_START BIT(0) +#define BIST_PMODE_CRC (3) +#define BIST_BMODE_RW_SWITCH (3) + +/* DRAMC048 MR Control Register */ +#define MR_TYPE_SHIFT 2 +#define MR_RW (0 << MR_TYPE_SHIFT) +#define MR_MPC BIT(2) +#define MR_VREFCS (2 << MR_TYPE_SHIFT) +#define MR_VREFCA (3 << MR_TYPE_SHIFT) +#define MR_ADDRESS_SHIFT 8 +#define MR_ADDR(n) (((n) << MR_ADDRESS_SHIFT) | DRAMC_MRCTL_CMD_WR_CTL) +#define MR_NUM_SHIFT 4 +#define MR_NUM(n) ((n) << MR_NUM_SHIFT) +#define MR_DLL_RESET BIT(7) +#define MR_1T_MODE BIT(16) + +#endif diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig index e4918460de6..9bb37b81cc3 100644 --- a/drivers/ram/aspeed/Kconfig +++ b/drivers/ram/aspeed/Kconfig @@ -77,7 +77,7 @@ choice prompt "AST2700 DDR target date rate" default ASPEED_DDR_3200 depends on ASPEED_RAM - depends on TARGET_ASPEED_AST2700_IBEX + depends on ASPEED_AST2700 || TARGET_ASPEED_AST2700_IBEX config ASPEED_DDR_1600 bool "1600 Mbps" diff --git a/drivers/ram/aspeed/Makefile b/drivers/ram/aspeed/Makefile index 1f0b22c8e9f..d29e2154ce9 100644 --- a/drivers/ram/aspeed/Makefile +++ b/drivers/ram/aspeed/Makefile @@ -2,4 +2,5 @@ # obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o +obj-$(CONFIG_ASPEED_AST2700) += sdram_ast2700.o obj-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += sdram_ast2700.o diff --git a/drivers/ram/aspeed/sdram_ast2700.c b/drivers/ram/aspeed/sdram_ast2700.c index 4a019c4edb1..0cd2d0a479e 100644 --- a/drivers/ram/aspeed/sdram_ast2700.c +++ b/drivers/ram/aspeed/sdram_ast2700.c @@ -14,6 +14,11 @@ #include #include +__weak int fmc_hdr_get_prebuilt(u32 type, u32 *ofst, u32 *size) +{ + return -ENOSYS; +} + enum ddr_type { DDR4_1600 = 0x0, DDR4_2400, @@ -128,13 +133,13 @@ static size_t ast2700_sdrammc_get_vga_mem_size(struct sdrammc *sdrammc) reg = readl(scu0 + SCU0_PCI_MISC70); if (reg & SCU0_PCI_MISC70_EN_PCIEVGA0) { - debug("VGA0:%dMB\n", vga_memsz[sel] / SZ_1M); + debug("VGA0:%zuMB\n", vga_memsz[sel] / SZ_1M); dual++; } reg = readl(scu0 + SCU0_PCI_MISC80); if (reg & SCU0_PCI_MISC80_EN_PCIEVGA1) { - debug("VGA1:%dMB\n", vga_memsz[sel] / SZ_1M); + debug("VGA1:%zuMB\n", vga_memsz[sel] / SZ_1M); dual++; } @@ -560,7 +565,7 @@ void dwc_get_mailbox(struct sdrammc *sdrammc, const int mode, u32 *mbox) dwc_ddrphy_apb_wr(0xd0031, 1); } -uint32_t dwc_readMsgBlock(struct sdrammc *sdrammc, const u32 addr_half) +u32 dwc_readMsgBlock(struct sdrammc *sdrammc, const u32 addr_half) { u32 data_word; @@ -727,7 +732,7 @@ int dwc_ddrphy_phyinit_userCustom_D_loadIMEM(struct sdrammc *sdrammc, const int fmc_hdr_get_prebuilt(pb_type, &imem_ofst, &imem_size); memcpy(sdrammc->phy + (DWC_PHY_IMEM_OFST << 1), - (void *)(0x20000000 + imem_ofst), imem_size); + (void *)(uintptr_t)(0x20000000 + imem_ofst), imem_size); return 0; } @@ -746,7 +751,7 @@ int dwc_ddrphy_phyinit_userCustom_F_loadDMEM(struct sdrammc *sdrammc, fmc_hdr_get_prebuilt(pb_type, &dmem_ofst, &dmem_size); memcpy(sdrammc->phy + (DWC_PHY_DMEM_OFST << 1), - (void *)(0x20000000 + dmem_ofst), dmem_size); + (void *)(uintptr_t)(0x20000000 + dmem_ofst), dmem_size); return 0; } -- cgit v1.3.1 From 1537ec5ceb7d80edaefb55743bb44e17f303285b Mon Sep 17 00:00:00 2001 From: Naveen Kumar Chaudhary Date: Wed, 10 Jun 2026 22:38:40 +0530 Subject: rtc: mcfrtc: fix leap year calculation using wrong variable The leap year check in rtc_set() passes the loop variable 'i' (month index, always 1 when the condition is true) to isleap() instead of the actual year. Since isleap(1) is always false, February 29th is never accounted for when computing the day count, resulting in the RTC being set one day behind for any date after February in a leap year. Pass tmp->tm_year to isleap() so the leap day is correctly included. Fixes: 8e585f02f82 ("Added M5329AFEE and M5329BFEE Platforms") Signed-off-by: Naveen Kumar Chaudhary --- drivers/rtc/mcfrtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/rtc/mcfrtc.c b/drivers/rtc/mcfrtc.c index 9708971c5c4..23ffb2b31a1 100644 --- a/drivers/rtc/mcfrtc.c +++ b/drivers/rtc/mcfrtc.c @@ -73,7 +73,7 @@ int rtc_set(struct rtc_time *tmp) days += month_days[i]; if (i == 1) - days += isleap(i); + days += isleap(tmp->tm_year); } days += tmp->tm_mday - 1; -- cgit v1.3.1 From 4a0990218aa9185c2ccd7986dc1ad14b24aaaa9d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Jun 2026 03:59:06 +0200 Subject: cros_ec: Convert dm_cros_ec_get_ops into an inline function and constify dm_cros_ec_ops Convert dm_cros_ec_get_ops into an inline function to improve compiler code coverage, and constify struct dm_cros_ec_ops in a few places. Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- drivers/misc/cros_ec.c | 9 ++++----- include/cros_ec.h | 7 +++++-- 2 files changed, 9 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index c3e647edfac..e163224b8e3 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -258,7 +258,7 @@ static int send_command_proto3(struct cros_ec_dev *cdev, const void *dout, int dout_len, uint8_t **dinp, int din_len) { - struct dm_cros_ec_ops *ops; + const struct dm_cros_ec_ops *ops; int out_bytes, in_bytes; int rv; @@ -287,7 +287,7 @@ static int send_command(struct cros_ec_dev *dev, uint cmd, int cmd_version, const void *dout, int dout_len, uint8_t **dinp, int din_len) { - struct dm_cros_ec_ops *ops; + const struct dm_cros_ec_ops *ops; int ret = -1; /* Handle protocol version 3 support */ @@ -756,9 +756,8 @@ int cros_ec_flash_protect(struct udevice *dev, uint32_t set_mask, static int cros_ec_check_version(struct udevice *dev) { struct cros_ec_dev *cdev = dev_get_uclass_priv(dev); + const struct dm_cros_ec_ops *ops; struct ec_params_hello req; - - struct dm_cros_ec_ops *ops; int ret; ops = dm_cros_ec_get_ops(dev); @@ -1638,7 +1637,7 @@ int cros_ec_vstore_write(struct udevice *dev, int slot, const uint8_t *data, int cros_ec_get_switches(struct udevice *dev) { - struct dm_cros_ec_ops *ops; + const struct dm_cros_ec_ops *ops; int ret; ops = dm_cros_ec_get_ops(dev); diff --git a/include/cros_ec.h b/include/cros_ec.h index 4ef34815e35..6e5153ceb6a 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -12,6 +12,7 @@ #include #include #include +#include #include /* @@ -316,8 +317,10 @@ struct dm_cros_ec_ops { int (*get_switches)(struct udevice *dev); }; -#define dm_cros_ec_get_ops(dev) \ - ((struct dm_cros_ec_ops *)(dev)->driver->ops) +static inline const struct dm_cros_ec_ops *dm_cros_ec_get_ops(struct udevice *dev) +{ + return (const struct dm_cros_ec_ops *)(dev->driver->ops); +} int cros_ec_register(struct udevice *dev); -- cgit v1.3.1 From d5046398433e48e7b0b664c1ee3e4e2af6f861a8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Jun 2026 04:05:38 +0200 Subject: treewide: Staticize and constify acpi ops Set the acpi_ops structure as static const where applicable. The The structure is not accessible from outside of drivers and is not going to be modified at runtime. The structure may be unused in a couple of drivers depending on their configuration, mark those sites with __maybe_unused . Signed-off-by: Marek Vasut Reviewed-by: Simon Glass --- arch/arm/lib/gic-v2.c | 2 +- arch/arm/lib/gic-v3-its.c | 2 +- arch/x86/cpu/apollolake/cpu.c | 4 +--- arch/x86/cpu/apollolake/hostbridge.c | 2 +- arch/x86/cpu/apollolake/lpc.c | 2 +- arch/x86/cpu/intel_common/generic_wifi.c | 2 +- arch/x86/lib/fsp/fsp_graphics.c | 2 +- board/google/chromebook_coral/coral.c | 2 +- drivers/core/acpi.c | 4 ++-- drivers/core/root.c | 2 +- drivers/cpu/armv8_cpu.c | 2 +- drivers/cpu/bcm283x_cpu.c | 2 +- drivers/gpio/sandbox.c | 4 ++-- drivers/i2c/designware_i2c_pci.c | 2 +- drivers/mmc/pci_mmc.c | 4 ++-- drivers/rtc/sandbox_rtc.c | 2 +- drivers/sound/da7219.c | 2 +- drivers/sound/max98357a.c | 2 +- drivers/tpm/cr50_i2c.c | 2 +- include/dm/device.h | 2 +- test/dm/acpi.c | 2 +- 21 files changed, 24 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/arch/arm/lib/gic-v2.c b/arch/arm/lib/gic-v2.c index b70434a45d4..378bdb54c89 100644 --- a/arch/arm/lib/gic-v2.c +++ b/arch/arm/lib/gic-v2.c @@ -38,7 +38,7 @@ static int acpi_gicv2_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -static struct acpi_ops gic_v2_acpi_ops = { +static const struct acpi_ops gic_v2_acpi_ops = { .fill_madt = acpi_gicv2_fill_madt, }; #endif diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index d11a1ea436e..064b93b2aa1 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -197,7 +197,7 @@ static int acpi_gicv3_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -struct acpi_ops gic_v3_acpi_ops = { +static const struct acpi_ops gic_v3_acpi_ops = { .fill_madt = acpi_gicv3_fill_madt, }; #endif diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c index f480bb1d8c3..d1f592ec57e 100644 --- a/arch/x86/cpu/apollolake/cpu.c +++ b/arch/x86/cpu/apollolake/cpu.c @@ -171,11 +171,9 @@ static int cpu_apl_probe(struct udevice *dev) return 0; } -#ifdef CONFIG_ACPIGEN -struct acpi_ops apl_cpu_acpi_ops = { +static const struct acpi_ops __maybe_unused apl_cpu_acpi_ops = { .fill_ssdt = acpi_cpu_fill_ssdt, }; -#endif static const struct cpu_ops cpu_x86_apl_ops = { .get_desc = cpu_x86_get_desc, diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index 284f16cfd91..360d091121c 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -366,7 +366,7 @@ ulong sa_get_tseg_base(struct udevice *dev) return sa_read_reg(dev, TSEG); } -struct acpi_ops apl_hostbridge_acpi_ops = { +static const struct acpi_ops __maybe_unused apl_hostbridge_acpi_ops = { .get_name = apl_acpi_hb_get_name, #if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) .write_tables = apl_acpi_hb_write_tables, diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c index f34c199bf73..008c4dc0037 100644 --- a/arch/x86/cpu/apollolake/lpc.c +++ b/arch/x86/cpu/apollolake/lpc.c @@ -119,7 +119,7 @@ static int apl_acpi_lpc_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "LPCB"); } -struct acpi_ops apl_lpc_acpi_ops = { +static const struct acpi_ops __maybe_unused apl_lpc_acpi_ops = { .get_name = apl_acpi_lpc_get_name, #ifdef CONFIG_GENERATE_ACPI_TABLE .write_tables = intel_southbridge_write_acpi_tables, diff --git a/arch/x86/cpu/intel_common/generic_wifi.c b/arch/x86/cpu/intel_common/generic_wifi.c index 75fa4e01d8a..1a24c10ab0b 100644 --- a/arch/x86/cpu/intel_common/generic_wifi.c +++ b/arch/x86/cpu/intel_common/generic_wifi.c @@ -102,7 +102,7 @@ static int intel_wifi_acpi_fill_ssdt(const struct udevice *dev, return 0; } -struct acpi_ops wifi_acpi_ops = { +static const struct acpi_ops wifi_acpi_ops = { .fill_ssdt = intel_wifi_acpi_fill_ssdt, }; diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index ad25020086c..d425e80760b 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -150,7 +150,7 @@ static int fsp_video_acpi_write_tables(const struct udevice *dev, } #endif -struct acpi_ops fsp_video_acpi_ops = { +static const struct acpi_ops __maybe_unused fsp_video_acpi_ops = { #ifdef CONFIG_INTEL_GMA_ACPI .write_tables = fsp_video_acpi_write_tables, #endif diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index b4053fa097d..2bb54d59bb8 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -293,7 +293,7 @@ static int coral_write_acpi_tables(const struct udevice *dev, return 0; } -struct acpi_ops coral_acpi_ops = { +static const struct acpi_ops __maybe_unused coral_acpi_ops = { .write_tables = coral_write_acpi_tables, .inject_dsdt = chromeos_acpi_gpio_generate, }; diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index 6a431171c8d..284fb70b036 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -87,7 +87,7 @@ int acpi_copy_name(char *out_name, const char *name) int acpi_get_name(const struct udevice *dev, char *out_name) { - struct acpi_ops *aops; + const struct acpi_ops *aops; const char *name; int ret; @@ -275,7 +275,7 @@ static int sort_acpi_item_type(struct acpi_ctx *ctx, void *start, acpi_method acpi_get_method(struct udevice *dev, enum method_t method) { - struct acpi_ops *aops; + const struct acpi_ops *aops; aops = device_get_acpi_ops(dev); if (aops) { diff --git a/drivers/core/root.c b/drivers/core/root.c index 1f32f33b295..2aa16d59b69 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -459,7 +459,7 @@ static int root_acpi_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "\\_SB"); } -struct acpi_ops root_acpi_ops = { +static const struct acpi_ops root_acpi_ops = { .get_name = root_acpi_get_name, }; #endif diff --git a/drivers/cpu/armv8_cpu.c b/drivers/cpu/armv8_cpu.c index ed87841b723..337661c23a8 100644 --- a/drivers/cpu/armv8_cpu.c +++ b/drivers/cpu/armv8_cpu.c @@ -124,7 +124,7 @@ int armv8_cpu_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -static struct acpi_ops armv8_cpu_acpi_ops = { +static const struct acpi_ops armv8_cpu_acpi_ops = { .fill_ssdt = armv8_cpu_fill_ssdt, .fill_madt = armv8_cpu_fill_madt, }; diff --git a/drivers/cpu/bcm283x_cpu.c b/drivers/cpu/bcm283x_cpu.c index ad638cd8fff..43e74d1811b 100644 --- a/drivers/cpu/bcm283x_cpu.c +++ b/drivers/cpu/bcm283x_cpu.c @@ -193,7 +193,7 @@ static int bcm_cpu_probe(struct udevice *dev) return ret; } -struct acpi_ops bcm283x_cpu_acpi_ops = { +static const struct acpi_ops __maybe_unused bcm283x_cpu_acpi_ops = { .fill_ssdt = armv8_cpu_fill_ssdt, .fill_madt = armv8_cpu_fill_madt, }; diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index e8f50d815d7..76aff0ed5aa 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -306,7 +306,7 @@ static int sb_gpio_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "GPIO"); } -struct acpi_ops gpio_sandbox_acpi_ops = { +static const struct acpi_ops gpio_sandbox_acpi_ops = { .get_name = sb_gpio_get_name, }; #endif /* ACPIGEN */ @@ -568,7 +568,7 @@ static struct pinctrl_ops sandbox_pinctrl_gpio_ops = { }; #if CONFIG_IS_ENABLED(ACPIGEN) -struct acpi_ops pinctrl_sandbox_acpi_ops = { +static const struct acpi_ops pinctrl_sandbox_acpi_ops = { .get_name = sb_pinctrl_get_name, }; #endif diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index ad4122c2abd..db2706fdb6e 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -168,7 +168,7 @@ static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev, return 0; } -static struct acpi_ops dw_i2c_acpi_ops = { +static const struct acpi_ops dw_i2c_acpi_ops = { .fill_ssdt = dw_i2c_acpi_fill_ssdt, }; diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index d446c55f72b..82e393fd9d6 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -137,11 +137,11 @@ static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev, return 0; } -struct acpi_ops pci_mmc_acpi_ops = { #ifdef CONFIG_ACPIGEN +static const struct acpi_ops pci_mmc_acpi_ops = { .fill_ssdt = pci_mmc_acpi_fill_ssdt, -#endif }; +#endif static const struct udevice_id pci_mmc_match[] = { { .compatible = "intel,apl-sd", .data = TYPE_SD }, diff --git a/drivers/rtc/sandbox_rtc.c b/drivers/rtc/sandbox_rtc.c index 4404501c2f6..1ade5d50b23 100644 --- a/drivers/rtc/sandbox_rtc.c +++ b/drivers/rtc/sandbox_rtc.c @@ -73,7 +73,7 @@ static int sandbox_rtc_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "RTCC"); } -struct acpi_ops sandbox_rtc_acpi_ops = { +static const struct acpi_ops sandbox_rtc_acpi_ops = { .get_name = sandbox_rtc_get_name, }; #endif diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c index 5b9b3f65263..d1d03ae91d4 100644 --- a/drivers/sound/da7219.c +++ b/drivers/sound/da7219.c @@ -170,7 +170,7 @@ static int da7219_acpi_setup_nhlt(const struct udevice *dev, } #endif -struct acpi_ops da7219_acpi_ops = { +static const struct acpi_ops da7219_acpi_ops = { #ifdef CONFIG_ACPIGEN .fill_ssdt = da7219_acpi_fill_ssdt, #ifdef CONFIG_X86 diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c index da56ffdd6bb..47978d4fe27 100644 --- a/drivers/sound/max98357a.c +++ b/drivers/sound/max98357a.c @@ -136,7 +136,7 @@ static int max98357a_acpi_setup_nhlt(const struct udevice *dev, } #endif -struct acpi_ops max98357a_acpi_ops = { +static const struct acpi_ops max98357a_acpi_ops = { #ifdef CONFIG_ACPIGEN .fill_ssdt = max98357a_acpi_fill_ssdt, #ifdef CONFIG_X86 diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c index 14a94f8d4a8..46805eaa013 100644 --- a/drivers/tpm/cr50_i2c.c +++ b/drivers/tpm/cr50_i2c.c @@ -889,7 +889,7 @@ static int cr50_i2c_probe(struct udevice *dev) return 0; } -struct acpi_ops cr50_acpi_ops = { +static const struct acpi_ops cr50_acpi_ops = { .fill_ssdt = cr50_acpi_fill_ssdt, }; diff --git a/include/dm/device.h b/include/dm/device.h index 7bcf6df2892..5d700888503 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -388,7 +388,7 @@ struct driver { const void *ops; /* driver-specific operations */ uint32_t flags; #if CONFIG_IS_ENABLED(ACPIGEN) - struct acpi_ops *acpi_ops; + const struct acpi_ops *acpi_ops; #endif }; diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 2de7983f9ae..293ea0274b5 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -136,7 +136,7 @@ static int testacpi_inject_dsdt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -struct acpi_ops testacpi_ops = { +static const struct acpi_ops testacpi_ops = { .get_name = testacpi_get_name, .write_tables = testacpi_write_tables, .fill_madt = testacpi_fill_madt, -- cgit v1.3.1 From f657eab9bedb0b7ea32857345fffb8c3c68dd6b6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 16:09:09 +0800 Subject: pci: rcar: Use dev_read_addr_index() Use dev_read_addr_index() which supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. While at here, correct the return value check. No functional changes. Signed-off-by: Peng Fan Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260526-devfdt-pci-v1-1-ed7f31d73938@nxp.com Signed-off-by: Neil Armstrong --- drivers/pci/pci-rcar-gen2.c | 7 ++++--- drivers/pci/pci-rcar-gen3.c | 5 +++-- 2 files changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index 08d5c4fbb8b..53cb0916741 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -235,9 +236,9 @@ static int rcar_gen2_pci_of_to_plat(struct udevice *dev) { struct rcar_gen2_pci_priv *priv = dev_get_priv(dev); - priv->cfg_base = devfdt_get_addr_index(dev, 0); - priv->mem_base = devfdt_get_addr_index(dev, 1); - if (!priv->cfg_base || !priv->mem_base) + priv->cfg_base = dev_read_addr_index(dev, 0); + priv->mem_base = dev_read_addr_index(dev, 1); + if (priv->cfg_base == FDT_ADDR_T_NONE || priv->mem_base == FDT_ADDR_T_NONE) return -EINVAL; return 0; diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index d4b4037ce19..1925d968c16 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -391,8 +392,8 @@ static int rcar_gen3_pcie_of_to_plat(struct udevice *dev) { struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev); - priv->regs = devfdt_get_addr_index(dev, 0); - if (!priv->regs) + priv->regs = dev_read_addr_index(dev, 0); + if (priv->regs == FDT_ADDR_T_NONE) return -EINVAL; return 0; -- cgit v1.3.1 From 9b6f2786aafd5247dd748e127ea6a01038b09b42 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 16:09:10 +0800 Subject: pci: mpc85xx: Simplfy code with dev_remap_addr() devfdt_get_addr_ptr() + map_physmem() could be simplifed with devfdt_remap_addr(). But to avoid direct dependency on devfdt_* helpers, use dev_remap_addr(). No functional changes. Signed-off-by: Peng Fan Reviewed-by: Neil Armstrong Reviewed-by: Heiko Schocher Link: https://patch.msgid.link/20260526-devfdt-pci-v1-2-ed7f31d73938@nxp.com Signed-off-by: Neil Armstrong --- drivers/pci/pci_mpc85xx.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c index c07feba7976..96550a9ff8f 100644 --- a/drivers/pci/pci_mpc85xx.c +++ b/drivers/pci/pci_mpc85xx.c @@ -170,13 +170,14 @@ static int mpc85xx_pci_dm_remove(struct udevice *dev) static int mpc85xx_pci_of_to_plat(struct udevice *dev) { struct mpc85xx_pci_priv *priv = dev_get_priv(dev); - fdt_addr_t addr; + void __iomem *addr; - addr = devfdt_get_addr_index(dev, 0); - if (addr == FDT_ADDR_T_NONE) + addr = dev_remap_addr_index(dev, 0); + if (!addr) return -EINVAL; - priv->cfg_addr = (void __iomem *)map_physmem(addr, 0, MAP_NOCACHE); - priv->cfg_data = (void __iomem *)((ulong)priv->cfg_addr + 4); + + priv->cfg_addr = addr; + priv->cfg_data = priv->cfg_addr + 4; return 0; } -- cgit v1.3.1 From 06fdccbcd8b3f5eba2788ce5cf4a5fe39e91783a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 16:09:11 +0800 Subject: pci: dw_mvebu: Use dev_read_addr_x APIs Use dev_read_addr_x APIs which support both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan Reviewed-by: Neil Armstrong Reviewed-by: Stefan Roese Link: https://patch.msgid.link/20260526-devfdt-pci-v1-3-ed7f31d73938@nxp.com Signed-off-by: Neil Armstrong --- drivers/pci/pcie_dw_mvebu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 43b919175c9..5a177478afc 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -565,13 +565,12 @@ static int pcie_dw_mvebu_of_to_plat(struct udevice *dev) struct pcie_dw_mvebu *pcie = dev_get_priv(dev); /* Get the controller base address */ - pcie->ctrl_base = devfdt_get_addr_index_ptr(dev, 0); + pcie->ctrl_base = dev_read_addr_index_ptr(dev, 0); if (!pcie->ctrl_base) return -EINVAL; /* Get the config space base address and size */ - pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1, - &pcie->cfg_size); + pcie->cfg_base = dev_read_addr_size_index_ptr(dev, 1, &pcie->cfg_size); if (!pcie->cfg_base) return -EINVAL; -- cgit v1.3.1 From fc1016d6838b9994083062a42a4ba530a85596cc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 16:09:12 +0800 Subject: pci: imx: Use dev_read_addr_index_ptr() Use dev_read_addr_index_ptr() which support both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes Signed-off-by: Peng Fan Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260526-devfdt-pci-v1-4-ed7f31d73938@nxp.com Signed-off-by: Neil Armstrong --- drivers/pci/pcie_imx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 8d853ecf2c2..c8b8e171e39 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -774,8 +774,8 @@ static int imx_pcie_of_to_plat(struct udevice *dev) { struct imx_pcie_priv *priv = dev_get_priv(dev); - priv->dbi_base = devfdt_get_addr_index_ptr(dev, 0); - priv->cfg_base = devfdt_get_addr_index_ptr(dev, 1); + priv->dbi_base = dev_read_addr_index_ptr(dev, 0); + priv->cfg_base = dev_read_addr_index_ptr(dev, 1); if (!priv->dbi_base || !priv->cfg_base) return -EINVAL; -- cgit v1.3.1 From 57abbbcc945079404ba8e3d4a68c991e3cd92a65 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 26 May 2026 16:09:13 +0800 Subject: pci: layerscape: ep: Use dev APIs Convert the Layerscape PCIe endpoint driver to use device and ofnode-based APIs instead of legacy FDT interfaces. Replace devfdt_get_addr_index_ptr(), fdt_get_named_resource(), fdtdec_get_bool(), and fdtdec_get_int() with their modern counterparts such as dev_read_addr_index_ptr(), dev_read_resource_byname(), dev_read_bool(), and dev_read_s32_default(). Also remove the dependency on gd->fdt_blob and global data access. No functional changes. Signed-off-by: Peng Fan Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260526-devfdt-pci-v1-5-ed7f31d73938@nxp.com Signed-off-by: Neil Armstrong --- drivers/pci/pcie_layerscape.h | 3 ++- drivers/pci/pcie_layerscape_ep.c | 24 +++++++----------------- 2 files changed, 9 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index d5f4930e181..e6d47241e71 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -164,7 +165,7 @@ struct ls_pcie_rc { }; struct ls_pcie_ep { - struct fdt_resource addr_res; + struct resource addr_res; struct ls_pcie *pcie; struct udevice *bus; void __iomem *addr; diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index 3520488b345..b7809857565 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -16,8 +15,6 @@ #include #include "pcie_layerscape.h" -DECLARE_GLOBAL_DATA_PTR; - static void ls_pcie_ep_enable_cfg(struct ls_pcie_ep *pcie_ep) { struct ls_pcie *pcie = pcie_ep->pcie; @@ -250,17 +247,15 @@ static int ls_pcie_ep_probe(struct udevice *dev) pcie_ep->pcie = pcie; - pcie->dbi = devfdt_get_addr_index_ptr(dev, 0); + pcie->dbi = dev_read_addr_index_ptr(dev, 0); if (!pcie->dbi) return -EINVAL; - pcie->ctrl = devfdt_get_addr_index_ptr(dev, 1); + pcie->ctrl = dev_read_addr_index_ptr(dev, 1); if (!pcie->ctrl) return -EINVAL; - ret = fdt_get_named_resource(gd->fdt_blob, dev_of_offset(dev), - "reg", "reg-names", - "addr_space", &pcie_ep->addr_res); + ret = dev_read_resource_byname(dev, "addr_space", &pcie_ep->addr_res); if (ret) { printf("%s: resource \"addr_space\" not found\n", dev->name); return ret; @@ -273,8 +268,7 @@ static int ls_pcie_ep_probe(struct udevice *dev) if (!is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx))) return 0; - pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), - "big-endian"); + pcie->big_endian = dev_read_bool(dev, "big-endian"); svr = SVR_SOC_VER(get_svr()); @@ -294,13 +288,9 @@ static int ls_pcie_ep_probe(struct udevice *dev) if (pcie->mode != PCI_HEADER_TYPE_NORMAL) return 0; - pcie_ep->max_functions = fdtdec_get_int(gd->fdt_blob, - dev_of_offset(dev), - "max-functions", 1); - pcie_ep->num_ib_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "num-ib-windows", 8); - pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "num-ob-windows", 8); + pcie_ep->max_functions = dev_read_s32_default(dev, "max-functions", 1); + pcie_ep->num_ib_wins = dev_read_s32_default(dev, "num-ib-windows", 8); + pcie_ep->num_ob_wins = dev_read_s32_default(dev, "num-ob-windows", 8); printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, "Endpoint"); -- cgit v1.3.1 From e800cc67f5b6cb50a20f37c993ec1cd4063bdbd3 Mon Sep 17 00:00:00 2001 From: Vincent Jardin Date: Wed, 20 May 2026 17:00:21 +0200 Subject: mtd: spi-nor: Add gd55lb02gf chips Add the GigaDevice GD55LB02GF (256 Mo) similar to gd55lb02ge with the same read path flags. SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB do not match this chip's status register layout: the GD55LB02GF uses a 5-bit block protect field BP0..BP4 plus a CMP bit in SR2 for direction (see datasheet "Status Register Block Protection"). The generic stm-lock helpers drive only BP0..BP2 and assume SR1 bit 5 is TB, but on this part SR1 bit 5 is BP3. Enabling either flag would leave BP3..BP4 unmanaged or corrupt BP3 on every lock op. A proper support needs a vendor specific lock callback, it is out of scope for this table update. Signed-off-by: Vincent Jardin Suggested-by: Takahiro Kuwano Reviewed-by: Takahiro Kuwano --- drivers/mtd/spi/spi-nor-ids.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index c0fa98424aa..31a2ba49a87 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -231,6 +231,10 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd55lb02gf", 0xc8601c, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ -- cgit v1.3.1 From 93e9af685fefc454580dcf567b03c139a2fe8ebc Mon Sep 17 00:00:00 2001 From: Denis Mukhin Date: Tue, 23 Jun 2026 15:06:30 -0700 Subject: test: bootdev: scan with a broken high-priority device Add bootdev_hunt_fallthrough() test to verify that 'bootflow scan -l' falls back to a lower-priority bootdev when a higher-priority hunter fails. Introduce a simple 'sandbox-bootdev' device for the test. The new bootdev can be configured to produce an error at the hunting stage. Introduce new host_set_flags_by_label() API and a flags field to 'host_sb_plat' to simulate a bootdev hunter failure for the test. Adjust boot{dev,flow} tests which depend on bootdev hunters. Signed-off-by: Denis Mukhin Reviewed-by: Simon Glass --- drivers/block/Makefile | 2 +- drivers/block/host-uclass.c | 15 +++++++++ drivers/block/sandbox-bootdev.c | 73 +++++++++++++++++++++++++++++++++++++++++ include/sandbox_host.h | 18 ++++++++++ test/boot/bootdev.c | 23 ++++++------- test/boot/bootflow.c | 47 ++++++++++++++++++++++++++ test/boot/bootstd_common.h | 5 ++- 7 files changed, 170 insertions(+), 13 deletions(-) create mode 100644 drivers/block/sandbox-bootdev.c (limited to 'drivers') diff --git a/drivers/block/Makefile b/drivers/block/Makefile index f5a9d8637a3..c827fa81a2d 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -13,7 +13,7 @@ ifndef CONFIG_XPL_BUILD obj-$(CONFIG_IDE) += ide.o obj-$(CONFIG_RKMTD) += rkmtd.o endif -obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o +obj-$(CONFIG_SANDBOX) += sandbox.o sandbox-bootdev.o host-uclass.o host_dev.o obj-$(CONFIG_$(PHASE_)BLOCK_CACHE) += blkcache.o obj-$(CONFIG_$(PHASE_)BLKMAP) += blkmap.o obj-$(CONFIG_$(PHASE_)BLKMAP) += blkmap_helper.o diff --git a/drivers/block/host-uclass.c b/drivers/block/host-uclass.c index cf42bd1e07a..95b0b0b2ffe 100644 --- a/drivers/block/host-uclass.c +++ b/drivers/block/host-uclass.c @@ -150,6 +150,21 @@ struct udevice *host_find_by_label(const char *label) return NULL; } +int host_set_flags_by_label(const char *label, unsigned int flags) +{ + struct udevice *dev; + struct host_sb_plat *plat; + + dev = host_find_by_label(label); + if (!dev) + return -ENODEV; + + plat = dev_get_plat(dev); + plat->flags = flags; + + return 0; +} + struct udevice *host_get_cur_dev(void) { struct uclass *uc = uclass_find(UCLASS_HOST); diff --git a/drivers/block/sandbox-bootdev.c b/drivers/block/sandbox-bootdev.c new file mode 100644 index 00000000000..15af0c17d1f --- /dev/null +++ b/drivers/block/sandbox-bootdev.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#define LOG_CATEGORY UCLASS_HOST + +#include +#include +#include +#include + +static int sandbox_bootdev_bind(struct udevice *dev) +{ + struct bootdev_uc_plat *ucp = dev_get_uclass_plat(dev); + + ucp->prio = BOOTDEVP_4_SCAN_FAST; + + return 0; +} + +/** + * sandbox_bootdev_hunt() - Hunt host bootdev. + * + * Note, this hunter exists for bootdev testing to simulate a failure + * mode. Do not use as an example of a real hunter. + * + * @info: Hunter details. + * @show: Enable extra printouts. + * + * Returns: 0 if OK, -ve on error (expected by the test) + */ +static int sandbox_bootdev_hunt(struct bootdev_hunter *info, bool show) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + uclass_id_foreach_dev(UCLASS_HOST, dev, uc) { + struct host_sb_plat *plat = dev_get_plat(dev); + + log_debug("hunting %s\n", plat->label); + + if (plat->flags & HOST_FLAG_BROKEN) { + ret = -ETIME; + log_debug("cannot hunt sandbox device '%s': %d\n", + plat->label, ret); + return ret; + } + } + + return 0; +} + +static const struct bootdev_ops sandbox_bootdev_ops = { +}; + +static const struct udevice_id sandbox_bootdev_ids[] = { + { .compatible = "u-boot,bootdev-sandbox" }, + { } +}; + +U_BOOT_DRIVER(sandbox_bootdev) = { + .name = "sandbox_bootdev", + .id = UCLASS_BOOTDEV, + .ops = &sandbox_bootdev_ops, + .bind = sandbox_bootdev_bind, + .of_match = sandbox_bootdev_ids, +}; + +BOOTDEV_HUNTER(sandbox_bootdev_hunter) = { + .prio = BOOTDEVP_4_SCAN_FAST, + .uclass = UCLASS_HOST, + .hunt = sandbox_bootdev_hunt, + .drv = DM_DRIVER_REF(sandbox_bootdev), +}; diff --git a/include/sandbox_host.h b/include/sandbox_host.h index f7a5fc67230..1330358ef7a 100644 --- a/include/sandbox_host.h +++ b/include/sandbox_host.h @@ -8,17 +8,26 @@ #ifndef __SANDBOX_HOST__ #define __SANDBOX_HOST__ +/** + * Device flags. + */ +enum host_platform_flags { + HOST_FLAG_BROKEN = BIT(0), /** Simulate broken device */ +}; + /** * struct host_sb_plat - platform data for a host device * * @label: Label for this device (allocated) * @filename: Name of file this is attached to, or NULL (allocated) * @fd: File descriptor of file, or 0 for none (file is not open) + * @flags: Device flags (e.g. for unit tests). */ struct host_sb_plat { char *label; char *filename; int fd; + unsigned int flags; }; /** @@ -122,4 +131,13 @@ struct udevice *host_get_cur_dev(void); */ void host_set_cur_dev(struct udevice *dev); +/** + * host_set_flags_by_label() - Set the host device test flags + * + * @label: Label of the attachment, e.g. "test1" + * @flags: Device flags + * Returns: 0 if OK, -ve on error + */ +int host_set_flags_by_label(const char *label, unsigned int flags); + #endif /* __SANDBOX_HOST__ */ diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c index 0820bf10ee0..c2eaf0b2c55 100644 --- a/test/boot/bootdev.c +++ b/test/boot/bootdev.c @@ -384,19 +384,19 @@ static int bootdev_test_hunter(struct unit_test_state *uts) ut_assert_nextline(" 2 mmc mmc_bootdev"); ut_assert_nextline(" 4 nvme nvme_bootdev"); ut_assert_nextline(" 4 qfw qfw_bootdev"); + ut_assert_nextline(" 4 host sandbox_bootdev"); ut_assert_nextline(" 4 scsi scsi_bootdev"); ut_assert_nextline(" 4 spi_flash sf_bootdev"); ut_assert_nextline(" 5 usb usb_bootdev"); ut_assert_nextline(" 4 virtio virtio_bootdev"); - ut_assert_nextline("(total hunters: 9)"); + ut_assert_nextline("(total hunters: 10)"); ut_assert_console_end(); ut_assertok(bootdev_hunt("usb1", false)); ut_assert_skip_to_line("Bus usb@1: 5 USB Device(s) found"); ut_assert_console_end(); - /* USB is 8th in the list, so bit 7 */ - ut_asserteq(BIT(7), std->hunters_used); + ut_asserteq(BIT(USB_HUNTER), std->hunters_used); return 0; } @@ -417,7 +417,7 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assert_nextline("Prio Used Uclass Hunter"); ut_assert_nextlinen("----"); ut_assert_nextline(" 6 ethernet eth_bootdev"); - ut_assert_skip_to_line("(total hunters: 9)"); + ut_assert_skip_to_line("(total hunters: 10)"); ut_assert_console_end(); /* Use the MMC hunter and see that it updates */ @@ -425,7 +425,7 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assertok(run_command("bootdev hunt -l", 0)); ut_assert_skip_to_line(" 5 ide ide_bootdev"); ut_assert_nextline(" 2 * mmc mmc_bootdev"); - ut_assert_skip_to_line("(total hunters: 9)"); + ut_assert_skip_to_line("(total hunters: 10)"); ut_assert_console_end(); /* Scan all hunters */ @@ -441,6 +441,7 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assert_nextline("Hunting with: nvme"); ut_assert_nextline("Hunting with: qfw"); + ut_assert_nextline("Hunting with: host"); ut_assert_nextline("Hunting with: scsi"); ut_assert_nextline("scanning bus for devices..."); ut_assert_skip_to_line("Hunting with: spi_flash"); @@ -458,11 +459,12 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assert_nextline(" 2 * mmc mmc_bootdev"); ut_assert_nextline(" 4 * nvme nvme_bootdev"); ut_assert_nextline(" 4 * qfw qfw_bootdev"); + ut_assert_nextline(" 4 * host sandbox_bootdev"); ut_assert_nextline(" 4 * scsi scsi_bootdev"); ut_assert_nextline(" 4 * spi_flash sf_bootdev"); ut_assert_nextline(" 5 * usb usb_bootdev"); ut_assert_nextline(" 4 * virtio virtio_bootdev"); - ut_assert_nextline("(total hunters: 9)"); + ut_assert_nextline("(total hunters: 10)"); ut_assert_console_end(); ut_asserteq(GENMASK(MAX_HUNTER, 0), std->hunters_used); @@ -646,8 +648,7 @@ static int bootdev_test_next_label(struct unit_test_state *uts) ut_asserteq_str("scsi.id0lun0.bootdev", dev->name); ut_asserteq(BOOTFLOW_METHF_SINGLE_UCLASS, mflags); - /* SCSI is 6th in the list, so bit 5 */ - ut_asserteq(BIT(MMC_HUNTER) | BIT(5), std->hunters_used); + ut_asserteq(BIT(MMC_HUNTER) | BIT(SCSI_HUNTER), std->hunters_used); ut_assertok(bootdev_next_label(&iter, &dev, &mflags)); ut_assert_console_end(); @@ -657,7 +658,7 @@ static int bootdev_test_next_label(struct unit_test_state *uts) mflags); /* dhcp: Ethernet is first so bit 0 */ - ut_asserteq(BIT(MMC_HUNTER) | BIT(5) | BIT(0), std->hunters_used); + ut_asserteq(BIT(MMC_HUNTER) | BIT(SCSI_HUNTER) | BIT(0), std->hunters_used); ut_assertok(bootdev_next_label(&iter, &dev, &mflags)); ut_assert_console_end(); @@ -667,7 +668,7 @@ static int bootdev_test_next_label(struct unit_test_state *uts) mflags); /* pxe: Ethernet is first so bit 0 */ - ut_asserteq(BIT(MMC_HUNTER) | BIT(5) | BIT(0), std->hunters_used); + ut_asserteq(BIT(MMC_HUNTER) | BIT(SCSI_HUNTER) | BIT(0), std->hunters_used); mflags = 123; ut_asserteq(-ENODEV, bootdev_next_label(&iter, &dev, &mflags)); @@ -675,7 +676,7 @@ static int bootdev_test_next_label(struct unit_test_state *uts) ut_assert_console_end(); /* no change */ - ut_asserteq(BIT(MMC_HUNTER) | BIT(5) | BIT(0), std->hunters_used); + ut_asserteq(BIT(MMC_HUNTER) | BIT(SCSI_HUNTER) | BIT(0), std->hunters_used); return 0; } diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index 56ee1952357..1cc137c9700 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -19,6 +19,8 @@ #include #ifdef CONFIG_SANDBOX #include +#include +#include #endif #include #include @@ -1532,3 +1534,48 @@ static int bootstd_images(struct unit_test_state *uts) return 0; } BOOTSTD_TEST(bootstd_images, UTF_CONSOLE); + +#if defined(CONFIG_SANDBOX) && defined(CONFIG_BOOTMETH_GLOBAL) +/* + * Check that bootdev scanning does not stop if higher-priority bootdevs + * are failed to be hunted. + */ +static int bootdev_hunt_fallthrough(struct unit_test_state *uts) +{ + struct bootstd_priv *std; + struct udevice *dev; + + ut_assertok(bootstd_get_priv(&std)); + bootstd_test_drop_bootdev_order(uts); + test_set_skip_delays(true); + bootstd_reset_usb(); + console_record_reset_enable(); + + /* + * Create a sandbox block device (BOOTDEVP_4_SCAN_FAST) and mark it as + * broken so that bootdev_hunt_prio() returns an error. + */ + ut_asserteq(0, uclass_id_count(UCLASS_HOST)); + ut_assertok(host_create_device("test", true, DEFAULT_BLKSZ, &dev)); + ut_assertok(host_set_flags_by_label("test", HOST_FLAG_BROKEN)); + ut_asserteq(1, uclass_id_count(UCLASS_HOST)); + + /* + * Scan with hunting. + * The sandbox hunter at priority 4 must fail, but the USB hunter at + * priority 5 must still be reached. + */ + ut_assertok(run_command("bootflow scan -l", 0)); + + ut_assert(!(std->hunters_used & BIT(HOST_HUNTER))); + ut_assert_skip_to_line("Hunting with: host"); + + /* USB was hunted despite the sandbox hunter failure */ + ut_assert(std->hunters_used & BIT(USB_HUNTER)); + ut_assert_skip_to_line("Bus usb@1: 5 USB Device(s) found"); + + return 0; +} +BOOTSTD_TEST(bootdev_hunt_fallthrough, + UTF_DM | UTF_SCAN_FDT | UTF_SF_BOOTDEV | UTF_CONSOLE); +#endif /* CONFIG_SANDBOX */ diff --git a/test/boot/bootstd_common.h b/test/boot/bootstd_common.h index dd769313a84..672917454a3 100644 --- a/test/boot/bootstd_common.h +++ b/test/boot/bootstd_common.h @@ -21,8 +21,11 @@ #define TEST_VERNUM 0x00010002 enum { - MAX_HUNTER = 8, MMC_HUNTER = 2, /* ID of MMC hunter */ + HOST_HUNTER = 5, + SCSI_HUNTER = 6, + USB_HUNTER = 8, + MAX_HUNTER = 9, }; struct unit_test_state; -- cgit v1.3.1 From d74dea04e3a15d38d6139776cdda99c376e9e3e9 Mon Sep 17 00:00:00 2001 From: Vincent Jardin Date: Thu, 2 Jul 2026 17:09:49 +0200 Subject: gpio: mpc8xxx: add set_flags/get_flags ops mpc8xxx_gpio_open_drain_on() / _off() helpers can program GPODR (open-drain enable) on QorIQ silicon, but they are not called. The open-drain capability is therefore unreachable from the GPIO uclass. Adding a set_flags op for the GPIOD_OPEN_DRAIN, plus a get_flags for the reports of state by reading GPDIR and GPODR back. For existing callers, it is unchanged: direction_input, direction_output, get_value, set_value and get_function still drive the same registers as before. The new ops only become observable when a caller explicitly asks for the GPIOD_OPEN_DRAIN flag (or queries flags via the uclass). Signed-off-by: Vincent Jardin Signed-off-by: Peng Fan --- drivers/gpio/mpc8xxx_gpio.c | 54 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'drivers') diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index 709d04017d1..40646407369 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -171,6 +171,58 @@ static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio) return dir ? GPIOF_OUTPUT : GPIOF_INPUT; } +static int mpc8xxx_gpio_set_flags(struct udevice *dev, uint gpio, + ulong flags) +{ + u32 mask = gpio_mask(gpio); + int ret; + + /* The QorIQ GPIO pad supports open-drain only; open-source has + * no silicon counterpart, so reject it rather than silently + * pretending. + */ + if (flags & GPIOD_OPEN_SOURCE) + return -EOPNOTSUPP; + + /* GPODR is per-pin and meaningful in both directions (it stays + * latched when the pin is re-purposed), so apply it before the + * direction change. + */ + if (flags & GPIOD_OPEN_DRAIN) + mpc8xxx_gpio_open_drain_on(dev, mask); + else + mpc8xxx_gpio_open_drain_off(dev, mask); + + if (flags & GPIOD_IS_OUT) { + ret = mpc8xxx_gpio_direction_output(dev, gpio, + !!(flags & GPIOD_IS_OUT_ACTIVE)); + } else if (flags & GPIOD_IS_IN) { + ret = mpc8xxx_gpio_direction_input(dev, gpio); + } else { + ret = 0; + } + + return ret; +} + +static int mpc8xxx_gpio_get_flags(struct udevice *dev, uint gpio, + ulong *flagsp) +{ + u32 mask = gpio_mask(gpio); + ulong flags = 0; + + if (mpc8xxx_gpio_get_dir(dev, mask)) + flags |= GPIOD_IS_OUT; + else + flags |= GPIOD_IS_IN; + + if (mpc8xxx_gpio_open_drain_val(dev, mask)) + flags |= GPIOD_OPEN_DRAIN; + + *flagsp = flags; + return 0; +} + #if CONFIG_IS_ENABLED(OF_CONTROL) static int mpc8xxx_gpio_of_to_plat(struct udevice *dev) { @@ -255,6 +307,8 @@ static const struct dm_gpio_ops gpio_mpc8xxx_ops = { .get_value = mpc8xxx_gpio_get_value, .set_value = mpc8xxx_gpio_set_value, .get_function = mpc8xxx_gpio_get_function, + .set_flags = mpc8xxx_gpio_set_flags, + .get_flags = mpc8xxx_gpio_get_flags, }; static const struct udevice_id mpc8xxx_gpio_ids[] = { -- cgit v1.3.1 From 69879030f70d96f02018c923ea740e00bc9cbca4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Jun 2026 04:40:23 +0200 Subject: crypto: fsl: Hide CAAM_64BIT symbol behind FSL_CAAM Make CAAM_64BIT selectable only in case FSL_CAAM is selected, otherwise CAAM_64BIT shows up in configs of unrelated platforms. Signed-off-by: Marek Vasut Reviewed-by: Tom Rini Reviewed-by: Peng Fan Reviewed-by: Heiko Schocher Signed-off-by: Peng Fan --- drivers/crypto/fsl/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 1398b0033f0..244a9bd905d 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -20,6 +20,7 @@ config SYS_FSL_MAX_NUM_OF_SEC config CAAM_64BIT bool + depends on FSL_CAAM default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8 help Select Crypto driver for 64 bits CAAM version -- cgit v1.3.1 From c9beb84a376853078e62f385447672fc7e8cd819 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 9 Jun 2026 11:54:32 +0800 Subject: power: domain: scmi: Allow failure in getting power domain attribute When one power domain fails to get attribute, continue getting attribute for remaining power domains, not return probe failure. So other power domains are still functional. It is possible that one power domain is assigned to other agent or this power domain is disabled by HW fuse, so platform returns denied or other error. Signed-off-by: Ye Li Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/power/domain/scmi-power-domain.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/power/domain/scmi-power-domain.c b/drivers/power/domain/scmi-power-domain.c index 6dcc259ad8f..a369fe52f2f 100644 --- a/drivers/power/domain/scmi-power-domain.c +++ b/drivers/power/domain/scmi-power-domain.c @@ -165,15 +165,9 @@ static int scmi_power_domain_probe(struct udevice *dev) for (i = 0; i < priv->num_pwdoms; i++) { ret = scmi_pwd_attrs(dev, i, &priv->prop[i].attributes, &priv->prop[i].name); - if (ret) { + if (ret) dev_err(dev, "failed to get attributes pwd:%d (%d)\n", i, ret); - for (i--; i >= 0; i--) - free(priv->prop[i].name); - free(priv->prop); - - return ret; - } } return 0; -- cgit v1.3.1