From f4aa24af69272824578e76d4f7da8d65d1a088d9 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 28 Jul 2025 12:25:29 +0100 Subject: arm: socfpga: Remove unnecessary for loop The for loop in fpgamgr_program_poll_cd will always terminate after a single pass and so is not necessary. Remove it and all related code and leave only the code that is effective. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/fpga/socfpga_gen5.c | 25 ++++++------------------- 1 file changed, 6 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c index 9473f057328..964a5cc8789 100644 --- a/drivers/fpga/socfpga_gen5.c +++ b/drivers/fpga/socfpga_gen5.c @@ -119,27 +119,14 @@ static int fpgamgr_program_poll_cd(void) { const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK | FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK; - unsigned long reg, i; + unsigned long reg; - /* (3) wait until full config done */ - for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { - reg = readl(&fpgamgr_regs->gpio_ext_porta); - - /* Config error */ - if (!(reg & mask)) { - printf("FPGA: Configuration error.\n"); - return -3; - } - - /* Config done without error */ - if (reg & mask) - break; - } + reg = readl(&fpgamgr_regs->gpio_ext_porta); - /* Timeout happened, return error */ - if (i == FPGA_TIMEOUT_CNT) { - printf("FPGA: Timeout waiting for program.\n"); - return -4; + /* Config error */ + if (!(reg & mask)) { + printf("FPGA: Configuration error.\n"); + return -3; } /* Disable AXI configuration */ -- cgit v1.3.1 From dff25bb4abd082e852108b04beba0685a2980aaa Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Wed, 23 Jul 2025 12:32:31 +0100 Subject: clk: n5x: Fix misplaced paren Smatch reported an issue about the precedence of shift being higher than mask in clk_get_emac_clk_hz. This turned out to be a misplaced paren in one of the calculations. Fix this by placing the paren in the same place as in the other similar calculations in the same function. Signed-off-by: Andrew Goodbody --- drivers/clk/altera/clk-n5x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c index 09db250ab6d..9e4e7a1d908 100644 --- a/drivers/clk/altera/clk-n5x.c +++ b/drivers/clk/altera/clk-n5x.c @@ -386,8 +386,8 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id) } else { clock /= 1 + ((CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) & - CLKMGR_PLLOUTDIV_C3CNT_MASK >> - CLKMGR_PLLOUTDIV_C3CNT_OFFSET)); + CLKMGR_PLLOUTDIV_C3CNT_MASK) >> + CLKMGR_PLLOUTDIV_C3CNT_OFFSET); } break; -- cgit v1.3.1 From 5a13fa7c66dabcf84438601663f7f1cb7fcc8cca Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Thu, 24 Jul 2025 16:19:24 +0100 Subject: ddr: altera: n5x: size_t cannot be less than 0 The function socfpga_get_handoff_size returns an int so make the struct fields used to accept the return value also an int so that testing for less than 0 is then valid. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/ddr/altera/sdram_n5x.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index d1fc93b6bdd..17ec6afa82b 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -346,25 +346,25 @@ struct ddr_handoff { phys_addr_t cntlr_base; size_t cntlr_total_length; enum ddr_type cntlr_t; - size_t cntlr_handoff_length; + int cntlr_handoff_length; /* Second controller attributes*/ phys_addr_t cntlr2_handoff_base; phys_addr_t cntlr2_base; size_t cntlr2_total_length; enum ddr_type cntlr2_t; - size_t cntlr2_handoff_length; + int cntlr2_handoff_length; /* PHY attributes */ phys_addr_t phy_handoff_base; phys_addr_t phy_base; size_t phy_total_length; - size_t phy_handoff_length; + int phy_handoff_length; /* PHY engine attributes */ phys_addr_t phy_engine_handoff_base; size_t phy_engine_total_length; - size_t phy_engine_handoff_length; + int phy_engine_handoff_length; /* Calibration attributes */ phys_addr_t train_imem_base; -- cgit v1.3.1 From 6e1cc5d861d388f5699859bac481822029881738 Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Tue, 29 Jul 2025 12:50:47 +0100 Subject: socfpga_dtreg: Ensure reg is initialised before use In socfpga_dtreg_probe it is possible that if mask is 0 then reg will not be assigned to before first use. Refactor the code slightly to ensure that reg is always assigned to and remove a piece of duplicated code. This issue was found by Smatch. Signed-off-by: Andrew Goodbody --- drivers/misc/socfpga_dtreg.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/misc/socfpga_dtreg.c b/drivers/misc/socfpga_dtreg.c index ea5d0bcdf51..dd6809433e3 100644 --- a/drivers/misc/socfpga_dtreg.c +++ b/drivers/misc/socfpga_dtreg.c @@ -76,16 +76,15 @@ static int socfpga_dtreg_probe(struct udevice *dev) return -EINVAL; } + reg = base + offset; + if (mask != 0) { if (mask == 0xffffffff) { - reg = base + offset; writel(val, (uintptr_t)reg); } else { /* Mask the value with the masking bits */ set_mask = val & mask; - reg = base + offset; - /* Clears and sets specific bits in the register */ clrsetbits_le32((uintptr_t)reg, mask, set_mask); } -- cgit v1.3.1 From 9f689086863dfae693551a68fc9dc426bca5727e Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Thu, 12 Jun 2025 01:08:00 -0700 Subject: arch: arm: agilex5: Enable power manager for Agilex5 Agilex5 FSBL is required to disable the power of unused peripheral SRAM blocks to reduce power consumption. Introducing a new power manager driver for Agilex5 which will be called as part of Agilex5 SPL initialization process. This driver will read the peripheral handoff data obtained from the bitstream and will power off the specified peripheral's SRAM from the handoff data values. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- MAINTAINERS | 1 + arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 6 ++ arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 1 + arch/arm/mach-socfpga/spl_agilex5.c | 6 ++ configs/socfpga_agilex5_defconfig | 2 + .../power/altr,pmgr-agilex5.yaml | 39 +++++++ drivers/power/domain/Kconfig | 8 ++ drivers/power/domain/Makefile | 1 + drivers/power/domain/altr-pmgr-agilex5.c | 112 +++++++++++++++++++++ 9 files changed, 176 insertions(+) create mode 100644 doc/device-tree-bindings/power/altr,pmgr-agilex5.yaml create mode 100644 drivers/power/domain/altr-pmgr-agilex5.c (limited to 'drivers') diff --git a/MAINTAINERS b/MAINTAINERS index c4eaba58a90..795ff2328dd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -156,6 +156,7 @@ M: Tingting Meng S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git F: drivers/ddr/altera/ +F: drivers/power/domain/altr-pmgr-agilex5.c F: arch/arm/mach-socfpga/ F: configs/socfpga_agilex5_vab_defconfig F: drivers/sysreset/sysreset_socfpga* diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 874e71b5ca4..402f0bec173 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -668,6 +668,12 @@ bootph-all; }; }; + + pwrmgr: pwrmgr@10d14000 { + compatible = "altr,pmgr-agilex5"; + reg = <0x10d14000 0x100>; + bootph-all; + }; }; }; diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 763b077d8c1..04203cceb8a 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -68,6 +68,7 @@ #define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620) +#define SOC64_HANDOFF_PERI_LEN 1 #define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634) #define SOC64_HANDOFF_SDRAM_LEN 5 #endif diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c index a9aad5350d2..2a13301802d 100644 --- a/arch/arm/mach-socfpga/spl_agilex5.c +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -96,6 +96,12 @@ void board_init_f(ulong dummy) hang(); } + ret = uclass_get_device(UCLASS_POWER_DOMAIN, 0, &dev); + if (ret) { + debug("PSS SRAM power-off failed: %d\n", ret); + hang(); + } + if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) { ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 33a6221979a..7dbb1b4aa4e 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -103,3 +103,5 @@ CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_AGILEX5_PMGR_POWER_DOMAIN=y diff --git a/doc/device-tree-bindings/power/altr,pmgr-agilex5.yaml b/doc/device-tree-bindings/power/altr,pmgr-agilex5.yaml new file mode 100644 index 00000000000..af7aeaa922c --- /dev/null +++ b/doc/device-tree-bindings/power/altr,pmgr-agilex5.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/altr,pmgr-agilex5.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Altera Agilex5 Power Manager + +maintainers: + - name: Alif Zakuan Yuslaimi + email: alif.zakuan.yuslaimi@altera.com + +description: | + This controller will read the peripheral handoff data obtained from the + bitstream and will power gate the specified peripheral's SRAM from the + handoff data values to reduce power consumption. + +properties: + compatible: + const: "altr,pmgr-agilex5" + + reg: + maxItems: 1 + + bootph-all: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pwrmgr: pwrmgr@10d14000 { + compatible = "altr,pmgr-agilex5"; + reg = <0x10d14000 0x100>; + bootph-all; + }; diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 5f5218bd8b5..ebf5d828cb0 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -18,6 +18,14 @@ config APPLE_PMGR_POWER_DOMAIN This driver is needed to power on parts of the SoC that have not been powered on by previous boot stages. +config AGILEX5_PMGR_POWER_DOMAIN + bool "Enable the Agilex5 PMGR power domain driver" + depends on SPL_POWER_DOMAIN + help + Enable support for power gating peripherals' SRAM specified in + the handoff data values obtained from the bitstream to reduce + power consumption. + config BCM6328_POWER_DOMAIN bool "Enable the BCM6328 power domain driver" depends on POWER_DOMAIN && ARCH_BMIPS diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index 4d20c97d26c..8e03f620437 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_$(PHASE_)POWER_DOMAIN) += power-domain-uclass.o obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o +obj-$(CONFIG_AGILEX5_PMGR_POWER_DOMAIN) += altr-pmgr-agilex5.o obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o imx8-power-domain.o obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o diff --git a/drivers/power/domain/altr-pmgr-agilex5.c b/drivers/power/domain/altr-pmgr-agilex5.c new file mode 100644 index 00000000000..257e8b234fd --- /dev/null +++ b/drivers/power/domain/altr-pmgr-agilex5.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Altera Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PSS_FWENCTL 0x44 +#define PSS_PGENCTL 0x48 +#define PSS_PGSTAT 0x4c + +#define DATA_MASK GENMASK(7, 0) +#define TIMEOUT_MS 1000 + +static int wait_verify_fsm(u16 timeout_ms, uintptr_t base_addr, u32 peripheral_handoff) +{ + u32 data = 0; + u32 pgstat = 0; + ulong start = get_timer(0); + + /* Wait FSM ready */ + do { + data = FIELD_GET(DATA_MASK, readl(base_addr + PSS_PGSTAT)); + if (data != 0) + break; + } while (get_timer(start) < timeout_ms); + + if (get_timer(start) >= timeout_ms) + return -ETIMEDOUT; + + /* Verify PSS SRAM power gated */ + pgstat = FIELD_GET(DATA_MASK, readl(base_addr + PSS_PGSTAT)); + if (pgstat != FIELD_GET(DATA_MASK, peripheral_handoff)) + return -EPERM; + + return 0; +} + +static int pss_sram_power_off(uintptr_t base_addr, u32 *handoff_table) +{ + u32 peripheral_handoff; + + /* Get PSS SRAM handoff data */ + peripheral_handoff = handoff_table[0]; + + /* Enable firewall for PSS SRAM */ + setbits_le32(base_addr + PSS_FWENCTL, peripheral_handoff); + + /* Wait */ + udelay(1); + + /* Power gating PSS SRAM */ + setbits_le32(base_addr + PSS_PGENCTL, peripheral_handoff); + + return wait_verify_fsm(TIMEOUT_MS, base_addr, peripheral_handoff); +} + +static int altera_pmgr_off(struct power_domain *power_domain) +{ + fdt_addr_t base_addr = dev_read_addr(power_domain->dev); + u32 handoff_table[SOC64_HANDOFF_PERI_LEN]; + int ret; + + /* Read handoff data for peripherals configuration */ + ret = socfpga_handoff_read((void *)SOC64_HANDOFF_PERI, handoff_table, + SOC64_HANDOFF_PERI_LEN); + if (ret) { + debug("%s: handoff data read failed. ret: %d\n", __func__, ret); + return ret; + } + + pss_sram_power_off(base_addr, handoff_table); + + return 0; +} + +static int altera_pmgr_probe(struct udevice *dev) +{ + struct power_domain *power_domain = dev_get_priv(dev); + + if (!power_domain) + return -EINVAL; + + power_domain->dev = dev; + + return altera_pmgr_off(power_domain); +} + +static const struct udevice_id altera_pmgr_ids[] = { + { .compatible = "altr,pmgr-agilex5" }, + { /* sentinel */ } +}; + +static struct power_domain_ops altera_pmgr_ops = { + .off = altera_pmgr_off, +}; + +U_BOOT_DRIVER(altr_pmgr) = { + .name = "altr_pmgr", + .id = UCLASS_POWER_DOMAIN, + .of_match = altera_pmgr_ids, + .ops = &altera_pmgr_ops, + .probe = altera_pmgr_probe, + .priv_auto = sizeof(struct power_domain), +}; -- cgit v1.3.1