From 9d7add8ac918a9610ca856f58a0dbf849ae6d15f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 2 Aug 2022 07:33:36 -0400 Subject: net: lpc32xx_eth.c ethernet driver This driver has not been converted to DM_ETH. The migration deadline passed 2 years ago. Cc: Trevor Woerner Signed-off-by: Tom Rini Acked-by: Ramon Fried --- drivers/net/Kconfig | 5 - drivers/net/Makefile | 1 - drivers/net/lpc32xx_eth.c | 651 ---------------------------------------------- 3 files changed, 657 deletions(-) delete mode 100644 drivers/net/lpc32xx_eth.c (limited to 'drivers') diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 53742b29041..4c1e1a77bb3 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -455,11 +455,6 @@ config KSZ9477 This driver implements a DSA switch driver for the KSZ9477 family of GbE switches using the I2C interface. -config LPC32XX_ETH - bool "LPC32xx Ethernet MAC interface driver" - depends on ARCH_LPC32XX - default y - config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 7b550635279..96b7678e988 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_KSZ9477) += ksz9477.o -obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c deleted file mode 100644 index 1a573434393..00000000000 --- a/drivers/net/lpc32xx_eth.c +++ /dev/null @@ -1,651 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * LPC32xx Ethernet MAC interface driver - * - * (C) Copyright 2014 DENX Software Engineering GmbH - * Written-by: Albert ARIBAUD - 3ADEV - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Notes: - * - * 1. Unless specified otherwise, all references to tables or paragraphs - * are to UM10326, "LPC32x0 and LPC32x0/01 User manual". - * - * 2. Only bitfield masks/values which are actually used by the driver - * are defined. - */ - -/* a single RX descriptor. The controller has an array of these */ -struct lpc32xx_eth_rxdesc { - u32 packet; /* Receive packet pointer */ - u32 control; /* Descriptor command status */ -}; - -#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc)) - -/* RX control bitfields/masks (see Table 330) */ -#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF -#define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800 -#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000 - -/* a single RX status. The controller has an array of these */ -struct lpc32xx_eth_rxstat { - u32 statusinfo; /* Transmit Descriptor status */ - u32 statushashcrc; /* Transmit Descriptor CRCs */ -}; - -#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat)) - -/* RX statusinfo bitfields/masks (see Table 333) */ -#define RX_STAT_RXSIZE 0x000007FF -/* Helper: OR of all errors except RANGE */ -#define RX_STAT_ERRORS 0x1B800000 - -/* a single TX descriptor. The controller has an array of these */ -struct lpc32xx_eth_txdesc { - u32 packet; /* Transmit packet pointer */ - u32 control; /* Descriptor control */ -}; - -#define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc)) - -/* TX control bitfields/masks (see Table 335) */ -#define TX_CTRL_TXSIZE 0x000007FF -#define TX_CTRL_LAST 0x40000000 - -/* a single TX status. The controller has an array of these */ -struct lpc32xx_eth_txstat { - u32 statusinfo; /* Transmit Descriptor status */ -}; - -#define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat)) - -/* Ethernet MAC interface registers (see Table 283) */ -struct lpc32xx_eth_registers { - /* MAC registers - 0x3106_0000 to 0x3106_01FC */ - u32 mac1; /* MAC configuration register 1 */ - u32 mac2; /* MAC configuration register 2 */ - u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */ - u32 ipgr; /* Non-back-to-back IPG register */ - u32 clrt; /* Collision Window / Retry register */ - u32 maxf; /* Maximum Frame register */ - u32 supp; /* Phy Support register */ - u32 test; - u32 mcfg; /* MII management configuration reg. */ - u32 mcmd; /* MII management command register */ - u32 madr; /* MII management address register */ - u32 mwtd; /* MII management wite data register */ - u32 mrdd; /* MII management read data register */ - u32 mind; /* MII management indicators register */ - u32 reserved1[2]; - u32 sa0; /* Station address register 0 */ - u32 sa1; /* Station address register 1 */ - u32 sa2; /* Station address register 2 */ - u32 reserved2[45]; - /* Control registers */ - u32 command; - u32 status; - u32 rxdescriptor; - u32 rxstatus; - u32 rxdescriptornumber; /* actually, number MINUS ONE */ - u32 rxproduceindex; /* head of rx desc fifo */ - u32 rxconsumeindex; /* tail of rx desc fifo */ - u32 txdescriptor; - u32 txstatus; - u32 txdescriptornumber; /* actually, number MINUS ONE */ - u32 txproduceindex; /* head of rx desc fifo */ - u32 txconsumeindex; /* tail of rx desc fifo */ - u32 reserved3[10]; - u32 tsv0; /* Transmit status vector register 0 */ - u32 tsv1; /* Transmit status vector register 1 */ - u32 rsv; /* Receive status vector register */ - u32 reserved4[3]; - u32 flowcontrolcounter; - u32 flowcontrolstatus; - u32 reserved5[34]; - /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */ - u32 rxfilterctrl; - u32 rxfilterwolstatus; - u32 rxfilterwolclear; - u32 reserved6; - u32 hashfilterl; - u32 hashfilterh; - u32 reserved7[882]; - /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */ - u32 intstatus; /* Interrupt status register */ - u32 intenable; - u32 intclear; - u32 intset; - u32 reserved8; - u32 powerdown; - u32 reserved9; -}; - -/* MAC1 register bitfields/masks and offsets (see Table 283) */ -#define MAC1_RECV_ENABLE 0x00000001 -#define MAC1_PASS_ALL_RX_FRAMES 0x00000002 -#define MAC1_SOFT_RESET 0x00008000 -/* Helper: general reset */ -#define MAC1_RESETS 0x0000CF00 - -/* MAC2 register bitfields/masks and offsets (see Table 284) */ -#define MAC2_FULL_DUPLEX 0x00000001 -#define MAC2_CRC_ENABLE 0x00000010 -#define MAC2_PAD_CRC_ENABLE 0x00000020 - -/* SUPP register bitfields/masks and offsets (see Table 290) */ -#define SUPP_SPEED 0x00000100 - -/* MCFG register bitfields/masks and offsets (see Table 292) */ -#define MCFG_RESET_MII_MGMT 0x00008000 -/* divide clock by 28 (see Table 293) */ -#define MCFG_CLOCK_SELECT_DIV28 0x0000001C - -/* MADR register bitfields/masks and offsets (see Table 295) */ -#define MADR_REG_MASK 0x0000001F -#define MADR_PHY_MASK 0x00001F00 -#define MADR_REG_OFFSET 0 -#define MADR_PHY_OFFSET 8 - -/* MIND register bitfields/masks (see Table 298) */ -#define MIND_BUSY 0x00000001 - -/* COMMAND register bitfields/masks and offsets (see Table 283) */ -#define COMMAND_RXENABLE 0x00000001 -#define COMMAND_TXENABLE 0x00000002 -#define COMMAND_PASSRUNTFRAME 0x00000040 -#define COMMAND_RMII 0x00000200 -#define COMMAND_FULL_DUPLEX 0x00000400 -/* Helper: general reset */ -#define COMMAND_RESETS 0x00000038 - -/* STATUS register bitfields/masks and offsets (see Table 283) */ -#define STATUS_RXSTATUS 0x00000001 -#define STATUS_TXSTATUS 0x00000002 - -/* RXFILTERCTRL register bitfields/masks (see Table 319) */ -#define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002 -#define RXFILTERCTRL_ACCEPTPERFECT 0x00000020 - -/* Buffers and descriptors */ - -#define ATTRS(n) __aligned(n) - -#define TX_BUF_COUNT 4 -#define RX_BUF_COUNT 4 - -struct lpc32xx_eth_buffers { - ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT]; - ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT]; - ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN]; - ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT]; - ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT]; - ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN]; -}; - -/* port device data struct */ -struct lpc32xx_eth_device { - struct eth_device dev; - struct lpc32xx_eth_registers *regs; - struct lpc32xx_eth_buffers *bufs; - bool phy_rmii; -}; - -#define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device)) - -/* generic macros */ -#define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev) - -/* timeout for MII polling */ -#define MII_TIMEOUT 10000000 - -/* limits for PHY and register addresses */ -#define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET) - -#define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET) - -#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -/* - * mii_reg_read - miiphy_read callback function. - * - * Returns 16bit phy register value, or 0xffff on error - */ -static int mii_reg_read(struct mii_dev *bus, int phy_adr, int devad, - int reg_ofs) -{ - u16 data = 0; - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); - struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; - u32 mind_reg; - u32 timeout; - - /* check parameters */ - if (phy_adr > MII_MAX_PHY) { - printf("%s:%u: Invalid PHY address %d\n", - __func__, __LINE__, phy_adr); - return -EFAULT; - } - if (reg_ofs > MII_MAX_REG) { - printf("%s:%u: Invalid register offset %d\n", - __func__, __LINE__, reg_ofs); - return -EFAULT; - } - - /* write the phy and reg addressse into the MII address reg */ - writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), - ®s->madr); - - /* write 1 to the MII command register to cause a read */ - writel(1, ®s->mcmd); - - /* wait till the MII is not busy */ - timeout = MII_TIMEOUT; - do { - /* read MII indicators register */ - mind_reg = readl(®s->mind); - if (--timeout == 0) - break; - } while (mind_reg & MIND_BUSY); - - /* write 0 to the MII command register to finish the read */ - writel(0, ®s->mcmd); - - if (timeout == 0) { - printf("%s:%u: MII busy timeout\n", __func__, __LINE__); - return -EFAULT; - } - - data = (u16) readl(®s->mrdd); - - debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr, - reg_ofs, data); - - return data; -} - -/* - * mii_reg_write - imiiphy_write callback function. - * - * Returns 0 if write succeed, -EINVAL on bad parameters - * -ETIME on timeout - */ -static int mii_reg_write(struct mii_dev *bus, int phy_adr, int devad, - int reg_ofs, u16 data) -{ - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); - struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; - u32 mind_reg; - u32 timeout; - - /* check parameters */ - if (phy_adr > MII_MAX_PHY) { - printf("%s:%u: Invalid PHY address %d\n", - __func__, __LINE__, phy_adr); - return -EFAULT; - } - if (reg_ofs > MII_MAX_REG) { - printf("%s:%u: Invalid register offset %d\n", - __func__, __LINE__, reg_ofs); - return -EFAULT; - } - - /* write the phy and reg addressse into the MII address reg */ - writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), - ®s->madr); - - /* write data to the MII write register */ - writel(data, ®s->mwtd); - - /* wait till the MII is not busy */ - timeout = MII_TIMEOUT; - do { - /* read MII indicators register */ - mind_reg = readl(®s->mind); - if (--timeout == 0) - break; - } while (mind_reg & MIND_BUSY); - - if (timeout == 0) { - printf("%s:%u: MII busy timeout\n", __func__, - __LINE__); - return -EFAULT; - } - - /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr, - reg_ofs, data);*/ - - return 0; -} -#endif - -/* - * Provide default Ethernet buffers base address if target did not. - * Locate buffers in SRAM at 0x00001000 to avoid cache issues and - * maximize throughput. - */ -#if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE) -#define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000 -#endif - -static struct lpc32xx_eth_device lpc32xx_eth = { - .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE, - .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE, -#if defined(CONFIG_RMII) - .phy_rmii = true, -#endif -}; - -#define TX_TIMEOUT 10000 - -static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; - int timeout, tx_index; - - /* time out if transmit descriptor array remains full too long */ - timeout = TX_TIMEOUT; - while ((readl(®s->status) & STATUS_TXSTATUS) && - (readl(®s->txconsumeindex) - == readl(®s->txproduceindex))) { - if (timeout-- == 0) - return -1; - } - - /* determine next transmit packet index to use */ - tx_index = readl(®s->txproduceindex); - - /* set up transmit packet */ - memcpy((void *)&bufs->tx_buf[tx_index * PKTSIZE_ALIGN], - (void *)dataptr, datasize); - writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE), - &bufs->tx_desc[tx_index].control); - writel(0, &bufs->tx_stat[tx_index].statusinfo); - - /* pass transmit packet to DMA engine */ - tx_index = (tx_index + 1) % TX_BUF_COUNT; - writel(tx_index, ®s->txproduceindex); - - /* transmission succeeded */ - return 0; -} - -#define RX_TIMEOUT 1000000 - -static int lpc32xx_eth_recv(struct eth_device *dev) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; - int timeout, rx_index; - - /* time out if receive descriptor array remains empty too long */ - timeout = RX_TIMEOUT; - while (readl(®s->rxproduceindex) == readl(®s->rxconsumeindex)) { - if (timeout-- == 0) - return -1; - } - - /* determine next receive packet index to use */ - rx_index = readl(®s->rxconsumeindex); - - /* if data was valid, pass it on */ - if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) { - net_process_received_packet( - &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]), - (bufs->rx_stat[rx_index].statusinfo - & RX_STAT_RXSIZE) + 1); - } - - /* pass receive slot back to DMA engine */ - rx_index = (rx_index + 1) % RX_BUF_COUNT; - writel(rx_index, ®s->rxconsumeindex); - - /* reception successful */ - return 0; -} - -static int lpc32xx_eth_write_hwaddr(struct eth_device *dev) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - - /* Save station address */ - writel((unsigned long) (dev->enetaddr[0] | - (dev->enetaddr[1] << 8)), ®s->sa2); - writel((unsigned long) (dev->enetaddr[2] | - (dev->enetaddr[3] << 8)), ®s->sa1); - writel((unsigned long) (dev->enetaddr[4] | - (dev->enetaddr[5] << 8)), ®s->sa0); - - return 0; -} - -static int lpc32xx_eth_init(struct eth_device *dev) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; - int index; - - /* Initial MAC initialization */ - writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1); - writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2); - writel(PKTSIZE_ALIGN, ®s->maxf); - - /* Retries: 15 (0xF). Collision window: 57 (0x37). */ - writel(0x370F, ®s->clrt); - - /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */ - writel(0x0012, ®s->ipgr); - - /* pass runt (smaller than 64 bytes) frames */ - if (lpc32xx_eth_device->phy_rmii) - writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, ®s->command); - else - writel(COMMAND_PASSRUNTFRAME, ®s->command); - - /* Configure Full/Half Duplex mode */ - if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) { - setbits_le32(®s->mac2, MAC2_FULL_DUPLEX); - setbits_le32(®s->command, COMMAND_FULL_DUPLEX); - writel(0x15, ®s->ipgt); - } else { - writel(0x12, ®s->ipgt); - } - - /* Configure 100MBit/10MBit mode */ - if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET) - writel(SUPP_SPEED, ®s->supp); - else - writel(0, ®s->supp); - - /* Save station address */ - writel((unsigned long) (dev->enetaddr[0] | - (dev->enetaddr[1] << 8)), ®s->sa2); - writel((unsigned long) (dev->enetaddr[2] | - (dev->enetaddr[3] << 8)), ®s->sa1); - writel((unsigned long) (dev->enetaddr[4] | - (dev->enetaddr[5] << 8)), ®s->sa0); - - /* set up transmit buffers */ - for (index = 0; index < TX_BUF_COUNT; index++) { - bufs->tx_desc[index].control = 0; - bufs->tx_stat[index].statusinfo = 0; - } - writel((u32)(&bufs->tx_desc), (u32 *)®s->txdescriptor); - writel((u32)(&bufs->tx_stat), ®s->txstatus); - writel(TX_BUF_COUNT-1, ®s->txdescriptornumber); - - /* set up receive buffers */ - for (index = 0; index < RX_BUF_COUNT; index++) { - bufs->rx_desc[index].packet = - (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN); - bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1; - bufs->rx_stat[index].statusinfo = 0; - bufs->rx_stat[index].statushashcrc = 0; - } - writel((u32)(&bufs->rx_desc), ®s->rxdescriptor); - writel((u32)(&bufs->rx_stat), ®s->rxstatus); - writel(RX_BUF_COUNT-1, ®s->rxdescriptornumber); - - /* set up transmit buffers */ - for (index = 0; index < TX_BUF_COUNT; index++) - bufs->tx_desc[index].packet = - (u32)(bufs->tx_buf + index * PKTSIZE_ALIGN); - - /* Enable broadcast and matching address packets */ - writel(RXFILTERCTRL_ACCEPTBROADCAST | - RXFILTERCTRL_ACCEPTPERFECT, ®s->rxfilterctrl); - - /* Clear and disable interrupts */ - writel(0xFFFF, ®s->intclear); - writel(0, ®s->intenable); - - /* Enable receive and transmit mode of MAC ethernet core */ - setbits_le32(®s->command, COMMAND_RXENABLE | COMMAND_TXENABLE); - setbits_le32(®s->mac1, MAC1_RECV_ENABLE); - - /* - * Perform a 'dummy' first send to work around Ethernet.1 - * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011). - * Use zeroed "index" variable as the dummy. - */ - - index = 0; - lpc32xx_eth_send(dev, &index, 4); - - return 0; -} - -static int lpc32xx_eth_halt(struct eth_device *dev) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - - /* Reset all MAC logic */ - writel(MAC1_RESETS, ®s->mac1); - writel(COMMAND_RESETS, ®s->command); - /* Let reset condition settle */ - udelay(2000); - - return 0; -} - -#if defined(CONFIG_PHYLIB) -int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct mii_dev *bus; - struct phy_device *phydev; - int ret; - - bus = mdio_alloc(); - if (!bus) { - printf("mdio_alloc failed\n"); - return -ENOMEM; - } - bus->read = mii_reg_read; - bus->write = mii_reg_write; - strcpy(bus->name, dev->name); - - ret = mdio_register(bus); - if (ret) { - printf("mdio_register failed\n"); - free(bus); - return -ENOMEM; - } - - if (lpc32xx_eth_device->phy_rmii) - phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII); - else - phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII); - - if (!phydev) { - printf("phy_connect failed\n"); - return -ENODEV; - } - - phy_config(phydev); - phy_startup(phydev); - - return 0; -} -#endif - -int lpc32xx_eth_initialize(struct bd_info *bis) -{ - struct eth_device *dev = &lpc32xx_eth.dev; - struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs; - - /* - * Set RMII management clock rate. With HCLK at 104 MHz and - * a divider of 28, this will be 3.72 MHz. - */ - writel(MCFG_RESET_MII_MGMT, ®s->mcfg); - writel(MCFG_CLOCK_SELECT_DIV28, ®s->mcfg); - - /* Reset all MAC logic */ - writel(MAC1_RESETS, ®s->mac1); - writel(COMMAND_RESETS, ®s->command); - - /* wait 10 ms for the whole I/F to reset */ - udelay(10000); - - /* must be less than sizeof(dev->name) */ - strcpy(dev->name, "eth0"); - - dev->init = (void *)lpc32xx_eth_init; - dev->halt = (void *)lpc32xx_eth_halt; - dev->send = (void *)lpc32xx_eth_send; - dev->recv = (void *)lpc32xx_eth_recv; - dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr; - - /* Release SOFT reset to let MII talk to PHY */ - clrbits_le32(®s->mac1, MAC1_SOFT_RESET); - - /* register driver before talking to phy */ - eth_register(dev); - -#if defined(CONFIG_PHYLIB) - lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR); -#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = mii_reg_read; - mdiodev->write = mii_reg_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - - return 0; -} -- cgit v1.3.1 From adae2ed62d3e88093a2e46d119178f03bfd6bc5a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 2 Aug 2022 07:33:37 -0400 Subject: fsl-mc: Update dependencies for DM_ETH When using DM_ETH, which should be the default now, we need to always have DM_MDIO and FSL_LS_MDIO enabled, so select them. Cc: Priyanka Jain Cc: Rajesh Bhagat Cc: Wasim Khan Cc: Udit Agarwal Cc: Ashish Kumar Cc: Meenakshi Aggarwal Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Manish Tomar Signed-off-by: Tom Rini --- drivers/net/fsl-mc/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/net/fsl-mc/Kconfig b/drivers/net/fsl-mc/Kconfig index ae4c35799bf..8fc34dc26f1 100644 --- a/drivers/net/fsl-mc/Kconfig +++ b/drivers/net/fsl-mc/Kconfig @@ -6,6 +6,8 @@ menuconfig FSL_MC_ENET bool "NXP Management Complex" depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A default y + select DM_MDIO + select FSL_LS_MDIO select RESV_RAM help Enable Management Complex (MC) network -- cgit v1.3.1 From a2504a1bd2a9d0c216df9b8da3be4a41753d0cf6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 2 Aug 2022 07:33:40 -0400 Subject: net: ks8851_mll: Remove legacy non-DM_ETH code and callers As this driver has been converted to DM_ETH and the migration deadline is 2 years passed, remove the legacy code and callers. Cc: Eugen Hristev Signed-off-by: Tom Rini Acked-by: Ramon Fried --- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 35 --------------- drivers/net/ks8851_mll.c | 75 ------------------------------- 2 files changed, 110 deletions(-) (limited to 'drivers') diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 018fed9cc2a..a337db4efc6 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -135,30 +135,6 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_LCD */ -#ifdef CONFIG_KS8851_MLL -void at91sam9n12ek_ks8851_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - - writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[2].setup); - writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | - AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7), - &smc->cs[2].pulse); - writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9), - &smc->cs[2].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | - AT91_SMC_MODE_TDF_CYCLE(1), - &smc->cs[2].mode); - - /* Configure NCS2 PIN */ - at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0); -} -#endif - #ifdef CONFIG_USB_ATMEL void at91sam9n12ek_usb_hw_init(void) { @@ -193,10 +169,6 @@ int board_init(void) at91_lcd_hw_init(); #endif -#ifdef CONFIG_KS8851_MLL - at91sam9n12ek_ks8851_hw_init(); -#endif - #ifdef CONFIG_USB_ATMEL at91sam9n12ek_usb_hw_init(); #endif @@ -204,13 +176,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_KS8851_MLL -int board_eth_init(struct bd_info *bis) -{ - return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR); -} -#endif - int dram_init(void) { gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c index 9dd9b33955a..518548e3bbc 100644 --- a/drivers/net/ks8851_mll.c +++ b/drivers/net/ks8851_mll.c @@ -28,9 +28,6 @@ * @extra_byte : number of extra byte prepended rx pkt. */ struct ks_net { -#ifndef CONFIG_DM_ETH - struct eth_device dev; -#endif phys_addr_t iobase; int bus_width; u16 sharedbus; @@ -505,77 +502,6 @@ static void ks8851_mll_write_hwaddr_common(struct ks_net *ks, u8 enetaddr[6]) ks_wrreg16(ks, KS_MARL, addrl); } -#ifndef CONFIG_DM_ETH -static int ks8851_mll_init(struct eth_device *dev, struct bd_info *bd) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - - return ks8851_mll_init_common(ks); -} - -static void ks8851_mll_halt(struct eth_device *dev) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - - ks8851_mll_halt_common(ks); -} - -static int ks8851_mll_send(struct eth_device *dev, void *packet, int length) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - - return ks8851_mll_send_common(ks, packet, length); -} - -static int ks8851_mll_recv(struct eth_device *dev) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - int ret; - - ret = ks8851_mll_recv_common(ks, net_rx_packets[0]); - if (ret) - net_process_received_packet(net_rx_packets[0], ret); - - return ret; -} - -static int ks8851_mll_write_hwaddr(struct eth_device *dev) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - - ks8851_mll_write_hwaddr_common(ks, ks->dev.enetaddr); - - return 0; -} - -int ks8851_mll_initialize(u8 dev_num, int base_addr) -{ - struct ks_net *ks; - - ks = calloc(1, sizeof(*ks)); - if (!ks) - return -ENOMEM; - - ks->iobase = base_addr; - - /* Try to detect chip. Will fail if not present. */ - if (ks8851_mll_detect_chip(ks)) { - free(ks); - return -1; - } - - ks->dev.init = ks8851_mll_init; - ks->dev.halt = ks8851_mll_halt; - ks->dev.send = ks8851_mll_send; - ks->dev.recv = ks8851_mll_recv; - ks->dev.write_hwaddr = ks8851_mll_write_hwaddr; - sprintf(ks->dev.name, "%s-%hu", DRIVERNAME, dev_num); - - eth_register(&ks->dev); - - return 0; -} -#else /* ifdef CONFIG_DM_ETH */ static int ks8851_start(struct udevice *dev) { struct ks_net *ks = dev_get_priv(dev); @@ -703,4 +629,3 @@ U_BOOT_DRIVER(ks8851) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif -- cgit v1.3.1 From 94633c36f9eb34e721faf38270b3dddc8f1cdaed Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 2 Aug 2022 07:33:47 -0400 Subject: net: Make DM_ETH be selected by NETDEVICE The deadline for DM_ETH migration passed 2 years ago. Now that platforms which cannot be migrated have been either removed or had drivers disabled, and platforms that needed minor help to migrate have been forcefully migrated, we can complete the migration. This entails select'ing DM_ETH under NETDEVICES, and then removing now extraneous depends on lines. In a few places, we can now either remove options or just simplify later dependencies. Cc: Ramon Fried Cc: Simon Glass Signed-off-by: Tom Rini Acked-by: Ramon Fried --- Makefile | 1 - drivers/net/Kconfig | 78 +++++++++++++++-------------------------------------- 2 files changed, 21 insertions(+), 58 deletions(-) (limited to 'drivers') diff --git a/Makefile b/Makefile index 1a66f69a4b1..187196c1c64 100644 --- a/Makefile +++ b/Makefile @@ -1151,7 +1151,6 @@ ifneq ($(CONFIG_DM),y) endif $(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\ $(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG)) - $(call deprecated,CONFIG_DM_ETH,Ethernet drivers,v2020.07,$(CONFIG_NET)) $(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY)) $(call deprecated,CONFIG_DM_KEYBOARD,Keyboard drivers,v2022.10,$(CONFIG_KEYBOARD)) @# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 4c1e1a77bb3..6bbbadc5eef 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -7,7 +7,7 @@ config ETH def_bool y config DM_ETH - bool "Enable Driver Model for Ethernet drivers" + bool depends on DM help Enable driver model for Ethernet. @@ -18,7 +18,7 @@ config DM_ETH config DM_MDIO bool "Enable Driver Model for MDIO devices" - depends on DM_ETH && PHYLIB + depends on PHYLIB help Enable driver model for MDIO devices @@ -43,7 +43,7 @@ config DM_MDIO_MUX config DM_DSA bool "Enable Driver Model for DSA switches" - depends on DM_ETH && DM_MDIO + depends on DM_MDIO depends on PHY_FIXED help Enable driver model for DSA switches @@ -94,7 +94,7 @@ config DSA_SANDBOX menuconfig NETDEVICES bool "Network device support" depends on NET - default y if DM_ETH + select DM_ETH help You must select Y to enable any network device support Generally if you have any networking support this is a given @@ -112,7 +112,7 @@ config PHY_GIGE config AG7XXX bool "Atheros AG7xxx Ethernet MAC support" - depends on DM_ETH && ARCH_ATH79 + depends on ARCH_ATH79 select PHYLIB help This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is @@ -121,7 +121,6 @@ config AG7XXX config ALTERA_TSE bool "Altera Triple-Speed Ethernet MAC support" - depends on DM_ETH select PHYLIB help This driver supports the Altera Triple-Speed (TSE) Ethernet MAC. @@ -154,7 +153,7 @@ config BCM_SF2_ETH_GMAC config BCM6348_ETH bool "BCM6348 EMAC support" - depends on DM_ETH && ARCH_BMIPS + depends on ARCH_BMIPS select DMA select DMA_CHANNELS select MII @@ -164,7 +163,7 @@ config BCM6348_ETH config BCM6368_ETH bool "BCM6368 EMAC support" - depends on DM_ETH && ARCH_BMIPS + depends on ARCH_BMIPS select DMA select MII help @@ -172,21 +171,19 @@ config BCM6368_ETH config BCMGENET bool "BCMGENET V5 support" - depends on DM_ETH select PHYLIB help This driver supports the BCMGENET Ethernet MAC. config CORTINA_NI_ENET bool "Cortina-Access Ethernet driver" - depends on DM_ETH && CORTINA_PLATFORM + depends on CORTINA_PLATFORM help This driver supports the Cortina-Access Ethernet MAC for all supported CAxxxx SoCs. config CALXEDA_XGMAC bool "Calxeda XGMAC support" - depends on DM_ETH help This driver supports the XGMAC in Calxeda Highbank and Midway machines. @@ -198,7 +195,6 @@ config DRIVER_DM9000 config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support" - depends on DM_ETH select PHYLIB help This driver supports the Synopsys Designware Ethernet QOS (Quality @@ -273,7 +269,7 @@ config EEPRO100 ethernet family of adapters. config ETH_SANDBOX - depends on DM_ETH && SANDBOX + depends on SANDBOX default y bool "Sandbox: Mocked Ethernet driver" help @@ -283,7 +279,7 @@ config ETH_SANDBOX This driver is particularly useful in the test/dm/eth.c tests config ETH_SANDBOX_RAW - depends on DM_ETH && SANDBOX + depends on SANDBOX default y bool "Sandbox: Bridge to Linux Raw Sockets" help @@ -303,7 +299,6 @@ config ETH_DESIGNWARE config ETH_DESIGNWARE_MESON8B bool "Amlogic Meson8b and later glue driver for Synopsys Designware Ethernet MAC" - depends on DM_ETH select ETH_DESIGNWARE help This provides glue layer to use Synopsys Designware Ethernet MAC @@ -314,7 +309,7 @@ config ETH_DESIGNWARE_SOCFPGA select SYSCON select DW_ALTDESCRIPTOR bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC" - depends on DM_ETH && ETH_DESIGNWARE + depends on ETH_DESIGNWARE help The Altera SoCFPGA requires additional configuration of the Altera system manager to correctly interface with the PHY. @@ -322,7 +317,7 @@ config ETH_DESIGNWARE_SOCFPGA config ETH_DESIGNWARE_S700 bool "Actins S700 glue driver for Synopsys Designware Ethernet MAC" - depends on DM_ETH && ETH_DESIGNWARE + depends on ETH_DESIGNWARE help This provides glue layer to use Synopsys Designware Ethernet MAC present on Actions S700 SoC. @@ -386,7 +381,6 @@ config FTMAC100 config FTGMAC100 bool "Ftgmac100 Ethernet Support" - depends on DM_ETH select PHYLIB help This driver supports the Faraday's FTGMAC100 Gigabit SoC @@ -414,7 +408,6 @@ config SYS_DISCOVER_PHY config MCFFEC bool "ColdFire Ethernet Support" - depends on DM_ETH select PHYLIB select SYS_DISCOVER_PHY help @@ -427,7 +420,6 @@ config SYS_UNIFY_CACHE config FSLDMAFEC bool "ColdFire DMA Ethernet Support" - depends on DM_ETH select PHYLIB select SYS_DISCOVER_PHY help @@ -439,15 +431,6 @@ config KS8851_MLL help The Microchip KS8851 parallel bus external ethernet interface chip. -if KS8851_MLL -if !DM_ETH -config KS8851_MLL_BASEADDR - hex "Microchip KS8851-MLL Base Address" - help - Define this to hold the physical address of the device (I/O space) -endif #DM_ETH -endif #KS8851_MLL - config KSZ9477 bool "Microchip KSZ9477 I2C controller driver" depends on DM_DSA && DM_I2C @@ -458,7 +441,7 @@ config KSZ9477 config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X - select PHYLIB if DM_ETH + select PHYLIB help This driver supports the network interface units in the Marvell Orion5x and Kirkwood SoCs @@ -563,7 +546,6 @@ config OCTEONTX2_CGX_INTF config PCH_GBE bool "Intel Platform Controller Hub EG20T GMAC driver" - depends on DM_ETH select PHYLIB help This MAC is present in Intel Platform Controller Hub EG20T. It @@ -624,25 +606,14 @@ config SJA1105 config SMC911X bool "SMSC LAN911x and LAN921x controller driver" -if SMC911X - -if !DM_ETH -config SMC911X_BASE - hex "SMC911X Base Address" - help - Define this to hold the physical address - of the device (I/O space) -endif #DM_ETH - config SMC911X_32_BIT bool "Enable SMC911X 32-bit interface" + depends on SMC911X help Define this if data bus is 32 bits. If your processor use a narrower 16 bit bus or cannot convert one 32 bit word to two 16 bit words, leave this to "n". -endif #SMC911X - config SUN7I_GMAC bool "Enable Allwinner GMAC Ethernet support" help @@ -658,14 +629,12 @@ config SUN7I_GMAC_FORCE_TXERR config SUN4I_EMAC bool "Allwinner Sun4i Ethernet MAC support" - depends on DM_ETH select PHYLIB help This driver supports the Allwinner based SUN4I Ethernet MAC. config SUN8I_EMAC bool "Allwinner Sun8i Ethernet MAC support" - depends on DM_ETH select PHYLIB select PHY_GIGE help @@ -687,7 +656,6 @@ config TULIP This driver supports DEC DC2114x Fast ethernet chips. config XILINX_AXIEMAC - depends on DM_ETH select PHYLIB select MII bool "Xilinx AXI Ethernet" @@ -695,7 +663,7 @@ config XILINX_AXIEMAC This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. config XILINX_AXIMRMAC - depends on DM_ETH && ARCH_VERSAL + depends on ARCH_VERSAL bool "Xilinx AXI MRMAC" help MRMAC is a high performance, low latency, adaptable Ethernet @@ -704,7 +672,6 @@ config XILINX_AXIMRMAC Versal designs. config XILINX_EMACLITE - depends on DM_ETH select PHYLIB select MII bool "Xilinx Ethernetlite" @@ -712,7 +679,6 @@ config XILINX_EMACLITE This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. config ZYNQ_GEM - depends on DM_ETH select PHYLIB bool "Xilinx Ethernet GEM" help @@ -720,7 +686,7 @@ config ZYNQ_GEM config PIC32_ETH bool "Microchip PIC32 Ethernet Support" - depends on DM_ETH && MACH_PIC32 + depends on MACH_PIC32 select PHYLIB help This driver implements 10/100 Mbps Ethernet and MAC layer for @@ -728,14 +694,14 @@ config PIC32_ETH config GMAC_ROCKCHIP bool "Rockchip Synopsys Designware Ethernet MAC" - depends on DM_ETH && ETH_DESIGNWARE + depends on ETH_DESIGNWARE help This driver provides Rockchip SoCs network support based on the Synopsys Designware driver. config RENESAS_RAVB bool "Renesas Ethernet AVB MAC" - depends on DM_ETH && RCAR_GEN3 + depends on RCAR_GEN3 select PHYLIB help This driver implements support for the Ethernet AVB block in @@ -753,7 +719,7 @@ config MPC8XX_FEC config SNI_AVE bool "Socionext AVE Ethernet support" - depends on DM_ETH && ARCH_UNIPHIER + depends on ARCH_UNIPHIER select PHYLIB select SYSCON select REGMAP @@ -763,7 +729,7 @@ config SNI_AVE config SNI_NETSEC bool "Socionext NETSEC Ethernet support" - depends on DM_ETH && SYNQUACER_SPI + depends on SYNQUACER_SPI select PHYLIB help This driver implements support for the Socionext SynQuacer NETSEC @@ -852,7 +818,6 @@ config TSEC_ENET config MEDIATEK_ETH bool "MediaTek Ethernet GMAC Driver" - depends on DM_ETH select PHYLIB select DM_GPIO select DM_RESET @@ -862,7 +827,6 @@ config MEDIATEK_ETH config HIGMACV300_ETH bool "HiSilicon Gigabit Ethernet Controller" - depends on DM_ETH select DM_RESET select PHYLIB help @@ -871,7 +835,7 @@ config HIGMACV300_ETH config FSL_ENETC bool "NXP ENETC Ethernet controller" - depends on DM_ETH && DM_MDIO + depends on DM_MDIO help This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs. -- cgit v1.3.1