From fa72de10452c51ee32f8278cdfabd38a6aafc7f8 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 13 Feb 2017 17:38:55 +0800 Subject: rockchip: arm64: rk3399: move grf register definitions to grf_rk3399.h rk3399 grf register bit defenitions should locate in header file, so that not only pinctrl can use it. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Added rockchip tag: Signed-off-by: Simon Glass --- drivers/pinctrl/rockchip/pinctrl_rk3399.c | 106 ------------------------------ 1 file changed, 106 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index da301544c99..6201603c5a3 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -22,112 +22,6 @@ struct rk3399_pinctrl_priv { struct rk3399_pmugrf_regs *pmugrf; }; -enum { - /* GRF_GPIO2B_IOMUX */ - GRF_GPIO2B1_SEL_SHIFT = 0, - GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT, - GRF_SPI2TPM_RXD = 1, - GRF_GPIO2B2_SEL_SHIFT = 2, - GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT, - GRF_SPI2TPM_TXD = 1, - GRF_GPIO2B3_SEL_SHIFT = 6, - GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT, - GRF_SPI2TPM_CLK = 1, - GRF_GPIO2B4_SEL_SHIFT = 8, - GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT, - GRF_SPI2TPM_CSN0 = 1, - - /* GRF_GPIO3A_IOMUX */ - GRF_GPIO3A4_SEL_SHIFT = 8, - GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT, - GRF_SPI0NORCODEC_RXD = 2, - GRF_GPIO3A5_SEL_SHIFT = 10, - GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT, - GRF_SPI0NORCODEC_TXD = 2, - GRF_GPIO3A6_SEL_SHIFT = 12, - GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT, - GRF_SPI0NORCODEC_CLK = 2, - GRF_GPIO3A7_SEL_SHIFT = 14, - GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT, - GRF_SPI0NORCODEC_CSN0 = 2, - - /* GRF_GPIO3B_IOMUX */ - GRF_GPIO3B0_SEL_SHIFT = 0, - GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT, - GRF_SPI0NORCODEC_CSN1 = 2, - - /* GRF_GPIO4B_IOMUX */ - GRF_GPIO4B0_SEL_SHIFT = 0, - GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT, - GRF_SDMMC_DATA0 = 1, - GRF_UART2DBGA_SIN = 2, - GRF_GPIO4B1_SEL_SHIFT = 2, - GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT, - GRF_SDMMC_DATA1 = 1, - GRF_UART2DBGA_SOUT = 2, - GRF_GPIO4B2_SEL_SHIFT = 4, - GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT, - GRF_SDMMC_DATA2 = 1, - GRF_GPIO4B3_SEL_SHIFT = 6, - GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT, - GRF_SDMMC_DATA3 = 1, - GRF_GPIO4B4_SEL_SHIFT = 8, - GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT, - GRF_SDMMC_CLKOUT = 1, - GRF_GPIO4B5_SEL_SHIFT = 10, - GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT, - GRF_SDMMC_CMD = 1, - - /* GRF_GPIO4C_IOMUX */ - GRF_GPIO4C2_SEL_SHIFT = 4, - GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT, - GRF_PWM_0 = 1, - GRF_GPIO4C3_SEL_SHIFT = 6, - GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT, - GRF_UART2DGBC_SIN = 1, - GRF_GPIO4C4_SEL_SHIFT = 8, - GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT, - GRF_UART2DBGC_SOUT = 1, - GRF_GPIO4C6_SEL_SHIFT = 12, - GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT, - GRF_PWM_1 = 1, - - /* PMUGRF_GPIO0A_IOMUX */ - PMUGRF_GPIO0A6_SEL_SHIFT = 12, - PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT, - PMUGRF_PWM_3A = 1, - - /* PMUGRF_GPIO1A_IOMUX */ - PMUGRF_GPIO1A7_SEL_SHIFT = 14, - PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT, - PMUGRF_SPI1EC_RXD = 2, - - /* PMUGRF_GPIO1B_IOMUX */ - PMUGRF_GPIO1B0_SEL_SHIFT = 0, - PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT, - PMUGRF_SPI1EC_TXD = 2, - PMUGRF_GPIO1B1_SEL_SHIFT = 2, - PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT, - PMUGRF_SPI1EC_CLK = 2, - PMUGRF_GPIO1B2_SEL_SHIFT = 4, - PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT, - PMUGRF_SPI1EC_CSN0 = 2, - PMUGRF_GPIO1B6_SEL_SHIFT = 12, - PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT, - PMUGRF_PWM_3B = 1, - PMUGRF_GPIO1B7_SEL_SHIFT = 14, - PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT, - PMUGRF_I2C0PMU_SDA = 2, - - /* PMUGRF_GPIO1C_IOMUX */ - PMUGRF_GPIO1C0_SEL_SHIFT = 0, - PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT, - PMUGRF_I2C0PMU_SCL = 2, - PMUGRF_GPIO1C3_SEL_SHIFT = 6, - PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT, - PMUGRF_PWM_2 = 1, - -}; static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf, struct rk3399_pmugrf_regs *pmugrf, int pwm_id) { -- cgit v1.3.1 From 5ae2fd97242d4eea97aeabe8801bb8592b37a8fe Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 13 Feb 2017 17:38:56 +0800 Subject: rockchip: clk: rk3399: update driver for spl Add ddr clock setting, add rockchip_get_pmucru API, and enable of-platdata support. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Added rockchip tag and fix pmuclk_init() build warning: Signed-off-by: Simon Glass --- arch/arm/include/asm/arch-rockchip/clock.h | 7 ++ arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 5 ++ arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 21 ++++++ drivers/clk/rockchip/clk_rk3399.c | 91 ++++++++++++++++++++++--- include/dt-bindings/clock/rk3399-cru.h | 16 +++-- 5 files changed, 125 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 804c77beaac..6f7e755d755 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -63,6 +63,13 @@ static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) */ void *rockchip_get_cru(void); +/** + * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers + * + * @return pointer to registers, or -ve error on error + */ +void *rockchip_get_pmucru(void); + struct rk3288_cru; struct rk3288_grf; diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index 98fba2bd755..cf830d04ead 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -15,6 +15,11 @@ struct rk3399_clk_priv { ulong rate; }; +struct rk3399_pmuclk_priv { + struct rk3399_pmucru *pmucru; + ulong rate; +}; + struct rk3399_pmucru { u32 ppll_con[6]; u32 reserved[0x1a]; diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index ce706a61e24..cf5b8c9548b 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -31,3 +31,24 @@ void *rockchip_get_cru(void) return priv->cru; } + +static int rockchip_get_pmucruclk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp); +} + +void *rockchip_get_pmucru(void) +{ + struct rk3399_pmuclk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_pmucruclk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->pmucru; +} diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 2e87e4b62d5..922ce7e5491 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -7,7 +7,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -18,10 +20,16 @@ DECLARE_GLOBAL_DATA_PTR; -struct rk3399_pmuclk_priv { - struct rk3399_pmucru *pmucru; +#if CONFIG_IS_ENABLED(OF_PLATDATA) +struct rk3399_clk_plat { + struct dtd_rockchip_rk3399_cru dtd; }; +struct rk3399_pmuclk_plat { + struct dtd_rockchip_rk3399_pmucru dtd; +}; +#endif + struct pll_div { u32 refdiv; u32 fbdiv; @@ -381,6 +389,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) return 0; } +#ifdef CONFIG_SPL_BUILD static void rkclk_init(struct rk3399_cru *cru) { u32 aclk_div; @@ -456,6 +465,7 @@ static void rkclk_init(struct rk3399_cru *cru) hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); } +#endif void rk3399_configure_cpu(struct rk3399_cru *cru, enum apll_l_frequencies apll_l_freq) @@ -709,6 +719,44 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, return rk3399_mmc_get_clk(cru, clk_id); } +#define PMUSGRF_DDR_RGN_CON16 0xff330040 +static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, + ulong set_rate) +{ + struct pll_div dpll_cfg; + + /* IC ECO bug, need to set this register */ + writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); + + /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ + switch (set_rate) { + case 200*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; + break; + case 300*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; + break; + case 666*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; + break; + case 800*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; + break; + case 933*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; + break; + default: + error("Unsupported SDRAM frequency!,%ld\n", set_rate); + } + rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); + + return set_rate; +} static ulong rk3399_clk_get_rate(struct clk *clk) { struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); @@ -763,6 +811,9 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case DCLK_VOP1: ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); break; + case SCLK_DDRCLK: + ret = rk3399_ddr_set_clk(priv->cru, rate); + break; default: return -ENOENT; } @@ -777,19 +828,26 @@ static struct clk_ops rk3399_clk_ops = { static int rk3399_clk_probe(struct udevice *dev) { +#ifdef CONFIG_SPL_BUILD struct rk3399_clk_priv *priv = dev_get_priv(dev); - rkclk_init(priv->cru); +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3399_clk_plat *plat = dev_get_platdata(dev); + priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]); +#endif + rkclk_init(priv->cru); +#endif return 0; } static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_clk_priv *priv = dev_get_priv(dev); priv->cru = (struct rk3399_cru *)dev_get_addr(dev); - +#endif return 0; } @@ -811,7 +869,7 @@ static const struct udevice_id rk3399_clk_ids[] = { }; U_BOOT_DRIVER(clk_rk3399) = { - .name = "clk_rk3399", + .name = "rockchip_rk3399_cru", .id = UCLASS_CLK, .of_match = rk3399_clk_ids, .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), @@ -819,6 +877,9 @@ U_BOOT_DRIVER(clk_rk3399) = { .ops = &rk3399_clk_ops, .bind = rk3399_clk_bind, .probe = rk3399_clk_probe, +#if CONFIG_IS_ENABLED(OF_PLATDATA) + .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), +#endif }; static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) @@ -930,6 +991,7 @@ static struct clk_ops rk3399_pmuclk_ops = { .set_rate = rk3399_pmuclk_set_rate, }; +#ifndef CONFIG_SPL_BUILD static void pmuclk_init(struct rk3399_pmucru *pmucru) { u32 pclk_div; @@ -939,27 +1001,35 @@ static void pmuclk_init(struct rk3399_pmucru *pmucru) /* configure pmu pclk */ pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; - assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f); rk_clrsetreg(&pmucru->pmucru_clksel[0], PMU_PCLK_DIV_CON_MASK, pclk_div << PMU_PCLK_DIV_CON_SHIFT); } +#endif static int rk3399_pmuclk_probe(struct udevice *dev) { struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); - pmuclk_init(priv->pmucru); +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); + + priv->pmucru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]); +#endif +#ifndef CONFIG_SPL_BUILD + pmuclk_init(priv->pmucru); +#endif return 0; } static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); priv->pmucru = (struct rk3399_pmucru *)dev_get_addr(dev); - +#endif return 0; } @@ -969,11 +1039,14 @@ static const struct udevice_id rk3399_pmuclk_ids[] = { }; U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { - .name = "pmuclk_rk3399", + .name = "rockchip_rk3399_pmucru", .id = UCLASS_CLK, .of_match = rk3399_pmuclk_ids, .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, .ops = &rk3399_pmuclk_ops, .probe = rk3399_pmuclk_probe, +#if CONFIG_IS_ENABLED(OF_PLATDATA) + .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), +#endif }; diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 0a86aec50a2..d4bdcc663fe 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -122,6 +122,10 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 +#define SCLK_DDRCLK 170 +#define SCLK_TESTOUT2 171 #define DCLK_VOP0 180 #define DCLK_VOP1 181 @@ -589,13 +593,13 @@ #define SRST_P_SPI0 214 #define SRST_P_SPI1 215 #define SRST_P_SPI2 216 -#define SRST_P_SPI3 217 -#define SRST_P_SPI4 218 +#define SRST_P_SPI4 217 +#define SRST_P_SPI5 218 #define SRST_SPI0 219 #define SRST_SPI1 220 #define SRST_SPI2 221 -#define SRST_SPI3 222 -#define SRST_SPI4 223 +#define SRST_SPI4 222 +#define SRST_SPI5 223 /* cru_softrst_con14 */ #define SRST_I2S0_8CH 224 @@ -717,8 +721,8 @@ #define SRST_H_CM0S_NOC 3 #define SRST_DBG_CM0S 4 #define SRST_PO_CM0S 5 -#define SRST_P_SPI6 6 -#define SRST_SPI6 7 +#define SRST_P_SPI3 6 +#define SRST_SPI3 7 #define SRST_P_TIMER_0_1 8 #define SRST_P_TIMER_0 9 #define SRST_P_TIMER_1 10 -- cgit v1.3.1 From c2868212bbd140be8e2448498734d8c48ae6404f Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 13 Feb 2017 17:38:57 +0800 Subject: rockchip: sdhci: rk3399: update driver to support of-platdata Change some API in order to enable of-platdata. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Added rockchip tag: Signed-off-by: Simon Glass --- drivers/mmc/rockchip_sdhci.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index bd91f917580..bdde831ffd5 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -8,9 +8,11 @@ #include #include +#include #include #include #include +#include #include #include @@ -19,6 +21,9 @@ DECLARE_GLOBAL_DATA_PTR; #define EMMC_MIN_FREQ 400000 struct rockchip_sdhc_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3399_sdhci_5_1 dtplat; +#endif struct mmc_config cfg; struct mmc mmc; }; @@ -37,10 +42,18 @@ static int arasan_sdhci_probe(struct udevice *dev) int max_frequency, ret; struct clk clk; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat; + host->name = dev->name; + host->ioaddr = map_sysmem(dtplat->reg[1], dtplat->reg[3]); + max_frequency = dtplat->max_frequency; + ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk); +#else max_frequency = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "max-frequency", 0); ret = clk_get_by_index(dev, 0, &clk); +#endif if (!ret) { ret = clk_set_rate(&clk, max_frequency); if (IS_ERR_VALUE(ret)) @@ -66,10 +79,12 @@ static int arasan_sdhci_probe(struct udevice *dev) static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct sdhci_host *host = dev_get_priv(dev); host->name = dev->name; host->ioaddr = dev_get_addr_ptr(dev); +#endif return 0; } @@ -87,7 +102,7 @@ static const struct udevice_id arasan_sdhci_ids[] = { }; U_BOOT_DRIVER(arasan_sdhci_drv) = { - .name = "arasan_sdhci", + .name = "rockchip_rk3399_sdhci_5_1", .id = UCLASS_MMC, .of_match = arasan_sdhci_ids, .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, -- cgit v1.3.1 From 6657f664180632dc352210ee87369d857037b0b1 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 13 Feb 2017 17:38:58 +0800 Subject: rockchip: pinctrl: rk3399: add the of-platdata support Do not use the API which of-platdata not support. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Added rockchip tag: Signed-off-by: Simon Glass --- drivers/pinctrl/rockchip/pinctrl_rk3399.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index 6201603c5a3..a74793aa485 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -253,6 +253,7 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) static int rk3399_pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) u32 cell[3]; int ret; @@ -283,7 +284,7 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev, case 65: return PERIPH_ID_SDMMC1; } - +#endif return -ENOENT; } @@ -328,6 +329,8 @@ U_BOOT_DRIVER(pinctrl_rk3399) = { .of_match = rk3399_pinctrl_ids, .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv), .ops = &rk3399_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) .bind = dm_scan_fdt_dev, +#endif .probe = rk3399_pinctrl_probe, }; -- cgit v1.3.1 From 27326c7ee269ff351bba8c2461e19f29d66b6a3a Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Sat, 18 Feb 2017 19:46:21 +0100 Subject: dm: allow limiting pre-reloc markings to spl or tpl Right now the u-boot,dm-pre-reloc flag will make each marked node always appear in both spl and tpl. But systems needing an additional tpl might have special constraints for each, like the spl needing to be very tiny. So introduce two additional flags to mark nodes for only spl or tpl environments and introduce a function dm_fdt_pre_reloc to automate the necessary checks in code instances checking for pre-relocation flags. The behaviour of the original flag stays untouched and still marks a node for both spl and tpl. Signed-off-by: Heiko Stuebner Reviewed-by: Simon Glass Tested-by: Kever Yang --- doc/driver-model/README.txt | 4 ++++ drivers/clk/at91/pmc.c | 3 ++- drivers/core/root.c | 2 +- drivers/core/util.c | 25 +++++++++++++++++++++++++ drivers/pinctrl/pinctrl-uclass.c | 3 ++- include/dm/util.h | 26 ++++++++++++++++++++++++++ scripts/Makefile.spl | 7 ++++++- tools/dtoc/dtoc.py | 2 ++ 8 files changed, 68 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt index fea324e25ee..0853477578a 100644 --- a/doc/driver-model/README.txt +++ b/doc/driver-model/README.txt @@ -825,6 +825,10 @@ drivers marked with DM_FLAG_PRE_RELOC or the device tree 'u-boot,dm-pre-reloc' flag are initialised prior to relocation. This helps to reduce the driver model overhead. +It is possible to limit this to specific relocation steps, by using +the more specialized 'u-boot,dm-spl' and 'u-boot,dm-tpl' flags +in the devicetree. + Then post relocation we throw that away and re-init driver model again. For drivers which require some sort of continuity between pre- and post-relocation devices, we can provide access to the pre-relocation diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index c73156a0df1..fcd693a2f6f 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "pmc.h" DECLARE_GLOBAL_DATA_PTR; @@ -56,7 +57,7 @@ int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name) offset > 0; offset = fdt_next_subnode(fdt, offset)) { if (pre_reloc_only && - !fdt_getprop(fdt, offset, "u-boot,dm-pre-reloc", NULL)) + !dm_fdt_pre_reloc(fdt, offset)) continue; /* * If this node has "compatible" property, this is not diff --git a/drivers/core/root.c b/drivers/core/root.c index 175fd3fb252..93ab5682968 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -205,7 +205,7 @@ int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset, offset > 0; offset = fdt_next_subnode(blob, offset)) { if (pre_reloc_only && - !fdt_getprop(blob, offset, "u-boot,dm-pre-reloc", NULL)) + !dm_fdt_pre_reloc(blob, offset)) continue; if (!fdtdec_get_is_enabled(blob, offset)) { dm_dbg(" - ignoring disabled device\n"); diff --git a/drivers/core/util.c b/drivers/core/util.c index e01dd06d282..bd4de7acd69 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -5,6 +5,7 @@ */ #include +#include #include void dm_warn(const char *fmt, ...) @@ -35,3 +36,27 @@ int list_count_items(struct list_head *head) return count; } + +int dm_fdt_pre_reloc(const void *blob, int offset) +{ + if (fdt_getprop(blob, offset, "u-boot,dm-pre-reloc", NULL)) + return 1; + +#ifdef CONFIG_TPL_BUILD + if (fdt_getprop(blob, offset, "u-boot,dm-tpl", NULL)) + return 1; +#elif defined(CONFIG_SPL_BUILD) + if (fdt_getprop(blob, offset, "u-boot,dm-spl", NULL)) + return 1; +#else + /* + * In regular builds individual spl and tpl handling both + * count as handled pre-relocation for later second init. + */ + if (fdt_getprop(blob, offset, "u-boot,dm-spl", NULL) || + fdt_getprop(blob, offset, "u-boot,dm-tpl", NULL)) + return 1; +#endif + + return 0; +} diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index 49afe91c24e..9efad0623a3 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -12,6 +12,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -131,7 +132,7 @@ static int pinconfig_post_bind(struct udevice *dev) offset > 0; offset = fdt_next_subnode(fdt, offset)) { if (pre_reloc_only && - !fdt_getprop(fdt, offset, "u-boot,dm-pre-reloc", NULL)) + !dm_fdt_pre_reloc(fdt, offset)) continue; /* * If this node has "compatible" property, this is not diff --git a/include/dm/util.h b/include/dm/util.h index 15daa3d19f1..32060ab30eb 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -48,4 +48,30 @@ static inline void dm_dump_devres(void) } #endif +/** + * Check if a dt node should be or was bound before relocation. + * + * Devicetree nodes can be marked as needed to be bound + * in the loader stages via special devicetree properties. + * + * Before relocation this function can be used to check if nodes + * are required in either SPL or TPL stages. + * + * After relocation and jumping into the real U-Boot binary + * it is possible to determine if a node was bound in one of + * SPL/TPL stages. + * + * There are 3 settings currently in use + * - + * - u-boot,dm-pre-reloc: legacy and indicates any of TPL or SPL + * Existing platforms only use it to indicate nodes needee in + * SPL. Should probably be replaced by u-boot,dm-spl for + * existing platforms. + * @blob: devicetree + * @offset: node offset + * + * Returns true if node is needed in SPL/TL, false otherwise. + */ +int dm_fdt_pre_reloc(const void *blob, int offset); + #endif diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index b52f9963f7d..5370648e853 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -215,8 +215,13 @@ $(obj)/$(SPL_BIN)-pad.bin: $(obj)/$(SPL_BIN) # 'u-boot,dm-pre-reloc' property and thus are not needed by SPL. The second # pass removes various unused properties from the remaining nodes. # The output is typically a much smaller device tree file. +ifeq ($(CONFIG_TPL_BUILD),y) +fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-tpl +else +fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-spl +endif quiet_cmd_fdtgrep = FDTGREP $@ - cmd_fdtgrep = $(objtree)/tools/fdtgrep -b u-boot,dm-pre-reloc -RT $< \ + cmd_fdtgrep = $(objtree)/tools/fdtgrep $(fdtgrep_props) -RT $< \ -n /chosen -O dtb | \ $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \ $(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS))) diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py index 6df7b0da13a..bf67ec80ca1 100755 --- a/tools/dtoc/dtoc.py +++ b/tools/dtoc/dtoc.py @@ -30,6 +30,8 @@ PROP_IGNORE_LIST = [ "status", 'phandle', 'u-boot,dm-pre-reloc', + 'u-boot,dm-tpl', + 'u-boot,dm-spl', ] # C type declarations for the tyues we support -- cgit v1.3.1 From 6496498a626dbde4d0ed96406e4efee9ff2ab0c0 Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Sat, 18 Feb 2017 19:46:22 +0100 Subject: rockchip: clk: rk3288: limit gpll and cpll init to SPL build The gpll and cpll init values are only used in rk_clk_init in the SPL and therefore produce compile time warnings in regular uboot builds. Fix that with an #ifdef. Signed-off-by: Heiko Stuebner Acked-by: Simon Glass Added rockchip tag: Signed-off-by: Simon Glass --- drivers/clk/rockchip/clk_rk3288.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index d15504c3aae..78356766a78 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -131,8 +131,10 @@ enum { /* Keep divisors as low as possible to reduce jitter and power usage */ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); +#ifdef CONFIG_SPL_BUILD static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); +#endif static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) -- cgit v1.3.1 From cd76916fa3195edae6faad67dea896118457b035 Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Sat, 18 Feb 2017 19:46:29 +0100 Subject: rockchip: serial: Adapt rockchip of-platdata driver for rk3188 Add necessary structs to have the driver also work for the serial on the rk3188. Signed-off-by: Heiko Stuebner Reviewed-by: Simon Glass Tested-by: Kever Yang --- drivers/serial/serial_rockchip.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c index c06afc58f7e..734cee2ba4d 100644 --- a/drivers/serial/serial_rockchip.c +++ b/drivers/serial/serial_rockchip.c @@ -12,12 +12,19 @@ #include #include +#if defined(CONFIG_ROCKCHIP_RK3188) +struct rockchip_uart_platdata { + struct dtd_rockchip_rk3188_uart dtplat; + struct ns16550_platdata plat; +}; +struct dtd_rockchip_rk3188_uart *dtplat, s_dtplat; +#elif defined(CONFIG_ROCKCHIP_RK3288) struct rockchip_uart_platdata { struct dtd_rockchip_rk3288_uart dtplat; struct ns16550_platdata plat; }; - struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat; +#endif static int rockchip_serial_probe(struct udevice *dev) { @@ -33,6 +40,16 @@ static int rockchip_serial_probe(struct udevice *dev) return ns16550_serial_probe(dev); } +U_BOOT_DRIVER(rockchip_rk3188_uart) = { + .name = "rockchip_rk3188_uart", + .id = UCLASS_SERIAL, + .priv_auto_alloc_size = sizeof(struct NS16550), + .platdata_auto_alloc_size = sizeof(struct rockchip_uart_platdata), + .probe = rockchip_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + U_BOOT_DRIVER(rockchip_rk3288_uart) = { .name = "rockchip_rk3288_uart", .id = UCLASS_SERIAL, -- cgit v1.3.1 From 155cd37f2cd9d776a4a35f348f22555720bbfd62 Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Sat, 18 Feb 2017 19:46:31 +0100 Subject: rockchip: rk3188: Add pinctrl driver Add a driver which supports pin multiplexing setup for the most commonly used peripherals. Signed-off-by: Heiko Stuebner Acked-by: Simon Glass Tested-by: Kever Yang --- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3188.c | 611 ++++++++++++++++++++++++++++++ 3 files changed, 621 insertions(+) create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c (limited to 'drivers') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 0c832e187da..397fbe13316 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -132,6 +132,15 @@ config ROCKCHIP_RK3036_PINCTRL definitions and pin control functions for each available multiplex function. +config ROCKCHIP_RK3188_PINCTRL + bool "Rockchip pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3188 SoCs. The driver + is controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + config ROCKCHIP_RK3288_PINCTRL bool "Rockchip pin control driver" depends on DM diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 805c833ec9d..cc99aeebb54 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -6,5 +6,6 @@ # obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3188_PINCTRL) += pinctrl_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3399_PINCTRL) += pinctrl_rk3399.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3188.c b/drivers/pinctrl/rockchip/pinctrl_rk3188.c new file mode 100644 index 00000000000..ef94dab210e --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk3188.c @@ -0,0 +1,611 @@ +/* + * Pinctrl driver for Rockchip RK3188 SoCs + * Copyright (c) 2016 Heiko Stuebner + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3188_pinctrl_priv { + struct rk3188_grf *grf; + struct rk3188_pmu *pmu; + int num_banks; +}; + +/** + * Encode variants of iomux registers into a type variable + */ +#define IOMUX_GPIO_ONLY BIT(0) + +/** + * @type: iomux variant using IOMUX_* constants + * @offset: if initialized to -1 it will be autocalculated, by specifying + * an initial offset value the relevant source offset can be reset + * to a new value for autocalculating the following iomux registers. + */ +struct rockchip_iomux { + u8 type; + s16 offset; +}; + +/** + * @reg: register offset of the gpio bank + * @nr_pins: number of pins in this bank + * @bank_num: number of the bank, to account for holes + * @name: name of the bank + * @iomux: array describing the 4 iomux sources of the bank + */ +struct rockchip_pin_bank { + u16 reg; + u8 nr_pins; + u8 bank_num; + char *name; + struct rockchip_iomux iomux[4]; +}; + +#define PIN_BANK(id, pins, label) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + }, \ + } + +#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = -1 }, \ + { .type = iom1, .offset = -1 }, \ + { .type = iom2, .offset = -1 }, \ + { .type = iom3, .offset = -1 }, \ + }, \ + } + +#ifndef CONFIG_SPL_BUILD +static struct rockchip_pin_bank rk3188_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; +#endif + +static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id) +{ + switch (pwm_id) { + case PERIPH_ID_PWM0: + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT, + GPIO3D3_PWM_0 << GPIO3D3_SHIFT); + break; + case PERIPH_ID_PWM1: + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT, + GPIO3D4_PWM_1 << GPIO3D4_SHIFT); + break; + case PERIPH_ID_PWM2: + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT, + GPIO3D5_PWM_2 << GPIO3D5_SHIFT); + break; + case PERIPH_ID_PWM3: + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT, + GPIO3D6_PWM_3 << GPIO3D6_SHIFT); + break; + default: + debug("pwm id = %d iomux error!\n", pwm_id); + break; + } +} + +static void pinctrl_rk3188_i2c_config(struct rk3188_grf *grf, + struct rk3188_pmu *pmu, int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D1_MASK << GPIO1D1_SHIFT | + GPIO1D0_MASK << GPIO1D0_SHIFT, + GPIO1D1_I2C0_SCL << GPIO1D1_SHIFT | + GPIO1D0_I2C0_SDA << GPIO1D0_SHIFT); + /* enable new i2c controller */ + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT, + 1 << RKI2C0_SEL_SHIFT); + break; + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D3_MASK << GPIO1D3_SHIFT | + GPIO1D2_MASK << GPIO1D2_SHIFT, + GPIO1D3_I2C1_SCL << GPIO1D2_SHIFT | + GPIO1D2_I2C1_SDA << GPIO1D2_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT, + 1 << RKI2C1_SEL_SHIFT); + break; + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D5_MASK << GPIO1D5_SHIFT | + GPIO1D4_MASK << GPIO1D4_SHIFT, + GPIO1D5_I2C2_SCL << GPIO1D5_SHIFT | + GPIO1D4_I2C2_SDA << GPIO1D4_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT, + 1 << RKI2C2_SEL_SHIFT); + break; + case PERIPH_ID_I2C3: + rk_clrsetreg(&grf->gpio3b_iomux, + GPIO3B7_MASK << GPIO3B7_SHIFT | + GPIO3B6_MASK << GPIO3B6_SHIFT, + GPIO3B7_I2C3_SCL << GPIO3B7_SHIFT | + GPIO3B6_I2C3_SDA << GPIO3B6_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT, + 1 << RKI2C3_SEL_SHIFT); + break; + case PERIPH_ID_I2C4: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D7_MASK << GPIO1D7_SHIFT | + GPIO1D6_MASK << GPIO1D6_SHIFT, + GPIO1D7_I2C4_SCL << GPIO1D7_SHIFT | + GPIO1D6_I2C4_SDA << GPIO1D6_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT, + 1 << RKI2C4_SEL_SHIFT); + break; + default: + debug("i2c id = %d iomux error!\n", i2c_id); + break; + } +} + +static int pinctrl_rk3188_spi_config(struct rk3188_grf *grf, + enum periph_id spi_id, int cs) +{ + switch (spi_id) { + case PERIPH_ID_SPI0: + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A7_MASK << GPIO1A7_SHIFT, + GPIO1A7_SPI0_CSN0 << GPIO1A7_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B7_MASK << GPIO1B7_SHIFT, + GPIO1B7_SPI0_CSN1 << GPIO1B7_SHIFT); + break; + default: + goto err; + } + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A4_MASK << GPIO1A4_SHIFT | + GPIO1A5_MASK << GPIO1A5_SHIFT | + GPIO1A6_MASK << GPIO1A6_SHIFT, + GPIO1A4_SPI0_RXD << GPIO1A4_SHIFT | + GPIO1A5_SPI0_TXD << GPIO1A5_SHIFT | + GPIO1A6_SPI0_CLK << GPIO1A6_SHIFT); + break; + case PERIPH_ID_SPI1: + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D7_MASK << GPIO0D7_SHIFT, + GPIO0D7_SPI1_CSN0 << GPIO0D7_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B6_MASK << GPIO1B6_SHIFT, + GPIO1B6_SPI1_CSN1 << GPIO1B6_SHIFT); + break; + default: + goto err; + } + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D4_MASK << GPIO0D4_SHIFT | + GPIO0D5_MASK << GPIO0D5_SHIFT | + GPIO0D6_MASK << GPIO0D6_SHIFT, + GPIO0D4_SPI0_RXD << GPIO0D4_SHIFT | + GPIO0D5_SPI1_TXD << GPIO0D5_SHIFT | + GPIO0D6_SPI1_CLK << GPIO0D6_SHIFT); + break; + default: + goto err; + } + + return 0; +err: + debug("rkspi: periph%d cs=%d not supported", spi_id, cs); + return -ENOENT; +} + +static void pinctrl_rk3188_uart_config(struct rk3188_grf *grf, int uart_id) +{ + switch (uart_id) { + case PERIPH_ID_UART0: + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A3_MASK << GPIO1A3_SHIFT | + GPIO1A2_MASK << GPIO1A2_SHIFT | + GPIO1A1_MASK << GPIO1A1_SHIFT | + GPIO1A0_MASK << GPIO1A0_SHIFT, + GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT | + GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT | + GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT | + GPIO1A0_UART0_SIN << GPIO1A0_SHIFT); + break; + case PERIPH_ID_UART1: + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A7_MASK << GPIO1A7_SHIFT | + GPIO1A6_MASK << GPIO1A6_SHIFT | + GPIO1A5_MASK << GPIO1A5_SHIFT | + GPIO1A4_MASK << GPIO1A4_SHIFT, + GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT | + GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT | + GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT | + GPIO1A4_UART1_SIN << GPIO1A4_SHIFT); + break; + case PERIPH_ID_UART2: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK << GPIO1B1_SHIFT | + GPIO1B0_MASK << GPIO1B0_SHIFT, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); + break; + case PERIPH_ID_UART3: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B5_MASK << GPIO1B5_SHIFT | + GPIO1B4_MASK << GPIO1B4_SHIFT | + GPIO1B3_MASK << GPIO1B3_SHIFT | + GPIO1B2_MASK << GPIO1B2_SHIFT, + GPIO1B5_UART3_RTS_N << GPIO1B5_SHIFT | + GPIO1B4_UART3_CTS_N << GPIO1B4_SHIFT | + GPIO1B3_UART3_SOUT << GPIO1B3_SHIFT | + GPIO1B2_UART3_SIN << GPIO1B2_SHIFT); + break; + default: + debug("uart id = %d iomux error!\n", uart_id); + break; + } +} + +static void pinctrl_rk3188_sdmmc_config(struct rk3188_grf *grf, int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&grf->soc_con0, 1 << EMMC_FLASH_SEL_SHIFT, + 1 << EMMC_FLASH_SEL_SHIFT); + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D2_MASK << GPIO0D2_SHIFT | + GPIO0D0_MASK << GPIO0D0_SHIFT, + GPIO0D2_EMMC_CMD << GPIO0D2_SHIFT | + GPIO0D0_EMMC_CLKOUT << GPIO0D0_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&grf->gpio3b_iomux, + GPIO3B0_MASK << GPIO3B0_SHIFT, + GPIO3B0_SDMMC_DETECT_N << GPIO3B0_SHIFT); + rk_clrsetreg(&grf->gpio3a_iomux, + GPIO3A7_MASK << GPIO3A7_SHIFT | + GPIO3A6_MASK << GPIO3A6_SHIFT | + GPIO3A5_MASK << GPIO3A5_SHIFT | + GPIO3A4_MASK << GPIO3A4_SHIFT | + GPIO3A3_MASK << GPIO3A3_SHIFT | + GPIO3A3_MASK << GPIO3A2_SHIFT, + GPIO3A7_SDMMC0_DATA3 << GPIO3A7_SHIFT | + GPIO3A6_SDMMC0_DATA2 << GPIO3A6_SHIFT | + GPIO3A5_SDMMC0_DATA1 << GPIO3A5_SHIFT | + GPIO3A4_SDMMC0_DATA0 << GPIO3A4_SHIFT | + GPIO3A3_SDMMC0_CMD << GPIO3A3_SHIFT | + GPIO3A2_SDMMC0_CLKOUT << GPIO3A2_SHIFT); + break; + default: + debug("mmc id = %d iomux error!\n", mmc_id); + break; + } +} + +static int rk3188_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + case PERIPH_ID_PWM4: + pinctrl_rk3188_pwm_config(priv->grf, func); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + pinctrl_rk3188_i2c_config(priv->grf, priv->pmu, func); + break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + pinctrl_rk3188_spi_config(priv->grf, func, flags); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + case PERIPH_ID_UART4: + pinctrl_rk3188_uart_config(priv->grf, func); + break; + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + pinctrl_rk3188_sdmmc_config(priv->grf, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk3188_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset, + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 44: + return PERIPH_ID_SPI0; + case 45: + return PERIPH_ID_SPI1; + case 46: + return PERIPH_ID_SPI2; + case 60: + return PERIPH_ID_I2C0; + case 62: /* Note strange order */ + return PERIPH_ID_I2C1; + case 61: + return PERIPH_ID_I2C2; + case 63: + return PERIPH_ID_I2C3; + case 64: + return PERIPH_ID_I2C4; + case 65: + return PERIPH_ID_I2C5; + } +#endif + + return -ENOENT; +} + +static int rk3188_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk3188_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + return rk3188_pinctrl_request(dev, func, 0); +} + +#ifndef CONFIG_SPL_BUILD +int rk3188_pinctrl_get_pin_info(struct rk3188_pinctrl_priv *priv, + int banknum, int ind, u32 **addrp, uint *shiftp, + uint *maskp) +{ + struct rockchip_pin_bank *bank = &rk3188_pin_banks[banknum]; + uint muxnum; + u32 *addr; + + for (muxnum = 0; muxnum < 4; muxnum++) { + struct rockchip_iomux *mux = &bank->iomux[muxnum]; + + if (ind >= 8) { + ind -= 8; + continue; + } + + addr = &priv->grf->gpio0c_iomux - 2; + addr += mux->offset; + *shiftp = ind & 7; + *maskp = 3; + *shiftp *= 2; + + debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr, + *maskp, *shiftp); + *addrp = addr; + return 0; + } + + return -EINVAL; +} + +static int rk3188_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, + int index) +{ + struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); + uint shift; + uint mask; + u32 *addr; + int ret; + + ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift, + &mask); + if (ret) + return ret; + return (readl(addr) & mask) >> shift; +} + +static int rk3188_pinctrl_set_pins(struct udevice *dev, int banknum, int index, + int muxval, int flags) +{ + struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); + uint shift, ind = index; + uint mask; + u32 *addr; + int ret; + + debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags); + ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift, + &mask); + if (ret) + return ret; + rk_clrsetreg(addr, mask << shift, muxval << shift); + + /* Handle pullup/pulldown */ + if (flags) { + uint val = 0; + + if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP)) + val = 1; + else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) + val = 2; + + ind = index >> 3; + + if (banknum == 0 && index < 12) { + addr = &priv->pmu->gpio0_p[ind]; + shift = (index & 7) * 2; + } else if (banknum == 0 && index >= 12) { + addr = &priv->grf->gpio0_p[ind - 1]; + /* + * The bits in the grf-registers have an inverse + * ordering with the lowest pin being in bits 15:14 + * and the highest pin in bits 1:0 . + */ + shift = (7 - (index & 7)) * 2; + } else { + addr = &priv->grf->gpio1_p[banknum - 1][ind]; + shift = (7 - (index & 7)) * 2; + } + debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val, + shift); + rk_clrsetreg(addr, 3 << shift, val << shift); + } + + return 0; +} + +static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + const void *blob = gd->fdt_blob; + int pcfg_node, ret, flags, count, i; + u32 cell[60], *ptr; + + debug("%s: %s %s\n", __func__, dev->name, config->name); + ret = fdtdec_get_int_array_count(blob, config->of_offset, + "rockchip,pins", cell, + ARRAY_SIZE(cell)); + if (ret < 0) { + debug("%s: bad array %d\n", __func__, ret); + return -EINVAL; + } + count = ret; + for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) { + pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]); + if (pcfg_node < 0) + return -EINVAL; + flags = pinctrl_decode_pin_config(blob, pcfg_node); + if (flags < 0) + return flags; + + ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2], + flags); + if (ret) + return ret; + } + + return 0; +} +#endif + +static struct pinctrl_ops rk3188_pinctrl_ops = { +#ifndef CONFIG_SPL_BUILD + .set_state = rk3188_pinctrl_set_state, + .get_gpio_mux = rk3188_pinctrl_get_gpio_mux, +#endif + .set_state_simple = rk3188_pinctrl_set_state_simple, + .request = rk3188_pinctrl_request, + .get_periph_id = rk3188_pinctrl_get_periph_id, +}; + +#ifndef CONFIG_SPL_BUILD +static int rk3188_pinctrl_parse_tables(struct rk3188_pinctrl_priv *priv, + struct rockchip_pin_bank *banks, + int count) +{ + struct rockchip_pin_bank *bank; + uint reg, muxnum, banknum; + + reg = 0; + for (banknum = 0; banknum < count; banknum++) { + bank = &banks[banknum]; + bank->reg = reg; + debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4); + for (muxnum = 0; muxnum < 4; muxnum++) { + struct rockchip_iomux *mux = &bank->iomux[muxnum]; + + mux->offset = reg; + reg += 1; + } + } + + return 0; +} +#endif + +static int rk3188_pinctrl_probe(struct udevice *dev) +{ + struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); + int ret = 0; + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); + debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu); +#ifndef CONFIG_SPL_BUILD + ret = rk3188_pinctrl_parse_tables(priv, rk3188_pin_banks, + ARRAY_SIZE(rk3188_pin_banks)); +#endif + + return ret; +} + +static const struct udevice_id rk3188_pinctrl_ids[] = { + { .compatible = "rockchip,rk3188-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3188) = { + .name = "rockchip_rk3188_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3188_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk3188_pinctrl_priv), + .ops = &rk3188_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rk3188_pinctrl_probe, +}; -- cgit v1.3.1 From 37c07c5b1ff89a75581a236d1536b0584d2f74c0 Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Sat, 18 Feb 2017 19:46:32 +0100 Subject: rockchip: rk3188: Add sysreset driver Driver for the sysreset of Rockchip rk3188 socs. Signed-off-by: Heiko Stuebner Reviewed-by: Simon Glass Tested-by: Kever Yang --- drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_rk3188.c | 47 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 drivers/sysreset/sysreset_rk3188.c (limited to 'drivers') diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 21bcc216274..e00b0f3fe0d 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_SYSRESET) += sysreset-uclass.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o endif +obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o diff --git a/drivers/sysreset/sysreset_rk3188.c b/drivers/sysreset/sysreset_rk3188.c new file mode 100644 index 00000000000..36ae47600a5 --- /dev/null +++ b/drivers/sysreset/sysreset_rk3188.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int rk3188_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rk3188_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case SYSRESET_WARM: + rk_clrreg(&cru->cru_mode_con, 0xffff); + writel(0xeca8, &cru->cru_glb_srst_snd_value); + break; + case SYSRESET_COLD: + rk_clrreg(&cru->cru_mode_con, 0xffff); + writel(0xfdb9, &cru->cru_glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rk3188_sysreset = { + .request = rk3188_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rk3188) = { + .name = "rk3188_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3188_sysreset, +}; -- cgit v1.3.1 From dcdd32788a03bd5e6dde79384eef0217a8e14b71 Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Sat, 18 Feb 2017 19:46:34 +0100 Subject: rockchip: rk3188: Add clock driver Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3188. Signed-off-by: Heiko Stuebner Reviewed-by: Simon Glass Tested-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 191 +++++++++ drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rk3188.c | 527 ++++++++++++++++++++++++ 3 files changed, 719 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3188.h create mode 100644 drivers/clk/rockchip/clk_rk3188.c (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h new file mode 100644 index 00000000000..74f0fedcc64 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2016 Heiko Stuebner + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK3188_H +#define _ASM_ARCH_CRU_RK3188_H + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (1608 * 1000000) +#define GPLL_HZ (594 * 1000000) +#define CPLL_HZ (384 * 1000000) + +/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */ +#define CPU_ACLK_HZ 297000000 +#define CPU_HCLK_HZ 148500000 +#define CPU_PCLK_HZ 74250000 +#define CPU_H2P_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3188_clk_priv { + struct rk3188_grf *grf; + struct rk3188_cru *cru; + ulong rate; + bool has_bwadj; +}; + +struct rk3188_cru { + struct rk3188_pll { + u32 con0; + u32 con1; + u32 con2; + u32 con3; + } pll[4]; + u32 cru_mode_con; + u32 cru_clksel_con[35]; + u32 cru_clkgate_con[10]; + u32 reserved1[2]; + u32 cru_glb_srst_fst_value; + u32 cru_glb_srst_snd_value; + u32 reserved2[2]; + u32 cru_softrst_con[9]; + u32 cru_misc_con; + u32 reserved3[2]; + u32 cru_glb_cnt_th; +}; +check_member(rk3188_cru, cru_glb_cnt_th, 0x0140); + +/* CRU_CLKSEL0_CON */ +enum { + /* a9_core_div: core = core_src / (a9_core_div + 1) */ + A9_CORE_DIV_SHIFT = 9, + A9_CORE_DIV_MASK = 0x1f, + CORE_PLL_SHIFT = 8, + CORE_PLL_MASK = 1, + CORE_PLL_SELECT_APLL = 0, + CORE_PLL_SELECT_GPLL, + + /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */ + CORE_PERI_DIV_SHIFT = 6, + CORE_PERI_DIV_MASK = 3, + + /* aclk_cpu pll selection */ + CPU_ACLK_PLL_SHIFT = 5, + CPU_ACLK_PLL_MASK = 1, + CPU_ACLK_PLL_SELECT_APLL = 0, + CPU_ACLK_PLL_SELECT_GPLL, + + /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */ + A9_CPU_DIV_SHIFT = 0, + A9_CPU_DIV_MASK = 0x1f, +}; + +/* CRU_CLKSEL1_CON */ +enum { + /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */ + AHB2APB_DIV_SHIFT = 14, + AHB2APB_DIV_MASK = 3, + + /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */ + CPU_PCLK_DIV_SHIFT = 12, + CPU_PCLK_DIV_MASK = 3, + + /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */ + CPU_HCLK_DIV_SHIFT = 8, + CPU_HCLK_DIV_MASK = 3, + + /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */ + CORE_ACLK_DIV_SHIFT = 3, + CORE_ACLK_DIV_MASK = 7, +}; + +/* CRU_CLKSEL10_CON */ +enum { + PERI_SEL_PLL_MASK = 1, + PERI_SEL_PLL_SHIFT = 15, + PERI_SEL_CPLL = 0, + PERI_SEL_GPLL, + + /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */ + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 3, + + /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */ + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3, + + /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */ + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f, +}; +/* CRU_CLKSEL11_CON */ +enum { + HSICPHY_DIV_SHIFT = 8, + HSICPHY_DIV_MASK = 0x3f, + + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x3f, +}; + +/* CRU_CLKSEL12_CON */ +enum { + UART_PLL_SHIFT = 15, + UART_PLL_MASK = 1, + UART_PLL_SELECT_GENERAL = 0, + UART_PLL_SELECT_CODEC, + + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0x3f, + + SDIO_DIV_SHIFT = 0, + SDIO_DIV_MASK = 0x3f, +}; + +/* CRU_CLKSEL25_CON */ +enum { + SPI1_DIV_SHIFT = 8, + SPI1_DIV_MASK = 0x7f, + + SPI0_DIV_SHIFT = 0, + SPI0_DIV_MASK = 0x7f, +}; + +/* CRU_MODE_CON */ +enum { + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 3, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORMAL, + GPLL_MODE_DEEP, + + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = 3, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORMAL, + CPLL_MODE_DEEP, + + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 3, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORMAL, + DPLL_MODE_DEEP, + + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 3, + APLL_MODE_SLOW = 0, + APLL_MODE_NORMAL, + APLL_MODE_DEEP, +}; + +/* CRU_APLL_CON0 */ +enum { + CLKR_SHIFT = 8, + CLKR_MASK = 0x3f, + + CLKOD_SHIFT = 0, + CLKOD_MASK = 0x3f, +}; + +/* CRU_APLL_CON1 */ +enum { + CLKF_SHIFT = 0, + CLKF_MASK = 0x1fff, +}; + +#endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 1f8e41739d6..b66e81e810a 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -5,5 +5,6 @@ # obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c new file mode 100644 index 00000000000..459649f7248 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -0,0 +1,527 @@ +/* + * (C) Copyright 2015 Google, Inc + * (C) Copyright 2016 Heiko Stuebner + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum rk3188_clk_type { + RK3188_CRU, + RK3188A_CRU, +}; + +struct rk3188_clk_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3188_cru dtd; +#endif +}; + +struct pll_div { + u32 nr; + u32 nf; + u32 no; +}; + +enum { + VCO_MAX_HZ = 2200U * 1000000, + VCO_MIN_HZ = 440 * 1000000, + OUTPUT_MAX_HZ = 2200U * 1000000, + OUTPUT_MIN_HZ = 30 * 1000000, + FREF_MAX_HZ = 2200U * 1000000, + FREF_MIN_HZ = 30 * 1000, +}; + +enum { + /* PLL CON0 */ + PLL_OD_MASK = 0x0f, + + /* PLL CON1 */ + PLL_NF_MASK = 0x1fff, + + /* PLL CON2 */ + PLL_BWADJ_MASK = 0x0fff, + + /* PLL CON3 */ + PLL_RESET_SHIFT = 5, + + /* GRF_SOC_STATUS0 */ + SOCSTS_DPLL_LOCK = 1 << 5, + SOCSTS_APLL_LOCK = 1 << 6, + SOCSTS_CPLL_LOCK = 1 << 7, + SOCSTS_GPLL_LOCK = 1 << 8, +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _nr, _no) {\ + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)); + +/* Keep divisors as low as possible to reduce jitter and power usage */ +#ifdef CONFIG_SPL_BUILD +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); +#endif + +static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div, bool has_bwadj) +{ + int pll_id = rk_pll_id(clk_id); + struct rk3188_pll *pll = &cru->pll[pll_id]; + /* All PLLs have same VCO and output frequency range restrictions. */ + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; + uint output_hz = vco_hz / div->no; + + debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", + (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && + (div->no == 1 || !(div->no % 2))); + + /* enter reset */ + rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); + + rk_clrsetreg(&pll->con0, + CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK, + ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); + rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); + + if (has_bwadj) + rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); + + udelay(10); + + /* return from reset */ + rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); + + return 0; +} + +static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, + unsigned int hz, bool has_bwadj) +{ + static const struct pll_div dpll_cfg[] = { + {.nf = 25, .nr = 2, .no = 1}, + {.nf = 400, .nr = 9, .no = 2}, + {.nf = 500, .nr = 9, .no = 2}, + {.nf = 100, .nr = 3, .no = 1}, + }; + int cfg; + + switch (hz) { + case 300000000: + cfg = 0; + break; + case 533000000: /* actually 533.3P MHz */ + cfg = 1; + break; + case 666000000: /* actually 666.6P MHz */ + cfg = 2; + break; + case 800000000: + cfg = 3; + break; + default: + debug("Unsupported SDRAM frequency"); + return -EINVAL; + } + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW << DPLL_MODE_SHIFT); + + rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); + + /* wait for pll lock */ + while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) + udelay(1); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); + + return 0; +} + +/* Get pll rate by id */ +static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru, + enum rk_clk_id clk_id) +{ + uint32_t nr, no, nf; + uint32_t con; + int pll_id = rk_pll_id(clk_id); + struct rk3188_pll *pll = &cru->pll[pll_id]; + static u8 clk_shift[CLK_COUNT] = { + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, + GPLL_MODE_SHIFT + }; + uint shift; + + con = readl(&cru->cru_mode_con); + shift = clk_shift[clk_id]; + switch ((con >> shift) & APLL_MODE_MASK) { + case APLL_MODE_SLOW: + return OSC_HZ; + case APLL_MODE_NORMAL: + /* normal mode */ + con = readl(&pll->con0); + no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1; + nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; + con = readl(&pll->con1); + nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1; + + return (24 * nf / (nr * no)) * 1000000; + case APLL_MODE_DEEP: + default: + return 32768; + } +} + +static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate, + int periph) +{ + uint div; + u32 con; + + switch (periph) { + case HCLK_EMMC: + con = readl(&cru->cru_clksel_con[12]); + div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + break; + case HCLK_SDMMC: + con = readl(&cru->cru_clksel_con[11]); + div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + break; + case HCLK_SDIO: + con = readl(&cru->cru_clksel_con[12]); + div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK; + break; + default: + return -EINVAL; + } + + return DIV_TO_RATE(gclk_rate, div); +} + +static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate, + int periph, uint freq) +{ + int src_clk_div; + + debug("%s: gclk_rate=%u\n", __func__, gclk_rate); + src_clk_div = RATE_TO_DIV(gclk_rate, freq); + assert(src_clk_div <= 0x3f); + + switch (periph) { + case HCLK_EMMC: + rk_clrsetreg(&cru->cru_clksel_con[12], + EMMC_DIV_MASK << EMMC_DIV_SHIFT, + src_clk_div << EMMC_DIV_SHIFT); + break; + case HCLK_SDMMC: + rk_clrsetreg(&cru->cru_clksel_con[11], + MMC0_DIV_MASK << MMC0_DIV_SHIFT, + src_clk_div << MMC0_DIV_SHIFT); + break; + case HCLK_SDIO: + rk_clrsetreg(&cru->cru_clksel_con[12], + SDIO_DIV_MASK << SDIO_DIV_SHIFT, + src_clk_div << SDIO_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_mmc_get_clk(cru, gclk_rate, periph); +} + +static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate, + int periph) +{ + uint div; + u32 con; + + switch (periph) { + case SCLK_SPI0: + con = readl(&cru->cru_clksel_con[25]); + div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK; + break; + case SCLK_SPI1: + con = readl(&cru->cru_clksel_con[25]); + div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK; + break; + default: + return -EINVAL; + } + + return DIV_TO_RATE(gclk_rate, div); +} + +static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate, + int periph, uint freq) +{ + int src_clk_div = RATE_TO_DIV(gclk_rate, freq); + + switch (periph) { + case SCLK_SPI0: + assert(src_clk_div <= SPI0_DIV_MASK); + rk_clrsetreg(&cru->cru_clksel_con[25], + SPI0_DIV_MASK << SPI0_DIV_SHIFT, + src_clk_div << SPI0_DIV_SHIFT); + break; + case SCLK_SPI1: + assert(src_clk_div <= SPI1_DIV_MASK); + rk_clrsetreg(&cru->cru_clksel_con[25], + SPI1_DIV_MASK << SPI1_DIV_SHIFT, + src_clk_div << SPI1_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_spi_get_clk(cru, gclk_rate, periph); +} + +#ifdef CONFIG_SPL_BUILD +static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf, + bool has_bwadj) +{ + u32 aclk_div, hclk_div, pclk_div, h2p_div; + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK << GPLL_MODE_SHIFT | + CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_SLOW << GPLL_MODE_SHIFT | + CPLL_MODE_SLOW << CPLL_MODE_SHIFT); + + /* init pll */ + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj); + rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj); + + /* waiting for pll lock */ + while ((readl(&grf->soc_status0) & + (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != + (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) + udelay(1); + + /* + * cpu clock pll source selection and + * reparent aclk_cpu_pre from apll to gpll + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ); + assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT | + A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT, + CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT | + aclk_div << A9_CPU_DIV_SHIFT); + + hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ); + assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3); + pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ); + assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4); + h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ); + assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3); + + rk_clrsetreg(&cru->cru_clksel_con[1], + AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT | + CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT | + CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT, + h2p_div << AHB2APB_DIV_SHIFT | + pclk_div << CPU_PCLK_DIV_SHIFT | + hclk_div << CPU_HCLK_DIV_SHIFT); + + /* + * peri clock pll source selection and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); + assert((1 << hclk_div) * PERI_HCLK_HZ == + PERI_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); + assert((1 << pclk_div) * PERI_PCLK_HZ == + PERI_ACLK_HZ && (pclk_div < 0x4)); + + rk_clrsetreg(&cru->cru_clksel_con[10], + PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | + PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | + PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | + pclk_div << PERI_PCLK_DIV_SHIFT | + hclk_div << PERI_HCLK_DIV_SHIFT | + aclk_div << PERI_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK << GPLL_MODE_SHIFT | + CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | + CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); + + rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000); +} +#endif + +static ulong rk3188_clk_get_rate(struct clk *clk) +{ + struct rk3188_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate, gclk_rate; + + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); + switch (clk->id) { + case 1 ... 4: + new_rate = rkclk_pll_get_rate(priv->cru, clk->id); + break; + case HCLK_EMMC: + case HCLK_SDMMC: + case HCLK_SDIO: + new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ, + clk->id); + break; + case SCLK_SPI0: + case SCLK_SPI1: + new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ, + clk->id); + break; + case PCLK_I2C0: + case PCLK_I2C1: + case PCLK_I2C2: + case PCLK_I2C3: + case PCLK_I2C4: + return gclk_rate; + default: + return -ENOENT; + } + + return new_rate; +} + +static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3188_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3188_cru *cru = priv->cru; + ulong new_rate; + + switch (clk->id) { + case CLK_DDR: + new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, + priv->has_bwadj); + break; + case HCLK_EMMC: + case HCLK_SDMMC: + case HCLK_SDIO: + new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, + clk->id, rate); + break; + case SCLK_SPI0: + case SCLK_SPI1: + new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ, + clk->id, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static struct clk_ops rk3188_clk_ops = { + .get_rate = rk3188_clk_get_rate, + .set_rate = rk3188_clk_set_rate, +}; + +static int rk3188_clk_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3188_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rk3188_cru *)dev_get_addr(dev); +#endif + + return 0; +} + +static int rk3188_clk_probe(struct udevice *dev) +{ + struct rk3188_clk_priv *priv = dev_get_priv(dev); + enum rk3188_clk_type type = dev_get_driver_data(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(priv->grf)) + return PTR_ERR(priv->grf); + priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0; + +#ifdef CONFIG_SPL_BUILD +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3188_clk_plat *plat = dev_get_platdata(dev); + + priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); +#endif + + rkclk_init(priv->cru, priv->grf, priv->has_bwadj); +#endif + + return 0; +} + +static int rk3188_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk3188_sysreset", "reset", &dev); + if (ret) + debug("Warning: No rk3188 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rk3188_clk_ids[] = { + { .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU }, + { .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3188_cru) = { + .name = "rockchip_rk3188_cru", + .id = UCLASS_CLK, + .of_match = rk3188_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3188_clk_priv), + .platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat), + .ops = &rk3188_clk_ops, + .bind = rk3188_clk_bind, + .ofdata_to_platdata = rk3188_clk_ofdata_to_platdata, + .probe = rk3188_clk_probe, +}; -- cgit v1.3.1 From 41793000d77172a7472aad256049473c00e29dc5 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 23 Feb 2017 15:37:52 +0800 Subject: rockchip: rk3328: add clock driver Add rk3328 clock driver and cru structure definition. Signed-off-by: William Zhang Signed-off-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 70 +++ arch/arm/mach-rockchip/rk3328/Makefile | 1 + arch/arm/mach-rockchip/rk3328/clk_rk3328.c | 31 ++ drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rk3328.c | 581 ++++++++++++++++++++++++ 5 files changed, 684 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3328.h create mode 100644 arch/arm/mach-rockchip/rk3328/clk_rk3328.c create mode 100644 drivers/clk/rockchip/clk_rk3328.c (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h new file mode 100644 index 00000000000..948706e9a38 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CRU_RK3328_H_ +#define __ASM_ARCH_CRU_RK3328_H_ + +#include + +struct rk3328_clk_priv { + struct rk3328_cru *cru; + ulong rate; +}; + +struct rk3328_cru { + u32 apll_con[5]; + u32 reserved1[3]; + u32 dpll_con[5]; + u32 reserved2[3]; + u32 cpll_con[5]; + u32 reserved3[3]; + u32 gpll_con[5]; + u32 reserved4[3]; + u32 mode_con; + u32 misc; + u32 reserved5[2]; + u32 glb_cnt_th; + u32 glb_rst_st; + u32 glb_srst_snd_value; + u32 glb_srst_fst_value; + u32 npll_con[5]; + u32 reserved6[(0x100 - 0xb4) / 4]; + u32 clksel_con[53]; + u32 reserved7[(0x200 - 0x1d4) / 4]; + u32 clkgate_con[29]; + u32 reserved8[3]; + u32 ssgtbl[32]; + u32 softrst_con[12]; + u32 reserved9[(0x380 - 0x330) / 4]; + u32 sdmmc_con[2]; + u32 sdio_con[2]; + u32 emmc_con[2]; + u32 sdmmc_ext_con[2]; +}; +check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (576 * MHz) +#define CPLL_HZ (594 * MHz) + +#define CLK_CORE_HZ (600 * MHz) +#define ACLKM_CORE_HZ (300 * MHz) +#define PCLK_DBG_HZ (300 * MHz) + +#define PERIHP_ACLK_HZ (144000 * KHz) +#define PERIHP_HCLK_HZ (72000 * KHz) +#define PERIHP_PCLK_HZ (72000 * KHz) + +#define PWM_CLOCK_HZ (74 * MHz) + +enum apll_frequencies { + APLL_816_MHZ, + APLL_600_MHZ, +}; + +#endif /* __ASM_ARCH_CRU_RK3328_H_ */ diff --git a/arch/arm/mach-rockchip/rk3328/Makefile b/arch/arm/mach-rockchip/rk3328/Makefile index 8ecf8eed1c9..bbab036a12a 100644 --- a/arch/arm/mach-rockchip/rk3328/Makefile +++ b/arch/arm/mach-rockchip/rk3328/Makefile @@ -4,5 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += clk_rk3328.o obj-y += rk3328.o obj-y += syscon_rk3328.o diff --git a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c new file mode 100644 index 00000000000..1205516227f --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3328_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3328_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_addr_ptr(dev); + + return priv->cru; +} diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index b66e81e810a..1091a76f055 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o +obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c new file mode 100644 index 00000000000..0ff1e30bb59 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -0,0 +1,581 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ + .refdiv = _refdiv,\ + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; + +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1); + +static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1); +static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1); + +static const struct pll_div *apll_cfgs[] = { + [APLL_816_MHZ] = &apll_816_cfg, + [APLL_600_MHZ] = &apll_600_cfg, +}; + +enum { + /* PLL_CON0 */ + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLL_CON1 */ + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_INTEGER_MODE = 1, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* PLL_CON2 */ + PLL_FRACDIV_SHIFT = 0, + PLL_FRACDIV_MASK = 0xffffff, + + /* MODE_CON */ + APLL_MODE_SHIFT = 0, + NPLL_MODE_SHIFT = 1, + DPLL_MODE_SHIFT = 4, + CPLL_MODE_SHIFT = 8, + GPLL_MODE_SHIFT = 12, + PLL_MODE_SLOW = 0, + PLL_MODE_NORM, + + /* CLKSEL_CON0 */ + CLK_CORE_PLL_SEL_APLL = 0, + CLK_CORE_PLL_SEL_GPLL, + CLK_CORE_PLL_SEL_DPLL, + CLK_CORE_PLL_SEL_NPLL, + CLK_CORE_PLL_SEL_SHIFT = 6, + CLK_CORE_PLL_SEL_MASK = 3 << CLK_CORE_PLL_SEL_SHIFT, + CLK_CORE_DIV_SHIFT = 0, + CLK_CORE_DIV_MASK = 0x1f, + + /* CLKSEL_CON1 */ + ACLKM_CORE_DIV_SHIFT = 4, + ACLKM_CORE_DIV_MASK = 0x7 << ACLKM_CORE_DIV_SHIFT, + PCLK_DBG_DIV_SHIFT = 0, + PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT, + + /* CLKSEL_CON28 */ + ACLK_PERIHP_PLL_SEL_CPLL = 0, + ACLK_PERIHP_PLL_SEL_GPLL, + ACLK_PERIHP_PLL_SEL_HDMIPHY, + ACLK_PERIHP_PLL_SEL_SHIFT = 6, + ACLK_PERIHP_PLL_SEL_MASK = 3 << ACLK_PERIHP_PLL_SEL_SHIFT, + ACLK_PERIHP_DIV_CON_SHIFT = 0, + ACLK_PERIHP_DIV_CON_MASK = 0x1f, + + /* CLKSEL_CON29 */ + PCLK_PERIHP_DIV_CON_SHIFT = 4, + PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, + HCLK_PERIHP_DIV_CON_SHIFT = 0, + HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, + + /* CLKSEL_CON22 */ + CLK_TSADC_DIV_CON_SHIFT = 0, + CLK_TSADC_DIV_CON_MASK = 0x3ff, + + /* CLKSEL_CON23 */ + CLK_SARADC_DIV_CON_SHIFT = 0, + CLK_SARADC_DIV_CON_MASK = 0x3ff << CLK_SARADC_DIV_CON_SHIFT, + + /* CLKSEL_CON24 */ + CLK_PWM_PLL_SEL_CPLL = 0, + CLK_PWM_PLL_SEL_GPLL, + CLK_PWM_PLL_SEL_SHIFT = 15, + CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT, + CLK_PWM_DIV_CON_SHIFT = 8, + CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, + + CLK_SPI_PLL_SEL_CPLL = 0, + CLK_SPI_PLL_SEL_GPLL, + CLK_SPI_PLL_SEL_SHIFT = 7, + CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT, + CLK_SPI_DIV_CON_SHIFT = 0, + CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, + + /* CLKSEL_CON30 */ + CLK_SDMMC_PLL_SEL_CPLL = 0, + CLK_SDMMC_PLL_SEL_GPLL, + CLK_SDMMC_PLL_SEL_24M, + CLK_SDMMC_PLL_SEL_USBPHY, + CLK_SDMMC_PLL_SHIFT = 8, + CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT, + CLK_SDMMC_DIV_CON_SHIFT = 0, + CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT, + + /* CLKSEL_CON32 */ + CLK_EMMC_PLL_SEL_CPLL = 0, + CLK_EMMC_PLL_SEL_GPLL, + CLK_EMMC_PLL_SEL_24M, + CLK_EMMC_PLL_SEL_USBPHY, + CLK_EMMC_PLL_SHIFT = 8, + CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT, + CLK_EMMC_DIV_CON_SHIFT = 0, + CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT, + + /* CLKSEL_CON34 */ + CLK_I2C_PLL_SEL_CPLL = 0, + CLK_I2C_PLL_SEL_GPLL, + CLK_I2C_DIV_CON_MASK = 0x7f, + CLK_I2C_PLL_SEL_MASK = 1, + CLK_I2C1_PLL_SEL_SHIFT = 15, + CLK_I2C1_DIV_CON_SHIFT = 8, + CLK_I2C0_PLL_SEL_SHIFT = 7, + CLK_I2C0_DIV_CON_SHIFT = 0, + + /* CLKSEL_CON35 */ + CLK_I2C3_PLL_SEL_SHIFT = 15, + CLK_I2C3_DIV_CON_SHIFT = 8, + CLK_I2C2_PLL_SEL_SHIFT = 7, + CLK_I2C2_DIV_CON_SHIFT = 0, +}; + +#define VCO_MAX_KHZ (3200 * (MHz / KHz)) +#define VCO_MIN_KHZ (800 * (MHz / KHz)) +#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) +#define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) + +/* + * the div restructions of pll in integer mode, these are defined in + * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 + */ +#define PLL_DIV_MIN 16 +#define PLL_DIV_MAX 3200 + +/* + * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): + * Formulas also embedded within the Fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 + * Where: + * FOUTVCO = Fractional PLL non-divided output frequency + * FOUTPOSTDIV = Fractional PLL divided output frequency + * (output of second post divider) + * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) + * REFDIV = Fractional PLL input reference clock divider + * FBDIV = Integer value programmed into feedback divide + * + */ +static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div) +{ + u32 *pll_con; + u32 mode_shift, mode_mask; + + pll_con = NULL; + mode_shift = 0; + switch (clk_id) { + case CLK_ARM: + pll_con = cru->apll_con; + mode_shift = APLL_MODE_SHIFT; + break; + case CLK_DDR: + pll_con = cru->dpll_con; + mode_shift = DPLL_MODE_SHIFT; + break; + case CLK_CODEC: + pll_con = cru->cpll_con; + mode_shift = CPLL_MODE_SHIFT; + break; + case CLK_GENERAL: + pll_con = cru->gpll_con; + mode_shift = GPLL_MODE_SHIFT; + break; + case CLK_NEW: + pll_con = cru->npll_con; + mode_shift = NPLL_MODE_SHIFT; + break; + default: + break; + } + mode_mask = 1 << mode_shift; + + /* All 8 PLLs have same VCO and output frequency range restrictions. */ + u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; + u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; + + debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \ + postdiv2=%d, vco=%u khz, output=%u khz\n", + pll_con, div->fbdiv, div->refdiv, div->postdiv1, + div->postdiv2, vco_khz, output_khz); + assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && + output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && + div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); + + /* + * When power on or changing PLL setting, + * we must force PLL into slow mode to ensure output stable clock. + */ + rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift); + + /* use integer mode */ + rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK, + PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); + + rk_clrsetreg(&pll_con[0], + PLL_FBDIV_MASK | PLL_POSTDIV1_MASK, + (div->fbdiv << PLL_FBDIV_SHIFT) | + (div->postdiv1 << PLL_POSTDIV1_SHIFT)); + rk_clrsetreg(&pll_con[1], + PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, + (div->postdiv2 << PLL_POSTDIV2_SHIFT) | + (div->refdiv << PLL_REFDIV_SHIFT)); + + /* waiting for pll lock */ + while (!(readl(&pll_con[1]) & (1 << PLL_LOCK_STATUS_SHIFT))) + udelay(1); + + /* pll enter normal mode */ + rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); +} + +static void rkclk_init(struct rk3328_cru *cru) +{ + u32 aclk_div; + u32 hclk_div; + u32 pclk_div; + + /* configure gpll cpll */ + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); + + /* configure perihp aclk, hclk, pclk */ + aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; + hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; + pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; + + rk_clrsetreg(&cru->clksel_con[28], + ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, + ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | + aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); + rk_clrsetreg(&cru->clksel_con[29], + PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK, + pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | + hclk_div << HCLK_PERIHP_DIV_CON_SHIFT); +} + +void rk3328_configure_cpu(struct rk3328_cru *cru, + enum apll_frequencies apll_freq) +{ + u32 clk_core_div; + u32 aclkm_div; + u32 pclk_dbg_div; + + rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]); + + clk_core_div = APLL_HZ / CLK_CORE_HZ - 1; + aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1; + pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1; + + rk_clrsetreg(&cru->clksel_con[0], + CLK_CORE_PLL_SEL_MASK | CLK_CORE_DIV_MASK, + CLK_CORE_PLL_SEL_APLL << CLK_CORE_PLL_SEL_SHIFT | + clk_core_div << CLK_CORE_DIV_SHIFT); + + rk_clrsetreg(&cru->clksel_con[1], + PCLK_DBG_DIV_MASK | ACLKM_CORE_DIV_MASK, + pclk_dbg_div << PCLK_DBG_DIV_SHIFT | + aclkm_div << ACLKM_CORE_DIV_SHIFT); +} + + +static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id) +{ + u32 div, con; + + switch (clk_id) { + case SCLK_I2C0: + con = readl(&cru->clksel_con[34]); + div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; + break; + case SCLK_I2C1: + con = readl(&cru->clksel_con[34]); + div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; + break; + case SCLK_I2C2: + con = readl(&cru->clksel_con[35]); + div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; + break; + case SCLK_I2C3: + con = readl(&cru->clksel_con[35]); + div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; + break; + default: + printf("do not support this i2c bus\n"); + return -EINVAL; + } + + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz) +{ + int src_clk_div; + + src_clk_div = GPLL_HZ / hz; + assert(src_clk_div - 1 < 127); + + switch (clk_id) { + case SCLK_I2C0: + rk_clrsetreg(&cru->clksel_con[34], + CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT, + (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT); + break; + case SCLK_I2C1: + rk_clrsetreg(&cru->clksel_con[34], + CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT, + (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT); + break; + case SCLK_I2C2: + rk_clrsetreg(&cru->clksel_con[35], + CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT, + (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT); + break; + case SCLK_I2C3: + rk_clrsetreg(&cru->clksel_con[35], + CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT, + (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT); + break; + default: + printf("do not support this i2c bus\n"); + return -EINVAL; + } + + return DIV_TO_RATE(GPLL_HZ, src_clk_div); +} + +static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id) +{ + u32 div, con, con_id; + + switch (clk_id) { + case HCLK_SDMMC: + con_id = 30; + break; + case HCLK_EMMC: + con_id = 32; + break; + default: + return -EINVAL; + } + con = readl(&cru->clksel_con[con_id]); + div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; + + if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT + == CLK_EMMC_PLL_SEL_24M) + return DIV_TO_RATE(OSC_HZ, div); + else + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru, + ulong clk_id, ulong set_rate) +{ + int src_clk_div; + u32 con_id; + + switch (clk_id) { + case HCLK_SDMMC: + con_id = 30; + break; + case HCLK_EMMC: + con_id = 32; + break; + default: + return -EINVAL; + } + /* Select clk_sdmmc/emmc source from GPLL by default */ + src_clk_div = GPLL_HZ / set_rate; + + if (src_clk_div > 127) { + /* use 24MHz source for 400KHz clock */ + src_clk_div = OSC_HZ / set_rate; + rk_clrsetreg(&cru->clksel_con[con_id], + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, + CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); + } else { + rk_clrsetreg(&cru->clksel_con[con_id], + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, + CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); + } + + return rk3328_mmc_get_clk(cru, clk_id); +} + +static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru) +{ + u32 div, con; + + con = readl(&cru->clksel_con[24]); + div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT; + + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz) +{ + u32 div = GPLL_HZ / hz; + + rk_clrsetreg(&cru->clksel_con[24], + CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK, + CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT | + (div - 1) << CLK_PWM_DIV_CON_SHIFT); + + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rk3328_clk_get_rate(struct clk *clk) +{ + struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + switch (clk->id) { + case 0 ... 29: + return 0; + case HCLK_SDMMC: + case HCLK_EMMC: + rate = rk3328_mmc_get_clk(priv->cru, clk->id); + break; + case SCLK_I2C0: + case SCLK_I2C1: + case SCLK_I2C2: + case SCLK_I2C3: + rate = rk3328_i2c_get_clk(priv->cru, clk->id); + break; + case SCLK_PWM: + rate = rk3328_pwm_get_clk(priv->cru); + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + switch (clk->id) { + case 0 ... 29: + return 0; + case HCLK_SDMMC: + case HCLK_EMMC: + ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate); + break; + case SCLK_I2C0: + case SCLK_I2C1: + case SCLK_I2C2: + case SCLK_I2C3: + ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate); + break; + case SCLK_PWM: + ret = rk3328_pwm_set_clk(priv->cru, rate); + break; + default: + return -ENOENT; + } + + return ret; +} + +static struct clk_ops rk3328_clk_ops = { + .get_rate = rk3328_clk_get_rate, + .set_rate = rk3328_clk_set_rate, +}; + +static int rk3328_clk_probe(struct udevice *dev) +{ + struct rk3328_clk_priv *priv = dev_get_priv(dev); + + rkclk_init(priv->cru); + + return 0; +} + +static int rk3328_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct rk3328_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rk3328_cru *)dev_get_addr(dev); + + return 0; +} + +static int rk3328_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk3328_sysreset", "reset", &dev); + if (ret) + printf("Warning: No RK3328 reset driver: ret=%d\n", ret); + + return ret; +} + +static const struct udevice_id rk3328_clk_ids[] = { + { .compatible = "rockchip,rk3328-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3328_cru) = { + .name = "rockchip_rk3328_cru", + .id = UCLASS_CLK, + .of_match = rk3328_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3328_clk_priv), + .ofdata_to_platdata = rk3328_clk_ofdata_to_platdata, + .ops = &rk3328_clk_ops, + .bind = rk3328_clk_bind, + .probe = rk3328_clk_probe, +}; -- cgit v1.3.1 From d439a46e46ab092bb6f0f16bead1a25b70b1a55b Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 23 Feb 2017 15:37:53 +0800 Subject: rockchip: rk3328: add pinctrl driver Add rk3328 pinctrl driver and grf/iomux structure definition. Signed-off-by: William Zhang Signed-off-by: Kever Yang Acked-by: Simon Glass --- arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 134 ++++++++ drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3328.c | 419 ++++++++++++++++++++++++ 4 files changed, 563 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3328.h create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3328.c (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h new file mode 100644 index 00000000000..2776cefbb26 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SOC_ROCKCHIP_RK3328_GRF_H__ +#define __SOC_ROCKCHIP_RK3328_GRF_H__ + +struct rk3328_grf_regs { + u32 gpio0a_iomux; + u32 gpio0b_iomux; + u32 gpio0c_iomux; + u32 gpio0d_iomux; + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + u32 gpio2a_iomux; + u32 gpio2bl_iomux; + u32 gpio2bh_iomux; + u32 gpio2cl_iomux; + u32 gpio2ch_iomux; + u32 gpio2d_iomux; + u32 gpio3al_iomux; + u32 gpio3ah_iomux; + u32 gpio3bl_iomux; + u32 gpio3bh_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + u32 com_iomux; + u32 reserved1[(0x100 - 0x54) / 4]; + + u32 gpio0a_p; + u32 gpio0b_p; + u32 gpio0c_p; + u32 gpio0d_p; + u32 gpio1a_p; + u32 gpio1b_p; + u32 gpio1c_p; + u32 gpio1d_p; + u32 gpio2a_p; + u32 gpio2b_p; + u32 gpio2c_p; + u32 gpio2d_p; + u32 gpio3a_p; + u32 gpio3b_p; + u32 gpio3c_p; + u32 gpio3d_p; + u32 reserved2[(0x200 - 0x140) / 4]; + u32 gpio0a_e; + u32 gpio0b_e; + u32 gpio0c_e; + u32 gpio0d_e; + u32 gpio1a_e; + u32 gpio1b_e; + u32 gpio1c_e; + u32 gpio1d_e; + u32 gpio2a_e; + u32 gpio2b_e; + u32 gpio2c_e; + u32 gpio2d_e; + u32 gpio3a_e; + u32 gpio3b_e; + u32 gpio3c_e; + u32 gpio3d_e; + u32 reserved3[(0x300 - 0x240) / 4]; + u32 gpio0l_sr; + u32 gpio0h_sr; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 gpio2l_sr; + u32 gpio2h_sr; + u32 gpio3l_sr; + u32 gpio3h_sr; + u32 reserved4[(0x380 - 0x320) / 4]; + u32 gpio0l_smt; + u32 gpio0h_smt; + u32 gpio1l_smt; + u32 gpio1h_smt; + u32 gpio2l_smt; + u32 gpio2h_smt; + u32 gpio3l_smt; + u32 gpio3h_smt; + u32 reserved5[(0x400 - 0x3a0) / 4]; + u32 soc_con[11]; + u32 reserved6[(0x480 - 0x42c) / 4]; + u32 soc_status[5]; + u32 reserved7[(0x4c0 - 0x494) / 4]; + u32 otg3_con[2]; + u32 reserved8[(0x500 - 0x4c8) / 4]; + u32 cpu_con[2]; + u32 reserved9[(0x520 - 0x508) / 4]; + u32 cpu_status[2]; + u32 reserved10[(0x5c8 - 0x528) / 4]; + u32 os_reg[8]; + u32 reserved11[(0x680 - 0x5e8) / 4]; + u32 sig_detect_con; + u32 reserved12[3]; + u32 sig_detect_status; + u32 reserved13[3]; + u32 sig_detect_status_clr; + u32 reserved14[3]; + + u32 sdmmc_det_counter; + u32 reserved15[(0x700 - 0x6b4) / 4]; + u32 host0_con[3]; + u32 reserved16[(0x880 - 0x70c) / 4]; + u32 otg_con0; + u32 reserved17[3]; + u32 host0_status; + u32 reserved18[(0x900 - 0x894) / 4]; + u32 mac_con[3]; + u32 reserved19[(0xb00 - 0x90c) / 4]; + u32 macphy_con[4]; + u32 macphy_status; +}; +check_member(rk3328_grf_regs, macphy_status, 0xb10); + +struct rk3328_sgrf_regs { + u32 soc_con[6]; + u32 reserved0[(0x100 - 0x18) / 4]; + u32 dmac_con[6]; + u32 reserved1[(0x180 - 0x118) / 4]; + u32 fast_boot_addr; + u32 reserved2[(0x200 - 0x184) / 4]; + u32 chip_fuse_con; + u32 reserved3[(0x280 - 0x204) / 4]; + u32 hdcp_key_reg[8]; + u32 hdcp_key_access_mask; +}; +check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0); + +#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */ diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 397fbe13316..2eab9bd2bef 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -157,6 +157,15 @@ config PINCTRL_AT91PIO4 This option is to enable the AT91 pinctrl driver for AT91 PIO4 controller which is available on SAMA5D2 SoC. +config ROCKCHIP_RK3328_PINCTRL + bool "Rockchip pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3328 SoCs. The driver + is controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + config ROCKCHIP_RK3399_PINCTRL bool "Rockchip pin control driver" depends on DM diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index cc99aeebb54..b0b698ac04a 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3188_PINCTRL) += pinctrl_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o +obj-$(CONFIG_ROCKCHIP_RK3328_PINCTRL) += pinctrl_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3399_PINCTRL) += pinctrl_rk3399.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c new file mode 100644 index 00000000000..5ca6782ccc1 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c @@ -0,0 +1,419 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3328_pinctrl_priv { + struct rk3328_grf_regs *grf; +}; + +enum { + /* GRF_GPIO0A_IOMUX */ + GRF_GPIO0A5_SEL_SHIFT = 10, + GRF_GPIO0A5_SEL_MASK = 3 << GRF_GPIO0A5_SEL_SHIFT, + GRF_I2C3_SCL = 2, + + GRF_GPIO0A6_SEL_SHIFT = 12, + GRF_GPIO0A6_SEL_MASK = 3 << GRF_GPIO0A6_SEL_SHIFT, + GRF_I2C3_SDA = 2, + + GRF_GPIO0A7_SEL_SHIFT = 14, + GRF_GPIO0A7_SEL_MASK = 3 << GRF_GPIO0A7_SEL_SHIFT, + GRF_EMMC_DATA0 = 2, + + /* GRF_GPIO1A_IOMUX */ + GRF_GPIO1A0_SEL_SHIFT = 0, + GRF_GPIO1A0_SEL_MASK = 0x3fff << GRF_GPIO1A0_SEL_SHIFT, + GRF_CARD_DATA_CLK_CMD_DETN = 0x1555, + + /* GRF_GPIO2A_IOMUX */ + GRF_GPIO2A0_SEL_SHIFT = 0, + GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT, + GRF_UART2_TX_M1 = 1, + + GRF_GPIO2A1_SEL_SHIFT = 2, + GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT, + GRF_UART2_RX_M1 = 1, + + GRF_GPIO2A2_SEL_SHIFT = 4, + GRF_GPIO2A2_SEL_MASK = 3 << GRF_GPIO2A2_SEL_SHIFT, + GRF_PWM_IR = 1, + + GRF_GPIO2A4_SEL_SHIFT = 8, + GRF_GPIO2A4_SEL_MASK = 3 << GRF_GPIO2A4_SEL_SHIFT, + GRF_PWM_0 = 1, + GRF_I2C1_SDA, + + GRF_GPIO2A5_SEL_SHIFT = 10, + GRF_GPIO2A5_SEL_MASK = 3 << GRF_GPIO2A5_SEL_SHIFT, + GRF_PWM_1 = 1, + GRF_I2C1_SCL, + + GRF_GPIO2A6_SEL_SHIFT = 12, + GRF_GPIO2A6_SEL_MASK = 3 << GRF_GPIO2A6_SEL_SHIFT, + GRF_PWM_2 = 1, + + GRF_GPIO2A7_SEL_SHIFT = 14, + GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT, + GRF_CARD_PWR_EN_M0 = 1, + + /* GRF_GPIO2BL_IOMUX */ + GRF_GPIO2BL0_SEL_SHIFT = 0, + GRF_GPIO2BL0_SEL_MASK = 0x3f << GRF_GPIO2BL0_SEL_SHIFT, + GRF_SPI_CLK_TX_RX_M0 = 0x15, + + GRF_GPIO2BL3_SEL_SHIFT = 6, + GRF_GPIO2BL3_SEL_MASK = 3 << GRF_GPIO2BL3_SEL_SHIFT, + GRF_SPI_CSN0_M0 = 1, + + GRF_GPIO2BL4_SEL_SHIFT = 8, + GRF_GPIO2BL4_SEL_MASK = 3 << GRF_GPIO2BL4_SEL_SHIFT, + GRF_SPI_CSN1_M0 = 1, + + GRF_GPIO2BL5_SEL_SHIFT = 10, + GRF_GPIO2BL5_SEL_MASK = 3 << GRF_GPIO2BL5_SEL_SHIFT, + GRF_I2C2_SDA = 1, + + GRF_GPIO2BL6_SEL_SHIFT = 12, + GRF_GPIO2BL6_SEL_MASK = 3 << GRF_GPIO2BL6_SEL_SHIFT, + GRF_I2C2_SCL = 1, + + /* GRF_GPIO2D_IOMUX */ + GRF_GPIO2D0_SEL_SHIFT = 0, + GRF_GPIO2D0_SEL_MASK = 3 << GRF_GPIO2D0_SEL_SHIFT, + GRF_I2C0_SCL = 1, + + GRF_GPIO2D1_SEL_SHIFT = 2, + GRF_GPIO2D1_SEL_MASK = 3 << GRF_GPIO2D1_SEL_SHIFT, + GRF_I2C0_SDA = 1, + + GRF_GPIO2D4_SEL_SHIFT = 8, + GRF_GPIO2D4_SEL_MASK = 0xff << GRF_GPIO2D4_SEL_SHIFT, + GRF_EMMC_DATA123 = 0xaa, + + /* GRF_GPIO3C_IOMUX */ + GRF_GPIO3C0_SEL_SHIFT = 0, + GRF_GPIO3C0_SEL_MASK = 0x3fff << GRF_GPIO3C0_SEL_SHIFT, + GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa, + + /* GRF_COM_IOMUX */ + GRF_UART2_IOMUX_SEL_SHIFT = 0, + GRF_UART2_IOMUX_SEL_MASK = 3 << GRF_UART2_IOMUX_SEL_SHIFT, + GRF_UART2_IOMUX_SEL_M0 = 0, + GRF_UART2_IOMUX_SEL_M1, + + GRF_SPI_IOMUX_SEL_SHIFT = 4, + GRF_SPI_IOMUX_SEL_MASK = 3 << GRF_SPI_IOMUX_SEL_SHIFT, + GRF_SPI_IOMUX_SEL_M0 = 0, + GRF_SPI_IOMUX_SEL_M1, + GRF_SPI_IOMUX_SEL_M2, + + GRF_CARD_IOMUX_SEL_SHIFT = 7, + GRF_CARD_IOMUX_SEL_MASK = 1 << GRF_CARD_IOMUX_SEL_SHIFT, + GRF_CARD_IOMUX_SEL_M0 = 0, + GRF_CARD_IOMUX_SEL_M1, +}; + +static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id) +{ + switch (pwm_id) { + case PERIPH_ID_PWM0: + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A4_SEL_MASK, + GRF_PWM_0 << GRF_GPIO2A4_SEL_SHIFT); + break; + case PERIPH_ID_PWM1: + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A5_SEL_MASK, + GRF_PWM_1 << GRF_GPIO2A5_SEL_SHIFT); + break; + case PERIPH_ID_PWM2: + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A6_SEL_MASK, + GRF_PWM_2 << GRF_GPIO2A6_SEL_SHIFT); + break; + case PERIPH_ID_PWM3: + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A2_SEL_MASK, + GRF_PWM_IR << GRF_GPIO2A2_SEL_SHIFT); + break; + default: + debug("pwm id = %d iomux error!\n", pwm_id); + break; + } +} + +static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&grf->gpio2d_iomux, + GRF_GPIO2D0_SEL_MASK | GRF_GPIO2D1_SEL_MASK, + GRF_I2C0_SCL << GRF_GPIO2D0_SEL_SHIFT + | GRF_I2C0_SDA << GRF_GPIO2D1_SEL_SHIFT); + break; + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A4_SEL_MASK | GRF_GPIO2A5_SEL_MASK, + GRF_I2C1_SCL << GRF_GPIO2A5_SEL_SHIFT + | GRF_I2C1_SDA << GRF_GPIO2A4_SEL_SHIFT); + break; + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio2bl_iomux, + GRF_GPIO2BL5_SEL_MASK | GRF_GPIO2BL6_SEL_MASK, + GRF_I2C2_SCL << GRF_GPIO2BL6_SEL_SHIFT + | GRF_I2C2_SDA << GRF_GPIO2BL6_SEL_SHIFT); + break; + case PERIPH_ID_I2C3: + rk_clrsetreg(&grf->gpio0a_iomux, + GRF_GPIO0A5_SEL_MASK | GRF_GPIO0A6_SEL_MASK, + GRF_I2C3_SCL << GRF_GPIO0A5_SEL_SHIFT + | GRF_I2C3_SDA << GRF_GPIO0A6_SEL_SHIFT); + break; + default: + debug("i2c id = %d iomux error!\n", i2c_id); + break; + } +} + +static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id) +{ + switch (lcd_id) { + case PERIPH_ID_LCDC0: + break; + default: + debug("lcdc id = %d iomux error!\n", lcd_id); + break; + } +} + +static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf, + enum periph_id spi_id, int cs) +{ + rk_clrsetreg(&grf->com_iomux, + GRF_SPI_IOMUX_SEL_MASK, + GRF_SPI_IOMUX_SEL_M0 << GRF_SPI_IOMUX_SEL_SHIFT); + + switch (spi_id) { + case PERIPH_ID_SPI0: + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio2bl_iomux, + GRF_GPIO2BL3_SEL_MASK, + GRF_SPI_CSN0_M0 << GRF_GPIO2BL3_SEL_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio2bl_iomux, + GRF_GPIO2BL4_SEL_MASK, + GRF_SPI_CSN1_M0 << GRF_GPIO2BL4_SEL_SHIFT); + break; + default: + goto err; + } + rk_clrsetreg(&grf->gpio2bl_iomux, + GRF_GPIO2BL0_SEL_MASK, + GRF_SPI_CLK_TX_RX_M0 << GRF_GPIO2BL0_SEL_SHIFT); + break; + default: + goto err; + } + + return 0; +err: + debug("rkspi: periph%d cs=%d not supported", spi_id, cs); + return -ENOENT; +} + +static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id) +{ + switch (uart_id) { + case PERIPH_ID_UART2: + break; + /* uart2 iomux select m1 */ + rk_clrsetreg(&grf->com_iomux, + GRF_UART2_IOMUX_SEL_MASK, + GRF_UART2_IOMUX_SEL_M1 + << GRF_UART2_IOMUX_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A0_SEL_MASK | GRF_GPIO2A1_SEL_MASK, + GRF_UART2_TX_M1 << GRF_GPIO2A0_SEL_SHIFT | + GRF_UART2_RX_M1 << GRF_GPIO2A1_SEL_SHIFT); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART3: + case PERIPH_ID_UART4: + default: + debug("uart id = %d iomux error!\n", uart_id); + break; + } +} + +static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf, + int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&grf->gpio0a_iomux, + GRF_GPIO0A7_SEL_MASK, + GRF_EMMC_DATA0 << GRF_GPIO0A7_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2d_iomux, + GRF_GPIO2D4_SEL_MASK, + GRF_EMMC_DATA123 << GRF_GPIO2D4_SEL_SHIFT); + rk_clrsetreg(&grf->gpio3c_iomux, + GRF_GPIO3C0_SEL_MASK, + GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD + << GRF_GPIO3C0_SEL_SHIFT); + break; + case PERIPH_ID_SDCARD: + /* sdcard iomux select m0 */ + rk_clrsetreg(&grf->com_iomux, + GRF_CARD_IOMUX_SEL_MASK, + GRF_CARD_IOMUX_SEL_M0 << GRF_CARD_IOMUX_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A7_SEL_MASK, + GRF_CARD_PWR_EN_M0 << GRF_GPIO2A7_SEL_SHIFT); + rk_clrsetreg(&grf->gpio1a_iomux, + GRF_GPIO1A0_SEL_MASK, + GRF_CARD_DATA_CLK_CMD_DETN + << GRF_GPIO1A0_SEL_SHIFT); + break; + default: + debug("mmc id = %d iomux error!\n", mmc_id); + break; + } +} + +static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk3328_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + pinctrl_rk3328_pwm_config(priv->grf, func); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + pinctrl_rk3328_i2c_config(priv->grf, func); + break; + case PERIPH_ID_SPI0: + pinctrl_rk3328_spi_config(priv->grf, func, flags); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + case PERIPH_ID_UART4: + pinctrl_rk3328_uart_config(priv->grf, func); + break; + case PERIPH_ID_LCDC0: + case PERIPH_ID_LCDC1: + pinctrl_rk3328_lcdc_config(priv->grf, func); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + pinctrl_rk3328_sdmmc_config(priv->grf, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk3328_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset, + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 49: + return PERIPH_ID_SPI0; + case 50: + return PERIPH_ID_PWM0; + case 36: + return PERIPH_ID_I2C0; + case 37: /* Note strange order */ + return PERIPH_ID_I2C1; + case 38: + return PERIPH_ID_I2C2; + case 39: + return PERIPH_ID_I2C3; + case 12: + return PERIPH_ID_SDCARD; + case 14: + return PERIPH_ID_EMMC; + } + + return -ENOENT; +} + +static int rk3328_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk3328_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + + return rk3328_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops rk3328_pinctrl_ops = { + .set_state_simple = rk3328_pinctrl_set_state_simple, + .request = rk3328_pinctrl_request, + .get_periph_id = rk3328_pinctrl_get_periph_id, +}; + +static int rk3328_pinctrl_probe(struct udevice *dev) +{ + struct rk3328_pinctrl_priv *priv = dev_get_priv(dev); + int ret = 0; + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + debug("%s: grf=%p\n", __func__, priv->grf); + + return ret; +} + +static const struct udevice_id rk3328_pinctrl_ids[] = { + { .compatible = "rockchip,rk3328-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3328) = { + .name = "rockchip_rk3328_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3328_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv), + .ops = &rk3328_pinctrl_ops, + .bind = dm_scan_fdt_dev, + .probe = rk3328_pinctrl_probe, +}; -- cgit v1.3.1 From 52f6c17ecb8f1f94f16f026518909337b474f34a Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 23 Feb 2017 15:37:54 +0800 Subject: rockchip: rk3328: add sysreset driver Add rk3328 sysreset driver. Signed-off-by: William Zhang Signed-off-by: Kever Yang Acked-by: Simon Glass --- drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_rk3328.c | 45 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 drivers/sysreset/sysreset_rk3328.c (limited to 'drivers') diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index e00b0f3fe0d..49b8bb61c63 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o endif obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o +obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o diff --git a/drivers/sysreset/sysreset_rk3328.c b/drivers/sysreset/sysreset_rk3328.c new file mode 100644 index 00000000000..7b9af0925b1 --- /dev/null +++ b/drivers/sysreset/sysreset_rk3328.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int rk3328_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rk3328_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case SYSRESET_WARM: + writel(0xeca8, &cru->glb_srst_snd_value); + break; + case SYSRESET_COLD: + writel(0xfdb9, &cru->glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rk3328_sysreset = { + .request = rk3328_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rk3328) = { + .name = "rk3328_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3328_sysreset, +}; -- cgit v1.3.1 From d905cf7365ad25c55129ce6bc473b67a642d7817 Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Thu, 23 Feb 2017 17:30:38 +0100 Subject: dm: Return actual bools in dm_fdt_pre_reloc Documentation says that we're returning true/false, not 1/0 so adapt the function to return actual booleans. Signed-off-by: Heiko Stuebner Acked-by: Simon Glass --- drivers/core/util.c | 12 ++++++------ include/dm/util.h | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/core/util.c b/drivers/core/util.c index bd4de7acd69..5ceac8bbb15 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -37,17 +37,17 @@ int list_count_items(struct list_head *head) return count; } -int dm_fdt_pre_reloc(const void *blob, int offset) +bool dm_fdt_pre_reloc(const void *blob, int offset) { if (fdt_getprop(blob, offset, "u-boot,dm-pre-reloc", NULL)) - return 1; + return true; #ifdef CONFIG_TPL_BUILD if (fdt_getprop(blob, offset, "u-boot,dm-tpl", NULL)) - return 1; + return true; #elif defined(CONFIG_SPL_BUILD) if (fdt_getprop(blob, offset, "u-boot,dm-spl", NULL)) - return 1; + return true; #else /* * In regular builds individual spl and tpl handling both @@ -55,8 +55,8 @@ int dm_fdt_pre_reloc(const void *blob, int offset) */ if (fdt_getprop(blob, offset, "u-boot,dm-spl", NULL) || fdt_getprop(blob, offset, "u-boot,dm-tpl", NULL)) - return 1; + return true; #endif - return 0; + return false; } diff --git a/include/dm/util.h b/include/dm/util.h index 32060ab30eb..45529ce0e6a 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -72,6 +72,6 @@ static inline void dm_dump_devres(void) * * Returns true if node is needed in SPL/TL, false otherwise. */ -int dm_fdt_pre_reloc(const void *blob, int offset); +bool dm_fdt_pre_reloc(const void *blob, int offset); #endif -- cgit v1.3.1 From a0a2774aebdaa039ce787090c903cf47263f04c9 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 9 Mar 2017 00:34:37 +0100 Subject: rockchip: video: Fix HDMI audio clocks Function hdmi_lookup_n_cts() is feed with clock in Hz, which gets compared with clocks in kHz. Fix that by converting all clocks to Hz. Signed-off-by: Jernej Skrabec Reviewed-by: Simon Glass --- drivers/video/rockchip/rk_hdmi.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 7b0c43b8581..274d1088511 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -32,37 +32,37 @@ struct rk_hdmi_priv { static const struct tmds_n_cts n_cts_table[] = { { - .tmds = 25175, .n = 6144, .cts = 25175, + .tmds = 25175000, .n = 6144, .cts = 25175, }, { - .tmds = 25200, .n = 6144, .cts = 25200, + .tmds = 25200000, .n = 6144, .cts = 25200, }, { - .tmds = 27000, .n = 6144, .cts = 27000, + .tmds = 27000000, .n = 6144, .cts = 27000, }, { - .tmds = 27027, .n = 6144, .cts = 27027, + .tmds = 27027000, .n = 6144, .cts = 27027, }, { - .tmds = 40000, .n = 6144, .cts = 40000, + .tmds = 40000000, .n = 6144, .cts = 40000, }, { - .tmds = 54000, .n = 6144, .cts = 54000, + .tmds = 54000000, .n = 6144, .cts = 54000, }, { - .tmds = 54054, .n = 6144, .cts = 54054, + .tmds = 54054000, .n = 6144, .cts = 54054, }, { - .tmds = 65000, .n = 6144, .cts = 65000, + .tmds = 65000000, .n = 6144, .cts = 65000, }, { - .tmds = 74176, .n = 11648, .cts = 140625, + .tmds = 74176000, .n = 11648, .cts = 140625, }, { - .tmds = 74250, .n = 6144, .cts = 74250, + .tmds = 74250000, .n = 6144, .cts = 74250, }, { - .tmds = 83500, .n = 6144, .cts = 83500, + .tmds = 83500000, .n = 6144, .cts = 83500, }, { - .tmds = 106500, .n = 6144, .cts = 106500, + .tmds = 106500000, .n = 6144, .cts = 106500, }, { - .tmds = 108000, .n = 6144, .cts = 108000, + .tmds = 108000000, .n = 6144, .cts = 108000, }, { - .tmds = 148352, .n = 5824, .cts = 140625, + .tmds = 148352000, .n = 5824, .cts = 140625, }, { - .tmds = 148500, .n = 6144, .cts = 148500, + .tmds = 148500000, .n = 6144, .cts = 148500, }, { - .tmds = 297000, .n = 5120, .cts = 247500, + .tmds = 297000000, .n = 5120, .cts = 247500, } }; -- cgit v1.3.1 From 520c174b3564ae183f0e7c118dc8ce3770ae20b0 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 9 Mar 2017 00:34:38 +0100 Subject: rockchip: video: Remove CSC initialization (HDMI) Despite the comment in the code, CSC unit is never used. According to the only public description of DW HDMI controller (i.MX6 manual), CSC unit is bypassed in MC_FLOWCTRL register and then actually powered down in MC_CLKDIS register. Signed-off-by: Jernej Skrabec Reviewed-by: Simon Glass --- drivers/video/rockchip/rk_hdmi.c | 39 --------------------------------------- 1 file changed, 39 deletions(-) (limited to 'drivers') diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 274d1088511..c8608db23cb 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -124,12 +124,6 @@ static const struct hdmi_mpll_config rockchip_mpll_cfg[] = { } }; -static const u32 csc_coeff_default[3][4] = { - { 0x2000, 0x0000, 0x0000, 0x0000 }, - { 0x0000, 0x2000, 0x0000, 0x0000 }, - { 0x0000, 0x0000, 0x2000, 0x0000 } -}; - static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 cts) { uint cts3; @@ -220,37 +214,6 @@ static void hdmi_video_sample(struct rk3288_hdmi *regs) writel(0x0, ®s->tx_bcbdata1); } -static void hdmi_update_csc_coeffs(struct rk3288_hdmi *regs) -{ - u32 i, j; - u32 csc_scale = 1; - - /* the csc registers are sequential, alternating msb then lsb */ - for (i = 0; i < ARRAY_SIZE(csc_coeff_default); i++) { - for (j = 0; j < ARRAY_SIZE(csc_coeff_default[0]); j++) { - u32 coeff = csc_coeff_default[i][j]; - writel(coeff >> 8, ®s->csc_coef[i][j].msb); - writel(coeff && 0xff, ®s->csc_coef[i][j].lsb); - } - } - - clrsetbits_le32(®s->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, - csc_scale); -} - -static void hdmi_video_csc(struct rk3288_hdmi *regs) -{ - u32 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; - u32 interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; - - /* configure the csc registers */ - writel(interpolation, ®s->csc_cfg); - clrsetbits_le32(®s->csc_scale, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth); - - hdmi_update_csc_coeffs(regs); -} - static void hdmi_video_packetize(struct rk3288_hdmi *regs) { u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; @@ -467,7 +430,6 @@ static int hdmi_phy_init(struct rk3288_hdmi *regs, uint mpixelclock) hdmi_phy_enable_tmds(regs, 0); hdmi_phy_enable_power(regs, 0); - /* enable csc */ ret = hdmi_phy_configure(regs, mpixelclock); if (ret) { debug("hdmi phy config failure %d\n", ret); @@ -837,7 +799,6 @@ static int rk_hdmi_enable(struct udevice *dev, int panel_bpp, hdmi_audio_set_samplerate(regs, edid->pixelclock.typ); hdmi_video_packetize(regs); - hdmi_video_csc(regs); hdmi_video_sample(regs); hdmi_clear_overflow(regs); -- cgit v1.3.1