From 3e326ece9eba8184f5d48aa4fb87760a8f6f0f10 Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Mon, 22 May 2006 16:33:54 +0200 Subject: This patch adds USB storage support for the delta board. This is the first board to make use of a generic OHCI driver, that calls hooks for board dependant initialization. --- include/asm-arm/arch-pxa/pxa-regs.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index ebda7192ed0..c47306cff28 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -592,9 +592,11 @@ typedef void (*ExcpHndlr) (void) ; #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ + /* * USB Device Controller */ +#ifndef CONFIG_CPU_MONAHANS #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ @@ -749,11 +751,30 @@ typedef void (*ExcpHndlr) (void) ; #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ +#endif /* ! CONFIG_CPU_MONAHANS */ + +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) + +/* + * USB Client Controller (incomplete) + */ +#define UDCCR __REG(0x40600000) +#define UDCICR0 __REG(0x40600004) +#define UDCCIR0 __REG(0x40600008) +#define UDCISR0 __REG(0x4060000c) +#define UDCSIR1 __REG(0x40600010) +#define UDCFNR __REG(0x40600014) +#define UDCOTGICR __REG(0x40600018) +#define UDCOTGISR __REG(0x4060001c) +#define UP2OCR __REG(0x40600020) +#define UP3OCR __REG(0x40600024) + + -#if defined(CONFIG_PXA27X) /* * USB Host Controller */ +#define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */ #define UHCREV __REG(0x4C000000) #define UHCHCON __REG(0x4C000004) #define UHCCOMS __REG(0x4C000008) -- cgit v1.3.1 From 386eda022473394ad8f36b86f2bdc9b4cb816291 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 14 Jun 2006 18:14:56 +0200 Subject: Code cleanup --- CHANGELOG | 4 +- README | 22 +- drivers/usbdcore_ep0.c | 8 +- drivers/usbdcore_mpc8xx.c | 1124 +++++++++++++++++------------------ drivers/usbdcore_omap1510.c | 4 +- drivers/usbtty.c | 164 ++--- drivers/usbtty.h | 4 +- include/asm-arm/arch-pxa/pxa-regs.h | 2 - include/configs/AdderUSB.h | 8 +- include/usb_cdc_acm.h | 2 +- include/usbdcore_mpc8xx.h | 14 +- include/usbdescriptors.h | 2 +- 12 files changed, 673 insertions(+), 685 deletions(-) (limited to 'include/asm-arm') diff --git a/CHANGELOG b/CHANGELOG index 449db66fd4b..bc334820d7d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,7 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== -* Various USB related patches +* Code cleanup + +* Various USB related patches - Add support for mpc8xx USB device. - Add support for Common Device Class - Abstract Control Model USB console. - Add support for flow control in USB slave devices. diff --git a/README b/README index 284a68823d3..178e51e91a0 100644 --- a/README +++ b/README @@ -870,7 +870,7 @@ The following options need to be configured: attach your usb cable. The Unix command "dmesg" should print it has found a new device. The environment variable usbtty can be set to gserial or cdc_acm to enable your device to - appear to a USB host as a Linux gserial device or a + appear to a USB host as a Linux gserial device or a Common Device Class Abstract Control Model serial device. If you select usbtty = gserial you should be able to enumerate a Linux host by @@ -878,14 +878,14 @@ The following options need to be configured: else if using cdc_acm, simply setting the environment variable usbtty to be cdc_acm should suffice. The following might be defined in YourBoardName.h - + CONFIG_USB_DEVICE Define this to build a UDC device CONFIG_USB_TTY Define this to have a tty type of device available to talk to the UDC device - + CFG_CONSOLE_IS_IN_ENV Define this if you want stdin, stdout &/or stderr to be set to usbtty. @@ -893,15 +893,15 @@ The following options need to be configured: mpc8xx: CFG_USB_EXTC_CLK 0xBLAH Derive USB clock from external clock "blah" - - CFG_USB_EXTC_CLK 0x02 - + - CFG_USB_EXTC_CLK 0x02 + CFG_USB_BRG_CLK 0xBLAH Derive USB clock from brgclk - CFG_USB_BRG_CLK 0x04 - If you have a USB-IF assigned VendorID then you may wish to + If you have a USB-IF assigned VendorID then you may wish to define your own vendor specific values either in BoardName.h - or directly in usbd_vendor_info.h. If you don't define + or directly in usbd_vendor_info.h. If you don't define CONFIG_USBD_MANUFACTURER, CONFIG_USBD_PRODUCT_NAME, CONFIG_USBD_VENDORID and CONFIG_USBD_PRODUCTID, then U-Boot should pretend to be a Linux device to it's target host. @@ -909,7 +909,7 @@ The following options need to be configured: CONFIG_USBD_MANUFACTURER Define this string as the name of your company for - CONFIG_USBD_MANUFACTURER "my company" - + CONFIG_USBD_PRODUCT_NAME Define this string as the name of your product - CONFIG_USBD_PRODUCT_NAME "acme usb device" @@ -919,13 +919,13 @@ The following options need to be configured: Implementors Forum. This *must* be a genuine Vendor ID to avoid polluting the USB namespace. - CONFIG_USBD_VENDORID 0xFFFF - + CONFIG_USBD_PRODUCTID Define this as the unique Product ID for your device - CONFIG_USBD_PRODUCTID 0xFFFF - - + + - MMC Support: The MMC controller on the Intel PXA is supported. To enable this define CONFIG_MMC. The MMC can be diff --git a/drivers/usbdcore_ep0.c b/drivers/usbdcore_ep0.c index 5e7443be8fc..1e44f322a79 100644 --- a/drivers/usbdcore_ep0.c +++ b/drivers/usbdcore_ep0.c @@ -44,7 +44,7 @@ * XXX * * As alluded to above, a simple callback cdc_recv_setup has been implemented - * in the usb_device data structure to facilicate passing + * in the usb_device data structure to facilicate passing * Common Device Class packets to a function driver. * * XXX @@ -221,7 +221,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device, (struct usb_device_descriptor *) urb->buffer; } - dbg_ep0(3, "copied device configuration, actual_length: 0x%x", urb->actual_length); + dbg_ep0(3, "copied device configuration, actual_length: 0x%x", urb->actual_length); break; case USB_DESCRIPTOR_TYPE_CONFIGURATION: @@ -268,7 +268,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device, serial_printf("Invalid string index %d\n", index); return -1; } - dbg_ep0(3, "string_descriptor: %p length %d", string_descriptor, string_descriptor->bLength); + dbg_ep0(3, "string_descriptor: %p length %d", string_descriptor, string_descriptor->bLength); copy_config (urb, string_descriptor, string_descriptor->bLength, max); } break; @@ -344,7 +344,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device, case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER: { /* If a USB device supports both a full speed and low speed operation - * we must send a Device_Qualifier descriptor here + * we must send a Device_Qualifier descriptor here */ return -1; } diff --git a/drivers/usbdcore_mpc8xx.c b/drivers/usbdcore_mpc8xx.c index 9bd2c231acd..e87284b1787 100644 --- a/drivers/usbdcore_mpc8xx.c +++ b/drivers/usbdcore_mpc8xx.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2006 by Bryan O'Donoghue, CodeHermit - * bodonoghue@CodeHermit.ie + * bodonoghue@CodeHermit.ie * * References * DasUBoot/drivers/usbdcore_omap1510.c, for design and implementation ideas. @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -24,12 +24,12 @@ /* * Notes : - * 1. #define __SIMULATE_ERROR__ to inject a CRC error into every 2nd TX + * 1. #define __SIMULATE_ERROR__ to inject a CRC error into every 2nd TX * packet to force the USB re-transmit protocol. * * 2. #define __DEBUG_UDC__ to switch on debug tracing to serial console - * be careful that tracing doesn't create Hiesen-bugs with respect to - * response timeouts to control requests. + * be careful that tracing doesn't create Hiesen-bugs with respect to + * response timeouts to control requests. * * 3. This driver should be able to support any higher level driver that * that wants to do either of the two standard UDC implementations @@ -41,18 +41,18 @@ * * 5. For some reason, cbd_datlen is *always* +2 the value it should be. * this means that having an RX cbd of 16 bytes is not possible, since - * the same size is reported for 14 bytes received as 16 bytes received + * the same size is reported for 14 bytes received as 16 bytes received * until we can find out why this happens, RX cbds must be limited to 8 * bytes. TODO: check errata for this behaviour. * * 6. Right now this code doesn't support properly powering up with the USB - * cable attached to the USB host my development board the Adder87x doesn't - * have a pull-up fitted to allow this, so it is necessary to power the - * board and *then* attached the USB cable to the host. However somebody - * with a different design in their board may be able to keep the cable - * constantly connected and simply enable/disable a pull-up re - * figure 31.1 in MPC885RM.pdf instead of having to power up the board and - * then attach the cable ! + * cable attached to the USB host my development board the Adder87x doesn't + * have a pull-up fitted to allow this, so it is necessary to power the + * board and *then* attached the USB cable to the host. However somebody + * with a different design in their board may be able to keep the cable + * constantly connected and simply enable/disable a pull-up re + * figure 31.1 in MPC885RM.pdf instead of having to power up the board and + * then attach the cable ! * */ #include @@ -60,7 +60,7 @@ #if defined(CONFIG_MPC885_FAMILY) && defined(CONFIG_USB_DEVICE) #include -#include "usbdcore.h" +#include "usbdcore.h" #include "usbdcore_mpc8xx.h" #include "usbdcore_ep0.h" @@ -68,24 +68,24 @@ serial_printf("ERROR : [%s] %s:%d: "fmt,\ __FILE__,__FUNCTION__,__LINE__, ##args) #ifdef __DEBUG_UDC__ - #define DBG(fmt,args...)\ +#define DBG(fmt,args...)\ serial_printf("[%s] %s:%d: "fmt,\ __FILE__,__FUNCTION__,__LINE__, ##args) #else - #define DBG(fmt,args...) +#define DBG(fmt,args...) #endif /* Static Data */ #ifdef __SIMULATE_ERROR__ - static char err_poison_test = 0; +static char err_poison_test = 0; #endif static struct mpc8xx_ep ep_ref[MAX_ENDPOINTS]; static u32 address_base = STATE_NOT_READY; static mpc8xx_udc_state_t udc_state = 0; static struct usb_device_instance *udc_device = 0; -static volatile usb_epb_t *endpoints[MAX_ENDPOINTS]; -static volatile cbd_t * tx_cbd[TX_RING_SIZE]; -static volatile cbd_t * rx_cbd[RX_RING_SIZE]; +static volatile usb_epb_t *endpoints[MAX_ENDPOINTS]; +static volatile cbd_t *tx_cbd[TX_RING_SIZE]; +static volatile cbd_t *rx_cbd[RX_RING_SIZE]; static volatile immap_t *immr = 0; static volatile cpm8xx_t *cp = 0; static volatile usb_pram_t *usb_paramp = 0; @@ -95,87 +95,87 @@ static int tx_ct = 0; /* Static Function Declarations */ static void mpc8xx_udc_state_transition_up (usb_device_state_t initial, - usb_device_state_t final); + usb_device_state_t final); static void mpc8xx_udc_state_transition_down (usb_device_state_t initial, - usb_device_state_t final); + usb_device_state_t final); static void mpc8xx_udc_stall (unsigned int ep); -static void mpc8xx_udc_flush_tx_fifo(int epid); -static void mpc8xx_udc_flush_rx_fifo(void); +static void mpc8xx_udc_flush_tx_fifo (int epid); +static void mpc8xx_udc_flush_rx_fifo (void); static void mpc8xx_udc_clear_rxbd (volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_init_tx(struct usb_endpoint_instance *epi, - struct urb * tx_urb); -static void mpc8xx_udc_dump_request(struct usb_device_request *request); -static void mpc8xx_udc_clock_init (volatile immap_t * immr, - volatile cpm8xx_t * cp); +static void mpc8xx_udc_init_tx (struct usb_endpoint_instance *epi, + struct urb *tx_urb); +static void mpc8xx_udc_dump_request (struct usb_device_request *request); +static void mpc8xx_udc_clock_init (volatile immap_t * immr, + volatile cpm8xx_t * cp); static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi); static int mpc8xx_udc_epn_rx (unsigned int epid, volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_ep0_rx(volatile cbd_t * rx_cbdp); +static void mpc8xx_udc_ep0_rx (volatile cbd_t * rx_cbdp); static void mpc8xx_udc_cbd_init (void); static void mpc8xx_udc_endpoint_init (void); static void mpc8xx_udc_cbd_attach (int ep, uchar tx_size, uchar rx_size); static u32 mpc8xx_udc_alloc (u32 data_size, u32 alignment); static int mpc8xx_udc_ep0_rx_setup (volatile cbd_t * rx_cbdp); static void mpc8xx_udc_set_nak (unsigned int ep); -static short mpc8xx_udc_handle_txerr(void); -static void mpc8xx_udc_advance_rx(volatile cbd_t ** rx_cbdp, int epid); +static short mpc8xx_udc_handle_txerr (void); +static void mpc8xx_udc_advance_rx (volatile cbd_t ** rx_cbdp, int epid); /****************************************************************************** - Global Linkage + Global Linkage *****************************************************************************/ /* udc_init * * Do initial bus gluing */ -int udc_init(void) +int udc_init (void) { /* Init various pointers */ immr = (immap_t *) CFG_IMMR; - cp = (cpm8xx_t *)&(immr->im_cpm); - usb_paramp = (usb_pram_t*)&(cp->cp_dparam[PROFF_USB]); - usbp = (usb_t *) &(cp->cp_scc[0]); + cp = (cpm8xx_t *) & (immr->im_cpm); + usb_paramp = (usb_pram_t *) & (cp->cp_dparam[PROFF_USB]); + usbp = (usb_t *) & (cp->cp_scc[0]); + + memset (ep_ref, 0x00, (sizeof (struct mpc8xx_ep) * MAX_ENDPOINTS)); - memset(ep_ref, 0x00, (sizeof(struct mpc8xx_ep) * MAX_ENDPOINTS)); - udc_device = 0; udc_state = STATE_NOT_READY; - - usbp->usmod= 0x00; - usbp->uscom= 0; - + + usbp->usmod = 0x00; + usbp->uscom = 0; + /* Set USB Frame #0, Respond at Address & Get a clock source */ usbp->usaddr = 0x00; mpc8xx_udc_clock_init (immr, cp); - + /* PA15, PA14 as perhiperal USBRXD and USBOE */ - immr->im_ioport.iop_padir&= ~0x0003; - immr->im_ioport.iop_papar|= 0x0003; - + immr->im_ioport.iop_padir &= ~0x0003; + immr->im_ioport.iop_papar |= 0x0003; + /* PC11/PC10 as peripheral USBRXP USBRXN */ - immr->im_ioport.iop_pcso|= 0x0030; - + immr->im_ioport.iop_pcso |= 0x0030; + /* PC7/PC6 as perhiperal USBTXP and USBTXN */ - immr->im_ioport.iop_pcdir|= 0x0300; - immr->im_ioport.iop_pcpar|= 0x0300; - + immr->im_ioport.iop_pcdir |= 0x0300; + immr->im_ioport.iop_pcpar |= 0x0300; + /* Set the base address */ - address_base = (u32)(cp->cp_dpmem + CPM_USB_BASE); + address_base = (u32) (cp->cp_dpmem + CPM_USB_BASE); /* Initialise endpoints and circular buffers */ - mpc8xx_udc_endpoint_init(); - mpc8xx_udc_cbd_init(); - + mpc8xx_udc_endpoint_init (); + mpc8xx_udc_cbd_init (); + /* Assign allocated Dual Port Endpoint descriptors */ - usb_paramp->ep0ptr = (u32)endpoints[0]; - usb_paramp->ep1ptr = (u32)endpoints[1]; - usb_paramp->ep2ptr = (u32)endpoints[2]; - usb_paramp->ep3ptr = (u32)endpoints[3]; + usb_paramp->ep0ptr = (u32) endpoints[0]; + usb_paramp->ep1ptr = (u32) endpoints[1]; + usb_paramp->ep2ptr = (u32) endpoints[2]; + usb_paramp->ep3ptr = (u32) endpoints[3]; usb_paramp->frame_n = 0; - DBG("ep0ptr=0x%08x ep1ptr=0x%08x ep2ptr=0x%08x ep3ptr=0x%08x\n", - usb_paramp->ep0ptr, usb_paramp->ep1ptr, usb_paramp->ep2ptr, - usb_paramp->ep3ptr); - + DBG ("ep0ptr=0x%08x ep1ptr=0x%08x ep2ptr=0x%08x ep3ptr=0x%08x\n", + usb_paramp->ep0ptr, usb_paramp->ep1ptr, usb_paramp->ep2ptr, + usb_paramp->ep3ptr); + return 0; } @@ -183,149 +183,147 @@ int udc_init(void) * * Poll for whatever events may have occured */ -void udc_irq(void) +void udc_irq (void) { int epid = 0; - volatile cbd_t * rx_cbdp = 0; - volatile cbd_t * rx_cbdp_base = 0; + volatile cbd_t *rx_cbdp = 0; + volatile cbd_t *rx_cbdp_base = 0; - if(udc_state!=STATE_READY){ + if (udc_state != STATE_READY) { return; } - - if(usbp->usber&USB_E_BSY){ + + if (usbp->usber & USB_E_BSY) { /* This shouldn't happen. If it does then it's a bug ! */ - usbp->usber|=USB_E_BSY; - mpc8xx_udc_flush_rx_fifo(); + usbp->usber |= USB_E_BSY; + mpc8xx_udc_flush_rx_fifo (); } - /* Scan all RX/Bidirectional Endpoints for RX data. */ - for(epid = 0; epidcbd_sc&RX_BD_E)){ - - if(rx_cbdp->cbd_sc&0x1F){ + + do { + if (!(rx_cbdp->cbd_sc & RX_BD_E)) { + + if (rx_cbdp->cbd_sc & 0x1F) { /* Corrupt data discard it. - * Controller has NAK'd this packet. + * Controller has NAK'd this packet. */ - mpc8xx_udc_clear_rxbd(rx_cbdp); + mpc8xx_udc_clear_rxbd (rx_cbdp); - }else{ - if(!epid){ - mpc8xx_udc_ep0_rx(rx_cbdp); + } else { + if (!epid) { + mpc8xx_udc_ep0_rx (rx_cbdp); - }else{ + } else { /* Process data */ - mpc8xx_udc_set_nak(epid); - mpc8xx_udc_epn_rx(epid,rx_cbdp); - mpc8xx_udc_clear_rxbd(rx_cbdp); - } + mpc8xx_udc_set_nak (epid); + mpc8xx_udc_epn_rx (epid, rx_cbdp); + mpc8xx_udc_clear_rxbd (rx_cbdp); + } } - + /* Advance RX CBD pointer */ - mpc8xx_udc_advance_rx(&rx_cbdp, epid); + mpc8xx_udc_advance_rx (&rx_cbdp, epid); ep_ref[epid].prx = rx_cbdp; - }else{ + } else { /* Advance RX CBD pointer */ - mpc8xx_udc_advance_rx(&rx_cbdp, epid); + mpc8xx_udc_advance_rx (&rx_cbdp, epid); } - }while(rx_cbdp != rx_cbdp_base); + } while (rx_cbdp != rx_cbdp_base); } /* Handle TX events as appropiate, the correct place to do this is * in a tx routine. Perhaps TX on epn was pre-empted by ep0 */ - if(usbp->usber&USB_E_TXB){ - usbp->usber|=USB_E_TXB; + if (usbp->usber & USB_E_TXB) { + usbp->usber |= USB_E_TXB; } - - if(usbp->usber&(USB_TX_ERRMASK)){ - mpc8xx_udc_handle_txerr(); + + if (usbp->usber & (USB_TX_ERRMASK)) { + mpc8xx_udc_handle_txerr (); } /* Switch to the default state, respond at the default address */ - if(usbp->usber&USB_E_RESET){ - usbp->usber|=USB_E_RESET; - usbp->usaddr = 0x00; + if (usbp->usber & USB_E_RESET) { + usbp->usber |= USB_E_RESET; + usbp->usaddr = 0x00; udc_device->device_state = STATE_DEFAULT; } - /*if(usbp->usber&USB_E_IDLE){ - We could suspend here ! - usbp->usber|=USB_E_IDLE; - DBG("idle state change\n"); - } - if(usbp->usbs){ - We could resume here when IDLE is deasserted ! - Not worth doing, so long as we are self powered though. - }*/ + /* if(usbp->usber&USB_E_IDLE){ + We could suspend here ! + usbp->usber|=USB_E_IDLE; + DBG("idle state change\n"); + } + if(usbp->usbs){ + We could resume here when IDLE is deasserted ! + Not worth doing, so long as we are self powered though. + } + */ return; } - - /* udc_endpoint_write * * Write some data to an endpoint */ -int udc_endpoint_write(struct usb_endpoint_instance *epi) +int udc_endpoint_write (struct usb_endpoint_instance *epi) { int ep = 0; short epid = 1, unnak = 0, ret = 0; - if(udc_state != STATE_READY){ - ERR("invalid udc_state != STATE_READY!\n"); + if (udc_state != STATE_READY) { + ERR ("invalid udc_state != STATE_READY!\n"); return -1; } - if(!udc_device || !epi){ + if (!udc_device || !epi) { return -1; } - - if(udc_device->device_state!=STATE_CONFIGURED){ + + if (udc_device->device_state != STATE_CONFIGURED) { return -1; } ep = epi->endpoint_address & 0x03; - if(ep >= MAX_ENDPOINTS){ + if (ep >= MAX_ENDPOINTS) { return -1; } - + /* Set NAK for all RX endpoints during TX */ - for(epid = 1; epidusep[epid]&( USEP_THS_NAK | USEP_RHS_NAK ))){ - unnak |= 1<usep[epid] & (USEP_THS_NAK | USEP_RHS_NAK))) { + unnak |= 1 << epid; } - mpc8xx_udc_set_nak(epid); + mpc8xx_udc_set_nak (epid); } - mpc8xx_udc_init_tx(&udc_device->bus->endpoint_array[ep],epi->tx_urb); - ret = mpc8xx_udc_ep_tx(&udc_device->bus->endpoint_array[ep]); - + mpc8xx_udc_init_tx (&udc_device->bus->endpoint_array[ep], + epi->tx_urb); + ret = mpc8xx_udc_ep_tx (&udc_device->bus->endpoint_array[ep]); + /* Remove temporary NAK */ - for(epid = 1; epid= MAX_ENDPOINTS){ + + if (ep >= MAX_ENDPOINTS) { goto err; } epi = &udc_device->bus->endpoint_array[ep]; - if(!epi){ + if (!epi) { goto err; } - if(!ep_ref[ep].urb){ - ep_ref[ep].urb = usbd_alloc_urb(udc_device, - udc_device->bus->endpoint_array); - if(!ep_ref[ep].urb){ + if (!ep_ref[ep].urb) { + ep_ref[ep].urb = usbd_alloc_urb (udc_device, udc_device->bus->endpoint_array); + if (!ep_ref[ep].urb) { goto err; } - }else{ + } else { ep_ref[ep].urb->actual_length = 0; } - switch(direction){ - case USB_DIR_IN: - epi->tx_urb = ep_ref[ep].urb; - break; - case USB_DIR_OUT: - epi->rcv_urb = ep_ref[ep].urb; - break; - default: - goto err; + switch (direction) { + case USB_DIR_IN: + epi->tx_urb = ep_ref[ep].urb; + break; + case USB_DIR_OUT: + epi->rcv_urb = ep_ref[ep].urb; + break; + default: + goto err; } return 0; -err: + err: udc_state = STATE_ERROR; return -1; } @@ -377,83 +374,84 @@ err: * Associate U-Boot software endpoints to mpc8xx endpoint parameter ram * Isochronous endpoints aren't yet supported! */ -void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, - struct usb_endpoint_instance *epi) +void udc_setup_ep (struct usb_device_instance *device, unsigned int ep, + struct usb_endpoint_instance *epi) { uchar direction = 0; int ep_attrib = 0; - if(epi && (ep < MAX_ENDPOINTS)){ - - if(ep == 0){ - if (epi->rcv_attributes!=USB_ENDPOINT_XFER_CONTROL - ||epi->tx_attributes!= - USB_ENDPOINT_XFER_CONTROL){ + if (epi && (ep < MAX_ENDPOINTS)) { - /* ep0 must be a control endpoint*/ + if (ep == 0) { + if (epi->rcv_attributes != USB_ENDPOINT_XFER_CONTROL + || epi->tx_attributes != + USB_ENDPOINT_XFER_CONTROL) { + + /* ep0 must be a control endpoint */ udc_state = STATE_ERROR; return; } - if(!(ep_ref[ep].sc & EP_ATTACHED)){ - mpc8xx_udc_cbd_attach (ep, epi->tx_packetSize, - epi->rcv_packetSize); + if (!(ep_ref[ep].sc & EP_ATTACHED)) { + mpc8xx_udc_cbd_attach (ep, epi->tx_packetSize, + epi->rcv_packetSize); } usbp->usep[ep] = 0x0000; return; } - - if ((epi->endpoint_address & USB_ENDPOINT_DIR_MASK) - == USB_DIR_IN) { + + if ((epi->endpoint_address & USB_ENDPOINT_DIR_MASK) + == USB_DIR_IN) { direction = 1; ep_attrib = epi->tx_attributes; epi->rcv_packetSize = 0; - ep_ref[ep].sc |= USB_DIR_IN; + ep_ref[ep].sc |= USB_DIR_IN; } else { - + direction = 0; ep_attrib = epi->rcv_attributes; - epi->tx_packetSize = 0; + epi->tx_packetSize = 0; ep_ref[ep].sc &= ~USB_DIR_IN; } - if(mpc8xx_udc_assign_urb(ep, epi->endpoint_address - &USB_ENDPOINT_DIR_MASK)){ + if (mpc8xx_udc_assign_urb (ep, epi->endpoint_address + & USB_ENDPOINT_DIR_MASK)) { return; } - switch(ep_attrib){ - case USB_ENDPOINT_XFER_CONTROL: - if(!(ep_ref[ep].sc & EP_ATTACHED)){ + switch (ep_attrib) { + case USB_ENDPOINT_XFER_CONTROL: + if (!(ep_ref[ep].sc & EP_ATTACHED)) { + mpc8xx_udc_cbd_attach (ep, + epi->tx_packetSize, + epi->rcv_packetSize); + } + usbp->usep[ep] = ep << 12; + epi->rcv_urb = epi->tx_urb = ep_ref[ep].urb; + + break; + case USB_ENDPOINT_XFER_BULK: + case USB_ENDPOINT_XFER_INT: + if (!(ep_ref[ep].sc & EP_ATTACHED)) { + if (direction) { mpc8xx_udc_cbd_attach (ep, - epi->tx_packetSize, - epi->rcv_packetSize); + epi->tx_packetSize, + 0); + } else { + mpc8xx_udc_cbd_attach (ep, + 0, + epi->rcv_packetSize); } - usbp->usep[ep] = ep<<12; - epi->rcv_urb = epi->tx_urb = ep_ref[ep].urb; + } + usbp->usep[ep] = (ep << 12) | ((ep_attrib) << 8); - break; - case USB_ENDPOINT_XFER_BULK : - case USB_ENDPOINT_XFER_INT: - if(!(ep_ref[ep].sc & EP_ATTACHED)){ - if(direction){ - mpc8xx_udc_cbd_attach (ep, - epi->tx_packetSize, 0); - }else{ - mpc8xx_udc_cbd_attach (ep, - 0, epi->rcv_packetSize); - } - } - usbp->usep[ep]= (ep<<12)|((ep_attrib)<<8); - - break; - case USB_ENDPOINT_XFER_ISOC: - default: - serial_printf("Error endpoint attrib %d>3\n", - ep_attrib); - udc_state = STATE_ERROR; - break; + break; + case USB_ENDPOINT_XFER_ISOC: + default: + serial_printf ("Error endpoint attrib %d>3\n", ep_attrib); + udc_state = STATE_ERROR; + break; } } @@ -463,54 +461,53 @@ void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, * * Move state, switch on the USB */ -void udc_connect(void) +void udc_connect (void) { - /* Enable pull-up resistor on D+ + /* Enable pull-up resistor on D+ * TODO: fit a pull-up resistor to drive SE0 for > 2.5us */ - - if(udc_state!=STATE_ERROR){ + + if (udc_state != STATE_ERROR) { udc_state = STATE_READY; - usbp->usmod|= USMOD_EN; + usbp->usmod |= USMOD_EN; } -} +} /* udc_disconnect * * Disconnect is not used but, is included for completeness */ -void udc_disconnect(void) +void udc_disconnect (void) { /* Disable pull-up resistor on D- * TODO: fix a pullup resistor to control this */ - if(udc_state!=STATE_ERROR){ + if (udc_state != STATE_ERROR) { udc_state = STATE_NOT_READY; } - usbp->usmod&=~USMOD_EN; + usbp->usmod &= ~USMOD_EN; } /* udc_enable - * + * * Grab an EP0 URB, register interest in a subset of USB events */ -void udc_enable(struct usb_device_instance *device) +void udc_enable (struct usb_device_instance *device) { - if(udc_state == STATE_ERROR){ + if (udc_state == STATE_ERROR) { return; } udc_device = device; - - if(!ep_ref[0].urb){ - ep_ref[0].urb = usbd_alloc_urb(device, - device->bus->endpoint_array); + + if (!ep_ref[0].urb) { + ep_ref[0].urb = usbd_alloc_urb (device, device->bus->endpoint_array); } /* Register interest in all events except SOF, enable transceiver */ - usbp->usber= 0x03FF; - usbp->usbmr= 0x02F7; + usbp->usber = 0x03FF; + usbp->usbmr = 0x02F7; return; } @@ -519,26 +516,26 @@ void udc_enable(struct usb_device_instance *device) * * disable the currently hooked device */ -void udc_disable(void) +void udc_disable (void) { int i = 0; - if(udc_state == STATE_ERROR){ - DBG("Won't disable UDC. udc_state==STATE_ERROR !\n"); + if (udc_state == STATE_ERROR) { + DBG ("Won't disable UDC. udc_state==STATE_ERROR !\n"); return; } udc_device = 0; - for(;iusbmr= 0x00; - usbp->usmod= ~USMOD_EN; + + usbp->usbmr = 0x00; + usbp->usmod = ~USMOD_EN; udc_state = STATE_NOT_READY; } @@ -546,46 +543,46 @@ void udc_disable(void) * * Enable the specified device */ -void udc_startup_events(struct usb_device_instance *device) +void udc_startup_events (struct usb_device_instance *device) { - udc_enable(device); - if(udc_state == STATE_READY){ + udc_enable (device); + if (udc_state == STATE_READY) { usbd_device_event_irq (device, DEVICE_CREATE, 0); } } /* udc_set_nak - * + * * Allow upper layers to signal lower layers should not accept more RX data * */ -void udc_set_nak(int epid) +void udc_set_nak (int epid) { - if(epid){ - mpc8xx_udc_set_nak(epid); + if (epid) { + mpc8xx_udc_set_nak (epid); } } -/* udc_unset_nak - * +/* udc_unset_nak + * * Suspend sending of NAK tokens for DATA OUT tokens on a given endpoint. * Switch off NAKing on this endpoint to accept more data output from host. * */ void udc_unset_nak (int epid) { - if(epid > MAX_ENDPOINTS){ + if (epid > MAX_ENDPOINTS) { return; } - if(usbp->usep[epid]&(USEP_THS_NAK | USEP_RHS_NAK)){ - usbp->usep[epid]&= ~(USEP_THS_NAK | USEP_RHS_NAK); + if (usbp->usep[epid] & (USEP_THS_NAK | USEP_RHS_NAK)) { + usbp->usep[epid] &= ~(USEP_THS_NAK | USEP_RHS_NAK); __asm__ ("eieio"); } } /****************************************************************************** - Static Linkage + Static Linkage ******************************************************************************/ /* udc_state_transition_up @@ -633,10 +630,10 @@ void udc_unset_nak (int epid) * state, then no state transitions will take place. * */ - + static void mpc8xx_udc_state_transition_up (usb_device_state_t initial, - usb_device_state_t final) -{ + usb_device_state_t final) +{ if (initial < final) { switch (initial) { case STATE_ATTACHED: @@ -665,13 +662,13 @@ static void mpc8xx_udc_state_transition_up (usb_device_state_t initial, } static void mpc8xx_udc_state_transition_down (usb_device_state_t initial, - usb_device_state_t final) + usb_device_state_t final) { if (initial > final) { switch (initial) { case STATE_CONFIGURED: - usbd_device_event_irq (udc_device, - DEVICE_DE_CONFIGURED, 0); + usbd_device_event_irq (udc_device, + DEVICE_DE_CONFIGURED, 0); if (final == STATE_ADDRESSED) break; case STATE_ADDRESSED: @@ -679,13 +676,13 @@ static void mpc8xx_udc_state_transition_down (usb_device_state_t initial, if (final == STATE_DEFAULT) break; case STATE_DEFAULT: - usbd_device_event_irq (udc_device, - DEVICE_POWER_INTERRUPTION, 0); + usbd_device_event_irq (udc_device, + DEVICE_POWER_INTERRUPTION, 0); if (final == STATE_POWERED) break; case STATE_POWERED: usbd_device_event_irq (udc_device, DEVICE_HUB_RESET, - 0); + 0); case STATE_ATTACHED: break; default: @@ -708,7 +705,7 @@ static void mpc8xx_udc_stall (unsigned int ep) * * Force returning of NAK responses for the given endpoint as a kind of very * simple flow control - */ + */ static void mpc8xx_udc_set_nak (unsigned int ep) { usbp->usep[ep] |= NAK_BITMASK; @@ -720,27 +717,26 @@ static void mpc8xx_udc_set_nak (unsigned int ep) * Handle errors relevant to TX. Return a status code to allow calling * indicative of what if anything happened */ -static short mpc8xx_udc_handle_txerr() +static short mpc8xx_udc_handle_txerr () { short ep = 0, ret = 0; - - for(; epusber&(0x10<usber & (0x10 << ep)) { + /* Timeout or underrun */ - if(tx_cbd[ep]->cbd_sc&0x06){ + if (tx_cbd[ep]->cbd_sc & 0x06) { ret = 1; - mpc8xx_udc_flush_tx_fifo(ep); + mpc8xx_udc_flush_tx_fifo (ep); - }else{ - if(usbp->usep[ep]&STALL_BITMASK){ - if(!ep){ - usbp->usep[ep]&= - ~STALL_BITMASK; + } else { + if (usbp->usep[ep] & STALL_BITMASK) { + if (!ep) { + usbp->usep[ep] &= ~STALL_BITMASK; } - }/* else NAK */ + } /* else NAK */ } - usbp->usber|=(0x10<usber |= (0x10 << ep); } } return ret; @@ -750,13 +746,12 @@ static short mpc8xx_udc_handle_txerr() * * Advance cbd rx */ -static void mpc8xx_udc_advance_rx(volatile cbd_t ** rx_cbdp, int epid) +static void mpc8xx_udc_advance_rx (volatile cbd_t ** rx_cbdp, int epid) { - if((*rx_cbdp)->cbd_sc & RX_BD_W){ - *rx_cbdp = (volatile cbd_t*) - (endpoints[epid]->rbase + CFG_IMMR); - - }else{ + if ((*rx_cbdp)->cbd_sc & RX_BD_W) { + *rx_cbdp = (volatile cbd_t *) (endpoints[epid]->rbase + CFG_IMMR); + + } else { (*rx_cbdp)++; } } @@ -766,34 +761,34 @@ static void mpc8xx_udc_advance_rx(volatile cbd_t ** rx_cbdp, int epid) * * Flush a given TX fifo. Assumes one tx cbd per endpoint */ -static void mpc8xx_udc_flush_tx_fifo(int epid) -{ - volatile cbd_t * tx_cbdp = 0; +static void mpc8xx_udc_flush_tx_fifo (int epid) +{ + volatile cbd_t *tx_cbdp = 0; - if(epid > MAX_ENDPOINTS){ + if (epid > MAX_ENDPOINTS) { return; } /* TX stop */ - immr->im_cpm.cp_cpcr = ((epid<<2) | 0x1D01); + immr->im_cpm.cp_cpcr = ((epid << 2) | 0x1D01); __asm__ ("eieio"); - while(immr->im_cpm.cp_cpcr & 0x01); - + while (immr->im_cpm.cp_cpcr & 0x01); + usbp->uscom = 0x40 | 0; - + /* reset ring */ - tx_cbdp = (cbd_t*)(endpoints[epid]->tbptr + CFG_IMMR); + tx_cbdp = (cbd_t *) (endpoints[epid]->tbptr + CFG_IMMR); tx_cbdp->cbd_sc = (TX_BD_I | TX_BD_W); - + endpoints[epid]->tptr = endpoints[epid]->tbase; - endpoints[epid]->tstate = 0x00; - endpoints[epid]->tbcnt = 0x00; + endpoints[epid]->tstate = 0x00; + endpoints[epid]->tbcnt = 0x00; /* TX start */ - immr->im_cpm.cp_cpcr = ((epid<<2) | 0x2D01); + immr->im_cpm.cp_cpcr = ((epid << 2) | 0x2D01); __asm__ ("eieio"); - while(immr->im_cpm.cp_cpcr & 0x01); + while (immr->im_cpm.cp_cpcr & 0x01); return; } @@ -807,28 +802,29 @@ static void mpc8xx_udc_flush_tx_fifo(int epid) * we have accepted data but, the CPM found it had no-where to put that data * which needless to say would be a bad thing. */ -static void mpc8xx_udc_flush_rx_fifo() +static void mpc8xx_udc_flush_rx_fifo () { int i = 0; - for(i = 0;icbd_sc&RX_BD_E)){ - ERR("buf %p used rx data len = 0x%x sc=0x%x!\n", - rx_cbd[i], rx_cbd[i]->cbd_datlen, - rx_cbd[i]->cbd_sc); + + for (i = 0; i < RX_RING_SIZE; i++) { + if (!(rx_cbd[i]->cbd_sc & RX_BD_E)) { + ERR ("buf %p used rx data len = 0x%x sc=0x%x!\n", + rx_cbd[i], rx_cbd[i]->cbd_datlen, + rx_cbd[i]->cbd_sc); } } - ERR("BUG : Input over-run\n"); + ERR ("BUG : Input over-run\n"); } /* mpc8xx_udc_clear_rxbd - * + * * Release control of RX CBD to CP. */ -static void mpc8xx_udc_clear_rxbd(volatile cbd_t * rx_cbdp) +static void mpc8xx_udc_clear_rxbd (volatile cbd_t * rx_cbdp) { rx_cbdp->cbd_datlen = 0x0000; - rx_cbdp->cbd_sc= ((rx_cbdp->cbd_sc & RX_BD_W)|(RX_BD_E | RX_BD_I)); + rx_cbdp->cbd_sc = ((rx_cbdp->cbd_sc & RX_BD_W) | (RX_BD_E | RX_BD_I)); __asm__ ("eieio"); } @@ -837,27 +833,27 @@ static void mpc8xx_udc_clear_rxbd(volatile cbd_t * rx_cbdp) * Parse for tx timeout, control RX or USB reset/busy conditions * Return -1 on timeout, -2 on fatal error, else return zero */ -static int mpc8xx_udc_tx_irq(int ep) +static int mpc8xx_udc_tx_irq (int ep) { int i = 0; - if(usbp->usber&(USB_TX_ERRMASK)){ - if(mpc8xx_udc_handle_txerr()){ + if (usbp->usber & (USB_TX_ERRMASK)) { + if (mpc8xx_udc_handle_txerr ()) { /* Timeout, controlling function must retry send */ return -1; } } - if(usbp->usber & (USB_E_RESET|USB_E_BSY)){ + if (usbp->usber & (USB_E_RESET | USB_E_BSY)) { /* Fatal, abandon TX transaction */ return -2; } - - if(usbp->usber & USB_E_RXB){ - for(i = 0;icbd_sc&RX_BD_E)){ - if((rx_cbd[i] == ep_ref[0].prx) || ep){ - return -2; + + if (usbp->usber & USB_E_RXB) { + for (i = 0; i < RX_RING_SIZE; i++) { + if (!(rx_cbd[i]->cbd_sc & RX_BD_E)) { + if ((rx_cbd[i] == ep_ref[0].prx) || ep) { + return -2; } } } @@ -875,106 +871,106 @@ static int mpc8xx_udc_tx_irq(int ep) * devices to give up TX, however tx_retry stops us getting stuck in an endless * TX loop. */ -static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi) +static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi) { struct urb *urb = epi->tx_urb; - volatile cbd_t * tx_cbdp = 0; + volatile cbd_t *tx_cbdp = 0; unsigned int ep = 0, pkt_len = 0, x = 0, tx_retry = 0; int ret = 0; - - if(!epi || (epi->endpoint_address&0x03)>=MAX_ENDPOINTS || !urb){ + + if (!epi || (epi->endpoint_address & 0x03) >= MAX_ENDPOINTS || !urb) { return -1; } ep = epi->endpoint_address & 0x03; - tx_cbdp = (cbd_t*)(endpoints[ep]->tbptr + CFG_IMMR); - - if(tx_cbdp->cbd_sc&TX_BD_R || usbp->usber&USB_E_TXB){ - mpc8xx_udc_flush_tx_fifo(ep); + tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CFG_IMMR); + + if (tx_cbdp->cbd_sc & TX_BD_R || usbp->usber & USB_E_TXB) { + mpc8xx_udc_flush_tx_fifo (ep); usbp->usber |= USB_E_TXB; }; - while(tx_retry++ < 100){ - ret = mpc8xx_udc_tx_irq(ep); - if(ret == -1){ + while (tx_retry++ < 100) { + ret = mpc8xx_udc_tx_irq (ep); + if (ret == -1) { /* ignore timeout here */ - }else if(ret == -2){ + } else if (ret == -2) { /* Abandon TX */ - mpc8xx_udc_flush_tx_fifo(ep); + mpc8xx_udc_flush_tx_fifo (ep); return -1; - } + } + + tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CFG_IMMR); + while (tx_cbdp->cbd_sc & TX_BD_R) { + }; + tx_cbdp->cbd_sc = (tx_cbdp->cbd_sc & TX_BD_W); - tx_cbdp = (cbd_t*)(endpoints[ep]->tbptr + CFG_IMMR); - while(tx_cbdp->cbd_sc&TX_BD_R){}; - tx_cbdp->cbd_sc = (tx_cbdp->cbd_sc&TX_BD_W); - pkt_len = urb->actual_length - epi->sent; - if(pkt_len> epi->tx_packetSize || pkt_len > EP_MAX_PKT){ - pkt_len = MIN(epi->tx_packetSize, EP_MAX_PKT); + if (pkt_len > epi->tx_packetSize || pkt_len > EP_MAX_PKT) { + pkt_len = MIN (epi->tx_packetSize, EP_MAX_PKT); } - for(x=0; xcbd_bufaddr+x)) = + for (x = 0; x < pkt_len; x++) { + *((unsigned char *) (tx_cbdp->cbd_bufaddr + x)) = urb->buffer[epi->sent + x]; } tx_cbdp->cbd_datlen = pkt_len; - tx_cbdp->cbd_sc|=(CBD_TX_BITMASK | ep_ref[ep].pid); + tx_cbdp->cbd_sc |= (CBD_TX_BITMASK | ep_ref[ep].pid); __asm__ ("eieio"); - #ifdef __SIMULATE_ERROR__ - if(++err_poison_test == 2){ - err_poison_test = 0; - tx_cbdp->cbd_sc&=~TX_BD_TC; - } - #endif +#ifdef __SIMULATE_ERROR__ + if (++err_poison_test == 2) { + err_poison_test = 0; + tx_cbdp->cbd_sc &= ~TX_BD_TC; + } +#endif - usbp->uscom = (USCOM_STR | ep); + usbp->uscom = (USCOM_STR | ep); - while(!(usbp->usber&USB_E_TXB)){ - ret = mpc8xx_udc_tx_irq(ep); - if(ret == -1){ + while (!(usbp->usber & USB_E_TXB)) { + ret = mpc8xx_udc_tx_irq (ep); + if (ret == -1) { /* TX timeout */ break; - }else if(ret == -2){ - if(usbp->usber & USB_E_TXB){ - usbp->usber|=USB_E_TXB; + } else if (ret == -2) { + if (usbp->usber & USB_E_TXB) { + usbp->usber |= USB_E_TXB; } - mpc8xx_udc_flush_tx_fifo(ep); + mpc8xx_udc_flush_tx_fifo (ep); return -1; } }; - if(usbp->usber & USB_E_TXB){ - usbp->usber|=USB_E_TXB; + if (usbp->usber & USB_E_TXB) { + usbp->usber |= USB_E_TXB; } /* ACK must be present <= 18bit times from TX */ - if(ret == -1){ + if (ret == -1) { continue; } - + /* TX ACK : USB 2.0 8.7.2, Toggle PID, Advance TX */ epi->sent += pkt_len; - epi->last = MIN (urb->actual_length - epi->sent, - epi->tx_packetSize); - TOGGLE_TX_PID(ep_ref[ep].pid); + epi->last = MIN (urb->actual_length - epi->sent, epi->tx_packetSize); + TOGGLE_TX_PID (ep_ref[ep].pid); + + if (epi->sent >= epi->tx_urb->actual_length) { - if(epi->sent >= epi->tx_urb->actual_length){ - epi->tx_urb->actual_length = 0; epi->sent = 0; - - if(ep_ref[ep].sc & EP_SEND_ZLP){ + + if (ep_ref[ep].sc & EP_SEND_ZLP) { ep_ref[ep].sc &= ~EP_SEND_ZLP; - }else{ + } else { return 0; } } } - - ERR("TX fail, endpoint 0x%x tx bytes 0x%x/0x%x\n",ep, epi->sent, - epi->tx_urb->actual_length); + + ERR ("TX fail, endpoint 0x%x tx bytes 0x%x/0x%x\n", ep, epi->sent, + epi->tx_urb->actual_length); return -1; } @@ -983,126 +979,117 @@ static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi) * * Dump a control request to console */ -static void mpc8xx_udc_dump_request(struct usb_device_request *request) +static void mpc8xx_udc_dump_request (struct usb_device_request *request) { - DBG( - "bmRequestType:%02x bRequest:%02x wValue:%04x " - "wIndex:%04x wLength:%04x ?\n", - request->bmRequestType, - request->bRequest, - request->wValue, - request->wIndex, - request->wLength); + DBG ("bmRequestType:%02x bRequest:%02x wValue:%04x " + "wIndex:%04x wLength:%04x ?\n", + request->bmRequestType, + request->bRequest, + request->wValue, request->wIndex, request->wLength); return; } -/* mpc8xx_udc_ep0_rx_setup - * +/* mpc8xx_udc_ep0_rx_setup + * * Decode received ep0 SETUP packet. return non-zero on error */ static int mpc8xx_udc_ep0_rx_setup (volatile cbd_t * rx_cbdp) { unsigned int x = 0; - struct urb * purb = ep_ref[0].urb; - struct usb_endpoint_instance *epi = + struct urb *purb = ep_ref[0].urb; + struct usb_endpoint_instance *epi = &udc_device->bus->endpoint_array[0]; - for(; xcbd_datlen; x++){ - *(((unsigned char*)&ep_ref[0].urb->device_request)+x) = - *((unsigned char*)(rx_cbdp->cbd_bufaddr+x)); + for (; x < rx_cbdp->cbd_datlen; x++) { + *(((unsigned char *) &ep_ref[0].urb->device_request) + x) = + *((unsigned char *) (rx_cbdp->cbd_bufaddr + x)); } - - mpc8xx_udc_clear_rxbd(rx_cbdp); - if (ep0_recv_setup(purb)) { - mpc8xx_udc_dump_request(&purb->device_request); + mpc8xx_udc_clear_rxbd (rx_cbdp); + + if (ep0_recv_setup (purb)) { + mpc8xx_udc_dump_request (&purb->device_request); return -1; } - if ((purb->device_request.bmRequestType&USB_REQ_DIRECTION_MASK) + if ((purb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) { - switch (purb->device_request.bRequest){ - case USB_REQ_SET_ADDRESS: - /* Send the Status OUT ZLP */ - ep_ref[0].pid = TX_BD_PID_DATA1; - purb->actual_length = 0; - mpc8xx_udc_init_tx(epi,purb); - mpc8xx_udc_ep_tx(epi); - - /* Move to the addressed state */ - usbp->usaddr = udc_device->address; - mpc8xx_udc_state_transition_up(udc_device->device_state, - STATE_ADDRESSED); - return 0; - - case USB_REQ_SET_CONFIGURATION: - if(!purb->device_request.wValue){ - - /* Respond at default address */ - usbp->usaddr = 0x00; - mpc8xx_udc_state_transition_down(udc_device->device_state, - STATE_ADDRESSED); - - } else { - - /* TODO: Support multiple configurations */ - mpc8xx_udc_state_transition_up(udc_device->device_state,STATE_CONFIGURED); - for(x=1; xbus->endpoint_array[x].endpoint_address&USB_ENDPOINT_DIR_MASK) - == USB_DIR_IN){ - ep_ref[x].pid = TX_BD_PID_DATA0; - }else{ - ep_ref[x].pid = RX_BD_PID_DATA0; - } - /* Set configuration must unstall endpoints */ - usbp->usep[x]&=~STALL_BITMASK; + switch (purb->device_request.bRequest) { + case USB_REQ_SET_ADDRESS: + /* Send the Status OUT ZLP */ + ep_ref[0].pid = TX_BD_PID_DATA1; + purb->actual_length = 0; + mpc8xx_udc_init_tx (epi, purb); + mpc8xx_udc_ep_tx (epi); + + /* Move to the addressed state */ + usbp->usaddr = udc_device->address; + mpc8xx_udc_state_transition_up (udc_device->device_state, + STATE_ADDRESSED); + return 0; + + case USB_REQ_SET_CONFIGURATION: + if (!purb->device_request.wValue) { + /* Respond at default address */ + usbp->usaddr = 0x00; + mpc8xx_udc_state_transition_down (udc_device->device_state, + STATE_ADDRESSED); + } else { + /* TODO: Support multiple configurations */ + mpc8xx_udc_state_transition_up (udc_device->device_state, + STATE_CONFIGURED); + for (x = 1; x < MAX_ENDPOINTS; x++) { + if ((udc_device->bus->endpoint_array[x].endpoint_address & USB_ENDPOINT_DIR_MASK) + == USB_DIR_IN) { + ep_ref[x].pid = TX_BD_PID_DATA0; + } else { + ep_ref[x].pid = RX_BD_PID_DATA0; } - + /* Set configuration must unstall endpoints */ + usbp->usep[x] &= ~STALL_BITMASK; } - break; - default: - /* CDC/Vendor specific */ - break; + } + break; + default: + /* CDC/Vendor specific */ + break; } /* Send ZLP as ACK in Status OUT phase */ ep_ref[0].pid = TX_BD_PID_DATA1; purb->actual_length = 0; - mpc8xx_udc_init_tx(epi,purb); - mpc8xx_udc_ep_tx(epi); + mpc8xx_udc_init_tx (epi, purb); + mpc8xx_udc_ep_tx (epi); - }else{ - if(purb->actual_length){ + } else { + + if (purb->actual_length) { ep_ref[0].pid = TX_BD_PID_DATA1; - mpc8xx_udc_init_tx(epi,purb); + mpc8xx_udc_init_tx (epi, purb); - if(!(purb->actual_length%EP0_MAX_PACKET_SIZE)){ + if (!(purb->actual_length % EP0_MAX_PACKET_SIZE)) { ep_ref[0].sc |= EP_SEND_ZLP; } - if(purb->device_request.wValue== - USB_DESCRIPTOR_TYPE_DEVICE){ - if(le16_to_cpu(purb->device_request.wLength)> - purb->actual_length){ + if (purb->device_request.wValue == + USB_DESCRIPTOR_TYPE_DEVICE) { + if (le16_to_cpu (purb->device_request.wLength) + > purb->actual_length) { /* Send EP0_MAX_PACKET_SIZE bytes * unless correct size requested. */ - if(purb->actual_length > - epi->tx_packetSize){ - - purb->actual_length = - epi->tx_packetSize; + if (purb->actual_length > epi->tx_packetSize) { + purb->actual_length = epi->tx_packetSize; } - } } - mpc8xx_udc_ep_tx(epi); + mpc8xx_udc_ep_tx (epi); - }else{ + } else { /* Corrupt SETUP packet? */ - ERR("Zero length data or SETUP with DATA-IN phase ?\n"); + ERR ("Zero length data or SETUP with DATA-IN phase ?\n"); return 1; } } @@ -1113,8 +1100,8 @@ static int mpc8xx_udc_ep0_rx_setup (volatile cbd_t * rx_cbdp) * * Setup some basic parameters for a TX transaction */ -static void mpc8xx_udc_init_tx(struct usb_endpoint_instance *epi, - struct urb * tx_urb) +static void mpc8xx_udc_init_tx (struct usb_endpoint_instance *epi, + struct urb *tx_urb) { epi->sent = 0; epi->last = 0; @@ -1125,24 +1112,24 @@ static void mpc8xx_udc_init_tx(struct usb_endpoint_instance *epi, * * Receive ep0/control USB data. Parse and possibly send a response. */ -static void mpc8xx_udc_ep0_rx(volatile cbd_t * rx_cbdp) +static void mpc8xx_udc_ep0_rx (volatile cbd_t * rx_cbdp) { - if(rx_cbdp->cbd_sc&RX_BD_PID_SETUP){ - + if (rx_cbdp->cbd_sc & RX_BD_PID_SETUP) { + /* Unconditionally accept SETUP packets */ - if(mpc8xx_udc_ep0_rx_setup(rx_cbdp)){ - mpc8xx_udc_stall (0); + if (mpc8xx_udc_ep0_rx_setup (rx_cbdp)) { + mpc8xx_udc_stall (0); } - + } else { - - mpc8xx_udc_clear_rxbd(rx_cbdp); - - if((rx_cbdp->cbd_datlen-2)){ + + mpc8xx_udc_clear_rxbd (rx_cbdp); + + if ((rx_cbdp->cbd_datlen - 2)) { /* SETUP with a DATA phase - * outside of SETUP packet. - * Reply with STALL. - */ + * outside of SETUP packet. + * Reply with STALL. + */ mpc8xx_udc_stall (0); } } @@ -1151,7 +1138,7 @@ static void mpc8xx_udc_ep0_rx(volatile cbd_t * rx_cbdp) /* mpc8xx_udc_epn_rx * * Receive some data from cbd into USB system urb data abstraction - * Upper layers should NAK if there is insufficient RX data space + * Upper layers should NAK if there is insufficient RX data space */ static int mpc8xx_udc_epn_rx (unsigned int epid, volatile cbd_t * rx_cbdp) { @@ -1159,115 +1146,115 @@ static int mpc8xx_udc_epn_rx (unsigned int epid, volatile cbd_t * rx_cbdp) struct urb *urb = 0; unsigned int x = 0; - if(epid >= MAX_ENDPOINTS || !rx_cbdp->cbd_datlen){ + if (epid >= MAX_ENDPOINTS || !rx_cbdp->cbd_datlen) { return 0; } - - /* USB 2.0 PDF section 8.6.4 + + /* USB 2.0 PDF section 8.6.4 * Discard data with invalid PID it is a resend. */ - if(ep_ref[epid].pid!=(rx_cbdp->cbd_sc&0xC0)){ + if (ep_ref[epid].pid != (rx_cbdp->cbd_sc & 0xC0)) { return 1; } - TOGGLE_RX_PID(ep_ref[epid].pid); - + TOGGLE_RX_PID (ep_ref[epid].pid); + epi = &udc_device->bus->endpoint_array[epid]; urb = epi->rcv_urb; - for(; x<(rx_cbdp->cbd_datlen-2); x++){ - *((unsigned char*)(urb->buffer + urb->actual_length +x)) = - *((unsigned char*)(rx_cbdp->cbd_bufaddr+x)); + for (; x < (rx_cbdp->cbd_datlen - 2); x++) { + *((unsigned char *) (urb->buffer + urb->actual_length + x)) = + *((unsigned char *) (rx_cbdp->cbd_bufaddr + x)); } - if(x){ + if (x) { usbd_rcv_complete (epi, x, 0); - if(ep_ref[epid].urb->status == RECV_ERROR){ - DBG("RX error unset NAK\n"); - udc_unset_nak(epid); + if (ep_ref[epid].urb->status == RECV_ERROR) { + DBG ("RX error unset NAK\n"); + udc_unset_nak (epid); } - } + } return x; } /* mpc8xx_udc_clock_init * - * Obtain a clock reference for Full Speed Signaling + * Obtain a clock reference for Full Speed Signaling */ -static void mpc8xx_udc_clock_init (volatile immap_t * immr, - volatile cpm8xx_t * cp) +static void mpc8xx_udc_clock_init (volatile immap_t * immr, + volatile cpm8xx_t * cp) { #if defined(CFG_USB_EXTC_CLK) /* This has been tested with a 48MHz crystal on CLK6 */ - switch(CFG_USB_EXTC_CLK){ - case 1: - immr->im_ioport.iop_papar|= 0x0100; - immr->im_ioport.iop_padir&= ~0x0100; - cp->cp_sicr|= 0x24; - break; - case 2: - immr->im_ioport.iop_papar|= 0x0200; - immr->im_ioport.iop_padir&= ~0x0200; - cp->cp_sicr|= 0x2D; - break; - case 3: - immr->im_ioport.iop_papar|= 0x0400; - immr->im_ioport.iop_padir&= ~0x0400; - cp->cp_sicr|= 0x36; - break; - case 4: - immr->im_ioport.iop_papar|= 0x0800; - immr->im_ioport.iop_padir&= ~0x0800; - cp->cp_sicr|= 0x3F; - break; - default: - udc_state = STATE_ERROR; - break; + switch (CFG_USB_EXTC_CLK) { + case 1: + immr->im_ioport.iop_papar |= 0x0100; + immr->im_ioport.iop_padir &= ~0x0100; + cp->cp_sicr |= 0x24; + break; + case 2: + immr->im_ioport.iop_papar |= 0x0200; + immr->im_ioport.iop_padir &= ~0x0200; + cp->cp_sicr |= 0x2D; + break; + case 3: + immr->im_ioport.iop_papar |= 0x0400; + immr->im_ioport.iop_padir &= ~0x0400; + cp->cp_sicr |= 0x36; + break; + case 4: + immr->im_ioport.iop_papar |= 0x0800; + immr->im_ioport.iop_padir &= ~0x0800; + cp->cp_sicr |= 0x3F; + break; + default: + udc_state = STATE_ERROR; + break; } #elif defined(CFG_USB_BRGCLK) - /* This has been tested with brgclk == 50MHz */ + /* This has been tested with brgclk == 50MHz */ DECLARE_GLOBAL_DATA_PTR; int divisor = 0; - if(gd->cpu_clk<48000000L){ - ERR("brgclk is too slow for full-speed USB!\n"); + if (gd->cpu_clk < 48000000L) { + ERR ("brgclk is too slow for full-speed USB!\n"); udc_state = STATE_ERROR; return; } /* Assume the brgclk is 'good enough', we want !(gd->cpu_clk%48Mhz) * but, can /probably/ live with close-ish alternative rates. - */ - divisor = (gd->cpu_clk/48000000L)-1; + */ + divisor = (gd->cpu_clk / 48000000L) - 1; cp->cp_sicr &= ~0x0000003F; - - switch(CFG_USB_BRGCLK){ - case 1: - cp->cp_brgc1 |= (divisor|CPM_BRG_EN); - cp->cp_sicr &= ~0x2F; - break; - case 2: - cp->cp_brgc2 |= (divisor|CPM_BRG_EN); - cp->cp_sicr |= 0x00000009; - break; - case 3: - cp->cp_brgc3 |= (divisor|CPM_BRG_EN); - cp->cp_sicr |= 0x00000012; - break; - case 4: - cp->cp_brgc4 = (divisor|CPM_BRG_EN); - cp->cp_sicr |= 0x0000001B; - break; - default: - udc_state = STATE_ERROR; - break; + + switch (CFG_USB_BRGCLK) { + case 1: + cp->cp_brgc1 |= (divisor | CPM_BRG_EN); + cp->cp_sicr &= ~0x2F; + break; + case 2: + cp->cp_brgc2 |= (divisor | CPM_BRG_EN); + cp->cp_sicr |= 0x00000009; + break; + case 3: + cp->cp_brgc3 |= (divisor | CPM_BRG_EN); + cp->cp_sicr |= 0x00000012; + break; + case 4: + cp->cp_brgc4 = (divisor | CPM_BRG_EN); + cp->cp_sicr |= 0x0000001B; + break; + default: + udc_state = STATE_ERROR; + break; } #else - #error "CFG_USB_EXTC_CLK or CFG_USB_BRGCLK must be defined" +#error "CFG_USB_EXTC_CLK or CFG_USB_BRGCLK must be defined" #endif } @@ -1278,51 +1265,51 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr, */ static void mpc8xx_udc_cbd_attach (int ep, uchar tx_size, uchar rx_size) { - - if (!tx_cbd[ep] || !rx_cbd[ep] || ep >= MAX_ENDPOINTS){ + + if (!tx_cbd[ep] || !rx_cbd[ep] || ep >= MAX_ENDPOINTS) { udc_state = STATE_ERROR; return; } - if (tx_size>USB_MAX_PKT || rx_size>USB_MAX_PKT || - (!tx_size && !rx_size)){ + if (tx_size > USB_MAX_PKT || rx_size > USB_MAX_PKT || + (!tx_size && !rx_size)) { udc_state = STATE_ERROR; return; } /* Attach CBD to appropiate Parameter RAM Endpoint data structure */ - if(rx_size){ - endpoints[ep]->rbase = (u32)rx_cbd[rx_ct]; - endpoints[ep]->rbptr = (u32)rx_cbd[rx_ct]; + if (rx_size) { + endpoints[ep]->rbase = (u32) rx_cbd[rx_ct]; + endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct]; rx_ct++; - if(!ep){ - - endpoints[ep]->rbptr = (u32)rx_cbd[rx_ct]; + if (!ep) { + + endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct]; rx_cbd[rx_ct]->cbd_sc |= RX_BD_W; rx_ct++; - }else{ + } else { rx_ct += 2; - endpoints[ep]->rbptr = (u32)rx_cbd[rx_ct]; + endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct]; rx_cbd[rx_ct]->cbd_sc |= RX_BD_W; rx_ct++; } /* Where we expect to RX data on this endpoint */ - ep_ref[ep].prx = rx_cbd[rx_ct-1]; - }else{ + ep_ref[ep].prx = rx_cbd[rx_ct - 1]; + } else { ep_ref[ep].prx = 0; endpoints[ep]->rbase = 0; endpoints[ep]->rbptr = 0; } - if(tx_size){ - endpoints[ep]->tbase = (u32)tx_cbd[tx_ct]; - endpoints[ep]->tbptr = (u32)tx_cbd[tx_ct]; + if (tx_size) { + endpoints[ep]->tbase = (u32) tx_cbd[tx_ct]; + endpoints[ep]->tbptr = (u32) tx_cbd[tx_ct]; tx_ct++; - }else{ + } else { endpoints[ep]->tbase = 0; endpoints[ep]->tbptr = 0; } @@ -1330,13 +1317,14 @@ static void mpc8xx_udc_cbd_attach (int ep, uchar tx_size, uchar rx_size) endpoints[ep]->tstate = 0; endpoints[ep]->tbcnt = 0; endpoints[ep]->mrblr = EP_MAX_PKT; - endpoints[ep]->rfcr = 0x18; + endpoints[ep]->rfcr = 0x18; endpoints[ep]->tfcr = 0x18; ep_ref[ep].sc |= EP_ATTACHED; - DBG("ep %d rbase 0x%08x rbptr 0x%08x tbase 0x%08x tbptr 0x%08x prx = %p\n", - ep, endpoints[ep]->rbase, endpoints[ep]->rbptr, endpoints[ep]->tbase, - endpoints[ep]->tbptr, ep_ref[ep].prx); + DBG ("ep %d rbase 0x%08x rbptr 0x%08x tbase 0x%08x tbptr 0x%08x prx = %p\n", + ep, endpoints[ep]->rbase, endpoints[ep]->rbptr, + endpoints[ep]->tbase, endpoints[ep]->tbptr, + ep_ref[ep].prx); return; } @@ -1349,28 +1337,28 @@ static void mpc8xx_udc_cbd_init (void) { int i = 0; - for(; icbd_bufaddr = + mpc8xx_udc_alloc (EP_MAX_PKT, sizeof (int)); - for(i=0; i< TX_RING_SIZE; i++){ - tx_cbd[i]->cbd_bufaddr = - mpc8xx_udc_alloc(EP_MAX_PKT, sizeof(int)); - - tx_cbd[i]->cbd_sc = (TX_BD_I | TX_BD_W); + tx_cbd[i]->cbd_sc = (TX_BD_I | TX_BD_W); tx_cbd[i]->cbd_datlen = 0x0000; } - for(i=0; i< RX_RING_SIZE; i++){ - rx_cbd[i]->cbd_bufaddr = - mpc8xx_udc_alloc(EP_MAX_PKT, sizeof(int)); + for (i = 0; i < RX_RING_SIZE; i++) { + rx_cbd[i]->cbd_bufaddr = + mpc8xx_udc_alloc (EP_MAX_PKT, sizeof (int)); rx_cbd[i]->cbd_sc = (RX_BD_I | RX_BD_E); rx_cbd[i]->cbd_datlen = 0x0000; @@ -1387,25 +1375,25 @@ static void mpc8xx_udc_endpoint_init (void) { int i = 0; - for(; i Entering device setup"); - + do { const int setup_pktsize = 8; unsigned char *datap = @@ -1518,7 +1518,7 @@ void udc_startup_events (struct usb_device_instance *device) } /** - * udc_irq - do pseudo interrupts + * udc_irq - do pseudo interrupts */ void udc_irq(void) { diff --git a/drivers/usbtty.c b/drivers/usbtty.c index ed96999e820..d41a00b8cf4 100644 --- a/drivers/usbtty.c +++ b/drivers/usbtty.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2003 * Gerry Hamel, geh@ti.com, Texas Instruments - * + * * (C) Copyright 2006 * Bryan O'Donoghue, bodonoghue@codehermit.ie * @@ -31,7 +31,7 @@ #include "usb_cdc_acm.h" #include "usbdescriptors.h" #include /* If defined, override Linux identifiers with - * vendor specific ones */ + * vendor specific ones */ #if 0 #define TTYDBG(fmt,args...)\ @@ -142,10 +142,10 @@ static struct usb_device_descriptor device_descriptor = { struct acm_config_desc { struct usb_configuration_descriptor configuration_desc; - + /* Master Interface */ struct usb_interface_descriptor interface_desc; - + struct usb_class_header_function_descriptor usb_class_header; struct usb_class_call_management_descriptor usb_class_call_mgt; struct usb_class_abstract_control_descriptor usb_class_acm; @@ -154,22 +154,22 @@ struct acm_config_desc { /* Slave Interface */ struct usb_interface_descriptor data_class_interface; - struct usb_endpoint_descriptor + struct usb_endpoint_descriptor data_endpoints[NUM_ENDPOINTS-1] __attribute__((packed)); } __attribute__((packed)); static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = { { .configuration_desc ={ - .bLength = + .bLength = sizeof(struct usb_configuration_descriptor), .bDescriptorType = USB_DT_CONFIG, - .wTotalLength = + .wTotalLength = cpu_to_le16(sizeof(struct acm_config_desc)), .bNumInterfaces = NUM_ACM_INTERFACES, .bConfigurationValue = 1, .iConfiguration = STR_CONFIG, - .bmAttributes = + .bmAttributes = BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED, .bMaxPower = USBTTY_MAXPOWER }, @@ -180,62 +180,62 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = { .bInterfaceNumber = 0, .bAlternateSetting = 0, .bNumEndpoints = 0x01, - .bInterfaceClass = + .bInterfaceClass = COMMUNICATIONS_INTERFACE_CLASS_CONTROL, .bInterfaceSubClass = COMMUNICATIONS_ACM_SUBCLASS, .bInterfaceProtocol = COMMUNICATIONS_V25TER_PROTOCOL, .iInterface = STR_CTRL_INTERFACE, }, .usb_class_header = { - .bFunctionLength = + .bFunctionLength = sizeof(struct usb_class_header_function_descriptor), - .bDescriptorType = CS_INTERFACE, + .bDescriptorType = CS_INTERFACE, .bDescriptorSubtype = USB_ST_HEADER, .bcdCDC = cpu_to_le16(110), }, .usb_class_call_mgt = { - .bFunctionLength = + .bFunctionLength = sizeof(struct usb_class_call_management_descriptor), .bDescriptorType = CS_INTERFACE, .bDescriptorSubtype = USB_ST_CMF, - .bmCapabilities = 0x00, - .bDataInterface = 0x01, + .bmCapabilities = 0x00, + .bDataInterface = 0x01, }, .usb_class_acm = { - .bFunctionLength = + .bFunctionLength = sizeof(struct usb_class_abstract_control_descriptor), .bDescriptorType = CS_INTERFACE, - .bDescriptorSubtype = USB_ST_ACMF, - .bmCapabilities = 0x00, + .bDescriptorSubtype = USB_ST_ACMF, + .bmCapabilities = 0x00, }, .usb_class_union = { - .bFunctionLength = + .bFunctionLength = sizeof(struct usb_class_union_function_descriptor), .bDescriptorType = CS_INTERFACE, .bDescriptorSubtype = USB_ST_UF, - .bMasterInterface = 0x00, - .bSlaveInterface0 = 0x01, + .bMasterInterface = 0x00, + .bSlaveInterface0 = 0x01, }, .notification_endpoint = { - .bLength = + .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = 0x01 | USB_DIR_IN, .bmAttributes = USB_ENDPOINT_XFER_INT, - .wMaxPacketSize + .wMaxPacketSize = cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE), .bInterval = 0xFF, }, /* Interface 2 */ .data_class_interface = { - .bLength = + .bLength = sizeof(struct usb_interface_descriptor), .bDescriptorType = USB_DT_INTERFACE, .bInterfaceNumber = 0x01, .bAlternateSetting = 0x00, .bNumEndpoints = 0x02, - .bInterfaceClass = + .bInterfaceClass = COMMUNICATIONS_INTERFACE_CLASS_DATA, .bInterfaceSubClass = DATA_INTERFACE_SUBCLASS_NONE, .bInterfaceProtocol = DATA_INTERFACE_PROTOCOL_NONE, @@ -243,30 +243,30 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = { }, .data_endpoints = { { - .bLength = + .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = 0x02 | USB_DIR_OUT, - .bmAttributes = + .bmAttributes = USB_ENDPOINT_XFER_BULK, - .wMaxPacketSize = + .wMaxPacketSize = cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE), .bInterval = 0xFF, }, { - .bLength = + .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = 0x03 | USB_DIR_IN, - .bmAttributes = + .bmAttributes = USB_ENDPOINT_XFER_BULK, - .wMaxPacketSize = + .wMaxPacketSize = cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE), .bInterval = 0xFF, }, }, }, -}; +}; static struct rs232_emu rs232_desc={ .dter = 115200, @@ -282,75 +282,75 @@ static struct rs232_emu rs232_desc={ struct gserial_config_desc { - + struct usb_configuration_descriptor configuration_desc; - struct usb_interface_descriptor + struct usb_interface_descriptor interface_desc[NUM_GSERIAL_INTERFACES] __attribute__((packed)); - struct usb_endpoint_descriptor + struct usb_endpoint_descriptor data_endpoints[NUM_ENDPOINTS] __attribute__((packed)); } __attribute__((packed)); -static struct gserial_config_desc +static struct gserial_config_desc gserial_configuration_descriptors[NUM_CONFIGS] ={ { .configuration_desc ={ .bLength = sizeof(struct usb_configuration_descriptor), .bDescriptorType = USB_DT_CONFIG, - .wTotalLength = + .wTotalLength = cpu_to_le16(sizeof(struct gserial_config_desc)), .bNumInterfaces = NUM_GSERIAL_INTERFACES, .bConfigurationValue = 1, .iConfiguration = STR_CONFIG, - .bmAttributes = + .bmAttributes = BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED, .bMaxPower = USBTTY_MAXPOWER }, .interface_desc = { { - .bLength = + .bLength = sizeof(struct usb_interface_descriptor), .bDescriptorType = USB_DT_INTERFACE, .bInterfaceNumber = 0, .bAlternateSetting = 0, .bNumEndpoints = NUM_ENDPOINTS, - .bInterfaceClass = + .bInterfaceClass = COMMUNICATIONS_INTERFACE_CLASS_VENDOR, - .bInterfaceSubClass = + .bInterfaceSubClass = COMMUNICATIONS_NO_SUBCLASS, - .bInterfaceProtocol = + .bInterfaceProtocol = COMMUNICATIONS_NO_PROTOCOL, .iInterface = STR_DATA_INTERFACE }, }, .data_endpoints = { { - .bLength = + .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = 0x01 | USB_DIR_OUT, .bmAttributes = USB_ENDPOINT_XFER_BULK, - .wMaxPacketSize = + .wMaxPacketSize = cpu_to_le16(CONFIG_USBD_SERIAL_OUT_PKTSIZE), .bInterval= 0xFF, }, { - .bLength = + .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = 0x02 | USB_DIR_IN, .bmAttributes = USB_ENDPOINT_XFER_BULK, - .wMaxPacketSize = + .wMaxPacketSize = cpu_to_le16(CONFIG_USBD_SERIAL_IN_PKTSIZE), .bInterval = 0xFF, }, { - .bLength = + .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = 0x03 | USB_DIR_IN, .bmAttributes = USB_ENDPOINT_XFER_INT, - .wMaxPacketSize = + .wMaxPacketSize = cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE), .bInterval = 0xFF, }, @@ -368,7 +368,7 @@ static void usbtty_init_endpoints (void); static void usbtty_init_terminal_type(short type); static void usbtty_event_handler (struct usb_device_instance *device, usb_device_event_t event, int data); -static int usbtty_cdc_setup(struct usb_device_request *request, +static int usbtty_cdc_setup(struct usb_device_request *request, struct urb *urb); static int usbtty_configured (void); static int write_buffer (circbuf_t * buf); @@ -477,12 +477,12 @@ static void __usbtty_puts (const char *str, int len) /* Empty buffer here, if needed, to ensure space... */ if (space) { write_buffer (&usbtty_output); - + n = MIN (space, MIN (len, maxlen)); buf_push (&usbtty_output, str, n); str += n; - len -= n; + len -= n; } } } @@ -543,7 +543,7 @@ int drv_usbtty_init (void) tt = "generic"; } usbtty_init_terminal_type(strcmp(tt,"cdc_acm")); - + /* prepare buffers... */ buf_init (&usbtty_input, USBTTY_BUFFER_SIZE); buf_init (&usbtty_output, USBTTY_BUFFER_SIZE); @@ -579,7 +579,7 @@ static void usbtty_init_strings (void) { struct usb_string_descriptor *string; - usbtty_string_table[STR_LANG] = + usbtty_string_table[STR_LANG] = (struct usb_string_descriptor*)wstrLang; string = (struct usb_string_descriptor *) wstrManufacturer; @@ -624,7 +624,7 @@ static void usbtty_init_strings (void) /* Now, initialize the string table for ep0 handling */ usb_strings = usbtty_string_table; -} +} static void usbtty_init_instances (void) { @@ -690,7 +690,7 @@ static void usbtty_init_instances (void) endpoint_instance[i].rcv_packetSize = le16_to_cpu(ep_descriptor_ptrs[i - 1]->wMaxPacketSize); - + endpoint_instance[i].tx_attributes = ep_descriptor_ptrs[i - 1]->bmAttributes; @@ -721,30 +721,30 @@ static void usbtty_init_endpoints (void) int i; bus_instance->max_endpoints = NUM_ENDPOINTS + 1; - for (i = 1; i <= NUM_ENDPOINTS; i++) { + for (i = 1; i <= NUM_ENDPOINTS; i++) { udc_setup_ep (device_instance, i, &endpoint_instance[i]); } } /* usbtty_init_terminal_type - * + * * Do some late binding for our device type. */ static void usbtty_init_terminal_type(short type) { switch(type){ - /* CDC ACM */ + /* CDC ACM */ case 0: /* Assign endpoint descriptors */ - ep_descriptor_ptrs[0] = + ep_descriptor_ptrs[0] = &acm_configuration_descriptors[0].notification_endpoint; - ep_descriptor_ptrs[1] = + ep_descriptor_ptrs[1] = &acm_configuration_descriptors[0].data_endpoints[0]; - ep_descriptor_ptrs[2] = + ep_descriptor_ptrs[2] = &acm_configuration_descriptors[0].data_endpoints[1]; /* Enumerate Device Descriptor */ - device_descriptor.bDeviceClass = + device_descriptor.bDeviceClass = COMMUNICATIONS_DEVICE_CLASS; device_descriptor.idProduct = cpu_to_le16(CONFIG_USBD_PRODUCTID_CDCACM); @@ -752,7 +752,7 @@ static void usbtty_init_terminal_type(short type) /* Assign endpoint indices */ tx_endpoint = ACM_TX_ENDPOINT; rx_endpoint = ACM_RX_ENDPOINT; - + /* Configuration Descriptor */ configuration_descriptor = (struct usb_configuration_descriptor*) @@ -766,11 +766,11 @@ static void usbtty_init_terminal_type(short type) case 1: default: /* Assign endpoint descriptors */ - ep_descriptor_ptrs[0] = + ep_descriptor_ptrs[0] = &gserial_configuration_descriptors[0].data_endpoints[0]; - ep_descriptor_ptrs[1] = + ep_descriptor_ptrs[1] = &gserial_configuration_descriptors[0].data_endpoints[1]; - ep_descriptor_ptrs[2] = + ep_descriptor_ptrs[2] = &gserial_configuration_descriptors[0].data_endpoints[2]; /* Enumerate Device Descriptor */ @@ -783,7 +783,7 @@ static void usbtty_init_terminal_type(short type) rx_endpoint = GSERIAL_RX_ENDPOINT; /* Configuration Descriptor */ - configuration_descriptor = + configuration_descriptor = (struct usb_configuration_descriptor*) &gserial_configuration_descriptors; @@ -832,14 +832,14 @@ static int write_buffer (circbuf_t * buf) if (!usbtty_configured ()) { return 0; } - + struct usb_endpoint_instance *endpoint = &endpoint_instance[tx_endpoint]; struct urb *current_urb = NULL; current_urb = next_urb (device_instance, endpoint); - /* TX data still exists - send it now - */ + /* TX data still exists - send it now + */ if(endpoint->sent < current_urb->actual_length){ if(udc_endpoint_write (endpoint)){ /* Write pre-empted by RX */ @@ -854,11 +854,11 @@ static int write_buffer (circbuf_t * buf) int popnum, popped; int total = 0; - /* Break buffer into urb sized pieces, - * and link each to the endpoint + /* Break buffer into urb sized pieces, + * and link each to the endpoint */ while (buf->size > 0) { - + if (!current_urb) { TTYERR ("current_urb is NULL, buf->size %d\n", buf->size); @@ -881,8 +881,8 @@ static int write_buffer (circbuf_t * buf) current_urb->actual_length += popped; total += popped; - /* If endpoint->last == 0, then transfers have - * not started on this endpoint + /* If endpoint->last == 0, then transfers have + * not started on this endpoint */ if (endpoint->last == 0) { if(udc_endpoint_write (endpoint)){ @@ -904,7 +904,7 @@ static int fill_buffer (circbuf_t * buf) &endpoint_instance[rx_endpoint]; if (endpoint->rcv_urb && endpoint->rcv_urb->actual_length) { - unsigned int nb = 0; + unsigned int nb = 0; char *src = (char *) endpoint->rcv_urb->buffer; unsigned int rx_avail = buf->totalsize - buf->size; @@ -913,7 +913,7 @@ static int fill_buffer (circbuf_t * buf) nb = endpoint->rcv_urb->actual_length; buf_push (buf, src, nb); endpoint->rcv_urb->actual_length = 0; - + } return nb; } @@ -958,7 +958,7 @@ int usbtty_cdc_setup(struct usb_device_request *request, struct urb *urb) case ACM_SEND_ENCAPSULATED_COMMAND : /* Required */ break; case ACM_SET_LINE_ENCODING : /* DTE stop/parity bits - * per character */ + * per character */ break; case ACM_GET_ENCAPSULATED_RESPONSE : /* request response */ break; @@ -986,8 +986,8 @@ void usbtty_poll (void) /* New interrupts? */ udc_irq(); - /* Write any output data to host buffer - * (do this before checking interrupts to avoid missing one) + /* Write any output data to host buffer + * (do this before checking interrupts to avoid missing one) */ if (usbtty_configured ()) { write_buffer (&usbtty_output); @@ -995,9 +995,9 @@ void usbtty_poll (void) /* New interrupts? */ udc_irq(); - - /* Check for new data from host.. - * (do this after checking interrupts to get latest data) + + /* Check for new data from host.. + * (do this after checking interrupts to get latest data) */ if (usbtty_configured ()) { fill_buffer (&usbtty_input); diff --git a/drivers/usbtty.h b/drivers/usbtty.h index 731b76330d4..8154e3072ef 100644 --- a/drivers/usbtty.h +++ b/drivers/usbtty.h @@ -33,7 +33,7 @@ #include -/* If no VendorID/ProductID is defined in config.h, pretend to be Linux +/* If no VendorID/ProductID is defined in config.h, pretend to be Linux * DO NOT Reuse this Vendor/Product setup with protocol incompatible devices */ #define CONFIG_USBD_VENDORID 0x0525 /* Linux/NetChip */ @@ -45,7 +45,7 @@ #define CONFIG_USBD_CONFIGURATION_STR "TTY via USB" -#define CONFIG_USBD_SERIAL_OUT_ENDPOINT UDC_OUT_ENDPOINT +#define CONFIG_USBD_SERIAL_OUT_ENDPOINT UDC_OUT_ENDPOINT #define CONFIG_USBD_SERIAL_OUT_PKTSIZE UDC_OUT_PACKET_SIZE #define CONFIG_USBD_SERIAL_IN_ENDPOINT UDC_IN_ENDPOINT #define CONFIG_USBD_SERIAL_IN_PKTSIZE UDC_IN_PACKET_SIZE diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index c47306cff28..e8cb29903be 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -769,8 +769,6 @@ typedef void (*ExcpHndlr) (void) ; #define UP2OCR __REG(0x40600020) #define UP3OCR __REG(0x40600024) - - /* * USB Host Controller */ diff --git a/include/configs/AdderUSB.h b/include/configs/AdderUSB.h index 2112e56e09c..a4f7f9a28fb 100644 --- a/include/configs/AdderUSB.h +++ b/include/configs/AdderUSB.h @@ -3,7 +3,7 @@ * Bryan O'Donoghue * * Provides support for USB console on the Analogue & Micro Adder87x - * + * * See file CREDITS for list of people who contributed to this * project. * @@ -37,13 +37,13 @@ /* If you have a USB-IF assigned VendorID then you may wish to define * your own vendor specific values either in BoardName.h or directly in - * usbd_vendor_info.h + * usbd_vendor_info.h */ -/* +/* #define CONFIG_USBD_MANUFACTURER "CodeHermit.ie" #define CONFIG_USBD_PRODUCT_NAME "Das U-Boot" -#define CONFIG_USBD_VENDORID 0xFFFF +#define CONFIG_USBD_VENDORID 0xFFFF #define CONFIG_USBD_PRODUCTID_GSERIAL 0xFFFF #define CONFIG_USBD_PRODUCTID_CDCACM 0xFFFE */ diff --git a/include/usb_cdc_acm.h b/include/usb_cdc_acm.h index 8cb16545d37..87bf50c52ba 100644 --- a/include/usb_cdc_acm.h +++ b/include/usb_cdc_acm.h @@ -34,7 +34,7 @@ #define ACM_RESPONSE_AVAILABLE 0x01 #define ACM_SERIAL_STATE 0x20 -/* Format of response expected by a ACM_GET_LINE_ENCODING request */ +/* Format of response expected by a ACM_GET_LINE_ENCODING request */ struct rs232_emu{ unsigned long dter; unsigned char stop_bits; diff --git a/include/usbdcore_mpc8xx.h b/include/usbdcore_mpc8xx.h index e54acd9a1e7..9df62f4ca51 100644 --- a/include/usbdcore_mpc8xx.h +++ b/include/usbdcore_mpc8xx.h @@ -99,7 +99,7 @@ #define TX_BD_TO 0x04 #define TX_BD_NO_PID 0x00 #define TX_BD_PID_DATA0 0x80 -#define TX_BD_PID_DATA1 0xC0 +#define TX_BD_PID_DATA1 0xC0 #define TX_BD_CNF 0x200 #define TX_BD_TC 0x400 #define TX_BD_L 0x800 @@ -151,16 +151,16 @@ typedef struct mpc8xx_usb{ ushort usber; /* Event Register */ ushort res3; /* Reserved */ ushort usbmr; /* Mask Register */ - char res4; /* Reserved */ + char res4; /* Reserved */ char usbs; /* Status Register */ char res5[8]; /* Reserved */ }usb_t; typedef struct mpc8xx_parameter_ram{ - ushort ep0ptr; /* Endpoint Pointer Register 0 */ - ushort ep1ptr; /* Endpoint Pointer Register 1 */ - ushort ep2ptr; /* Endpoint Pointer Register 2 */ - ushort ep3ptr; /* Endpoint Pointer Register 3 */ + ushort ep0ptr; /* Endpoint Pointer Register 0 */ + ushort ep1ptr; /* Endpoint Pointer Register 1 */ + ushort ep2ptr; /* Endpoint Pointer Register 2 */ + ushort ep3ptr; /* Endpoint Pointer Register 3 */ uint rstate; /* Receive state */ uint rptr; /* Receive internal data pointer */ ushort frame_n; /* Frame number */ @@ -198,7 +198,7 @@ int udc_init(void); void udc_irq(void); int udc_endpoint_write(struct usb_endpoint_instance *endpoint); void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, - struct usb_endpoint_instance *endpoint); + struct usb_endpoint_instance *endpoint); void udc_connect(void); void udc_disconnect(void); void udc_enable(struct usb_device_instance *device); diff --git a/include/usbdescriptors.h b/include/usbdescriptors.h index 8336c188c10..a752097e5bc 100644 --- a/include/usbdescriptors.h +++ b/include/usbdescriptors.h @@ -321,7 +321,7 @@ struct usb_class_union_function_descriptor { u8 bDescriptorType; u8 bDescriptorSubtype; /* 0x06 */ u8 bMasterInterface; - //u8 bSlaveInterface0[0]; + /* u8 bSlaveInterface0[0]; */ u8 bSlaveInterface0; } __attribute__ ((packed)); -- cgit v1.3.1 From c74b2108e31fe09bd1c5d291c3cf360510d4f13e Mon Sep 17 00:00:00 2001 From: Sergey Kubushyn Date: Fri, 10 Aug 2007 20:26:18 +0200 Subject: [ARM] TI DaVinci support, hopefully final Add support for the following DaVinci boards: - DV_EVM - SCHMOOGIE - SONATA Changes: - Split into separate board directories - Removed changes to MTD_DEBUG (or whatever it's called) - New CONFIG_CMD party line followed - Some cosmetic fixes, cleanup etc. - Patches against the latest U-Boot tree as of now. - Fixed CONFIG_CMD_NET in net files. - Fixed CONFIG_CMD_EEPROM for schmoogie. - Made sure it compiles and works (forceenv() link problem) on SCHMOOGIE and DV_EVM. Can't check if it works on SONATA, don't have a board any more, but it at least compiles. Here is an excerpt from session log on SCHMOOGIE... U-Boot 1.2.0-g6c33c785-dirty (Aug 7 2007 - 13:07:17) DRAM: 128 MB NAND: 128 MiB In: serial Out: serial Err: serial ARM Clock : 297MHz DDR Clock : 162MHz ETH PHY : DP83848 @ 0x01 U-Boot > iprobe Valid chip addresses: 1B 38 3A 3D 3F 50 5D 6F U-Boot > ping 192.168.253.10 host 192.168.253.10 is alive U-Boot > Signed-off-by: Sergey Kubushyn Acked-by: Dirk Behme Acked-by: Zach Sadecki Acked-by: Stefan Roese --- CREDITS | 4 + MAINTAINERS | 6 + MAKEALL | 3 +- Makefile | 9 + board/davinci/dv-evm/Makefile | 52 +++ board/davinci/dv-evm/board_init.S | 29 ++ board/davinci/dv-evm/config.mk | 39 ++ board/davinci/dv-evm/dv_board.c | 211 +++++++++ board/davinci/dv-evm/u-boot.lds | 52 +++ board/davinci/schmoogie/Makefile | 52 +++ board/davinci/schmoogie/board_init.S | 29 ++ board/davinci/schmoogie/config.mk | 39 ++ board/davinci/schmoogie/dv_board.c | 253 +++++++++++ board/davinci/schmoogie/u-boot.lds | 52 +++ board/davinci/sonata/Makefile | 52 +++ board/davinci/sonata/board_init.S | 100 +++++ board/davinci/sonata/config.mk | 39 ++ board/davinci/sonata/dv_board.c | 208 +++++++++ board/davinci/sonata/u-boot.lds | 52 +++ common/cmd_nvedit.c | 15 +- cpu/arm926ejs/davinci/Makefile | 49 +++ cpu/arm926ejs/davinci/dp83848.c | 156 +++++++ cpu/arm926ejs/davinci/ether.c | 652 ++++++++++++++++++++++++++++ cpu/arm926ejs/davinci/i2c.c | 351 +++++++++++++++ cpu/arm926ejs/davinci/lowlevel_init.S | 707 +++++++++++++++++++++++++++++++ cpu/arm926ejs/davinci/lxt972.c | 142 +++++++ cpu/arm926ejs/davinci/nand.c | 389 +++++++++++++++++ cpu/arm926ejs/davinci/reset.S | 77 ++++ cpu/arm926ejs/davinci/timer.c | 165 ++++++++ include/_exports.h | 3 + include/asm-arm/arch-davinci/emac_defs.h | 311 ++++++++++++++ include/asm-arm/arch-davinci/emif_defs.h | 61 +++ include/asm-arm/arch-davinci/hardware.h | 166 ++++++++ include/asm-arm/arch-davinci/i2c_defs.h | 94 ++++ include/asm-arm/arch-davinci/nand_defs.h | 161 +++++++ include/common.h | 3 + include/configs/davinci_dvevm.h | 214 ++++++++++ include/configs/davinci_schmoogie.h | 157 +++++++ include/configs/davinci_sonata.h | 209 +++++++++ include/dp83848.h | 88 ++++ include/exports.h | 3 + lib_arm/board.c | 7 + net/eth.c | 5 + 43 files changed, 5464 insertions(+), 2 deletions(-) create mode 100644 board/davinci/dv-evm/Makefile create mode 100644 board/davinci/dv-evm/board_init.S create mode 100644 board/davinci/dv-evm/config.mk create mode 100644 board/davinci/dv-evm/dv_board.c create mode 100644 board/davinci/dv-evm/u-boot.lds create mode 100644 board/davinci/schmoogie/Makefile create mode 100644 board/davinci/schmoogie/board_init.S create mode 100644 board/davinci/schmoogie/config.mk create mode 100644 board/davinci/schmoogie/dv_board.c create mode 100644 board/davinci/schmoogie/u-boot.lds create mode 100644 board/davinci/sonata/Makefile create mode 100644 board/davinci/sonata/board_init.S create mode 100644 board/davinci/sonata/config.mk create mode 100644 board/davinci/sonata/dv_board.c create mode 100644 board/davinci/sonata/u-boot.lds create mode 100644 cpu/arm926ejs/davinci/Makefile create mode 100644 cpu/arm926ejs/davinci/dp83848.c create mode 100644 cpu/arm926ejs/davinci/ether.c create mode 100644 cpu/arm926ejs/davinci/i2c.c create mode 100644 cpu/arm926ejs/davinci/lowlevel_init.S create mode 100644 cpu/arm926ejs/davinci/lxt972.c create mode 100644 cpu/arm926ejs/davinci/nand.c create mode 100644 cpu/arm926ejs/davinci/reset.S create mode 100644 cpu/arm926ejs/davinci/timer.c create mode 100644 include/asm-arm/arch-davinci/emac_defs.h create mode 100644 include/asm-arm/arch-davinci/emif_defs.h create mode 100644 include/asm-arm/arch-davinci/hardware.h create mode 100644 include/asm-arm/arch-davinci/i2c_defs.h create mode 100644 include/asm-arm/arch-davinci/nand_defs.h create mode 100644 include/configs/davinci_dvevm.h create mode 100644 include/configs/davinci_schmoogie.h create mode 100644 include/configs/davinci_sonata.h create mode 100644 include/dp83848.h (limited to 'include/asm-arm') diff --git a/CREDITS b/CREDITS index 7af1b806ab0..4c8b896f215 100644 --- a/CREDITS +++ b/CREDITS @@ -252,6 +252,10 @@ E: Raghu.Krishnaprasad@fci.com D: Support for Adder-II MPC852T evaluation board W: http://www.forcecomputers.com +N: Sergey Kubushyn +E: ksi@koi8.net +D: Support for various TI DaVinci based boards. + N: Bernhard Kuhn E: bkuhn@metrowerks.com D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards diff --git a/MAINTAINERS b/MAINTAINERS index 693b1157290..865f6fe0e12 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -444,6 +444,12 @@ Nishant Kamat omap1610h2 ARM926EJS +Sergey Kubushyn + + DV-EVM ARM926EJS + SONATA ARM926EJS + SCHMOOGIE ARM926EJS + Prakash Kumar cerf250 xscale diff --git a/MAKEALL b/MAKEALL index 3e186ccd5a3..c672b514be4 100755 --- a/MAKEALL +++ b/MAKEALL @@ -220,7 +220,8 @@ LIST_ARM9=" \ omap1610h2 omap1610inn omap730p2 sbc2410x \ scb9328 smdk2400 smdk2410 trab \ VCMA9 versatile versatileab versatilepb \ - voiceblue \ + voiceblue davinci_dvevm davinci_schmoogie \ + davinci_sonata " ######################################################################### diff --git a/Makefile b/Makefile index 0e6d3992dbe..87ddb1c933d 100644 --- a/Makefile +++ b/Makefile @@ -2018,6 +2018,15 @@ omap1510inn_config : unconfig omap5912osk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk NULL omap +davinci_dvevm_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs dv-evm davinci davinci + +davinci_schmoogie_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci + +davinci_sonata_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci + omap1610inn_config \ omap1610inn_cs0boot_config \ omap1610inn_cs3boot_config \ diff --git a/board/davinci/dv-evm/Makefile b/board/davinci/dv-evm/Makefile new file mode 100644 index 00000000000..fa0013811d4 --- /dev/null +++ b/board/davinci/dv-evm/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/dv-evm/board_init.S b/board/davinci/dv-evm/board_init.S new file mode 100644 index 00000000000..22d8adc18ca --- /dev/null +++ b/board/davinci/dv-evm/board_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl dv_board_init +dv_board_init: + + mov pc, lr diff --git a/board/davinci/dv-evm/config.mk b/board/davinci/dv-evm/config.mk new file mode 100644 index 00000000000..aa89d0ec8ae --- /dev/null +++ b/board/davinci/dv-evm/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Swaminathan +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dv-evm/dv_board.c new file mode 100644 index 00000000000..94925ecfb14 --- /dev/null +++ b/board/davinci/dv-evm/dv_board.c @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include +#include +#include +#include + +#define MACH_TYPE_DAVINCI_EVM 901 + +extern void i2c_init(int speed, int slaveaddr); +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ( (id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO) + ) + *mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r (void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); + printf ("DDR Clock : %dMHz\n", (clk / 2)); + + /* Set Ethernet MAC address from EEPROM */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) { + printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR); + } else { + tmp[0] = 0xff; + for (i = 0; i < 6; i++) + tmp[0] &= buf[i]; + + if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { + sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + setenv("ethaddr", (char *)&tmp[0]); + } + } + + if (!eth_hw_init()) { + printf("ethernet init failed!\n"); + } else { + printf("ETH PHY : %s\n", phy.name); + } + + i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1); + + setenv ("videostd", ((i & 0x80) ? "pal" : "ntsc")); + + return(0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/dv-evm/u-boot.lds b/board/davinci/dv-evm/u-boot.lds new file mode 100644 index 00000000000..710b2a2d6e6 --- /dev/null +++ b/board/davinci/dv-evm/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/davinci/schmoogie/Makefile b/board/davinci/schmoogie/Makefile new file mode 100644 index 00000000000..fa0013811d4 --- /dev/null +++ b/board/davinci/schmoogie/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/schmoogie/board_init.S b/board/davinci/schmoogie/board_init.S new file mode 100644 index 00000000000..22d8adc18ca --- /dev/null +++ b/board/davinci/schmoogie/board_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl dv_board_init +dv_board_init: + + mov pc, lr diff --git a/board/davinci/schmoogie/config.mk b/board/davinci/schmoogie/config.mk new file mode 100644 index 00000000000..aa89d0ec8ae --- /dev/null +++ b/board/davinci/schmoogie/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Swaminathan +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/dv_board.c new file mode 100644 index 00000000000..b15c5f71893 --- /dev/null +++ b/board/davinci/schmoogie/dv_board.c @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include +#include +#include +#include + +#define MACH_TYPE_SCHMOOGIE 1255 + +extern void i2c_init(int speed, int slaveaddr); +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ( (id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO) + ) + *mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r (void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + /* Set serial number from UID chip */ + u_int8_t crc_tbl[256] = { + 0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83, + 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41, + 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e, + 0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc, + 0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0, + 0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62, + 0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d, + 0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff, + 0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5, + 0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07, + 0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58, + 0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a, + 0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6, + 0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24, + 0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b, + 0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9, + 0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f, + 0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd, + 0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92, + 0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50, + 0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c, + 0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee, + 0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1, + 0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73, + 0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49, + 0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b, + 0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4, + 0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16, + 0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a, + 0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8, + 0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7, + 0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35 + }; + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); + printf ("DDR Clock : %dMHz\n", (clk / 2)); + + /* Set serial number from UID chip */ + if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) { + printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); + forceenv("serial#", "FAILED"); + } else { + if (buf[0] != 0x70) { /* Device Family Code */ + printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); + forceenv("serial#", "FAILED"); + } + } + /* Now check CRC */ + tmp[0] = 0; + for (i = 0; i < 8; i++) + tmp[0] = crc_tbl[tmp[0] ^ buf[i]]; + + if (tmp[0] != 0) { + printf("\nUID @ 0x%02x - BAD CRC!!!\n", CFG_UID_ADDR); + forceenv("serial#", "FAILED"); + } else { + /* CRC OK, set "serial" env variable */ + sprintf((char *)&tmp[0], "%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx", + buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]); + forceenv("serial#", (char *)&tmp[0]); + } + + if (!eth_hw_init()) { + printf("ethernet init failed!\n"); + } else { + printf("ETH PHY : %s\n", phy.name); + } + + return(0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/schmoogie/u-boot.lds b/board/davinci/schmoogie/u-boot.lds new file mode 100644 index 00000000000..710b2a2d6e6 --- /dev/null +++ b/board/davinci/schmoogie/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/davinci/sonata/Makefile b/board/davinci/sonata/Makefile new file mode 100644 index 00000000000..fa0013811d4 --- /dev/null +++ b/board/davinci/sonata/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/sonata/board_init.S b/board/davinci/sonata/board_init.S new file mode 100644 index 00000000000..fbb9ea73e9f --- /dev/null +++ b/board/davinci/sonata/board_init.S @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer + * Sonata boards, AFAIK, don't use this so it's just return by default. Ask + * Visioneering if they reinvented the wheel once again to make sure :) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl dv_board_init +dv_board_init: +#ifdef SONATA_BOARD_GPIOWP + /* Set PINMUX0 to enable GPIO4 */ + ldr r0, _PINMUX0 + ldr r1, GPIO4_EN_MASK + ldr r2, [r0] + and r2, r2, r1 + str r2, [r0] + + /* Enable GPIO LPSC module */ + ldr r0, PTSTAT + +gpio_ptstat_loop1: + ldr r2, [r0] + tst r2, $0x00000001 + bne gpio_ptstat_loop1 + + ldr r1, MDCTL_GPIO + ldr r2, [r1] + and r2, r2, $0xfffffff8 + orr r2, r2, $0x00000003 + str r2, [r1] + + orr r2, r2, $0x00000200 + str r2, [r1] + + ldr r1, PTCMD + mov r2, $0x00000001 + str r2, [r1] + +gpio_ptstat_loop2: + ldr r2, [r0] + tst r2, $0x00000001 + bne gpio_ptstat_loop2 + + ldr r0, MDSTAT_GPIO +gpio_mdstat_loop: + ldr r2, [r0] + and r2, r2, $0x0000001f + teq r2, $0x00000003 + bne gpio_mdstat_loop + + /* GPIO4 -> output */ + ldr r0, GPIO_DIR01 + mov r1, $0x10 + ldr r2, [r0] + bic r2, r2, r0 + str r2, [r0] + + /* Set it to 0 (Write Protect) */ + ldr r0, GPIO_CLR_DATA01 + str r1, [r0] +#endif + + mov pc, lr + +#ifdef SONATA_BOARD_GPIOWP +.ltorg + +GPIO4_EN_MASK: + .word 0xf77fffff +MDCTL_GPIO: + .word 0x01c41a68 +MDSTAT_GPIO: + .word 0x01c41868 +GPIO_DIR01: + .word 0x01c67010 +GPIO_CLR_DATA01: + .word 0x01c6701c +#endif diff --git a/board/davinci/sonata/config.mk b/board/davinci/sonata/config.mk new file mode 100644 index 00000000000..aa89d0ec8ae --- /dev/null +++ b/board/davinci/sonata/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Swaminathan +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/dv_board.c new file mode 100644 index 00000000000..7b0a459fa31 --- /dev/null +++ b/board/davinci/sonata/dv_board.c @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include +#include +#include +#include + +#define MACH_TYPE_SONATA 1254 + +extern void i2c_init(int speed, int slaveaddr); +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ( (id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO) + ) + *mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_SONATA; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r (void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); + printf ("DDR Clock : %dMHz\n", (clk / 2)); + + /* Set Ethernet MAC address from EEPROM */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) { + printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR); + } else { + tmp[0] = 0xff; + for (i = 0; i < 6; i++) + tmp[0] &= buf[i]; + + if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { + sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + setenv("ethaddr", (char *)&tmp[0]); + } + } + + if (!eth_hw_init()) { + printf("ethernet init failed!\n"); + } else { + printf("ETH PHY : %s\n", phy.name); + } + + return(0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/sonata/u-boot.lds b/board/davinci/sonata/u-boot.lds new file mode 100644 index 00000000000..710b2a2d6e6 --- /dev/null +++ b/board/davinci/sonata/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index de5a5148f69..1db0fc3c03b 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -193,7 +193,12 @@ int _do_setenv (int flag, int argc, char *argv[]) * Ethernet Address and serial# can be set only once, * ver is readonly. */ +#ifdef CONFIG_HAS_UID + /* Allow serial# forced overwrite with 0xdeaf4add flag */ + if ( ((strcmp (name, "serial#") == 0) && (flag != 0xdeaf4add)) || +#else if ( (strcmp (name, "serial#") == 0) || +#endif ((strcmp (name, "ethaddr") == 0) #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) && (strcmp ((char *)env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0) @@ -397,7 +402,15 @@ void setenv (char *varname, char *varvalue) _do_setenv (0, 3, argv); } -int do_setenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +#ifdef CONFIG_HAS_UID +void forceenv (char *varname, char *varvalue) +{ + char *argv[4] = { "forceenv", varname, varvalue, NULL }; + _do_setenv (0xdeaf4add, 3, argv); +} +#endif + +int do_setenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { printf ("Usage:\n%s\n", cmdtp->usage); diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile new file mode 100644 index 00000000000..0f77f402ed8 --- /dev/null +++ b/cpu/arm926ejs/davinci/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o ether.o lxt972.o dp83848.o i2c.o nand.o +SOBJS = lowlevel_init.o reset.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/davinci/dp83848.c b/cpu/arm926ejs/davinci/dp83848.c new file mode 100644 index 00000000000..5719845b340 --- /dev/null +++ b/cpu/arm926ejs/davinci/dp83848.c @@ -0,0 +1,156 @@ +/* + * National Semiconductor DP83848 PHY Driver for TI DaVinci + * (TMS320DM644x) based boards. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * -------------------------------------------------------- + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CONFIG_DRIVER_TI_EMAC + +#ifdef CONFIG_CMD_NET + +int dp83848_is_phy_connected(int phy_addr) +{ + u_int16_t id1, id2; + + if (!dm644x_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1)) + return(0); + if (!dm644x_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2)) + return(0); + + if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI)) + return(1); + + return(0); +} + +int dp83848_get_link_speed(int phy_addr) +{ + u_int16_t tmp; + volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; + + if (!dm644x_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) + return(0); + + if (!(tmp & DP83848_LINK_STATUS)) /* link up? */ + return(0); + + if (!dm644x_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp)) + return(0); + + /* Speed doesn't matter, there is no setting for it in EMAC... */ + if (tmp & DP83848_SPEED) { + if (tmp & DP83848_DUPLEX) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } else { + if (tmp & DP83848_DUPLEX) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } + + return(0); +} + + +int dp83848_init_phy(int phy_addr) +{ + int ret = 1; + + if (!dp83848_get_link_speed(phy_addr)) { + /* Try another time */ + udelay(100000); + ret = dp83848_get_link_speed(phy_addr); + } + + /* Disable PHY Interrupts */ + dm644x_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0); + + return(ret); +} + + +int dp83848_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + + + if (!dm644x_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */ + tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */ + dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); + + /* Set the Auto_negotiation Advertisement Register + * MII advertising for Next page, 100BaseTxFD and HD, + * 10BaseTFD and HD, IEEE 802.3 + */ + tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX | + DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3; + dm644x_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp); + + + /* Read Control Register */ + if (!dm644x_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) + return(0); + + tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE; + dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); + + /* Restart Auto_negotiation */ + tmp |= DP83848_RESTART_AUTONEG; + dm644x_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); + + /*check AutoNegotiate complete */ + udelay(10000); + if (!dm644x_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) + return(0); + + if (!(tmp & DP83848_AUTONEG_COMP)) + return(0); + + return (dp83848_get_link_speed(phy_addr)); +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm926ejs/davinci/ether.c b/cpu/arm926ejs/davinci/ether.c new file mode 100644 index 00000000000..9ec1ee70bf7 --- /dev/null +++ b/cpu/arm926ejs/davinci/ether.c @@ -0,0 +1,652 @@ +/* + * Ethernet driver for TI TMS320DM644x (DaVinci) chips. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright + * follows: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.c + * + * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + + * Modifications: + * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. + * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors + * + */ +#include +#include +#include +#include +#include + +#ifdef CONFIG_DRIVER_TI_EMAC + +#ifdef CONFIG_CMD_NET + +unsigned int emac_dbg = 0; +#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) + +/* Internal static functions */ +static int dm644x_eth_hw_init (void); +static int dm644x_eth_open (void); +static int dm644x_eth_close (void); +static int dm644x_eth_send_packet (volatile void *packet, int length); +static int dm644x_eth_rcv_packet (void); +static void dm644x_eth_mdio_enable(void); + +static int gen_init_phy(int phy_addr); +static int gen_is_phy_connected(int phy_addr); +static int gen_get_link_speed(int phy_addr); +static int gen_auto_negotiate(int phy_addr); + +/* Wrappers exported to the U-Boot proper */ +int eth_hw_init(void) +{ + return(dm644x_eth_hw_init()); +} + +int eth_init(bd_t * bd) +{ + return(dm644x_eth_open()); +} + +void eth_halt(void) +{ + dm644x_eth_close(); +} + +int eth_send(volatile void *packet, int length) +{ + return(dm644x_eth_send_packet(packet, length)); +} + +int eth_rx(void) +{ + return(dm644x_eth_rcv_packet()); +} + +void eth_mdio_enable(void) +{ + dm644x_eth_mdio_enable(); +} +/* End of wrappers */ + + +static u_int8_t dm644x_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + +/* + * This function must be called before emac_open() if you want to override + * the default mac address. + */ +void dm644x_eth_set_mac_addr(const u_int8_t *addr) +{ + int i; + + for (i = 0; i < sizeof (dm644x_eth_mac_addr); i++) { + dm644x_eth_mac_addr[i] = addr[i]; + } +} + +/* EMAC Addresses */ +static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; +static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; +static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; + +/* EMAC descriptors */ +static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); +static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); +static volatile emac_desc *emac_rx_active_head = 0; +static volatile emac_desc *emac_rx_active_tail = 0; +static int emac_rx_queue_active = 0; + +/* Receive packet buffers */ +static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; + +/* PHY address for a discovered PHY (0xff - not found) */ +static volatile u_int8_t active_phy_addr = 0xff; + +phy_t phy; + +static void dm644x_eth_mdio_enable(void) +{ + u_int32_t clkdiv; + + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + + adap_mdio->CONTROL = (clkdiv & 0xff) | + MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT | + MDIO_CONTROL_FAULT_ENABLE; + + while (adap_mdio->CONTROL & MDIO_CONTROL_IDLE) {;} +} + +/* + * Tries to find an active connected PHY. Returns 1 if address if found. + * If no active PHY (or more than one PHY) found returns 0. + * Sets active_phy_addr variable. + */ +static int dm644x_eth_phy_detect(void) +{ + u_int32_t phy_act_state; + int i; + + active_phy_addr = 0xff; + + if ((phy_act_state = adap_mdio->ALIVE) == 0) + return(0); /* No active PHYs */ + + debug_emac("dm644x_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); + + for (i = 0; i < 32; i++) { + if (phy_act_state & (1 << i)) { + if (phy_act_state & ~(1 << i)) + return(0); /* More than one PHY */ + else { + active_phy_addr = i; + return(1); + } + } + } + + return(0); /* Just to make GCC happy */ +} + + +/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ +int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) +{ + int tmp; + + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_READ | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16); + + /* Wait for command to complete */ + while ((tmp = adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) {;} + + if (tmp & MDIO_USERACCESS0_ACK) { + *data = tmp & 0xffff; + return(1); + } + + *data = -1; + return(0); +} + +/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ +int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) +{ + + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_WRITE | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16) | + (data & 0xffff); + + /* Wait for command to complete */ + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + return(1); +} + +/* PHY functions for a generic PHY */ +static int gen_init_phy(int phy_addr) +{ + int ret = 1; + + if (gen_get_link_speed(phy_addr)) { + /* Try another time */ + ret = gen_get_link_speed(phy_addr); + } + + return(ret); +} + +static int gen_is_phy_connected(int phy_addr) +{ + u_int16_t dummy; + + return(dm644x_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy)); +} + +static int gen_get_link_speed(int phy_addr) +{ + u_int16_t tmp; + + if (dm644x_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04)) + return(1); + + return(0); +} + +static int gen_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + + + if (!dm644x_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp |= PHY_BMCR_AUTON; + dm644x_eth_phy_write(phy_addr, PHY_BMCR, tmp); + + /*check AutoNegotiate complete */ + udelay (10000); + if (!dm644x_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) + return(0); + + if (!(tmp & PHY_BMSR_AUTN_COMP)) + return(0); + + return(gen_get_link_speed(phy_addr)); +} +/* End of generic PHY functions */ + + + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +static int dm644x_mii_phy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value) +{ + return(dm644x_eth_phy_read(addr, reg, value) ? 0 : 1); +} + +static int dm644x_mii_phy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value) +{ + return(dm644x_eth_phy_write(addr, reg, value) ? 0 : 1); +} + +int dm644x_eth_miiphy_initialize(bd_t *bis) +{ + miiphy_register(phy.name, dm644x_mii_phy_read, dm644x_mii_phy_write); + + return(1); +} +#endif + +/* + * This function initializes the emac hardware. It does NOT initialize + * EMAC modules power or pin multiplexors, that is done by board_init() + * much earlier in bootup process. Returns 1 on success, 0 otherwise. + */ +static int dm644x_eth_hw_init(void) +{ + u_int32_t phy_id; + u_int16_t tmp; + int i; + + dm644x_eth_mdio_enable(); + + for (i = 0; i < 256; i++) { + if (adap_mdio->ALIVE) + break; + udelay(10); + } + + if (i >= 256) { + printf("No ETH PHY detected!!!\n"); + return(0); + } + + /* Find if a PHY is connected and get it's address */ + if (!dm644x_eth_phy_detect()) + return(0); + + /* Get PHY ID and initialize phy_ops for a detected PHY */ + if (!dm644x_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { + active_phy_addr = 0xff; + return(0); + } + + phy_id = (tmp << 16) & 0xffff0000; + + if (!dm644x_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { + active_phy_addr = 0xff; + return(0); + } + + phy_id |= tmp & 0x0000ffff; + + switch (phy_id) { + case PHY_LXT972: + sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr); + phy.init = lxt972_init_phy; + phy.is_phy_connected = lxt972_is_phy_connected; + phy.get_link_speed = lxt972_get_link_speed; + phy.auto_negotiate = lxt972_auto_negotiate; + break; + case PHY_DP83848: + sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr); + phy.init = dp83848_init_phy; + phy.is_phy_connected = dp83848_is_phy_connected; + phy.get_link_speed = dp83848_get_link_speed; + phy.auto_negotiate = dp83848_auto_negotiate; + break; + default: + sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr); + phy.init = gen_init_phy; + phy.is_phy_connected = gen_is_phy_connected; + phy.get_link_speed = gen_get_link_speed; + phy.auto_negotiate = gen_auto_negotiate; + } + + return(1); +} + + +/* Eth device open */ +static int dm644x_eth_open(void) +{ + dv_reg_p addr; + u_int32_t clkdiv, cnt; + volatile emac_desc *rx_desc; + + debug_emac("+ emac_open\n"); + + /* Reset EMAC module and disable interrupts in wrapper */ + adap_emac->SOFTRESET = 1; + while (adap_emac->SOFTRESET != 0) {;} + adap_ewrap->EWCTL = 0; + for (cnt = 0; cnt < 5; cnt++) { + clkdiv = adap_ewrap->EWCTL; + } + + rx_desc = emac_rx_desc; + + adap_emac->TXCONTROL = 0x01; + adap_emac->RXCONTROL = 0x01; + + /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */ + /* Using channel 0 only - other channels are disabled */ + adap_emac->MACINDEX = 0; + adap_emac->MACADDRHI = + (dm644x_eth_mac_addr[3] << 24) | + (dm644x_eth_mac_addr[2] << 16) | + (dm644x_eth_mac_addr[1] << 8) | + (dm644x_eth_mac_addr[0]); + adap_emac->MACADDRLO = + (dm644x_eth_mac_addr[5] << 8) | + (dm644x_eth_mac_addr[4]); + + adap_emac->MACHASH1 = 0; + adap_emac->MACHASH2 = 0; + + /* Set source MAC address - REQUIRED */ + adap_emac->MACSRCADDRHI = + (dm644x_eth_mac_addr[3] << 24) | + (dm644x_eth_mac_addr[2] << 16) | + (dm644x_eth_mac_addr[1] << 8) | + (dm644x_eth_mac_addr[0]); + adap_emac->MACSRCADDRLO = + (dm644x_eth_mac_addr[4] << 8) | + (dm644x_eth_mac_addr[5]); + + /* Set DMA 8 TX / 8 RX Head pointers to 0 */ + addr = &adap_emac->TX0HDP; + for(cnt = 0; cnt < 16; cnt++) + *addr++ = 0; + + addr = &adap_emac->RX0HDP; + for(cnt = 0; cnt < 16; cnt++) + *addr++ = 0; + + /* Clear Statistics (do this before setting MacControl register) */ + addr = &adap_emac->RXGOODFRAMES; + for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) + *addr++ = 0; + + /* No multicast addressing */ + adap_emac->MACHASH1 = 0; + adap_emac->MACHASH2 = 0; + + /* Create RX queue and set receive process in place */ + emac_rx_active_head = emac_rx_desc; + for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { + rx_desc->next = (u_int32_t)(rx_desc + 1); + rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; + rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; + rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; + rx_desc++; + } + + /* Set the last descriptor's "next" parameter to 0 to end the RX desc list */ + rx_desc--; + rx_desc->next = 0; + emac_rx_active_tail = rx_desc; + emac_rx_queue_active = 1; + + /* Enable TX/RX */ + adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE; + adap_emac->RXBUFFEROFFSET = 0; + + /* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */ + adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN; + + /* Enable ch 0 only */ + adap_emac->RXUNICASTSET = 0x01; + + /* Enable MII interface and Full duplex mode */ + adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE); + + /* Init MDIO & get link state */ + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + adap_mdio->CONTROL = ((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT); + + if (!phy.get_link_speed(active_phy_addr)) + return(0); + + /* Start receive process */ + adap_emac->RX0HDP = (u_int32_t)emac_rx_desc; + + debug_emac("- emac_open\n"); + + return(1); +} + +/* EMAC Channel Teardown */ +static void dm644x_eth_ch_teardown(int ch) +{ + dv_reg dly = 0xff; + dv_reg cnt; + + debug_emac("+ emac_ch_teardown\n"); + + if (ch == EMAC_CH_TX) { + /* Init TX channel teardown */ + adap_emac->TXTEARDOWN = 1; + for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->TX0CP) { + /* Wait here for Tx teardown completion interrupt to occur + * Note: A task delay can be called here to pend rather than + * occupying CPU cycles - anyway it has been found that teardown + * takes very few cpu cycles and does not affect functionality */ + dly--; + udelay(1); + if (dly == 0) + break; + } + adap_emac->TX0CP = cnt; + adap_emac->TX0HDP = 0; + } else { + /* Init RX channel teardown */ + adap_emac->RXTEARDOWN = 1; + for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->RX0CP) { + /* Wait here for Rx teardown completion interrupt to occur + * Note: A task delay can be called here to pend rather than + * occupying CPU cycles - anyway it has been found that teardown + * takes very few cpu cycles and does not affect functionality */ + dly--; + udelay(1); + if (dly == 0) + break; + } + adap_emac->RX0CP = cnt; + adap_emac->RX0HDP = 0; + } + + debug_emac("- emac_ch_teardown\n"); +} + +/* Eth device close */ +static int dm644x_eth_close(void) +{ + debug_emac("+ emac_close\n"); + + dm644x_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ + dm644x_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ + + /* Reset EMAC module and disable interrupts in wrapper */ + adap_emac->SOFTRESET = 1; + adap_ewrap->EWCTL = 0; + + debug_emac("- emac_close\n"); + return(1); +} + +static int tx_send_loop = 0; + +/* + * This function sends a single packet on the network and returns + * positive number (number of bytes transmitted) or negative for error + */ +static int dm644x_eth_send_packet(volatile void *packet, int length) +{ + int ret_status = -1; + tx_send_loop = 0; + + /* Return error if no link */ + if (!phy.get_link_speed(active_phy_addr)) + { + printf("WARN: emac_send_packet: No link\n"); + return (ret_status); + } + + /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ + if (length < EMAC_MIN_ETHERNET_PKT_SIZE) + { + length = EMAC_MIN_ETHERNET_PKT_SIZE; + } + + /* Populate the TX descriptor */ + emac_tx_desc->next = 0; + emac_tx_desc->buffer = (u_int8_t *)packet; + emac_tx_desc->buff_off_len = (length & 0xffff); + emac_tx_desc->pkt_flag_len = ((length & 0xffff) | + EMAC_CPPI_SOP_BIT | + EMAC_CPPI_OWNERSHIP_BIT | + EMAC_CPPI_EOP_BIT); + /* Send the packet */ + adap_emac->TX0HDP = (unsigned int)emac_tx_desc; + + /* Wait for packet to complete or link down */ + while (1) { + if (!phy.get_link_speed(active_phy_addr)) { + dm644x_eth_ch_teardown(EMAC_CH_TX); + return (ret_status); + } + if (adap_emac->TXINTSTATRAW & 0x01) { + ret_status = length; + break; + } + tx_send_loop++; + } + + return(ret_status); +} + +/* + * This function handles receipt of a packet from the network + */ +static int dm644x_eth_rcv_packet(void) +{ + volatile emac_desc *rx_curr_desc; + volatile emac_desc *curr_desc; + volatile emac_desc *tail_desc; + int status, ret = -1; + + rx_curr_desc = emac_rx_active_head; + status = rx_curr_desc->pkt_flag_len; + if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { + if (status & EMAC_CPPI_RX_ERROR_FRAME) { + /* Error in packet - discard it and requeue desc */ + printf("WARN: emac_rcv_pkt: Error in packet\n"); + } else { + NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xffff)); + ret = rx_curr_desc->buff_off_len & 0xffff; + } + + /* Ack received packet descriptor */ + adap_emac->RX0CP = (unsigned int)rx_curr_desc; + curr_desc = rx_curr_desc; + emac_rx_active_head = (volatile emac_desc *)rx_curr_desc->next; + + if (status & EMAC_CPPI_EOQ_BIT) { + if (emac_rx_active_head) { + adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; + } else { + emac_rx_queue_active = 0; + printf("INFO:emac_rcv_packet: RX Queue not active\n"); + } + } + + /* Recycle RX descriptor */ + rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; + rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; + rx_curr_desc->next = 0; + + if (emac_rx_active_head == 0) { + printf("INFO: emac_rcv_pkt: active queue head = 0\n"); + emac_rx_active_head = curr_desc; + emac_rx_active_tail = curr_desc; + if (emac_rx_queue_active != 0) { + adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; + printf("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); + emac_rx_queue_active = 1; + } + } else { + tail_desc = emac_rx_active_tail; + emac_rx_active_tail = curr_desc; + tail_desc->next = (unsigned int)curr_desc; + status = tail_desc->pkt_flag_len; + if (status & EMAC_CPPI_EOQ_BIT) { + adap_emac->RX0HDP = (unsigned int)curr_desc; + status &= ~EMAC_CPPI_EOQ_BIT; + tail_desc->pkt_flag_len = status; + } + } + return(ret); + } + return(0); +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/cpu/arm926ejs/davinci/i2c.c b/cpu/arm926ejs/davinci/i2c.c new file mode 100644 index 00000000000..af9dc034c2a --- /dev/null +++ b/cpu/arm926ejs/davinci/i2c.c @@ -0,0 +1,351 @@ +/* + * TI DaVinci (TMS320DM644x) I2C driver. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * -------------------------------------------------------- + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_DRIVER_DAVINCI_I2C + +#include +#include +#include + +#define CHECK_NACK() \ + do {\ + if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\ + REG(I2C_CON) = 0;\ + return(1);\ + }\ + } while (0) + + +static int wait_for_bus(void) +{ + int stat, timeout; + + REG(I2C_STAT) = 0xffff; + + for (timeout = 0; timeout < 10; timeout++) { + if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) { + REG(I2C_STAT) = 0xffff; + return(0); + } + + REG(I2C_STAT) = stat; + udelay(50000); + } + + REG(I2C_STAT) = 0xffff; + return(1); +} + + +static int poll_i2c_irq(int mask) +{ + int stat, timeout; + + for (timeout = 0; timeout < 10; timeout++) { + udelay(1000); + stat = REG(I2C_STAT); + if (stat & mask) { + return(stat); + } + } + + REG(I2C_STAT) = 0xffff; + return(stat | I2C_TIMEOUT); +} + + +void flush_rx(void) +{ + int dummy; + + while (1) { + if (!(REG(I2C_STAT) & I2C_STAT_RRDY)) + break; + + dummy = REG(I2C_DRR); + REG(I2C_STAT) = I2C_STAT_RRDY; + udelay(1000); + } +} + + +void i2c_init(int speed, int slaveadd) +{ + u_int32_t div, psc; + + if (REG(I2C_CON) & I2C_CON_EN) { + REG(I2C_CON) = 0; + udelay (50000); + } + + psc = 2; + div = (CFG_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ + REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */ + REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */ + REG(I2C_SCLH) = div - REG(I2C_SCLL); + + REG(I2C_OA) = slaveadd; + REG(I2C_CNT) = 0; + + /* Interrupts must be enabled or I2C module won't work */ + REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | + I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE; + + /* Now enable I2C controller (get it out of reset) */ + REG(I2C_CON) = I2C_CON_EN; + + udelay(1000); +} + + +int i2c_probe(u_int8_t chip) +{ + int rc = 1; + + if (chip == REG(I2C_OA)) { + return(rc); + } + + REG(I2C_CON) = 0; + if (wait_for_bus()) {return(1);} + + /* try to read one byte from current (or only) address */ + REG(I2C_CNT) = 1; + REG(I2C_SA) = chip; + REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP); + udelay (50000); + + if (!(REG(I2C_STAT) & I2C_STAT_NACK)) { + rc = 0; + flush_rx(); + REG(I2C_STAT) = 0xffff; + } else { + REG(I2C_STAT) = 0xffff; + REG(I2C_CON) |= I2C_CON_STP; + udelay(20000); + if (wait_for_bus()) {return(1);} + } + + flush_rx(); + REG(I2C_STAT) = 0xffff; + REG(I2C_CNT) = 0; + return(rc); +} + + +int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +{ + u_int32_t tmp; + int i; + + if ((alen < 0) || (alen > 2)) { + printf("%s(): bogus address length %x\n", __FUNCTION__, alen); + return(1); + } + + if (wait_for_bus()) {return(1);} + + if (alen != 0) { + /* Start address phase */ + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; + REG(I2C_CNT) = alen; + REG(I2C_SA) = chip; + REG(I2C_CON) = tmp; + + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + switch (alen) { + case 2: + /* Send address MSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = (addr >> 8) & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + /* No break, fall through */ + case 1: + /* Send address LSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = addr & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_ARDY)) { + REG(I2C_CON) = 0; + return(1); + } + } + } + + /* Address phase is over, now read 'len' bytes and stop */ + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; + REG(I2C_CNT) = len & 0xffff; + REG(I2C_SA) = chip; + REG(I2C_CON) = tmp; + + for (i = 0; i < len; i++) { + tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR); + + CHECK_NACK(); + + if (tmp & I2C_STAT_RRDY) { + buf[i] = REG(I2C_DRR); + } else { + REG(I2C_CON) = 0; + return(1); + } + } + + tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_SCD)) { + REG(I2C_CON) = 0; + return(1); + } + + flush_rx(); + REG(I2C_STAT) = 0xffff; + REG(I2C_CNT) = 0; + REG(I2C_CON) = 0; + + return(0); +} + + +int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +{ + u_int32_t tmp; + int i; + + if ((alen < 0) || (alen > 2)) { + printf("%s(): bogus address length %x\n", __FUNCTION__, alen); + return(1); + } + if (len < 0) { + printf("%s(): bogus length %x\n", __FUNCTION__, len); + return(1); + } + + if (wait_for_bus()) {return(1);} + + /* Start address phase */ + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP; + REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen; + REG(I2C_SA) = chip; + REG(I2C_CON) = tmp; + + switch (alen) { + case 2: + /* Send address MSByte */ + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = (addr >> 8) & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + /* No break, fall through */ + case 1: + /* Send address LSByte */ + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = addr & 0xff; + } else { + REG(I2C_CON) = 0; + return(1); + } + } + + for (i = 0; i < len; i++) { + tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + + if (tmp & I2C_STAT_XRDY) { + REG(I2C_DXR) = buf[i]; + } else { + return(1); + } + } + + tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_SCD)) { + REG(I2C_CON) = 0; + return(1); + } + + flush_rx(); + REG(I2C_STAT) = 0xffff; + REG(I2C_CNT) = 0; + REG(I2C_CON) = 0; + + return(0); +} + + +u_int8_t i2c_reg_read(u_int8_t chip, u_int8_t reg) +{ + u_int8_t tmp; + + i2c_read(chip, reg, 1, &tmp, 1); + return(tmp); +} + + +void i2c_reg_write(u_int8_t chip, u_int8_t reg, u_int8_t val) +{ + u_int8_t tmp; + + i2c_write(chip, reg, 1, &tmp, 1); +} + +#endif /* CONFIG_DRIVER_DAVINCI_I2C */ diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/cpu/arm926ejs/davinci/lowlevel_init.S new file mode 100644 index 00000000000..bbc48ec4725 --- /dev/null +++ b/cpu/arm926ejs/davinci/lowlevel_init.S @@ -0,0 +1,707 @@ +/* + * Low-level board setup code for TI DaVinci SoC based boards. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * Partially based on TI sources, original copyrights follow: + */ + +/* + * Board specific setup info + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 + * + * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 + * See file CREDITS for list of people who contributed to this + * project. + * + * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005 + * See file CREDITS for list of people who contributed to this + * project. + * + * Modified for DV-EVM board by Swaminathan S, Nov 2005 + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl lowlevel_init +lowlevel_init: + + /*-------------------------------------------------------* + * Mask all IRQs by setting all bits in the EINT default * + *-------------------------------------------------------*/ + mov r1, $0 + ldr r0, =EINT_ENABLE0 + str r1, [r0] + ldr r0, =EINT_ENABLE1 + str r1, [r0] + + /*------------------------------------------------------* + * Put the GEM in reset * + *------------------------------------------------------*/ + + /* Put the GEM in reset */ + ldr r8, PSC_GEM_FLAG_CLEAR + ldr r6, MDCTL_GEM + ldr r7, [r6] + and r7, r7, r8 + str r7, [r6] + + /* Enable the Power Domain Transition Command */ + ldr r6, PTCMD + ldr r7, [r6] + orr r7, r7, $0x02 + str r7, [r6] + + /* Check for Transition Complete(PTSTAT) */ +checkStatClkStopGem: + ldr r6, PTSTAT + ldr r7, [r6] + ands r7, r7, $0x02 + bne checkStatClkStopGem + + /* Check for GEM Reset Completion */ +checkGemStatClkStop: + ldr r6, MDSTAT_GEM + ldr r7, [r6] + ands r7, r7, $0x100 + bne checkGemStatClkStop + + /* Do this for enabling a WDT initiated reset this is a workaround + for a chip bug. Not required under normal situations */ + ldr r6, P1394 + mov r10, $0 + str r10, [r6] + + /*------------------------------------------------------* + * Enable L1 & L2 Memories in Fast mode * + *------------------------------------------------------*/ + ldr r6, DFT_ENABLE + mov r10, $0x01 + str r10, [r6] + + ldr r6, MMARG_BRF0 + ldr r10, MMARG_BRF0_VAL + str r10, [r6] + + ldr r6, DFT_ENABLE + mov r10, $0 + str r10, [r6] + + /*------------------------------------------------------* + * DDR2 PLL Initialization * + *------------------------------------------------------*/ + + /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ + mov r10, $0 + ldr r6, PLL2_CTL + ldr r7, PLL_CLKSRC_MASK + ldr r8, [r6] + and r8, r8, r7 + mov r9, r10, lsl $8 + orr r8, r8, r9 + str r8, [r6] + + /* Select the PLLEN source */ + ldr r7, PLL_ENSRC_MASK + and r8, r8, r7 + str r8, [r6] + + /* Bypass the PLL */ + ldr r7, PLL_BYPASS_MASK + and r8, r8, r7 + str r8, [r6] + + /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */ + mov r10, $0x20 +WaitPPL2Loop: + subs r10, r10, $1 + bne WaitPPL2Loop + + /* Reset the PLL */ + ldr r7, PLL_RESET_MASK + and r8, r8, r7 + str r8, [r6] + + /* Power up the PLL */ + ldr r7, PLL_PWRUP_MASK + and r8, r8, r7 + str r8, [r6] + + /* Enable the PLL from Disable Mode */ + ldr r7, PLL_DISABLE_ENABLE_MASK + and r8, r8, r7 + str r8, [r6] + + /* Program the PLL Multiplier */ + ldr r6, PLL2_PLLM + mov r2, $0x17 /* 162 MHz */ + str r2, [r6] + + /* Program the PLL2 Divisor Value */ + ldr r6, PLL2_DIV2 + mov r3, $0x01 + str r3, [r6] + + /* Program the PLL2 Divisor Value */ + ldr r6, PLL2_DIV1 + mov r4, $0x0b /* 54 MHz */ + str r4, [r6] + + /* PLL2 DIV2 MMR */ + ldr r8, PLL2_DIV_MASK + ldr r6, PLL2_DIV2 + ldr r9, [r6] + and r8, r8, r9 + mov r9, $0x01 + mov r9, r9, lsl $15 + orr r8, r8, r9 + str r8, [r6] + + /* Program the GOSET bit to take new divider values */ + ldr r6, PLL2_PLLCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Wait for Done */ + ldr r6, PLL2_PLLSTAT +doneLoop_0: + ldr r7, [r6] + ands r7, r7, $0x01 + bne doneLoop_0 + + /* PLL2 DIV1 MMR */ + ldr r8, PLL2_DIV_MASK + ldr r6, PLL2_DIV1 + ldr r9, [r6] + and r8, r8, r9 + mov r9, $0x01 + mov r9, r9, lsl $15 + orr r8, r8, r9 + str r8, [r6] + + /* Program the GOSET bit to take new divider values */ + ldr r6, PLL2_PLLCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Wait for Done */ + ldr r6, PLL2_PLLSTAT +doneLoop: + ldr r7, [r6] + ands r7, r7, $0x01 + bne doneLoop + + /* Wait for PLL to Reset Properly */ + mov r10, $0x218 +ResetPPL2Loop: + subs r10, r10, $1 + bne ResetPPL2Loop + + /* Bring PLL out of Reset */ + ldr r6, PLL2_CTL + ldr r8, [r6] + orr r8, r8, $0x08 + str r8, [r6] + + /* Wait for PLL to Lock */ + ldr r10, PLL_LOCK_COUNT +PLL2Lock: + subs r10, r10, $1 + bne PLL2Lock + + /* Enable the PLL */ + ldr r6, PLL2_CTL + ldr r8, [r6] + orr r8, r8, $0x01 + str r8, [r6] + + /*------------------------------------------------------* + * Issue Soft Reset to DDR Module * + *------------------------------------------------------*/ + + /* Shut down the DDR2 LPSC Module */ + ldr r8, PSC_FLAG_CLEAR + ldr r6, MDCTL_DDR2 + ldr r7, [r6] + and r7, r7, r8 + orr r7, r7, $0x03 + str r7, [r6] + + /* Enable the Power Domain Transition Command */ + ldr r6, PTCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Check for Transition Complete(PTSTAT) */ +checkStatClkStop: + ldr r6, PTSTAT + ldr r7, [r6] + ands r7, r7, $0x01 + bne checkStatClkStop + + /* Check for DDR2 Controller Enable Completion */ +checkDDRStatClkStop: + ldr r6, MDSTAT_DDR2 + ldr r7, [r6] + and r7, r7, $0x1f + cmp r7, $0x03 + bne checkDDRStatClkStop + + /*------------------------------------------------------* + * Program DDR2 MMRs for 162MHz Setting * + *------------------------------------------------------*/ + + /* Program PHY Control Register */ + ldr r6, DDRCTL + ldr r7, DDRCTL_VAL + str r7, [r6] + + /* Program SDRAM Bank Config Register */ + ldr r6, SDCFG + ldr r7, SDCFG_VAL + str r7, [r6] + + /* Program SDRAM TIM-0 Config Register */ + ldr r6, SDTIM0 + ldr r7, SDTIM0_VAL_162MHz + str r7, [r6] + + /* Program SDRAM TIM-1 Config Register */ + ldr r6, SDTIM1 + ldr r7, SDTIM1_VAL_162MHz + str r7, [r6] + + /* Program the SDRAM Bank Config Control Register */ + ldr r10, MASK_VAL + ldr r8, SDCFG + ldr r9, SDCFG_VAL + and r9, r9, r10 + str r9, [r8] + + /* Program SDRAM SDREF Config Register */ + ldr r6, SDREF + ldr r7, SDREF_VAL + str r7, [r6] + + /*------------------------------------------------------* + * Issue Soft Reset to DDR Module * + *------------------------------------------------------*/ + + /* Issue a Dummy DDR2 read/write */ + ldr r8, DDR2_START_ADDR + ldr r7, DUMMY_VAL + str r7, [r8] + ldr r7, [r8] + + /* Shut down the DDR2 LPSC Module */ + ldr r8, PSC_FLAG_CLEAR + ldr r6, MDCTL_DDR2 + ldr r7, [r6] + and r7, r7, r8 + orr r7, r7, $0x01 + str r7, [r6] + + /* Enable the Power Domain Transition Command */ + ldr r6, PTCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Check for Transition Complete(PTSTAT) */ +checkStatClkStop2: + ldr r6, PTSTAT + ldr r7, [r6] + ands r7, r7, $0x01 + bne checkStatClkStop2 + + /* Check for DDR2 Controller Enable Completion */ +checkDDRStatClkStop2: + ldr r6, MDSTAT_DDR2 + ldr r7, [r6] + and r7, r7, $0x1f + cmp r7, $0x01 + bne checkDDRStatClkStop2 + + /*------------------------------------------------------* + * Turn DDR2 Controller Clocks On * + *------------------------------------------------------*/ + + /* Enable the DDR2 LPSC Module */ + ldr r6, MDCTL_DDR2 + ldr r7, [r6] + orr r7, r7, $0x03 + str r7, [r6] + + /* Enable the Power Domain Transition Command */ + ldr r6, PTCMD + ldr r7, [r6] + orr r7, r7, $0x01 + str r7, [r6] + + /* Check for Transition Complete(PTSTAT) */ +checkStatClkEn2: + ldr r6, PTSTAT + ldr r7, [r6] + ands r7, r7, $0x01 + bne checkStatClkEn2 + + /* Check for DDR2 Controller Enable Completion */ +checkDDRStatClkEn2: + ldr r6, MDSTAT_DDR2 + ldr r7, [r6] + and r7, r7, $0x1f + cmp r7, $0x03 + bne checkDDRStatClkEn2 + + /* DDR Writes and Reads */ + ldr r6, CFGTEST + mov r3, $0x01 + str r3, [r6] + + /*------------------------------------------------------* + * System PLL Initialization * + *------------------------------------------------------*/ + + /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */ + mov r2, $0 + ldr r6, PLL1_CTL + ldr r7, PLL_CLKSRC_MASK + ldr r8, [r6] + and r8, r8, r7 + mov r9, r2, lsl $8 + orr r8, r8, r9 + str r8, [r6] + + /* Select the PLLEN source */ + ldr r7, PLL_ENSRC_MASK + and r8, r8, r7 + str r8, [r6] + + /* Bypass the PLL */ + ldr r7, PLL_BYPASS_MASK + and r8, r8, r7 + str r8, [r6] + + /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */ + mov r10, $0x20 + +WaitLoop: + subs r10, r10, $1 + bne WaitLoop + + /* Reset the PLL */ + ldr r7, PLL_RESET_MASK + and r8, r8, r7 + str r8, [r6] + + /* Disable the PLL */ + orr r8, r8, $0x10 + str r8, [r6] + + /* Power up the PLL */ + ldr r7, PLL_PWRUP_MASK + and r8, r8, r7 + str r8, [r6] + + /* Enable the PLL from Disable Mode */ + ldr r7, PLL_DISABLE_ENABLE_MASK + and r8, r8, r7 + str r8, [r6] + + /* Program the PLL Multiplier */ + ldr r6, PLL1_PLLM + mov r3, $0x15 /* For 594MHz */ + str r3, [r6] + + /* Wait for PLL to Reset Properly */ + mov r10, $0xff + +ResetLoop: + subs r10, r10, $1 + bne ResetLoop + + /* Bring PLL out of Reset */ + ldr r6, PLL1_CTL + orr r8, r8, $0x08 + str r8, [r6] + + /* Wait for PLL to Lock */ + ldr r10, PLL_LOCK_COUNT + +PLL1Lock: + subs r10, r10, $1 + bne PLL1Lock + + /* Enable the PLL */ + orr r8, r8, $0x01 + str r8, [r6] + + nop + nop + nop + nop + + /*------------------------------------------------------* + * AEMIF configuration for NOR Flash (double check) * + *------------------------------------------------------*/ + ldr r0, _PINMUX0 + ldr r1, _DEV_SETTING + str r1, [r0] + + ldr r0, WAITCFG + ldr r1, WAITCFG_VAL + ldr r2, [r0] + orr r2, r2, r1 + str r2, [r0] + + ldr r0, ACFG3 + ldr r1, ACFG3_VAL + ldr r2, [r0] + and r1, r2, r1 + str r1, [r0] + + ldr r0, ACFG4 + ldr r1, ACFG4_VAL + ldr r2, [r0] + and r1, r2, r1 + str r1, [r0] + + ldr r0, ACFG5 + ldr r1, ACFG5_VAL + ldr r2, [r0] + and r1, r2, r1 + str r1, [r0] + + /*--------------------------------------* + * VTP manual Calibration * + *--------------------------------------*/ + ldr r0, VTPIOCR + ldr r1, VTP_MMR0 + str r1, [r0] + + ldr r0, VTPIOCR + ldr r1, VTP_MMR1 + str r1, [r0] + + /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */ + ldr r10, VTP_LOCK_COUNT +VTPLock: + subs r10, r10, $1 + bne VTPLock + + ldr r6, DFT_ENABLE + mov r10, $0x01 + str r10, [r6] + + ldr r6, DDRVTPR + ldr r7, [r6] + and r7, r7, $0x1f + and r8, r7, $0x3e0 + orr r8, r7, r8 + ldr r7, VTP_RECAL + orr r8, r7, r8 + ldr r7, VTP_EN + orr r8, r7, r8 + str r8, [r0] + + + /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */ + ldr r10, VTP_LOCK_COUNT +VTP1Lock: + subs r10, r10, $1 + bne VTP1Lock + + ldr r1, [r0] + ldr r2, VTP_MASK + and r2, r1, r2 + str r2, [r0] + + ldr r6, DFT_ENABLE + mov r10, $0 + str r10, [r6] + + /* + * Call board-specific lowlevel init. + * That MUST be present and THAT returns + * back to arch calling code with "mov pc, lr." + */ + b dv_board_init + +.ltorg + +_PINMUX0: + .word 0x01c40000 /* Device Configuration Registers */ +_PINMUX1: + .word 0x01c40004 /* Device Configuration Registers */ + +_DEV_SETTING: + .word 0x00000c1f + +WAITCFG: + .word 0x01e00004 +WAITCFG_VAL: + .word 0 +ACFG3: + .word 0x01e00014 +ACFG3_VAL: + .word 0x3ffffffd +ACFG4: + .word 0x01e00018 +ACFG4_VAL: + .word 0x3ffffffd +ACFG5: + .word 0x01e0001c +ACFG5_VAL: + .word 0x3ffffffd + +MDCTL_DDR2: + .word 0x01c41a34 +MDSTAT_DDR2: + .word 0x01c41834 + +PTCMD: + .word 0x01c41120 +PTSTAT: + .word 0x01c41128 + +EINT_ENABLE0: + .word 0x01c48018 +EINT_ENABLE1: + .word 0x01c4801c + +PSC_FLAG_CLEAR: + .word 0xffffffe0 +PSC_GEM_FLAG_CLEAR: + .word 0xfffffeff + +/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */ +DDRCTL: + .word 0x200000e4 +DDRCTL_VAL: + .word 0x50006405 +SDREF: + .word 0x2000000c +SDREF_VAL: + .word 0x000005c3 +SDCFG: + .word 0x20000008 +SDCFG_VAL: +#ifdef DDR_4BANKS + .word 0x00178622 +#elif defined DDR_8BANKS + .word 0x00178632 +#else +#error "Unknown DDR configuration!!!" +#endif +SDTIM0: + .word 0x20000010 +SDTIM0_VAL_162MHz: + .word 0x28923211 +SDTIM1: + .word 0x20000014 +SDTIM1_VAL_162MHz: + .word 0x0016c722 +VTPIOCR: + .word 0x200000f0 /* VTP IO Control register */ +DDRVTPR: + .word 0x01c42030 /* DDR VPTR MMR */ +VTP_MMR0: + .word 0x201f +VTP_MMR1: + .word 0xa01f +DFT_ENABLE: + .word 0x01c4004c +VTP_LOCK_COUNT: + .word 0x5b0 +VTP_MASK: + .word 0xffffdfff +VTP_RECAL: + .word 0x40000 +VTP_EN: + .word 0x02000 +CFGTEST: + .word 0x80010000 +MASK_VAL: + .word 0x00000fff + +/* GEM Power Up & LPSC Control Register */ +MDCTL_GEM: + .word 0x01c41a9c +MDSTAT_GEM: + .word 0x01c4189c + +/* For WDT reset chip bug */ +P1394: + .word 0x01c41a20 + +PLL_CLKSRC_MASK: + .word 0xfffffeff /* Mask the Clock Mode bit */ +PLL_ENSRC_MASK: + .word 0xffffffdf /* Select the PLLEN source */ +PLL_BYPASS_MASK: + .word 0xfffffffe /* Put the PLL in BYPASS */ +PLL_RESET_MASK: + .word 0xfffffff7 /* Put the PLL in Reset Mode */ +PLL_PWRUP_MASK: + .word 0xfffffffd /* PLL Power up Mask Bit */ +PLL_DISABLE_ENABLE_MASK: + .word 0xffffffef /* Enable the PLL from Disable */ +PLL_LOCK_COUNT: + .word 0x2000 + +/* PLL1-SYSTEM PLL MMRs */ +PLL1_CTL: + .word 0x01c40900 +PLL1_PLLM: + .word 0x01c40910 + +/* PLL2-SYSTEM PLL MMRs */ +PLL2_CTL: + .word 0x01c40d00 +PLL2_PLLM: + .word 0x01c40d10 +PLL2_DIV1: + .word 0x01c40d18 +PLL2_DIV2: + .word 0x01c40d1c +PLL2_PLLCMD: + .word 0x01c40d38 +PLL2_PLLSTAT: + .word 0x01c40d3c +PLL2_DIV_MASK: + .word 0xffff7fff + +MMARG_BRF0: + .word 0x01c42010 /* BRF margin mode 0 (R/W)*/ +MMARG_BRF0_VAL: + .word 0x00444400 + +DDR2_START_ADDR: + .word 0x80000000 +DUMMY_VAL: + .word 0xa55aa55a diff --git a/cpu/arm926ejs/davinci/lxt972.c b/cpu/arm926ejs/davinci/lxt972.c new file mode 100644 index 00000000000..6eeb6e5ee92 --- /dev/null +++ b/cpu/arm926ejs/davinci/lxt972.c @@ -0,0 +1,142 @@ +/* + * Intel LXT971/LXT972 PHY Driver for TI DaVinci + * (TMS320DM644x) based boards. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * -------------------------------------------------------- + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CONFIG_DRIVER_TI_EMAC + +#ifdef CONFIG_CMD_NET + +int lxt972_is_phy_connected(int phy_addr) +{ + u_int16_t id1, id2; + + if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID1, &id1)) + return(0); + if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID2, &id2)) + return(0); + + if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0)) + return(1); + + return(0); +} + +int lxt972_get_link_speed(int phy_addr) +{ + u_int16_t stat1, tmp; + volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; + + if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1)) + return(0); + + if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */ + return(0); + + if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) + return(0); + + tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE; + + dm644x_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp); + /* Read back */ + if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) + return(0); + + + /* Speed doesn't matter, there is no setting for it in EMAC... */ + if (stat1 & PHY_LXT971_STAT2_100BTX) { + if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } else { + if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; + } else { + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; + } + + return(1); + } + + return(0); +} + + +int lxt972_init_phy(int phy_addr) +{ + int ret = 1; + + if (!lxt972_get_link_speed(phy_addr)) { + /* Try another time */ + ret = lxt972_get_link_speed(phy_addr); + } + + /* Disable PHY Interrupts */ + dm644x_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0); + + return(ret); +} + + +int lxt972_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + + + if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_CTRL, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp |= PHY_COMMON_CTRL_RES_AUTO; + dm644x_eth_phy_write(phy_addr, PHY_COMMON_CTRL, tmp); + + /*check AutoNegotiate complete */ + udelay (10000); + if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_STAT, &tmp)) + return(0); + + if (!(tmp & PHY_COMMON_STAT_AN_COMP)) + return(0); + + return (lxt972_get_link_speed(phy_addr)); +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c new file mode 100644 index 00000000000..127be9fcd43 --- /dev/null +++ b/cpu/arm926ejs/davinci/nand.c @@ -0,0 +1,389 @@ +/* + * NAND driver for TI DaVinci based boards. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * Based on Linux DaVinci NAND driver by TI. Original copyright follows: + */ + +/* + * + * linux/drivers/mtd/nand/nand_davinci.c + * + * NAND Flash Driver + * + * Copyright (C) 2006 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + * + * Overview: + * This is a device driver for the NAND flash device found on the + * DaVinci board which utilizes the Samsung k9k2g08 part. + * + Modifications: + ver. 1.0: Feb 2005, Vinod/Sudhakar + - + * + */ + +#include + +#ifdef CFG_USE_NAND +#if !defined(CFG_NAND_LEGACY) + +#include +#include +#include + +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; + + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + + switch (cmd) { + case NAND_CTL_SETCLE: + IO_ADDR_W |= MASK_CLE; + break; + case NAND_CTL_SETALE: + IO_ADDR_W |= MASK_ALE; + break; + } + + this->IO_ADDR_W = (void *)IO_ADDR_W; +} + +/* Set WP on deselect, write enable on select */ +static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) +{ +#define GPIO_SET_DATA01 0x01c67018 +#define GPIO_CLR_DATA01 0x01c6701c +#define GPIO_NAND_WP (1 << 4) +#ifdef SONATA_BOARD_GPIOWP + if (chip < 0) { + REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP; + } else { + REG(GPIO_SET_DATA01) |= GPIO_NAND_WP; + } +#endif +} + +#ifdef CFG_NAND_HW_ECC +#ifdef CFG_NAND_LARGEPAGE +static struct nand_oobinfo davinci_nand_oobinfo = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 12, + .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, + .oobfree = { {2, 6}, {12, 12}, {28, 12}, {44, 12}, {60, 4} } +}; +#elif defined(CFG_NAND_SMALLPAGE) +static struct nand_oobinfo davinci_nand_oobinfo = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 3, + .eccpos = {0, 1, 2}, + .oobfree = { {6, 2}, {8, 8} } +}; +#else +#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!" +#endif + +static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) +{ + emifregs emif_addr; + int dummy; + + emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + dummy = emif_addr->NANDF1ECC; + dummy = emif_addr->NANDF2ECC; + dummy = emif_addr->NANDF3ECC; + dummy = emif_addr->NANDF4ECC; + + emif_addr->NANDFCR |= (1 << 8); +} + +static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) +{ + u_int32_t ecc = 0; + emifregs emif_base_addr; + + emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + if (region == 1) + ecc = emif_base_addr->NANDF1ECC; + else if (region == 2) + ecc = emif_base_addr->NANDF2ECC; + else if (region == 3) + ecc = emif_base_addr->NANDF3ECC; + else if (region == 4) + ecc = emif_base_addr->NANDF4ECC; + + return(ecc); +} + +static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +{ + u_int32_t tmp; + int region, n; + struct nand_chip *this = mtd->priv; + + n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1; + + region = 1; + while (n--) { + tmp = nand_davinci_readecc(mtd, region); + *ecc_code++ = tmp; + *ecc_code++ = tmp >> 16; + *ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0); + region++; + } + return(0); +} + +static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf) +{ + u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8); + + ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); + ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); + ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); +} + +static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data) +{ + u_int32_t i; + u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; + u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8]; + u_int8_t ecc_bit[24]; + u_int8_t ecc_sum = 0; + u_int8_t find_bit = 0; + u_int32_t find_byte = 0; + int is_ecc_ff; + + is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff)); + + nand_davinci_gen_true_ecc(ecc_nand); + nand_davinci_gen_true_ecc(ecc_calc); + + for (i = 0; i <= 2; i++) { + *(ecc_nand + i) = ~(*(ecc_nand + i)); + *(ecc_calc + i) = ~(*(ecc_calc + i)); + } + + for (i = 0; i < 8; i++) { + tmp0_bit[i] = *ecc_nand % 2; + *ecc_nand = *ecc_nand / 2; + } + + for (i = 0; i < 8; i++) { + tmp1_bit[i] = *(ecc_nand + 1) % 2; + *(ecc_nand + 1) = *(ecc_nand + 1) / 2; + } + + for (i = 0; i < 8; i++) { + tmp2_bit[i] = *(ecc_nand + 2) % 2; + *(ecc_nand + 2) = *(ecc_nand + 2) / 2; + } + + for (i = 0; i < 8; i++) { + comp0_bit[i] = *ecc_calc % 2; + *ecc_calc = *ecc_calc / 2; + } + + for (i = 0; i < 8; i++) { + comp1_bit[i] = *(ecc_calc + 1) % 2; + *(ecc_calc + 1) = *(ecc_calc + 1) / 2; + } + + for (i = 0; i < 8; i++) { + comp2_bit[i] = *(ecc_calc + 2) % 2; + *(ecc_calc + 2) = *(ecc_calc + 2) / 2; + } + + for (i = 0; i< 6; i++) + ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; + + for (i = 0; i < 8; i++) + ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; + + for (i = 0; i < 8; i++) + ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; + + ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; + ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; + + for (i = 0; i < 24; i++) + ecc_sum += ecc_bit[i]; + + switch (ecc_sum) { + case 0: + /* Not reached because this function is not called if + ECC values are equal */ + return 0; + case 1: + /* Uncorrectable error */ + DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); + return(-1); + case 12: + /* Correctable error */ + find_byte = (ecc_bit[23] << 8) + + (ecc_bit[21] << 7) + + (ecc_bit[19] << 6) + + (ecc_bit[17] << 5) + + (ecc_bit[15] << 4) + + (ecc_bit[13] << 3) + + (ecc_bit[11] << 2) + + (ecc_bit[9] << 1) + + ecc_bit[7]; + + find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; + + DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit); + + page_data[find_byte] ^= (1 << find_bit); + + return(0); + default: + if (is_ecc_ff) { + if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0) + return(0); + } + DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n"); + return(-1); + } +} + +static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + struct nand_chip *this; + int block_count = 0, i, rc; + + this = mtd->priv; + block_count = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1; + for (i = 0; i < block_count; i++) { + if (memcmp(read_ecc, calc_ecc, 3) != 0) { + rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat); + if (rc < 0) { + return(rc); + } + } + read_ecc += 3; + calc_ecc += 3; + dat += 512; + } + return(0); +} +#endif + +static int nand_davinci_dev_ready(struct mtd_info *mtd) +{ + emifregs emif_addr; + + emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + return(emif_addr->NANDFSR & 0x1); +} + +static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + while(!nand_davinci_dev_ready(mtd)) {;} + *NAND_CE0CLE = NAND_STATUS; + return(*NAND_CE0DATA); +} + +static void nand_flash_init(void) +{ + u_int32_t acfg1 = 0x3ffffffc; + u_int32_t acfg2 = 0x3ffffffc; + u_int32_t acfg3 = 0x3ffffffc; + u_int32_t acfg4 = 0x3ffffffc; + emifregs emif_regs; + + /*------------------------------------------------------------------* + * NAND FLASH CHIP TIMEOUT @ 459 MHz * + * * + * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz * + * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * + * * + *------------------------------------------------------------------*/ + acfg1 = 0 + | (0 << 31 ) /* selectStrobe */ + | (0 << 30 ) /* extWait */ + | (1 << 26 ) /* writeSetup 10 ns */ + | (3 << 20 ) /* writeStrobe 40 ns */ + | (1 << 17 ) /* writeHold 10 ns */ + | (1 << 13 ) /* readSetup 10 ns */ + | (5 << 7 ) /* readStrobe 60 ns */ + | (1 << 4 ) /* readHold 10 ns */ + | (3 << 2 ) /* turnAround ?? ns */ + | (0 << 0 ) /* asyncSize 8-bit bus */ + ; + + emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + emif_regs->AWCCR |= 0x10000000; + emif_regs->AB1CR = acfg1; /* 0x08244128 */; + emif_regs->AB2CR = acfg2; + emif_regs->AB3CR = acfg3; + emif_regs->AB4CR = acfg4; + emif_regs->NANDFCR = 0x00000101; +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA; + nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA; + nand->chip_delay = 0; + nand->select_chip = nand_davinci_select_chip; +#ifdef CFG_NAND_USE_FLASH_BBT + nand->options = NAND_USE_FLASH_BBT; +#endif +#ifdef CFG_NAND_HW_ECC +#ifdef CFG_NAND_LARGEPAGE + nand->eccmode = NAND_ECC_HW12_2048; +#elif defined(CFG_NAND_SMALLPAGE) + nand->eccmode = NAND_ECC_HW3_512; +#else +#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!" +#endif + nand->autooob = &davinci_nand_oobinfo; + nand->calculate_ecc = nand_davinci_calculate_ecc; + nand->correct_data = nand_davinci_correct_data; + nand->enable_hwecc = nand_davinci_enable_hwecc; +#else + nand->eccmode = NAND_ECC_SOFT; +#endif + + /* Set address of hardware control function */ + nand->hwcontrol = nand_davinci_hwcontrol; + + nand->dev_ready = nand_davinci_dev_ready; + nand->waitfunc = nand_davinci_waitfunc; + + nand_flash_init(); + + return(0); +} + +#else +#error "U-Boot legacy NAND support not available for DaVinci chips" +#endif +#endif /* CFG_USE_NAND */ diff --git a/cpu/arm926ejs/davinci/reset.S b/cpu/arm926ejs/davinci/reset.S new file mode 100644 index 00000000000..a687d44035c --- /dev/null +++ b/cpu/arm926ejs/davinci/reset.S @@ -0,0 +1,77 @@ +/* + * Processor reset using WDT for TI TMS320DM644x SoC. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * ----------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.globl reset_cpu +reset_cpu: + ldr r0, WDT_TGCR + mov r1, $0x08 + str r1, [r0] + ldr r1, [r0] + orr r1, r1, $0x03 + str r1, [r0] + mov r1, $0 + ldr r0, WDT_TIM12 + str r1, [r0] + ldr r0, WDT_TIM34 + str r1, [r0] + ldr r0, WDT_PRD12 + str r1, [r0] + ldr r0, WDT_PRD34 + str r1, [r0] + ldr r0, WDT_TCR + ldr r1, [r0] + orr r1, r1, $0x40 + str r1, [r0] + ldr r0, WDT_WDTCR + ldr r1, [r0] + orr r1, r1, $0x4000 + str r1, [r0] + ldr r1, WDTCR_VAL1 + str r1, [r0] + ldr r1, WDTCR_VAL2 + str r1, [r0] + nop + nop + nop + nop +reset_cpu_loop: + b reset_cpu_loop + +WDT_TGCR: + .word 0x01c21c24 +WDT_TIM12: + .word 0x01c21c10 +WDT_TIM34: + .word 0x01c21c14 +WDT_PRD12: + .word 0x01c21c18 +WDT_PRD34: + .word 0x01c21c1c +WDT_TCR: + .word 0x01c21c20 +WDT_WDTCR: + .word 0x01c21c28 +WDTCR_VAL1: + .word 0xa5c64000 +WDTCR_VAL2: + .word 0xda7e4000 diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c new file mode 100644 index 00000000000..c6b1dda51fc --- /dev/null +++ b/cpu/arm926ejs/davinci/timer.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2003 + * Texas Instruments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +typedef volatile struct { + u_int32_t pid12; + u_int32_t emumgt_clksped; + u_int32_t gpint_en; + u_int32_t gpdir_dat; + u_int32_t tim12; + u_int32_t tim34; + u_int32_t prd12; + u_int32_t prd34; + u_int32_t tcr; + u_int32_t tgcr; + u_int32_t wdtcr; + u_int32_t tlgc; + u_int32_t tlmr; +} davinci_timer; + +davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE; + +#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ) +#define READ_TIMER timer->tim34 + +static ulong timestamp; +static ulong lastinc; + +int timer_init(void) +{ + /* We are using timer34 in unchained 32-bit mode, full speed */ + timer->tcr = 0x0; + timer->tgcr = 0x0; + timer->tgcr = 0x06; + timer->tim34 = 0x0; + timer->prd34 = TIMER_LOAD_VAL; + lastinc = 0; + timer->tcr = 0x80 << 16; + timestamp = 0; + + return(0); +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return(get_timer_masked() - base); +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void udelay(unsigned long usec) +{ + udelay_masked(usec); +} + +void reset_timer_masked(void) +{ + lastinc = READ_TIMER; + timestamp = 0; +} + +ulong get_timer_raw(void) +{ + ulong now = READ_TIMER; + + if (now >= lastinc) { + /* normal mode */ + timestamp += now - lastinc; + } else { + /* overflow ... */ + timestamp += now + TIMER_LOAD_VAL - lastinc; + } + lastinc = now; + return timestamp; +} + +ulong get_timer_masked(void) +{ + return(get_timer_raw() / TIMER_LOAD_VAL); +} + +void udelay_masked(unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + tmo = CFG_HZ_CLOCK / 1000; + tmo *= usec; + tmo /= 1000; + + endtime = get_timer_raw() + tmo; + + do { + ulong now = get_timer_raw(); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return(get_timer(0)); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CFG_HZ; + return(tbclk); +} diff --git a/include/_exports.h b/include/_exports.h index da6e088163e..af43885c527 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -14,6 +14,9 @@ EXPORT_FUNC(vprintf) EXPORT_FUNC(do_reset) EXPORT_FUNC(getenv) EXPORT_FUNC(setenv) +#ifdef CONFIG_HAS_UID +EXPORT_FUNC(forceenv) +#endif EXPORT_FUNC(simple_strtoul) EXPORT_FUNC(simple_strtol) EXPORT_FUNC(strcmp) diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/include/asm-arm/arch-davinci/emac_defs.h new file mode 100644 index 00000000000..0e10116d870 --- /dev/null +++ b/include/asm-arm/arch-davinci/emac_defs.h @@ -0,0 +1,311 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Based on: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.h + * + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + + * Modifications: + * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. + * + */ + +#ifndef _DM644X_EMAC_H_ +#define _DM644X_EMAC_H_ + +#include + +#define EMAC_BASE_ADDR (0x01c80000) +#define EMAC_WRAPPER_BASE_ADDR (0x01c81000) +#define EMAC_WRAPPER_RAM_ADDR (0x01c82000) +#define EMAC_MDIO_BASE_ADDR (0x01c84000) + +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ + +/* Ethernet Min/Max packet size */ +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 +#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 +#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ + +/* Number of RX packet buffers + * NOTE: Only 1 buffer supported as of now + */ +#define EMAC_MAX_RX_BUFFERS 10 + + +/*********************************************** + ******** Internally used macros *************** + ***********************************************/ + +#define EMAC_CH_TX 1 +#define EMAC_CH_RX 0 + +/* Each descriptor occupies 4 words, lets start RX desc's at 0 and + * reserve space for 64 descriptors max + */ +#define EMAC_RX_DESC_BASE 0x0 +#define EMAC_TX_DESC_BASE 0x1000 + +/* EMAC Teardown value */ +#define EMAC_TEARDOWN_VALUE 0xfffffffc + +/* MII Status Register */ +#define MII_STATUS_REG 1 + +/* Number of statistics registers */ +#define EMAC_NUM_STATS 36 + + +/* EMAC Descriptor */ +typedef volatile struct _emac_desc +{ + u_int32_t next; /* Pointer to next descriptor in chain */ + u_int8_t *buffer; /* Pointer to data buffer */ + u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ + u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ +} emac_desc; + +/* CPPI bit positions */ +#define EMAC_CPPI_SOP_BIT (0x80000000) +#define EMAC_CPPI_EOP_BIT (0x40000000) +#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) +#define EMAC_CPPI_EOQ_BIT (0x10000000) +#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) +#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) + +#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) + +#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) + +#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) +#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) + + +#define MDIO_CONTROL_IDLE (0x80000000) +#define MDIO_CONTROL_ENABLE (0x40000000) +#define MDIO_CONTROL_FAULT_ENABLE (0x40000) +#define MDIO_CONTROL_FAULT (0x80000) +#define MDIO_USERACCESS0_GO (0x80000000) +#define MDIO_USERACCESS0_WRITE_READ (0x0) +#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) +#define MDIO_USERACCESS0_ACK (0x20000000) + +/* Ethernet MAC Registers Structure */ +typedef struct { + dv_reg TXIDVER; + dv_reg TXCONTROL; + dv_reg TXTEARDOWN; + u_int8_t RSVD0[4]; + dv_reg RXIDVER; + dv_reg RXCONTROL; + dv_reg RXTEARDOWN; + u_int8_t RSVD1[100]; + dv_reg TXINTSTATRAW; + dv_reg TXINTSTATMASKED; + dv_reg TXINTMASKSET; + dv_reg TXINTMASKCLEAR; + dv_reg MACINVECTOR; + u_int8_t RSVD2[12]; + dv_reg RXINTSTATRAW; + dv_reg RXINTSTATMASKED; + dv_reg RXINTMASKSET; + dv_reg RXINTMASKCLEAR; + dv_reg MACINTSTATRAW; + dv_reg MACINTSTATMASKED; + dv_reg MACINTMASKSET; + dv_reg MACINTMASKCLEAR; + u_int8_t RSVD3[64]; + dv_reg RXMBPENABLE; + dv_reg RXUNICASTSET; + dv_reg RXUNICASTCLEAR; + dv_reg RXMAXLEN; + dv_reg RXBUFFEROFFSET; + dv_reg RXFILTERLOWTHRESH; + u_int8_t RSVD4[8]; + dv_reg RX0FLOWTHRESH; + dv_reg RX1FLOWTHRESH; + dv_reg RX2FLOWTHRESH; + dv_reg RX3FLOWTHRESH; + dv_reg RX4FLOWTHRESH; + dv_reg RX5FLOWTHRESH; + dv_reg RX6FLOWTHRESH; + dv_reg RX7FLOWTHRESH; + dv_reg RX0FREEBUFFER; + dv_reg RX1FREEBUFFER; + dv_reg RX2FREEBUFFER; + dv_reg RX3FREEBUFFER; + dv_reg RX4FREEBUFFER; + dv_reg RX5FREEBUFFER; + dv_reg RX6FREEBUFFER; + dv_reg RX7FREEBUFFER; + dv_reg MACCONTROL; + dv_reg MACSTATUS; + dv_reg EMCONTROL; + dv_reg FIFOCONTROL; + dv_reg MACCONFIG; + dv_reg SOFTRESET; + u_int8_t RSVD5[88]; + dv_reg MACSRCADDRLO; + dv_reg MACSRCADDRHI; + dv_reg MACHASH1; + dv_reg MACHASH2; + dv_reg BOFFTEST; + dv_reg TPACETEST; + dv_reg RXPAUSE; + dv_reg TXPAUSE; + u_int8_t RSVD6[16]; + dv_reg RXGOODFRAMES; + dv_reg RXBCASTFRAMES; + dv_reg RXMCASTFRAMES; + dv_reg RXPAUSEFRAMES; + dv_reg RXCRCERRORS; + dv_reg RXALIGNCODEERRORS; + dv_reg RXOVERSIZED; + dv_reg RXJABBER; + dv_reg RXUNDERSIZED; + dv_reg RXFRAGMENTS; + dv_reg RXFILTERED; + dv_reg RXQOSFILTERED; + dv_reg RXOCTETS; + dv_reg TXGOODFRAMES; + dv_reg TXBCASTFRAMES; + dv_reg TXMCASTFRAMES; + dv_reg TXPAUSEFRAMES; + dv_reg TXDEFERRED; + dv_reg TXCOLLISION; + dv_reg TXSINGLECOLL; + dv_reg TXMULTICOLL; + dv_reg TXEXCESSIVECOLL; + dv_reg TXLATECOLL; + dv_reg TXUNDERRUN; + dv_reg TXCARRIERSENSE; + dv_reg TXOCTETS; + dv_reg FRAME64; + dv_reg FRAME65T127; + dv_reg FRAME128T255; + dv_reg FRAME256T511; + dv_reg FRAME512T1023; + dv_reg FRAME1024TUP; + dv_reg NETOCTETS; + dv_reg RXSOFOVERRUNS; + dv_reg RXMOFOVERRUNS; + dv_reg RXDMAOVERRUNS; + u_int8_t RSVD7[624]; + dv_reg MACADDRLO; + dv_reg MACADDRHI; + dv_reg MACINDEX; + u_int8_t RSVD8[244]; + dv_reg TX0HDP; + dv_reg TX1HDP; + dv_reg TX2HDP; + dv_reg TX3HDP; + dv_reg TX4HDP; + dv_reg TX5HDP; + dv_reg TX6HDP; + dv_reg TX7HDP; + dv_reg RX0HDP; + dv_reg RX1HDP; + dv_reg RX2HDP; + dv_reg RX3HDP; + dv_reg RX4HDP; + dv_reg RX5HDP; + dv_reg RX6HDP; + dv_reg RX7HDP; + dv_reg TX0CP; + dv_reg TX1CP; + dv_reg TX2CP; + dv_reg TX3CP; + dv_reg TX4CP; + dv_reg TX5CP; + dv_reg TX6CP; + dv_reg TX7CP; + dv_reg RX0CP; + dv_reg RX1CP; + dv_reg RX2CP; + dv_reg RX3CP; + dv_reg RX4CP; + dv_reg RX5CP; + dv_reg RX6CP; + dv_reg RX7CP; +} emac_regs; + +/* EMAC Wrapper Registers Structure */ +typedef struct { + u_int8_t RSVD0[4100]; + dv_reg EWCTL; + dv_reg EWINTTCNT; +} ewrap_regs; + + +/* EMAC MDIO Registers Structure */ +typedef struct { + dv_reg VERSION; + dv_reg CONTROL; + dv_reg ALIVE; + dv_reg LINK; + dv_reg LINKINTRAW; + dv_reg LINKINTMASKED; + u_int8_t RSVD0[8]; + dv_reg USERINTRAW; + dv_reg USERINTMASKED; + dv_reg USERINTMASKSET; + dv_reg USERINTMASKCLEAR; + u_int8_t RSVD1[80]; + dv_reg USERACCESS0; + dv_reg USERPHYSEL0; + dv_reg USERACCESS1; + dv_reg USERPHYSEL1; +} mdio_regs; + +int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); +int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); + +typedef struct +{ + char name[64]; + int (*init)(int phy_addr); + int (*is_phy_connected)(int phy_addr); + int (*get_link_speed)(int phy_addr); + int (*auto_negotiate)(int phy_addr); +} phy_t; + +#define PHY_LXT972 (0x001378e2) +int lxt972_is_phy_connected(int phy_addr); +int lxt972_get_link_speed(int phy_addr); +int lxt972_init_phy(int phy_addr); +int lxt972_auto_negotiate(int phy_addr); + +#define PHY_DP83848 (0x20005c90) +int dp83848_is_phy_connected(int phy_addr); +int dp83848_get_link_speed(int phy_addr); +int dp83848_init_phy(int phy_addr); +int dp83848_auto_negotiate(int phy_addr); + +#endif /* _DM644X_EMAC_H_ */ diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h new file mode 100644 index 00000000000..646fc774694 --- /dev/null +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _EMIF_DEFS_H_ +#define _EMIF_DEFS_H_ + +#include + +typedef struct { + dv_reg ERCSR; + dv_reg AWCCR; + dv_reg SDBCR; + dv_reg SDRCR; + dv_reg AB1CR; + dv_reg AB2CR; + dv_reg AB3CR; + dv_reg AB4CR; + dv_reg SDTIMR; + dv_reg DDRSR; + dv_reg DDRPHYCR; + dv_reg DDRPHYSR; + dv_reg TOTAR; + dv_reg TOTACTR; + dv_reg DDRPHYID_REV; + dv_reg SDSRETR; + dv_reg EIRR; + dv_reg EIMR; + dv_reg EIMSR; + dv_reg EIMCR; + dv_reg IOCTRLR; + dv_reg IOSTATR; + u_int8_t RSVD0[8]; + dv_reg NANDFCR; + dv_reg NANDFSR; + u_int8_t RSVD1[8]; + dv_reg NANDF1ECC; + dv_reg NANDF2ECC; + dv_reg NANDF3ECC; + dv_reg NANDF4ECC; +} emif_registers; + +typedef emif_registers *emifregs; +#endif diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h new file mode 100644 index 00000000000..ebcdcfea1e9 --- /dev/null +++ b/include/asm-arm/arch-davinci/hardware.h @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Based on: + * + * ------------------------------------------------------------------------- + * + * linux/include/asm-arm/arch-davinci/hardware.h + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include +#include + +#define REG(addr) (*(volatile unsigned int *)(addr)) +#define REG_P(addr) ((volatile unsigned int *)(addr)) + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int * dv_reg_p; + +/* + * Base register addresses + */ +#define DAVINCI_DMA_3PCC_BASE (0x01c00000) +#define DAVINCI_DMA_3PTC0_BASE (0x01c10000) +#define DAVINCI_DMA_3PTC1_BASE (0x01c10400) +#define DAVINCI_UART0_BASE (0x01c20000) +#define DAVINCI_UART1_BASE (0x01c20400) +#define DAVINCI_UART2_BASE (0x01c20800) +#define DAVINCI_I2C_BASE (0x01c21000) +#define DAVINCI_TIMER0_BASE (0x01c21400) +#define DAVINCI_TIMER1_BASE (0x01c21800) +#define DAVINCI_WDOG_BASE (0x01c21c00) +#define DAVINCI_PWM0_BASE (0x01c22000) +#define DAVINCI_PWM1_BASE (0x01c22400) +#define DAVINCI_PWM2_BASE (0x01c22800) +#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000) +#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800) +#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) +#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000) +#define DAVINCI_SYSTEM_DFT_BASE (0x01c42000) +#define DAVINCI_ARM_INTC_BASE (0x01c48000) +#define DAVINCI_IEEE1394_BASE (0x01c60000) +#define DAVINCI_USB_OTG_BASE (0x01c64000) +#define DAVINCI_CFC_ATA_BASE (0x01c66000) +#define DAVINCI_SPI_BASE (0x01c66800) +#define DAVINCI_GPIO_BASE (0x01c67000) +#define DAVINCI_UHPI_BASE (0x01c67800) +#define DAVINCI_VPSS_REGS_BASE (0x01c70000) +#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01c80000) +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01c81000) +#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01c82000) +#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01c84000) +#define DAVINCI_IMCOP_BASE (0x01cc0000) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01e00000) +#define DAVINCI_VLYNQ_BASE (0x01e01000) +#define DAVINCI_MCBSP_BASE (0x01e02000) +#define DAVINCI_MMC_SD_BASE (0x01e10000) +#define DAVINCI_MS_BASE (0x01e20000) +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) +#define DAVINCI_VLYNQ_REMOTE_BASE (0x0c000000) + +/* Power and Sleep Controller (PSC) Domains */ +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 + +#define DAVINCI_LPSC_VPSSMSTR 0 +#define DAVINCI_LPSC_VPSSSLV 1 +#define DAVINCI_LPSC_TPCC 2 +#define DAVINCI_LPSC_TPTC0 3 +#define DAVINCI_LPSC_TPTC1 4 +#define DAVINCI_LPSC_EMAC 5 +#define DAVINCI_LPSC_EMAC_WRAPPER 6 +#define DAVINCI_LPSC_MDIO 7 +#define DAVINCI_LPSC_IEEE1394 8 +#define DAVINCI_LPSC_USB 9 +#define DAVINCI_LPSC_ATA 10 +#define DAVINCI_LPSC_VLYNQ 11 +#define DAVINCI_LPSC_UHPI 12 +#define DAVINCI_LPSC_DDR_EMIF 13 +#define DAVINCI_LPSC_AEMIF 14 +#define DAVINCI_LPSC_MMC_SD 15 +#define DAVINCI_LPSC_MEMSTICK 16 +#define DAVINCI_LPSC_McBSP 17 +#define DAVINCI_LPSC_I2C 18 +#define DAVINCI_LPSC_UART0 19 +#define DAVINCI_LPSC_UART1 20 +#define DAVINCI_LPSC_UART2 21 +#define DAVINCI_LPSC_SPI 22 +#define DAVINCI_LPSC_PWM0 23 +#define DAVINCI_LPSC_PWM1 24 +#define DAVINCI_LPSC_PWM2 25 +#define DAVINCI_LPSC_GPIO 26 +#define DAVINCI_LPSC_TIMER0 27 +#define DAVINCI_LPSC_TIMER1 28 +#define DAVINCI_LPSC_TIMER2 29 +#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 +#define DAVINCI_LPSC_ARM 31 +#define DAVINCI_LPSC_SCR2 32 +#define DAVINCI_LPSC_SCR3 33 +#define DAVINCI_LPSC_SCR4 34 +#define DAVINCI_LPSC_CROSSBAR 35 +#define DAVINCI_LPSC_CFG27 36 +#define DAVINCI_LPSC_CFG3 37 +#define DAVINCI_LPSC_CFG5 38 +#define DAVINCI_LPSC_GEM 39 +#define DAVINCI_LPSC_IMCOP 40 + +/* Some PSC defines */ +#define PSC_CHP_SHRTSW (0x01c40038) +#define PSC_GBLCTL (0x01c41010) +#define PSC_EPCPR (0x01c41070) +#define PSC_EPCCR (0x01c41078) +#define PSC_PTCMD (0x01c41120) +#define PSC_PTSTAT (0x01c41128) +#define PSC_PDSTAT (0x01c41200) +#define PSC_PDSTAT1 (0x01c41204) +#define PSC_PDCTL (0x01c41300) +#define PSC_PDCTL1 (0x01c41304) + +#define PSC_MDCTL_BASE (0x01c41a00) +#define PSC_MDSTAT_BASE (0x01c41800) + +#define VDD3P3V_PWDN (0x01c40048) +#define UART0_PWREMU_MGMT (0x01c20030) + +#define PSC_SILVER_BULLET (0x01c41a20) + +/* Some PLL defines */ +#define PLL1_PLLM (0x01c40910) +#define PLL2_PLLM (0x01c40d10) +#define PLL2_DIV2 (0x01c40d1c) + +/* Miscellania... */ +#define VBPR (0x20000020) +#define PINMUX0 (0x01c40000) +#define PINMUX1 (0x01c40004) + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-davinci/i2c_defs.h b/include/asm-arm/arch-davinci/i2c_defs.h new file mode 100644 index 00000000000..2e902e17f83 --- /dev/null +++ b/include/asm-arm/arch-davinci/i2c_defs.h @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * + * Some changes copyright (C) 2007 Sergey Kubushyn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DAVINCI_I2C_H_ +#define _DAVINCI_I2C_H_ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +#define I2C_BASE 0x01c21000 + +#define I2C_OA (I2C_BASE + 0x00) +#define I2C_IE (I2C_BASE + 0x04) +#define I2C_STAT (I2C_BASE + 0x08) +#define I2C_SCLL (I2C_BASE + 0x0c) +#define I2C_SCLH (I2C_BASE + 0x10) +#define I2C_CNT (I2C_BASE + 0x14) +#define I2C_DRR (I2C_BASE + 0x18) +#define I2C_SA (I2C_BASE + 0x1c) +#define I2C_DXR (I2C_BASE + 0x20) +#define I2C_CON (I2C_BASE + 0x24) +#define I2C_IV (I2C_BASE + 0x28) +#define I2C_PSC (I2C_BASE + 0x30) + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ +#define I2C_INTCODE_SCD 6 /* Stop condition detect */ + + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 5) /* I2C module enable */ +#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ + +#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ + +#endif diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h new file mode 100644 index 00000000000..619bd479736 --- /dev/null +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts shamelesly stolen from Linux Kernel source tree. + * + * ------------------------------------------------------------ + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _NAND_DEFS_H_ +#define _NAND_DEFS_H_ + +#include + +#define MASK_CLE 0x10 +#define MASK_ALE 0x0a + +#define NAND_CE0CLE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x10)) +#define NAND_CE0ALE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x0a)) +#define NAND_CE0DATA ((volatile u_int8_t *)CFG_NAND_BASE) + +typedef struct { + u_int32_t NRCSR; + u_int32_t AWCCR; + u_int8_t RSVD0[8]; + u_int32_t AB1CR; + u_int32_t AB2CR; + u_int32_t AB3CR; + u_int32_t AB4CR; + u_int8_t RSVD1[32]; + u_int32_t NIRR; + u_int32_t NIMR; + u_int32_t NIMSR; + u_int32_t NIMCR; + u_int8_t RSVD2[16]; + u_int32_t NANDFCR; + u_int32_t NANDFSR; + u_int8_t RSVD3[8]; + u_int32_t NANDF1ECC; + u_int32_t NANDF2ECC; + u_int32_t NANDF3ECC; + u_int32_t NANDF4ECC; + u_int8_t RSVD4[4]; + u_int32_t IODFTECR; + u_int32_t IODFTGCR; + u_int8_t RSVD5[4]; + u_int32_t IODFTMRLR; + u_int32_t IODFTMRMR; + u_int32_t IODFTMRMSBR; + u_int8_t RSVD6[20]; + u_int32_t MODRNR; + u_int8_t RSVD7[76]; + u_int32_t CE0DATA; + u_int32_t CE0ALE; + u_int32_t CE0CLE; + u_int8_t RSVD8[4]; + u_int32_t CE1DATA; + u_int32_t CE1ALE; + u_int32_t CE1CLE; + u_int8_t RSVD9[4]; + u_int32_t CE2DATA; + u_int32_t CE2ALE; + u_int32_t CE2CLE; + u_int8_t RSVD10[4]; + u_int32_t CE3DATA; + u_int32_t CE3ALE; + u_int32_t CE3CLE; +} nand_registers; + +typedef volatile nand_registers *nandregs; + +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 + +#ifdef CFG_NAND_HW_ECC +#define NAND_Ecc_P1e (1 << 0) +#define NAND_Ecc_P2e (1 << 1) +#define NAND_Ecc_P4e (1 << 2) +#define NAND_Ecc_P8e (1 << 3) +#define NAND_Ecc_P16e (1 << 4) +#define NAND_Ecc_P32e (1 << 5) +#define NAND_Ecc_P64e (1 << 6) +#define NAND_Ecc_P128e (1 << 7) +#define NAND_Ecc_P256e (1 << 8) +#define NAND_Ecc_P512e (1 << 9) +#define NAND_Ecc_P1024e (1 << 10) +#define NAND_Ecc_P2048e (1 << 11) + +#define NAND_Ecc_P1o (1 << 16) +#define NAND_Ecc_P2o (1 << 17) +#define NAND_Ecc_P4o (1 << 18) +#define NAND_Ecc_P8o (1 << 19) +#define NAND_Ecc_P16o (1 << 20) +#define NAND_Ecc_P32o (1 << 21) +#define NAND_Ecc_P64o (1 << 22) +#define NAND_Ecc_P128o (1 << 23) +#define NAND_Ecc_P256o (1 << 24) +#define NAND_Ecc_P512o (1 << 25) +#define NAND_Ecc_P1024o (1 << 26) +#define NAND_Ecc_P2048o (1 << 27) + +#define TF(v) (v ? 1 : 0) + +#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) +#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) +#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) +#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) +#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) +#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) +#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) +#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) + +#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) +#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) +#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) +#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) +#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) +#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) +#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) +#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) + +#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) +#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) +#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) +#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) +#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) +#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) +#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) +#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) + +#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) +#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) +#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) +#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) +#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) +#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) +#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) +#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) + +#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) +#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) +#endif + +#endif diff --git a/include/common.h b/include/common.h index ac29d3aac6c..229e64bd49d 100644 --- a/include/common.h +++ b/include/common.h @@ -241,6 +241,9 @@ int saveenv (void); void inline setenv (char *, char *); #else void setenv (char *, char *); +#ifdef CONFIG_HAS_UID +void forceenv (char *, char *); +#endif #endif /* CONFIG_PPC */ #ifdef CONFIG_ARM # include diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h new file mode 100644 index 00000000000..8ecd0595a20 --- /dev/null +++ b/include/configs/davinci_dvevm.h @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include + +/* + * Define this to make U-Boot skip low level initialization when loaded + * by initial bootloader. Not required by NAND U-Boot version but IS + * required for a NOR version used to burn the real NOR U-Boot into + * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive + * so it is NOT possible to build a U-Boot with both NAND and NOR routines. + * NOR U-Boot is loaded directly from Flash so it must perform all the + * low level initialization itself. NAND version is loaded by an initial + * bootloader (UBL in TI-ese) that performs such an initialization so it's + * skipped in NAND version. The third DaVinci boot mode loads a bootloader + * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) + * performing low level init prior to loading. All that means we can NOT use + * NAND version to put U-Boot into NOR because it doesn't have NOR support and + * we can NOT use NOR version because it performs low level initialization + * effectively destroying itself in DDR memory. That's why a separate NOR + * version with this define is needed. It is loaded via UART, then one uses + * it to somehow download a proper NOR version built WITHOUT this define to + * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze + * NOR support into the initial bootloader so it won't be needed but DaVinci + * static RAM might be too small for this (I have something like 2Kbytes left + * as of now, without NOR support) so this might've not happened... + * +#define CONFIG_NOR_UART_BOOT + */ + +/*=======*/ +/* Board */ +/*=======*/ +#define DV_EVM +#define CFG_NAND_SMALLPAGE +#define CFG_USE_NOR +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/*====================================================*/ +/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ +/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ +/*====================================================*/ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 6 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */ +#define DDR_8BANKS /* 8-bank DDR2 (256MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#ifdef CFG_USE_NAND +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#ifdef CFG_NAND_SMALLPAGE +#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_16K +#else +#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_128K +#endif +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define DEF_BOOTM "" +#elif defined(CFG_USE_NOR) +#ifdef CONFIG_NOR_UART_BOOT +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#else +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT +#endif +#define CFG_ENV_IS_IN_FLASH +#undef CFG_NO_FLASH +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */ +#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3) +#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ +#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ +#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ +#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) +#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ +#endif +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000" +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#ifdef CFG_USE_NAND +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND +#elif defined(CFG_USE_NOR) +#define CONFIG_CMD_JFFS2 +#else +#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!" +#endif +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h new file mode 100644 index 00000000000..96c9a301478 --- /dev/null +++ b/include/configs/davinci_schmoogie.h @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include + +/*=======*/ +/* Board */ +/*=======*/ +#define SCHMOOGIE +#define CFG_NAND_LARGEPAGE +#define CFG_USE_NAND +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ +#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_128K +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +/*=====================*/ +/* Board related stuff */ +/*=====================*/ +#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */ +#define CFG_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */ +#define CONFIG_HAS_UID +#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */ +#define CFG_UID_ADDR 0x50 /* UID chip I2C address */ +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_DATE +#define CONFIG_CMD_NAND +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h new file mode 100644 index 00000000000..de8c4fac2b0 --- /dev/null +++ b/include/configs/davinci_sonata.h @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include + +/* + * Define this to make U-Boot skip low level initialization when loaded + * by initial bootloader. Not required by NAND U-Boot version but IS + * required for a NOR version used to burn the real NOR U-Boot into + * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive + * so it is NOT possible to build a U-Boot with both NAND and NOR routines. + * NOR U-Boot is loaded directly from Flash so it must perform all the + * low level initialization itself. NAND version is loaded by an initial + * bootloader (UBL in TI-ese) that performs such an initialization so it's + * skipped in NAND version. The third DaVinci boot mode loads a bootloader + * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever) + * performing low level init prior to loading. All that means we can NOT use + * NAND version to put U-Boot into NOR because it doesn't have NOR support and + * we can NOT use NOR version because it performs low level initialization + * effectively destroying itself in DDR memory. That's why a separate NOR + * version with this define is needed. It is loaded via UART, then one uses + * it to somehow download a proper NOR version built WITHOUT this define to + * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze + * NOR support into the initial bootloader so it won't be needed but DaVinci + * static RAM might be too small for this (I have something like 2Kbytes left + * as of now, without NOR support) so this might've not happened... + * +#define CONFIG_NOR_UART_BOOT + */ + +/*=======*/ +/* Board */ +/*=======*/ +#define SONATA_BOARD +#define CFG_NAND_SMALLPAGE +#define CFG_USE_NOR +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/*====================================================*/ +/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ +/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ +/*====================================================*/ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 6 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CFG_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ +#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#ifdef CFG_USE_NAND +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CFG_ENV_SECT_SIZE 512 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_16K +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define DEF_BOOTM "" +#elif defined(CFG_USE_NOR) +#ifdef CONFIG_NOR_UART_BOOT +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#else +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT +#endif +#define CFG_ENV_IS_IN_FLASH +#undef CFG_NO_FLASH +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */ +#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*2) +#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ +#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ +#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ +#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) +#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ +#endif +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000" +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#ifdef CFG_USE_NAND +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND +#elif defined(CFG_USE_NOR) +#define CONFIG_CMD_JFFS2 +#else +#error "Either CFG_USE_NAND or CFG_USE_NOR _MUST_ be defined !!!" +#endif +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/dp83848.h b/include/dp83848.h new file mode 100644 index 00000000000..274bc4c969c --- /dev/null +++ b/include/dp83848.h @@ -0,0 +1,88 @@ +/* + * DP83848 ethernet Physical layer + * + * Copyright (C) 2007 Sergey Kubushyn + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + + +/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */ + +#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */ +#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */ +#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */ +#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */ +#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */ +#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */ +#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */ +#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */ +#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */ +#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ + +/*--Bit definitions: DP83848_CTL_REG */ +#define DP83848_RESET (1 << 15) /* 1= S/W Reset */ +#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ +#define DP83848_SPEED_SELECT (1 << 13) +#define DP83848_AUTONEG (1 << 12) +#define DP83848_POWER_DOWN (1 << 11) +#define DP83848_ISOLATE (1 << 10) +#define DP83848_RESTART_AUTONEG (1 << 9) +#define DP83848_DUPLEX_MODE (1 << 8) +#define DP83848_COLLISION_TEST (1 << 7) + +/*--Bit definitions: DP83848_STAT_REG */ +#define DP83848_100BASE_T4 (1 << 15) +#define DP83848_100BASE_TX_FD (1 << 14) +#define DP83848_100BASE_TX_HD (1 << 13) +#define DP83848_10BASE_T_FD (1 << 12) +#define DP83848_10BASE_T_HD (1 << 11) +#define DP83848_MF_PREAMB_SUPPR (1 << 6) +#define DP83848_AUTONEG_COMP (1 << 5) +#define DP83848_RMT_FAULT (1 << 4) +#define DP83848_AUTONEG_ABILITY (1 << 3) +#define DP83848_LINK_STATUS (1 << 2) +#define DP83848_JABBER_DETECT (1 << 1) +#define DP83848_EXTEND_CAPAB (1 << 0) + +/*--definitions: DP83848_PHYID1 */ +#define DP83848_PHYID1_OUI 0x2000 +#define DP83848_PHYID2_OUI 0x5c90 + +/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ +#define DP83848_NP (1 << 15) +#define DP83848_ACK (1 << 14) +#define DP83848_RF (1 << 13) +#define DP83848_PAUSE (1 << 10) +#define DP83848_T4 (1 << 9) +#define DP83848_TX_FDX (1 << 8) +#define DP83848_TX_HDX (1 << 7) +#define DP83848_10_FDX (1 << 6) +#define DP83848_10_HDX (1 << 5) +#define DP83848_AN_IEEE_802_3 0x0001 + +/*--Bit definitions: DP83848_ANER */ +#define DP83848_PDF (1 << 4) +#define DP83848_LP_NP_ABLE (1 << 3) +#define DP83848_NP_ABLE (1 << 2) +#define DP83848_PAGE_RX (1 << 1) +#define DP83848_LP_AN_ABLE (1 << 0) + +/*--Bit definitions: DP83848_PHY_STAT */ +#define DP83848_RX_ERR_LATCH (1 << 13) +#define DP83848_POLARITY_STAT (1 << 12) +#define DP83848_FALSE_CAR_SENSE (1 << 11) +#define DP83848_SIG_DETECT (1 << 10) +#define DP83848_DESCRAM_LOCK (1 << 9) +#define DP83848_PAGE_RCV (1 << 8) +#define DP83848_PHY_RMT_FAULT (1 << 6) +#define DP83848_JABBER (1 << 5) +#define DP83848_AUTONEG_COMPLETE (1 << 4) +#define DP83848_LOOPBACK_STAT (1 << 3) +#define DP83848_DUPLEX (1 << 2) +#define DP83848_SPEED (1 << 1) +#define DP83848_LINK (1 << 0) diff --git a/include/exports.h b/include/exports.h index 0516da93749..d6512cb3a45 100644 --- a/include/exports.h +++ b/include/exports.h @@ -25,6 +25,9 @@ char *getenv (char *name); void setenv (char *varname, char *varvalue); long simple_strtol(const char *cp,char **endp,unsigned int base); int strcmp(const char * cs,const char * ct); +#ifdef CONFIG_HAS_UID +void forceenv (char *varname, char *varvalue); +#endif #if defined(CONFIG_CMD_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); diff --git a/lib_arm/board.c b/lib_arm/board.c index 8f4e19bfcb5..d37e5dab352 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -364,6 +364,13 @@ void start_armboot (void) enable_interrupts (); /* Perform network card initialisation if necessary */ +#ifdef CONFIG_DRIVER_TI_EMAC +extern void dm644x_eth_set_mac_addr (const u_int8_t *addr); + if (getenv ("ethaddr")) { + dm644x_eth_set_mac_addr(gd->bd->bi_enetaddr); + } +#endif + #ifdef CONFIG_DRIVER_CS8900 cs8900_get_enetaddr (gd->bd->bi_enetaddr); #endif diff --git a/net/eth.c b/net/eth.c index 6576ee405bb..c8f92a52634 100644 --- a/net/eth.c +++ b/net/eth.c @@ -464,6 +464,8 @@ extern int at91rm9200_miiphy_initialize(bd_t *bis); extern int emac4xx_miiphy_initialize(bd_t *bis); extern int mcf52x2_miiphy_initialize(bd_t *bis); extern int ns7520_miiphy_initialize(bd_t *bis); +extern int dm644x_eth_miiphy_initialize(bd_t *bis); + int eth_initialize(bd_t *bis) { @@ -483,6 +485,9 @@ int eth_initialize(bd_t *bis) #endif #if defined(CONFIG_NETARM) ns7520_miiphy_initialize(bis); +#endif +#if defined(CONFIG_DRIVER_TI_EMAC) + dm644x_eth_miiphy_initialize(bis); #endif return 0; } -- cgit v1.3.1