From 48412f8f2962e27abe3b9a4a73221cebbfd73333 Mon Sep 17 00:00:00 2001 From: Randolph Sapp Date: Thu, 4 Jun 2026 10:50:38 -0500 Subject: memory: reserve from start_addr_sp to initial_relocaddr Add a new global data struct member called initial_relocaddr. This stores the original value of relocaddr, directly from setup_dest_addr. This is specifically to avoid any adjustments made by other init functions. Reserve the memory from gd->start_addr_sp - CONFIG_STACK_SIZE to gd->initial_relocaddr instead of gd->ram_top. This allows platform specific relocation addresses to work without unnecessarily painting over a large range. Signed-off-by: Randolph Sapp Reviewed-by: Simon Glass Reviewed-by: Ilias Apalodimas --- include/asm-generic/global_data.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/asm-generic/global_data.h') diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 745d2c3a966..8d1d49b1133 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -107,6 +107,15 @@ struct global_data { * GDB using the 'add-symbol-file u-boot ' command. */ unsigned long relocaddr; + /** + * @initial_relocaddr: top address of U-Boot in RAM + * + * This should be the value of relocaddr after setup_dest_addr() and + * before reserve_pram() or any other allocations or reservations shift + * it. This address will, depending on the platform, be equivalent to + * ram_top and should also be considered an exclusive address. + */ + unsigned long initial_relocaddr; /** * @irq_sp: IRQ stack pointer */ -- cgit v1.3.1 From 157186fbfc24c54117b41e292a35809a0560b9c0 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 5 Jun 2026 15:44:46 +0200 Subject: global_data: fix type for gd_malloc_ptr() With commit 92aa3ec321b5 ("global_data: Reduce size of early-malloc vars") the type changes from (unsigned) long to int. But the type for default if SYS_MALLOC_F_LEN is unset was not changed. Remove the suffix. Fixes the warning: common/spl/spl.c:800:23: warning: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'long int' [-Wformat=] Fixes: 92aa3ec321b5 ("global_data: Reduce size of early-malloc vars") Signed-off-by: Alexander Stein Reviewed-by: Simon Glass --- include/asm-generic/global_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-generic/global_data.h') diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 8d1d49b1133..ba6a10cf2ad 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -547,7 +547,7 @@ static_assert(sizeof(struct global_data) == GD_SIZE); #if CONFIG_VAL(SYS_MALLOC_F_LEN) #define gd_malloc_ptr() gd->malloc_ptr #else -#define gd_malloc_ptr() 0L +#define gd_malloc_ptr() 0 #endif #if CONFIG_IS_ENABLED(UPL) -- cgit v1.3.1 From 1174c99ab421168221be372bd83a4143bf5f167d Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Wed, 17 Jun 2026 10:48:19 +0300 Subject: treewide: move bi_dram[] from bd to gd Currently, the bi_dram[] information is stored in the board info structure (bd). Because bd is only valid after reserve_board(), dram_init_banksize() must be called late in the initialization process. This limitation is problematic, as it forces us to rely on a variety of bespoke functions to determine board RAM, bank memory sizes, and other early setup requirements. By moving bi_dram[] into the global data (gd), we can run it earlier. This is particularly convenient since boards define their own dram_init_banksize() routines, which do not always rely on parsing Device Tree (DT) memory nodes. Additionally, U-Boot defaults to relocating to the top of the first memory bank. While boards currently use custom functions to override this behavior, having the DRAM bank information available earlier in gd makes relocating to a different bank trivial and standardizes the process. Reviewed-by: Anshul Dalal Tested-by: Michal Simek # Versal Gen 2 Vek385 Tested-by: Anshul Dalal Reviewed-by: Simon Glass Signed-off-by: Ilias Apalodimas Tested-by: Christophe Leroy (CS GROUP) --- api/api_platform.c | 4 +- arch/arm/cpu/armv8/cache_v8.c | 6 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 118 ++++++++++----------- arch/arm/lib/bootm-fdt.c | 5 +- arch/arm/lib/bootm.c | 4 +- arch/arm/lib/cache-cp15.c | 9 +- arch/arm/lib/image.c | 2 +- arch/arm/mach-airoha/an7581/init.c | 8 +- arch/arm/mach-apple/board.c | 4 +- arch/arm/mach-davinci/misc.c | 4 +- arch/arm/mach-imx/ele_ahab.c | 7 +- arch/arm/mach-imx/imx8/ahab.c | 7 +- arch/arm/mach-imx/imx8/cpu.c | 44 ++++---- arch/arm/mach-imx/imx8m/soc.c | 24 ++--- arch/arm/mach-imx/imx8ulp/soc.c | 20 ++-- arch/arm/mach-imx/imx9/scmi/soc.c | 24 ++--- arch/arm/mach-imx/imx9/soc.c | 24 ++--- arch/arm/mach-imx/mx5/mx53_dram.c | 8 +- arch/arm/mach-imx/spl.c | 4 +- arch/arm/mach-k3/k3-ddr.c | 4 +- arch/arm/mach-mvebu/alleycat5/cpu.c | 4 +- arch/arm/mach-mvebu/armada3700/cpu.c | 10 +- arch/arm/mach-mvebu/armada8k/dram.c | 10 +- arch/arm/mach-mvebu/dram.c | 6 +- arch/arm/mach-omap2/am33xx/board.c | 4 +- arch/arm/mach-omap2/omap-cache.c | 5 +- arch/arm/mach-omap2/omap3/emif4.c | 8 +- arch/arm/mach-omap2/omap3/sdrc.c | 8 +- arch/arm/mach-owl/soc.c | 4 +- arch/arm/mach-renesas/memmap-gen3.c | 8 +- arch/arm/mach-renesas/memmap-rzg2l.c | 4 +- arch/arm/mach-rockchip/rk3588/rk3588.c | 8 +- arch/arm/mach-rockchip/sdram.c | 42 ++++---- arch/arm/mach-snapdragon/board.c | 16 +-- arch/arm/mach-socfpga/board.c | 5 +- arch/arm/mach-socfpga/misc_arria10.c | 7 +- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 +- arch/arm/mach-stm32mp/stm32mp1/cpu.c | 7 +- arch/arm/mach-tegra/board2.c | 14 +-- arch/arm/mach-tegra/cboot.c | 4 +- arch/arm/mach-uniphier/dram_init.c | 6 +- arch/arm/mach-uniphier/fdt-fixup.c | 8 +- arch/arm/mach-versal-net/cpu.c | 8 +- arch/arm/mach-versal/cpu.c | 16 +-- arch/arm/mach-versal2/cpu.c | 7 +- arch/arm/mach-zynqmp/cpu.c | 8 +- arch/mips/mach-octeon/dram.c | 4 +- arch/riscv/cpu/k1/dram.c | 12 +-- arch/sandbox/cpu/spl.c | 4 +- arch/x86/cpu/coreboot/sdram.c | 4 +- arch/x86/cpu/efi/payload.c | 4 +- arch/x86/cpu/efi/sdram.c | 4 +- arch/x86/cpu/intel_common/mrc.c | 4 +- arch/x86/cpu/ivybridge/sdram_nop.c | 4 +- arch/x86/cpu/qemu/dram.c | 8 +- arch/x86/cpu/quark/dram.c | 4 +- arch/x86/cpu/slimbootloader/sdram.c | 4 +- arch/x86/cpu/tangier/sdram.c | 4 +- arch/x86/lib/bootm.c | 5 +- arch/x86/lib/fsp/fsp_dram.c | 18 ++-- board/CZ.NIC/turris_1x/turris_1x.c | 42 ++++---- board/armltd/corstone1000/corstone1000.c | 4 +- board/armltd/integrator/integrator.c | 4 +- board/armltd/total_compute/total_compute.c | 6 +- board/armltd/vexpress/vexpress_common.c | 8 +- board/atmel/common/video_display.c | 2 +- board/atmel/sam9x60_curiosity/sam9x60_curiosity.c | 2 +- board/atmel/sam9x75_curiosity/sam9x75_curiosity.c | 2 +- board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c | 2 +- .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 2 +- .../atmel/sama5d29_curiosity/sama5d29_curiosity.c | 2 +- board/atmel/sama5d2_xplained/sama5d2_xplained.c | 2 +- .../atmel/sama7d65_curiosity/sama7d65_curiosity.c | 2 +- .../atmel/sama7g54_curiosity/sama7g54_curiosity.c | 2 +- board/axiado/scm3005/scm3005.c | 4 +- board/broadcom/bcmns3/ns3.c | 4 +- board/compulab/cm_fx6/cm_fx6.c | 28 ++--- board/elgin/elgin_rv1108/elgin_rv1108.c | 4 +- board/esd/meesc/meesc.c | 4 +- board/friendlyarm/nanopi2/board.c | 10 +- board/ge/mx53ppd/mx53ppd.c | 8 +- board/hisilicon/hikey/hikey.c | 24 ++--- board/hisilicon/hikey960/hikey960.c | 4 +- board/hisilicon/poplar/poplar.c | 4 +- board/k+p/kp_imx53/kp_imx53.c | 4 +- board/keymile/pg-wcom-ls102xa/ddr.c | 4 +- board/kontron/sl28/sl28.c | 4 +- board/kontron/sl28/spl_atf.c | 6 +- board/liebherr/btt/btt.c | 2 +- board/menlo/m53menlo/m53menlo.c | 8 +- board/nuvoton/arbel_evb/arbel_evb.c | 26 ++--- board/nxp/imxrt1020-evk/imxrt1020-evk.c | 2 +- board/nxp/imxrt1050-evk/imxrt1050-evk.c | 2 +- board/nxp/imxrt1170-evk/imxrt1170-evk.c | 2 +- board/nxp/ls1021aqds/ddr.c | 4 +- board/nxp/ls1028a/ls1028a.c | 10 +- board/nxp/ls1043aqds/ls1043aqds.c | 8 +- board/nxp/ls1043ardb/ls1043ardb.c | 8 +- board/nxp/ls1046afrwy/ls1046afrwy.c | 8 +- board/nxp/ls1046aqds/ls1046aqds.c | 8 +- board/nxp/ls1046ardb/ls1046ardb.c | 8 +- board/nxp/ls1088a/ls1088a.c | 6 +- board/nxp/ls2080aqds/ls2080aqds.c | 14 +-- board/nxp/ls2080ardb/ls2080ardb.c | 14 +-- board/nxp/lx2160a/lx2160a.c | 6 +- board/phytec/phycore_am62x/phycore-am62x.c | 26 ++--- board/phytec/phycore_am64x/phycore-am64x.c | 18 ++-- board/phytium/durian/durian.c | 4 +- board/phytium/pe2201/pe2201.c | 4 +- board/raspberrypi/rpi/rpi.c | 4 +- board/renesas/common/rcar64-common.c | 6 +- board/renesas/genmai/genmai.c | 4 +- board/renesas/sparrowhawk/sparrowhawk.c | 8 +- board/ronetix/pm9261/pm9261.c | 4 +- board/ronetix/pm9263/pm9263.c | 4 +- board/ronetix/pm9g45/pm9g45.c | 4 +- board/samsung/arndale/arndale.c | 4 +- board/samsung/common/board.c | 6 +- board/samsung/exynos-mobile/exynos-mobile.c | 4 +- board/samsung/goni/goni.c | 12 +-- board/samsung/smdkc100/smdkc100.c | 4 +- board/samsung/smdkv310/smdkv310.c | 16 +-- board/siemens/iot2050/board.c | 16 +-- board/socionext/developerbox/developerbox.c | 6 +- board/st/stih410-b2260/board.c | 4 +- board/ste/stemmy/stemmy.c | 4 +- board/ti/dra7xx/evm.c | 8 +- board/ti/ks2_evm/board.c | 4 +- board/toradex/colibri_imx7/colibri_imx7.c | 8 +- board/toradex/verdin-am62/verdin-am62.c | 2 +- board/toradex/verdin-am62p/verdin-am62p.c | 2 +- board/traverse/ten64/ten64.c | 6 +- board/xilinx/zynq/cmds.c | 6 +- board/xilinx/zynqmp/zynqmp.c | 4 +- boot/image-board.c | 2 +- boot/image-fdt.c | 4 +- cmd/bdinfo.c | 12 +-- cmd/ti/ddr4.c | 8 +- cmd/ufetch.c | 4 +- common/board_f.c | 10 +- common/init/handoff.c | 10 +- drivers/bootcount/bootcount_ram.c | 4 +- drivers/ddr/altera/sdram_agilex.c | 4 +- drivers/ddr/altera/sdram_agilex5.c | 18 ++-- drivers/ddr/altera/sdram_agilex7m.c | 4 +- drivers/ddr/altera/sdram_arria10.c | 12 +-- drivers/ddr/altera/sdram_n5x.c | 4 +- drivers/ddr/altera/sdram_s10.c | 4 +- drivers/ddr/altera/sdram_soc64.c | 28 ++--- drivers/mmc/mvebu_mmc.c | 4 +- drivers/net/mvgbe.c | 4 +- drivers/pci/pci-uclass.c | 8 +- drivers/usb/host/ehci-marvell.c | 4 +- drivers/video/meson/meson_vpu.c | 8 +- drivers/video/sunxi/sunxi_de2.c | 2 +- drivers/video/sunxi/sunxi_display.c | 2 +- include/asm-generic/global_data.h | 7 ++ include/asm-generic/u-boot.h | 4 - include/configs/m53menlo.h | 4 +- include/configs/mx53cx9020.h | 4 +- include/configs/mx53loco.h | 4 +- include/configs/mx53ppd.h | 4 +- include/fdtdec.h | 7 +- include/init.h | 2 +- lib/fdtdec.c | 23 ++-- lib/lmb.c | 19 ++-- test/cmd/bdinfo.c | 7 +- 167 files changed, 707 insertions(+), 714 deletions(-) (limited to 'include/asm-generic/global_data.h') diff --git a/api/api_platform.c b/api/api_platform.c index d5cbcd6e201..d4edf3a20fe 100644 --- a/api/api_platform.c +++ b/api/api_platform.c @@ -21,8 +21,8 @@ int platform_sys_info(struct sys_info *si) si->clk_cpu = gd->cpu_clk; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - platform_set_mr(si, gd->bd->bi_dram[i].start, - gd->bd->bi_dram[i].size, MR_ATTR_DRAM); + platform_set_mr(si, gd->dram[i].start, + gd->dram[i].size, MR_ATTR_DRAM); platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM); platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH); diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 6c85022556a..e59528e576e 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -69,9 +69,9 @@ int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs) } for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - mem_map[index].virt = gd->bd->bi_dram[i].start; - mem_map[index].phys = gd->bd->bi_dram[i].start; - mem_map[index].size = gd->bd->bi_dram[i].size; + mem_map[index].virt = gd->dram[i].start; + mem_map[index].phys = gd->dram[i].start; + mem_map[index].size = gd->dram[i].size; mem_map[index].attrs = attrs; index++; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index cbeac6d4383..88adcf35432 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -538,16 +538,16 @@ static inline void final_mmu_setup(void) */ switch (final_map[index].virt) { case CFG_SYS_FSL_DRAM_BASE1: - final_map[index].virt = gd->bd->bi_dram[0].start; - final_map[index].phys = gd->bd->bi_dram[0].start; - final_map[index].size = gd->bd->bi_dram[0].size; + final_map[index].virt = gd->dram[0].start; + final_map[index].phys = gd->dram[0].start; + final_map[index].size = gd->dram[0].size; break; #ifdef CFG_SYS_FSL_DRAM_BASE2 case CFG_SYS_FSL_DRAM_BASE2: #if (CONFIG_NR_DRAM_BANKS >= 2) - final_map[index].virt = gd->bd->bi_dram[1].start; - final_map[index].phys = gd->bd->bi_dram[1].start; - final_map[index].size = gd->bd->bi_dram[1].size; + final_map[index].virt = gd->dram[1].start; + final_map[index].phys = gd->dram[1].start; + final_map[index].size = gd->dram[1].size; #else final_map[index].size = 0; #endif @@ -556,9 +556,9 @@ static inline void final_mmu_setup(void) #ifdef CFG_SYS_FSL_DRAM_BASE3 case CFG_SYS_FSL_DRAM_BASE3: #if (CONFIG_NR_DRAM_BANKS >= 3) - final_map[index].virt = gd->bd->bi_dram[2].start; - final_map[index].phys = gd->bd->bi_dram[2].start; - final_map[index].size = gd->bd->bi_dram[2].size; + final_map[index].virt = gd->dram[2].start; + final_map[index].phys = gd->dram[2].start; + final_map[index].size = gd->dram[2].size; #else final_map[index].size = 0; #endif @@ -1396,10 +1396,10 @@ static int tfa_dram_init_banksize(void) } debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2); - gd->bd->bi_dram[i].start = res.a1; - gd->bd->bi_dram[i].size = res.a2; + gd->dram[i].start = res.a1; + gd->dram[i].size = res.a2; - dram_size -= gd->bd->bi_dram[i].size; + dram_size -= gd->dram[i].size; i++; } while (dram_size); @@ -1410,24 +1410,24 @@ static int tfa_dram_init_banksize(void) #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bd->bi_dram[2].size >= - board_reserve_ram_top(gd->bd->bi_dram[2].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[2].start + - gd->bd->bi_dram[2].size - - board_reserve_ram_top(gd->bd->bi_dram[2].size); + if (gd->dram[2].size >= + board_reserve_ram_top(gd->dram[2].size)) { + gd->arch.resv_ram = gd->dram[2].start + + gd->dram[2].size - + board_reserve_ram_top(gd->dram[2].size); } else #endif { - if (gd->bd->bi_dram[1].size >= - board_reserve_ram_top(gd->bd->bi_dram[1].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[1].start + - gd->bd->bi_dram[1].size - - board_reserve_ram_top(gd->bd->bi_dram[1].size); - } else if (gd->bd->bi_dram[0].size > - board_reserve_ram_top(gd->bd->bi_dram[0].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - - board_reserve_ram_top(gd->bd->bi_dram[0].size); + if (gd->dram[1].size >= + board_reserve_ram_top(gd->dram[1].size)) { + gd->arch.resv_ram = gd->dram[1].start + + gd->dram[1].size - + board_reserve_ram_top(gd->dram[1].size); + } else if (gd->dram[0].size > + board_reserve_ram_top(gd->dram[0].size)) { + gd->arch.resv_ram = gd->dram[0].start + + gd->dram[0].size - + board_reserve_ram_top(gd->dram[0].size); } } #endif /* CONFIG_RESV_RAM */ @@ -1464,30 +1464,30 @@ int dram_init_banksize(void) } #endif - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - + gd->dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; + gd->dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; + gd->dram[1].size = gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; - gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - + if (gd->dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { + gd->dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; + gd->dram[2].size = gd->dram[1].size - CONFIG_SYS_DDR_BLOCK2_SIZE; - gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; + gd->dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; } #endif } else { - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; } #ifdef CFG_SYS_MEM_RESERVE_SECURE - if (gd->bd->bi_dram[0].size > + if (gd->dram[0].size > CFG_SYS_MEM_RESERVE_SECURE) { - gd->bd->bi_dram[0].size -= + gd->dram[0].size -= CFG_SYS_MEM_RESERVE_SECURE; - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size; + gd->arch.secure_ram = gd->dram[0].start + + gd->dram[0].size; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE; } @@ -1496,24 +1496,24 @@ int dram_init_banksize(void) #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bd->bi_dram[2].size >= - board_reserve_ram_top(gd->bd->bi_dram[2].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[2].start + - gd->bd->bi_dram[2].size - - board_reserve_ram_top(gd->bd->bi_dram[2].size); + if (gd->dram[2].size >= + board_reserve_ram_top(gd->dram[2].size)) { + gd->arch.resv_ram = gd->dram[2].start + + gd->dram[2].size - + board_reserve_ram_top(gd->dram[2].size); } else #endif { - if (gd->bd->bi_dram[1].size >= - board_reserve_ram_top(gd->bd->bi_dram[1].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[1].start + - gd->bd->bi_dram[1].size - - board_reserve_ram_top(gd->bd->bi_dram[1].size); - } else if (gd->bd->bi_dram[0].size > - board_reserve_ram_top(gd->bd->bi_dram[0].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - - board_reserve_ram_top(gd->bd->bi_dram[0].size); + if (gd->dram[1].size >= + board_reserve_ram_top(gd->dram[1].size)) { + gd->arch.resv_ram = gd->dram[1].start + + gd->dram[1].size - + board_reserve_ram_top(gd->dram[1].size); + } else if (gd->dram[0].size > + board_reserve_ram_top(gd->dram[0].size)) { + gd->arch.resv_ram = gd->dram[0].start + + gd->dram[0].size - + board_reserve_ram_top(gd->dram[0].size); } } #endif /* CONFIG_RESV_RAM */ @@ -1535,8 +1535,8 @@ int dram_init_banksize(void) CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, NULL, NULL, NULL); if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; + gd->dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->dram[2].size = dp_ddr_size; } else { puts("Not detected"); } @@ -1567,8 +1567,8 @@ void lmb_arch_add_memory(void) if (i == 2) continue; /* skip DP-DDR */ #endif - ram_start = gd->bd->bi_dram[i].start; - ram_size = gd->bd->bi_dram[i].size; + ram_start = gd->dram[i].start; + ram_size = gd->dram[i].size; #ifdef CONFIG_RESV_RAM if (gd->arch.resv_ram >= ram_start && gd->arch.resv_ram < ram_start + ram_size) diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 2671f9a0ebf..a82ceeaf22f 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -35,14 +35,13 @@ int arch_fixup_fdt(void *blob) { __maybe_unused int ret = 0; #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT) - struct bd_info *bd = gd->bd; int bank; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; #ifdef CONFIG_ARMV7_NONSEC ret = armv7_apply_memory_carveout(&start[bank], &size[bank]); if (ret) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 1cde655bc80..9a115cc6078 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -64,8 +64,8 @@ static void setup_memory_tags(struct bd_info *bd) params->hdr.tag = ATAG_MEM; params->hdr.size = tag_size (tag_mem32); - params->u.mem.start = bd->bi_dram[i].start; - params->u.mem.size = bd->bi_dram[i].size; + params->u.mem.start = gd->dram[i].start; + params->u.mem.size = gd->dram[i].size; params = tag_next (params); } diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 947012f2996..28bb6fd36c8 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -94,17 +94,16 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, __weak void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; - /* bd->bi_dram is available only after relocation */ + /* gd->dram is available only after relocation */ if ((gd->flags & GD_FLG_RELOC) == 0) return; debug("%s: bank: %d\n", __func__, bank); - for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + - (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); + for (i = gd->dram[bank].start >> MMU_SECTION_SHIFT; + i < (gd->dram[bank].start >> MMU_SECTION_SHIFT) + + (gd->dram[bank].size >> MMU_SECTION_SHIFT); i++) set_section_dcache(i, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c index 1f672eee2c8..2268661de93 100644 --- a/arch/arm/lib/image.c +++ b/arch/arm/lib/image.c @@ -69,7 +69,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, if (!force_reloc && (le64_to_cpu(ih->flags) & BIT(3))) dst = image - text_offset; else - dst = gd->bd->bi_dram[0].start; + dst = gd->dram[0].start; *relocated_addr = ALIGN(dst, SZ_2M) + text_offset; diff --git a/arch/arm/mach-airoha/an7581/init.c b/arch/arm/mach-airoha/an7581/init.c index ab32706a79d..f33527ca129 100644 --- a/arch/arm/mach-airoha/an7581/init.c +++ b/arch/arm/mach-airoha/an7581/init.c @@ -23,12 +23,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); if (gd->ram_size > SZ_2G) { - gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = gd->ram_base + SZ_2G; + gd->dram[1].size = gd->ram_size - SZ_2G; } return 0; diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 20054f54089..e74a5a76919 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -807,8 +807,8 @@ void build_mem_map(void) ; /* Align RAM mapping to page boundaries */ - base = gd->bd->bi_dram[0].start; - size = gd->bd->bi_dram[0].size; + base = gd->dram[0].start; + size = gd->dram[0].size; size += (base - ALIGN_DOWN(base, SZ_4K)); base = ALIGN_DOWN(base, SZ_4K); size = ALIGN(size, SZ_4K); diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 07125eac7cd..2281686d633 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -33,8 +33,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 86b11bdf2ac..e1284833ac5 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -311,12 +311,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) static inline bool check_in_dram(ulong addr) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - if (addr >= bd->bi_dram[i].start && - addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + if (gd->dram[i].size) { + if (addr >= gd->dram[i].start && + addr < (gd->dram[i].start + gd->dram[i].size)) return true; } } diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 71a3b341913..34712747fa3 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -111,12 +111,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) static inline bool check_in_dram(ulong addr) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - if (addr >= bd->bi_dram[i].start && - addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + if (gd->dram[i].size) { + if (addr >= gd->dram[i].start && + addr < (gd->dram[i].start + gd->dram[i].size)) return true; } } diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index f4738e3fda8..b52675d8aba 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -604,18 +604,18 @@ static void dram_bank_sort(int current_bank) phys_size_t size; while (current_bank > 0) { - if (gd->bd->bi_dram[current_bank - 1].start > - gd->bd->bi_dram[current_bank].start) { - start = gd->bd->bi_dram[current_bank - 1].start; - size = gd->bd->bi_dram[current_bank - 1].size; - - gd->bd->bi_dram[current_bank - 1].start = - gd->bd->bi_dram[current_bank].start; - gd->bd->bi_dram[current_bank - 1].size = - gd->bd->bi_dram[current_bank].size; - - gd->bd->bi_dram[current_bank].start = start; - gd->bd->bi_dram[current_bank].size = size; + if (gd->dram[current_bank - 1].start > + gd->dram[current_bank].start) { + start = gd->dram[current_bank - 1].start; + size = gd->dram[current_bank - 1].size; + + gd->dram[current_bank - 1].start = + gd->dram[current_bank].start; + gd->dram[current_bank - 1].size = + gd->dram[current_bank].size; + + gd->dram[current_bank].start = start; + gd->dram[current_bank].size = size; } current_bank--; } @@ -643,24 +643,24 @@ int dram_init_banksize(void) continue; if (start >= phys_sdram_1_start && start <= end1) { - gd->bd->bi_dram[i].start = start; + gd->dram[i].start = start; if ((end + 1) <= end1) - gd->bd->bi_dram[i].size = + gd->dram[i].size = end - start + 1; else - gd->bd->bi_dram[i].size = end1 - start; + gd->dram[i].size = end1 - start; dram_bank_sort(i); i++; } else if (start >= phys_sdram_2_start && start <= end2) { - gd->bd->bi_dram[i].start = start; + gd->dram[i].start = start; if ((end + 1) <= end2) - gd->bd->bi_dram[i].size = + gd->dram[i].size = end - start + 1; else - gd->bd->bi_dram[i].size = end2 - start; + gd->dram[i].size = end2 - start; dram_bank_sort(i); i++; @@ -670,10 +670,10 @@ int dram_init_banksize(void) /* If error, set to the default value */ if (!i) { - gd->bd->bi_dram[0].start = phys_sdram_1_start; - gd->bd->bi_dram[0].size = phys_sdram_1_size; - gd->bd->bi_dram[1].start = phys_sdram_2_start; - gd->bd->bi_dram[1].size = phys_sdram_2_size; + gd->dram[0].start = phys_sdram_1_start; + gd->dram[0].size = phys_sdram_1_size; + gd->dram[1].start = phys_sdram_2_start; + gd->dram[1].size = phys_sdram_2_size; } return 0; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 498bbe6704f..e600fd6b33e 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -224,11 +224,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx8m_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx8m_mem_map[entry].phys = gd->dram[i].start; + imx8m_mem_map[entry].virt = gd->dram[i].start; + imx8m_mem_map[entry].size = gd->dram[i].size; imx8m_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size); @@ -290,24 +290,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -315,8 +315,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index ccdb949a9da..6d6f3b81aca 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -512,11 +512,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx8ulp_arm64_mem_map[entry].phys = gd->dram[i].start; + imx8ulp_arm64_mem_map[entry].virt = gd->dram[i].start; + imx8ulp_arm64_mem_map[entry].size = gd->dram[i].size; imx8ulp_arm64_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size); @@ -568,24 +568,24 @@ int dram_init_banksize(void) if (ret) return ret; - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_size; + gd->dram[bank].size = sdram_size; } return 0; diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 123c1d51a4d..82b3cdffeea 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -356,11 +356,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx9_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx9_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx9_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx9_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx9_mem_map[entry].phys = gd->dram[i].start; + imx9_mem_map[entry].virt = gd->dram[i].start; + imx9_mem_map[entry].size = gd->dram[i].size; imx9_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx9_mem_map[entry].phys, imx9_mem_map[entry].size); @@ -453,24 +453,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -478,8 +478,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 6576ecefd5f..0c731e76329 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -367,11 +367,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx93_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx93_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx93_mem_map[entry].phys = gd->dram[i].start; + imx93_mem_map[entry].virt = gd->dram[i].start; + imx93_mem_map[entry].size = gd->dram[i].size; imx93_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx93_mem_map[entry].phys, imx93_mem_map[entry].size); @@ -445,24 +445,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -470,8 +470,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; diff --git a/arch/arm/mach-imx/mx5/mx53_dram.c b/arch/arm/mach-imx/mx5/mx53_dram.c index 180a745d435..5f7709e00b0 100644 --- a/arch/arm/mach-imx/mx5/mx53_dram.c +++ b/arch/arm/mach-imx/mx5/mx53_dram.c @@ -35,11 +35,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); return 0; } diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 57ae81c7834..1029c1e4e85 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -375,8 +375,8 @@ void *spl_load_simple_fit_fix_load(const void *fit) #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = imx_ddr_size(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = imx_ddr_size(); return 0; } diff --git a/arch/arm/mach-k3/k3-ddr.c b/arch/arm/mach-k3/k3-ddr.c index 6e3e60cdc86..35c30b1a16f 100644 --- a/arch/arm/mach-k3/k3-ddr.c +++ b/arch/arm/mach-k3/k3-ddr.c @@ -59,8 +59,8 @@ void fixup_memory_node(struct spl_image_info *spl_image) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index be2d9a25bf9..3ebb4294bdd 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -138,8 +138,8 @@ int alleycat5_dram_init_banksize(void) /* * Config single DRAM bank */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index 17525691e68..38d9b40f482 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -256,7 +256,7 @@ int a3700_dram_init_banksize(void) * build_mem_map. */ if (last_end == dram_wins[win].base) { - gd->bd->bi_dram[bank - 1].size += size; + gd->dram[bank - 1].size += size; last_end += size; } else { if (bank == CONFIG_NR_DRAM_BANKS) { @@ -264,8 +264,8 @@ int a3700_dram_init_banksize(void) return -ENOBUFS; } - gd->bd->bi_dram[bank].start = dram_wins[win].base; - gd->bd->bi_dram[bank].size = size; + gd->dram[bank].start = dram_wins[win].base; + gd->dram[bank].size = size; last_end = dram_wins[win].base + size; ++bank; } @@ -276,8 +276,8 @@ int a3700_dram_init_banksize(void) * the rest with zeros. */ for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) { - gd->bd->bi_dram[bank].start = 0; - gd->bd->bi_dram[bank].size = 0; + gd->dram[bank].start = 0; + gd->dram[bank].size = 0; } return 0; diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index fd58551d0e3..af37dfa2252 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -38,16 +38,16 @@ int a8k_dram_init_banksize(void) */ phys_size_t max_bank0_size = SZ_4G - SZ_1G; - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size <= max_bank0_size) { - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return 0; } - gd->bd->bi_dram[0].size = max_bank0_size; + gd->dram[0].size = max_bank0_size; if (CONFIG_NR_DRAM_BANKS > 1) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = gd->ram_size - max_bank0_size; } return 0; diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index c00c6b9b3fc..41eaaa24bd0 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -294,11 +294,11 @@ int dram_init_banksize(void) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = mvebu_sdram_bar(i); - gd->bd->bi_dram[i].size = mvebu_sdram_bs(i); + gd->dram[i].start = mvebu_sdram_bar(i); + gd->dram[i].size = mvebu_sdram_bs(i); /* Clip the banksize to 1GiB if it exceeds the max size */ - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; if (size > MVEBU_SDRAM_SIZE_MAX) mvebu_sdram_bs_set(i, 0x40000000); } diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 8699cf46b67..729533d02d4 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -80,8 +80,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c index 200a08fa5c8..f08a9b263f6 100644 --- a/arch/arm/mach-omap2/omap-cache.c +++ b/arch/arm/mach-omap2/omap-cache.c @@ -53,11 +53,10 @@ void enable_caches(void) void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; - u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + u32 start = gd->dram[bank].start >> MMU_SECTION_SHIFT; + u32 size = gd->dram[bank].size >> MMU_SECTION_SHIFT; u32 end = start + size; debug("%s: bank: %d\n", __func__, bank); diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index 049eedfeb65..67e14d70e92 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -150,10 +150,10 @@ int dram_init_banksize(void) size0 = get_sdr_cs_size(CS0); size1 = get_sdr_cs_size(CS1); - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = size0; + gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->dram[1].size = size1; return 0; } diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 24fae484369..c4187369c29 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -222,10 +222,10 @@ int dram_init_banksize(void) size0 = get_sdr_cs_size(CS0); size1 = get_sdr_cs_size(CS1); - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = size0; + gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->dram[1].size = size1; return 0; } diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index 0130cad7678..e316c2cc40e 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -50,8 +50,8 @@ int dram_init(void) /* This is called after dram_init() so use get_ram_size result */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c index d24419f5daa..f7dc2be6cca 100644 --- a/arch/arm/mach-renesas/memmap-gen3.c +++ b/arch/arm/mach-renesas/memmap-gen3.c @@ -70,8 +70,8 @@ void enable_caches(void) /* Generate entires for DRAM in 32bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) @@ -114,8 +114,8 @@ void enable_caches(void) /* Generate entires for DRAM in 64bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) diff --git a/arch/arm/mach-renesas/memmap-rzg2l.c b/arch/arm/mach-renesas/memmap-rzg2l.c index 3b3c6f7cde9..5981b3c9c4d 100644 --- a/arch/arm/mach-renesas/memmap-rzg2l.c +++ b/arch/arm/mach-renesas/memmap-rzg2l.c @@ -67,8 +67,8 @@ void enable_caches(void) /* Generate entries for DRAM in 32bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index eedce7b9b08..c8de1a21024 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -243,14 +243,14 @@ int arch_cpu_init(void) int rockchip_dram_init_banksize_fixup(struct bd_info *bd) { - size_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size; + size_t ram_top = gd->dram[1].start + gd->dram[1].size; if (ram_top > DRAM_GAP_START) { - bd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start; + gd->dram[1].size = DRAM_GAP_START - gd->dram[1].start; if (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) { - bd->bi_dram[2].start = DRAM_GAP_END; - bd->bi_dram[2].size = ram_top - bd->bi_dram[2].start; + gd->dram[2].start = DRAM_GAP_END; + gd->dram[2].size = ram_top - gd->dram[2].start; } } diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index ea0e3621af7..f0923186fa6 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -171,7 +171,7 @@ static int rockchip_dram_init_banksize(void) /* * Rockchip guaranteed DDR_MEM is ordered so no need to worry about - * bi_dram order. + * dram order. */ for (i = 0, j = 0; i < ddr_info->count; i++, j++) { phys_size_t size = ddr_info->bank[(i + ddr_info->count)]; @@ -261,8 +261,8 @@ static int rockchip_dram_init_banksize(void) * split the region in two, one for before the * reserved memory area and one for after. */ - gd->bd->bi_dram[j].start = start_addr; - gd->bd->bi_dram[j].size = rsrv_start - start_addr; + gd->dram[j].start = start_addr; + gd->dram[j].size = rsrv_start - start_addr; j++; @@ -281,8 +281,8 @@ static int rockchip_dram_init_banksize(void) return -ENOMEM; } - gd->bd->bi_dram[j].start = start_addr; - gd->bd->bi_dram[j].size = size; + gd->dram[j].start = start_addr; + gd->dram[j].size = size; } return 0; @@ -309,15 +309,15 @@ int dram_init_banksize(void) ret); /* Reserve 2M for ATF bl31 */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M; - gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; + gd->dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M; + gd->dram[0].size = top - gd->dram[0].start; /* Add usable memory beyond the blob of space for peripheral near 4GB */ if (ram_top > SZ_4G && top < SZ_4G) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = ram_top - gd->dram[1].start; } else if (ram_top > SZ_4G && top == SZ_4G) { - gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start; + gd->dram[0].size = ram_top - gd->dram[0].start; } #else #ifdef CONFIG_SPL_OPTEE_IMAGE @@ -327,23 +327,23 @@ int dram_init_banksize(void) TRUST_PARAMETER_OFFSET); if (tos_parameter->tee_mem.flags == 1) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = tos_parameter->tee_mem.phy_addr - CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + + gd->dram[1].start = tos_parameter->tee_mem.phy_addr + tos_parameter->tee_mem.size; - gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; + gd->dram[1].size = top - gd->dram[1].start; } else { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x8400000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x8400000; /* Reserve 32M for OPTEE with TA */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE - + gd->bd->bi_dram[0].size + 0x2000000; - gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; + gd->dram[1].start = CFG_SYS_SDRAM_BASE + + gd->dram[0].size + 0x2000000; + gd->dram[1].size = top - gd->dram[1].start; } #else - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = top - gd->dram[0].start; #endif #endif diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 829a0109ac7..35735f1551c 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -73,19 +73,19 @@ static int ddr_bank_cmp(const void *v1, const void *v2) } /* This has to be done post-relocation since gd->bd isn't preserved */ -static void qcom_configure_bi_dram(void) +static void qcom_configure_dram(void) { int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start; - gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size; + gd->dram[i].start = prevbl_ddr_banks[i].start; + gd->dram[i].size = prevbl_ddr_banks[i].size; } } int dram_init_banksize(void) { - qcom_configure_bi_dram(); + qcom_configure_dram(); return 0; } @@ -594,15 +594,15 @@ static void build_mem_map(void) */ mem_map[0].phys = 0x1000; mem_map[0].virt = mem_map[0].phys; - mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys; + mem_map[0].size = gd->dram[0].start - mem_map[0].phys; mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; - for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) { - mem_map[i].phys = gd->bd->bi_dram[j].start; + for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->dram[j].size; i++, j++) { + mem_map[i].phys = gd->dram[j].start; mem_map[i].virt = mem_map[i].phys; - mem_map[i].size = gd->bd->bi_dram[j].size; + mem_map[i].size = gd->dram[j].size; mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \ PTE_BLOCK_INNER_SHARE; } diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 4d7f0b9a79c..b202ca258bc 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -202,11 +202,10 @@ void board_prep_linux(struct bootm_headers *images) void lmb_arch_add_memory(void) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (bd->bi_dram[i].size) - lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size); + if (gd->dram[i].size) + lmb_add(gd->dram[i].start, gd->dram[i].size); } } #endif diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 7e0f3875b7c..338f73d6e73 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -246,7 +246,6 @@ int qspi_flash_software_reset(void) void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; u32 start, size; int i; @@ -261,11 +260,11 @@ void dram_bank_mmu_setup(int bank) * The default implementation of this function allows the DRAM dcache * to be enabled only after relocation. However, to speed up ECC * initialization, we want to be able to enable DRAM dcache before - * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram + * relocation, so we don't check GD_FLG_RELOC (this assumes gd->dram * is set first). */ - start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + start = gd->dram[bank].start >> MMU_SECTION_SHIFT; + size = gd->dram[bank].size >> MMU_SECTION_SHIFT; for (i = start; i < start + size; i++) set_section_dcache(i, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 835eaf48dfa..76c324b55ae 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -825,8 +825,8 @@ static int init_device(struct stm32prog_data *data, dev->mtd = mtd; break; case STM32PROG_RAM: - first_addr = gd->bd->bi_dram[0].start; - last_addr = first_addr + gd->bd->bi_dram[0].size; + first_addr = gd->dram[0].start; + last_addr = first_addr + gd->dram[0].size; dev->erase_size = 1; break; default: diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 252aef1852e..4d81c70b230 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -52,7 +52,6 @@ u32 get_bootauth(void) */ void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; phys_addr_t start; phys_addr_t addr; @@ -67,9 +66,9 @@ void dram_bank_mmu_setup(int bank) size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); #endif } else if (gd->flags & GD_FLG_RELOC) { - /* bd->bi_dram is available only after relocation */ - start = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; + /* gd->dram is available only after relocation */ + start = gd->dram[bank].start; + size = gd->dram[bank].size; use_lmb = true; } else { /* mark cacheable and executable the beggining of the DDR */ diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 396851c5bd8..1763f95ace4 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -393,18 +393,18 @@ int dram_init_banksize(void) /* fall back to default DRAM bank size computation */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = usable_ram_size_below_4g(); #ifdef CONFIG_PHYS_64BIT if (gd->ram_size > SZ_2G) { - gd->bd->bi_dram[1].start = 0x100000000; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = 0x100000000; + gd->dram[1].size = gd->ram_size - SZ_2G; } else #endif { - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[1].start = 0; + gd->dram[1].size = 0; } return 0; @@ -418,7 +418,7 @@ int dram_init_banksize(void) * carve-out, as mentioned above. * * This function is called before dram_init_banksize(), so we can't simply - * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. + * return gd->dram[1].start + gd->dram[1].size. */ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c index e2342b2aece..ff15fa28eb5 100644 --- a/arch/arm/mach-tegra/cboot.c +++ b/arch/arm/mach-tegra/cboot.c @@ -185,8 +185,8 @@ int cboot_dram_init_banksize(void) } for (i = 0; i < ram_bank_count; i++) { - gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; - gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; + gd->dram[i].start = tegra_mem_map[1 + i].virt; + gd->dram[i].size = tegra_mem_map[1 + i].size; } return 0; diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 0e1164a2680..ae495808dec 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -280,9 +280,9 @@ int dram_init_banksize(void) return ret; for (i = 0; i < ARRAY_SIZE(dram_map); i++) { - if (i < ARRAY_SIZE(gd->bd->bi_dram)) { - gd->bd->bi_dram[i].start = dram_map[i].base; - gd->bd->bi_dram[i].size = dram_map[i].size; + if (i < ARRAY_SIZE(gd->dram)) { + gd->dram[i].start = dram_map[i].base; + gd->dram[i].size = dram_map[i].size; } if (!dram_map[i].size) diff --git a/arch/arm/mach-uniphier/fdt-fixup.c b/arch/arm/mach-uniphier/fdt-fixup.c index dfa32fdd48b..4e1de15cd98 100644 --- a/arch/arm/mach-uniphier/fdt-fixup.c +++ b/arch/arm/mach-uniphier/fdt-fixup.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include #include @@ -20,6 +21,7 @@ */ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd) { + DECLARE_GLOBAL_DATA_PTR; unsigned long rsv_addr; const unsigned long rsv_size = 64; int i, ret; @@ -28,11 +30,11 @@ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd) uniphier_get_soc_id() != UNIPHIER_LD20_ID) return 0; - for (i = 0; i < ARRAY_SIZE(bd->bi_dram); i++) { - if (!bd->bi_dram[i].size) + for (i = 0; i < ARRAY_SIZE(gd->dram); i++) { + if (!gd->dram[i].size) continue; - rsv_addr = bd->bi_dram[i].start + bd->bi_dram[i].size; + rsv_addr = gd->dram[i].start + gd->dram[i].size; rsv_addr -= rsv_size; ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c index d088e440f63..78ead1f45f6 100644 --- a/arch/arm/mach-versal-net/cpu.c +++ b/arch/arm/mach-versal-net/cpu.c @@ -69,12 +69,12 @@ void mem_map_fill(void) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; - versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; - versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; - versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].virt = gd->dram[i].start; + versal_mem_map[banks].phys = gd->dram[i].start; + versal_mem_map[banks].size = gd->dram[i].size; versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 363ce3007fd..0dd5cc153c4 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -82,21 +82,21 @@ void mem_map_fill(void) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; #if defined(CONFIG_VERSAL_NO_DDR) - if (gd->bd->bi_dram[i].start < 0x80000000UL || - gd->bd->bi_dram[i].start > 0x100000000UL) { + if (gd->dram[i].start < 0x80000000UL || + gd->dram[i].start > 0x100000000UL) { printf("Ignore caches over %llx/%llx\n", - gd->bd->bi_dram[i].start, - gd->bd->bi_dram[i].size); + gd->dram[i].start, + gd->dram[i].size); continue; } #endif - versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; - versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; - versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].virt = gd->dram[i].start; + versal_mem_map[banks].phys = gd->dram[i].start; + versal_mem_map[banks].size = gd->dram[i].size; versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index a81609cdec7..f65c231bdab 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -109,7 +109,7 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks) * fill_bd_mem_info() - Copy DRAM banks from mem_map to bd_info * * Transfers DRAM bank information from the global versal2_mem_map[] - * array to bd->bi_dram[] for passing memory configuration to the + * array to gd->dram[] for passing memory configuration to the * Linux kernel via boot parameters (ATAGS/FDT). Each bank's physical * address and size are copied. * @@ -119,15 +119,14 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks) */ void fill_bd_mem_info(void) { - struct bd_info *bd = gd->bd; int banks = VERSAL2_MEM_MAP_USED; for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { if (!versal2_mem_map[banks].size) break; - bd->bi_dram[i].start = versal2_mem_map[banks].phys; - bd->bi_dram[i].size = versal2_mem_map[banks].size; + gd->dram[i].start = versal2_mem_map[banks].phys; + gd->dram[i].size = versal2_mem_map[banks].size; banks++; } } diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 5f194aaff9a..3dc47e5d48e 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -92,12 +92,12 @@ void mem_map_fill(void) #if !defined(CONFIG_ZYNQMP_NO_DDR) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; - zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start; - zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start; - zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size; + zynqmp_mem_map[banks].virt = gd->dram[i].start; + zynqmp_mem_map[banks].phys = gd->dram[i].start; + zynqmp_mem_map[banks].size = gd->dram[i].size; zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 5b1311d8b5b..817728aa569 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -41,8 +41,8 @@ int dram_init(void) * No DDR init yet -> run in L2 cache */ gd->ram_size = (4 << 20); - gd->bd->bi_dram[0].size = gd->ram_size; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = gd->ram_size; + gd->dram[1].size = 0; } return 0; diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c index cc1e903c9dd..2893bc6b99a 100644 --- a/arch/riscv/cpu/k1/dram.c +++ b/arch/riscv/cpu/k1/dram.c @@ -56,12 +56,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) { - gd->bd->bi_dram[1].start = 0x100000000; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = 0x100000000; + gd->dram[1].size = gd->ram_size - SZ_2G; } return 0; @@ -82,8 +82,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - start[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + start[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index 1668b58d3fb..460013f933b 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -131,8 +131,8 @@ SPL_LOAD_IMAGE_METHOD("sandbox_image", 7, BOOT_DEVICE_BOARD, load_from_image); int dram_init_banksize(void) { /* These are necessary so TFTP can use LMBs to check its load address */ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); return 0; } diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index cc1edd7badd..81604ee12fb 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -91,8 +91,8 @@ int dram_init_banksize(void) struct memrange *memrange = &lib_sysinfo.memrange[i]; if (memrange->type == CB_MEM_RAM) { - gd->bd->bi_dram[j].start = memrange->base; - gd->bd->bi_dram[j].size = memrange->size; + gd->dram[j].start = memrange->base; + gd->dram[j].size = memrange->size; j++; if (j >= CONFIG_NR_DRAM_BANKS) break; diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 6845ce72ff9..b86d50b2cab 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -123,8 +123,8 @@ int dram_init_banksize(void) if (desc->type != EFI_CONVENTIONAL_MEMORY || (desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20) continue; - gd->bd->bi_dram[num_banks].start = desc->physical_start; - gd->bd->bi_dram[num_banks].size = desc->num_pages << + gd->dram[num_banks].start = desc->physical_start; + gd->dram[num_banks].size = desc->num_pages << EFI_PAGE_SHIFT; num_banks++; } diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c index 6fe40071140..e09fce8bb1b 100644 --- a/arch/x86/cpu/efi/sdram.c +++ b/arch/x86/cpu/efi/sdram.c @@ -24,8 +24,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = efi_get_ram_base(); - gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE; + gd->dram[0].start = efi_get_ram_base(); + gd->dram[0].size = CONFIG_EFI_RAM_SIZE; return 0; } diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index baa1f0e32d6..11ce97b5143 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -67,8 +67,8 @@ void mrc_common_dram_init_banksize(void) if (area->start >= 1ULL << 32) continue; - gd->bd->bi_dram[num_banks].start = area->start; - gd->bd->bi_dram[num_banks].size = area->size; + gd->dram[num_banks].start = area->start; + gd->dram[num_banks].size = area->size; num_banks++; } } diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c index d20c9a2a379..a5e81dfada5 100644 --- a/arch/x86/cpu/ivybridge/sdram_nop.c +++ b/arch/x86/cpu/ivybridge/sdram_nop.c @@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { gd->ram_size = 1ULL << 31; - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index ba3638e6acc..3cba04f2c3e 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -69,13 +69,13 @@ int dram_init_banksize(void) { u64 high_mem_size; - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = qemu_get_low_memory_size(); + gd->dram[0].start = 0; + gd->dram[0].size = qemu_get_low_memory_size(); high_mem_size = qemu_get_high_memory_size(); if (high_mem_size) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = high_mem_size; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = high_mem_size; } return 0; diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 34e576940d4..34fdb7e026a 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -169,8 +169,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c index 75ca5273625..5aa4f6d3e07 100644 --- a/arch/x86/cpu/slimbootloader/sdram.c +++ b/arch/x86/cpu/slimbootloader/sdram.c @@ -129,8 +129,8 @@ int dram_init_banksize(void) return 0; /* simply use a single bank to have whole size for now */ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index 6192f2296b8..6ce96b0569b 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -160,8 +160,8 @@ static int sfi_get_bank_size(void) if (mentry->type != SFI_MEM_CONV) continue; - gd->bd->bi_dram[bank].start = mentry->phys_start; - gd->bd->bi_dram[bank].size = mentry->pages << 12; + gd->dram[bank].start = mentry->phys_start; + gd->dram[bank].size = mentry->pages << 12; bank++; } diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index cde4fbf3557..e054f42fa86 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -43,14 +43,13 @@ void bootm_announce_and_cleanup(void) #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL) int arch_fixup_memory_node(void *blob) { - struct bd_info *bd = gd->bd; int bank; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 730721dc176..a45e4060ef2 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -64,8 +64,8 @@ int dram_init_banksize(void) update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2); if (!ll_boot_init()) { - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; if (update_mtrr) mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); @@ -89,21 +89,21 @@ int dram_init_banksize(void) mtrr_top = max(mtrr_top, res_desc->phys_start + res_desc->len); } else { - gd->bd->bi_dram[bank].start = res_desc->phys_start; - gd->bd->bi_dram[bank].size = res_desc->len; + gd->dram[bank].start = res_desc->phys_start; + gd->dram[bank].size = res_desc->len; if (update_mtrr) mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start, res_desc->len); log_debug("ram %llx %llx\n", - gd->bd->bi_dram[bank].start, - gd->bd->bi_dram[bank].size); + gd->dram[bank].start, + gd->dram[bank].size); } } /* Add the memory below 4GB */ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = low_end; + gd->dram[0].start = 0; + gd->dram[0].size = low_end; /* * Set up an MTRR to the top of low, reserved memory. This is necessary @@ -184,7 +184,7 @@ unsigned int install_e820_map(unsigned int max_entries, #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB) int handoff_arch_save(struct spl_handoff *ho) { - ho->arch.usable_ram_top = gd->bd->bi_dram[0].size; + ho->arch.usable_ram_top = gd->dram[0].size; ho->arch.hob_list = gd->arch.hob_list; return 0; diff --git a/board/CZ.NIC/turris_1x/turris_1x.c b/board/CZ.NIC/turris_1x/turris_1x.c index 2f9557a4170..32535ed6ee0 100644 --- a/board/CZ.NIC/turris_1x/turris_1x.c +++ b/board/CZ.NIC/turris_1x/turris_1x.c @@ -42,9 +42,9 @@ int dram_init_banksize(void) static_assert(CONFIG_NR_DRAM_BANKS >= 3); - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); - size -= gd->bd->bi_dram[0].size; + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); + size -= gd->dram[0].size; /* Note: This address space is not mapped via TLB entries in U-Boot */ @@ -68,16 +68,16 @@ int dram_init_banksize(void) if (size > 0) { /* Free space between PCIe bus 3 MEM and NOR */ - gd->bd->bi_dram[1].start = 0xc0200000; - gd->bd->bi_dram[1].size = min(size, 0xef000000 - gd->bd->bi_dram[1].start); - size -= gd->bd->bi_dram[1].size; + gd->dram[1].start = 0xc0200000; + gd->dram[1].size = min(size, 0xef000000 - gd->dram[1].start); + size -= gd->dram[1].size; } if (size > 0) { /* Free space between NOR and NAND */ - gd->bd->bi_dram[2].start = 0xf0000000; - gd->bd->bi_dram[2].size = min(size, 0xff800000 - gd->bd->bi_dram[2].start); - size -= gd->bd->bi_dram[2].size; + gd->dram[2].start = 0xf0000000; + gd->dram[2].size = min(size, 0xff800000 - gd->dram[2].start); + size -= gd->dram[2].size; } #else puts("\n\n!!! TODO: fix sdcard >2GB RAM\n\n\n"); @@ -231,8 +231,8 @@ void ft_memory_setup(void *blob, struct bd_info *bd) if (!env_get("bootm_low") && !env_get("bootm_size")) { for (count = 0; count < CONFIG_NR_DRAM_BANKS; count++) { - start[count] = gd->bd->bi_dram[count].start; - size[count] = gd->bd->bi_dram[count].size; + start[count] = gd->dram[count].start; + size[count] = gd->dram[count].size; if (!size[count]) break; } @@ -452,13 +452,13 @@ static void recalculate_used_pcie_mem(void) size = gd->ram_size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size -= gd->bd->bi_dram[i].size; + size -= gd->dram[i].size; if (size == 0) return; e = find_law_by_addr_id(CFG_SYS_PCIE3_MEM_PHYS, LAW_TRGT_IF_PCIE_3); - if (e.index < 0 && gd->bd->bi_dram[1].size > 0) { + if (e.index < 0 && gd->dram[1].size > 0) { /* * If there is no LAW for PCIe 3 MEM then 3rd PCIe controller * is inactive, which is the case for Turris 1.0 boards. So @@ -471,8 +471,8 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(bank_size, ""); printf(" of PCIe 3 MEM for DDR RAM\n"); - gd->bd->bi_dram[1].start -= bank_size; - gd->bd->bi_dram[1].size += bank_size; + gd->dram[1].start -= bank_size; + gd->dram[1].size += bank_size; size -= bank_size; if (size == 0) return; @@ -534,9 +534,9 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(free_size2, ""); printf(" of PCIe 2 MEM for DDR RAM\n"); - gd->bd->bi_dram[i].start = free_start2; - gd->bd->bi_dram[i].size = min(size, free_size2); - size -= gd->bd->bi_dram[i].start; + gd->dram[i].start = free_start2; + gd->dram[i].size = min(size, free_size2); + size -= gd->dram[i].start; i++; if (size == 0) return; @@ -548,9 +548,9 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(free_size1, ""); printf(" of PCIe 1 MEM for DDR RAM\n"); - gd->bd->bi_dram[i].start = free_start1; - gd->bd->bi_dram[i].size = min(size, free_size1); - size -= gd->bd->bi_dram[i].size; + gd->dram[i].start = free_start1; + gd->dram[i].size = min(size, free_size1); + size -= gd->dram[i].size; i++; if (size == 0) return; diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c index 16d0e679c3e..eb0f9c06849 100644 --- a/board/armltd/corstone1000/corstone1000.c +++ b/board/armltd/corstone1000/corstone1000.c @@ -86,8 +86,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index eaf87e3bfe3..6cd24bf25fb 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -137,7 +137,7 @@ int misc_init_r (void) int dram_init (void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; #ifdef CONFIG_CM_SPD_DETECT { extern void dram_query(void); @@ -170,7 +170,7 @@ extern void dram_query(void); PHYS_SDRAM_1_SIZE); #endif /* CM_SPD_DETECT */ /* We only have one bank of RAM, set it to whatever was detected */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index 12bb6defab2..057e916ab1b 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -89,9 +89,9 @@ void build_mem_map(void) * The first node is for I/O device, start from node 1 for * updating DRAM info. */ - mem_map[i + 1].virt = gd->bd->bi_dram[i].start; - mem_map[i + 1].phys = gd->bd->bi_dram[i].start; - mem_map[i + 1].size = gd->bd->bi_dram[i].size; + mem_map[i + 1].virt = gd->dram[i].start; + mem_map[i + 1].phys = gd->dram[i].start; + mem_map[i + 1].size = gd->dram[i].size; mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; } diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 3833af59b09..87e53f64e06 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -79,11 +79,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); return 0; diff --git a/board/atmel/common/video_display.c b/board/atmel/common/video_display.c index 77188820581..7cb492b2da6 100644 --- a/board/atmel/common/video_display.c +++ b/board/atmel/common/video_display.c @@ -40,7 +40,7 @@ int at91_video_show_board_info(void) dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - dram_size += gd->bd->bi_dram[i].size; + dram_size += gd->dram[i].size; nand_size = 0; #ifdef CONFIG_NAND_ATMEL diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c index 43797d625e9..b19ae3b4b03 100644 --- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c +++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c @@ -66,7 +66,7 @@ int misc_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; board_leds_init(); diff --git a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c index 364b6a3e24b..5c35239a90a 100644 --- a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c +++ b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c @@ -45,7 +45,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index 858061bf9f9..33ae6a76bf7 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -64,7 +64,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 19341d325bd..0e2d5592753 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -58,7 +58,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c index 8759ff6f01a..1a17db1bd5b 100644 --- a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c +++ b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c @@ -65,7 +65,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index c0862f58606..b48e8fe7697 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -63,7 +63,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c index 764c8f035c9..cdf2793b643 100644 --- a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c +++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c @@ -52,7 +52,7 @@ void board_debug_uart_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; board_leds_init(); diff --git a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c index b05c9754c96..02543d8e99f 100644 --- a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c +++ b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { // Address of boot parameters - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/axiado/scm3005/scm3005.c b/board/axiado/scm3005/scm3005.c index 4643ba4a55c..b2df6d89cd8 100644 --- a/board/axiado/scm3005/scm3005.c +++ b/board/axiado/scm3005/scm3005.c @@ -96,8 +96,8 @@ int dram_init(void) */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index bb2f1e4f62a..2683f46f41c 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -176,8 +176,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M); - gd->bd->bi_dram[0].size = SZ_16M; + gd->dram[0].start = (BCM_NS3_MEM_END - SZ_16M); + gd->dram[0].size = SZ_16M; return 0; } diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index e20350dc5d5..5bc4d3248bd 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -666,34 +666,34 @@ int misc_init_r(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[1].start = PHYS_SDRAM_2; switch (gd->ram_size) { case 0x10000000: /* DDR_16BIT_256MB */ - gd->bd->bi_dram[0].size = 0x10000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x10000000; + gd->dram[1].size = 0; break; case 0x20000000: /* DDR_32BIT_512MB */ - gd->bd->bi_dram[0].size = 0x20000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x20000000; + gd->dram[1].size = 0; break; case 0x40000000: if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */ - gd->bd->bi_dram[0].size = 0x20000000; - gd->bd->bi_dram[1].size = 0x20000000; + gd->dram[0].size = 0x20000000; + gd->dram[1].size = 0x20000000; } else { /* DDR_64BIT_1GB */ - gd->bd->bi_dram[0].size = 0x40000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x40000000; + gd->dram[1].size = 0; } break; case 0x80000000: /* DDR_64BIT_2GB */ - gd->bd->bi_dram[0].size = 0x40000000; - gd->bd->bi_dram[1].size = 0x40000000; + gd->dram[0].size = 0x40000000; + gd->dram[1].size = 0x40000000; break; case 0xEFF00000: /* DDR_64BIT_4GB */ - gd->bd->bi_dram[0].size = 0x70000000; - gd->bd->bi_dram[1].size = 0x7FF00000; + gd->dram[0].size = 0x70000000; + gd->dram[1].size = 0x7FF00000; break; } diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c index 9fea4f86d5a..33f7ec6d048 100644 --- a/board/elgin/elgin_rv1108/elgin_rv1108.c +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -66,8 +66,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = 0x60000000; - gd->bd->bi_dram[0].size = 0x8000000; + gd->dram[0].start = 0x60000000; + gd->dram[0].size = 0x8000000; return 0; } diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index dce69abdfd1..3d76c936073 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -141,8 +141,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index eb10cd5143d..5e560a7f927 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -532,17 +532,17 @@ int dram_init_banksize(void) /* set global data memory */ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100; - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; /* Number of Row: 14 bits */ if ((reg_val >> 28) == 14) - gd->bd->bi_dram[0].size -= 0x20000000; + gd->dram[0].size -= 0x20000000; /* Number of Memory Chips */ if ((reg_val & 0x3) > 1) { - gd->bd->bi_dram[1].start = 0x80000000; - gd->bd->bi_dram[1].size = 0x40000000; + gd->dram[1].start = 0x80000000; + gd->dram[1].size = 0x40000000; } return 0; } diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index cb9b88a1a58..d3a385bf6b7 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -71,11 +71,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = mx53_dram_size[0]; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = mx53_dram_size[0]; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = mx53_dram_size[1]; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = mx53_dram_size[1]; return 0; } diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 5e60ab9d7b7..ba0465cf96f 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -456,23 +456,23 @@ int dram_init_banksize(void) * 0x3e00,0000 - 0x3fff,ffff: OP-TEE */ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = 0x05e00000; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = 0x05e00000; - gd->bd->bi_dram[1].start = 0x05f00000; - gd->bd->bi_dram[1].size = 0x00001000; + gd->dram[1].start = 0x05f00000; + gd->dram[1].size = 0x00001000; - gd->bd->bi_dram[2].start = 0x05f02000; - gd->bd->bi_dram[2].size = 0x00efd000; + gd->dram[2].start = 0x05f02000; + gd->dram[2].size = 0x00efd000; - gd->bd->bi_dram[3].start = 0x06e00000; - gd->bd->bi_dram[3].size = 0x0060f000; + gd->dram[3].start = 0x06e00000; + gd->dram[3].size = 0x0060f000; - gd->bd->bi_dram[4].start = 0x07410000; - gd->bd->bi_dram[4].size = 0x1aaf0000; + gd->dram[4].start = 0x07410000; + gd->dram[4].size = 0x1aaf0000; - gd->bd->bi_dram[5].start = 0x22000000; - gd->bd->bi_dram[5].size = 0x1c000000; + gd->dram[5].start = 0x22000000; + gd->dram[5].size = 0x1c000000; return 0; } diff --git a/board/hisilicon/hikey960/hikey960.c b/board/hisilicon/hikey960/hikey960.c index fb56762fff6..e7908d4c048 100644 --- a/board/hisilicon/hikey960/hikey960.c +++ b/board/hisilicon/hikey960/hikey960.c @@ -74,8 +74,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c index c3ea080ff75..dbab67d6f65 100644 --- a/board/hisilicon/poplar/poplar.c +++ b/board/hisilicon/poplar/poplar.c @@ -87,8 +87,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET; - gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start; + gd->dram[0].start = KERNEL_TEXT_OFFSET; + gd->dram[0].size = gd->ram_size - gd->dram[0].start; return 0; } diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c index efb7b49cbe0..07668bae7a9 100644 --- a/board/k+p/kp_imx53/kp_imx53.c +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -39,8 +39,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c index 51938a1b4d8..e37d4e767db 100644 --- a/board/keymile/pg-wcom-ls102xa/ddr.c +++ b/board/keymile/pg-wcom-ls102xa/ddr.c @@ -84,8 +84,8 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 8a9502037fb..ce778bc0849 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -175,8 +175,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < nbanks; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } fdt_fixup_memory_banks(blob, base, size, nbanks); diff --git a/board/kontron/sl28/spl_atf.c b/board/kontron/sl28/spl_atf.c index 0710316a48b..cc741dea504 100644 --- a/board/kontron/sl28/spl_atf.c +++ b/board/kontron/sl28/spl_atf.c @@ -36,9 +36,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - dram_regions_info.region[i].addr = gd->bd->bi_dram[i].start; - dram_regions_info.region[i].size = gd->bd->bi_dram[i].size; - dram_regions_info.total_dram_size += gd->bd->bi_dram[i].size; + dram_regions_info.region[i].addr = gd->dram[i].start; + dram_regions_info.region[i].size = gd->dram[i].size; + dram_regions_info.total_dram_size += gd->dram[i].size; } bl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry, diff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c index e1ff041c54f..ba922b43064 100644 --- a/board/liebherr/btt/btt.c +++ b/board/liebherr/btt/btt.c @@ -239,7 +239,7 @@ int spl_start_uboot(void) static const char *get_board_name(void) { - if (gd->bd->bi_dram[0].size == SZ_128M) + if (gd->dram[0].size == SZ_128M) return STR_BTTC; return STR_BTT3; diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index fc76d5765fa..5e76942783f 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -69,11 +69,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = mx53_dram_size[0]; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = mx53_dram_size[0]; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = mx53_dram_size[1]; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = mx53_dram_size[1]; return 0; } diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 05c4dd187fe..68d516c7db8 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -57,7 +57,7 @@ int dram_init_banksize(void) { phys_size_t ram_size = gd->ram_size; - gd->bd->bi_dram[0].start = 0; + gd->dram[0].start = 0; #if defined(CONFIG_SYS_MEM_TOP_HIDE) ram_size += CONFIG_SYS_MEM_TOP_HIDE; @@ -69,25 +69,25 @@ int dram_init_banksize(void) case DRAM_1GB_SIZE: case DRAM_2GB_ECC_SIZE: case DRAM_2GB_SIZE: - gd->bd->bi_dram[0].size = ram_size; - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = ram_size; + gd->dram[1].start = 0; + gd->dram[1].size = 0; break; case DRAM_4GB_ECC_SIZE: - gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; - gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; - gd->bd->bi_dram[1].size = DRAM_2GB_SIZE - + gd->dram[0].size = DRAM_2GB_SIZE; + gd->dram[1].start = DRAM_4GB_SIZE; + gd->dram[1].size = DRAM_2GB_SIZE - (DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE); break; case DRAM_4GB_SIZE: - gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; - gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; - gd->bd->bi_dram[1].size = DRAM_2GB_SIZE; + gd->dram[0].size = DRAM_2GB_SIZE; + gd->dram[1].start = DRAM_4GB_SIZE; + gd->dram[1].size = DRAM_2GB_SIZE; break; default: - gd->bd->bi_dram[0].size = DRAM_1GB_SIZE; - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = DRAM_1GB_SIZE; + gd->dram[1].start = 0; + gd->dram[1].size = 0; break; } diff --git a/board/nxp/imxrt1020-evk/imxrt1020-evk.c b/board/nxp/imxrt1020-evk/imxrt1020-evk.c index 11dbef84688..6843b33679d 100644 --- a/board/nxp/imxrt1020-evk/imxrt1020-evk.c +++ b/board/nxp/imxrt1020-evk/imxrt1020-evk.c @@ -73,7 +73,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/imxrt1050-evk/imxrt1050-evk.c b/board/nxp/imxrt1050-evk/imxrt1050-evk.c index 056489932ac..19d068fc626 100644 --- a/board/nxp/imxrt1050-evk/imxrt1050-evk.c +++ b/board/nxp/imxrt1050-evk/imxrt1050-evk.c @@ -78,7 +78,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/imxrt1170-evk/imxrt1170-evk.c b/board/nxp/imxrt1170-evk/imxrt1170-evk.c index 047aea8181a..3afd5ae2136 100644 --- a/board/nxp/imxrt1170-evk/imxrt1170-evk.c +++ b/board/nxp/imxrt1170-evk/imxrt1170-evk.c @@ -73,7 +73,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/ls1021aqds/ddr.c b/board/nxp/ls1021aqds/ddr.c index fd897e832c8..8d07f6110ce 100644 --- a/board/nxp/ls1021aqds/ddr.c +++ b/board/nxp/ls1021aqds/ddr.c @@ -192,8 +192,8 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c index 196e25931f3..e1e83137f4d 100644 --- a/board/nxp/ls1028a/ls1028a.c +++ b/board/nxp/ls1028a/ls1028a.c @@ -149,7 +149,7 @@ int board_early_init_f(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -202,10 +202,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/ls1043aqds/ls1043aqds.c b/board/nxp/ls1043aqds/ls1043aqds.c index 0f115c16232..dba93add698 100644 --- a/board/nxp/ls1043aqds/ls1043aqds.c +++ b/board/nxp/ls1043aqds/ls1043aqds.c @@ -542,10 +542,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 reg; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1043ardb/ls1043ardb.c b/board/nxp/ls1043ardb/ls1043ardb.c index bba041065b5..678c529cf55 100644 --- a/board/nxp/ls1043ardb/ls1043ardb.c +++ b/board/nxp/ls1043ardb/ls1043ardb.c @@ -305,10 +305,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046afrwy/ls1046afrwy.c b/board/nxp/ls1046afrwy/ls1046afrwy.c index 8889c24f1f0..6c35c0a4347 100644 --- a/board/nxp/ls1046afrwy/ls1046afrwy.c +++ b/board/nxp/ls1046afrwy/ls1046afrwy.c @@ -198,10 +198,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046aqds/ls1046aqds.c b/board/nxp/ls1046aqds/ls1046aqds.c index 679b0b2235f..ddd9993986f 100644 --- a/board/nxp/ls1046aqds/ls1046aqds.c +++ b/board/nxp/ls1046aqds/ls1046aqds.c @@ -426,10 +426,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 reg; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046ardb/ls1046ardb.c b/board/nxp/ls1046ardb/ls1046ardb.c index 83b280f7646..6677e271029 100644 --- a/board/nxp/ls1046ardb/ls1046ardb.c +++ b/board/nxp/ls1046ardb/ls1046ardb.c @@ -171,10 +171,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1088a/ls1088a.c b/board/nxp/ls1088a/ls1088a.c index 5783dd8a403..1b477e83676 100644 --- a/board/nxp/ls1088a/ls1088a.c +++ b/board/nxp/ls1088a/ls1088a.c @@ -830,7 +830,7 @@ int board_init(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -959,8 +959,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } #ifdef CONFIG_RESV_RAM diff --git a/board/nxp/ls2080aqds/ls2080aqds.c b/board/nxp/ls2080aqds/ls2080aqds.c index aba0560181a..325dc817aaf 100644 --- a/board/nxp/ls2080aqds/ls2080aqds.c +++ b/board/nxp/ls2080aqds/ls2080aqds.c @@ -253,12 +253,12 @@ int misc_init_r(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->dram[2].size) { puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); + print_size(gd->dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } #endif @@ -302,10 +302,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/ls2080ardb/ls2080ardb.c b/board/nxp/ls2080ardb/ls2080ardb.c index d08598d1c62..9dec818280b 100644 --- a/board/nxp/ls2080ardb/ls2080ardb.c +++ b/board/nxp/ls2080ardb/ls2080ardb.c @@ -359,12 +359,12 @@ int misc_init_r(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->dram[2].size) { puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); + print_size(gd->dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } #endif @@ -487,10 +487,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) size = calloc(total_memory_banks, sizeof(u64)); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/lx2160a/lx2160a.c b/board/nxp/lx2160a/lx2160a.c index b7a6ccf46aa..10729dfaf24 100644 --- a/board/nxp/lx2160a/lx2160a.c +++ b/board/nxp/lx2160a/lx2160a.c @@ -573,7 +573,7 @@ void detail_board_ddr_info(void) puts("\nDDR "); for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - ddr_size += gd->bd->bi_dram[i].size; + ddr_size += gd->dram[i].size; print_size(ddr_size, ""); print_ddr_info(0); } @@ -808,8 +808,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the three GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } #ifdef CONFIG_RESV_RAM diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 3cdcbf2ecc9..6df521d789f 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -93,7 +93,7 @@ int dram_init_banksize(void) { u8 ram_size; - memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS); if (!IS_ENABLED(CONFIG_CPU_V7R)) return fdtdec_setup_memory_banksize(); @@ -101,34 +101,34 @@ int dram_init_banksize(void) ram_size = phytec_get_am62_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x40000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x40000000; gd->ram_size = 0x40000000; break; case EEPROM_RAM_SIZE_2GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; break; case EEPROM_RAM_SIZE_4GB: /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR upper region */ - gd->bd->bi_dram[1].start = 0x880000000; - gd->bd->bi_dram[1].size = 0x80000000; + gd->dram[1].start = 0x880000000; + gd->dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif break; default: /* Continue with default 2GB setup */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; printf("DDR size %d is not supported\n", ram_size); } @@ -186,8 +186,8 @@ int do_board_detect(void) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } ret = fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c index 114aa217023..5e077872152 100644 --- a/board/phytec/phycore_am64x/phycore-am64x.c +++ b/board/phytec/phycore_am64x/phycore-am64x.c @@ -66,7 +66,7 @@ int dram_init_banksize(void) { u8 ram_size; - memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS); if (!IS_ENABLED(CONFIG_CPU_V7R)) return fdtdec_setup_memory_banksize(); @@ -74,21 +74,21 @@ int dram_init_banksize(void) ram_size = phytec_get_am64_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x40000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x40000000; gd->ram_size = 0x40000000; break; case EEPROM_RAM_SIZE_2GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; break; default: /* Continue with default 2GB setup */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; printf("DDR size %d is not supported\n", ram_size); } @@ -109,8 +109,8 @@ int do_board_detect(void) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } return fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c index 9fc63febdac..a738e3542e2 100644 --- a/board/phytium/durian/durian.c +++ b/board/phytium/durian/durian.c @@ -31,8 +31,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c index 6824454cdf4..421e193e730 100644 --- a/board/phytium/pe2201/pe2201.c +++ b/board/phytium/pe2201/pe2201.c @@ -44,8 +44,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index b0a1484c0fa..885c660a289 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -356,9 +356,9 @@ int dram_init_banksize(void) /* Update gd->ram_size to reflect total RAM across all banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (gd->bd->bi_dram[i].size == 0) + if (gd->dram[i].size == 0) break; - total_size += gd->bd->bi_dram[i].size; + total_size += gd->dram[i].size; } gd->ram_size = total_size; diff --git a/board/renesas/common/rcar64-common.c b/board/renesas/common/rcar64-common.c index 3d537be4d02..09667d46d99 100644 --- a/board/renesas/common/rcar64-common.c +++ b/board/renesas/common/rcar64-common.c @@ -49,15 +49,15 @@ int dram_init_banksize(void) return 0; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (gd->bd->bi_dram[bank].start != 0x48000000) + if (gd->dram[bank].start != 0x48000000) continue; /* * If this U-Boot runs in EL3, make the bottom 128 MiB * available for loading of follow up firmware blobs. */ - gd->bd->bi_dram[bank].start -= 0x8000000; - gd->bd->bi_dram[bank].size += 0x8000000; + gd->dram[bank].start -= 0x8000000; + gd->dram[bank].size += 0x8000000; break; } diff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c index 8153aed15e3..9245bf348f8 100644 --- a/board/renesas/genmai/genmai.c +++ b/board/renesas/genmai/genmai.c @@ -43,7 +43,7 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c index a229542ba7e..1503de675d5 100644 --- a/board/renesas/sparrowhawk/sparrowhawk.c +++ b/board/renesas/sparrowhawk/sparrowhawk.c @@ -261,10 +261,10 @@ void renesas_dram_init_banksize(void) /* 16 GiB device, adjust memory map. */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (gd->bd->bi_dram[bank].start == 0x480000000ULL) - gd->bd->bi_dram[bank].size = 0x180000000ULL; - else if (gd->bd->bi_dram[bank].start == 0x600000000ULL) - gd->bd->bi_dram[bank].size = 0x200000000ULL; + if (gd->dram[bank].start == 0x480000000ULL) + gd->dram[bank].size = 0x180000000ULL; + else if (gd->dram[bank].start == 0x600000000ULL) + gd->dram[bank].size = 0x200000000ULL; } } diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 1f78654b685..7a0a93c1afe 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -103,8 +103,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index cc58e0f3a38..0ff49dceb9e 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -97,8 +97,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 5d5edd9f253..b5664296a81 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -150,8 +150,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index e70b4a82687..130136e8596 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -67,8 +67,8 @@ int dram_init_banksize(void) addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; + gd->dram[i].start = addr; + gd->dram[i].size = size; } return 0; diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index eed1c2450fa..da3510023c4 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -115,7 +115,7 @@ int board_init(void) ulong size = CONFIG_SYS_MEM_TOP_HIDE; gd->ram_size -= size; - gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; + gd->dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; #endif exynos_init(); @@ -143,8 +143,8 @@ int dram_init_banksize(void) addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; + gd->dram[i].start = addr; + gd->dram[i].size = size; } return 0; diff --git a/board/samsung/exynos-mobile/exynos-mobile.c b/board/samsung/exynos-mobile/exynos-mobile.c index 6b2b1523663..d91e2e7d3f2 100644 --- a/board/samsung/exynos-mobile/exynos-mobile.c +++ b/board/samsung/exynos-mobile/exynos-mobile.c @@ -346,8 +346,8 @@ int dram_init_banksize(void) unsigned int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = mem_map[i + 1].phys; - gd->bd->bi_dram[i].size = mem_map[i + 1].size; + gd->dram[i].start = mem_map[i + 1].phys; + gd->dram[i].size = mem_map[i + 1].size; } return 0; diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index a1047f3fd2a..96a411233d1 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -43,12 +43,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = PHYS_SDRAM_2_SIZE; + gd->dram[2].start = PHYS_SDRAM_3; + gd->dram[2].size = PHYS_SDRAM_3_SIZE; return 0; } diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 7d0b0fcb0ae..7e992c23a1b 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -56,8 +56,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 5a4874b29cd..f013893b465 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -57,17 +57,17 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, + gd->dram[2].start = PHYS_SDRAM_3; + gd->dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE); - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, + gd->dram[3].start = PHYS_SDRAM_4; + gd->dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); return 0; diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index 79cf34b40eb..69d3b9d61d3 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -397,20 +397,20 @@ int dram_init_banksize(void) if (gd->ram_size > SZ_2G) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = SZ_2G; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = SZ_2G; /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = CFG_SYS_SDRAM_BASE1; + gd->dram[1].size = gd->ram_size - SZ_2G; } else { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[1].start = 0; + gd->dram[1].size = 0; } return 0; diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index 556a9ed527e..a7bd08f69ad 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -170,11 +170,11 @@ int dram_init_banksize(void) struct draminfo_entry *ent = synquacer_draminfo->entry; int i; - for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { + for (i = 0; i < ARRAY_SIZE(gd->dram); i++) { if (i < synquacer_draminfo->nr_regions) { debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); - gd->bd->bi_dram[i].start = ent[i].base; - gd->bd->bi_dram[i].size = ent[i].size; + gd->dram[i].start = ent[i].base; + gd->dram[i].size = ent[i].size; } } diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index f5174720434..a1b0265d5ac 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -18,8 +18,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/ste/stemmy/stemmy.c b/board/ste/stemmy/stemmy.c index 826c002907d..66330184af8 100644 --- a/board/ste/stemmy/stemmy.c +++ b/board/ste/stemmy/stemmy.c @@ -70,8 +70,8 @@ int dram_init_banksize(void) if (t->hdr.tag != ATAG_MEM) continue; - gd->bd->bi_dram[bank].start = t->u.mem.start; - gd->bd->bi_dram[bank].size = t->u.mem.size; + gd->dram[bank].start = t->u.mem.start; + gd->dram[bank].size = t->u.mem.size; if (++bank == CONFIG_NR_DRAM_BANKS) break; } diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 0966db2bb62..6f1fed43e36 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -643,11 +643,11 @@ int dram_init_banksize(void) ram_size = board_ti_get_emif_size(); - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = get_effective_memsize(); if (ram_size > CFG_MAX_MEM_MAPPED) { - gd->bd->bi_dram[1].start = 0x200000000; - gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; + gd->dram[1].start = 0x200000000; + gd->dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; } return 0; diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index a92aa5cfc67..43330993955 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -117,8 +117,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) } nbanks = 1; - start[0] = bd->bi_dram[0].start; - size[0] = bd->bi_dram[0].size; + start[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; /* adjust memory start address for LPAE */ if (lpae) { diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 69a8a18d3a7..c63812bd966 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -288,13 +288,13 @@ int ft_board_setup(void *blob, struct bd_info *bd) * Reserve 1MB of memory for M4 (1MiB is also the minimum * alignment for Linux due to MMU section size restrictions). */ - start[0] = gd->bd->bi_dram[0].start; + start[0] = gd->dram[0].start; size[0] = SZ_256M - SZ_1M; /* If needed, create a second entry for memory beyond 256M */ - if (gd->bd->bi_dram[0].size > SZ_256M) { - start[1] = gd->bd->bi_dram[0].start + SZ_256M; - size[1] = gd->bd->bi_dram[0].size - SZ_256M; + if (gd->dram[0].size > SZ_256M) { + start[1] = gd->dram[0].start + SZ_256M; + size[1] = gd->dram[0].size - SZ_256M; areas = 2; } diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 19ac2ae9313..26af1af2069 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -44,7 +44,7 @@ int dram_init_banksize(void) printf("Error setting up memory banksize. %d\n", ret); /* Use the detected RAM size, we only support 1 bank right now. */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return ret; } diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c index 1234b3887c6..ec7775e06a7 100644 --- a/board/toradex/verdin-am62p/verdin-am62p.c +++ b/board/toradex/verdin-am62p/verdin-am62p.c @@ -78,7 +78,7 @@ int dram_init_banksize(void) printf("Error setting up memory banksize. %d\n", ret); /* Use the detected RAM size, we only support 1 bank right now. */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return ret; } diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c index ac8c9a9a81a..5c45f9932c5 100644 --- a/board/traverse/ten64/ten64.c +++ b/board/traverse/ten64/ten64.c @@ -148,7 +148,7 @@ int fsl_initdram(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -277,8 +277,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; /* reduce size if reserved memory is within this bank */ if (IS_ENABLED(CONFIG_RESV_RAM) && RESV_MEM_IN_BANK(i)) size[i] = gd->arch.resv_ram - base[i]; diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c index 05ecb75406b..d8eff203a56 100644 --- a/board/xilinx/zynq/cmds.c +++ b/board/xilinx/zynq/cmds.c @@ -347,10 +347,10 @@ static int zynq_verify_image(u32 src_ptr) * This validation is just for PS DDR. * TODO: Update this for PL DDR check as well. */ - if (part_load_addr < gd->bd->bi_dram[0].start && + if (part_load_addr < gd->dram[0].start && ((part_load_addr + part_data_len) > - (gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size))) { + (gd->dram[0].start + + gd->dram[0].size))) { printf("INVALID_LOAD_ADDRESS_FAIL\n"); return -1; } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index eb41f84c198..a12c039d8c9 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -279,8 +279,8 @@ int dram_init(void) #else int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = get_effective_memsize(); mem_map_fill(); diff --git a/boot/image-board.c b/boot/image-board.c index 265f29d44ff..67938fdd200 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -118,7 +118,7 @@ phys_addr_t env_get_bootm_low(void) #if defined(CFG_SYS_SDRAM_BASE) return CFG_SYS_SDRAM_BASE; #elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV) - return gd->bd->bi_dram[0].start; + return gd->dram[0].start; #else return 0; #endif diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 1150131a11e..9e0e0f93edd 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -260,8 +260,8 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) of_start = NULL; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* DRAM bank addresses are too low, skip it. */ if (start + size < low) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index ddf77303735..bf1eca75904 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -77,15 +77,15 @@ void bdinfo_print_mhz(const char *name, unsigned long hz) printf("%-12s= %6s MHz\n", name, strmhz(buf, hz)); } -static void print_bi_dram(const struct bd_info *bd) +static void print_dram(const struct bd_info *bd) { int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { + if (gd->dram[i].size) { bdinfo_print_num_l("DRAM bank", i); - bdinfo_print_num_ll("-> start", bd->bi_dram[i].start); - bdinfo_print_num_ll("-> size", bd->bi_dram[i].size); + bdinfo_print_num_ll("-> start", gd->dram[i].start); + bdinfo_print_num_ll("-> size", gd->dram[i].size); } } } @@ -144,7 +144,7 @@ static int bdinfo_print_all(struct bd_info *bd) bdinfo_print_num_l("bd address", (ulong)bd); #endif bdinfo_print_num_l("boot_params", (ulong)bd->bi_boot_params); - print_bi_dram(bd); + print_dram(bd); bdinfo_print_num_l("flashstart", (ulong)bd->bi_flashstart); bdinfo_print_num_l("flashsize", (ulong)bd->bi_flashsize); bdinfo_print_num_l("flashoffset", (ulong)bd->bi_flashoffset); @@ -199,7 +199,7 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) print_eth(); return CMD_RET_SUCCESS; case 'm': - print_bi_dram(bd); + print_dram(bd); return CMD_RET_SUCCESS; default: return CMD_RET_USAGE; diff --git a/cmd/ti/ddr4.c b/cmd/ti/ddr4.c index a8d71d11a91..36277cc154c 100644 --- a/cmd/ti/ddr4.c +++ b/cmd/ti/ddr4.c @@ -227,10 +227,10 @@ static int do_ddr4_ecc_inject(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - if (!((start_addr >= gd->bd->bi_dram[0].start && - (start_addr <= (gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - 1))) || - (start_addr >= gd->bd->bi_dram[1].start && - (start_addr <= (gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size - 1))))) { + if (!((start_addr >= gd->dram[0].start && + (start_addr <= (gd->dram[0].start + gd->dram[0].size - 1))) || + (start_addr >= gd->dram[1].start && + (start_addr <= (gd->dram[1].start + gd->dram[1].size - 1))))) { puts("Address is not in the DDR range\n"); return CMD_RET_FAILURE; } diff --git a/cmd/ufetch.c b/cmd/ufetch.c index e7b5d773f5e..763ab42c48a 100644 --- a/cmd/ufetch.c +++ b/cmd/ufetch.c @@ -202,8 +202,8 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc, printf("CPU: " RESET CONFIG_SYS_ARCH " (%d cores, 1 in use)\n", n_cpus); break; case MEMORY: - for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->bd->bi_dram[j].size; j++) - size += gd->bd->bi_dram[j].size; + for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->dram[j].size; j++) + size += gd->dram[j].size; printf("Memory:" RESET " "); print_size(size, "\n"); break; diff --git a/common/board_f.c b/common/board_f.c index fdb3577fec0..a3abec35271 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -222,11 +222,11 @@ static int show_dram_config(void) debug("\nRAM Configuration:\n"); for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; debug("Bank #%d: %llx ", i, - (unsigned long long)(gd->bd->bi_dram[i].start)); + (unsigned long long)(gd->dram[i].start)); #ifdef DEBUG - print_size(gd->bd->bi_dram[i].size, "\n"); + print_size(gd->dram[i].size, "\n"); #endif } debug("\nDRAM: "); @@ -244,8 +244,8 @@ static int show_dram_config(void) __weak int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); return 0; } diff --git a/common/init/handoff.c b/common/init/handoff.c index a7cd065fb38..a4d9d14393b 100644 --- a/common/init/handoff.c +++ b/common/init/handoff.c @@ -12,14 +12,13 @@ DECLARE_GLOBAL_DATA_PTR; void handoff_save_dram(struct spl_handoff *ho) { - struct bd_info *bd = gd->bd; int i; ho->ram_size = gd->ram_size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - ho->ram_bank[i].start = bd->bi_dram[i].start; - ho->ram_bank[i].size = bd->bi_dram[i].size; + ho->ram_bank[i].start = gd->dram[i].start; + ho->ram_bank[i].size = gd->dram[i].size; } } @@ -30,11 +29,10 @@ void handoff_load_dram_size(struct spl_handoff *ho) void handoff_load_dram_banks(struct spl_handoff *ho) { - struct bd_info *bd = gd->bd; int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - bd->bi_dram[i].start = ho->ram_bank[i].start; - bd->bi_dram[i].size = ho->ram_bank[i].size; + gd->dram[i].start = ho->ram_bank[i].start; + gd->dram[i].size = ho->ram_bank[i].size; } } diff --git a/drivers/bootcount/bootcount_ram.c b/drivers/bootcount/bootcount_ram.c index 33e157b865a..f726d9ab016 100644 --- a/drivers/bootcount/bootcount_ram.c +++ b/drivers/bootcount/bootcount_ram.c @@ -27,7 +27,7 @@ void bootcount_store(ulong a) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; save_addr = (ulong *)(size - BOOTCOUNT_ADDR); writel(a, save_addr); writel(CONFIG_SYS_BOOTCOUNT_MAGIC, &save_addr[1]); @@ -50,7 +50,7 @@ ulong bootcount_load(void) int i, tmp; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; save_addr = (ulong *)(size - BOOTCOUNT_ADDR); counter = readl(&save_addr[0]); diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index b36a765a5de..2d2b72cf766 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -104,7 +104,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); return -ENXIO; @@ -158,7 +158,7 @@ int sdram_mmr_init_full(struct udevice *dev) sdram_set_firewall(&bd); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; debug("DDR: HMC init success\n"); diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c index ee66c72157a..d14e4bc5dcc 100644 --- a/drivers/ddr/altera/sdram_agilex5.c +++ b/drivers/ddr/altera/sdram_agilex5.c @@ -302,7 +302,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, gd->bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); ret = -ENXIO; @@ -345,19 +345,19 @@ int sdram_mmr_init_full(struct udevice *dev) for (i = 0; i < config_dram_banks; i++) { remaining_size = hw_size - size_counter; if (remaining_size <= dram_bank_info[i].max_size) { - gd->bd->bi_dram[i].start = dram_bank_info[i].start; - gd->bd->bi_dram[i].size = remaining_size; + gd->dram[i].start = dram_bank_info[i].start; + gd->dram[i].size = remaining_size; debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n", - i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); + i, gd->dram[i].start, gd->dram[i].size); break; } - gd->bd->bi_dram[i].start = dram_bank_info[i].start; - gd->bd->bi_dram[i].size = dram_bank_info[i].max_size; + gd->dram[i].start = dram_bank_info[i].start; + gd->dram[i].size = dram_bank_info[i].max_size; debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n", - i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); - size_counter += gd->bd->bi_dram[i].size; + i, gd->dram[i].start, gd->dram[i].size); + size_counter += gd->dram[i].size; } gd->ram_size = hw_size; @@ -408,7 +408,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR: firewall init success\n"); - priv->info.base = gd->bd->bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; /* Ending DDR driver initialization success tracking */ diff --git a/drivers/ddr/altera/sdram_agilex7m.c b/drivers/ddr/altera/sdram_agilex7m.c index 9b3cc5c7b86..e4d522202d8 100644 --- a/drivers/ddr/altera/sdram_agilex7m.c +++ b/drivers/ddr/altera/sdram_agilex7m.c @@ -375,7 +375,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { printf("%s: Failed to decode memory node\n", memory_type_in_use(dev)); @@ -484,7 +484,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("%s: firewall init success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; /* Ending DDR driver initialization success tracking */ diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index c281f711fdf..9cc809b8001 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -674,9 +674,9 @@ static void sdram_size_check(void) debug("DDR: Running SDRAM size sanity check\n"); - ram_check = get_ram_size((long *)gd->bd->bi_dram[0].start, - gd->bd->bi_dram[0].size); - if (ram_check != gd->bd->bi_dram[0].size) { + ram_check = get_ram_size((long *)gd->dram[0].start, + gd->dram[0].size); + if (ram_check != gd->dram[0].size) { puts("DDR: SDRAM size check failed!\n"); hang(); } @@ -719,14 +719,14 @@ int ddr_calibration_sequence(void) /* setup the dram info within bd */ dram_init_banksize(); - if (gd->ram_size != gd->bd->bi_dram[0].size) { + if (gd->ram_size != gd->dram[0].size) { printf("DDR: Warning: DRAM size from device tree (%ld MiB)\n", - gd->bd->bi_dram[0].size >> 20); + gd->dram[0].size >> 20); printf(" mismatch with hardware (%ld MiB).\n", gd->ram_size >> 20); } - if (gd->bd->bi_dram[0].size > gd->ram_size) { + if (gd->dram[0].size > gd->ram_size) { printf("DDR: Error: DRAM size from device tree is greater\n"); printf(" than hardware size.\n"); hang(); diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 17ec6afa82b..900d4f59989 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -2279,7 +2279,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { debug("%s: Failed to decode memory node\n", __func__); return -1; @@ -2287,7 +2287,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR: %lld MiB\n", gd->ram_size >> 20); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; sdram_size_check(&bd); diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 4ac4c79e0ac..6664090f86a 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -285,7 +285,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); return -1; @@ -328,7 +328,7 @@ int sdram_mmr_init_full(struct udevice *dev) sdram_size_check(&bd); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; debug("DDR: HMC init success\n"); diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 8ee7049b164..93df3d1812a 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -150,8 +150,8 @@ void sdram_init_ecc_bits(struct bd_info *bd) icache_enable(); - start_addr = bd->bi_dram[0].start; - size = bd->bi_dram[0].size; + start_addr = gd->dram[0].start; + size = gd->dram[0].size; /* Initialize small block for page table */ memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF); @@ -174,8 +174,8 @@ void sdram_init_ecc_bits(struct bd_info *bd) if (bank >= CONFIG_NR_DRAM_BANKS) break; - start_addr = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; + start_addr = gd->dram[bank].start; + size = gd->dram[bank].size; } dcache_disable(); @@ -198,12 +198,12 @@ void sdram_size_check(struct bd_info *bd) phys_addr_t start = 0; phys_size_t remaining_size; - start = bd->bi_dram[bank].start; - remaining_size = bd->bi_dram[bank].size; + start = gd->dram[bank].start; + remaining_size = gd->dram[bank].size; debug("Checking bank %d: start=0x%llx, size=0x%llx\n", bank, start, remaining_size); - while (ram_check < bd->bi_dram[bank].size) { + while (ram_check < gd->dram[bank].size) { phys_size_t size, test_size, detected_size; size = min((phys_addr_t)SZ_1G, (phys_addr_t)remaining_size); @@ -232,7 +232,7 @@ void sdram_size_check(struct bd_info *bd) } ram_check += detected_size; - remaining_size = bd->bi_dram[bank].size - ram_check; + remaining_size = gd->dram[bank].size - ram_check; } total_ram_check += ram_check; @@ -292,10 +292,10 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) u32 lower, upper; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (!bd->bi_dram[i].size) + if (!gd->dram[i].size) continue; - value = bd->bi_dram[i].start; + value = gd->dram[i].start; /* Keep first 1MB of SDRAM memory region as secure region when * using ATF flow, where the ATF code is located. @@ -322,7 +322,7 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) (i * 4 * sizeof(u32))); /* Setting non-secure MPU limit and limit extended */ - value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + value = gd->dram[i].start + gd->dram[i].size - 1; lower = lower_32_bits(value); upper = upper_32_bits(value); @@ -354,10 +354,10 @@ static void sdram_set_firewall_f2sdram(struct bd_info *bd) phys_size_t value; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (!bd->bi_dram[i].size) + if (!gd->dram[i].size) continue; - value = bd->bi_dram[i].start; + value = gd->dram[i].start; /* Keep first 1MB of SDRAM memory region as secure region when * using ATF flow, where the ATF code is located. @@ -376,7 +376,7 @@ static void sdram_set_firewall_f2sdram(struct bd_info *bd) (i * 4 * sizeof(u32))); /* Setting limit and limit extended */ - value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + value = gd->dram[i].start + gd->dram[i].size - 1; lower = lower_32_bits(value); upper = upper_32_bits(value); diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c index 5af1953cd14..89d511c1a6f 100644 --- a/drivers/mmc/mvebu_mmc.c +++ b/drivers/mmc/mvebu_mmc.c @@ -375,8 +375,8 @@ static void mvebu_window_setup(const struct mmc *mmc) break; } - size = gd->bd->bi_dram[i].size; - base = gd->bd->bi_dram[i].start; + size = gd->dram[i].size; + base = gd->dram[i].start; if (size && attrib) { mvebu_mmc_write(mmc, WINDOW_CTRL(i), MVCPU_WIN_CTRL_DATA(size, diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 107a33aa9f5..4dc738980cb 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -256,8 +256,8 @@ static void set_dram_access(struct mvgbe_registers *regs) win_param.access_ctrl = EWIN_ACCESS_FULL; win_param.high_addr = 0; /* Get bank base and size */ - win_param.base_addr = gd->bd->bi_dram[i].start; - win_param.size = gd->bd->bi_dram[i].size; + win_param.base_addr = gd->dram[i].start; + win_param.size = gd->dram[i].size; if (win_param.size == 0) win_param.enable = 0; else diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index f58d542ef75..4bdd1f7477f 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1126,14 +1126,14 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, return 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - phys_addr_t start = bd->bi_dram[i].start; + if (gd->dram[i].size) { + phys_addr_t start = gd->dram[i].start; if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY)) - start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start); + start = virt_to_phys((void *)(uintptr_t)gd->dram[i].start); pci_set_region(hose->regions + hose->region_count++, - start, start, bd->bi_dram[i].size, + start, start, gd->dram[i].size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); } } diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 794a4168913..38ee17f063d 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -222,8 +222,8 @@ static void usb_brg_adrdec_setup(int index) break; } - size = gd->bd->bi_dram[i].size; - base = gd->bd->bi_dram[i].start; + size = gd->dram[i].size; + base = gd->dram[i].start; if ((size) && (attrib)) writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM, attrib, MVCPU_WIN_ENABLE), diff --git a/drivers/video/meson/meson_vpu.c b/drivers/video/meson/meson_vpu.c index ca627728743..a686faf9f58 100644 --- a/drivers/video/meson/meson_vpu.c +++ b/drivers/video/meson/meson_vpu.c @@ -81,8 +81,8 @@ cvbs: meson_fb.fb_size = ALIGN(meson_fb.xsize * meson_fb.ysize * ((1 << VPU_MAX_LOG2_BPP) / 8) + MESON_VPU_OVERSCAN, EFI_PAGE_SIZE); - meson_fb.base = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - meson_fb.fb_size; + meson_fb.base = gd->dram[0].start + + gd->dram[0].size - meson_fb.fb_size; /* Override the framebuffer address */ uc_plat->base = meson_fb.base; @@ -175,8 +175,8 @@ static void meson_vpu_setup_simplefb(void *fdt) * at the end of the RAM and we strip this portion from the kernel * allowed region */ - mem_start = gd->bd->bi_dram[0].start; - mem_size = gd->bd->bi_dram[0].size - meson_fb.fb_size; + mem_start = gd->dram[0].start; + mem_size = gd->dram[0].size - meson_fb.fb_size; ret = fdt_fixup_memory_banks(fdt, &mem_start, &mem_size, 1); if (ret) { eprintf("Cannot setup simplefb: Error reserving memory\n"); diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 154641b9a69..ab36ee1595b 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -368,7 +368,7 @@ int sunxi_simplefb_setup(void *blob) return 0; /* Keep older kernels working */ } - start = gd->bd->bi_dram[0].start; + start = gd->dram[0].start; size = de2_plat->base - start; ret = fdt_fixup_memory_banks(blob, &start, &size, 1); if (ret) { diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 4a6a89ef9d2..fa492c661db 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -1336,7 +1336,7 @@ int sunxi_simplefb_setup(void *blob) * and e.g. Linux refuses to iomap RAM on ARM, see: * linux/arch/arm/mm/ioremap.c around line 301. */ - start = gd->bd->bi_dram[0].start; + start = gd->dram[0].start; size = sunxi_display->fb_addr - start; ret = fdt_fixup_memory_banks(blob, &start, &size, 1); if (ret) { diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index ba6a10cf2ad..ad7ebb1bbc9 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -457,6 +457,13 @@ struct global_data { */ struct upl *upl; #endif + /** + * @dram: array describing DRAM banks (start address and size for each bank) + */ + struct { /* RAM configuration */ + phys_addr_t start; + phys_size_t size; + } dram[CONFIG_NR_DRAM_BANKS]; }; #ifndef DO_DEPS_ONLY static_assert(sizeof(struct global_data) == GD_SIZE); diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 8c619c1b74a..931fe2f3274 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -59,10 +59,6 @@ struct bd_info { #endif ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ - struct { /* RAM configuration */ - phys_addr_t start; - phys_size_t size; - } bi_dram[CONFIG_NR_DRAM_BANKS]; }; #endif /* __ASSEMBLY__ */ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index a6aafb51854..36e330887cd 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -15,9 +15,9 @@ * Memory configurations */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 2bd1426c7d9..e823611d2e4 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -51,9 +51,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 14095b99f03..acd6eb6f8ac 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -86,9 +86,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 3707de254e1..65babf50546 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -81,9 +81,9 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_1_SIZE (gd->dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_2_SIZE (gd->dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) diff --git a/include/fdtdec.h b/include/fdtdec.h index 46eaa0da63c..51d9f14a9f2 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -57,6 +57,7 @@ struct fdt_memory { }; struct bd_info; +struct global_data; /** * enum fdt_source_t - indicates where the devicetree came from @@ -974,7 +975,7 @@ int fdtdec_setup_mem_size_base(void); int fdtdec_setup_mem_size_base_lowest(void); /** - * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram + * fdtdec_setup_memory_banksize() - decode and populate gd->dram * * Decode the /memory 'reg' property to determine the address and size of the * memory banks. Use this data to populate the global data board info with the @@ -1256,12 +1257,12 @@ int board_fdt_blob_setup(void **fdtp); * @param basep Returns base address of first memory bank (NULL to * ignore) * @param sizep Returns total memory size (NULL to ignore) - * @param bd Updated with the memory bank information (NULL to skip) + * @param gd_ptr Updated with the memory bank information (NULL to skip) * Return: 0 if OK, -ve on error */ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, phys_addr_t *basep, phys_size_t *sizep, - struct bd_info *bd); + struct global_data *gd_ptr); /** * fdtdec_get_srcname() - Get the name of where the devicetree comes from diff --git a/include/init.h b/include/init.h index c31ebd83b85..23466d3f153 100644 --- a/include/init.h +++ b/include/init.h @@ -80,7 +80,7 @@ int dram_init(void); * dram_init_banksize() - Set up DRAM bank sizes * * This can be implemented by boards to set up the DRAM bank information in - * gd->bd->bi_dram(). It is called just before relocation, after dram_init() + * gd->dram[] It is called just before relocation, after dram_init() * is called. * * If this is not provided, a default implementation will try to set up a diff --git a/lib/fdtdec.c b/lib/fdtdec.c index d0a84b5034b..b91e067106d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -35,6 +35,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -1142,14 +1143,14 @@ int fdtdec_setup_memory_banksize(void) if (ret != 0) return -EINVAL; - gd->bd->bi_dram[bank].start = (phys_addr_t)res.start; - gd->bd->bi_dram[bank].size = + gd->dram[bank].start = (phys_addr_t)res.start; + gd->dram[bank].size = (phys_size_t)(res.end - res.start + 1); debug("%s: DRAM Bank #%d: start = %pap, size = %pap\n", __func__, bank, - &gd->bd->bi_dram[bank].start, - &gd->bd->bi_dram[bank].size); + &gd->dram[bank].start, + &gd->dram[bank].size); } return 0; @@ -1930,7 +1931,7 @@ int fdtdec_resetup(int *rescan) int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, phys_addr_t *basep, phys_size_t *sizep, - struct bd_info *bd) + gd_t *gd_ptr) { int addr_cells, size_cells; const u32 *cell, *end; @@ -1982,8 +1983,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, } /* Note: if no matching subnode was found we use the parent node */ - if (bd) { - memset(bd->bi_dram, '\0', sizeof(bd->bi_dram[0]) * + if (gd_ptr) { + memset(gd_ptr->dram, '\0', sizeof(gd_ptr->dram[0]) * CONFIG_NR_DRAM_BANKS); } @@ -1999,8 +2000,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, if (addr_cells == 2) addr += (u64)fdt32_to_cpu(*cell++) << 32UL; addr += fdt32_to_cpu(*cell++); - if (bd) - bd->bi_dram[bank].start = addr; + if (gd_ptr) + gd_ptr->dram[bank].start = addr; if (basep && !bank) *basep = (phys_addr_t)addr; @@ -2022,8 +2023,8 @@ int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, } } - if (bd) - bd->bi_dram[bank].size = size; + if (gd_ptr) + gd_ptr->dram[bank].size = size; total_size += size; } diff --git a/lib/lmb.c b/lib/lmb.c index 779df35eb9c..77440a48486 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -555,12 +555,12 @@ static void lmb_reserve_uboot_region(void) #endif for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (!gd->bd->bi_dram[bank].size || - rsv_start < gd->bd->bi_dram[bank].start) + if (!gd->dram[bank].size || + rsv_start < gd->dram[bank].start) continue; /* Watch out for RAM at end of address space! */ - bank_end = gd->bd->bi_dram[bank].start + - gd->bd->bi_dram[bank].size - 1; + bank_end = gd->dram[bank].start + + gd->dram[bank].size - 1; if (rsv_start > bank_end) continue; if (bank_end > end) @@ -615,7 +615,6 @@ static void lmb_add_memory(void) phys_addr_t bank_end; phys_size_t size; u64 ram_top = gd->ram_top; - struct bd_info *bd = gd->bd; if (CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP)) return lmb_arch_add_memory(); @@ -625,22 +624,22 @@ static void lmb_add_memory(void) ram_top = 0x100000000ULL; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - size = bd->bi_dram[i].size; + size = gd->dram[i].size; if (size) { - lmb_add(bd->bi_dram[i].start, size); + lmb_add(gd->dram[i].start, size); if (!IS_ENABLED(CONFIG_LMB_LIMIT_DMA_BELOW_RAM_TOP)) continue; - bank_end = bd->bi_dram[i].start + size; + bank_end = gd->dram[i].start + size; /* * Reserve memory above ram_top as * no-overwrite so that it cannot be * allocated */ - if (bd->bi_dram[i].start >= ram_top) - lmb_reserve(bd->bi_dram[i].start, size, + if (gd->dram[i].start >= ram_top) + lmb_reserve(gd->dram[i].start, size, LMB_NOOVERWRITE); else if (bank_end > ram_top) lmb_reserve(ram_top, bank_end - ram_top, diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c index 7f4f1868c6a..7b7fb0894dd 100644 --- a/test/cmd/bdinfo.c +++ b/test/cmd/bdinfo.c @@ -138,16 +138,15 @@ static int lmb_test_dump_all(struct unit_test_state *uts) static int bdinfo_check_mem(struct unit_test_state *uts) { - struct bd_info *bd = gd->bd; int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { + if (gd->dram[i].size) { ut_assertok(test_num_l(uts, "DRAM bank", i)); ut_assertok(test_num_ll(uts, "-> start", - bd->bi_dram[i].start)); + gd->dram[i].start)); ut_assertok(test_num_ll(uts, "-> size", - bd->bi_dram[i].size)); + gd->dram[i].size)); } } -- cgit v1.3.1